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FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/runme.log

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  1. 

  2. *** Running vivado

  3.     with args -log fixedPointTest.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fixedPointTest.tcl

  4. 

  5. 

  6. 

  7. ****** Vivado v2021.2 (64-bit)

  8.   **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  9.   **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  10.     ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  11. 

  12. source fixedPointTest.tcl -notrace

  13. create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.980 ; gain = 10.180

  14. Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp

  15. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/utils_1/imports/synth_1/fixedPointTest.dcp for incremental synthesis

  16. INFO: [Vivado 12-7989] Please ensure there are no constraint changes

  17. Command: synth_design -top fixedPointTest -part xc7z010clg400-1

  18. Starting synth_design

  19. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'

  20. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'

  21. INFO: [Device 21-403] Loading part xc7z010clg400-1

  22. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  23. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  24. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.

  25. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

  26. INFO: [Synth 8-7075] Helper process launched with PID 9900

  27. ---------------------------------------------------------------------------------

  28. Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.980 ; gain = 0.000

  29. ---------------------------------------------------------------------------------

  30. INFO: [Synth 8-638] synthesizing module 'fixedPointTest' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]

  31. INFO: [Synth 8-256] done synthesizing module 'fixedPointTest' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/sources_1/new/fixedPointTest.vhd:44]

  32. ---------------------------------------------------------------------------------

  33. Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.980 ; gain = 0.000

  34. ---------------------------------------------------------------------------------

  35. ---------------------------------------------------------------------------------

  36. Start Handling Custom Attributes

  37. ---------------------------------------------------------------------------------

  38. ---------------------------------------------------------------------------------

  39. Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.980 ; gain = 0.000

  40. ---------------------------------------------------------------------------------

  41. ---------------------------------------------------------------------------------

  42. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1261.980 ; gain = 0.000

  43. ---------------------------------------------------------------------------------

  44. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.980 ; gain = 0.000

  45. INFO: [Project 1-570] Preparing netlist for logic optimization

  46. 

  47. Processing XDC Constraints

  48. Initializing timing engine

  49. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  50. WARNING: [Vivado 12-584] No ports matched 'clk'. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]

  51. CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc:7]

  52. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

  53. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  54. Completed Processing XDC Constraints

  55. 

  56. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1261.980 ; gain = 0.000

  57. INFO: [Project 1-111] Unisim Transformation Summary:

  58. No Unisim elements were transformed.

  59. 

  60. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1261.980 ; gain = 0.000

  61. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  62. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  63. ---------------------------------------------------------------------------------

  64. Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  65. ---------------------------------------------------------------------------------

  66. ---------------------------------------------------------------------------------

  67. Start Loading Part and Timing Information

  68. ---------------------------------------------------------------------------------

  69. Loading part: xc7z010clg400-1

  70. ---------------------------------------------------------------------------------

  71. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  72. ---------------------------------------------------------------------------------

  73. ---------------------------------------------------------------------------------

  74. Start Applying 'set_property' XDC Constraints

  75. ---------------------------------------------------------------------------------

  76. ---------------------------------------------------------------------------------

  77. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  78. ---------------------------------------------------------------------------------

  79. ---------------------------------------------------------------------------------

  80. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1261.980 ; gain = 0.000

  81. ---------------------------------------------------------------------------------

  82. ---------------------------------------------------------------------------------

  83. Start RTL Component Statistics 

  84. ---------------------------------------------------------------------------------

  85. Detailed RTL Component Info : 

  86. ---------------------------------------------------------------------------------

  87. Finished RTL Component Statistics 

  88. ---------------------------------------------------------------------------------

  89. ---------------------------------------------------------------------------------

  90. Start Part Resource Summary

  91. ---------------------------------------------------------------------------------

  92. Part Resources:

  93. DSPs: 80 (col length:40)

  94. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)

  95. ---------------------------------------------------------------------------------

  96. Finished Part Resource Summary

  97. ---------------------------------------------------------------------------------

  98. ---------------------------------------------------------------------------------

  99. Start Cross Boundary and Area Optimization

  100. ---------------------------------------------------------------------------------

  101. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met

  102. DSP Report: Generating DSP arg, operation Mode is: A*B.

  103. DSP Report: operator arg is absorbed into DSP arg.

  104. ---------------------------------------------------------------------------------

  105. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:21 . Memory (MB): peak = 1261.980 ; gain = 0.000

  106. ---------------------------------------------------------------------------------

  107. ---------------------------------------------------------------------------------

  108. Start ROM, RAM, DSP, Shift Register and Retiming Reporting

  109. ---------------------------------------------------------------------------------

  110. 

  111. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)

  112. +---------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  113. |Module Name    | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 

  114. +---------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  115. |fixedPointTest | A*B         | 14     | 14     | -      | -      | 28     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  116. +---------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  117. 

  118. Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.

  119. ---------------------------------------------------------------------------------

  120. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting

  121. ---------------------------------------------------------------------------------

  122. ---------------------------------------------------------------------------------

  123. Start Applying XDC Timing Constraints

  124. ---------------------------------------------------------------------------------

  125. ---------------------------------------------------------------------------------

  126. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1277.898 ; gain = 15.918

  127. ---------------------------------------------------------------------------------

  128. ---------------------------------------------------------------------------------

  129. Start Timing Optimization

  130. ---------------------------------------------------------------------------------

  131. ---------------------------------------------------------------------------------

  132. Finished Timing Optimization : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 1277.898 ; gain = 15.918

  133. ---------------------------------------------------------------------------------

  134. ---------------------------------------------------------------------------------

  135. Start Technology Mapping

  136. ---------------------------------------------------------------------------------

  137. ---------------------------------------------------------------------------------

  138. Finished Technology Mapping : Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 1297.012 ; gain = 35.031

  139. ---------------------------------------------------------------------------------

  140. ---------------------------------------------------------------------------------

  141. Start IO Insertion

  142. ---------------------------------------------------------------------------------

  143. ---------------------------------------------------------------------------------

  144. Start Flattening Before IO Insertion

  145. ---------------------------------------------------------------------------------

  146. ---------------------------------------------------------------------------------

  147. Finished Flattening Before IO Insertion

  148. ---------------------------------------------------------------------------------

  149. ---------------------------------------------------------------------------------

  150. Start Final Netlist Cleanup

  151. ---------------------------------------------------------------------------------

  152. ---------------------------------------------------------------------------------

  153. Finished Final Netlist Cleanup

  154. ---------------------------------------------------------------------------------

  155. ---------------------------------------------------------------------------------

  156. Finished IO Insertion : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  157. ---------------------------------------------------------------------------------

  158. ---------------------------------------------------------------------------------

  159. Start Renaming Generated Instances

  160. ---------------------------------------------------------------------------------

  161. ---------------------------------------------------------------------------------

  162. Finished Renaming Generated Instances : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  163. ---------------------------------------------------------------------------------

  164. ---------------------------------------------------------------------------------

  165. Start Rebuilding User Hierarchy

  166. ---------------------------------------------------------------------------------

  167. ---------------------------------------------------------------------------------

  168. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  169. ---------------------------------------------------------------------------------

  170. ---------------------------------------------------------------------------------

  171. Start Renaming Generated Ports

  172. ---------------------------------------------------------------------------------

  173. ---------------------------------------------------------------------------------

  174. Finished Renaming Generated Ports : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  175. ---------------------------------------------------------------------------------

  176. ---------------------------------------------------------------------------------

  177. Start Handling Custom Attributes

  178. ---------------------------------------------------------------------------------

  179. ---------------------------------------------------------------------------------

  180. Finished Handling Custom Attributes : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  181. ---------------------------------------------------------------------------------

  182. ---------------------------------------------------------------------------------

  183. Start Renaming Generated Nets

  184. ---------------------------------------------------------------------------------

  185. ---------------------------------------------------------------------------------

  186. Finished Renaming Generated Nets : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  187. ---------------------------------------------------------------------------------

  188. ---------------------------------------------------------------------------------

  189. Start Writing Synthesis Report

  190. ---------------------------------------------------------------------------------

  191. 

  192. Report BlackBoxes: 

  193. +-+--------------+----------+

  194. | |BlackBox name |Instances |

  195. +-+--------------+----------+

  196. +-+--------------+----------+

  197. 

  198. Report Cell Usage: 

  199. +------+--------+------+

  200. |      |Cell    |Count |

  201. +------+--------+------+

  202. |1     |DSP48E1 |     1|

  203. |2     |IBUF    |    28|

  204. |3     |OBUF    |    28|

  205. +------+--------+------+

  206. ---------------------------------------------------------------------------------

  207. Finished Writing Synthesis Report : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1303.738 ; gain = 41.758

  208. ---------------------------------------------------------------------------------

  209. Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.

  210. Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:39 . Memory (MB): peak = 1303.738 ; gain = 41.758

  211. Synthesis Optimization Complete : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 1303.738 ; gain = 41.758

  212. INFO: [Project 1-571] Translating synthesized netlist

  213. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1315.801 ; gain = 0.000

  214. INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement

  215. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  216. INFO: [Project 1-570] Preparing netlist for logic optimization

  217. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  218. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1322.461 ; gain = 0.000

  219. INFO: [Project 1-111] Unisim Transformation Summary:

  220. No Unisim elements were transformed.

  221. 

  222. Synth Design complete, checksum: acd46f8c

  223. INFO: [Common 17-83] Releasing license: Synthesis

  224. 20 Infos, 4 Warnings, 1 Critical Warnings and 0 Errors encountered.

  225. synth_design completed successfully

  226. synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:47 . Memory (MB): peak = 1322.461 ; gain = 60.480

  227. INFO: [runtcl-6] Synthesis results are not added to the cache due to CRITICAL_WARNING

  228. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/synth_1/fixedPointTest.dcp' has been generated.

  229. INFO: [runtcl-4] Executing : report_utilization -file fixedPointTest_utilization_synth.rpt -pb fixedPointTest_utilization_synth.pb

  230. INFO: [Common 17-206] Exiting Vivado at Mon May 16 13:48:36 2022...