vhdl_srcs = ../../../hardware/system/reg32.vhd \ ../../../hardware/system/task.vhd \ ../../../hardware/system/avalon_slave.vhd \ ../../../hardware/system/avalon_slave_transitions.vhd \ ../../../hardware/system/hardware_task_control.vhd \ ../../../hardware/system/float_add.vhd \ ../../../hardware/signal_processing/add.vhd \ ../../../hardware/system/task_add.vhd \ ../../../hardware/system/data_channel_control.vhd \ ../../../hardware/system/data_sink_mux.vhd \ ../../../hardware/system/data_source_mux.vhd \ ../../../hardware/system/fifo.vhd \ ../../../hardware/system/data_channel.vhd \ ../test_utility.vhd \ ../test_avalon_slave.vhd \ ../test_hardware_task.vhd \ ../test_data_channel.vhd \ ../../data/sine_cosine.vhd \ ../../data/rand.vhd \ ../../data/add_rand.vhd \ test_task_add_rand.vhd \ main = test_task_add_rand expected_data = ../../data/add_rand.py include ../data_tests.mk