Studentenversion des ESY6/A Praktikums "signal_processing".
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fifo.vhd 3.2KB

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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4. entity fifo is
  5. generic (
  6. DEPTH : positive := 1024
  7. );
  8. port
  9. (
  10. aclr : in std_logic;
  11. clock : in std_logic;
  12. sclr : in std_logic;
  13. data : in std_logic_vector( 31 downto 0 );
  14. rdreq : in std_logic;
  15. wrreq : in std_logic;
  16. empty : out std_logic;
  17. full : out std_logic;
  18. q : out std_logic_vector( 31 downto 0 );
  19. usedw : out std_logic_vector( 9 downto 0 )
  20. );
  21. end entity fifo;
  22. architecture rtl of fifo is
  23. type Operation is (
  24. OPERATION_IDLE,
  25. OPERATION_CLEAR,
  26. OPERATION_READ,
  27. OPERATION_WRITE,
  28. OPERATION_READ_WRITE
  29. );
  30. signal is_empty : boolean;
  31. signal is_full : boolean;
  32. signal is_read : boolean;
  33. signal is_write : boolean;
  34. signal is_read_write : boolean;
  35. signal next_operation : Operation;
  36. signal fifo_data : work.reg32.RegArray( 0 to DEPTH - 1 );
  37. signal write_index : integer range 0 to DEPTH - 1;
  38. signal read_index : integer range 0 to DEPTH - 1;
  39. signal item_count : integer range 0 to DEPTH;
  40. function increment_with_overflow( value : integer; max : integer ) return integer
  41. is
  42. begin
  43. if ( value < max - 1 ) then
  44. return value + 1;
  45. end if;
  46. return 0;
  47. end function increment_with_overflow;
  48. begin
  49. c_is_empty: is_empty <= item_count = 0;
  50. c_is_full: is_full <= item_count = DEPTH;
  51. c_is_read: is_read <= rdreq = '1' and not is_empty;
  52. c_is_write: is_write <= wrreq = '1' and not is_full;
  53. c_is_read_write: is_read_write <= is_read and is_write;
  54. c_next_operation: next_operation <= OPERATION_CLEAR when sclr
  55. else OPERATION_READ_WRITE when is_read_write
  56. else OPERATION_READ when is_read
  57. else OPERATION_WRITE when is_write
  58. else OPERATION_IDLE;
  59. sync: process( clock, aclr ) is
  60. begin
  61. if ( aclr = '1' ) then
  62. write_index <= 0;
  63. read_index <= 0;
  64. item_count <= 0;
  65. elsif ( rising_edge( clock ) ) then
  66. case next_operation is
  67. when OPERATION_IDLE =>
  68. null;
  69. when OPERATION_CLEAR =>
  70. write_index <= 0;
  71. read_index <= 0;
  72. item_count <= 0;
  73. when OPERATION_READ =>
  74. item_count <= item_count - 1;
  75. read_index <= increment_with_overflow( read_index, DEPTH );
  76. when OPERATION_WRITE =>
  77. fifo_data( write_index ) <= data;
  78. item_count <= item_count + 1;
  79. write_index <= increment_with_overflow( write_index, DEPTH );
  80. when OPERATION_READ_WRITE =>
  81. read_index <= increment_with_overflow( read_index, DEPTH );
  82. fifo_data( write_index ) <= data;
  83. write_index <= increment_with_overflow( write_index, DEPTH );
  84. end case;
  85. end if;
  86. end process;
  87. c_assign_q: q <= data when ( is_empty and is_write ) else
  88. fifo_data( read_index );
  89. c_assign_usedw:
  90. usedw <= std_logic_vector( to_unsigned( item_count, usedw'length ) );
  91. full <= '1' when is_full else '0';
  92. empty <= '1' when is_empty else '0';
  93. end architecture rtl;