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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
-
- library work;
- use work.reg32.all;
- use work.task.all;
-
- entity task_sine is
- port (
- clk : in std_logic;
- reset : in std_logic;
-
- address : in std_logic_vector( 3 downto 0 );
- read : in std_logic;
- readdata : out std_logic_vector( 31 downto 0 );
- write : in std_logic;
- writedata : in std_logic_vector( 31 downto 0 );
-
- signal_write : out std_logic;
- signal_writedata : out std_logic_vector( 31 downto 0 )
- );
- end entity task_sine;
-
- architecture struct of task_sine is
-
- signal task_start : std_logic;
- signal task_state : work.task.State := work.task.TASK_IDLE;
- signal task_config : work.reg32.RegArray( 0 to 2 );
-
- begin
- u_control: entity work.hardware_task_control
- port map (
- clk => clk,
- reset => reset,
-
- address => address,
- read => read,
- readdata => readdata,
- write => write,
- writedata => writedata,
-
- task_start => task_start,
- task_state => task_state,
- task_config => task_config
- );
-
- u_sine: entity work.sine
- port map (
- clk => clk,
- reset => reset,
-
- task_start => task_start,
- task_state => task_state,
-
- step_size => task_config( 0 ),
- phase => task_config( 1 ),
- amplitude => task_config( 2 ),
-
- signal_write => signal_write,
- signal_writedata => signal_writedata
- );
-
- end architecture struct;
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