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weingartzra102473
2024-12-18 09:52:29 +01:00
parent 0d1b73e3e0
commit 22e222fab4
6 changed files with 490 additions and 145 deletions
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hardware/signal_processing/add.vhd
+109 -10
View File
@@ -30,8 +30,103 @@ architecture rtl of add is
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
type AddState is(
ADD_IDLE,
ADD_READ,
ADD_CALC,
ADD_STORERESULT
);
signal curAddState : ADDState;
signal nextAddState : ADDState;
signal a : std_logic_vector (31 downto 0);
signal b : std_logic_vector (31 downto 0);
signal startcore : std_logic;
signal donecore : std_logic;
signal sumcore : std_logic_vector (31 downto 0);
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
u_float_add : entity work.float_add
port map(
clk => clk,
reset => reset,
start => startcore,
done => donecore,
A => a,
B => b,
sum => sumcore
);
--Zuletzt haben wir den State transitions prozess angelegt. Ziegler nachfragen
add_state_transitions : process (all) is
begin
--if(reset ='1' and rising_edge(clk)) then
nextAddState <= curAddState;
case curAddState is
when ADD_IDLE =>
if(current_task_state = work.task.TASK_RUNNING) then
nextAddState <= ADD_CALC;
end if;
when ADD_READ =>
nextAddState <= ADD_CALC;
when ADD_CALC => Null;
if(donecore = '1') then
nextAddState <=ADD_STORERESULT;
end if;
when ADD_STORERESULT =>
nextAddState <= ADD_READ;
when others =>
nextAddState <= curAddState;
end case;
end process add_state_transitions;
add_process : process (clk,reset) is
begin
if(reset = '1') then
curADDState <= ADD_CALC;
index <= 0;
signal_write <='0';
signal_a_read <='0';
signal_b_read <='0';
startcore <= '0';
signal_writedata <= (others => '0');
b<= (others => '0');
a<= (others => '0');
elsif(rising_edge(clk)) then
curAddState <= nextAddState;
Case curAddState is
when ADD_IDLE =>
NULL;
when ADD_READ =>
signal_write <= '0';
signal_a_read <= '1';
signal_b_read <= '1';
when ADD_CALC =>
signal_a_read <= '0';
signal_b_read <= '0';
a <= signal_a_readdata;
b <= signal_b_readdata;
startcore <= '1';
when ADD_STORERESULT =>
startcore <= '0';
signal_writedata <= sumcore;
signal_write <= '1';
index <= index+1;
when others =>Null;
end case;
if(current_task_state=work.task.TASK_DONE)then
index <= 0;
signal_write <= '0';
end if;
end if;
end process add_process;
--
task_state_transitions : process ( all ) is
begin
next_task_state <= current_task_state;
case current_task_state is
@@ -40,7 +135,7 @@ begin
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
if ( index = work.task.STREAM_LEN ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
@@ -54,21 +149,25 @@ begin
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
-- index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
NULL;
-- index <= 0;
-- signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
NULL;
-- index <= index + 1;
-- signal_write <= '1';
-- signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
NULL;
-- index <= 0;
-- signal_write <= '0';
end case;
--test
end if;
end process sync;
hardware/signal_processing/crc.vhd
+89 -4
View File
@@ -28,7 +28,19 @@ architecture rtl of crc is
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
-- function berechne_crc(crc_in : signed( 31 downto 0 ), data : signed( 31 downto 0 )) return signed;
--Selbst angelegte Signale
signal flag_index : bit := '0';
signal crc_state : integer range 0 to 2;
signal crcOut : std_logic_vector( 31 downto 0);
signal crcIn : std_logic_vector( 31 downto 0) := x"FFFFFFFF";
begin
--No Touchy
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
@@ -48,6 +60,8 @@ begin
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
@@ -58,18 +72,89 @@ begin
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
-- signal_write <= '0';
when work.task.TASK_RUNNING =>
if ( flag_index = '1' ) then
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
end if;
--signal_write <= '1';
--signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
--signal_write <= '0';
end case;
end if;
end process sync;
crc_calc :process ( clk, reset ) is
begin
if ( reset = '1' ) then
signal_read <= '0';
signal_write <= '0';
signal_writedata <= (others => '0');
flag_index <= '0';
elsif ( rising_edge( clk ) ) then
case crc_state is --current oder next_calc_state
when 0 =>
signal_write <= '0';
flag_index <= '0';
if ( current_task_state = work.task.TASK_RUNNING ) then
signal_read <= '1';
crc_state <= 1;
end if;
when 1 =>
signal_read <= '0';
crcOut(0) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(16) xor crcIn(20) xor crcIn(22) xor crcIn(23) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(26);
crcOut(1) <= crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(17) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(27);
crcOut(2) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(18) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(28) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(28);
crcOut(3) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(19) xor crcIn(23) xor crcIn(25) xor crcIn(26) xor crcIn(29) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(29);
crcOut(4) <= crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(20) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(20) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(30);
crcOut(5) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(21) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(21) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(31);
crcOut(6) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(28) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(28) xor signal_readdata(29);
crcOut(7) <= crcIn(1) xor crcIn(3) xor crcIn(4) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(29) xor signal_readdata(30);
crcOut(8) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
crcOut(9) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(31);
crcOut(10) <= crcIn(0) xor crcIn(2) xor crcIn(4) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(13) xor crcIn(14) xor crcIn(18) xor crcIn(21) xor crcIn(22) xor crcIn(26) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(26);
crcOut(11) <= crcIn(1) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(8) xor crcIn(10) xor crcIn(14) xor crcIn(15) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(27) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(27);
crcOut(12) <= crcIn(2) xor crcIn(4) xor crcIn(6) xor crcIn(7) xor crcIn(9) xor crcIn(11) xor crcIn(15) xor crcIn(16) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28);
crcOut(13) <= crcIn(0) xor crcIn(3) xor crcIn(5) xor crcIn(7) xor crcIn(8) xor crcIn(10) xor crcIn(12) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29);
crcOut(14) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(6) xor crcIn(8) xor crcIn(9) xor crcIn(11) xor crcIn(13) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(30);
crcOut(15) <= crcIn(1) xor crcIn(2) xor crcIn(5) xor crcIn(7) xor crcIn(9) xor crcIn(10) xor crcIn(12) xor crcIn(14) xor crcIn(18) xor crcIn(19) xor crcIn(23) xor crcIn(26) xor crcIn(27) xor crcIn(31) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(31);
crcOut(16) <= crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(13) xor crcIn(15) xor crcIn(16) xor crcIn(19) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28);
crcOut(17) <= crcIn(2) xor crcIn(5) xor crcIn(8) xor crcIn(11) xor crcIn(12) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(8) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29);
crcOut(18) <= crcIn(0) xor crcIn(3) xor crcIn(6) xor crcIn(9) xor crcIn(12) xor crcIn(13) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
crcOut(19) <= crcIn(0) xor crcIn(1) xor crcIn(4) xor crcIn(7) xor crcIn(10) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(18) xor crcIn(19) xor crcIn(22) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
crcOut(20) <= crcIn(0) xor crcIn(3) xor crcIn(4) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(14) xor crcIn(15) xor crcIn(16) xor crcIn(17) xor crcIn(19) xor crcIn(22) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
crcOut(21) <= crcIn(0) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(12) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(12) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
crcOut(22) <= crcIn(2) xor crcIn(7) xor crcIn(8) xor crcIn(13) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(2) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(13) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
crcOut(23) <= crcIn(0) xor crcIn(3) xor crcIn(8) xor crcIn(9) xor crcIn(14) xor crcIn(19) xor crcIn(20) xor crcIn(21) xor crcIn(23) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(14) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
crcOut(24) <= crcIn(2) xor crcIn(3) xor crcIn(6) xor crcIn(7) xor crcIn(8) xor crcIn(9) xor crcIn(10) xor crcIn(15) xor crcIn(16) xor crcIn(21) xor crcIn(23) xor crcIn(24) xor crcIn(26) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
crcOut(25) <= crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(9) xor crcIn(10) xor crcIn(11) xor crcIn(17) xor crcIn(20) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(29) xor crcIn(30) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
crcOut(26) <= crcIn(2) xor crcIn(3) xor crcIn(7) xor crcIn(10) xor crcIn(11) xor crcIn(12) xor crcIn(18) xor crcIn(21) xor crcIn(24) xor crcIn(25) xor crcIn(26) xor crcIn(27) xor crcIn(28) xor crcIn(30) xor crcIn(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
crcOut(27) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(6) xor crcIn(7) xor crcIn(11) xor crcIn(12) xor crcIn(13) xor crcIn(16) xor crcIn(19) xor crcIn(20) xor crcIn(23) xor crcIn(25) xor crcIn(27) xor crcIn(28) xor crcIn(29) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
crcOut(28) <= crcIn(0) xor crcIn(4) xor crcIn(6) xor crcIn(12) xor crcIn(13) xor crcIn(14) xor crcIn(16) xor crcIn(17) xor crcIn(21) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(28) xor crcIn(29) xor crcIn(30) xor signal_readdata(0) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
crcOut(29) <= crcIn(0) xor crcIn(1) xor crcIn(5) xor crcIn(7) xor crcIn(13) xor crcIn(14) xor crcIn(15) xor crcIn(17) xor crcIn(18) xor crcIn(22) xor crcIn(23) xor crcIn(24) xor crcIn(25) xor crcIn(29) xor crcIn(30) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
crcOut(30) <= crcIn(3) xor crcIn(4) xor crcIn(7) xor crcIn(14) xor crcIn(15) xor crcIn(18) xor crcIn(19) xor crcIn(20) xor crcIn(22) xor crcIn(24) xor crcIn(25) xor crcIn(30) xor crcIn(31) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
crcOut(31) <= crcIn(0) xor crcIn(1) xor crcIn(2) xor crcIn(3) xor crcIn(5) xor crcIn(6) xor crcIn(7) xor crcIn(15) xor crcIn(19) xor crcIn(21) xor crcIn(22) xor crcIn(25) xor crcIn(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(31);
crc_state <= 2; --Calc Zustand aendern
when 2 =>
if ( current_task_state = work.task.TASK_DONE ) then
signal_writedata <= not crcOut; --Ergebnis invertieren
signal_write <= '1';
end if;
flag_index <= '1'; --flag_index sagt nur, dass der index hochgezaehlt werden soll
crc_state <= 0; --Calc Zustand aendern
-- assign new crc value
crcIn <= crcOut;
end case;
end if;
end process crc_calc;
task_state <= current_task_state;
end architecture rtl;
hardware/signal_processing/sine.vhd
+99 -12
View File
@@ -26,12 +26,46 @@ end entity sine;
architecture rtl of sine is
signal current_task_state : work.task.State;
signal current_task_state : work.task.State; --multiple sources
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal index : integer range 0 to work.task.STREAM_LEN; --multiple sources
--Selbst angelegte Signal:
signal data_valid_flag : std_logic;
signal busy_flag : std_logic;
signal result_valid_flag : std_logic;
signal angle_sig : signed( 31 downto 0);
signal ergebnis : signed( 31 downto 0 );
signal ampl_sig : signed( 31 downto 0 );
--Zustände für die Zustandsmaschine für die Berechnung
type CalcState is (
CALC_IDLE,
CALC_START,
CALC_SINE,
CALC_STORE_RESULT
);
--Signale für die Zustandsmaschine für die Berechnung
signal current_calc_state : CalcState;
signal next_calc_state : CalcState;
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
u_float_sine : entity work.float_sine -- Das hier ist der Core!
generic map (
ITERATIONS => 8
)
port map (
clk => clk,
reset => reset,
data_valid => data_valid_flag, --# load new input data
busy => busy_flag, --# generating new result
result_valid => result_valid_flag, --# flag when result is valid
angle => angle_sig, -- angle in brads (2**size brads = 2*pi radians)
sine => ergebnis --Hierzu nachfragen
);
--Bei diesem task nichts ändern!
task_state_transitions : process ( all ) is
begin
next_task_state <= current_task_state;
case current_task_state is
@@ -50,28 +84,81 @@ begin
end case;
end process task_state_transitions;
sync : process ( clk, reset ) is
--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Fertig
calc_state_transitions: process (all) is
begin
next_calc_state <= current_calc_state;
case current_calc_state is
when CALC_IDLE=>
if (current_task_state= work.task.TASK_RUNNING) then
next_calc_state <= CALC_START;
end if;
when CALC_START=>
next_calc_state <= CALC_SINE;
when CALC_SINE =>
if (result_valid_flag = '1' and busy_flag = '0') then --or falling_edge( busy) ?
next_calc_state <= CALC_STORE_RESULT;
end if;
when CALC_STORE_RESULT =>
if ( index = work.task.STREAM_LEN ) then
next_calc_state <= CALC_IDLE;
else
next_calc_state <= CALC_START;
end if;
end case;
end process calc_state_transitions;
--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks
task_sync : process (clk, reset) is
begin
if (reset = '1') then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif (rising_edge( clk)) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
when work.task. TASK_IDLE => null;
when work.task. TASK_RUNNING => null;
when work.task. TASK_DONE => null;
end case;
end if;
end process task_sync;
--Zustandsspeicher und Ausgangsschaltnetz zu Berechnung
sync : process (clk, reset) is
begin
if (reset = '1') then
index <= 0;
data_valid_flag <= '0';
current_calc_state <= CALC_IDLE;
--ergebnis <= (others => '0'); --Wird von IP Core gesteuert und darf deshalb hier nicht getrieben werden
signal_writedata <= (others => '0');
signal_write <= '0';
when work.task.TASK_RUNNING =>
angle_sig <= (others => '0');
elsif (rising_edge( clk)) then
current_calc_state <= next_calc_state;
case next_calc_state is
when CALC_IDLE =>
data_valid_flag <= '0';
signal_write <= '0';
angle_sig <= signed (phase);
ampl_sig <= signed (amplitude);
when CALC_START =>
data_valid_flag <= '1';
signal_write <= '0';
angle_sig <= angle_sig + signed(step_size); --step_size = 2 * PI / 32
when CALC_SINE => --hier Berechnung mit IP Core?
data_valid_flag <= '0';
when CALC_STORE_RESULT =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
--Berechne float multiplikation zu Fuss. Exponent + Exponent usw.
signal_writedata <= std_logic_vector( ergebnis(31 downto 31) & (ergebnis(30 downto 23) + (signed(ampl_sig(30 downto 23)) - 127)) & ergebnis(22 downto 0));
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
software/signal_processing/add.c
+10 -1
View File
@@ -5,7 +5,16 @@
int task_add_run( void * task ) {
// TODO
add_config * config = (add_config *) task;
for( uint32_t i=0; i< DATA_CHANNEL_DEPTH; ++i)
{
float a,b;
float_word c;
data_channel_read(config->sources [0],(uint32_t * ) & a);
data_channel_read(config->sources [1],(uint32_t * ) & b);
c.value = a+b;
data_channel_write( config->sink, c.word);
}
return 0;
}
software/signal_processing/crc.c
+47 -1
View File
@@ -1,11 +1,57 @@
#include "system/task_crc.h"
#include "system/data_channel.h"
#include "system/float_word.h"
#include <stdio.h>
// Funktion zur Berechnung des CRC32
void berechne_crc32(uint32_t data, uint32_t * crc);
void crc32( uint32_t data, uint32_t* crc );
int task_crc_run( void * task ) {
crc_config * config = (crc_config*) task;
uint32_t value = config->start;
// Nachfolgende Antworten Lesen den FIFO der ersten Datenquelle aus und multiplizieren
// den jeweils gelesenen Wert mit 4 und speichern das Ergebnis in der Datensenke
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
float_word a;
data_channel_read(config->base.sources[0], (uint32_t * ) & a.value );
if (i<10) {printf("\n Input %i DATA; %x\ CRC: %x\n", i, a.word, value);}
berechne_crc32(a.word, &value); //Startwert jedes Mal, oder mit vorheriger crc starten?
if (i<10) {printf("\n CRC Zwischenwert Output(%i): %x\n", i, value);}
}
printf("CRC Wert: %x\n", value);
data_channel_write( config->base.sink, value);
// TODO
return 0;
}
void berechne_crc32(uint32_t data, uint32_t * crc) {
uint32_t bytes[4]; //Reihenfolge richtig?
uint32_t reg32 = ~*crc;
bytes[0] = (uint32_t) (data) & 0x000000FF;
bytes[1] = (uint32_t) (data >>8) & 0x000000FF;
bytes[2] = (uint32_t) (data >>16) & 0x000000FF;
bytes[3] = (uint32_t) (data >>24) & 0x000000FF; //aufffüllen
for (uint32_t i = 0; i < 4; i++) {
//von rechts nch links
for (uint8_t j = 0; j <8; j++) {
// Prüfen, ob das am weitesten rechts stehende Bit von crc 1 ist
if ((reg32 & 1) != (bytes[i] & 1)) { //Wieso crc & 1?
reg32 = (reg32 >> 1)^CRC32POLY; // XOR mit dem Polynom
} else {
reg32 >>= 1;
}
bytes[i]>>=1;
}
*crc = reg32 ^0xFFFFFFFF;
}
}
software/signal_processing/sine.c
+20 -1
View File
@@ -1,10 +1,29 @@
//Aus dem Skript kopiert:
#include "system/task_sine.h"
#include "system/hardware_task.h"
#include "system/sine_config.h"
#include "system/data_channel.h"
#include "system/float_word.h"
#include <math.h>
#include <stdio.h>
#include <limits.h>
#include <system.h>
int task_sine_run( void * data) {
// TODO
// Nachfolgende Anweisungen Schreiben 1024 Mal den Wert 4 in den FIFO für Sinus
sine_config * task = (sine_config * ) data;
uint32_t data_channel_base = task->base.sink;
data_channel_clear( data_channel_base );
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
float_word res;
res.value = task->amplitude * sin(task->phase + i *2 * M_PI / task->samples_per_periode);
data_channel_write( data_channel_base, res.word );
}
return 0;
}