diff --git a/RTC/.cproject b/RTC/.cproject index 6ac5a98..3da22de 100644 --- a/RTC/.cproject +++ b/RTC/.cproject @@ -1,8 +1,8 @@ - - + + @@ -14,61 +14,61 @@ - - - - - - + + @@ -92,60 +92,60 @@ - - - - + - + - + - + - + + diff --git a/RTC/.mxproject b/RTC/.mxproject index f37cc11..f852674 100644 --- a/RTC/.mxproject +++ b/RTC/.mxproject @@ -1,25 +1,25 @@ [PreviousLibFiles] -LibFiles=Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h;Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h;Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; +LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_armv8mbl.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/tz_context.h; [PreviousUsedCubeIDEFiles] -SourceFiles=Core\Src\main.c;Core\Src\stm32l1xx_it.c;Core\Src\stm32l1xx_hal_msp.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Core\Src/system_stm32l1xx.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c;Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c;Core\Src/system_stm32l1xx.c;Drivers/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c;; -HeaderPath=Drivers\STM32L1xx_HAL_Driver\Inc;Drivers\STM32L1xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32L1xx\Include;Drivers\CMSIS\Include;Core\Inc; -CDefines=USE_HAL_DRIVER;STM32L152xE;USE_HAL_DRIVER;USE_HAL_DRIVER; +SourceFiles=Core\Src\main.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Core\Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Core\Src/system_stm32f4xx.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;; +HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc; +CDefines=USE_HAL_DRIVER;STM32F401xE;USE_HAL_DRIVER;USE_HAL_DRIVER; [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=3 -HeaderFiles#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Inc/stm32l1xx_it.h -HeaderFiles#1=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Inc/stm32l1xx_hal_conf.h -HeaderFiles#2=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Inc/main.h +HeaderFiles#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Inc/stm32f4xx_it.h +HeaderFiles#1=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Inc/stm32f4xx_hal_conf.h +HeaderFiles#2=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Inc/main.h HeaderFolderListSize=1 -HeaderPath#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Inc +HeaderPath#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Inc HeaderFiles=; SourceFileListSize=3 -SourceFiles#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Src/stm32l1xx_it.c -SourceFiles#1=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Src/stm32l1xx_hal_msp.c -SourceFiles#2=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Src/main.c +SourceFiles#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Src/stm32f4xx_it.c +SourceFiles#1=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Src/stm32f4xx_hal_msp.c +SourceFiles#2=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Src/main.c SourceFolderListSize=1 -SourcePath#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace_Solar_Panel/RTC/Core/Src +SourcePath#0=C:/Users/Gregor/Desktop/Projektarbeit/Workspace/RTC/Core/Src SourceFiles=; diff --git a/RTC/.settings/language.settings.xml b/RTC/.settings/language.settings.xml index d9f4747..54f19ce 100644 --- a/RTC/.settings/language.settings.xml +++ b/RTC/.settings/language.settings.xml @@ -1,24 +1,24 @@ - + - + - + - + diff --git a/RTC/Core/Inc/main.h b/RTC/Core/Inc/main.h index 519401c..2987eb0 100644 --- a/RTC/Core/Inc/main.h +++ b/RTC/Core/Inc/main.h @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -28,7 +28,7 @@ extern "C" { #endif /* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" +#include "stm32f4xx_hal.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/RTC/Core/Inc/stm32l1xx_hal_conf.h b/RTC/Core/Inc/stm32l1xx_hal_conf.h deleted file mode 100644 index 7e459e6..0000000 --- a/RTC/Core/Inc/stm32l1xx_hal_conf.h +++ /dev/null @@ -1,335 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_conf.h - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CONF_H -#define __STM32L1xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ - -#define HAL_MODULE_ENABLED -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_I2C_MODULE_ENABLED */ -/*#define HAL_I2S_MODULE_ENABLED */ -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_LCD_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_OPAMP_MODULE_ENABLED */ -/*#define HAL_PCD_MODULE_ENABLED */ -#define HAL_RTC_MODULE_ENABLED -/*#define HAL_SD_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SPI_MODULE_ENABLED */ -/*#define HAL_SRAM_MODULE_ENABLED */ -/*#define HAL_TIM_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_EXTI_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE (37000U) /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature.*/ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ - -#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority */ -#define USE_RTOS 0 -#define PREFETCH_ENABLE 0 -#define INSTRUCTION_CACHE_ENABLE 1 -#define DATA_CACHE_ENABLE 1 - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Register callback feature configuration ############### */ -/** - * @brief Set below the peripheral configuration to "1U" to add the support - * of HAL callback registration/deregistration feature for the HAL - * driver(s). This allows user application to provide specific callback - * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting - * the default weak callback functions (see each stm32l0xx_hal_ppp.h file - * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef - * for each PPP peripheral). - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U -#define USE_HAL_SDMMC_REGISTER_CALLBACKS 0U -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U -#define USE_HAL_UART_REGISTER_CALLBACKS 0U -#define USE_HAL_USART_REGISTER_CALLBACKS 0U -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ - -#define USE_SPI_CRC 0U -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32l1xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32l1xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32l1xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32l1xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32l1xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED - #include "stm32l1xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32l1xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32l1xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32l1xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32l1xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32l1xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32l1xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32l1xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32l1xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32l1xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LCD_MODULE_ENABLED - #include "stm32l1xx_hal_lcd.h" -#endif /* HAL_LCD_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED - #include "stm32l1xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32l1xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32l1xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32l1xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32l1xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32l1xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32l1xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32l1xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32l1xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32l1xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32l1xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32l1xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32l1xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CONF_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Core/Inc/stm32l1xx_it.h b/RTC/Core/Inc/stm32l1xx_it.h deleted file mode 100644 index 019f774..0000000 --- a/RTC/Core/Inc/stm32l1xx_it.h +++ /dev/null @@ -1,69 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32l1xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_IT_H -#define __STM32L1xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_IT_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Core/Src/main.c b/RTC/Core/Src/main.c index 83e8eac..c13ba53 100644 --- a/RTC/Core/Src/main.c +++ b/RTC/Core/Src/main.c @@ -6,7 +6,7 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2020 STMicroelectronics. + *

© Copyright (c) 2021 STMicroelectronics. * All rights reserved.

* * This software component is licensed by ST under BSD 3-Clause license, @@ -19,6 +19,8 @@ /* USER CODE END Header */ /* Includes ------------------------------------------------------------------*/ #include "main.h" +#include "math.h" +#include "stdbool.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ @@ -32,6 +34,7 @@ /* Private define ------------------------------------------------------------*/ /* USER CODE BEGIN PD */ + /* USER CODE END PD */ /* Private macro -------------------------------------------------------------*/ @@ -44,7 +47,16 @@ RTC_HandleTypeDef hrtc; UART_HandleTypeDef huart2; RTC_TimeTypeDef sTime; RTC_DateTypeDef sDate; +RTC_AlarmTypeDef sAlarm; +//Nuernberg coordinates +int latitude_nbg = 49; +int longitude_nbg = 11; + +//German UTC time,summer (+2) and winter (+1) +int UTC_DER_sum = 2; +int UTC_DER_win = 1; +bool winterTime = true; /* USER CODE BEGIN PV */ @@ -61,6 +73,265 @@ static void MX_RTC_Init(void); /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ +/******************************************************************************* +* Function Name : deg_to_rad +* Description : converts degrees to radians +* Return : angle in radians +*******************************************************************************/ +double deg_to_rad(double deg) +{ + double rad = deg*(M_PI/180); + return rad; +} + +/******************************************************************************* +* Function Name : rad_to_deg +* Description : converts radians to degrees +* Return : angle in degrees +*******************************************************************************/ +double rad_to_deg(double rad) +{ + double deg = rad*(180/M_PI); + return deg; +} + +/******************************************************************************* +* Function Name : leap_year_check +* Description : checks if year is a leap year +* Return : false: no leap year, true: leap year +*******************************************************************************/ +int leap_year_check(int year) +{ + if((year % 4 == 0 && year % 100 != 0) || (year % 400 == 0)) + { + return true; + } + return false; +} + +/******************************************************************************* +* Function Name : calc_day_of_year +* Description : calculates the day of year +* Return : day of year (1.1.. = 1, 2.1.. = 2,...) +* Source : https://overiq.com/c-examples/c-program-to-calculate-the-day-of-year-from-the-date/ +*******************************************************************************/ +int calc_day_of_year(int day, int mon, int year) +{ + int days_in_feb = 28; + int doy = day; //day of year + + // check for leap year + bool leap_year = leap_year_check(year); + if(leap_year == true) + { + days_in_feb = 29; + } + + switch(mon) + { + case 2: + doy += 31; + break; + case 3: + doy += 31+days_in_feb; + break; + case 4: + doy += days_in_feb+62; + break; + case 5: + doy += days_in_feb+92; + break; + case 6: + doy += days_in_feb+123; + break; + case 7: + doy += days_in_feb+153; + break; + case 8: + doy += days_in_feb+184; + break; + case 9: + doy += days_in_feb+215; + break; + case 10: + doy += days_in_feb+245; + break; + case 11: + doy += days_in_feb+276; + break; + case 12: + doy += days_in_feb+306; + break; + } + return doy; +} + +/******************************************************************************* +* Function Name : calc_sunrise_sunset +* Description : calculates the sunrise and sunset time of a specific date +* Source : General Solar Position Calculations, NOAA Global Monitoring Division +*******************************************************************************/ +void calc_sunrise_sunset(int date, int month, int year, int sunrise_time[2], int sunset_time[2]) +{ + double gamma = 0; + bool leap_year; + double eqtime = 0; + double decl = 0; + double decl_deg = 0; + double zenith_sun = 0; + double lat_nbg_rad = 0; + double ha = 0; + double sunrise = 0; + double sunset = 0; + double ha_deg = 0; + int sunrise_h = 0; + int sunset_h = 0; + double sunrise_min = 0; + double sunset_min = 0; + int int_sunrise_min = 0; + int int_sunset_min = 0; + + //day of year calculation + int day_of_year = calc_day_of_year(date, month, year); + + // fractional year (γ) in radians + // check for leap year + leap_year = leap_year_check(year); + if(leap_year == false) + { + //The back part of the formula was omitted, because there is no difference in the result + gamma = ((2 * M_PI)/365)*(day_of_year - 1); + } else { + //The back part of the formula was omitted, because there is no difference in the result + gamma = ((2 * M_PI)/366)*(day_of_year - 1); + } + + //Equation of time in minutes + eqtime = 229.18*(0.000075 + 0.001868*cos(gamma) - 0.032077*sin(gamma) - 0.014615*cos(2*gamma) - 0.040849*sin(2*gamma)); + + //Solar declination angle in radians + decl = 0.006918 - 0.399912*cos(gamma) + 0.070257*sin(gamma) - 0.006758*cos(2*gamma) + 0.000907*sin(2*gamma) - 0.002697*cos(3*gamma) + 0.00148*sin(3*gamma); + + //Solar declination angle in degrees + decl_deg = rad_to_deg(decl); + + //Hour angle in degrees, positive number corresponds to sunrise, negative to sunset + //special case of sunrise or sunset, the zenith is set to 90.833Deg + zenith_sun = deg_to_rad(90.833); + //Latitude of Nuernberg in rad + lat_nbg_rad = deg_to_rad(latitude_nbg); + ha = acos((cos(zenith_sun)/(cos(lat_nbg_rad)*cos(decl)))-(tan(lat_nbg_rad)*tan(decl))); + ha_deg = rad_to_deg(ha); + + //UTC time of sunrise (or sunset) in minutes + sunrise = (720-4*(longitude_nbg+ha_deg)-eqtime); + sunset = 720-4*(longitude_nbg-ha_deg)-eqtime; + + //Convert sunrise (or sunset) UTC time in hours + sunrise = sunrise/60; + sunset = sunset/60; + + //Seperate hours and minutes + sunrise_h = floor(sunrise); + sunrise_min = sunrise - sunrise_h; + //Cut off after two decimal places + int_sunrise_min = floor(sunrise_min * 100.0); + if (int_sunrise_min >= 60) + { + sunrise_h = sunrise_h + 1; + int_sunrise_min = int_sunrise_min - 60; + } + sunset_h = floor(sunset); + sunset_min = sunset - sunset_h; + //Cut off after two decimal places + int_sunset_min = floor(sunset_min * 100.0); + if (int_sunset_min >= 60) + { + sunset_h = sunset_h + 1; + int_sunset_min = int_sunset_min - 60; + } + + //Add time difference from German time to UTC Time + //Private variable winterTime must be initialized accordingly + if (winterTime) + { + sunrise_h = sunrise_h + UTC_DER_win; + sunset_h = sunset_h + UTC_DER_win; + } else { + sunrise_h = sunrise_h + UTC_DER_sum; + sunset_h = sunset_h + UTC_DER_sum; + } + + sunrise_time[0] = sunrise_h; + sunrise_time[1] = int_sunrise_min; + sunset_time[0] = sunset_h; + sunset_time[1] = int_sunset_min; +} + +/******************************************************************************* +* Function Name : calc_tomorrows_date +* Description : calculates tomorrow's date +* Source : https://github.com/vyacht/stm32/blob/master/vynmea/rtc.c +*******************************************************************************/ +void calc_tomorrows_date(int day, int wday, int month, int year, int DaysInMonth[12], int tomorrows_date[4]) +{ + bool leap_year; + + day++; // next day + wday++; // next weekday + if(wday == 8) + { + wday = 1; // Monday + } + if(day > DaysInMonth[month-1]) + { // next month + day = 1; + month++; + } + if(day > 31 && month == 12) // next year + { + day = 1; + month = 1; + year++; + } + + tomorrows_date[0] = day; + tomorrows_date[1] = wday; + tomorrows_date[2] = month; + tomorrows_date[3] = year; + +} + +/******************************************************************************* +* Function Name : set_Alarm +* Description : sets the wake up Alarm +*******************************************************************************/ +void set_Alarm(int h, int min, int weekDay) +{ + /** Enable the Alarm A*/ + sAlarm.AlarmTime.Hours = h; + sAlarm.AlarmTime.Minutes = min; + sAlarm.AlarmTime.Seconds = 0; + sAlarm.AlarmTime.SubSeconds = 0; + sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; //only by specific time + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL; + sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_WEEKDAY; + sAlarm.AlarmDateWeekDay = weekDay; + sAlarm.Alarm = RTC_ALARM_A; + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BIN) != HAL_OK) + { + Error_Handler(); + } +} + +// sending to UART +void transmit_uart(char *string){ + uint8_t len = strlen(string); + HAL_UART_Transmit(&huart2, (uint8_t*) string, len, 200); +} + /* USER CODE END 0 */ @@ -95,13 +366,26 @@ int main(void) MX_USART2_UART_Init(); MX_RTC_Init(); /* USER CODE BEGIN 2 */ - uint8_t hours = 0; - uint8_t minutes = 0; - uint8_t seconds = 0; - uint8_t weekDay = 0; - uint8_t month = 0; - uint8_t date = 0; - uint8_t year = 0; + int hours = 0; + int minutes = 0; + int seconds = 0; + int weekDay = 0; + int month = 0; + int date = 0; + int year = 0; + + int sunrise_h = 0; + int sunset_h = 0; + int int_sunrise_min = 0; + int int_sunset_min = 0; + int sunrise_time[2] = {0}; + int sunset_time[2] = {0}; + int tomorrows_date[4] = {0}; + int DaysInMonth[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + int DaysInMonthLeapYear[12] = {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + bool leap_year = false; + + /* USER CODE END 2 */ @@ -109,22 +393,50 @@ int main(void) /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ - if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK) - { - hours = sTime.Hours; - minutes = sTime.Minutes; - seconds = sTime.Seconds; - } - if (HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK) - { - weekDay = sDate.WeekDay; - month = sDate.Month; - date = sDate.Date; - year = sDate.Year; - } - HAL_Delay(200); + //Get Time and Date + if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK) + { + hours = sTime.Hours; + minutes = sTime.Minutes; + seconds = sTime.Seconds; + } + if (HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK) + { + weekDay = sDate.WeekDay; + month = sDate.Month; + date = sDate.Date; + year = 2000 + sDate.Year; + } + + // check for leap year + leap_year = leap_year_check(year); + if (leap_year) + { + //Calculate tomorrow's date + calc_tomorrows_date(date, weekDay, month, year, DaysInMonthLeapYear, tomorrows_date); + } else { + //Calculate tomorrow's date + calc_tomorrows_date(date, weekDay, month, year, DaysInMonth, tomorrows_date); + } + + //Calculate sunrise and sunset time for tomorrow + calc_sunrise_sunset(tomorrows_date[0], tomorrows_date[2], tomorrows_date[3], sunrise_time, sunset_time); + + set_Alarm(16, 22, 1); + + HAL_Delay(5000); + + transmit_uart("Ich gehe schlafen!\r\n"); + + // Suspend Tick increment to prevent wake up by Systick interrupt + HAL_SuspendTick(); + + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); //Interrupt for wake up + + HAL_ResumeTick(); + + transmit_uart("Bin wieder wach!\r\n"); } /* USER CODE END 3 */ } @@ -137,22 +449,25 @@ void SystemClock_Config(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; /** Configure the main internal regulator output voltage */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI; RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; + RCC_OscInitStruct.PLL.PLLM = 16; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + RCC_OscInitStruct.PLL.PLLQ = 7; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); @@ -163,16 +478,16 @@ void SystemClock_Config(void) |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; - PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } @@ -213,24 +528,25 @@ static void MX_RTC_Init(void) /** Initialize RTC and set the Time and Date */ - sTime.Hours = 23; - sTime.Minutes = 59; - sTime.Seconds = 45; + sTime.Hours = 16; + sTime.Minutes = 20; + sTime.Seconds = 30; sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; sTime.StoreOperation = RTC_STOREOPERATION_RESET; if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) { Error_Handler(); } - sDate.WeekDay = RTC_WEEKDAY_SUNDAY; - sDate.Month = RTC_MONTH_DECEMBER; - sDate.Date = 31; - sDate.Year = 17; + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + sDate.Month = RTC_MONTH_JANUARY; + sDate.Date = 11; + sDate.Year = 21; if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK) { Error_Handler(); } + /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ @@ -290,7 +606,7 @@ static void MX_GPIO_Init(void) /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); @@ -315,10 +631,25 @@ void Error_Handler(void) { /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ - + __disable_irq(); + while (1) + { + } /* USER CODE END Error_Handler_Debug */ } +/** + * @brief Alarm callback + * @param hrtc: RTC handle + * @retval None + */ +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* Alarm generation */ + transmit_uart("Alarm!!!!\r\n"); +} + + #ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number @@ -331,7 +662,7 @@ void assert_failed(uint8_t *file, uint32_t line) { /* USER CODE BEGIN 6 */ /* User can add his own implementation to report the file name and line number, - tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ /* USER CODE END 6 */ } #endif /* USE_FULL_ASSERT */ diff --git a/RTC/Core/Src/stm32l1xx_hal_msp.c b/RTC/Core/Src/stm32l1xx_hal_msp.c deleted file mode 100644 index 13267b9..0000000 --- a/RTC/Core/Src/stm32l1xx_hal_msp.c +++ /dev/null @@ -1,196 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * File Name : stm32l1xx_hal_msp.c - * Description : This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* External functions --------------------------------------------------------*/ -/* USER CODE BEGIN ExternalFunctions */ - -/* USER CODE END ExternalFunctions */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_COMP_CLK_ENABLE(); - __HAL_RCC_SYSCFG_CLK_ENABLE(); - __HAL_RCC_PWR_CLK_ENABLE(); - - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); - - /* System interrupt init*/ - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/** -* @brief RTC MSP Initialization -* This function configures the hardware resources used in this example -* @param hrtc: RTC handle pointer -* @retval None -*/ -void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) -{ - if(hrtc->Instance==RTC) - { - /* USER CODE BEGIN RTC_MspInit 0 */ - - /* USER CODE END RTC_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_RTC_ENABLE(); - /* USER CODE BEGIN RTC_MspInit 1 */ - - /* USER CODE END RTC_MspInit 1 */ - } - -} - -/** -* @brief RTC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hrtc: RTC handle pointer -* @retval None -*/ -void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) -{ - if(hrtc->Instance==RTC) - { - /* USER CODE BEGIN RTC_MspDeInit 0 */ - - /* USER CODE END RTC_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_RTC_DISABLE(); - /* USER CODE BEGIN RTC_MspDeInit 1 */ - - /* USER CODE END RTC_MspDeInit 1 */ - } - -} - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspInit 0 */ - - /* USER CODE END USART2_MspInit 0 */ - /* Peripheral clock enable */ - __HAL_RCC_USART2_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN USART2_MspInit 1 */ - - /* USER CODE END USART2_MspInit 1 */ - } - -} - -/** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - if(huart->Instance==USART2) - { - /* USER CODE BEGIN USART2_MspDeInit 0 */ - - /* USER CODE END USART2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART2_CLK_DISABLE(); - - /**USART2 GPIO Configuration - PA2 ------> USART2_TX - PA3 ------> USART2_RX - */ - HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); - - /* USER CODE BEGIN USART2_MspDeInit 1 */ - - /* USER CODE END USART2_MspDeInit 1 */ - } - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Core/Src/stm32l1xx_it.c b/RTC/Core/Src/stm32l1xx_it.c deleted file mode 100644 index 5e8c29e..0000000 --- a/RTC/Core/Src/stm32l1xx_it.c +++ /dev/null @@ -1,203 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32l1xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32l1xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ - -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex-M3 Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } -} - -/** - * @brief This function handles Pre-fetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } -} - -/** - * @brief This function handles System service call via SWI instruction. - */ -void SVC_Handler(void) -{ - /* USER CODE BEGIN SVC_IRQn 0 */ - - /* USER CODE END SVC_IRQn 0 */ - /* USER CODE BEGIN SVC_IRQn 1 */ - - /* USER CODE END SVC_IRQn 1 */ -} - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/** - * @brief This function handles Pendable request for system service. - */ -void PendSV_Handler(void) -{ - /* USER CODE BEGIN PendSV_IRQn 0 */ - - /* USER CODE END PendSV_IRQn 0 */ - /* USER CODE BEGIN PendSV_IRQn 1 */ - - /* USER CODE END PendSV_IRQn 1 */ -} - -/** - * @brief This function handles System tick timer. - */ -void SysTick_Handler(void) -{ - /* USER CODE BEGIN SysTick_IRQn 0 */ - - /* USER CODE END SysTick_IRQn 0 */ - HAL_IncTick(); - /* USER CODE BEGIN SysTick_IRQn 1 */ - - /* USER CODE END SysTick_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32L1xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32l1xx.s). */ -/******************************************************************************/ - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Core/Src/sysmem.c b/RTC/Core/Src/sysmem.c index 23180b6..d7cc52c 100644 --- a/RTC/Core/Src/sysmem.c +++ b/RTC/Core/Src/sysmem.c @@ -60,7 +60,7 @@ void *_sbrk(ptrdiff_t incr) const uint8_t *max_heap = (uint8_t *)stack_limit; uint8_t *prev_heap_end; - /* Initalize heap end at first call */ + /* Initialize heap end at first call */ if (NULL == __sbrk_heap_end) { __sbrk_heap_end = &_end; diff --git a/RTC/Core/Src/system_stm32l1xx.c b/RTC/Core/Src/system_stm32l1xx.c deleted file mode 100644 index c3d397d..0000000 --- a/RTC/Core/Src/system_stm32l1xx.c +++ /dev/null @@ -1,408 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l1xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** @addtogroup STM32L1xx_System_Private_Includes - * @{ - */ - -#include "stm32l1xx.h" - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000U) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM32L152D_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -uint32_t SystemCoreClock = 2097000U; -const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; -const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; -const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes - * @{ - */ - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI - * value as defined by the MSI range. - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - case 0x04: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x08: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x0C: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00) - { - /* HSI oscillator clock selected as PLL clock entry */ - SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); - } - else - { - /* HSE selected as PLL clock entry */ - SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in SystemInit() function before jump to main. - * This function configures the external SRAM mounted on STM32L152D_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ - __IO uint32_t tmpreg = 0; - - /* Flash 1 wait state */ - FLASH->ACR |= FLASH_ACR_LATENCY; - - /* Power enable */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN); - - /* Select the Voltage Range 1 (1.8 V) */ - PWR->CR = PWR_CR_VOS_0; - - /* Wait Until the Voltage Regulator is ready */ - while((PWR->CSR & PWR_CSR_VOSF) != RESET) - { - } - -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ - | PD15 <-> FSMC_D1 |--------------------+ - +-------------------+ -*/ - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHBENR = 0x000080D8; - - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN); - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00CC00CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A0A; - /* Configure PDx pins speed to 40 MHz */ - GPIOD->OSPEEDR = 0xFFFF0F0F; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 40 MHz */ - GPIOE->OSPEEDR = 0xFFFFC00F; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 40 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x00000C00; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00200AAA; - /* Configure PGx pins speed to 40 MHz */ - GPIOG->OSPEEDR = 0x00300FFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHBENR = 0x400080D8; - - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN); - - (void)(tmpreg); - - /* Configure and enable Bank1_SRAM3 */ - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000300; - FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; -/* - Bank1_SRAM3 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 3; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); -*/ - -} -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Core/Startup/startup_stm32l152retx.s b/RTC/Core/Startup/startup_stm32l152retx.s deleted file mode 100644 index 39307f4..0000000 --- a/RTC/Core/Startup/startup_stm32l152retx.s +++ /dev/null @@ -1,409 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32l152xe.s - * @author MCD Application Team - * @brief STM32L152XE Devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Configure the clock system - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * @attention - * - * Copyright (c) 2017 STMicroelectronics. All rights reserved. - * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -.equ BootRAM, 0xF108F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler - .word PVD_IRQHandler - .word TAMPER_STAMP_IRQHandler - .word RTC_WKUP_IRQHandler - .word FLASH_IRQHandler - .word RCC_IRQHandler - .word EXTI0_IRQHandler - .word EXTI1_IRQHandler - .word EXTI2_IRQHandler - .word EXTI3_IRQHandler - .word EXTI4_IRQHandler - .word DMA1_Channel1_IRQHandler - .word DMA1_Channel2_IRQHandler - .word DMA1_Channel3_IRQHandler - .word DMA1_Channel4_IRQHandler - .word DMA1_Channel5_IRQHandler - .word DMA1_Channel6_IRQHandler - .word DMA1_Channel7_IRQHandler - .word ADC1_IRQHandler - .word USB_HP_IRQHandler - .word USB_LP_IRQHandler - .word DAC_IRQHandler - .word COMP_IRQHandler - .word EXTI9_5_IRQHandler - .word LCD_IRQHandler - .word TIM9_IRQHandler - .word TIM10_IRQHandler - .word TIM11_IRQHandler - .word TIM2_IRQHandler - .word TIM3_IRQHandler - .word TIM4_IRQHandler - .word I2C1_EV_IRQHandler - .word I2C1_ER_IRQHandler - .word I2C2_EV_IRQHandler - .word I2C2_ER_IRQHandler - .word SPI1_IRQHandler - .word SPI2_IRQHandler - .word USART1_IRQHandler - .word USART2_IRQHandler - .word USART3_IRQHandler - .word EXTI15_10_IRQHandler - .word RTC_Alarm_IRQHandler - .word USB_FS_WKUP_IRQHandler - .word TIM6_IRQHandler - .word TIM7_IRQHandler - .word 0 - .word TIM5_IRQHandler - .word SPI3_IRQHandler - .word UART4_IRQHandler - .word UART5_IRQHandler - .word DMA2_Channel1_IRQHandler - .word DMA2_Channel2_IRQHandler - .word DMA2_Channel3_IRQHandler - .word DMA2_Channel4_IRQHandler - .word DMA2_Channel5_IRQHandler - .word 0 - .word COMP_ACQ_IRQHandler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word BootRAM /* @0x108. This is for boot in RAM mode for - STM32L152XE devices. */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMPER_STAMP_IRQHandler - .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_IRQHandler - .thumb_set DMA1_Channel2_IRQHandler,Default_Handler - - .weak DMA1_Channel3_IRQHandler - .thumb_set DMA1_Channel3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_IRQHandler - .thumb_set DMA1_Channel4_IRQHandler,Default_Handler - - .weak DMA1_Channel5_IRQHandler - .thumb_set DMA1_Channel5_IRQHandler,Default_Handler - - .weak DMA1_Channel6_IRQHandler - .thumb_set DMA1_Channel6_IRQHandler,Default_Handler - - .weak DMA1_Channel7_IRQHandler - .thumb_set DMA1_Channel7_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak USB_HP_IRQHandler - .thumb_set USB_HP_IRQHandler,Default_Handler - - .weak USB_LP_IRQHandler - .thumb_set USB_LP_IRQHandler,Default_Handler - - .weak DAC_IRQHandler - .thumb_set DAC_IRQHandler,Default_Handler - - .weak COMP_IRQHandler - .thumb_set COMP_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak LCD_IRQHandler - .thumb_set LCD_IRQHandler,Default_Handler - - .weak TIM9_IRQHandler - .thumb_set TIM9_IRQHandler,Default_Handler - - .weak TIM10_IRQHandler - .thumb_set TIM10_IRQHandler,Default_Handler - - .weak TIM11_IRQHandler - .thumb_set TIM11_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak USB_FS_WKUP_IRQHandler - .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak DMA2_Channel1_IRQHandler - .thumb_set DMA2_Channel1_IRQHandler,Default_Handler - - .weak DMA2_Channel2_IRQHandler - .thumb_set DMA2_Channel2_IRQHandler,Default_Handler - - .weak DMA2_Channel3_IRQHandler - .thumb_set DMA2_Channel3_IRQHandler,Default_Handler - - .weak DMA2_Channel4_IRQHandler - .thumb_set DMA2_Channel4_IRQHandler,Default_Handler - - .weak DMA2_Channel5_IRQHandler - .thumb_set DMA2_Channel5_IRQHandler,Default_Handler - - .weak COMP_ACQ_IRQHandler - .thumb_set COMP_ACQ_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/RTC/Debug/Core/Src/main.d b/RTC/Debug/Core/Src/main.d index c8e7916..4c7ac9d 100644 --- a/RTC/Debug/Core/Src/main.d +++ b/RTC/Debug/Core/Src/main.d @@ -1,47 +1,48 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ ../Drivers/CMSIS/Include/cmsis_version.h \ ../Drivers/CMSIS/Include/cmsis_compiler.h \ ../Drivers/CMSIS/Include/cmsis_gcc.h \ ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h ../Core/Inc/main.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: -../Core/Inc/stm32l1xx_hal_conf.h: +../Core/Inc/stm32f4xx_hal_conf.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h: -../Drivers/CMSIS/Include/core_cm3.h: +../Drivers/CMSIS/Include/core_cm4.h: ../Drivers/CMSIS/Include/cmsis_version.h: @@ -51,34 +52,36 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/CMSIS/Include/mpu_armv7.h: -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc.h: -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rtc_ex.h: + +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: diff --git a/RTC/Debug/Core/Src/main.o b/RTC/Debug/Core/Src/main.o index 0ea88be..f9c4c17 100644 Binary files a/RTC/Debug/Core/Src/main.o and b/RTC/Debug/Core/Src/main.o differ diff --git a/RTC/Debug/Core/Src/main.su b/RTC/Debug/Core/Src/main.su index 7dde0de..b6fbf8d 100644 --- a/RTC/Debug/Core/Src/main.su +++ b/RTC/Debug/Core/Src/main.su @@ -1,6 +1,15 @@ -main.c:71:5:main 16 static -main.c:136:6:SystemClock_Config 96 static -main.c:186:13:MX_RTC_Init 8 static -main.c:245:13:MX_USART2_UART_Init 8 static -main.c:278:13:MX_GPIO_Init 48 static -main.c:314:6:Error_Handler 4 static +main.c:81:8:deg_to_rad 32 static +main.c:92:8:rad_to_deg 32 static +main.c:103:5:leap_year_check 16 static +main.c:118:5:calc_day_of_year 40 static +main.c:174:6:calc_sunrise_sunset 168 static +main.c:276:6:calc_tomorrows_date 24 static +main.c:309:6:set_Alarm 24 static +main.c:330:6:transmit_uart 24 static +main.c:342:5:main 200 static +main.c:448:6:SystemClock_Config 104 static +main.c:501:13:MX_RTC_Init 8 static +main.c:561:13:MX_USART2_UART_Init 8 static +main.c:594:13:MX_GPIO_Init 48 static +main.c:630:6:Error_Handler 4 static,ignoring_inline_asm +main.c:646:6:HAL_RTC_AlarmAEventCallback 16 static diff --git a/RTC/Debug/Core/Src/stm32l1xx_hal_msp.d b/RTC/Debug/Core/Src/stm32l1xx_hal_msp.d deleted file mode 100644 index fbd80ec..0000000 --- a/RTC/Debug/Core/Src/stm32l1xx_hal_msp.d +++ /dev/null @@ -1,84 +0,0 @@ -Core/Src/stm32l1xx_hal_msp.o: ../Core/Src/stm32l1xx_hal_msp.c \ - ../Core/Inc/main.h ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Core/Inc/main.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Core/Src/stm32l1xx_hal_msp.o b/RTC/Debug/Core/Src/stm32l1xx_hal_msp.o deleted file mode 100644 index 1970469..0000000 Binary files a/RTC/Debug/Core/Src/stm32l1xx_hal_msp.o and /dev/null differ diff --git a/RTC/Debug/Core/Src/stm32l1xx_hal_msp.su b/RTC/Debug/Core/Src/stm32l1xx_hal_msp.su deleted file mode 100644 index a80b018..0000000 --- a/RTC/Debug/Core/Src/stm32l1xx_hal_msp.su +++ /dev/null @@ -1,5 +0,0 @@ -stm32l1xx_hal_msp.c:64:6:HAL_MspInit 24 static -stm32l1xx_hal_msp.c:89:6:HAL_RTC_MspInit 16 static -stm32l1xx_hal_msp.c:111:6:HAL_RTC_MspDeInit 16 static -stm32l1xx_hal_msp.c:133:6:HAL_UART_MspInit 48 static -stm32l1xx_hal_msp.c:169:6:HAL_UART_MspDeInit 16 static diff --git a/RTC/Debug/Core/Src/stm32l1xx_it.d b/RTC/Debug/Core/Src/stm32l1xx_it.d deleted file mode 100644 index 67a1385..0000000 --- a/RTC/Debug/Core/Src/stm32l1xx_it.d +++ /dev/null @@ -1,87 +0,0 @@ -Core/Src/stm32l1xx_it.o: ../Core/Src/stm32l1xx_it.c ../Core/Inc/main.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h \ - ../Core/Inc/stm32l1xx_it.h - -../Core/Inc/main.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: - -../Core/Inc/stm32l1xx_it.h: diff --git a/RTC/Debug/Core/Src/stm32l1xx_it.o b/RTC/Debug/Core/Src/stm32l1xx_it.o deleted file mode 100644 index 73eb0bd..0000000 Binary files a/RTC/Debug/Core/Src/stm32l1xx_it.o and /dev/null differ diff --git a/RTC/Debug/Core/Src/stm32l1xx_it.su b/RTC/Debug/Core/Src/stm32l1xx_it.su deleted file mode 100644 index e35489c..0000000 --- a/RTC/Debug/Core/Src/stm32l1xx_it.su +++ /dev/null @@ -1,9 +0,0 @@ -stm32l1xx_it.c:70:6:NMI_Handler 4 static -stm32l1xx_it.c:83:6:HardFault_Handler 4 static -stm32l1xx_it.c:98:6:MemManage_Handler 4 static -stm32l1xx_it.c:113:6:BusFault_Handler 4 static -stm32l1xx_it.c:128:6:UsageFault_Handler 4 static -stm32l1xx_it.c:143:6:SVC_Handler 4 static -stm32l1xx_it.c:156:6:DebugMon_Handler 4 static -stm32l1xx_it.c:169:6:PendSV_Handler 4 static -stm32l1xx_it.c:182:6:SysTick_Handler 8 static diff --git a/RTC/Debug/Core/Src/subdir.mk b/RTC/Debug/Core/Src/subdir.mk index d2f7208..b142670 100644 --- a/RTC/Debug/Core/Src/subdir.mk +++ b/RTC/Debug/Core/Src/subdir.mk @@ -5,40 +5,40 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Core/Src/main.c \ -../Core/Src/stm32l1xx_hal_msp.c \ -../Core/Src/stm32l1xx_it.c \ +../Core/Src/stm32f4xx_hal_msp.c \ +../Core/Src/stm32f4xx_it.c \ ../Core/Src/syscalls.c \ ../Core/Src/sysmem.c \ -../Core/Src/system_stm32l1xx.c +../Core/Src/system_stm32f4xx.c OBJS += \ ./Core/Src/main.o \ -./Core/Src/stm32l1xx_hal_msp.o \ -./Core/Src/stm32l1xx_it.o \ +./Core/Src/stm32f4xx_hal_msp.o \ +./Core/Src/stm32f4xx_it.o \ ./Core/Src/syscalls.o \ ./Core/Src/sysmem.o \ -./Core/Src/system_stm32l1xx.o +./Core/Src/system_stm32f4xx.o C_DEPS += \ ./Core/Src/main.d \ -./Core/Src/stm32l1xx_hal_msp.d \ -./Core/Src/stm32l1xx_it.d \ +./Core/Src/stm32f4xx_hal_msp.d \ +./Core/Src/stm32f4xx_it.d \ ./Core/Src/syscalls.d \ ./Core/Src/sysmem.d \ -./Core/Src/system_stm32l1xx.d +./Core/Src/system_stm32f4xx.d # Each subdirectory must supply rules for building sources it contributes Core/Src/main.o: ../Core/Src/main.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Core/Src/stm32l1xx_hal_msp.o: ../Core/Src/stm32l1xx_hal_msp.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32l1xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Core/Src/stm32l1xx_it.o: ../Core/Src/stm32l1xx_it.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32l1xx_it.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/main.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f4xx_hal_msp.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/stm32f4xx_it.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" Core/Src/syscalls.o: ../Core/Src/syscalls.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/syscalls.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" Core/Src/sysmem.o: ../Core/Src/sysmem.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Core/Src/system_stm32l1xx.o: ../Core/Src/system_stm32l1xx.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32l1xx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/sysmem.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" +Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32F401xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Core/Src/system_stm32f4xx.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" diff --git a/RTC/Debug/Core/Src/syscalls.o b/RTC/Debug/Core/Src/syscalls.o index 18ae057..0863e90 100644 Binary files a/RTC/Debug/Core/Src/syscalls.o and b/RTC/Debug/Core/Src/syscalls.o differ diff --git a/RTC/Debug/Core/Src/sysmem.o b/RTC/Debug/Core/Src/sysmem.o index 602c545..3860d6d 100644 Binary files a/RTC/Debug/Core/Src/sysmem.o and b/RTC/Debug/Core/Src/sysmem.o differ diff --git a/RTC/Debug/Core/Src/system_stm32l1xx.d b/RTC/Debug/Core/Src/system_stm32l1xx.d deleted file mode 100644 index f8ec2d6..0000000 --- a/RTC/Debug/Core/Src/system_stm32l1xx.d +++ /dev/null @@ -1,82 +0,0 @@ -Core/Src/system_stm32l1xx.o: ../Core/Src/system_stm32l1xx.c \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Core/Src/system_stm32l1xx.o b/RTC/Debug/Core/Src/system_stm32l1xx.o deleted file mode 100644 index adb25c6..0000000 Binary files a/RTC/Debug/Core/Src/system_stm32l1xx.o and /dev/null differ diff --git a/RTC/Debug/Core/Src/system_stm32l1xx.su b/RTC/Debug/Core/Src/system_stm32l1xx.su deleted file mode 100644 index 2042771..0000000 --- a/RTC/Debug/Core/Src/system_stm32l1xx.su +++ /dev/null @@ -1,2 +0,0 @@ -system_stm32l1xx.c:140:6:SystemInit 4 static -system_stm32l1xx.c:191:6:SystemCoreClockUpdate 32 static diff --git a/RTC/Debug/Core/Startup/startup_stm32l152retx.d b/RTC/Debug/Core/Startup/startup_stm32l152retx.d deleted file mode 100644 index 98bd1c7..0000000 --- a/RTC/Debug/Core/Startup/startup_stm32l152retx.d +++ /dev/null @@ -1,2 +0,0 @@ -Core/Startup/startup_stm32l152retx.o: \ - ../Core/Startup/startup_stm32l152retx.s diff --git a/RTC/Debug/Core/Startup/startup_stm32l152retx.o b/RTC/Debug/Core/Startup/startup_stm32l152retx.o deleted file mode 100644 index d3dda63..0000000 Binary files a/RTC/Debug/Core/Startup/startup_stm32l152retx.o and /dev/null differ diff --git a/RTC/Debug/Core/Startup/subdir.mk b/RTC/Debug/Core/Startup/subdir.mk index 4befb17..24f50d1 100644 --- a/RTC/Debug/Core/Startup/subdir.mk +++ b/RTC/Debug/Core/Startup/subdir.mk @@ -4,16 +4,16 @@ # Add inputs and outputs from these tool invocations to the build variables S_SRCS += \ -../Core/Startup/startup_stm32l152retx.s +../Core/Startup/startup_stm32f401retx.s OBJS += \ -./Core/Startup/startup_stm32l152retx.o +./Core/Startup/startup_stm32f401retx.o S_DEPS += \ -./Core/Startup/startup_stm32l152retx.d +./Core/Startup/startup_stm32f401retx.d # Each subdirectory must supply rules for building sources it contributes -Core/Startup/startup_stm32l152retx.o: ../Core/Startup/startup_stm32l152retx.s - arm-none-eabi-gcc -mcpu=cortex-m3 -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32l152retx.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Core/Startup/startup_stm32f401retx.o: ../Core/Startup/startup_stm32f401retx.s + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -c -x assembler-with-cpp -MMD -MP -MF"Core/Startup/startup_stm32f401retx.d" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@" "$<" diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d deleted file mode 100644 index 045d53a..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o deleted file mode 100644 index fe1e0a3..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su deleted file mode 100644 index 9459f44..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.su +++ /dev/null @@ -1,25 +0,0 @@ -stm32l1xx_hal.c:140:19:HAL_Init 16 static -stm32l1xx_hal.c:173:19:HAL_DeInit 8 static -stm32l1xx_hal.c:196:13:HAL_MspInit 4 static -stm32l1xx_hal.c:207:13:HAL_MspDeInit 4 static -stm32l1xx_hal.c:230:26:HAL_InitTick 24 static -stm32l1xx_hal.c:298:13:HAL_IncTick 4 static -stm32l1xx_hal.c:309:17:HAL_GetTick 4 static -stm32l1xx_hal.c:318:10:HAL_GetTickPrio 4 static -stm32l1xx_hal.c:328:19:HAL_SetTickFreq 24 static -stm32l1xx_hal.c:360:10:HAL_GetTickFreq 4 static -stm32l1xx_hal.c:376:13:HAL_Delay 24 static -stm32l1xx_hal.c:402:13:HAL_SuspendTick 4 static -stm32l1xx_hal.c:418:13:HAL_ResumeTick 4 static -stm32l1xx_hal.c:428:10:HAL_GetHalVersion 4 static -stm32l1xx_hal.c:437:10:HAL_GetREVID 4 static -stm32l1xx_hal.c:446:10:HAL_GetDEVID 4 static -stm32l1xx_hal.c:455:10:HAL_GetUIDw0 4 static -stm32l1xx_hal.c:464:10:HAL_GetUIDw1 4 static -stm32l1xx_hal.c:473:10:HAL_GetUIDw2 4 static -stm32l1xx_hal.c:502:6:HAL_DBGMCU_EnableDBGSleepMode 4 static -stm32l1xx_hal.c:511:6:HAL_DBGMCU_DisableDBGSleepMode 4 static -stm32l1xx_hal.c:520:6:HAL_DBGMCU_EnableDBGStopMode 4 static -stm32l1xx_hal.c:529:6:HAL_DBGMCU_DisableDBGStopMode 4 static -stm32l1xx_hal.c:538:6:HAL_DBGMCU_EnableDBGStandbyMode 4 static -stm32l1xx_hal.c:547:6:HAL_DBGMCU_DisableDBGStandbyMode 4 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d deleted file mode 100644 index 6dae4fc..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o deleted file mode 100644 index 3d56a37..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.su deleted file mode 100644 index 55b5570..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.su +++ /dev/null @@ -1,32 +0,0 @@ -core_cm3.h:1480:22:__NVIC_SetPriorityGrouping 24 static -core_cm3.h:1499:26:__NVIC_GetPriorityGrouping 4 static -core_cm3.h:1511:22:__NVIC_EnableIRQ 16 static -core_cm3.h:1547:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm -core_cm3.h:1566:26:__NVIC_GetPendingIRQ 16 static -core_cm3.h:1585:22:__NVIC_SetPendingIRQ 16 static -core_cm3.h:1600:22:__NVIC_ClearPendingIRQ 16 static -core_cm3.h:1617:26:__NVIC_GetActive 16 static -core_cm3.h:1639:22:__NVIC_SetPriority 16 static -core_cm3.h:1661:26:__NVIC_GetPriority 16 static -core_cm3.h:1686:26:NVIC_EncodePriority 40 static -core_cm3.h:1713:22:NVIC_DecodePriority 40 static -core_cm3.h:1762:34:__NVIC_SystemReset 4 static,ignoring_inline_asm -core_cm3.h:1834:26:SysTick_Config 16 static -stm32l1xx_hal_cortex.c:169:6:HAL_NVIC_SetPriorityGrouping 16 static -stm32l1xx_hal_cortex.c:191:6:HAL_NVIC_SetPriority 32 static -stm32l1xx_hal_cortex.c:213:6:HAL_NVIC_EnableIRQ 16 static -stm32l1xx_hal_cortex.c:229:6:HAL_NVIC_DisableIRQ 16 static -stm32l1xx_hal_cortex.c:242:6:HAL_NVIC_SystemReset 8 static -stm32l1xx_hal_cortex.c:255:10:HAL_SYSTICK_Config 16 static -stm32l1xx_hal_cortex.c:291:6:HAL_MPU_Enable 16 static,ignoring_inline_asm -stm32l1xx_hal_cortex.c:305:6:HAL_MPU_Disable 4 static,ignoring_inline_asm -stm32l1xx_hal_cortex.c:320:6:HAL_MPU_ConfigRegion 16 static -stm32l1xx_hal_cortex.c:364:10:HAL_NVIC_GetPriorityGrouping 8 static -stm32l1xx_hal_cortex.c:391:6:HAL_NVIC_GetPriority 24 static -stm32l1xx_hal_cortex.c:406:6:HAL_NVIC_SetPendingIRQ 16 static -stm32l1xx_hal_cortex.c:421:10:HAL_NVIC_GetPendingIRQ 16 static -stm32l1xx_hal_cortex.c:434:6:HAL_NVIC_ClearPendingIRQ 16 static -stm32l1xx_hal_cortex.c:448:10:HAL_NVIC_GetActive 16 static -stm32l1xx_hal_cortex.c:462:6:HAL_SYSTICK_CLKSourceConfig 16 static -stm32l1xx_hal_cortex.c:480:6:HAL_SYSTICK_IRQHandler 8 static -stm32l1xx_hal_cortex.c:489:13:HAL_SYSTICK_Callback 4 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d deleted file mode 100644 index c9cec93..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o deleted file mode 100644 index a7fe624..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.su deleted file mode 100644 index 563b6c3..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.su +++ /dev/null @@ -1,13 +0,0 @@ -stm32l1xx_hal_dma.c:143:19:HAL_DMA_Init 24 static -stm32l1xx_hal_dma.c:222:19:HAL_DMA_DeInit 16 static -stm32l1xx_hal_dma.c:314:19:HAL_DMA_Start 32 static -stm32l1xx_hal_dma.c:357:19:HAL_DMA_Start_IT 32 static -stm32l1xx_hal_dma.c:412:19:HAL_DMA_Abort 24 static -stm32l1xx_hal_dma.c:453:19:HAL_DMA_Abort_IT 24 static -stm32l1xx_hal_dma.c:498:19:HAL_DMA_PollForTransfer 32 static -stm32l1xx_hal_dma.c:599:6:HAL_DMA_IRQHandler 24 static -stm32l1xx_hal_dma.c:696:19:HAL_DMA_RegisterCallback 32 static -stm32l1xx_hal_dma.c:747:19:HAL_DMA_UnRegisterCallback 24 static -stm32l1xx_hal_dma.c:825:22:HAL_DMA_GetState 16 static -stm32l1xx_hal_dma.c:837:10:HAL_DMA_GetError 16 static -stm32l1xx_hal_dma.c:863:13:DMA_SetConfig 24 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d deleted file mode 100644 index abf31f4..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o deleted file mode 100644 index 930bdae..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.su deleted file mode 100644 index 0e3e728..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.su +++ /dev/null @@ -1,9 +0,0 @@ -stm32l1xx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 32 static -stm32l1xx_hal_exti.c:238:19:HAL_EXTI_GetConfigLine 32 static -stm32l1xx_hal_exti.c:327:19:HAL_EXTI_ClearConfigLine 32 static -stm32l1xx_hal_exti.c:380:19:HAL_EXTI_RegisterCallback 32 static -stm32l1xx_hal_exti.c:405:19:HAL_EXTI_GetHandle 16 static -stm32l1xx_hal_exti.c:445:6:HAL_EXTI_IRQHandler 24 static -stm32l1xx_hal_exti.c:477:10:HAL_EXTI_GetPending 32 static -stm32l1xx_hal_exti.c:506:6:HAL_EXTI_ClearPending 24 static -stm32l1xx_hal_exti.c:527:6:HAL_EXTI_GenerateSWI 24 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d deleted file mode 100644 index 50015c6..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o deleted file mode 100644 index 75bb79b..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.su deleted file mode 100644 index 9ec37c6..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.su +++ /dev/null @@ -1,13 +0,0 @@ -stm32l1xx_hal_flash.c:231:19:HAL_FLASH_Program 32 static -stm32l1xx_hal_flash.c:273:19:HAL_FLASH_Program_IT 32 static -stm32l1xx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 16 static -stm32l1xx_hal_flash.c:419:13:HAL_FLASH_EndOfOperationCallback 16 static -stm32l1xx_hal_flash.c:436:13:HAL_FLASH_OperationErrorCallback 16 static -stm32l1xx_hal_flash.c:469:19:HAL_FLASH_Unlock 4 static -stm32l1xx_hal_flash.c:504:19:HAL_FLASH_Lock 4 static -stm32l1xx_hal_flash.c:516:19:HAL_FLASH_OB_Unlock 4 static -stm32l1xx_hal_flash.c:552:19:HAL_FLASH_OB_Lock 4 static -stm32l1xx_hal_flash.c:565:19:HAL_FLASH_OB_Launch 8 static -stm32l1xx_hal_flash.c:597:10:HAL_FLASH_GetError 4 static -stm32l1xx_hal_flash.c:619:19:FLASH_WaitForLastOperation 24 static -stm32l1xx_hal_flash.c:669:13:FLASH_SetErrorCode 16 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d deleted file mode 100644 index e4a181c..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o deleted file mode 100644 index 65981ba..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su deleted file mode 100644 index 304923f..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.su +++ /dev/null @@ -1,31 +0,0 @@ -stm32l1xx_hal_flash_ex.c:187:19:HAL_FLASHEx_Erase 24 static -stm32l1xx_hal_flash_ex.c:283:19:HAL_FLASHEx_Erase_IT 24 static -stm32l1xx_hal_flash_ex.c:406:19:HAL_FLASHEx_OBProgram 24 static -stm32l1xx_hal_flash_ex.c:488:6:HAL_FLASHEx_OBGetConfig 16 static -stm32l1xx_hal_flash_ex.c:542:19:HAL_FLASHEx_AdvOBProgram 24 static -stm32l1xx_hal_flash_ex.c:599:6:HAL_FLASHEx_AdvOBGetConfig 16 static -stm32l1xx_hal_flash_ex.c:751:19:HAL_FLASHEx_DATAEEPROM_Unlock 4 static -stm32l1xx_hal_flash_ex.c:770:19:HAL_FLASHEx_DATAEEPROM_Lock 4 static -stm32l1xx_hal_flash_ex.c:790:19:HAL_FLASHEx_DATAEEPROM_Erase 24 static -stm32l1xx_hal_flash_ex.c:848:21:HAL_FLASHEx_DATAEEPROM_Program 32 static -stm32l1xx_hal_flash_ex.c:913:6:HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram 4 static -stm32l1xx_hal_flash_ex.c:922:6:HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram 4 static -stm32l1xx_hal_flash_ex.c:958:26:FLASH_OB_RDPConfig 32 static -stm32l1xx_hal_flash_ex.c:1022:26:FLASH_OB_BORConfig 32 static -stm32l1xx_hal_flash_ex.c:1060:16:FLASH_OB_GetUser 4 static -stm32l1xx_hal_flash_ex.c:1074:16:FLASH_OB_GetRDP 16 static -stm32l1xx_hal_flash_ex.c:1092:16:FLASH_OB_GetBOR 4 static -stm32l1xx_hal_flash_ex.c:1106:26:FLASH_OB_WRPConfig 24 static -stm32l1xx_hal_flash_ex.c:1237:13:FLASH_OB_WRPConfigWRP1OrPCROP1 32 static -stm32l1xx_hal_flash_ex.c:1283:13:FLASH_OB_WRPConfigWRP2OrPCROP2 32 static -stm32l1xx_hal_flash_ex.c:1329:13:FLASH_OB_WRPConfigWRP3 32 static -stm32l1xx_hal_flash_ex.c:1374:13:FLASH_OB_WRPConfigWRP4 32 static -stm32l1xx_hal_flash_ex.c:1424:26:FLASH_OB_UserConfig 32 static -stm32l1xx_hal_flash_ex.c:1477:26:FLASH_OB_BootConfig 32 static -stm32l1xx_hal_flash_ex.c:1526:26:FLASH_DATAEEPROM_FastProgramByte 24 static -stm32l1xx_hal_flash_ex.c:1586:26:FLASH_DATAEEPROM_FastProgramHalfWord 24 static -stm32l1xx_hal_flash_ex.c:1654:26:FLASH_DATAEEPROM_FastProgramWord 24 static -stm32l1xx_hal_flash_ex.c:1685:26:FLASH_DATAEEPROM_ProgramByte 24 static -stm32l1xx_hal_flash_ex.c:1739:26:FLASH_DATAEEPROM_ProgramHalfWord 24 static -stm32l1xx_hal_flash_ex.c:1800:26:FLASH_DATAEEPROM_ProgramWord 24 static -stm32l1xx_hal_flash_ex.c:1845:6:FLASH_PageErase 16 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d deleted file mode 100644 index 19506b8..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o deleted file mode 100644 index 1964939..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.su deleted file mode 100644 index 75f6bc9..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.su +++ /dev/null @@ -1,10 +0,0 @@ -stm32l1xx_hal_flash_ramfunc.c:115:30:HAL_FLASHEx_EnableRunPowerDown 4 static -stm32l1xx_hal_flash_ramfunc.c:128:30:HAL_FLASHEx_DisableRunPowerDown 4 static -stm32l1xx_hal_flash_ramfunc.c:165:30:HAL_FLASHEx_EraseParallelPage 24 static -stm32l1xx_hal_flash_ramfunc.c:226:30:HAL_FLASHEx_ProgramParallelHalfPage 48 static,ignoring_inline_asm -stm32l1xx_hal_flash_ramfunc.c:304:30:HAL_FLASHEx_HalfPageProgram 40 static,ignoring_inline_asm -stm32l1xx_hal_flash_ramfunc.c:396:30:HAL_FLASHEx_GetError 16 static -stm32l1xx_hal_flash_ramfunc.c:428:30:HAL_FLASHEx_DATAEEPROM_EraseDoubleWord 32 static,ignoring_inline_asm -stm32l1xx_hal_flash_ramfunc.c:488:30:HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord 48 static,ignoring_inline_asm -stm32l1xx_hal_flash_ramfunc.c:588:37:FLASHRAM_WaitForLastOperation 16 static -stm32l1xx_hal_flash_ramfunc.c:542:37:FLASHRAM_SetErrorCode 16 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d deleted file mode 100644 index 052f24b..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o deleted file mode 100644 index 770326a..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.su deleted file mode 100644 index 5ec9aa1..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.su +++ /dev/null @@ -1,8 +0,0 @@ -stm32l1xx_hal_gpio.c:178:6:HAL_GPIO_Init 32 static -stm32l1xx_hal_gpio.c:304:6:HAL_GPIO_DeInit 32 static -stm32l1xx_hal_gpio.c:384:15:HAL_GPIO_ReadPin 24 static -stm32l1xx_hal_gpio.c:416:6:HAL_GPIO_WritePin 16 static -stm32l1xx_hal_gpio.c:438:6:HAL_GPIO_TogglePin 24 static -stm32l1xx_hal_gpio.c:472:19:HAL_GPIO_LockPin 24 static -stm32l1xx_hal_gpio.c:507:6:HAL_GPIO_EXTI_IRQHandler 16 static -stm32l1xx_hal_gpio.c:522:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d deleted file mode 100644 index 2f9713c..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o deleted file mode 100644 index 8611bca..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.su deleted file mode 100644 index 7e0addd..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.su +++ /dev/null @@ -1,17 +0,0 @@ -stm32l1xx_hal_pwr.c:85:6:HAL_PWR_DeInit 4 static -stm32l1xx_hal_pwr.c:98:6:HAL_PWR_EnableBkUpAccess 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:111:6:HAL_PWR_DisableBkUpAccess 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:339:6:HAL_PWR_ConfigPVD 16 static -stm32l1xx_hal_pwr.c:381:6:HAL_PWR_EnablePVD 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:391:6:HAL_PWR_DisablePVD 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:406:6:HAL_PWR_EnableWakeUpPin 24 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:423:6:HAL_PWR_DisableWakeUpPin 24 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:446:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:492:6:HAL_PWR_EnterSTOPMode 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:532:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm -stm32l1xx_hal_pwr.c:557:6:HAL_PWR_EnableSleepOnExit 4 static -stm32l1xx_hal_pwr.c:570:6:HAL_PWR_DisableSleepOnExit 4 static -stm32l1xx_hal_pwr.c:583:6:HAL_PWR_EnableSEVOnPend 4 static -stm32l1xx_hal_pwr.c:596:6:HAL_PWR_DisableSEVOnPend 4 static -stm32l1xx_hal_pwr.c:609:6:HAL_PWR_PVD_IRQHandler 8 static -stm32l1xx_hal_pwr.c:626:13:HAL_PWR_PVDCallback 4 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d deleted file mode 100644 index 94d8bd5..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o deleted file mode 100644 index a5f7449..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.su deleted file mode 100644 index 44c4424..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.su +++ /dev/null @@ -1,7 +0,0 @@ -stm32l1xx_hal_pwr_ex.c:66:10:HAL_PWREx_GetVoltageRange 4 static -stm32l1xx_hal_pwr_ex.c:79:6:HAL_PWREx_EnableFastWakeUp 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr_ex.c:89:6:HAL_PWREx_DisableFastWakeUp 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr_ex.c:99:6:HAL_PWREx_EnableUltraLowPower 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr_ex.c:109:6:HAL_PWREx_DisableUltraLowPower 16 static,ignoring_inline_asm -stm32l1xx_hal_pwr_ex.c:125:6:HAL_PWREx_EnableLowPowerRunMode 24 static,ignoring_inline_asm -stm32l1xx_hal_pwr_ex.c:136:19:HAL_PWREx_DisableLowPowerRunMode 24 static,ignoring_inline_asm diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d deleted file mode 100644 index a6c4bb3..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o deleted file mode 100644 index 3eaae76..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.su deleted file mode 100644 index a390e6d..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.su +++ /dev/null @@ -1,15 +0,0 @@ -stm32l1xx_hal_rcc.c:228:19:HAL_RCC_DeInit 16 static -stm32l1xx_hal_rcc.c:324:19:HAL_RCC_OscConfig 40 static -stm32l1xx_hal_rcc.c:799:19:HAL_RCC_ClockConfig 24 static -stm32l1xx_hal_rcc.c:1005:6:HAL_RCC_MCOConfig 48 static -stm32l1xx_hal_rcc.c:1039:6:HAL_RCC_EnableCSS 4 static -stm32l1xx_hal_rcc.c:1048:6:HAL_RCC_DisableCSS 4 static -stm32l1xx_hal_rcc.c:1083:10:HAL_RCC_GetSysClockFreq 48 static -stm32l1xx_hal_rcc.c:1139:10:HAL_RCC_GetHCLKFreq 4 static -stm32l1xx_hal_rcc.c:1150:10:HAL_RCC_GetPCLK1Freq 8 static -stm32l1xx_hal_rcc.c:1162:10:HAL_RCC_GetPCLK2Freq 8 static -stm32l1xx_hal_rcc.c:1175:6:HAL_RCC_GetOscConfig 16 static -stm32l1xx_hal_rcc.c:1271:6:HAL_RCC_GetClockConfig 16 static -stm32l1xx_hal_rcc.c:1301:6:HAL_RCC_NMI_IRQHandler 8 static -stm32l1xx_hal_rcc.c:1318:13:HAL_RCC_CSSCallback 4 static -stm32l1xx_hal_rcc.c:1343:26:RCC_SetFlashLatencyFromMSIRange 32 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d deleted file mode 100644 index bc8b97f..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o deleted file mode 100644 index c95c012..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.su deleted file mode 100644 index 1b1c4d1..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.su +++ /dev/null @@ -1,8 +0,0 @@ -stm32l1xx_hal_rcc_ex.c:92:19:HAL_RCCEx_PeriphCLKConfig 32 static -stm32l1xx_hal_rcc_ex.c:221:6:HAL_RCCEx_GetPeriphCLKConfig 24 static -stm32l1xx_hal_rcc_ex.c:258:10:HAL_RCCEx_GetPeriphCLKFreq 24 static -stm32l1xx_hal_rcc_ex.c:350:6:HAL_RCCEx_EnableLSECSS 4 static -stm32l1xx_hal_rcc_ex.c:363:6:HAL_RCCEx_DisableLSECSS 4 static -stm32l1xx_hal_rcc_ex.c:377:6:HAL_RCCEx_EnableLSECSS_IT 4 static -stm32l1xx_hal_rcc_ex.c:394:6:HAL_RCCEx_LSECSS_IRQHandler 8 static -stm32l1xx_hal_rcc_ex.c:411:13:HAL_RCCEx_LSECSS_Callback 4 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.d deleted file mode 100644 index d2c442d..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o deleted file mode 100644 index d5658a1..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.su deleted file mode 100644 index f496e13..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.su +++ /dev/null @@ -1,20 +0,0 @@ -stm32l1xx_hal_rtc.c:243:19:HAL_RTC_Init 16 static -stm32l1xx_hal_rtc.c:349:19:HAL_RTC_DeInit 24 static -stm32l1xx_hal_rtc.c:670:13:HAL_RTC_MspInit 16 static -stm32l1xx_hal_rtc.c:685:13:HAL_RTC_MspDeInit 16 static -stm32l1xx_hal_rtc.c:723:19:HAL_RTC_SetTime 40 static -stm32l1xx_hal_rtc.c:854:19:HAL_RTC_GetTime 32 static -stm32l1xx_hal_rtc.c:900:19:HAL_RTC_SetDate 40 static -stm32l1xx_hal_rtc.c:1006:19:HAL_RTC_GetDate 32 static -stm32l1xx_hal_rtc.c:1060:19:HAL_RTC_SetAlarm 48 static -stm32l1xx_hal_rtc.c:1253:19:HAL_RTC_SetAlarm_IT 48 static -stm32l1xx_hal_rtc.c:1446:19:HAL_RTC_DeactivateAlarm 24 static -stm32l1xx_hal_rtc.c:1540:19:HAL_RTC_GetAlarm 32 static -stm32l1xx_hal_rtc.c:1599:6:HAL_RTC_AlarmIRQHandler 16 static -stm32l1xx_hal_rtc.c:1648:13:HAL_RTC_AlarmAEventCallback 16 static -stm32l1xx_hal_rtc.c:1664:19:HAL_RTC_PollForAlarmAEvent 24 static -stm32l1xx_hal_rtc.c:1723:19:HAL_RTC_WaitForSynchro 24 static -stm32l1xx_hal_rtc.c:1773:21:HAL_RTC_GetState 16 static -stm32l1xx_hal_rtc.c:1796:19:RTC_EnterInitMode 24 static -stm32l1xx_hal_rtc.c:1826:9:RTC_ByteToBcd2 24 static -stm32l1xx_hal_rtc.c:1845:9:RTC_Bcd2ToByte 24 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.d deleted file mode 100644 index 2c5b8b3..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o deleted file mode 100644 index 8536608..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.su deleted file mode 100644 index c63ef76..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.su +++ /dev/null @@ -1,37 +0,0 @@ -stm32l1xx_hal_rtc_ex.c:128:19:HAL_RTCEx_SetTimeStamp 24 static -stm32l1xx_hal_rtc_ex.c:178:19:HAL_RTCEx_SetTimeStamp_IT 24 static -stm32l1xx_hal_rtc_ex.c:227:19:HAL_RTCEx_DeactivateTimeStamp 24 static -stm32l1xx_hal_rtc_ex.c:270:19:HAL_RTCEx_GetTimeStamp 32 static -stm32l1xx_hal_rtc_ex.c:323:19:HAL_RTCEx_SetTamper 24 static -stm32l1xx_hal_rtc_ex.c:384:19:HAL_RTCEx_SetTamper_IT 24 static -stm32l1xx_hal_rtc_ex.c:452:19:HAL_RTCEx_DeactivateTamper 16 static -stm32l1xx_hal_rtc_ex.c:477:6:HAL_RTCEx_TamperTimeStampIRQHandler 16 static -stm32l1xx_hal_rtc_ex.c:565:13:HAL_RTCEx_TimeStampEventCallback 16 static -stm32l1xx_hal_rtc_ex.c:580:13:HAL_RTCEx_Tamper1EventCallback 16 static -stm32l1xx_hal_rtc_ex.c:596:13:HAL_RTCEx_Tamper2EventCallback 16 static -stm32l1xx_hal_rtc_ex.c:611:13:HAL_RTCEx_Tamper3EventCallback 16 static -stm32l1xx_hal_rtc_ex.c:628:19:HAL_RTCEx_PollForTimeStampEvent 24 static -stm32l1xx_hal_rtc_ex.c:667:19:HAL_RTCEx_PollForTamper1Event 24 static -stm32l1xx_hal_rtc_ex.c:700:19:HAL_RTCEx_PollForTamper2Event 24 static -stm32l1xx_hal_rtc_ex.c:732:19:HAL_RTCEx_PollForTamper3Event 24 static -stm32l1xx_hal_rtc_ex.c:784:19:HAL_RTCEx_SetWakeUpTimer 32 static -stm32l1xx_hal_rtc_ex.c:874:19:HAL_RTCEx_SetWakeUpTimer_IT 32 static -stm32l1xx_hal_rtc_ex.c:974:19:HAL_RTCEx_DeactivateWakeUpTimer 24 static -stm32l1xx_hal_rtc_ex.c:1026:10:HAL_RTCEx_GetWakeUpTimer 16 static -stm32l1xx_hal_rtc_ex.c:1037:6:HAL_RTCEx_WakeUpTimerIRQHandler 16 static -stm32l1xx_hal_rtc_ex.c:1066:13:HAL_RTCEx_WakeUpTimerEventCallback 16 static -stm32l1xx_hal_rtc_ex.c:1082:19:HAL_RTCEx_PollForWakeUpTimerEvent 24 static -stm32l1xx_hal_rtc_ex.c:1148:6:HAL_RTCEx_BKUPWrite 32 static -stm32l1xx_hal_rtc_ex.c:1170:10:HAL_RTCEx_BKUPRead 24 static -stm32l1xx_hal_rtc_ex.c:1201:19:HAL_RTCEx_SetCoarseCalib 24 static -stm32l1xx_hal_rtc_ex.c:1259:19:HAL_RTCEx_DeactivateCoarseCalib 16 static -stm32l1xx_hal_rtc_ex.c:1324:19:HAL_RTCEx_SetSmoothCalib 32 static -stm32l1xx_hal_rtc_ex.c:1392:19:HAL_RTCEx_SetSynchroShift 32 static -stm32l1xx_hal_rtc_ex.c:1485:19:HAL_RTCEx_SetCalibrationOutPut 16 static -stm32l1xx_hal_rtc_ex.c:1535:19:HAL_RTCEx_DeactivateCalibrationOutPut 16 static -stm32l1xx_hal_rtc_ex.c:1564:19:HAL_RTCEx_SetRefClock 16 static -stm32l1xx_hal_rtc_ex.c:1613:19:HAL_RTCEx_DeactivateRefClock 16 static -stm32l1xx_hal_rtc_ex.c:1665:19:HAL_RTCEx_EnableBypassShadow 16 static -stm32l1xx_hal_rtc_ex.c:1697:19:HAL_RTCEx_DisableBypassShadow 16 static -stm32l1xx_hal_rtc_ex.c:1747:13:HAL_RTCEx_AlarmBEventCallback 16 static -stm32l1xx_hal_rtc_ex.c:1763:19:HAL_RTCEx_PollForAlarmBEvent 24 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d deleted file mode 100644 index 354a9b9..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o deleted file mode 100644 index 2814a36..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.su deleted file mode 100644 index e69de29..0000000 diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d deleted file mode 100644 index 5208f56..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o deleted file mode 100644 index d66a839..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.su deleted file mode 100644 index e69de29..0000000 diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d deleted file mode 100644 index 2130805..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d +++ /dev/null @@ -1,83 +0,0 @@ -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o: \ - ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h \ - ../Core/Inc/stm32l1xx_hal_conf.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h \ - ../Drivers/CMSIS/Include/core_cm3.h \ - ../Drivers/CMSIS/Include/cmsis_version.h \ - ../Drivers/CMSIS/Include/cmsis_compiler.h \ - ../Drivers/CMSIS/Include/cmsis_gcc.h \ - ../Drivers/CMSIS/Include/mpu_armv7.h \ - ../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h \ - ../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h: - -../Core/Inc/stm32l1xx_hal_conf.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h: - -../Drivers/CMSIS/Include/core_cm3.h: - -../Drivers/CMSIS/Include/cmsis_version.h: - -../Drivers/CMSIS/Include/cmsis_compiler.h: - -../Drivers/CMSIS/Include/cmsis_gcc.h: - -../Drivers/CMSIS/Include/mpu_armv7.h: - -../Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h: - -../Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h: diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o deleted file mode 100644 index 799a2a6..0000000 Binary files a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o and /dev/null differ diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.su b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.su deleted file mode 100644 index c919f87..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.su +++ /dev/null @@ -1,55 +0,0 @@ -stm32l1xx_hal_uart.c:313:19:HAL_UART_Init 16 static -stm32l1xx_hal_uart.c:388:19:HAL_HalfDuplex_Init 16 static -stm32l1xx_hal_uart.c:461:19:HAL_LIN_Init 16 static -stm32l1xx_hal_uart.c:542:19:HAL_MultiProcessor_Init 24 static -stm32l1xx_hal_uart.c:619:19:HAL_UART_DeInit 16 static -stm32l1xx_hal_uart.c:663:13:HAL_UART_MspInit 16 static -stm32l1xx_hal_uart.c:678:13:HAL_UART_MspDeInit 16 static -stm32l1xx_hal_uart.c:1018:19:HAL_UART_Transmit 40 static -stm32l1xx_hal_uart.c:1104:19:HAL_UART_Receive 40 static -stm32l1xx_hal_uart.c:1195:19:HAL_UART_Transmit_IT 24 static -stm32l1xx_hal_uart.c:1240:19:HAL_UART_Receive_IT 24 static -stm32l1xx_hal_uart.c:1291:19:HAL_UART_Transmit_DMA 32 static -stm32l1xx_hal_uart.c:1359:19:HAL_UART_Receive_DMA 32 static -stm32l1xx_hal_uart.c:1426:19:HAL_UART_DMAPause 24 static -stm32l1xx_hal_uart.c:1463:19:HAL_UART_DMAResume 24 static -stm32l1xx_hal_uart.c:1499:19:HAL_UART_DMAStop 24 static -stm32l1xx_hal_uart.c:1551:19:HAL_UART_Abort 16 static -stm32l1xx_hal_uart.c:1633:19:HAL_UART_AbortTransmit 16 static -stm32l1xx_hal_uart.c:1684:19:HAL_UART_AbortReceive 16 static -stm32l1xx_hal_uart.c:1738:19:HAL_UART_Abort_IT 24 static -stm32l1xx_hal_uart.c:1866:19:HAL_UART_AbortTransmit_IT 16 static -stm32l1xx_hal_uart.c:1943:19:HAL_UART_AbortReceive_IT 16 static -stm32l1xx_hal_uart.c:2013:6:HAL_UART_IRQHandler 40 static -stm32l1xx_hal_uart.c:2159:13:HAL_UART_TxCpltCallback 16 static -stm32l1xx_hal_uart.c:2174:13:HAL_UART_TxHalfCpltCallback 16 static -stm32l1xx_hal_uart.c:2189:13:HAL_UART_RxCpltCallback 16 static -stm32l1xx_hal_uart.c:2204:13:HAL_UART_RxHalfCpltCallback 16 static -stm32l1xx_hal_uart.c:2219:13:HAL_UART_ErrorCallback 16 static -stm32l1xx_hal_uart.c:2233:13:HAL_UART_AbortCpltCallback 16 static -stm32l1xx_hal_uart.c:2248:13:HAL_UART_AbortTransmitCpltCallback 16 static -stm32l1xx_hal_uart.c:2263:13:HAL_UART_AbortReceiveCpltCallback 16 static -stm32l1xx_hal_uart.c:2302:19:HAL_LIN_SendBreak 16 static -stm32l1xx_hal_uart.c:2329:19:HAL_MultiProcessor_EnterMuteMode 16 static -stm32l1xx_hal_uart.c:2356:19:HAL_MultiProcessor_ExitMuteMode 16 static -stm32l1xx_hal_uart.c:2383:19:HAL_HalfDuplex_EnableTransmitter 24 static -stm32l1xx_hal_uart.c:2418:19:HAL_HalfDuplex_EnableReceiver 24 static -stm32l1xx_hal_uart.c:2475:23:HAL_UART_GetState 24 static -stm32l1xx_hal_uart.c:2490:10:HAL_UART_GetError 16 static -stm32l1xx_hal_uart.c:2534:13:UART_DMATransmitCplt 24 static -stm32l1xx_hal_uart.c:2569:13:UART_DMATxHalfCplt 24 static -stm32l1xx_hal_uart.c:2588:13:UART_DMAReceiveCplt 24 static -stm32l1xx_hal_uart.c:2622:13:UART_DMARxHalfCplt 24 static -stm32l1xx_hal_uart.c:2641:13:UART_DMAError 24 static -stm32l1xx_hal_uart.c:2682:26:UART_WaitOnFlagUntilTimeout 24 static -stm32l1xx_hal_uart.c:2714:13:UART_EndTxTransfer 16 static -stm32l1xx_hal_uart.c:2728:13:UART_EndRxTransfer 16 static -stm32l1xx_hal_uart.c:2745:13:UART_DMAAbortOnError 24 static -stm32l1xx_hal_uart.c:2769:13:UART_DMATxAbortCallback 24 static -stm32l1xx_hal_uart.c:2814:13:UART_DMARxAbortCallback 24 static -stm32l1xx_hal_uart.c:2859:13:UART_DMATxOnlyAbortCallback 24 static -stm32l1xx_hal_uart.c:2887:13:UART_DMARxOnlyAbortCallback 24 static -stm32l1xx_hal_uart.c:2912:26:UART_Transmit_IT 24 static -stm32l1xx_hal_uart.c:2959:26:UART_EndTransmit_IT 16 static -stm32l1xx_hal_uart.c:2984:26:UART_Receive_IT 24 static -stm32l1xx_hal_uart.c:3055:13:UART_SetConfig 24 static diff --git a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk b/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk deleted file mode 100644 index db4e74d..0000000 --- a/RTC/Debug/Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk +++ /dev/null @@ -1,99 +0,0 @@ -################################################################################ -# Automatically-generated file. Do not edit! -################################################################################ - -# Add inputs and outputs from these tool invocations to the build variables -C_SRCS += \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c \ -../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c - -OBJS += \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - -C_DEPS += \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d \ -./Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d - - -# Each subdirectory must supply rules for building sources it contributes -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" -Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o: ../Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c - arm-none-eabi-gcc "$<" -mcpu=cortex-m3 -std=gnu11 -g3 -DUSE_HAL_DRIVER -DSTM32L152xE -DDEBUG -c -I../Core/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc -I../Drivers/STM32L1xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32L1xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -MMD -MP -MF"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.d" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" - diff --git a/RTC/Debug/RTC.bin b/RTC/Debug/RTC.bin index b91fdc9..2a3e1f5 100644 Binary files a/RTC/Debug/RTC.bin and b/RTC/Debug/RTC.bin differ diff --git a/RTC/Debug/RTC.elf b/RTC/Debug/RTC.elf index b7afc44..51eeb78 100644 Binary files a/RTC/Debug/RTC.elf and b/RTC/Debug/RTC.elf differ diff --git a/RTC/Debug/RTC.list b/RTC/Debug/RTC.list index a1a07d5..7b73d21 100644 --- a/RTC/Debug/RTC.list +++ b/RTC/Debug/RTC.list @@ -3,6384 +3,12178 @@ RTC.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn - 0 .isr_vector 0000013c 08000000 08000000 00010000 2**0 + 0 .isr_vector 00000194 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 000024a8 0800013c 0800013c 0001013c 2**2 + 1 .text 00005de4 08000198 08000198 00010198 2**3 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000024 080025e4 080025e4 000125e4 2**2 + 2 .rodata 00000290 08005f80 08005f80 00015f80 2**3 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08002608 08002608 0002000c 2**0 + 3 .ARM.extab 00000000 08006210 08006210 00020088 2**0 CONTENTS - 4 .ARM 00000008 08002608 08002608 00012608 2**2 + 4 .ARM 00000008 08006210 08006210 00016210 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08002610 08002610 0002000c 2**0 + 5 .preinit_array 00000000 08006218 08006218 00020088 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08002610 08002610 00012610 2**2 + 6 .init_array 00000004 08006218 08006218 00016218 2**2 CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08002614 08002614 00012614 2**2 + 7 .fini_array 00000004 0800621c 0800621c 0001621c 2**2 CONTENTS, ALLOC, LOAD, DATA - 8 .data 0000000c 20000000 08002618 00020000 2**2 + 8 .data 00000088 20000000 08006220 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00000098 2000000c 08002624 0002000c 2**2 + 9 .bss 000000c0 20000088 080062a8 00020088 2**2 ALLOC - 10 ._user_heap_stack 00000604 200000a4 08002624 000200a4 2**0 + 10 ._user_heap_stack 00000600 20000148 080062a8 00020148 2**0 ALLOC - 11 .ARM.attributes 00000029 00000000 00000000 0002000c 2**0 + 11 .ARM.attributes 00000030 00000000 00000000 00020088 2**0 CONTENTS, READONLY - 12 .debug_info 00006999 00000000 00000000 00020035 2**0 + 12 .debug_info 000098e6 00000000 00000000 000200b8 2**0 CONTENTS, READONLY, DEBUGGING - 13 .debug_abbrev 00001431 00000000 00000000 000269ce 2**0 + 13 .debug_abbrev 0000196e 00000000 00000000 0002999e 2**0 CONTENTS, READONLY, DEBUGGING - 14 .debug_aranges 000006f8 00000000 00000000 00027e00 2**3 + 14 .debug_aranges 00000910 00000000 00000000 0002b310 2**3 CONTENTS, READONLY, DEBUGGING - 15 .debug_ranges 00000640 00000000 00000000 000284f8 2**3 + 15 .debug_ranges 00000838 00000000 00000000 0002bc20 2**3 CONTENTS, READONLY, DEBUGGING - 16 .debug_macro 00015151 00000000 00000000 00028b38 2**0 + 16 .debug_macro 00015f3a 00000000 00000000 0002c458 2**0 CONTENTS, READONLY, DEBUGGING - 17 .debug_line 000062c4 00000000 00000000 0003dc89 2**0 + 17 .debug_line 00007bf1 00000000 00000000 00042392 2**0 CONTENTS, READONLY, DEBUGGING - 18 .debug_str 000859c4 00000000 00000000 00043f4d 2**0 + 18 .debug_str 00089db1 00000000 00000000 00049f83 2**0 CONTENTS, READONLY, DEBUGGING - 19 .comment 0000007b 00000000 00000000 000c9911 2**0 + 19 .comment 0000007b 00000000 00000000 000d3d34 2**0 CONTENTS, READONLY - 20 .debug_frame 00001b48 00000000 00000000 000c998c 2**2 + 20 .debug_frame 000029c4 00000000 00000000 000d3db0 2**2 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: -0800013c <__do_global_dtors_aux>: - 800013c: b510 push {r4, lr} - 800013e: 4c05 ldr r4, [pc, #20] ; (8000154 <__do_global_dtors_aux+0x18>) - 8000140: 7823 ldrb r3, [r4, #0] - 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16> - 8000144: 4b04 ldr r3, [pc, #16] ; (8000158 <__do_global_dtors_aux+0x1c>) - 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12> - 8000148: 4804 ldr r0, [pc, #16] ; (800015c <__do_global_dtors_aux+0x20>) - 800014a: f3af 8000 nop.w - 800014e: 2301 movs r3, #1 - 8000150: 7023 strb r3, [r4, #0] - 8000152: bd10 pop {r4, pc} - 8000154: 2000000c .word 0x2000000c - 8000158: 00000000 .word 0x00000000 - 800015c: 080025cc .word 0x080025cc +08000198 <__do_global_dtors_aux>: + 8000198: b510 push {r4, lr} + 800019a: 4c05 ldr r4, [pc, #20] ; (80001b0 <__do_global_dtors_aux+0x18>) + 800019c: 7823 ldrb r3, [r4, #0] + 800019e: b933 cbnz r3, 80001ae <__do_global_dtors_aux+0x16> + 80001a0: 4b04 ldr r3, [pc, #16] ; (80001b4 <__do_global_dtors_aux+0x1c>) + 80001a2: b113 cbz r3, 80001aa <__do_global_dtors_aux+0x12> + 80001a4: 4804 ldr r0, [pc, #16] ; (80001b8 <__do_global_dtors_aux+0x20>) + 80001a6: f3af 8000 nop.w + 80001aa: 2301 movs r3, #1 + 80001ac: 7023 strb r3, [r4, #0] + 80001ae: bd10 pop {r4, pc} + 80001b0: 20000088 .word 0x20000088 + 80001b4: 00000000 .word 0x00000000 + 80001b8: 08005f64 .word 0x08005f64 -08000160 : - 8000160: b508 push {r3, lr} - 8000162: 4b03 ldr r3, [pc, #12] ; (8000170 ) - 8000164: b11b cbz r3, 800016e - 8000166: 4903 ldr r1, [pc, #12] ; (8000174 ) - 8000168: 4803 ldr r0, [pc, #12] ; (8000178 ) - 800016a: f3af 8000 nop.w - 800016e: bd08 pop {r3, pc} - 8000170: 00000000 .word 0x00000000 - 8000174: 20000010 .word 0x20000010 - 8000178: 080025cc .word 0x080025cc +080001bc : + 80001bc: b508 push {r3, lr} + 80001be: 4b03 ldr r3, [pc, #12] ; (80001cc ) + 80001c0: b11b cbz r3, 80001ca + 80001c2: 4903 ldr r1, [pc, #12] ; (80001d0 ) + 80001c4: 4803 ldr r0, [pc, #12] ; (80001d4 ) + 80001c6: f3af 8000 nop.w + 80001ca: bd08 pop {r3, pc} + 80001cc: 00000000 .word 0x00000000 + 80001d0: 2000008c .word 0x2000008c + 80001d4: 08005f64 .word 0x08005f64 -0800017c <__aeabi_uldivmod>: - 800017c: b953 cbnz r3, 8000194 <__aeabi_uldivmod+0x18> - 800017e: b94a cbnz r2, 8000194 <__aeabi_uldivmod+0x18> - 8000180: 2900 cmp r1, #0 - 8000182: bf08 it eq - 8000184: 2800 cmpeq r0, #0 - 8000186: bf1c itt ne - 8000188: f04f 31ff movne.w r1, #4294967295 - 800018c: f04f 30ff movne.w r0, #4294967295 - 8000190: f000 b974 b.w 800047c <__aeabi_idiv0> - 8000194: f1ad 0c08 sub.w ip, sp, #8 - 8000198: e96d ce04 strd ip, lr, [sp, #-16]! - 800019c: f000 f806 bl 80001ac <__udivmoddi4> - 80001a0: f8dd e004 ldr.w lr, [sp, #4] - 80001a4: e9dd 2302 ldrd r2, r3, [sp, #8] - 80001a8: b004 add sp, #16 - 80001aa: 4770 bx lr +080001d8 : + 80001d8: 4603 mov r3, r0 + 80001da: f813 2b01 ldrb.w r2, [r3], #1 + 80001de: 2a00 cmp r2, #0 + 80001e0: d1fb bne.n 80001da + 80001e2: 1a18 subs r0, r3, r0 + 80001e4: 3801 subs r0, #1 + 80001e6: 4770 bx lr -080001ac <__udivmoddi4>: - 80001ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} - 80001b0: 468c mov ip, r1 - 80001b2: 4604 mov r4, r0 - 80001b4: 9e08 ldr r6, [sp, #32] - 80001b6: 2b00 cmp r3, #0 - 80001b8: d14b bne.n 8000252 <__udivmoddi4+0xa6> - 80001ba: 428a cmp r2, r1 - 80001bc: 4615 mov r5, r2 - 80001be: d967 bls.n 8000290 <__udivmoddi4+0xe4> - 80001c0: fab2 f282 clz r2, r2 - 80001c4: b14a cbz r2, 80001da <__udivmoddi4+0x2e> - 80001c6: f1c2 0720 rsb r7, r2, #32 - 80001ca: fa01 f302 lsl.w r3, r1, r2 - 80001ce: fa20 f707 lsr.w r7, r0, r7 - 80001d2: 4095 lsls r5, r2 - 80001d4: ea47 0c03 orr.w ip, r7, r3 - 80001d8: 4094 lsls r4, r2 - 80001da: ea4f 4e15 mov.w lr, r5, lsr #16 - 80001de: fbbc f7fe udiv r7, ip, lr - 80001e2: fa1f f885 uxth.w r8, r5 - 80001e6: fb0e c317 mls r3, lr, r7, ip - 80001ea: fb07 f908 mul.w r9, r7, r8 - 80001ee: 0c21 lsrs r1, r4, #16 - 80001f0: ea41 4303 orr.w r3, r1, r3, lsl #16 - 80001f4: 4599 cmp r9, r3 - 80001f6: d909 bls.n 800020c <__udivmoddi4+0x60> - 80001f8: 18eb adds r3, r5, r3 - 80001fa: f107 31ff add.w r1, r7, #4294967295 - 80001fe: f080 811c bcs.w 800043a <__udivmoddi4+0x28e> - 8000202: 4599 cmp r9, r3 - 8000204: f240 8119 bls.w 800043a <__udivmoddi4+0x28e> - 8000208: 3f02 subs r7, #2 - 800020a: 442b add r3, r5 - 800020c: eba3 0309 sub.w r3, r3, r9 - 8000210: fbb3 f0fe udiv r0, r3, lr - 8000214: fb0e 3310 mls r3, lr, r0, r3 - 8000218: fb00 f108 mul.w r1, r0, r8 - 800021c: b2a4 uxth r4, r4 - 800021e: ea44 4403 orr.w r4, r4, r3, lsl #16 - 8000222: 42a1 cmp r1, r4 - 8000224: d909 bls.n 800023a <__udivmoddi4+0x8e> - 8000226: 192c adds r4, r5, r4 - 8000228: f100 33ff add.w r3, r0, #4294967295 - 800022c: f080 8107 bcs.w 800043e <__udivmoddi4+0x292> - 8000230: 42a1 cmp r1, r4 - 8000232: f240 8104 bls.w 800043e <__udivmoddi4+0x292> - 8000236: 3802 subs r0, #2 - 8000238: 442c add r4, r5 - 800023a: ea40 4007 orr.w r0, r0, r7, lsl #16 - 800023e: 2700 movs r7, #0 - 8000240: 1a64 subs r4, r4, r1 - 8000242: b11e cbz r6, 800024c <__udivmoddi4+0xa0> - 8000244: 2300 movs r3, #0 - 8000246: 40d4 lsrs r4, r2 - 8000248: e9c6 4300 strd r4, r3, [r6] - 800024c: 4639 mov r1, r7 - 800024e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 8000252: 428b cmp r3, r1 - 8000254: d909 bls.n 800026a <__udivmoddi4+0xbe> - 8000256: 2e00 cmp r6, #0 - 8000258: f000 80ec beq.w 8000434 <__udivmoddi4+0x288> - 800025c: 2700 movs r7, #0 - 800025e: e9c6 0100 strd r0, r1, [r6] - 8000262: 4638 mov r0, r7 - 8000264: 4639 mov r1, r7 - 8000266: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} - 800026a: fab3 f783 clz r7, r3 - 800026e: 2f00 cmp r7, #0 - 8000270: d148 bne.n 8000304 <__udivmoddi4+0x158> - 8000272: 428b cmp r3, r1 - 8000274: d302 bcc.n 800027c <__udivmoddi4+0xd0> - 8000276: 4282 cmp r2, r0 - 8000278: f200 80fb bhi.w 8000472 <__udivmoddi4+0x2c6> - 800027c: 1a84 subs r4, r0, r2 - 800027e: eb61 0303 sbc.w r3, r1, r3 - 8000282: 2001 movs r0, #1 - 8000284: 469c mov ip, r3 - 8000286: 2e00 cmp r6, #0 - 8000288: d0e0 beq.n 800024c <__udivmoddi4+0xa0> - 800028a: e9c6 4c00 strd r4, ip, [r6] - 800028e: e7dd b.n 800024c <__udivmoddi4+0xa0> - 8000290: b902 cbnz r2, 8000294 <__udivmoddi4+0xe8> - 8000292: deff udf #255 ; 0xff - 8000294: fab2 f282 clz r2, r2 - 8000298: 2a00 cmp r2, #0 - 800029a: f040 808f bne.w 80003bc <__udivmoddi4+0x210> - 800029e: 2701 movs r7, #1 - 80002a0: 1b49 subs r1, r1, r5 - 80002a2: ea4f 4815 mov.w r8, r5, lsr #16 - 80002a6: fa1f f985 uxth.w r9, r5 - 80002aa: fbb1 fef8 udiv lr, r1, r8 - 80002ae: fb08 111e mls r1, r8, lr, r1 - 80002b2: fb09 f00e mul.w r0, r9, lr - 80002b6: ea4f 4c14 mov.w ip, r4, lsr #16 - 80002ba: ea4c 4301 orr.w r3, ip, r1, lsl #16 - 80002be: 4298 cmp r0, r3 - 80002c0: d907 bls.n 80002d2 <__udivmoddi4+0x126> - 80002c2: 18eb adds r3, r5, r3 - 80002c4: f10e 31ff add.w r1, lr, #4294967295 - 80002c8: d202 bcs.n 80002d0 <__udivmoddi4+0x124> - 80002ca: 4298 cmp r0, r3 - 80002cc: f200 80cd bhi.w 800046a <__udivmoddi4+0x2be> - 80002d0: 468e mov lr, r1 - 80002d2: 1a1b subs r3, r3, r0 - 80002d4: fbb3 f0f8 udiv r0, r3, r8 - 80002d8: fb08 3310 mls r3, r8, r0, r3 - 80002dc: fb09 f900 mul.w r9, r9, r0 - 80002e0: b2a4 uxth r4, r4 - 80002e2: ea44 4403 orr.w r4, r4, r3, lsl #16 - 80002e6: 45a1 cmp r9, r4 - 80002e8: d907 bls.n 80002fa <__udivmoddi4+0x14e> - 80002ea: 192c adds r4, r5, r4 - 80002ec: f100 33ff add.w r3, r0, #4294967295 - 80002f0: d202 bcs.n 80002f8 <__udivmoddi4+0x14c> - 80002f2: 45a1 cmp r9, r4 - 80002f4: f200 80b6 bhi.w 8000464 <__udivmoddi4+0x2b8> - 80002f8: 4618 mov r0, r3 - 80002fa: eba4 0409 sub.w r4, r4, r9 - 80002fe: ea40 400e orr.w r0, r0, lr, lsl #16 - 8000302: e79e b.n 8000242 <__udivmoddi4+0x96> - 8000304: f1c7 0520 rsb r5, r7, #32 - 8000308: 40bb lsls r3, r7 - 800030a: fa22 fc05 lsr.w ip, r2, r5 - 800030e: ea4c 0c03 orr.w ip, ip, r3 - 8000312: fa21 f405 lsr.w r4, r1, r5 - 8000316: ea4f 4e1c mov.w lr, ip, lsr #16 - 800031a: fbb4 f9fe udiv r9, r4, lr - 800031e: fa1f f88c uxth.w r8, ip - 8000322: fb0e 4419 mls r4, lr, r9, r4 - 8000326: fa20 f305 lsr.w r3, r0, r5 - 800032a: 40b9 lsls r1, r7 - 800032c: fb09 fa08 mul.w sl, r9, r8 - 8000330: 4319 orrs r1, r3 - 8000332: 0c0b lsrs r3, r1, #16 - 8000334: ea43 4404 orr.w r4, r3, r4, lsl #16 - 8000338: 45a2 cmp sl, r4 - 800033a: fa02 f207 lsl.w r2, r2, r7 - 800033e: fa00 f307 lsl.w r3, r0, r7 - 8000342: d90b bls.n 800035c <__udivmoddi4+0x1b0> - 8000344: eb1c 0404 adds.w r4, ip, r4 - 8000348: f109 30ff add.w r0, r9, #4294967295 - 800034c: f080 8088 bcs.w 8000460 <__udivmoddi4+0x2b4> - 8000350: 45a2 cmp sl, r4 - 8000352: f240 8085 bls.w 8000460 <__udivmoddi4+0x2b4> - 8000356: f1a9 0902 sub.w r9, r9, #2 - 800035a: 4464 add r4, ip - 800035c: eba4 040a sub.w r4, r4, sl - 8000360: fbb4 f0fe udiv r0, r4, lr - 8000364: fb0e 4410 mls r4, lr, r0, r4 - 8000368: fb00 fa08 mul.w sl, r0, r8 - 800036c: b289 uxth r1, r1 - 800036e: ea41 4404 orr.w r4, r1, r4, lsl #16 - 8000372: 45a2 cmp sl, r4 - 8000374: d908 bls.n 8000388 <__udivmoddi4+0x1dc> - 8000376: eb1c 0404 adds.w r4, ip, r4 - 800037a: f100 31ff add.w r1, r0, #4294967295 - 800037e: d26b bcs.n 8000458 <__udivmoddi4+0x2ac> - 8000380: 45a2 cmp sl, r4 - 8000382: d969 bls.n 8000458 <__udivmoddi4+0x2ac> - 8000384: 3802 subs r0, #2 - 8000386: 4464 add r4, ip - 8000388: ea40 4009 orr.w r0, r0, r9, lsl #16 - 800038c: fba0 8902 umull r8, r9, r0, r2 - 8000390: eba4 040a sub.w r4, r4, sl - 8000394: 454c cmp r4, r9 - 8000396: 4641 mov r1, r8 - 8000398: 46ce mov lr, r9 - 800039a: d354 bcc.n 8000446 <__udivmoddi4+0x29a> - 800039c: d051 beq.n 8000442 <__udivmoddi4+0x296> - 800039e: 2e00 cmp r6, #0 - 80003a0: d069 beq.n 8000476 <__udivmoddi4+0x2ca> - 80003a2: 1a5a subs r2, r3, r1 - 80003a4: eb64 040e sbc.w r4, r4, lr - 80003a8: fa04 f505 lsl.w r5, r4, r5 - 80003ac: fa22 f307 lsr.w r3, r2, r7 - 80003b0: 40fc lsrs r4, r7 - 80003b2: 431d orrs r5, r3 - 80003b4: e9c6 5400 strd r5, r4, [r6] - 80003b8: 2700 movs r7, #0 - 80003ba: e747 b.n 800024c <__udivmoddi4+0xa0> - 80003bc: 4095 lsls r5, r2 - 80003be: f1c2 0320 rsb r3, r2, #32 - 80003c2: fa21 f003 lsr.w r0, r1, r3 - 80003c6: ea4f 4815 mov.w r8, r5, lsr #16 - 80003ca: fbb0 f7f8 udiv r7, r0, r8 - 80003ce: fa1f f985 uxth.w r9, r5 - 80003d2: fb08 0017 mls r0, r8, r7, r0 - 80003d6: fa24 f303 lsr.w r3, r4, r3 - 80003da: 4091 lsls r1, r2 - 80003dc: fb07 fc09 mul.w ip, r7, r9 - 80003e0: 430b orrs r3, r1 - 80003e2: 0c19 lsrs r1, r3, #16 - 80003e4: ea41 4100 orr.w r1, r1, r0, lsl #16 - 80003e8: 458c cmp ip, r1 - 80003ea: fa04 f402 lsl.w r4, r4, r2 - 80003ee: d907 bls.n 8000400 <__udivmoddi4+0x254> - 80003f0: 1869 adds r1, r5, r1 - 80003f2: f107 30ff add.w r0, r7, #4294967295 - 80003f6: d231 bcs.n 800045c <__udivmoddi4+0x2b0> - 80003f8: 458c cmp ip, r1 - 80003fa: d92f bls.n 800045c <__udivmoddi4+0x2b0> - 80003fc: 3f02 subs r7, #2 - 80003fe: 4429 add r1, r5 - 8000400: eba1 010c sub.w r1, r1, ip - 8000404: fbb1 f0f8 udiv r0, r1, r8 - 8000408: fb08 1c10 mls ip, r8, r0, r1 - 800040c: fb00 fe09 mul.w lr, r0, r9 - 8000410: b299 uxth r1, r3 - 8000412: ea41 410c orr.w r1, r1, ip, lsl #16 - 8000416: 458e cmp lr, r1 - 8000418: d907 bls.n 800042a <__udivmoddi4+0x27e> - 800041a: 1869 adds r1, r5, r1 - 800041c: f100 33ff add.w r3, r0, #4294967295 - 8000420: d218 bcs.n 8000454 <__udivmoddi4+0x2a8> - 8000422: 458e cmp lr, r1 - 8000424: d916 bls.n 8000454 <__udivmoddi4+0x2a8> - 8000426: 3802 subs r0, #2 - 8000428: 4429 add r1, r5 - 800042a: eba1 010e sub.w r1, r1, lr - 800042e: ea40 4707 orr.w r7, r0, r7, lsl #16 - 8000432: e73a b.n 80002aa <__udivmoddi4+0xfe> - 8000434: 4637 mov r7, r6 - 8000436: 4630 mov r0, r6 - 8000438: e708 b.n 800024c <__udivmoddi4+0xa0> - 800043a: 460f mov r7, r1 - 800043c: e6e6 b.n 800020c <__udivmoddi4+0x60> - 800043e: 4618 mov r0, r3 - 8000440: e6fb b.n 800023a <__udivmoddi4+0x8e> - 8000442: 4543 cmp r3, r8 - 8000444: d2ab bcs.n 800039e <__udivmoddi4+0x1f2> - 8000446: ebb8 0102 subs.w r1, r8, r2 - 800044a: eb69 020c sbc.w r2, r9, ip - 800044e: 3801 subs r0, #1 - 8000450: 4696 mov lr, r2 - 8000452: e7a4 b.n 800039e <__udivmoddi4+0x1f2> - 8000454: 4618 mov r0, r3 - 8000456: e7e8 b.n 800042a <__udivmoddi4+0x27e> - 8000458: 4608 mov r0, r1 - 800045a: e795 b.n 8000388 <__udivmoddi4+0x1dc> - 800045c: 4607 mov r7, r0 - 800045e: e7cf b.n 8000400 <__udivmoddi4+0x254> - 8000460: 4681 mov r9, r0 - 8000462: e77b b.n 800035c <__udivmoddi4+0x1b0> - 8000464: 3802 subs r0, #2 - 8000466: 442c add r4, r5 - 8000468: e747 b.n 80002fa <__udivmoddi4+0x14e> - 800046a: f1ae 0e02 sub.w lr, lr, #2 - 800046e: 442b add r3, r5 - 8000470: e72f b.n 80002d2 <__udivmoddi4+0x126> - 8000472: 4638 mov r0, r7 - 8000474: e707 b.n 8000286 <__udivmoddi4+0xda> - 8000476: 4637 mov r7, r6 - 8000478: e6e8 b.n 800024c <__udivmoddi4+0xa0> - 800047a: bf00 nop +080001e8 <__aeabi_drsub>: + 80001e8: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 + 80001ec: e002 b.n 80001f4 <__adddf3> + 80001ee: bf00 nop -0800047c <__aeabi_idiv0>: - 800047c: 4770 bx lr - 800047e: bf00 nop +080001f0 <__aeabi_dsub>: + 80001f0: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 -08000480
: +080001f4 <__adddf3>: + 80001f4: b530 push {r4, r5, lr} + 80001f6: ea4f 0441 mov.w r4, r1, lsl #1 + 80001fa: ea4f 0543 mov.w r5, r3, lsl #1 + 80001fe: ea94 0f05 teq r4, r5 + 8000202: bf08 it eq + 8000204: ea90 0f02 teqeq r0, r2 + 8000208: bf1f itttt ne + 800020a: ea54 0c00 orrsne.w ip, r4, r0 + 800020e: ea55 0c02 orrsne.w ip, r5, r2 + 8000212: ea7f 5c64 mvnsne.w ip, r4, asr #21 + 8000216: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 800021a: f000 80e2 beq.w 80003e2 <__adddf3+0x1ee> + 800021e: ea4f 5454 mov.w r4, r4, lsr #21 + 8000222: ebd4 5555 rsbs r5, r4, r5, lsr #21 + 8000226: bfb8 it lt + 8000228: 426d neglt r5, r5 + 800022a: dd0c ble.n 8000246 <__adddf3+0x52> + 800022c: 442c add r4, r5 + 800022e: ea80 0202 eor.w r2, r0, r2 + 8000232: ea81 0303 eor.w r3, r1, r3 + 8000236: ea82 0000 eor.w r0, r2, r0 + 800023a: ea83 0101 eor.w r1, r3, r1 + 800023e: ea80 0202 eor.w r2, r0, r2 + 8000242: ea81 0303 eor.w r3, r1, r3 + 8000246: 2d36 cmp r5, #54 ; 0x36 + 8000248: bf88 it hi + 800024a: bd30 pophi {r4, r5, pc} + 800024c: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000250: ea4f 3101 mov.w r1, r1, lsl #12 + 8000254: f44f 1c80 mov.w ip, #1048576 ; 0x100000 + 8000258: ea4c 3111 orr.w r1, ip, r1, lsr #12 + 800025c: d002 beq.n 8000264 <__adddf3+0x70> + 800025e: 4240 negs r0, r0 + 8000260: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 8000264: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 + 8000268: ea4f 3303 mov.w r3, r3, lsl #12 + 800026c: ea4c 3313 orr.w r3, ip, r3, lsr #12 + 8000270: d002 beq.n 8000278 <__adddf3+0x84> + 8000272: 4252 negs r2, r2 + 8000274: eb63 0343 sbc.w r3, r3, r3, lsl #1 + 8000278: ea94 0f05 teq r4, r5 + 800027c: f000 80a7 beq.w 80003ce <__adddf3+0x1da> + 8000280: f1a4 0401 sub.w r4, r4, #1 + 8000284: f1d5 0e20 rsbs lr, r5, #32 + 8000288: db0d blt.n 80002a6 <__adddf3+0xb2> + 800028a: fa02 fc0e lsl.w ip, r2, lr + 800028e: fa22 f205 lsr.w r2, r2, r5 + 8000292: 1880 adds r0, r0, r2 + 8000294: f141 0100 adc.w r1, r1, #0 + 8000298: fa03 f20e lsl.w r2, r3, lr + 800029c: 1880 adds r0, r0, r2 + 800029e: fa43 f305 asr.w r3, r3, r5 + 80002a2: 4159 adcs r1, r3 + 80002a4: e00e b.n 80002c4 <__adddf3+0xd0> + 80002a6: f1a5 0520 sub.w r5, r5, #32 + 80002aa: f10e 0e20 add.w lr, lr, #32 + 80002ae: 2a01 cmp r2, #1 + 80002b0: fa03 fc0e lsl.w ip, r3, lr + 80002b4: bf28 it cs + 80002b6: f04c 0c02 orrcs.w ip, ip, #2 + 80002ba: fa43 f305 asr.w r3, r3, r5 + 80002be: 18c0 adds r0, r0, r3 + 80002c0: eb51 71e3 adcs.w r1, r1, r3, asr #31 + 80002c4: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80002c8: d507 bpl.n 80002da <__adddf3+0xe6> + 80002ca: f04f 0e00 mov.w lr, #0 + 80002ce: f1dc 0c00 rsbs ip, ip, #0 + 80002d2: eb7e 0000 sbcs.w r0, lr, r0 + 80002d6: eb6e 0101 sbc.w r1, lr, r1 + 80002da: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 + 80002de: d31b bcc.n 8000318 <__adddf3+0x124> + 80002e0: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 + 80002e4: d30c bcc.n 8000300 <__adddf3+0x10c> + 80002e6: 0849 lsrs r1, r1, #1 + 80002e8: ea5f 0030 movs.w r0, r0, rrx + 80002ec: ea4f 0c3c mov.w ip, ip, rrx + 80002f0: f104 0401 add.w r4, r4, #1 + 80002f4: ea4f 5244 mov.w r2, r4, lsl #21 + 80002f8: f512 0f80 cmn.w r2, #4194304 ; 0x400000 + 80002fc: f080 809a bcs.w 8000434 <__adddf3+0x240> + 8000300: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 + 8000304: bf08 it eq + 8000306: ea5f 0c50 movseq.w ip, r0, lsr #1 + 800030a: f150 0000 adcs.w r0, r0, #0 + 800030e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8000312: ea41 0105 orr.w r1, r1, r5 + 8000316: bd30 pop {r4, r5, pc} + 8000318: ea5f 0c4c movs.w ip, ip, lsl #1 + 800031c: 4140 adcs r0, r0 + 800031e: eb41 0101 adc.w r1, r1, r1 + 8000322: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000326: f1a4 0401 sub.w r4, r4, #1 + 800032a: d1e9 bne.n 8000300 <__adddf3+0x10c> + 800032c: f091 0f00 teq r1, #0 + 8000330: bf04 itt eq + 8000332: 4601 moveq r1, r0 + 8000334: 2000 moveq r0, #0 + 8000336: fab1 f381 clz r3, r1 + 800033a: bf08 it eq + 800033c: 3320 addeq r3, #32 + 800033e: f1a3 030b sub.w r3, r3, #11 + 8000342: f1b3 0220 subs.w r2, r3, #32 + 8000346: da0c bge.n 8000362 <__adddf3+0x16e> + 8000348: 320c adds r2, #12 + 800034a: dd08 ble.n 800035e <__adddf3+0x16a> + 800034c: f102 0c14 add.w ip, r2, #20 + 8000350: f1c2 020c rsb r2, r2, #12 + 8000354: fa01 f00c lsl.w r0, r1, ip + 8000358: fa21 f102 lsr.w r1, r1, r2 + 800035c: e00c b.n 8000378 <__adddf3+0x184> + 800035e: f102 0214 add.w r2, r2, #20 + 8000362: bfd8 it le + 8000364: f1c2 0c20 rsble ip, r2, #32 + 8000368: fa01 f102 lsl.w r1, r1, r2 + 800036c: fa20 fc0c lsr.w ip, r0, ip + 8000370: bfdc itt le + 8000372: ea41 010c orrle.w r1, r1, ip + 8000376: 4090 lslle r0, r2 + 8000378: 1ae4 subs r4, r4, r3 + 800037a: bfa2 ittt ge + 800037c: eb01 5104 addge.w r1, r1, r4, lsl #20 + 8000380: 4329 orrge r1, r5 + 8000382: bd30 popge {r4, r5, pc} + 8000384: ea6f 0404 mvn.w r4, r4 + 8000388: 3c1f subs r4, #31 + 800038a: da1c bge.n 80003c6 <__adddf3+0x1d2> + 800038c: 340c adds r4, #12 + 800038e: dc0e bgt.n 80003ae <__adddf3+0x1ba> + 8000390: f104 0414 add.w r4, r4, #20 + 8000394: f1c4 0220 rsb r2, r4, #32 + 8000398: fa20 f004 lsr.w r0, r0, r4 + 800039c: fa01 f302 lsl.w r3, r1, r2 + 80003a0: ea40 0003 orr.w r0, r0, r3 + 80003a4: fa21 f304 lsr.w r3, r1, r4 + 80003a8: ea45 0103 orr.w r1, r5, r3 + 80003ac: bd30 pop {r4, r5, pc} + 80003ae: f1c4 040c rsb r4, r4, #12 + 80003b2: f1c4 0220 rsb r2, r4, #32 + 80003b6: fa20 f002 lsr.w r0, r0, r2 + 80003ba: fa01 f304 lsl.w r3, r1, r4 + 80003be: ea40 0003 orr.w r0, r0, r3 + 80003c2: 4629 mov r1, r5 + 80003c4: bd30 pop {r4, r5, pc} + 80003c6: fa21 f004 lsr.w r0, r1, r4 + 80003ca: 4629 mov r1, r5 + 80003cc: bd30 pop {r4, r5, pc} + 80003ce: f094 0f00 teq r4, #0 + 80003d2: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 + 80003d6: bf06 itte eq + 80003d8: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 + 80003dc: 3401 addeq r4, #1 + 80003de: 3d01 subne r5, #1 + 80003e0: e74e b.n 8000280 <__adddf3+0x8c> + 80003e2: ea7f 5c64 mvns.w ip, r4, asr #21 + 80003e6: bf18 it ne + 80003e8: ea7f 5c65 mvnsne.w ip, r5, asr #21 + 80003ec: d029 beq.n 8000442 <__adddf3+0x24e> + 80003ee: ea94 0f05 teq r4, r5 + 80003f2: bf08 it eq + 80003f4: ea90 0f02 teqeq r0, r2 + 80003f8: d005 beq.n 8000406 <__adddf3+0x212> + 80003fa: ea54 0c00 orrs.w ip, r4, r0 + 80003fe: bf04 itt eq + 8000400: 4619 moveq r1, r3 + 8000402: 4610 moveq r0, r2 + 8000404: bd30 pop {r4, r5, pc} + 8000406: ea91 0f03 teq r1, r3 + 800040a: bf1e ittt ne + 800040c: 2100 movne r1, #0 + 800040e: 2000 movne r0, #0 + 8000410: bd30 popne {r4, r5, pc} + 8000412: ea5f 5c54 movs.w ip, r4, lsr #21 + 8000416: d105 bne.n 8000424 <__adddf3+0x230> + 8000418: 0040 lsls r0, r0, #1 + 800041a: 4149 adcs r1, r1 + 800041c: bf28 it cs + 800041e: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 + 8000422: bd30 pop {r4, r5, pc} + 8000424: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 + 8000428: bf3c itt cc + 800042a: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 + 800042e: bd30 popcc {r4, r5, pc} + 8000430: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 8000434: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 + 8000438: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 800043c: f04f 0000 mov.w r0, #0 + 8000440: bd30 pop {r4, r5, pc} + 8000442: ea7f 5c64 mvns.w ip, r4, asr #21 + 8000446: bf1a itte ne + 8000448: 4619 movne r1, r3 + 800044a: 4610 movne r0, r2 + 800044c: ea7f 5c65 mvnseq.w ip, r5, asr #21 + 8000450: bf1c itt ne + 8000452: 460b movne r3, r1 + 8000454: 4602 movne r2, r0 + 8000456: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 800045a: bf06 itte eq + 800045c: ea52 3503 orrseq.w r5, r2, r3, lsl #12 + 8000460: ea91 0f03 teqeq r1, r3 + 8000464: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 + 8000468: bd30 pop {r4, r5, pc} + 800046a: bf00 nop + +0800046c <__aeabi_ui2d>: + 800046c: f090 0f00 teq r0, #0 + 8000470: bf04 itt eq + 8000472: 2100 moveq r1, #0 + 8000474: 4770 bxeq lr + 8000476: b530 push {r4, r5, lr} + 8000478: f44f 6480 mov.w r4, #1024 ; 0x400 + 800047c: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000480: f04f 0500 mov.w r5, #0 + 8000484: f04f 0100 mov.w r1, #0 + 8000488: e750 b.n 800032c <__adddf3+0x138> + 800048a: bf00 nop + +0800048c <__aeabi_i2d>: + 800048c: f090 0f00 teq r0, #0 + 8000490: bf04 itt eq + 8000492: 2100 moveq r1, #0 + 8000494: 4770 bxeq lr + 8000496: b530 push {r4, r5, lr} + 8000498: f44f 6480 mov.w r4, #1024 ; 0x400 + 800049c: f104 0432 add.w r4, r4, #50 ; 0x32 + 80004a0: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 + 80004a4: bf48 it mi + 80004a6: 4240 negmi r0, r0 + 80004a8: f04f 0100 mov.w r1, #0 + 80004ac: e73e b.n 800032c <__adddf3+0x138> + 80004ae: bf00 nop + +080004b0 <__aeabi_f2d>: + 80004b0: 0042 lsls r2, r0, #1 + 80004b2: ea4f 01e2 mov.w r1, r2, asr #3 + 80004b6: ea4f 0131 mov.w r1, r1, rrx + 80004ba: ea4f 7002 mov.w r0, r2, lsl #28 + 80004be: bf1f itttt ne + 80004c0: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 + 80004c4: f093 4f7f teqne r3, #4278190080 ; 0xff000000 + 80004c8: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 + 80004cc: 4770 bxne lr + 80004ce: f032 427f bics.w r2, r2, #4278190080 ; 0xff000000 + 80004d2: bf08 it eq + 80004d4: 4770 bxeq lr + 80004d6: f093 4f7f teq r3, #4278190080 ; 0xff000000 + 80004da: bf04 itt eq + 80004dc: f441 2100 orreq.w r1, r1, #524288 ; 0x80000 + 80004e0: 4770 bxeq lr + 80004e2: b530 push {r4, r5, lr} + 80004e4: f44f 7460 mov.w r4, #896 ; 0x380 + 80004e8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 + 80004ec: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 80004f0: e71c b.n 800032c <__adddf3+0x138> + 80004f2: bf00 nop + +080004f4 <__aeabi_ul2d>: + 80004f4: ea50 0201 orrs.w r2, r0, r1 + 80004f8: bf08 it eq + 80004fa: 4770 bxeq lr + 80004fc: b530 push {r4, r5, lr} + 80004fe: f04f 0500 mov.w r5, #0 + 8000502: e00a b.n 800051a <__aeabi_l2d+0x16> + +08000504 <__aeabi_l2d>: + 8000504: ea50 0201 orrs.w r2, r0, r1 + 8000508: bf08 it eq + 800050a: 4770 bxeq lr + 800050c: b530 push {r4, r5, lr} + 800050e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 + 8000512: d502 bpl.n 800051a <__aeabi_l2d+0x16> + 8000514: 4240 negs r0, r0 + 8000516: eb61 0141 sbc.w r1, r1, r1, lsl #1 + 800051a: f44f 6480 mov.w r4, #1024 ; 0x400 + 800051e: f104 0432 add.w r4, r4, #50 ; 0x32 + 8000522: ea5f 5c91 movs.w ip, r1, lsr #22 + 8000526: f43f aed8 beq.w 80002da <__adddf3+0xe6> + 800052a: f04f 0203 mov.w r2, #3 + 800052e: ea5f 0cdc movs.w ip, ip, lsr #3 + 8000532: bf18 it ne + 8000534: 3203 addne r2, #3 + 8000536: ea5f 0cdc movs.w ip, ip, lsr #3 + 800053a: bf18 it ne + 800053c: 3203 addne r2, #3 + 800053e: eb02 02dc add.w r2, r2, ip, lsr #3 + 8000542: f1c2 0320 rsb r3, r2, #32 + 8000546: fa00 fc03 lsl.w ip, r0, r3 + 800054a: fa20 f002 lsr.w r0, r0, r2 + 800054e: fa01 fe03 lsl.w lr, r1, r3 + 8000552: ea40 000e orr.w r0, r0, lr + 8000556: fa21 f102 lsr.w r1, r1, r2 + 800055a: 4414 add r4, r2 + 800055c: e6bd b.n 80002da <__adddf3+0xe6> + 800055e: bf00 nop + +08000560 <__aeabi_dmul>: + 8000560: b570 push {r4, r5, r6, lr} + 8000562: f04f 0cff mov.w ip, #255 ; 0xff + 8000566: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 800056a: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 800056e: bf1d ittte ne + 8000570: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 8000574: ea94 0f0c teqne r4, ip + 8000578: ea95 0f0c teqne r5, ip + 800057c: f000 f8de bleq 800073c <__aeabi_dmul+0x1dc> + 8000580: 442c add r4, r5 + 8000582: ea81 0603 eor.w r6, r1, r3 + 8000586: ea21 514c bic.w r1, r1, ip, lsl #21 + 800058a: ea23 534c bic.w r3, r3, ip, lsl #21 + 800058e: ea50 3501 orrs.w r5, r0, r1, lsl #12 + 8000592: bf18 it ne + 8000594: ea52 3503 orrsne.w r5, r2, r3, lsl #12 + 8000598: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 800059c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 80005a0: d038 beq.n 8000614 <__aeabi_dmul+0xb4> + 80005a2: fba0 ce02 umull ip, lr, r0, r2 + 80005a6: f04f 0500 mov.w r5, #0 + 80005aa: fbe1 e502 umlal lr, r5, r1, r2 + 80005ae: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 + 80005b2: fbe0 e503 umlal lr, r5, r0, r3 + 80005b6: f04f 0600 mov.w r6, #0 + 80005ba: fbe1 5603 umlal r5, r6, r1, r3 + 80005be: f09c 0f00 teq ip, #0 + 80005c2: bf18 it ne + 80005c4: f04e 0e01 orrne.w lr, lr, #1 + 80005c8: f1a4 04ff sub.w r4, r4, #255 ; 0xff + 80005cc: f5b6 7f00 cmp.w r6, #512 ; 0x200 + 80005d0: f564 7440 sbc.w r4, r4, #768 ; 0x300 + 80005d4: d204 bcs.n 80005e0 <__aeabi_dmul+0x80> + 80005d6: ea5f 0e4e movs.w lr, lr, lsl #1 + 80005da: 416d adcs r5, r5 + 80005dc: eb46 0606 adc.w r6, r6, r6 + 80005e0: ea42 21c6 orr.w r1, r2, r6, lsl #11 + 80005e4: ea41 5155 orr.w r1, r1, r5, lsr #21 + 80005e8: ea4f 20c5 mov.w r0, r5, lsl #11 + 80005ec: ea40 505e orr.w r0, r0, lr, lsr #21 + 80005f0: ea4f 2ece mov.w lr, lr, lsl #11 + 80005f4: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 80005f8: bf88 it hi + 80005fa: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 80005fe: d81e bhi.n 800063e <__aeabi_dmul+0xde> + 8000600: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 + 8000604: bf08 it eq + 8000606: ea5f 0e50 movseq.w lr, r0, lsr #1 + 800060a: f150 0000 adcs.w r0, r0, #0 + 800060e: eb41 5104 adc.w r1, r1, r4, lsl #20 + 8000612: bd70 pop {r4, r5, r6, pc} + 8000614: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 + 8000618: ea46 0101 orr.w r1, r6, r1 + 800061c: ea40 0002 orr.w r0, r0, r2 + 8000620: ea81 0103 eor.w r1, r1, r3 + 8000624: ebb4 045c subs.w r4, r4, ip, lsr #1 + 8000628: bfc2 ittt gt + 800062a: ebd4 050c rsbsgt r5, r4, ip + 800062e: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 8000632: bd70 popgt {r4, r5, r6, pc} + 8000634: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000638: f04f 0e00 mov.w lr, #0 + 800063c: 3c01 subs r4, #1 + 800063e: f300 80ab bgt.w 8000798 <__aeabi_dmul+0x238> + 8000642: f114 0f36 cmn.w r4, #54 ; 0x36 + 8000646: bfde ittt le + 8000648: 2000 movle r0, #0 + 800064a: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 + 800064e: bd70 pople {r4, r5, r6, pc} + 8000650: f1c4 0400 rsb r4, r4, #0 + 8000654: 3c20 subs r4, #32 + 8000656: da35 bge.n 80006c4 <__aeabi_dmul+0x164> + 8000658: 340c adds r4, #12 + 800065a: dc1b bgt.n 8000694 <__aeabi_dmul+0x134> + 800065c: f104 0414 add.w r4, r4, #20 + 8000660: f1c4 0520 rsb r5, r4, #32 + 8000664: fa00 f305 lsl.w r3, r0, r5 + 8000668: fa20 f004 lsr.w r0, r0, r4 + 800066c: fa01 f205 lsl.w r2, r1, r5 + 8000670: ea40 0002 orr.w r0, r0, r2 + 8000674: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 + 8000678: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 800067c: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 8000680: fa21 f604 lsr.w r6, r1, r4 + 8000684: eb42 0106 adc.w r1, r2, r6 + 8000688: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 800068c: bf08 it eq + 800068e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 8000692: bd70 pop {r4, r5, r6, pc} + 8000694: f1c4 040c rsb r4, r4, #12 + 8000698: f1c4 0520 rsb r5, r4, #32 + 800069c: fa00 f304 lsl.w r3, r0, r4 + 80006a0: fa20 f005 lsr.w r0, r0, r5 + 80006a4: fa01 f204 lsl.w r2, r1, r4 + 80006a8: ea40 0002 orr.w r0, r0, r2 + 80006ac: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80006b0: eb10 70d3 adds.w r0, r0, r3, lsr #31 + 80006b4: f141 0100 adc.w r1, r1, #0 + 80006b8: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80006bc: bf08 it eq + 80006be: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80006c2: bd70 pop {r4, r5, r6, pc} + 80006c4: f1c4 0520 rsb r5, r4, #32 + 80006c8: fa00 f205 lsl.w r2, r0, r5 + 80006cc: ea4e 0e02 orr.w lr, lr, r2 + 80006d0: fa20 f304 lsr.w r3, r0, r4 + 80006d4: fa01 f205 lsl.w r2, r1, r5 + 80006d8: ea43 0302 orr.w r3, r3, r2 + 80006dc: fa21 f004 lsr.w r0, r1, r4 + 80006e0: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 80006e4: fa21 f204 lsr.w r2, r1, r4 + 80006e8: ea20 0002 bic.w r0, r0, r2 + 80006ec: eb00 70d3 add.w r0, r0, r3, lsr #31 + 80006f0: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 + 80006f4: bf08 it eq + 80006f6: ea20 70d3 biceq.w r0, r0, r3, lsr #31 + 80006fa: bd70 pop {r4, r5, r6, pc} + 80006fc: f094 0f00 teq r4, #0 + 8000700: d10f bne.n 8000722 <__aeabi_dmul+0x1c2> + 8000702: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 + 8000706: 0040 lsls r0, r0, #1 + 8000708: eb41 0101 adc.w r1, r1, r1 + 800070c: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 8000710: bf08 it eq + 8000712: 3c01 subeq r4, #1 + 8000714: d0f7 beq.n 8000706 <__aeabi_dmul+0x1a6> + 8000716: ea41 0106 orr.w r1, r1, r6 + 800071a: f095 0f00 teq r5, #0 + 800071e: bf18 it ne + 8000720: 4770 bxne lr + 8000722: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 + 8000726: 0052 lsls r2, r2, #1 + 8000728: eb43 0303 adc.w r3, r3, r3 + 800072c: f413 1f80 tst.w r3, #1048576 ; 0x100000 + 8000730: bf08 it eq + 8000732: 3d01 subeq r5, #1 + 8000734: d0f7 beq.n 8000726 <__aeabi_dmul+0x1c6> + 8000736: ea43 0306 orr.w r3, r3, r6 + 800073a: 4770 bx lr + 800073c: ea94 0f0c teq r4, ip + 8000740: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8000744: bf18 it ne + 8000746: ea95 0f0c teqne r5, ip + 800074a: d00c beq.n 8000766 <__aeabi_dmul+0x206> + 800074c: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000750: bf18 it ne + 8000752: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000756: d1d1 bne.n 80006fc <__aeabi_dmul+0x19c> + 8000758: ea81 0103 eor.w r1, r1, r3 + 800075c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 8000760: f04f 0000 mov.w r0, #0 + 8000764: bd70 pop {r4, r5, r6, pc} + 8000766: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 800076a: bf06 itte eq + 800076c: 4610 moveq r0, r2 + 800076e: 4619 moveq r1, r3 + 8000770: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 8000774: d019 beq.n 80007aa <__aeabi_dmul+0x24a> + 8000776: ea94 0f0c teq r4, ip + 800077a: d102 bne.n 8000782 <__aeabi_dmul+0x222> + 800077c: ea50 3601 orrs.w r6, r0, r1, lsl #12 + 8000780: d113 bne.n 80007aa <__aeabi_dmul+0x24a> + 8000782: ea95 0f0c teq r5, ip + 8000786: d105 bne.n 8000794 <__aeabi_dmul+0x234> + 8000788: ea52 3603 orrs.w r6, r2, r3, lsl #12 + 800078c: bf1c itt ne + 800078e: 4610 movne r0, r2 + 8000790: 4619 movne r1, r3 + 8000792: d10a bne.n 80007aa <__aeabi_dmul+0x24a> + 8000794: ea81 0103 eor.w r1, r1, r3 + 8000798: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 + 800079c: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 80007a0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 80007a4: f04f 0000 mov.w r0, #0 + 80007a8: bd70 pop {r4, r5, r6, pc} + 80007aa: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 + 80007ae: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 + 80007b2: bd70 pop {r4, r5, r6, pc} + +080007b4 <__aeabi_ddiv>: + 80007b4: b570 push {r4, r5, r6, lr} + 80007b6: f04f 0cff mov.w ip, #255 ; 0xff + 80007ba: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 + 80007be: ea1c 5411 ands.w r4, ip, r1, lsr #20 + 80007c2: bf1d ittte ne + 80007c4: ea1c 5513 andsne.w r5, ip, r3, lsr #20 + 80007c8: ea94 0f0c teqne r4, ip + 80007cc: ea95 0f0c teqne r5, ip + 80007d0: f000 f8a7 bleq 8000922 <__aeabi_ddiv+0x16e> + 80007d4: eba4 0405 sub.w r4, r4, r5 + 80007d8: ea81 0e03 eor.w lr, r1, r3 + 80007dc: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 80007e0: ea4f 3101 mov.w r1, r1, lsl #12 + 80007e4: f000 8088 beq.w 80008f8 <__aeabi_ddiv+0x144> + 80007e8: ea4f 3303 mov.w r3, r3, lsl #12 + 80007ec: f04f 5580 mov.w r5, #268435456 ; 0x10000000 + 80007f0: ea45 1313 orr.w r3, r5, r3, lsr #4 + 80007f4: ea43 6312 orr.w r3, r3, r2, lsr #24 + 80007f8: ea4f 2202 mov.w r2, r2, lsl #8 + 80007fc: ea45 1511 orr.w r5, r5, r1, lsr #4 + 8000800: ea45 6510 orr.w r5, r5, r0, lsr #24 + 8000804: ea4f 2600 mov.w r6, r0, lsl #8 + 8000808: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 + 800080c: 429d cmp r5, r3 + 800080e: bf08 it eq + 8000810: 4296 cmpeq r6, r2 + 8000812: f144 04fd adc.w r4, r4, #253 ; 0xfd + 8000816: f504 7440 add.w r4, r4, #768 ; 0x300 + 800081a: d202 bcs.n 8000822 <__aeabi_ddiv+0x6e> + 800081c: 085b lsrs r3, r3, #1 + 800081e: ea4f 0232 mov.w r2, r2, rrx + 8000822: 1ab6 subs r6, r6, r2 + 8000824: eb65 0503 sbc.w r5, r5, r3 + 8000828: 085b lsrs r3, r3, #1 + 800082a: ea4f 0232 mov.w r2, r2, rrx + 800082e: f44f 1080 mov.w r0, #1048576 ; 0x100000 + 8000832: f44f 2c00 mov.w ip, #524288 ; 0x80000 + 8000836: ebb6 0e02 subs.w lr, r6, r2 + 800083a: eb75 0e03 sbcs.w lr, r5, r3 + 800083e: bf22 ittt cs + 8000840: 1ab6 subcs r6, r6, r2 + 8000842: 4675 movcs r5, lr + 8000844: ea40 000c orrcs.w r0, r0, ip + 8000848: 085b lsrs r3, r3, #1 + 800084a: ea4f 0232 mov.w r2, r2, rrx + 800084e: ebb6 0e02 subs.w lr, r6, r2 + 8000852: eb75 0e03 sbcs.w lr, r5, r3 + 8000856: bf22 ittt cs + 8000858: 1ab6 subcs r6, r6, r2 + 800085a: 4675 movcs r5, lr + 800085c: ea40 005c orrcs.w r0, r0, ip, lsr #1 + 8000860: 085b lsrs r3, r3, #1 + 8000862: ea4f 0232 mov.w r2, r2, rrx + 8000866: ebb6 0e02 subs.w lr, r6, r2 + 800086a: eb75 0e03 sbcs.w lr, r5, r3 + 800086e: bf22 ittt cs + 8000870: 1ab6 subcs r6, r6, r2 + 8000872: 4675 movcs r5, lr + 8000874: ea40 009c orrcs.w r0, r0, ip, lsr #2 + 8000878: 085b lsrs r3, r3, #1 + 800087a: ea4f 0232 mov.w r2, r2, rrx + 800087e: ebb6 0e02 subs.w lr, r6, r2 + 8000882: eb75 0e03 sbcs.w lr, r5, r3 + 8000886: bf22 ittt cs + 8000888: 1ab6 subcs r6, r6, r2 + 800088a: 4675 movcs r5, lr + 800088c: ea40 00dc orrcs.w r0, r0, ip, lsr #3 + 8000890: ea55 0e06 orrs.w lr, r5, r6 + 8000894: d018 beq.n 80008c8 <__aeabi_ddiv+0x114> + 8000896: ea4f 1505 mov.w r5, r5, lsl #4 + 800089a: ea45 7516 orr.w r5, r5, r6, lsr #28 + 800089e: ea4f 1606 mov.w r6, r6, lsl #4 + 80008a2: ea4f 03c3 mov.w r3, r3, lsl #3 + 80008a6: ea43 7352 orr.w r3, r3, r2, lsr #29 + 80008aa: ea4f 02c2 mov.w r2, r2, lsl #3 + 80008ae: ea5f 1c1c movs.w ip, ip, lsr #4 + 80008b2: d1c0 bne.n 8000836 <__aeabi_ddiv+0x82> + 80008b4: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80008b8: d10b bne.n 80008d2 <__aeabi_ddiv+0x11e> + 80008ba: ea41 0100 orr.w r1, r1, r0 + 80008be: f04f 0000 mov.w r0, #0 + 80008c2: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 + 80008c6: e7b6 b.n 8000836 <__aeabi_ddiv+0x82> + 80008c8: f411 1f80 tst.w r1, #1048576 ; 0x100000 + 80008cc: bf04 itt eq + 80008ce: 4301 orreq r1, r0 + 80008d0: 2000 moveq r0, #0 + 80008d2: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd + 80008d6: bf88 it hi + 80008d8: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 + 80008dc: f63f aeaf bhi.w 800063e <__aeabi_dmul+0xde> + 80008e0: ebb5 0c03 subs.w ip, r5, r3 + 80008e4: bf04 itt eq + 80008e6: ebb6 0c02 subseq.w ip, r6, r2 + 80008ea: ea5f 0c50 movseq.w ip, r0, lsr #1 + 80008ee: f150 0000 adcs.w r0, r0, #0 + 80008f2: eb41 5104 adc.w r1, r1, r4, lsl #20 + 80008f6: bd70 pop {r4, r5, r6, pc} + 80008f8: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 + 80008fc: ea4e 3111 orr.w r1, lr, r1, lsr #12 + 8000900: eb14 045c adds.w r4, r4, ip, lsr #1 + 8000904: bfc2 ittt gt + 8000906: ebd4 050c rsbsgt r5, r4, ip + 800090a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 + 800090e: bd70 popgt {r4, r5, r6, pc} + 8000910: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 + 8000914: f04f 0e00 mov.w lr, #0 + 8000918: 3c01 subs r4, #1 + 800091a: e690 b.n 800063e <__aeabi_dmul+0xde> + 800091c: ea45 0e06 orr.w lr, r5, r6 + 8000920: e68d b.n 800063e <__aeabi_dmul+0xde> + 8000922: ea0c 5513 and.w r5, ip, r3, lsr #20 + 8000926: ea94 0f0c teq r4, ip + 800092a: bf08 it eq + 800092c: ea95 0f0c teqeq r5, ip + 8000930: f43f af3b beq.w 80007aa <__aeabi_dmul+0x24a> + 8000934: ea94 0f0c teq r4, ip + 8000938: d10a bne.n 8000950 <__aeabi_ddiv+0x19c> + 800093a: ea50 3401 orrs.w r4, r0, r1, lsl #12 + 800093e: f47f af34 bne.w 80007aa <__aeabi_dmul+0x24a> + 8000942: ea95 0f0c teq r5, ip + 8000946: f47f af25 bne.w 8000794 <__aeabi_dmul+0x234> + 800094a: 4610 mov r0, r2 + 800094c: 4619 mov r1, r3 + 800094e: e72c b.n 80007aa <__aeabi_dmul+0x24a> + 8000950: ea95 0f0c teq r5, ip + 8000954: d106 bne.n 8000964 <__aeabi_ddiv+0x1b0> + 8000956: ea52 3503 orrs.w r5, r2, r3, lsl #12 + 800095a: f43f aefd beq.w 8000758 <__aeabi_dmul+0x1f8> + 800095e: 4610 mov r0, r2 + 8000960: 4619 mov r1, r3 + 8000962: e722 b.n 80007aa <__aeabi_dmul+0x24a> + 8000964: ea50 0641 orrs.w r6, r0, r1, lsl #1 + 8000968: bf18 it ne + 800096a: ea52 0643 orrsne.w r6, r2, r3, lsl #1 + 800096e: f47f aec5 bne.w 80006fc <__aeabi_dmul+0x19c> + 8000972: ea50 0441 orrs.w r4, r0, r1, lsl #1 + 8000976: f47f af0d bne.w 8000794 <__aeabi_dmul+0x234> + 800097a: ea52 0543 orrs.w r5, r2, r3, lsl #1 + 800097e: f47f aeeb bne.w 8000758 <__aeabi_dmul+0x1f8> + 8000982: e712 b.n 80007aa <__aeabi_dmul+0x24a> + +08000984 <__gedf2>: + 8000984: f04f 3cff mov.w ip, #4294967295 + 8000988: e006 b.n 8000998 <__cmpdf2+0x4> + 800098a: bf00 nop + +0800098c <__ledf2>: + 800098c: f04f 0c01 mov.w ip, #1 + 8000990: e002 b.n 8000998 <__cmpdf2+0x4> + 8000992: bf00 nop + +08000994 <__cmpdf2>: + 8000994: f04f 0c01 mov.w ip, #1 + 8000998: f84d cd04 str.w ip, [sp, #-4]! + 800099c: ea4f 0c41 mov.w ip, r1, lsl #1 + 80009a0: ea7f 5c6c mvns.w ip, ip, asr #21 + 80009a4: ea4f 0c43 mov.w ip, r3, lsl #1 + 80009a8: bf18 it ne + 80009aa: ea7f 5c6c mvnsne.w ip, ip, asr #21 + 80009ae: d01b beq.n 80009e8 <__cmpdf2+0x54> + 80009b0: b001 add sp, #4 + 80009b2: ea50 0c41 orrs.w ip, r0, r1, lsl #1 + 80009b6: bf0c ite eq + 80009b8: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 + 80009bc: ea91 0f03 teqne r1, r3 + 80009c0: bf02 ittt eq + 80009c2: ea90 0f02 teqeq r0, r2 + 80009c6: 2000 moveq r0, #0 + 80009c8: 4770 bxeq lr + 80009ca: f110 0f00 cmn.w r0, #0 + 80009ce: ea91 0f03 teq r1, r3 + 80009d2: bf58 it pl + 80009d4: 4299 cmppl r1, r3 + 80009d6: bf08 it eq + 80009d8: 4290 cmpeq r0, r2 + 80009da: bf2c ite cs + 80009dc: 17d8 asrcs r0, r3, #31 + 80009de: ea6f 70e3 mvncc.w r0, r3, asr #31 + 80009e2: f040 0001 orr.w r0, r0, #1 + 80009e6: 4770 bx lr + 80009e8: ea4f 0c41 mov.w ip, r1, lsl #1 + 80009ec: ea7f 5c6c mvns.w ip, ip, asr #21 + 80009f0: d102 bne.n 80009f8 <__cmpdf2+0x64> + 80009f2: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 80009f6: d107 bne.n 8000a08 <__cmpdf2+0x74> + 80009f8: ea4f 0c43 mov.w ip, r3, lsl #1 + 80009fc: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a00: d1d6 bne.n 80009b0 <__cmpdf2+0x1c> + 8000a02: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000a06: d0d3 beq.n 80009b0 <__cmpdf2+0x1c> + 8000a08: f85d 0b04 ldr.w r0, [sp], #4 + 8000a0c: 4770 bx lr + 8000a0e: bf00 nop + +08000a10 <__aeabi_cdrcmple>: + 8000a10: 4684 mov ip, r0 + 8000a12: 4610 mov r0, r2 + 8000a14: 4662 mov r2, ip + 8000a16: 468c mov ip, r1 + 8000a18: 4619 mov r1, r3 + 8000a1a: 4663 mov r3, ip + 8000a1c: e000 b.n 8000a20 <__aeabi_cdcmpeq> + 8000a1e: bf00 nop + +08000a20 <__aeabi_cdcmpeq>: + 8000a20: b501 push {r0, lr} + 8000a22: f7ff ffb7 bl 8000994 <__cmpdf2> + 8000a26: 2800 cmp r0, #0 + 8000a28: bf48 it mi + 8000a2a: f110 0f00 cmnmi.w r0, #0 + 8000a2e: bd01 pop {r0, pc} + +08000a30 <__aeabi_dcmpeq>: + 8000a30: f84d ed08 str.w lr, [sp, #-8]! + 8000a34: f7ff fff4 bl 8000a20 <__aeabi_cdcmpeq> + 8000a38: bf0c ite eq + 8000a3a: 2001 moveq r0, #1 + 8000a3c: 2000 movne r0, #0 + 8000a3e: f85d fb08 ldr.w pc, [sp], #8 + 8000a42: bf00 nop + +08000a44 <__aeabi_dcmplt>: + 8000a44: f84d ed08 str.w lr, [sp, #-8]! + 8000a48: f7ff ffea bl 8000a20 <__aeabi_cdcmpeq> + 8000a4c: bf34 ite cc + 8000a4e: 2001 movcc r0, #1 + 8000a50: 2000 movcs r0, #0 + 8000a52: f85d fb08 ldr.w pc, [sp], #8 + 8000a56: bf00 nop + +08000a58 <__aeabi_dcmple>: + 8000a58: f84d ed08 str.w lr, [sp, #-8]! + 8000a5c: f7ff ffe0 bl 8000a20 <__aeabi_cdcmpeq> + 8000a60: bf94 ite ls + 8000a62: 2001 movls r0, #1 + 8000a64: 2000 movhi r0, #0 + 8000a66: f85d fb08 ldr.w pc, [sp], #8 + 8000a6a: bf00 nop + +08000a6c <__aeabi_dcmpge>: + 8000a6c: f84d ed08 str.w lr, [sp, #-8]! + 8000a70: f7ff ffce bl 8000a10 <__aeabi_cdrcmple> + 8000a74: bf94 ite ls + 8000a76: 2001 movls r0, #1 + 8000a78: 2000 movhi r0, #0 + 8000a7a: f85d fb08 ldr.w pc, [sp], #8 + 8000a7e: bf00 nop + +08000a80 <__aeabi_dcmpgt>: + 8000a80: f84d ed08 str.w lr, [sp, #-8]! + 8000a84: f7ff ffc4 bl 8000a10 <__aeabi_cdrcmple> + 8000a88: bf34 ite cc + 8000a8a: 2001 movcc r0, #1 + 8000a8c: 2000 movcs r0, #0 + 8000a8e: f85d fb08 ldr.w pc, [sp], #8 + 8000a92: bf00 nop + +08000a94 <__aeabi_dcmpun>: + 8000a94: ea4f 0c41 mov.w ip, r1, lsl #1 + 8000a98: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000a9c: d102 bne.n 8000aa4 <__aeabi_dcmpun+0x10> + 8000a9e: ea50 3c01 orrs.w ip, r0, r1, lsl #12 + 8000aa2: d10a bne.n 8000aba <__aeabi_dcmpun+0x26> + 8000aa4: ea4f 0c43 mov.w ip, r3, lsl #1 + 8000aa8: ea7f 5c6c mvns.w ip, ip, asr #21 + 8000aac: d102 bne.n 8000ab4 <__aeabi_dcmpun+0x20> + 8000aae: ea52 3c03 orrs.w ip, r2, r3, lsl #12 + 8000ab2: d102 bne.n 8000aba <__aeabi_dcmpun+0x26> + 8000ab4: f04f 0000 mov.w r0, #0 + 8000ab8: 4770 bx lr + 8000aba: f04f 0001 mov.w r0, #1 + 8000abe: 4770 bx lr + +08000ac0 <__aeabi_d2iz>: + 8000ac0: ea4f 0241 mov.w r2, r1, lsl #1 + 8000ac4: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 + 8000ac8: d215 bcs.n 8000af6 <__aeabi_d2iz+0x36> + 8000aca: d511 bpl.n 8000af0 <__aeabi_d2iz+0x30> + 8000acc: f46f 7378 mvn.w r3, #992 ; 0x3e0 + 8000ad0: ebb3 5262 subs.w r2, r3, r2, asr #21 + 8000ad4: d912 bls.n 8000afc <__aeabi_d2iz+0x3c> + 8000ad6: ea4f 23c1 mov.w r3, r1, lsl #11 + 8000ada: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 + 8000ade: ea43 5350 orr.w r3, r3, r0, lsr #21 + 8000ae2: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 + 8000ae6: fa23 f002 lsr.w r0, r3, r2 + 8000aea: bf18 it ne + 8000aec: 4240 negne r0, r0 + 8000aee: 4770 bx lr + 8000af0: f04f 0000 mov.w r0, #0 + 8000af4: 4770 bx lr + 8000af6: ea50 3001 orrs.w r0, r0, r1, lsl #12 + 8000afa: d105 bne.n 8000b08 <__aeabi_d2iz+0x48> + 8000afc: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 + 8000b00: bf08 it eq + 8000b02: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 + 8000b06: 4770 bx lr + 8000b08: f04f 0000 mov.w r0, #0 + 8000b0c: 4770 bx lr + 8000b0e: bf00 nop + +08000b10 <__aeabi_uldivmod>: + 8000b10: b953 cbnz r3, 8000b28 <__aeabi_uldivmod+0x18> + 8000b12: b94a cbnz r2, 8000b28 <__aeabi_uldivmod+0x18> + 8000b14: 2900 cmp r1, #0 + 8000b16: bf08 it eq + 8000b18: 2800 cmpeq r0, #0 + 8000b1a: bf1c itt ne + 8000b1c: f04f 31ff movne.w r1, #4294967295 + 8000b20: f04f 30ff movne.w r0, #4294967295 + 8000b24: f000 b972 b.w 8000e0c <__aeabi_idiv0> + 8000b28: f1ad 0c08 sub.w ip, sp, #8 + 8000b2c: e96d ce04 strd ip, lr, [sp, #-16]! + 8000b30: f000 f806 bl 8000b40 <__udivmoddi4> + 8000b34: f8dd e004 ldr.w lr, [sp, #4] + 8000b38: e9dd 2302 ldrd r2, r3, [sp, #8] + 8000b3c: b004 add sp, #16 + 8000b3e: 4770 bx lr + +08000b40 <__udivmoddi4>: + 8000b40: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000b44: 9e08 ldr r6, [sp, #32] + 8000b46: 4604 mov r4, r0 + 8000b48: 4688 mov r8, r1 + 8000b4a: 2b00 cmp r3, #0 + 8000b4c: d14b bne.n 8000be6 <__udivmoddi4+0xa6> + 8000b4e: 428a cmp r2, r1 + 8000b50: 4615 mov r5, r2 + 8000b52: d967 bls.n 8000c24 <__udivmoddi4+0xe4> + 8000b54: fab2 f282 clz r2, r2 + 8000b58: b14a cbz r2, 8000b6e <__udivmoddi4+0x2e> + 8000b5a: f1c2 0720 rsb r7, r2, #32 + 8000b5e: fa01 f302 lsl.w r3, r1, r2 + 8000b62: fa20 f707 lsr.w r7, r0, r7 + 8000b66: 4095 lsls r5, r2 + 8000b68: ea47 0803 orr.w r8, r7, r3 + 8000b6c: 4094 lsls r4, r2 + 8000b6e: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000b72: 0c23 lsrs r3, r4, #16 + 8000b74: fbb8 f7fe udiv r7, r8, lr + 8000b78: fa1f fc85 uxth.w ip, r5 + 8000b7c: fb0e 8817 mls r8, lr, r7, r8 + 8000b80: ea43 4308 orr.w r3, r3, r8, lsl #16 + 8000b84: fb07 f10c mul.w r1, r7, ip + 8000b88: 4299 cmp r1, r3 + 8000b8a: d909 bls.n 8000ba0 <__udivmoddi4+0x60> + 8000b8c: 18eb adds r3, r5, r3 + 8000b8e: f107 30ff add.w r0, r7, #4294967295 + 8000b92: f080 811b bcs.w 8000dcc <__udivmoddi4+0x28c> + 8000b96: 4299 cmp r1, r3 + 8000b98: f240 8118 bls.w 8000dcc <__udivmoddi4+0x28c> + 8000b9c: 3f02 subs r7, #2 + 8000b9e: 442b add r3, r5 + 8000ba0: 1a5b subs r3, r3, r1 + 8000ba2: b2a4 uxth r4, r4 + 8000ba4: fbb3 f0fe udiv r0, r3, lr + 8000ba8: fb0e 3310 mls r3, lr, r0, r3 + 8000bac: ea44 4403 orr.w r4, r4, r3, lsl #16 + 8000bb0: fb00 fc0c mul.w ip, r0, ip + 8000bb4: 45a4 cmp ip, r4 + 8000bb6: d909 bls.n 8000bcc <__udivmoddi4+0x8c> + 8000bb8: 192c adds r4, r5, r4 + 8000bba: f100 33ff add.w r3, r0, #4294967295 + 8000bbe: f080 8107 bcs.w 8000dd0 <__udivmoddi4+0x290> + 8000bc2: 45a4 cmp ip, r4 + 8000bc4: f240 8104 bls.w 8000dd0 <__udivmoddi4+0x290> + 8000bc8: 3802 subs r0, #2 + 8000bca: 442c add r4, r5 + 8000bcc: ea40 4007 orr.w r0, r0, r7, lsl #16 + 8000bd0: eba4 040c sub.w r4, r4, ip + 8000bd4: 2700 movs r7, #0 + 8000bd6: b11e cbz r6, 8000be0 <__udivmoddi4+0xa0> + 8000bd8: 40d4 lsrs r4, r2 + 8000bda: 2300 movs r3, #0 + 8000bdc: e9c6 4300 strd r4, r3, [r6] + 8000be0: 4639 mov r1, r7 + 8000be2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000be6: 428b cmp r3, r1 + 8000be8: d909 bls.n 8000bfe <__udivmoddi4+0xbe> + 8000bea: 2e00 cmp r6, #0 + 8000bec: f000 80eb beq.w 8000dc6 <__udivmoddi4+0x286> + 8000bf0: 2700 movs r7, #0 + 8000bf2: e9c6 0100 strd r0, r1, [r6] + 8000bf6: 4638 mov r0, r7 + 8000bf8: 4639 mov r1, r7 + 8000bfa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000bfe: fab3 f783 clz r7, r3 + 8000c02: 2f00 cmp r7, #0 + 8000c04: d147 bne.n 8000c96 <__udivmoddi4+0x156> + 8000c06: 428b cmp r3, r1 + 8000c08: d302 bcc.n 8000c10 <__udivmoddi4+0xd0> + 8000c0a: 4282 cmp r2, r0 + 8000c0c: f200 80fa bhi.w 8000e04 <__udivmoddi4+0x2c4> + 8000c10: 1a84 subs r4, r0, r2 + 8000c12: eb61 0303 sbc.w r3, r1, r3 + 8000c16: 2001 movs r0, #1 + 8000c18: 4698 mov r8, r3 + 8000c1a: 2e00 cmp r6, #0 + 8000c1c: d0e0 beq.n 8000be0 <__udivmoddi4+0xa0> + 8000c1e: e9c6 4800 strd r4, r8, [r6] + 8000c22: e7dd b.n 8000be0 <__udivmoddi4+0xa0> + 8000c24: b902 cbnz r2, 8000c28 <__udivmoddi4+0xe8> + 8000c26: deff udf #255 ; 0xff + 8000c28: fab2 f282 clz r2, r2 + 8000c2c: 2a00 cmp r2, #0 + 8000c2e: f040 808f bne.w 8000d50 <__udivmoddi4+0x210> + 8000c32: 1b49 subs r1, r1, r5 + 8000c34: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000c38: fa1f f885 uxth.w r8, r5 + 8000c3c: 2701 movs r7, #1 + 8000c3e: fbb1 fcfe udiv ip, r1, lr + 8000c42: 0c23 lsrs r3, r4, #16 + 8000c44: fb0e 111c mls r1, lr, ip, r1 + 8000c48: ea43 4301 orr.w r3, r3, r1, lsl #16 + 8000c4c: fb08 f10c mul.w r1, r8, ip + 8000c50: 4299 cmp r1, r3 + 8000c52: d907 bls.n 8000c64 <__udivmoddi4+0x124> + 8000c54: 18eb adds r3, r5, r3 + 8000c56: f10c 30ff add.w r0, ip, #4294967295 + 8000c5a: d202 bcs.n 8000c62 <__udivmoddi4+0x122> + 8000c5c: 4299 cmp r1, r3 + 8000c5e: f200 80cd bhi.w 8000dfc <__udivmoddi4+0x2bc> + 8000c62: 4684 mov ip, r0 + 8000c64: 1a59 subs r1, r3, r1 + 8000c66: b2a3 uxth r3, r4 + 8000c68: fbb1 f0fe udiv r0, r1, lr + 8000c6c: fb0e 1410 mls r4, lr, r0, r1 + 8000c70: ea43 4404 orr.w r4, r3, r4, lsl #16 + 8000c74: fb08 f800 mul.w r8, r8, r0 + 8000c78: 45a0 cmp r8, r4 + 8000c7a: d907 bls.n 8000c8c <__udivmoddi4+0x14c> + 8000c7c: 192c adds r4, r5, r4 + 8000c7e: f100 33ff add.w r3, r0, #4294967295 + 8000c82: d202 bcs.n 8000c8a <__udivmoddi4+0x14a> + 8000c84: 45a0 cmp r8, r4 + 8000c86: f200 80b6 bhi.w 8000df6 <__udivmoddi4+0x2b6> + 8000c8a: 4618 mov r0, r3 + 8000c8c: eba4 0408 sub.w r4, r4, r8 + 8000c90: ea40 400c orr.w r0, r0, ip, lsl #16 + 8000c94: e79f b.n 8000bd6 <__udivmoddi4+0x96> + 8000c96: f1c7 0c20 rsb ip, r7, #32 + 8000c9a: 40bb lsls r3, r7 + 8000c9c: fa22 fe0c lsr.w lr, r2, ip + 8000ca0: ea4e 0e03 orr.w lr, lr, r3 + 8000ca4: fa01 f407 lsl.w r4, r1, r7 + 8000ca8: fa20 f50c lsr.w r5, r0, ip + 8000cac: fa21 f30c lsr.w r3, r1, ip + 8000cb0: ea4f 481e mov.w r8, lr, lsr #16 + 8000cb4: 4325 orrs r5, r4 + 8000cb6: fbb3 f9f8 udiv r9, r3, r8 + 8000cba: 0c2c lsrs r4, r5, #16 + 8000cbc: fb08 3319 mls r3, r8, r9, r3 + 8000cc0: fa1f fa8e uxth.w sl, lr + 8000cc4: ea44 4303 orr.w r3, r4, r3, lsl #16 + 8000cc8: fb09 f40a mul.w r4, r9, sl + 8000ccc: 429c cmp r4, r3 + 8000cce: fa02 f207 lsl.w r2, r2, r7 + 8000cd2: fa00 f107 lsl.w r1, r0, r7 + 8000cd6: d90b bls.n 8000cf0 <__udivmoddi4+0x1b0> + 8000cd8: eb1e 0303 adds.w r3, lr, r3 + 8000cdc: f109 30ff add.w r0, r9, #4294967295 + 8000ce0: f080 8087 bcs.w 8000df2 <__udivmoddi4+0x2b2> + 8000ce4: 429c cmp r4, r3 + 8000ce6: f240 8084 bls.w 8000df2 <__udivmoddi4+0x2b2> + 8000cea: f1a9 0902 sub.w r9, r9, #2 + 8000cee: 4473 add r3, lr + 8000cf0: 1b1b subs r3, r3, r4 + 8000cf2: b2ad uxth r5, r5 + 8000cf4: fbb3 f0f8 udiv r0, r3, r8 + 8000cf8: fb08 3310 mls r3, r8, r0, r3 + 8000cfc: ea45 4403 orr.w r4, r5, r3, lsl #16 + 8000d00: fb00 fa0a mul.w sl, r0, sl + 8000d04: 45a2 cmp sl, r4 + 8000d06: d908 bls.n 8000d1a <__udivmoddi4+0x1da> + 8000d08: eb1e 0404 adds.w r4, lr, r4 + 8000d0c: f100 33ff add.w r3, r0, #4294967295 + 8000d10: d26b bcs.n 8000dea <__udivmoddi4+0x2aa> + 8000d12: 45a2 cmp sl, r4 + 8000d14: d969 bls.n 8000dea <__udivmoddi4+0x2aa> + 8000d16: 3802 subs r0, #2 + 8000d18: 4474 add r4, lr + 8000d1a: ea40 4009 orr.w r0, r0, r9, lsl #16 + 8000d1e: fba0 8902 umull r8, r9, r0, r2 + 8000d22: eba4 040a sub.w r4, r4, sl + 8000d26: 454c cmp r4, r9 + 8000d28: 46c2 mov sl, r8 + 8000d2a: 464b mov r3, r9 + 8000d2c: d354 bcc.n 8000dd8 <__udivmoddi4+0x298> + 8000d2e: d051 beq.n 8000dd4 <__udivmoddi4+0x294> + 8000d30: 2e00 cmp r6, #0 + 8000d32: d069 beq.n 8000e08 <__udivmoddi4+0x2c8> + 8000d34: ebb1 050a subs.w r5, r1, sl + 8000d38: eb64 0403 sbc.w r4, r4, r3 + 8000d3c: fa04 fc0c lsl.w ip, r4, ip + 8000d40: 40fd lsrs r5, r7 + 8000d42: 40fc lsrs r4, r7 + 8000d44: ea4c 0505 orr.w r5, ip, r5 + 8000d48: e9c6 5400 strd r5, r4, [r6] + 8000d4c: 2700 movs r7, #0 + 8000d4e: e747 b.n 8000be0 <__udivmoddi4+0xa0> + 8000d50: f1c2 0320 rsb r3, r2, #32 + 8000d54: fa20 f703 lsr.w r7, r0, r3 + 8000d58: 4095 lsls r5, r2 + 8000d5a: fa01 f002 lsl.w r0, r1, r2 + 8000d5e: fa21 f303 lsr.w r3, r1, r3 + 8000d62: ea4f 4e15 mov.w lr, r5, lsr #16 + 8000d66: 4338 orrs r0, r7 + 8000d68: 0c01 lsrs r1, r0, #16 + 8000d6a: fbb3 f7fe udiv r7, r3, lr + 8000d6e: fa1f f885 uxth.w r8, r5 + 8000d72: fb0e 3317 mls r3, lr, r7, r3 + 8000d76: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000d7a: fb07 f308 mul.w r3, r7, r8 + 8000d7e: 428b cmp r3, r1 + 8000d80: fa04 f402 lsl.w r4, r4, r2 + 8000d84: d907 bls.n 8000d96 <__udivmoddi4+0x256> + 8000d86: 1869 adds r1, r5, r1 + 8000d88: f107 3cff add.w ip, r7, #4294967295 + 8000d8c: d22f bcs.n 8000dee <__udivmoddi4+0x2ae> + 8000d8e: 428b cmp r3, r1 + 8000d90: d92d bls.n 8000dee <__udivmoddi4+0x2ae> + 8000d92: 3f02 subs r7, #2 + 8000d94: 4429 add r1, r5 + 8000d96: 1acb subs r3, r1, r3 + 8000d98: b281 uxth r1, r0 + 8000d9a: fbb3 f0fe udiv r0, r3, lr + 8000d9e: fb0e 3310 mls r3, lr, r0, r3 + 8000da2: ea41 4103 orr.w r1, r1, r3, lsl #16 + 8000da6: fb00 f308 mul.w r3, r0, r8 + 8000daa: 428b cmp r3, r1 + 8000dac: d907 bls.n 8000dbe <__udivmoddi4+0x27e> + 8000dae: 1869 adds r1, r5, r1 + 8000db0: f100 3cff add.w ip, r0, #4294967295 + 8000db4: d217 bcs.n 8000de6 <__udivmoddi4+0x2a6> + 8000db6: 428b cmp r3, r1 + 8000db8: d915 bls.n 8000de6 <__udivmoddi4+0x2a6> + 8000dba: 3802 subs r0, #2 + 8000dbc: 4429 add r1, r5 + 8000dbe: 1ac9 subs r1, r1, r3 + 8000dc0: ea40 4707 orr.w r7, r0, r7, lsl #16 + 8000dc4: e73b b.n 8000c3e <__udivmoddi4+0xfe> + 8000dc6: 4637 mov r7, r6 + 8000dc8: 4630 mov r0, r6 + 8000dca: e709 b.n 8000be0 <__udivmoddi4+0xa0> + 8000dcc: 4607 mov r7, r0 + 8000dce: e6e7 b.n 8000ba0 <__udivmoddi4+0x60> + 8000dd0: 4618 mov r0, r3 + 8000dd2: e6fb b.n 8000bcc <__udivmoddi4+0x8c> + 8000dd4: 4541 cmp r1, r8 + 8000dd6: d2ab bcs.n 8000d30 <__udivmoddi4+0x1f0> + 8000dd8: ebb8 0a02 subs.w sl, r8, r2 + 8000ddc: eb69 020e sbc.w r2, r9, lr + 8000de0: 3801 subs r0, #1 + 8000de2: 4613 mov r3, r2 + 8000de4: e7a4 b.n 8000d30 <__udivmoddi4+0x1f0> + 8000de6: 4660 mov r0, ip + 8000de8: e7e9 b.n 8000dbe <__udivmoddi4+0x27e> + 8000dea: 4618 mov r0, r3 + 8000dec: e795 b.n 8000d1a <__udivmoddi4+0x1da> + 8000dee: 4667 mov r7, ip + 8000df0: e7d1 b.n 8000d96 <__udivmoddi4+0x256> + 8000df2: 4681 mov r9, r0 + 8000df4: e77c b.n 8000cf0 <__udivmoddi4+0x1b0> + 8000df6: 3802 subs r0, #2 + 8000df8: 442c add r4, r5 + 8000dfa: e747 b.n 8000c8c <__udivmoddi4+0x14c> + 8000dfc: f1ac 0c02 sub.w ip, ip, #2 + 8000e00: 442b add r3, r5 + 8000e02: e72f b.n 8000c64 <__udivmoddi4+0x124> + 8000e04: 4638 mov r0, r7 + 8000e06: e708 b.n 8000c1a <__udivmoddi4+0xda> + 8000e08: 4637 mov r7, r6 + 8000e0a: e6e9 b.n 8000be0 <__udivmoddi4+0xa0> + +08000e0c <__aeabi_idiv0>: + 8000e0c: 4770 bx lr + 8000e0e: bf00 nop + +08000e10 : +* Function Name : deg_to_rad +* Description : converts degrees to radians +* Return : angle in radians +*******************************************************************************/ +double deg_to_rad(double deg) +{ + 8000e10: b590 push {r4, r7, lr} + 8000e12: b085 sub sp, #20 + 8000e14: af00 add r7, sp, #0 + 8000e16: ed87 0b00 vstr d0, [r7] + double rad = deg*(M_PI/180); + 8000e1a: a30b add r3, pc, #44 ; (adr r3, 8000e48 ) + 8000e1c: e9d3 2300 ldrd r2, r3, [r3] + 8000e20: e9d7 0100 ldrd r0, r1, [r7] + 8000e24: f7ff fb9c bl 8000560 <__aeabi_dmul> + 8000e28: 4603 mov r3, r0 + 8000e2a: 460c mov r4, r1 + 8000e2c: e9c7 3402 strd r3, r4, [r7, #8] + return rad; + 8000e30: e9d7 3402 ldrd r3, r4, [r7, #8] + 8000e34: ec44 3b17 vmov d7, r3, r4 +} + 8000e38: eeb0 0a47 vmov.f32 s0, s14 + 8000e3c: eef0 0a67 vmov.f32 s1, s15 + 8000e40: 3714 adds r7, #20 + 8000e42: 46bd mov sp, r7 + 8000e44: bd90 pop {r4, r7, pc} + 8000e46: bf00 nop + 8000e48: a2529d39 .word 0xa2529d39 + 8000e4c: 3f91df46 .word 0x3f91df46 + +08000e50 : +* Function Name : rad_to_deg +* Description : converts radians to degrees +* Return : angle in degrees +*******************************************************************************/ +double rad_to_deg(double rad) +{ + 8000e50: b590 push {r4, r7, lr} + 8000e52: b085 sub sp, #20 + 8000e54: af00 add r7, sp, #0 + 8000e56: ed87 0b00 vstr d0, [r7] + double deg = rad*(180/M_PI); + 8000e5a: a30b add r3, pc, #44 ; (adr r3, 8000e88 ) + 8000e5c: e9d3 2300 ldrd r2, r3, [r3] + 8000e60: e9d7 0100 ldrd r0, r1, [r7] + 8000e64: f7ff fb7c bl 8000560 <__aeabi_dmul> + 8000e68: 4603 mov r3, r0 + 8000e6a: 460c mov r4, r1 + 8000e6c: e9c7 3402 strd r3, r4, [r7, #8] + return deg; + 8000e70: e9d7 3402 ldrd r3, r4, [r7, #8] + 8000e74: ec44 3b17 vmov d7, r3, r4 +} + 8000e78: eeb0 0a47 vmov.f32 s0, s14 + 8000e7c: eef0 0a67 vmov.f32 s1, s15 + 8000e80: 3714 adds r7, #20 + 8000e82: 46bd mov sp, r7 + 8000e84: bd90 pop {r4, r7, pc} + 8000e86: bf00 nop + 8000e88: 1a63c1f8 .word 0x1a63c1f8 + 8000e8c: 404ca5dc .word 0x404ca5dc + +08000e90 : +* Function Name : leap_year_check +* Description : checks if year is a leap year +* Return : false: no leap year, true: leap year +*******************************************************************************/ +int leap_year_check(int year) +{ + 8000e90: b480 push {r7} + 8000e92: b083 sub sp, #12 + 8000e94: af00 add r7, sp, #0 + 8000e96: 6078 str r0, [r7, #4] + if((year % 4 == 0 && year % 100 != 0) || (year % 400 == 0)) + 8000e98: 687b ldr r3, [r7, #4] + 8000e9a: f003 0303 and.w r3, r3, #3 + 8000e9e: 2b00 cmp r3, #0 + 8000ea0: d10c bne.n 8000ebc + 8000ea2: 687a ldr r2, [r7, #4] + 8000ea4: 4b11 ldr r3, [pc, #68] ; (8000eec ) + 8000ea6: fb83 1302 smull r1, r3, r3, r2 + 8000eaa: 1159 asrs r1, r3, #5 + 8000eac: 17d3 asrs r3, r2, #31 + 8000eae: 1acb subs r3, r1, r3 + 8000eb0: 2164 movs r1, #100 ; 0x64 + 8000eb2: fb01 f303 mul.w r3, r1, r3 + 8000eb6: 1ad3 subs r3, r2, r3 + 8000eb8: 2b00 cmp r3, #0 + 8000eba: d10d bne.n 8000ed8 + 8000ebc: 687a ldr r2, [r7, #4] + 8000ebe: 4b0b ldr r3, [pc, #44] ; (8000eec ) + 8000ec0: fb83 1302 smull r1, r3, r3, r2 + 8000ec4: 11d9 asrs r1, r3, #7 + 8000ec6: 17d3 asrs r3, r2, #31 + 8000ec8: 1acb subs r3, r1, r3 + 8000eca: f44f 71c8 mov.w r1, #400 ; 0x190 + 8000ece: fb01 f303 mul.w r3, r1, r3 + 8000ed2: 1ad3 subs r3, r2, r3 + 8000ed4: 2b00 cmp r3, #0 + 8000ed6: d101 bne.n 8000edc + { + return true; + 8000ed8: 2301 movs r3, #1 + 8000eda: e000 b.n 8000ede + } + return false; + 8000edc: 2300 movs r3, #0 +} + 8000ede: 4618 mov r0, r3 + 8000ee0: 370c adds r7, #12 + 8000ee2: 46bd mov sp, r7 + 8000ee4: f85d 7b04 ldr.w r7, [sp], #4 + 8000ee8: 4770 bx lr + 8000eea: bf00 nop + 8000eec: 51eb851f .word 0x51eb851f + +08000ef0 : +* Description : calculates the day of year +* Return : day of year (1.1.. = 1, 2.1.. = 2,...) +* Source : https://overiq.com/c-examples/c-program-to-calculate-the-day-of-year-from-the-date/ +*******************************************************************************/ +int calc_day_of_year(int day, int mon, int year) +{ + 8000ef0: b580 push {r7, lr} + 8000ef2: b088 sub sp, #32 + 8000ef4: af00 add r7, sp, #0 + 8000ef6: 60f8 str r0, [r7, #12] + 8000ef8: 60b9 str r1, [r7, #8] + 8000efa: 607a str r2, [r7, #4] + int days_in_feb = 28; + 8000efc: 231c movs r3, #28 + 8000efe: 61fb str r3, [r7, #28] + int doy = day; //day of year + 8000f00: 68fb ldr r3, [r7, #12] + 8000f02: 61bb str r3, [r7, #24] + + // check for leap year + bool leap_year = leap_year_check(year); + 8000f04: 6878 ldr r0, [r7, #4] + 8000f06: f7ff ffc3 bl 8000e90 + 8000f0a: 4603 mov r3, r0 + 8000f0c: 2b00 cmp r3, #0 + 8000f0e: bf14 ite ne + 8000f10: 2301 movne r3, #1 + 8000f12: 2300 moveq r3, #0 + 8000f14: 75fb strb r3, [r7, #23] + if(leap_year == true) + 8000f16: 7dfb ldrb r3, [r7, #23] + 8000f18: 2b00 cmp r3, #0 + 8000f1a: d001 beq.n 8000f20 + { + days_in_feb = 29; + 8000f1c: 231d movs r3, #29 + 8000f1e: 61fb str r3, [r7, #28] + } + + switch(mon) + 8000f20: 68bb ldr r3, [r7, #8] + 8000f22: 3b02 subs r3, #2 + 8000f24: 2b0a cmp r3, #10 + 8000f26: d85b bhi.n 8000fe0 + 8000f28: a201 add r2, pc, #4 ; (adr r2, 8000f30 ) + 8000f2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8000f2e: bf00 nop + 8000f30: 08000f5d .word 0x08000f5d + 8000f34: 08000f65 .word 0x08000f65 + 8000f38: 08000f71 .word 0x08000f71 + 8000f3c: 08000f7d .word 0x08000f7d + 8000f40: 08000f89 .word 0x08000f89 + 8000f44: 08000f95 .word 0x08000f95 + 8000f48: 08000fa1 .word 0x08000fa1 + 8000f4c: 08000fad .word 0x08000fad + 8000f50: 08000fb9 .word 0x08000fb9 + 8000f54: 08000fc5 .word 0x08000fc5 + 8000f58: 08000fd3 .word 0x08000fd3 + { + case 2: + doy += 31; + 8000f5c: 69bb ldr r3, [r7, #24] + 8000f5e: 331f adds r3, #31 + 8000f60: 61bb str r3, [r7, #24] + break; + 8000f62: e03d b.n 8000fe0 + case 3: + doy += 31+days_in_feb; + 8000f64: 69fb ldr r3, [r7, #28] + 8000f66: 331f adds r3, #31 + 8000f68: 69ba ldr r2, [r7, #24] + 8000f6a: 4413 add r3, r2 + 8000f6c: 61bb str r3, [r7, #24] + break; + 8000f6e: e037 b.n 8000fe0 + case 4: + doy += days_in_feb+62; + 8000f70: 69fb ldr r3, [r7, #28] + 8000f72: 333e adds r3, #62 ; 0x3e + 8000f74: 69ba ldr r2, [r7, #24] + 8000f76: 4413 add r3, r2 + 8000f78: 61bb str r3, [r7, #24] + break; + 8000f7a: e031 b.n 8000fe0 + case 5: + doy += days_in_feb+92; + 8000f7c: 69fb ldr r3, [r7, #28] + 8000f7e: 335c adds r3, #92 ; 0x5c + 8000f80: 69ba ldr r2, [r7, #24] + 8000f82: 4413 add r3, r2 + 8000f84: 61bb str r3, [r7, #24] + break; + 8000f86: e02b b.n 8000fe0 + case 6: + doy += days_in_feb+123; + 8000f88: 69fb ldr r3, [r7, #28] + 8000f8a: 337b adds r3, #123 ; 0x7b + 8000f8c: 69ba ldr r2, [r7, #24] + 8000f8e: 4413 add r3, r2 + 8000f90: 61bb str r3, [r7, #24] + break; + 8000f92: e025 b.n 8000fe0 + case 7: + doy += days_in_feb+153; + 8000f94: 69fb ldr r3, [r7, #28] + 8000f96: 3399 adds r3, #153 ; 0x99 + 8000f98: 69ba ldr r2, [r7, #24] + 8000f9a: 4413 add r3, r2 + 8000f9c: 61bb str r3, [r7, #24] + break; + 8000f9e: e01f b.n 8000fe0 + case 8: + doy += days_in_feb+184; + 8000fa0: 69fb ldr r3, [r7, #28] + 8000fa2: 33b8 adds r3, #184 ; 0xb8 + 8000fa4: 69ba ldr r2, [r7, #24] + 8000fa6: 4413 add r3, r2 + 8000fa8: 61bb str r3, [r7, #24] + break; + 8000faa: e019 b.n 8000fe0 + case 9: + doy += days_in_feb+215; + 8000fac: 69fb ldr r3, [r7, #28] + 8000fae: 33d7 adds r3, #215 ; 0xd7 + 8000fb0: 69ba ldr r2, [r7, #24] + 8000fb2: 4413 add r3, r2 + 8000fb4: 61bb str r3, [r7, #24] + break; + 8000fb6: e013 b.n 8000fe0 + case 10: + doy += days_in_feb+245; + 8000fb8: 69fb ldr r3, [r7, #28] + 8000fba: 33f5 adds r3, #245 ; 0xf5 + 8000fbc: 69ba ldr r2, [r7, #24] + 8000fbe: 4413 add r3, r2 + 8000fc0: 61bb str r3, [r7, #24] + break; + 8000fc2: e00d b.n 8000fe0 + case 11: + doy += days_in_feb+276; + 8000fc4: 69fb ldr r3, [r7, #28] + 8000fc6: f503 738a add.w r3, r3, #276 ; 0x114 + 8000fca: 69ba ldr r2, [r7, #24] + 8000fcc: 4413 add r3, r2 + 8000fce: 61bb str r3, [r7, #24] + break; + 8000fd0: e006 b.n 8000fe0 + case 12: + doy += days_in_feb+306; + 8000fd2: 69fb ldr r3, [r7, #28] + 8000fd4: f503 7399 add.w r3, r3, #306 ; 0x132 + 8000fd8: 69ba ldr r2, [r7, #24] + 8000fda: 4413 add r3, r2 + 8000fdc: 61bb str r3, [r7, #24] + break; + 8000fde: bf00 nop + } + return doy; + 8000fe0: 69bb ldr r3, [r7, #24] +} + 8000fe2: 4618 mov r0, r3 + 8000fe4: 3720 adds r7, #32 + 8000fe6: 46bd mov sp, r7 + 8000fe8: bd80 pop {r7, pc} + 8000fea: bf00 nop + 8000fec: 0000 movs r0, r0 + ... + +08000ff0 : +* Function Name : calc_sunrise_sunset +* Description : calculates the sunrise and sunset time of a specific date +* Source : General Solar Position Calculations, NOAA Global Monitoring Division +*******************************************************************************/ +void calc_sunrise_sunset(int date, int month, int year, int sunrise_time[2], int sunset_time[2]) +{ + 8000ff0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 8000ff4: b0a3 sub sp, #140 ; 0x8c + 8000ff6: af00 add r7, sp, #0 + 8000ff8: 60f8 str r0, [r7, #12] + 8000ffa: 60b9 str r1, [r7, #8] + 8000ffc: 607a str r2, [r7, #4] + 8000ffe: 603b str r3, [r7, #0] + double gamma = 0; + 8001000: f04f 0300 mov.w r3, #0 + 8001004: f04f 0400 mov.w r4, #0 + 8001008: e9c7 3420 strd r3, r4, [r7, #128] ; 0x80 + bool leap_year; + double eqtime = 0; + 800100c: f04f 0300 mov.w r3, #0 + 8001010: f04f 0400 mov.w r4, #0 + 8001014: e9c7 341a strd r3, r4, [r7, #104] ; 0x68 + double decl = 0; + 8001018: f04f 0300 mov.w r3, #0 + 800101c: f04f 0400 mov.w r4, #0 + 8001020: e9c7 3418 strd r3, r4, [r7, #96] ; 0x60 + double decl_deg = 0; + 8001024: f04f 0300 mov.w r3, #0 + 8001028: f04f 0400 mov.w r4, #0 + 800102c: e9c7 3416 strd r3, r4, [r7, #88] ; 0x58 + double zenith_sun = 0; + 8001030: f04f 0300 mov.w r3, #0 + 8001034: f04f 0400 mov.w r4, #0 + 8001038: e9c7 3414 strd r3, r4, [r7, #80] ; 0x50 + double lat_nbg_rad = 0; + 800103c: f04f 0300 mov.w r3, #0 + 8001040: f04f 0400 mov.w r4, #0 + 8001044: e9c7 3412 strd r3, r4, [r7, #72] ; 0x48 + double ha = 0; + 8001048: f04f 0300 mov.w r3, #0 + 800104c: f04f 0400 mov.w r4, #0 + 8001050: e9c7 3410 strd r3, r4, [r7, #64] ; 0x40 + double sunrise = 0; + 8001054: f04f 0300 mov.w r3, #0 + 8001058: f04f 0400 mov.w r4, #0 + 800105c: e9c7 340e strd r3, r4, [r7, #56] ; 0x38 + double sunset = 0; + 8001060: f04f 0300 mov.w r3, #0 + 8001064: f04f 0400 mov.w r4, #0 + 8001068: e9c7 340c strd r3, r4, [r7, #48] ; 0x30 + double ha_deg = 0; + 800106c: f04f 0300 mov.w r3, #0 + 8001070: f04f 0400 mov.w r4, #0 + 8001074: e9c7 340a strd r3, r4, [r7, #40] ; 0x28 + int sunrise_h = 0; + 8001078: 2300 movs r3, #0 + 800107a: 67fb str r3, [r7, #124] ; 0x7c + int sunset_h = 0; + 800107c: 2300 movs r3, #0 + 800107e: 67bb str r3, [r7, #120] ; 0x78 + double sunrise_min = 0; + 8001080: f04f 0300 mov.w r3, #0 + 8001084: f04f 0400 mov.w r4, #0 + 8001088: e9c7 3408 strd r3, r4, [r7, #32] + double sunset_min = 0; + 800108c: f04f 0300 mov.w r3, #0 + 8001090: f04f 0400 mov.w r4, #0 + 8001094: e9c7 3406 strd r3, r4, [r7, #24] + int int_sunrise_min = 0; + 8001098: 2300 movs r3, #0 + 800109a: 677b str r3, [r7, #116] ; 0x74 + int int_sunset_min = 0; + 800109c: 2300 movs r3, #0 + 800109e: 673b str r3, [r7, #112] ; 0x70 + + //day of year calculation + int day_of_year = calc_day_of_year(date, month, year); + 80010a0: 687a ldr r2, [r7, #4] + 80010a2: 68b9 ldr r1, [r7, #8] + 80010a4: 68f8 ldr r0, [r7, #12] + 80010a6: f7ff ff23 bl 8000ef0 + 80010aa: 6178 str r0, [r7, #20] + + // fractional year (γ) in radians + // check for leap year + leap_year = leap_year_check(year); + 80010ac: 6878 ldr r0, [r7, #4] + 80010ae: f7ff feef bl 8000e90 + 80010b2: 4603 mov r3, r0 + 80010b4: 2b00 cmp r3, #0 + 80010b6: bf14 ite ne + 80010b8: 2301 movne r3, #1 + 80010ba: 2300 moveq r3, #0 + 80010bc: 74fb strb r3, [r7, #19] + if(leap_year == false) + 80010be: 7cfb ldrb r3, [r7, #19] + 80010c0: f083 0301 eor.w r3, r3, #1 + 80010c4: b2db uxtb r3, r3 + 80010c6: 2b00 cmp r3, #0 + 80010c8: d00f beq.n 80010ea + { + //The back part of the formula was omitted, because there is no difference in the result + gamma = ((2 * M_PI)/365)*(day_of_year - 1); + 80010ca: 697b ldr r3, [r7, #20] + 80010cc: 3b01 subs r3, #1 + 80010ce: 4618 mov r0, r3 + 80010d0: f7ff f9dc bl 800048c <__aeabi_i2d> + 80010d4: f20f 537c addw r3, pc, #1404 ; 0x57c + 80010d8: e9d3 2300 ldrd r2, r3, [r3] + 80010dc: f7ff fa40 bl 8000560 <__aeabi_dmul> + 80010e0: 4603 mov r3, r0 + 80010e2: 460c mov r4, r1 + 80010e4: e9c7 3420 strd r3, r4, [r7, #128] ; 0x80 + 80010e8: e00e b.n 8001108 + } else { + //The back part of the formula was omitted, because there is no difference in the result + gamma = ((2 * M_PI)/366)*(day_of_year - 1); + 80010ea: 697b ldr r3, [r7, #20] + 80010ec: 3b01 subs r3, #1 + 80010ee: 4618 mov r0, r3 + 80010f0: f7ff f9cc bl 800048c <__aeabi_i2d> + 80010f4: f20f 5364 addw r3, pc, #1380 ; 0x564 + 80010f8: e9d3 2300 ldrd r2, r3, [r3] + 80010fc: f7ff fa30 bl 8000560 <__aeabi_dmul> + 8001100: 4603 mov r3, r0 + 8001102: 460c mov r4, r1 + 8001104: e9c7 3420 strd r3, r4, [r7, #128] ; 0x80 + } + + //Equation of time in minutes + eqtime = 229.18*(0.000075 + 0.001868*cos(gamma) - 0.032077*sin(gamma) - 0.014615*cos(2*gamma) - 0.040849*sin(2*gamma)); + 8001108: ed97 0b20 vldr d0, [r7, #128] ; 0x80 + 800110c: f003 f968 bl 80043e0 + 8001110: ec51 0b10 vmov r0, r1, d0 + 8001114: f20f 534c addw r3, pc, #1356 ; 0x54c + 8001118: e9d3 2300 ldrd r2, r3, [r3] + 800111c: f7ff fa20 bl 8000560 <__aeabi_dmul> + 8001120: 4603 mov r3, r0 + 8001122: 460c mov r4, r1 + 8001124: 4618 mov r0, r3 + 8001126: 4621 mov r1, r4 + 8001128: f20f 5340 addw r3, pc, #1344 ; 0x540 + 800112c: e9d3 2300 ldrd r2, r3, [r3] + 8001130: f7ff f860 bl 80001f4 <__adddf3> + 8001134: 4603 mov r3, r0 + 8001136: 460c mov r4, r1 + 8001138: 4625 mov r5, r4 + 800113a: 461c mov r4, r3 + 800113c: ed97 0b20 vldr d0, [r7, #128] ; 0x80 + 8001140: f003 fa16 bl 8004570 + 8001144: ec51 0b10 vmov r0, r1, d0 + 8001148: f20f 5328 addw r3, pc, #1320 ; 0x528 + 800114c: e9d3 2300 ldrd r2, r3, [r3] + 8001150: f7ff fa06 bl 8000560 <__aeabi_dmul> + 8001154: 4602 mov r2, r0 + 8001156: 460b mov r3, r1 + 8001158: 4620 mov r0, r4 + 800115a: 4629 mov r1, r5 + 800115c: f7ff f848 bl 80001f0 <__aeabi_dsub> + 8001160: 4603 mov r3, r0 + 8001162: 460c mov r4, r1 + 8001164: 4625 mov r5, r4 + 8001166: 461c mov r4, r3 + 8001168: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 800116c: 4602 mov r2, r0 + 800116e: 460b mov r3, r1 + 8001170: f7ff f840 bl 80001f4 <__adddf3> + 8001174: 4602 mov r2, r0 + 8001176: 460b mov r3, r1 + 8001178: ec43 2b17 vmov d7, r2, r3 + 800117c: eeb0 0a47 vmov.f32 s0, s14 + 8001180: eef0 0a67 vmov.f32 s1, s15 + 8001184: f003 f92c bl 80043e0 + 8001188: ec51 0b10 vmov r0, r1, d0 + 800118c: f20f 43ec addw r3, pc, #1260 ; 0x4ec + 8001190: e9d3 2300 ldrd r2, r3, [r3] + 8001194: f7ff f9e4 bl 8000560 <__aeabi_dmul> + 8001198: 4602 mov r2, r0 + 800119a: 460b mov r3, r1 + 800119c: 4620 mov r0, r4 + 800119e: 4629 mov r1, r5 + 80011a0: f7ff f826 bl 80001f0 <__aeabi_dsub> + 80011a4: 4603 mov r3, r0 + 80011a6: 460c mov r4, r1 + 80011a8: 4625 mov r5, r4 + 80011aa: 461c mov r4, r3 + 80011ac: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 80011b0: 4602 mov r2, r0 + 80011b2: 460b mov r3, r1 + 80011b4: f7ff f81e bl 80001f4 <__adddf3> + 80011b8: 4602 mov r2, r0 + 80011ba: 460b mov r3, r1 + 80011bc: ec43 2b17 vmov d7, r2, r3 + 80011c0: eeb0 0a47 vmov.f32 s0, s14 + 80011c4: eef0 0a67 vmov.f32 s1, s15 + 80011c8: f003 f9d2 bl 8004570 + 80011cc: ec51 0b10 vmov r0, r1, d0 + 80011d0: f20f 43b0 addw r3, pc, #1200 ; 0x4b0 + 80011d4: e9d3 2300 ldrd r2, r3, [r3] + 80011d8: f7ff f9c2 bl 8000560 <__aeabi_dmul> + 80011dc: 4602 mov r2, r0 + 80011de: 460b mov r3, r1 + 80011e0: 4620 mov r0, r4 + 80011e2: 4629 mov r1, r5 + 80011e4: f7ff f804 bl 80001f0 <__aeabi_dsub> + 80011e8: 4603 mov r3, r0 + 80011ea: 460c mov r4, r1 + 80011ec: 4618 mov r0, r3 + 80011ee: 4621 mov r1, r4 + 80011f0: f20f 4398 addw r3, pc, #1176 ; 0x498 + 80011f4: e9d3 2300 ldrd r2, r3, [r3] + 80011f8: f7ff f9b2 bl 8000560 <__aeabi_dmul> + 80011fc: 4603 mov r3, r0 + 80011fe: 460c mov r4, r1 + 8001200: e9c7 341a strd r3, r4, [r7, #104] ; 0x68 + + //Solar declination angle in radians + decl = 0.006918 - 0.399912*cos(gamma) + 0.070257*sin(gamma) - 0.006758*cos(2*gamma) + 0.000907*sin(2*gamma) - 0.002697*cos(3*gamma) + 0.00148*sin(3*gamma); + 8001204: ed97 0b20 vldr d0, [r7, #128] ; 0x80 + 8001208: f003 f8ea bl 80043e0 + 800120c: ec51 0b10 vmov r0, r1, d0 + 8001210: f20f 4380 addw r3, pc, #1152 ; 0x480 + 8001214: e9d3 2300 ldrd r2, r3, [r3] + 8001218: f7ff f9a2 bl 8000560 <__aeabi_dmul> + 800121c: 4603 mov r3, r0 + 800121e: 460c mov r4, r1 + 8001220: 461a mov r2, r3 + 8001222: 4623 mov r3, r4 + 8001224: f20f 4174 addw r1, pc, #1140 ; 0x474 + 8001228: e9d1 0100 ldrd r0, r1, [r1] + 800122c: f7fe ffe0 bl 80001f0 <__aeabi_dsub> + 8001230: 4603 mov r3, r0 + 8001232: 460c mov r4, r1 + 8001234: 4625 mov r5, r4 + 8001236: 461c mov r4, r3 + 8001238: ed97 0b20 vldr d0, [r7, #128] ; 0x80 + 800123c: f003 f998 bl 8004570 + 8001240: ec51 0b10 vmov r0, r1, d0 + 8001244: f20f 435c addw r3, pc, #1116 ; 0x45c + 8001248: e9d3 2300 ldrd r2, r3, [r3] + 800124c: f7ff f988 bl 8000560 <__aeabi_dmul> + 8001250: 4602 mov r2, r0 + 8001252: 460b mov r3, r1 + 8001254: 4620 mov r0, r4 + 8001256: 4629 mov r1, r5 + 8001258: f7fe ffcc bl 80001f4 <__adddf3> + 800125c: 4603 mov r3, r0 + 800125e: 460c mov r4, r1 + 8001260: 4625 mov r5, r4 + 8001262: 461c mov r4, r3 + 8001264: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 8001268: 4602 mov r2, r0 + 800126a: 460b mov r3, r1 + 800126c: f7fe ffc2 bl 80001f4 <__adddf3> + 8001270: 4602 mov r2, r0 + 8001272: 460b mov r3, r1 + 8001274: ec43 2b17 vmov d7, r2, r3 + 8001278: eeb0 0a47 vmov.f32 s0, s14 + 800127c: eef0 0a67 vmov.f32 s1, s15 + 8001280: f003 f8ae bl 80043e0 + 8001284: ec51 0b10 vmov r0, r1, d0 + 8001288: f20f 4320 addw r3, pc, #1056 ; 0x420 + 800128c: e9d3 2300 ldrd r2, r3, [r3] + 8001290: f7ff f966 bl 8000560 <__aeabi_dmul> + 8001294: 4602 mov r2, r0 + 8001296: 460b mov r3, r1 + 8001298: 4620 mov r0, r4 + 800129a: 4629 mov r1, r5 + 800129c: f7fe ffa8 bl 80001f0 <__aeabi_dsub> + 80012a0: 4603 mov r3, r0 + 80012a2: 460c mov r4, r1 + 80012a4: 4625 mov r5, r4 + 80012a6: 461c mov r4, r3 + 80012a8: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 80012ac: 4602 mov r2, r0 + 80012ae: 460b mov r3, r1 + 80012b0: f7fe ffa0 bl 80001f4 <__adddf3> + 80012b4: 4602 mov r2, r0 + 80012b6: 460b mov r3, r1 + 80012b8: ec43 2b17 vmov d7, r2, r3 + 80012bc: eeb0 0a47 vmov.f32 s0, s14 + 80012c0: eef0 0a67 vmov.f32 s1, s15 + 80012c4: f003 f954 bl 8004570 + 80012c8: ec51 0b10 vmov r0, r1, d0 + 80012cc: a3f9 add r3, pc, #996 ; (adr r3, 80016b4 ) + 80012ce: e9d3 2300 ldrd r2, r3, [r3] + 80012d2: f7ff f945 bl 8000560 <__aeabi_dmul> + 80012d6: 4602 mov r2, r0 + 80012d8: 460b mov r3, r1 + 80012da: 4620 mov r0, r4 + 80012dc: 4629 mov r1, r5 + 80012de: f7fe ff89 bl 80001f4 <__adddf3> + 80012e2: 4603 mov r3, r0 + 80012e4: 460c mov r4, r1 + 80012e6: 4625 mov r5, r4 + 80012e8: 461c mov r4, r3 + 80012ea: f04f 0200 mov.w r2, #0 + 80012ee: 4bd0 ldr r3, [pc, #832] ; (8001630 ) + 80012f0: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 80012f4: f7ff f934 bl 8000560 <__aeabi_dmul> + 80012f8: 4602 mov r2, r0 + 80012fa: 460b mov r3, r1 + 80012fc: ec43 2b17 vmov d7, r2, r3 + 8001300: eeb0 0a47 vmov.f32 s0, s14 + 8001304: eef0 0a67 vmov.f32 s1, s15 + 8001308: f003 f86a bl 80043e0 + 800130c: ec51 0b10 vmov r0, r1, d0 + 8001310: a3c1 add r3, pc, #772 ; (adr r3, 8001618 ) + 8001312: e9d3 2300 ldrd r2, r3, [r3] + 8001316: f7ff f923 bl 8000560 <__aeabi_dmul> + 800131a: 4602 mov r2, r0 + 800131c: 460b mov r3, r1 + 800131e: 4620 mov r0, r4 + 8001320: 4629 mov r1, r5 + 8001322: f7fe ff65 bl 80001f0 <__aeabi_dsub> + 8001326: 4603 mov r3, r0 + 8001328: 460c mov r4, r1 + 800132a: 4625 mov r5, r4 + 800132c: 461c mov r4, r3 + 800132e: f04f 0200 mov.w r2, #0 + 8001332: 4bbf ldr r3, [pc, #764] ; (8001630 ) + 8001334: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 8001338: f7ff f912 bl 8000560 <__aeabi_dmul> + 800133c: 4602 mov r2, r0 + 800133e: 460b mov r3, r1 + 8001340: ec43 2b17 vmov d7, r2, r3 + 8001344: eeb0 0a47 vmov.f32 s0, s14 + 8001348: eef0 0a67 vmov.f32 s1, s15 + 800134c: f003 f910 bl 8004570 + 8001350: ec51 0b10 vmov r0, r1, d0 + 8001354: a3b2 add r3, pc, #712 ; (adr r3, 8001620 ) + 8001356: e9d3 2300 ldrd r2, r3, [r3] + 800135a: f7ff f901 bl 8000560 <__aeabi_dmul> + 800135e: 4602 mov r2, r0 + 8001360: 460b mov r3, r1 + 8001362: 4620 mov r0, r4 + 8001364: 4629 mov r1, r5 + 8001366: f7fe ff45 bl 80001f4 <__adddf3> + 800136a: 4603 mov r3, r0 + 800136c: 460c mov r4, r1 + 800136e: e9c7 3418 strd r3, r4, [r7, #96] ; 0x60 + + //Solar declination angle in degrees + decl_deg = rad_to_deg(decl); + 8001372: ed97 0b18 vldr d0, [r7, #96] ; 0x60 + 8001376: f7ff fd6b bl 8000e50 + 800137a: ed87 0b16 vstr d0, [r7, #88] ; 0x58 + + //Hour angle in degrees, positive number corresponds to sunrise, negative to sunset + //special case of sunrise or sunset, the zenith is set to 90.833Deg + zenith_sun = deg_to_rad(90.833); + 800137e: ed9f 0baa vldr d0, [pc, #680] ; 8001628 + 8001382: f7ff fd45 bl 8000e10 + 8001386: ed87 0b14 vstr d0, [r7, #80] ; 0x50 + //Latitude of Nuernberg in rad + lat_nbg_rad = deg_to_rad(latitude_nbg); + 800138a: 4baa ldr r3, [pc, #680] ; (8001634 ) + 800138c: 681b ldr r3, [r3, #0] + 800138e: 4618 mov r0, r3 + 8001390: f7ff f87c bl 800048c <__aeabi_i2d> + 8001394: 4603 mov r3, r0 + 8001396: 460c mov r4, r1 + 8001398: ec44 3b10 vmov d0, r3, r4 + 800139c: f7ff fd38 bl 8000e10 + 80013a0: ed87 0b12 vstr d0, [r7, #72] ; 0x48 + ha = acos((cos(zenith_sun)/(cos(lat_nbg_rad)*cos(decl)))-(tan(lat_nbg_rad)*tan(decl))); + 80013a4: ed97 0b14 vldr d0, [r7, #80] ; 0x50 + 80013a8: f003 f81a bl 80043e0 + 80013ac: ec56 5b10 vmov r5, r6, d0 + 80013b0: ed97 0b12 vldr d0, [r7, #72] ; 0x48 + 80013b4: f003 f814 bl 80043e0 + 80013b8: ec59 8b10 vmov r8, r9, d0 + 80013bc: ed97 0b18 vldr d0, [r7, #96] ; 0x60 + 80013c0: f003 f80e bl 80043e0 + 80013c4: ec54 3b10 vmov r3, r4, d0 + 80013c8: 461a mov r2, r3 + 80013ca: 4623 mov r3, r4 + 80013cc: 4640 mov r0, r8 + 80013ce: 4649 mov r1, r9 + 80013d0: f7ff f8c6 bl 8000560 <__aeabi_dmul> + 80013d4: 4603 mov r3, r0 + 80013d6: 460c mov r4, r1 + 80013d8: 461a mov r2, r3 + 80013da: 4623 mov r3, r4 + 80013dc: 4628 mov r0, r5 + 80013de: 4631 mov r1, r6 + 80013e0: f7ff f9e8 bl 80007b4 <__aeabi_ddiv> + 80013e4: 4603 mov r3, r0 + 80013e6: 460c mov r4, r1 + 80013e8: 4625 mov r5, r4 + 80013ea: 461c mov r4, r3 + 80013ec: ed97 0b12 vldr d0, [r7, #72] ; 0x48 + 80013f0: f003 f906 bl 8004600 + 80013f4: ec59 8b10 vmov r8, r9, d0 + 80013f8: ed97 0b18 vldr d0, [r7, #96] ; 0x60 + 80013fc: f003 f900 bl 8004600 + 8001400: ec53 2b10 vmov r2, r3, d0 + 8001404: 4640 mov r0, r8 + 8001406: 4649 mov r1, r9 + 8001408: f7ff f8aa bl 8000560 <__aeabi_dmul> + 800140c: 4602 mov r2, r0 + 800140e: 460b mov r3, r1 + 8001410: 4620 mov r0, r4 + 8001412: 4629 mov r1, r5 + 8001414: f7fe feec bl 80001f0 <__aeabi_dsub> + 8001418: 4603 mov r3, r0 + 800141a: 460c mov r4, r1 + 800141c: ec44 3b17 vmov d7, r3, r4 + 8001420: eeb0 0a47 vmov.f32 s0, s14 + 8001424: eef0 0a67 vmov.f32 s1, s15 + 8001428: f003 f91a bl 8004660 + 800142c: ed87 0b10 vstr d0, [r7, #64] ; 0x40 + ha_deg = rad_to_deg(ha); + 8001430: ed97 0b10 vldr d0, [r7, #64] ; 0x40 + 8001434: f7ff fd0c bl 8000e50 + 8001438: ed87 0b0a vstr d0, [r7, #40] ; 0x28 + + //UTC time of sunrise (or sunset) in minutes + sunrise = (720-4*(longitude_nbg+ha_deg)-eqtime); + 800143c: 4b7e ldr r3, [pc, #504] ; (8001638 ) + 800143e: 681b ldr r3, [r3, #0] + 8001440: 4618 mov r0, r3 + 8001442: f7ff f823 bl 800048c <__aeabi_i2d> + 8001446: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 + 800144a: f7fe fed3 bl 80001f4 <__adddf3> + 800144e: 4603 mov r3, r0 + 8001450: 460c mov r4, r1 + 8001452: 4618 mov r0, r3 + 8001454: 4621 mov r1, r4 + 8001456: f04f 0200 mov.w r2, #0 + 800145a: 4b78 ldr r3, [pc, #480] ; (800163c ) + 800145c: f7ff f880 bl 8000560 <__aeabi_dmul> + 8001460: 4603 mov r3, r0 + 8001462: 460c mov r4, r1 + 8001464: 461a mov r2, r3 + 8001466: 4623 mov r3, r4 + 8001468: f04f 0000 mov.w r0, #0 + 800146c: 4974 ldr r1, [pc, #464] ; (8001640 ) + 800146e: f7fe febf bl 80001f0 <__aeabi_dsub> + 8001472: 4603 mov r3, r0 + 8001474: 460c mov r4, r1 + 8001476: 4618 mov r0, r3 + 8001478: 4621 mov r1, r4 + 800147a: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 + 800147e: f7fe feb7 bl 80001f0 <__aeabi_dsub> + 8001482: 4603 mov r3, r0 + 8001484: 460c mov r4, r1 + 8001486: e9c7 340e strd r3, r4, [r7, #56] ; 0x38 + sunset = 720-4*(longitude_nbg-ha_deg)-eqtime; + 800148a: 4b6b ldr r3, [pc, #428] ; (8001638 ) + 800148c: 681b ldr r3, [r3, #0] + 800148e: 4618 mov r0, r3 + 8001490: f7fe fffc bl 800048c <__aeabi_i2d> + 8001494: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 + 8001498: f7fe feaa bl 80001f0 <__aeabi_dsub> + 800149c: 4603 mov r3, r0 + 800149e: 460c mov r4, r1 + 80014a0: 4618 mov r0, r3 + 80014a2: 4621 mov r1, r4 + 80014a4: f04f 0200 mov.w r2, #0 + 80014a8: 4b64 ldr r3, [pc, #400] ; (800163c ) + 80014aa: f7ff f859 bl 8000560 <__aeabi_dmul> + 80014ae: 4603 mov r3, r0 + 80014b0: 460c mov r4, r1 + 80014b2: 461a mov r2, r3 + 80014b4: 4623 mov r3, r4 + 80014b6: f04f 0000 mov.w r0, #0 + 80014ba: 4961 ldr r1, [pc, #388] ; (8001640 ) + 80014bc: f7fe fe98 bl 80001f0 <__aeabi_dsub> + 80014c0: 4603 mov r3, r0 + 80014c2: 460c mov r4, r1 + 80014c4: 4618 mov r0, r3 + 80014c6: 4621 mov r1, r4 + 80014c8: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 + 80014cc: f7fe fe90 bl 80001f0 <__aeabi_dsub> + 80014d0: 4603 mov r3, r0 + 80014d2: 460c mov r4, r1 + 80014d4: e9c7 340c strd r3, r4, [r7, #48] ; 0x30 + + //Convert sunrise (or sunset) UTC time in hours + sunrise = sunrise/60; + 80014d8: f04f 0200 mov.w r2, #0 + 80014dc: 4b59 ldr r3, [pc, #356] ; (8001644 ) + 80014de: e9d7 010e ldrd r0, r1, [r7, #56] ; 0x38 + 80014e2: f7ff f967 bl 80007b4 <__aeabi_ddiv> + 80014e6: 4603 mov r3, r0 + 80014e8: 460c mov r4, r1 + 80014ea: e9c7 340e strd r3, r4, [r7, #56] ; 0x38 + sunset = sunset/60; + 80014ee: f04f 0200 mov.w r2, #0 + 80014f2: 4b54 ldr r3, [pc, #336] ; (8001644 ) + 80014f4: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 80014f8: f7ff f95c bl 80007b4 <__aeabi_ddiv> + 80014fc: 4603 mov r3, r0 + 80014fe: 460c mov r4, r1 + 8001500: e9c7 340c strd r3, r4, [r7, #48] ; 0x30 + + //Seperate hours and minutes + sunrise_h = floor(sunrise); + 8001504: ed97 0b0e vldr d0, [r7, #56] ; 0x38 + 8001508: f002 ffae bl 8004468 + 800150c: ec54 3b10 vmov r3, r4, d0 + 8001510: 4618 mov r0, r3 + 8001512: 4621 mov r1, r4 + 8001514: f7ff fad4 bl 8000ac0 <__aeabi_d2iz> + 8001518: 4603 mov r3, r0 + 800151a: 67fb str r3, [r7, #124] ; 0x7c + sunrise_min = sunrise - sunrise_h; + 800151c: 6ff8 ldr r0, [r7, #124] ; 0x7c + 800151e: f7fe ffb5 bl 800048c <__aeabi_i2d> + 8001522: 4603 mov r3, r0 + 8001524: 460c mov r4, r1 + 8001526: 461a mov r2, r3 + 8001528: 4623 mov r3, r4 + 800152a: e9d7 010e ldrd r0, r1, [r7, #56] ; 0x38 + 800152e: f7fe fe5f bl 80001f0 <__aeabi_dsub> + 8001532: 4603 mov r3, r0 + 8001534: 460c mov r4, r1 + 8001536: e9c7 3408 strd r3, r4, [r7, #32] + //Cut off after two decimal places + int_sunrise_min = floor(sunrise_min * 100.0); + 800153a: f04f 0200 mov.w r2, #0 + 800153e: 4b42 ldr r3, [pc, #264] ; (8001648 ) + 8001540: e9d7 0108 ldrd r0, r1, [r7, #32] + 8001544: f7ff f80c bl 8000560 <__aeabi_dmul> + 8001548: 4603 mov r3, r0 + 800154a: 460c mov r4, r1 + 800154c: ec44 3b17 vmov d7, r3, r4 + 8001550: eeb0 0a47 vmov.f32 s0, s14 + 8001554: eef0 0a67 vmov.f32 s1, s15 + 8001558: f002 ff86 bl 8004468 + 800155c: ec54 3b10 vmov r3, r4, d0 + 8001560: 4618 mov r0, r3 + 8001562: 4621 mov r1, r4 + 8001564: f7ff faac bl 8000ac0 <__aeabi_d2iz> + 8001568: 4603 mov r3, r0 + 800156a: 677b str r3, [r7, #116] ; 0x74 + if (int_sunrise_min >= 60) + 800156c: 6f7b ldr r3, [r7, #116] ; 0x74 + 800156e: 2b3b cmp r3, #59 ; 0x3b + 8001570: dd05 ble.n 800157e + { + sunrise_h = sunrise_h + 1; + 8001572: 6ffb ldr r3, [r7, #124] ; 0x7c + 8001574: 3301 adds r3, #1 + 8001576: 67fb str r3, [r7, #124] ; 0x7c + int_sunrise_min = int_sunrise_min - 60; + 8001578: 6f7b ldr r3, [r7, #116] ; 0x74 + 800157a: 3b3c subs r3, #60 ; 0x3c + 800157c: 677b str r3, [r7, #116] ; 0x74 + } + sunset_h = floor(sunset); + 800157e: ed97 0b0c vldr d0, [r7, #48] ; 0x30 + 8001582: f002 ff71 bl 8004468 + 8001586: ec54 3b10 vmov r3, r4, d0 + 800158a: 4618 mov r0, r3 + 800158c: 4621 mov r1, r4 + 800158e: f7ff fa97 bl 8000ac0 <__aeabi_d2iz> + 8001592: 4603 mov r3, r0 + 8001594: 67bb str r3, [r7, #120] ; 0x78 + sunset_min = sunset - sunset_h; + 8001596: 6fb8 ldr r0, [r7, #120] ; 0x78 + 8001598: f7fe ff78 bl 800048c <__aeabi_i2d> + 800159c: 4603 mov r3, r0 + 800159e: 460c mov r4, r1 + 80015a0: 461a mov r2, r3 + 80015a2: 4623 mov r3, r4 + 80015a4: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 + 80015a8: f7fe fe22 bl 80001f0 <__aeabi_dsub> + 80015ac: 4603 mov r3, r0 + 80015ae: 460c mov r4, r1 + 80015b0: e9c7 3406 strd r3, r4, [r7, #24] + //Cut off after two decimal places + int_sunset_min = floor(sunset_min * 100.0); + 80015b4: f04f 0200 mov.w r2, #0 + 80015b8: 4b23 ldr r3, [pc, #140] ; (8001648 ) + 80015ba: e9d7 0106 ldrd r0, r1, [r7, #24] + 80015be: f7fe ffcf bl 8000560 <__aeabi_dmul> + 80015c2: 4603 mov r3, r0 + 80015c4: 460c mov r4, r1 + 80015c6: ec44 3b17 vmov d7, r3, r4 + 80015ca: eeb0 0a47 vmov.f32 s0, s14 + 80015ce: eef0 0a67 vmov.f32 s1, s15 + 80015d2: f002 ff49 bl 8004468 + 80015d6: ec54 3b10 vmov r3, r4, d0 + 80015da: 4618 mov r0, r3 + 80015dc: 4621 mov r1, r4 + 80015de: f7ff fa6f bl 8000ac0 <__aeabi_d2iz> + 80015e2: 4603 mov r3, r0 + 80015e4: 673b str r3, [r7, #112] ; 0x70 + if (int_sunset_min >= 60) + 80015e6: 6f3b ldr r3, [r7, #112] ; 0x70 + 80015e8: 2b3b cmp r3, #59 ; 0x3b + 80015ea: dd05 ble.n 80015f8 + { + sunset_h = sunset_h + 1; + 80015ec: 6fbb ldr r3, [r7, #120] ; 0x78 + 80015ee: 3301 adds r3, #1 + 80015f0: 67bb str r3, [r7, #120] ; 0x78 + int_sunset_min = int_sunset_min - 60; + 80015f2: 6f3b ldr r3, [r7, #112] ; 0x70 + 80015f4: 3b3c subs r3, #60 ; 0x3c + 80015f6: 673b str r3, [r7, #112] ; 0x70 + } + + //Add time difference from German time to UTC Time + //Private variable winterTime must be initialized accordingly + if (winterTime) + 80015f8: 4b14 ldr r3, [pc, #80] ; (800164c ) + 80015fa: 781b ldrb r3, [r3, #0] + 80015fc: 2b00 cmp r3, #0 + 80015fe: d05d beq.n 80016bc + { + sunrise_h = sunrise_h + UTC_DER_win; + 8001600: 4b13 ldr r3, [pc, #76] ; (8001650 ) + 8001602: 681b ldr r3, [r3, #0] + 8001604: 6ffa ldr r2, [r7, #124] ; 0x7c + 8001606: 4413 add r3, r2 + 8001608: 67fb str r3, [r7, #124] ; 0x7c + sunset_h = sunset_h + UTC_DER_win; + 800160a: 4b11 ldr r3, [pc, #68] ; (8001650 ) + 800160c: 681b ldr r3, [r3, #0] + 800160e: 6fba ldr r2, [r7, #120] ; 0x78 + 8001610: 4413 add r3, r2 + 8001612: 67bb str r3, [r7, #120] ; 0x78 + 8001614: e05c b.n 80016d0 + 8001616: bf00 nop + 8001618: d9839475 .word 0xd9839475 + 800161c: 3f661804 .word 0x3f661804 + 8001620: e646f156 .word 0xe646f156 + 8001624: 3f583f91 .word 0x3f583f91 + 8001628: df3b645a .word 0xdf3b645a + 800162c: 4056b54f .word 0x4056b54f + 8001630: 40080000 .word 0x40080000 + 8001634: 20000000 .word 0x20000000 + 8001638: 20000004 .word 0x20000004 + 800163c: 40100000 .word 0x40100000 + 8001640: 40868000 .word 0x40868000 + 8001644: 404e0000 .word 0x404e0000 + 8001648: 40590000 .word 0x40590000 + 800164c: 20000010 .word 0x20000010 + 8001650: 2000000c .word 0x2000000c + 8001654: d4b3ac9a .word 0xd4b3ac9a + 8001658: 3f91a099 .word 0x3f91a099 + 800165c: 79e42523 .word 0x79e42523 + 8001660: 3f919445 .word 0x3f919445 + 8001664: ba2be059 .word 0xba2be059 + 8001668: 3f5e9af5 .word 0x3f5e9af5 + 800166c: 30553261 .word 0x30553261 + 8001670: 3f13a92a .word 0x3f13a92a + 8001674: 83e8576d .word 0x83e8576d + 8001678: 3fa06c65 .word 0x3fa06c65 + 800167c: 183f91e6 .word 0x183f91e6 + 8001680: 3f8dee78 .word 0x3f8dee78 + 8001684: fe260b2d .word 0xfe260b2d + 8001688: 3fa4ea28 .word 0x3fa4ea28 + 800168c: 8f5c28f6 .word 0x8f5c28f6 + 8001690: 406ca5c2 .word 0x406ca5c2 + 8001694: 8051c9f7 .word 0x8051c9f7 + 8001698: 3fd99828 .word 0x3fd99828 + 800169c: 7c0f4517 .word 0x7c0f4517 + 80016a0: 3f7c560c .word 0x3f7c560c + 80016a4: dd50a88f .word 0xdd50a88f + 80016a8: 3fb1fc5c .word 0x3fb1fc5c + 80016ac: cfc829d0 .word 0xcfc829d0 + 80016b0: 3f7bae46 .word 0x3f7bae46 + 80016b4: ab324852 .word 0xab324852 + 80016b8: 3f4db877 .word 0x3f4db877 + } else { + sunrise_h = sunrise_h + UTC_DER_sum; + 80016bc: 4b0f ldr r3, [pc, #60] ; (80016fc ) + 80016be: 681b ldr r3, [r3, #0] + 80016c0: 6ffa ldr r2, [r7, #124] ; 0x7c + 80016c2: 4413 add r3, r2 + 80016c4: 67fb str r3, [r7, #124] ; 0x7c + sunset_h = sunset_h + UTC_DER_sum; + 80016c6: 4b0d ldr r3, [pc, #52] ; (80016fc ) + 80016c8: 681b ldr r3, [r3, #0] + 80016ca: 6fba ldr r2, [r7, #120] ; 0x78 + 80016cc: 4413 add r3, r2 + 80016ce: 67bb str r3, [r7, #120] ; 0x78 + } + + sunrise_time[0] = sunrise_h; + 80016d0: 683b ldr r3, [r7, #0] + 80016d2: 6ffa ldr r2, [r7, #124] ; 0x7c + 80016d4: 601a str r2, [r3, #0] + sunrise_time[1] = int_sunrise_min; + 80016d6: 683b ldr r3, [r7, #0] + 80016d8: 3304 adds r3, #4 + 80016da: 6f7a ldr r2, [r7, #116] ; 0x74 + 80016dc: 601a str r2, [r3, #0] + sunset_time[0] = sunset_h; + 80016de: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 80016e2: 6fba ldr r2, [r7, #120] ; 0x78 + 80016e4: 601a str r2, [r3, #0] + sunset_time[1] = int_sunset_min; + 80016e6: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 80016ea: 3304 adds r3, #4 + 80016ec: 6f3a ldr r2, [r7, #112] ; 0x70 + 80016ee: 601a str r2, [r3, #0] +} + 80016f0: bf00 nop + 80016f2: 378c adds r7, #140 ; 0x8c + 80016f4: 46bd mov sp, r7 + 80016f6: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 80016fa: bf00 nop + 80016fc: 20000008 .word 0x20000008 + +08001700 : +* Function Name : calc_tomorrows_date +* Description : calculates tomorrow's date +* Source : https://github.com/vyacht/stm32/blob/master/vynmea/rtc.c +*******************************************************************************/ +void calc_tomorrows_date(int day, int wday, int month, int year, int DaysInMonth[12], int tomorrows_date[4]) +{ + 8001700: b480 push {r7} + 8001702: b085 sub sp, #20 + 8001704: af00 add r7, sp, #0 + 8001706: 60f8 str r0, [r7, #12] + 8001708: 60b9 str r1, [r7, #8] + 800170a: 607a str r2, [r7, #4] + 800170c: 603b str r3, [r7, #0] + bool leap_year; + + day++; // next day + 800170e: 68fb ldr r3, [r7, #12] + 8001710: 3301 adds r3, #1 + 8001712: 60fb str r3, [r7, #12] + wday++; // next weekday + 8001714: 68bb ldr r3, [r7, #8] + 8001716: 3301 adds r3, #1 + 8001718: 60bb str r3, [r7, #8] + if(wday == 8) + 800171a: 68bb ldr r3, [r7, #8] + 800171c: 2b08 cmp r3, #8 + 800171e: d101 bne.n 8001724 + { + wday = 1; // Monday + 8001720: 2301 movs r3, #1 + 8001722: 60bb str r3, [r7, #8] + } + if(day > DaysInMonth[month-1]) + 8001724: 687b ldr r3, [r7, #4] + 8001726: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 + 800172a: 3b01 subs r3, #1 + 800172c: 009b lsls r3, r3, #2 + 800172e: 69ba ldr r2, [r7, #24] + 8001730: 4413 add r3, r2 + 8001732: 681b ldr r3, [r3, #0] + 8001734: 68fa ldr r2, [r7, #12] + 8001736: 429a cmp r2, r3 + 8001738: dd04 ble.n 8001744 + { // next month + day = 1; + 800173a: 2301 movs r3, #1 + 800173c: 60fb str r3, [r7, #12] + month++; + 800173e: 687b ldr r3, [r7, #4] + 8001740: 3301 adds r3, #1 + 8001742: 607b str r3, [r7, #4] + } + if(day > 31 && month == 12) // next year + 8001744: 68fb ldr r3, [r7, #12] + 8001746: 2b1f cmp r3, #31 + 8001748: dd09 ble.n 800175e + 800174a: 687b ldr r3, [r7, #4] + 800174c: 2b0c cmp r3, #12 + 800174e: d106 bne.n 800175e + { + day = 1; + 8001750: 2301 movs r3, #1 + 8001752: 60fb str r3, [r7, #12] + month = 1; + 8001754: 2301 movs r3, #1 + 8001756: 607b str r3, [r7, #4] + year++; + 8001758: 683b ldr r3, [r7, #0] + 800175a: 3301 adds r3, #1 + 800175c: 603b str r3, [r7, #0] + } + + tomorrows_date[0] = day; + 800175e: 69fb ldr r3, [r7, #28] + 8001760: 68fa ldr r2, [r7, #12] + 8001762: 601a str r2, [r3, #0] + tomorrows_date[1] = wday; + 8001764: 69fb ldr r3, [r7, #28] + 8001766: 3304 adds r3, #4 + 8001768: 68ba ldr r2, [r7, #8] + 800176a: 601a str r2, [r3, #0] + tomorrows_date[2] = month; + 800176c: 69fb ldr r3, [r7, #28] + 800176e: 3308 adds r3, #8 + 8001770: 687a ldr r2, [r7, #4] + 8001772: 601a str r2, [r3, #0] + tomorrows_date[3] = year; + 8001774: 69fb ldr r3, [r7, #28] + 8001776: 330c adds r3, #12 + 8001778: 683a ldr r2, [r7, #0] + 800177a: 601a str r2, [r3, #0] + +} + 800177c: bf00 nop + 800177e: 3714 adds r7, #20 + 8001780: 46bd mov sp, r7 + 8001782: f85d 7b04 ldr.w r7, [sp], #4 + 8001786: 4770 bx lr + +08001788 : +/******************************************************************************* +* Function Name : set_Alarm +* Description : sets the wake up Alarm +*******************************************************************************/ +void set_Alarm(int h, int min, int weekDay) +{ + 8001788: b580 push {r7, lr} + 800178a: b084 sub sp, #16 + 800178c: af00 add r7, sp, #0 + 800178e: 60f8 str r0, [r7, #12] + 8001790: 60b9 str r1, [r7, #8] + 8001792: 607a str r2, [r7, #4] + /** Enable the Alarm A*/ + sAlarm.AlarmTime.Hours = h; + 8001794: 68fb ldr r3, [r7, #12] + 8001796: b2da uxtb r2, r3 + 8001798: 4b19 ldr r3, [pc, #100] ; (8001800 ) + 800179a: 701a strb r2, [r3, #0] + sAlarm.AlarmTime.Minutes = min; + 800179c: 68bb ldr r3, [r7, #8] + 800179e: b2da uxtb r2, r3 + 80017a0: 4b17 ldr r3, [pc, #92] ; (8001800 ) + 80017a2: 705a strb r2, [r3, #1] + sAlarm.AlarmTime.Seconds = 0; + 80017a4: 4b16 ldr r3, [pc, #88] ; (8001800 ) + 80017a6: 2200 movs r2, #0 + 80017a8: 709a strb r2, [r3, #2] + sAlarm.AlarmTime.SubSeconds = 0; + 80017aa: 4b15 ldr r3, [pc, #84] ; (8001800 ) + 80017ac: 2200 movs r2, #0 + 80017ae: 605a str r2, [r3, #4] + sAlarm.AlarmTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; + 80017b0: 4b13 ldr r3, [pc, #76] ; (8001800 ) + 80017b2: 2200 movs r2, #0 + 80017b4: 60da str r2, [r3, #12] + sAlarm.AlarmTime.StoreOperation = RTC_STOREOPERATION_RESET; + 80017b6: 4b12 ldr r3, [pc, #72] ; (8001800 ) + 80017b8: 2200 movs r2, #0 + 80017ba: 611a str r2, [r3, #16] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; //only by specific time + 80017bc: 4b10 ldr r3, [pc, #64] ; (8001800 ) + 80017be: 2200 movs r2, #0 + 80017c0: 615a str r2, [r3, #20] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDMASK_ALL; + 80017c2: 4b0f ldr r3, [pc, #60] ; (8001800 ) + 80017c4: 2200 movs r2, #0 + 80017c6: 619a str r2, [r3, #24] + sAlarm.AlarmDateWeekDaySel = RTC_ALARMDATEWEEKDAYSEL_WEEKDAY; + 80017c8: 4b0d ldr r3, [pc, #52] ; (8001800 ) + 80017ca: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 80017ce: 61da str r2, [r3, #28] + sAlarm.AlarmDateWeekDay = weekDay; + 80017d0: 687b ldr r3, [r7, #4] + 80017d2: b2da uxtb r2, r3 + 80017d4: 4b0a ldr r3, [pc, #40] ; (8001800 ) + 80017d6: f883 2020 strb.w r2, [r3, #32] + sAlarm.Alarm = RTC_ALARM_A; + 80017da: 4b09 ldr r3, [pc, #36] ; (8001800 ) + 80017dc: f44f 7280 mov.w r2, #256 ; 0x100 + 80017e0: 625a str r2, [r3, #36] ; 0x24 + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BIN) != HAL_OK) + 80017e2: 2200 movs r2, #0 + 80017e4: 4906 ldr r1, [pc, #24] ; (8001800 ) + 80017e6: 4807 ldr r0, [pc, #28] ; (8001804 ) + 80017e8: f001 ff04 bl 80035f4 + 80017ec: 4603 mov r3, r0 + 80017ee: 2b00 cmp r3, #0 + 80017f0: d001 beq.n 80017f6 + { + Error_Handler(); + 80017f2: f000 fa7d bl 8001cf0 + } +} + 80017f6: bf00 nop + 80017f8: 3710 adds r7, #16 + 80017fa: 46bd mov sp, r7 + 80017fc: bd80 pop {r7, pc} + 80017fe: bf00 nop + 8001800: 200000b8 .word 0x200000b8 + 8001804: 200000e4 .word 0x200000e4 + +08001808 : + +// sending to UART +void transmit_uart(char *string){ + 8001808: b580 push {r7, lr} + 800180a: b084 sub sp, #16 + 800180c: af00 add r7, sp, #0 + 800180e: 6078 str r0, [r7, #4] + uint8_t len = strlen(string); + 8001810: 6878 ldr r0, [r7, #4] + 8001812: f7fe fce1 bl 80001d8 + 8001816: 4603 mov r3, r0 + 8001818: 73fb strb r3, [r7, #15] + HAL_UART_Transmit(&huart2, (uint8_t*) string, len, 200); + 800181a: 7bfb ldrb r3, [r7, #15] + 800181c: b29a uxth r2, r3 + 800181e: 23c8 movs r3, #200 ; 0xc8 + 8001820: 6879 ldr r1, [r7, #4] + 8001822: 4803 ldr r0, [pc, #12] ; (8001830 ) + 8001824: f002 f94b bl 8003abe +} + 8001828: bf00 nop + 800182a: 3710 adds r7, #16 + 800182c: 46bd mov sp, r7 + 800182e: bd80 pop {r7, pc} + 8001830: 20000104 .word 0x20000104 + +08001834
: /** * @brief The application entry point. * @retval int */ int main(void) { - 8000480: b580 push {r7, lr} - 8000482: b082 sub sp, #8 - 8000484: af00 add r7, sp, #0 + 8001834: b5b0 push {r4, r5, r7, lr} + 8001836: b0ae sub sp, #184 ; 0xb8 + 8001838: af02 add r7, sp, #8 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); - 8000486: f000 fa7e bl 8000986 + 800183a: f000 fb6b bl 8001f14 /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); - 800048a: f000 f843 bl 8000514 + 800183e: f000 f8e1 bl 8001a04 /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - 800048e: f000 f927 bl 80006e0 + 8001842: f000 f9e5 bl 8001c10 MX_USART2_UART_Init(); - 8000492: f000 f8fb bl 800068c + 8001846: f000 f9b9 bl 8001bbc MX_RTC_Init(); - 8000496: f000 f8a1 bl 80005dc + 800184a: f000 f95f bl 8001b0c /* USER CODE BEGIN 2 */ - uint8_t hours = 0; - 800049a: 2300 movs r3, #0 - 800049c: 71fb strb r3, [r7, #7] - uint8_t minutes = 0; - 800049e: 2300 movs r3, #0 - 80004a0: 71bb strb r3, [r7, #6] - uint8_t seconds = 0; - 80004a2: 2300 movs r3, #0 - 80004a4: 717b strb r3, [r7, #5] - uint8_t weekDay = 0; - 80004a6: 2300 movs r3, #0 - 80004a8: 713b strb r3, [r7, #4] - uint8_t month = 0; - 80004aa: 2300 movs r3, #0 - 80004ac: 70fb strb r3, [r7, #3] - uint8_t date = 0; - 80004ae: 2300 movs r3, #0 - 80004b0: 70bb strb r3, [r7, #2] - uint8_t year = 0; - 80004b2: 2300 movs r3, #0 - 80004b4: 707b strb r3, [r7, #1] - /* Infinite loop */ + int hours = 0; + 800184e: 2300 movs r3, #0 + 8001850: f8c7 309c str.w r3, [r7, #156] ; 0x9c + int minutes = 0; + 8001854: 2300 movs r3, #0 + 8001856: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + int seconds = 0; + 800185a: 2300 movs r3, #0 + 800185c: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + int weekDay = 0; + 8001860: 2300 movs r3, #0 + 8001862: f8c7 30ac str.w r3, [r7, #172] ; 0xac + int month = 0; + 8001866: 2300 movs r3, #0 + 8001868: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + int date = 0; + 800186c: 2300 movs r3, #0 + 800186e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + int year = 0; + 8001872: 2300 movs r3, #0 + 8001874: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + + int sunrise_h = 0; + 8001878: 2300 movs r3, #0 + 800187a: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + int sunset_h = 0; + 800187e: 2300 movs r3, #0 + 8001880: f8c7 308c str.w r3, [r7, #140] ; 0x8c + int int_sunrise_min = 0; + 8001884: 2300 movs r3, #0 + 8001886: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + int int_sunset_min = 0; + 800188a: 2300 movs r3, #0 + 800188c: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + int sunrise_time[2] = {0}; + 8001890: f107 0378 add.w r3, r7, #120 ; 0x78 + 8001894: 2200 movs r2, #0 + 8001896: 601a str r2, [r3, #0] + 8001898: 605a str r2, [r3, #4] + int sunset_time[2] = {0}; + 800189a: f107 0370 add.w r3, r7, #112 ; 0x70 + 800189e: 2200 movs r2, #0 + 80018a0: 601a str r2, [r3, #0] + 80018a2: 605a str r2, [r3, #4] + int tomorrows_date[4] = {0}; + 80018a4: f107 0360 add.w r3, r7, #96 ; 0x60 + 80018a8: 2200 movs r2, #0 + 80018aa: 601a str r2, [r3, #0] + 80018ac: 605a str r2, [r3, #4] + 80018ae: 609a str r2, [r3, #8] + 80018b0: 60da str r2, [r3, #12] + int DaysInMonth[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + 80018b2: 4b4d ldr r3, [pc, #308] ; (80019e8 ) + 80018b4: f107 0430 add.w r4, r7, #48 ; 0x30 + 80018b8: 461d mov r5, r3 + 80018ba: cd0f ldmia r5!, {r0, r1, r2, r3} + 80018bc: c40f stmia r4!, {r0, r1, r2, r3} + 80018be: cd0f ldmia r5!, {r0, r1, r2, r3} + 80018c0: c40f stmia r4!, {r0, r1, r2, r3} + 80018c2: e895 000f ldmia.w r5, {r0, r1, r2, r3} + 80018c6: e884 000f stmia.w r4, {r0, r1, r2, r3} + int DaysInMonthLeapYear[12] = {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + 80018ca: 4b48 ldr r3, [pc, #288] ; (80019ec ) + 80018cc: 463c mov r4, r7 + 80018ce: 461d mov r5, r3 + 80018d0: cd0f ldmia r5!, {r0, r1, r2, r3} + 80018d2: c40f stmia r4!, {r0, r1, r2, r3} + 80018d4: cd0f ldmia r5!, {r0, r1, r2, r3} + 80018d6: c40f stmia r4!, {r0, r1, r2, r3} + 80018d8: e895 000f ldmia.w r5, {r0, r1, r2, r3} + 80018dc: e884 000f stmia.w r4, {r0, r1, r2, r3} + bool leap_year = false; + 80018e0: 2300 movs r3, #0 + 80018e2: f887 3083 strb.w r3, [r7, #131] ; 0x83 /* USER CODE BEGIN WHILE */ while (1) { - /* USER CODE END WHILE */ - if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK) - 80004b6: 2200 movs r2, #0 - 80004b8: 4913 ldr r1, [pc, #76] ; (8000508 ) - 80004ba: 4814 ldr r0, [pc, #80] ; (800050c ) - 80004bc: f001 fd4f bl 8001f5e - 80004c0: 4603 mov r3, r0 - 80004c2: 2b00 cmp r3, #0 - 80004c4: d108 bne.n 80004d8 - { - hours = sTime.Hours; - 80004c6: 4b10 ldr r3, [pc, #64] ; (8000508 ) - 80004c8: 781b ldrb r3, [r3, #0] - 80004ca: 71fb strb r3, [r7, #7] - minutes = sTime.Minutes; - 80004cc: 4b0e ldr r3, [pc, #56] ; (8000508 ) - 80004ce: 785b ldrb r3, [r3, #1] - 80004d0: 71bb strb r3, [r7, #6] - seconds = sTime.Seconds; - 80004d2: 4b0d ldr r3, [pc, #52] ; (8000508 ) - 80004d4: 789b ldrb r3, [r3, #2] - 80004d6: 717b strb r3, [r7, #5] - } - if (HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK) - 80004d8: 2200 movs r2, #0 - 80004da: 490d ldr r1, [pc, #52] ; (8000510 ) - 80004dc: 480b ldr r0, [pc, #44] ; (800050c ) - 80004de: f001 fe39 bl 8002154 - 80004e2: 4603 mov r3, r0 - 80004e4: 2b00 cmp r3, #0 - 80004e6: d10b bne.n 8000500 - { - weekDay = sDate.WeekDay; - 80004e8: 4b09 ldr r3, [pc, #36] ; (8000510 ) - 80004ea: 781b ldrb r3, [r3, #0] - 80004ec: 713b strb r3, [r7, #4] - month = sDate.Month; - 80004ee: 4b08 ldr r3, [pc, #32] ; (8000510 ) - 80004f0: 785b ldrb r3, [r3, #1] - 80004f2: 70fb strb r3, [r7, #3] - date = sDate.Date; - 80004f4: 4b06 ldr r3, [pc, #24] ; (8000510 ) - 80004f6: 789b ldrb r3, [r3, #2] - 80004f8: 70bb strb r3, [r7, #2] - year = sDate.Year; - 80004fa: 4b05 ldr r3, [pc, #20] ; (8000510 ) - 80004fc: 78db ldrb r3, [r3, #3] - 80004fe: 707b strb r3, [r7, #1] - } - HAL_Delay(200); - 8000500: 20c8 movs r0, #200 ; 0xc8 - 8000502: f000 faaf bl 8000a64 - if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK) - 8000506: e7d6 b.n 80004b6 - 8000508: 20000028 .word 0x20000028 - 800050c: 20000040 .word 0x20000040 - 8000510: 2000003c .word 0x2000003c -08000514 : + //Get Time and Date + if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK) + 80018e6: 2200 movs r2, #0 + 80018e8: 4941 ldr r1, [pc, #260] ; (80019f0 ) + 80018ea: 4842 ldr r0, [pc, #264] ; (80019f4 ) + 80018ec: f001 fd2e bl 800334c + 80018f0: 4603 mov r3, r0 + 80018f2: 2b00 cmp r3, #0 + 80018f4: d10b bne.n 800190e + { + hours = sTime.Hours; + 80018f6: 4b3e ldr r3, [pc, #248] ; (80019f0 ) + 80018f8: 781b ldrb r3, [r3, #0] + 80018fa: f8c7 309c str.w r3, [r7, #156] ; 0x9c + minutes = sTime.Minutes; + 80018fe: 4b3c ldr r3, [pc, #240] ; (80019f0 ) + 8001900: 785b ldrb r3, [r3, #1] + 8001902: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + seconds = sTime.Seconds; + 8001906: 4b3a ldr r3, [pc, #232] ; (80019f0 ) + 8001908: 789b ldrb r3, [r3, #2] + 800190a: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + } + if (HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK) + 800190e: 2200 movs r2, #0 + 8001910: 4939 ldr r1, [pc, #228] ; (80019f8 ) + 8001912: 4838 ldr r0, [pc, #224] ; (80019f4 ) + 8001914: f001 fe1f bl 8003556 + 8001918: 4603 mov r3, r0 + 800191a: 2b00 cmp r3, #0 + 800191c: d111 bne.n 8001942 + { + weekDay = sDate.WeekDay; + 800191e: 4b36 ldr r3, [pc, #216] ; (80019f8 ) + 8001920: 781b ldrb r3, [r3, #0] + 8001922: f8c7 30ac str.w r3, [r7, #172] ; 0xac + month = sDate.Month; + 8001926: 4b34 ldr r3, [pc, #208] ; (80019f8 ) + 8001928: 785b ldrb r3, [r3, #1] + 800192a: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + date = sDate.Date; + 800192e: 4b32 ldr r3, [pc, #200] ; (80019f8 ) + 8001930: 789b ldrb r3, [r3, #2] + 8001932: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + year = 2000 + sDate.Year; + 8001936: 4b30 ldr r3, [pc, #192] ; (80019f8 ) + 8001938: 78db ldrb r3, [r3, #3] + 800193a: f503 63fa add.w r3, r3, #2000 ; 0x7d0 + 800193e: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + } + + // check for leap year + leap_year = leap_year_check(year); + 8001942: f8d7 00a0 ldr.w r0, [r7, #160] ; 0xa0 + 8001946: f7ff faa3 bl 8000e90 + 800194a: 4603 mov r3, r0 + 800194c: 2b00 cmp r3, #0 + 800194e: bf14 ite ne + 8001950: 2301 movne r3, #1 + 8001952: 2300 moveq r3, #0 + 8001954: f887 3083 strb.w r3, [r7, #131] ; 0x83 + if (leap_year) + 8001958: f897 3083 ldrb.w r3, [r7, #131] ; 0x83 + 800195c: 2b00 cmp r3, #0 + 800195e: d00f beq.n 8001980 + { + //Calculate tomorrow's date + calc_tomorrows_date(date, weekDay, month, year, DaysInMonthLeapYear, tomorrows_date); + 8001960: f107 0360 add.w r3, r7, #96 ; 0x60 + 8001964: 9301 str r3, [sp, #4] + 8001966: 463b mov r3, r7 + 8001968: 9300 str r3, [sp, #0] + 800196a: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 800196e: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8 + 8001972: f8d7 10ac ldr.w r1, [r7, #172] ; 0xac + 8001976: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 + 800197a: f7ff fec1 bl 8001700 + 800197e: e00f b.n 80019a0 + } else { + //Calculate tomorrow's date + calc_tomorrows_date(date, weekDay, month, year, DaysInMonth, tomorrows_date); + 8001980: f107 0360 add.w r3, r7, #96 ; 0x60 + 8001984: 9301 str r3, [sp, #4] + 8001986: f107 0330 add.w r3, r7, #48 ; 0x30 + 800198a: 9300 str r3, [sp, #0] + 800198c: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 8001990: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8 + 8001994: f8d7 10ac ldr.w r1, [r7, #172] ; 0xac + 8001998: f8d7 00a4 ldr.w r0, [r7, #164] ; 0xa4 + 800199c: f7ff feb0 bl 8001700 + } + + //Calculate sunrise and sunset time for tomorrow + calc_sunrise_sunset(tomorrows_date[0], tomorrows_date[2], tomorrows_date[3], sunrise_time, sunset_time); + 80019a0: 6e38 ldr r0, [r7, #96] ; 0x60 + 80019a2: 6eb9 ldr r1, [r7, #104] ; 0x68 + 80019a4: 6efa ldr r2, [r7, #108] ; 0x6c + 80019a6: f107 0478 add.w r4, r7, #120 ; 0x78 + 80019aa: f107 0370 add.w r3, r7, #112 ; 0x70 + 80019ae: 9300 str r3, [sp, #0] + 80019b0: 4623 mov r3, r4 + 80019b2: f7ff fb1d bl 8000ff0 + + set_Alarm(16, 22, 1); + 80019b6: 2201 movs r2, #1 + 80019b8: 2116 movs r1, #22 + 80019ba: 2010 movs r0, #16 + 80019bc: f7ff fee4 bl 8001788 + + HAL_Delay(5000); + 80019c0: f241 3088 movw r0, #5000 ; 0x1388 + 80019c4: f000 fb18 bl 8001ff8 + + transmit_uart("Ich gehe schlafen!\r\n"); + 80019c8: 480c ldr r0, [pc, #48] ; (80019fc ) + 80019ca: f7ff ff1d bl 8001808 + + // Suspend Tick increment to prevent wake up by Systick interrupt + HAL_SuspendTick(); + 80019ce: f000 fb35 bl 800203c + + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); //Interrupt for wake up + 80019d2: 2101 movs r1, #1 + 80019d4: 2000 movs r0, #0 + 80019d6: f000 fdff bl 80025d8 + + HAL_ResumeTick(); + 80019da: f000 fb3f bl 800205c + + transmit_uart("Bin wieder wach!\r\n"); + 80019de: 4808 ldr r0, [pc, #32] ; (8001a00 ) + 80019e0: f7ff ff12 bl 8001808 + if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK) + 80019e4: e77f b.n 80018e6 + 80019e6: bf00 nop + 80019e8: 08005fac .word 0x08005fac + 80019ec: 08005fdc .word 0x08005fdc + 80019f0: 200000a4 .word 0x200000a4 + 80019f4: 200000e4 .word 0x200000e4 + 80019f8: 200000e0 .word 0x200000e0 + 80019fc: 08005f80 .word 0x08005f80 + 8001a00: 08005f98 .word 0x08005f98 + +08001a04 : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { - 8000514: b580 push {r7, lr} - 8000516: b096 sub sp, #88 ; 0x58 - 8000518: af00 add r7, sp, #0 + 8001a04: b580 push {r7, lr} + 8001a06: b098 sub sp, #96 ; 0x60 + 8001a08: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - 800051a: f107 0324 add.w r3, r7, #36 ; 0x24 - 800051e: 2234 movs r2, #52 ; 0x34 - 8000520: 2100 movs r1, #0 - 8000522: 4618 mov r0, r3 - 8000524: f002 f84a bl 80025bc + 8001a0a: f107 0330 add.w r3, r7, #48 ; 0x30 + 8001a0e: 2230 movs r2, #48 ; 0x30 + 8001a10: 2100 movs r1, #0 + 8001a12: 4618 mov r0, r3 + 8001a14: f002 fcdc bl 80043d0 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - 8000528: f107 0310 add.w r3, r7, #16 - 800052c: 2200 movs r2, #0 - 800052e: 601a str r2, [r3, #0] - 8000530: 605a str r2, [r3, #4] - 8000532: 609a str r2, [r3, #8] - 8000534: 60da str r2, [r3, #12] - 8000536: 611a str r2, [r3, #16] - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - 8000538: 1d3b adds r3, r7, #4 - 800053a: 2200 movs r2, #0 - 800053c: 601a str r2, [r3, #0] - 800053e: 605a str r2, [r3, #4] - 8000540: 609a str r2, [r3, #8] + 8001a18: f107 031c add.w r3, r7, #28 + 8001a1c: 2200 movs r2, #0 + 8001a1e: 601a str r2, [r3, #0] + 8001a20: 605a str r2, [r3, #4] + 8001a22: 609a str r2, [r3, #8] + 8001a24: 60da str r2, [r3, #12] + 8001a26: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 8001a28: f107 0308 add.w r3, r7, #8 + 8001a2c: 2200 movs r2, #0 + 8001a2e: 601a str r2, [r3, #0] + 8001a30: 605a str r2, [r3, #4] + 8001a32: 609a str r2, [r3, #8] + 8001a34: 60da str r2, [r3, #12] + 8001a36: 611a str r2, [r3, #16] /** Configure the main internal regulator output voltage */ - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 8000542: 4b25 ldr r3, [pc, #148] ; (80005d8 ) - 8000544: 681b ldr r3, [r3, #0] - 8000546: f423 53c0 bic.w r3, r3, #6144 ; 0x1800 - 800054a: 4a23 ldr r2, [pc, #140] ; (80005d8 ) - 800054c: f443 6300 orr.w r3, r3, #2048 ; 0x800 - 8000550: 6013 str r3, [r2, #0] + __HAL_RCC_PWR_CLK_ENABLE(); + 8001a38: 2300 movs r3, #0 + 8001a3a: 607b str r3, [r7, #4] + 8001a3c: 4b31 ldr r3, [pc, #196] ; (8001b04 ) + 8001a3e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a40: 4a30 ldr r2, [pc, #192] ; (8001b04 ) + 8001a42: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8001a46: 6413 str r3, [r2, #64] ; 0x40 + 8001a48: 4b2e ldr r3, [pc, #184] ; (8001b04 ) + 8001a4a: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001a4c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001a50: 607b str r3, [r7, #4] + 8001a52: 687b ldr r3, [r7, #4] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + 8001a54: 2300 movs r3, #0 + 8001a56: 603b str r3, [r7, #0] + 8001a58: 4b2b ldr r3, [pc, #172] ; (8001b08 ) + 8001a5a: 681b ldr r3, [r3, #0] + 8001a5c: f423 4340 bic.w r3, r3, #49152 ; 0xc000 + 8001a60: 4a29 ldr r2, [pc, #164] ; (8001b08 ) + 8001a62: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8001a66: 6013 str r3, [r2, #0] + 8001a68: 4b27 ldr r3, [pc, #156] ; (8001b08 ) + 8001a6a: 681b ldr r3, [r3, #0] + 8001a6c: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8001a70: 603b str r3, [r7, #0] + 8001a72: 683b ldr r3, [r7, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE; - 8000552: 2306 movs r3, #6 - 8000554: 627b str r3, [r7, #36] ; 0x24 - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - 8000556: 2301 movs r3, #1 - 8000558: 62fb str r3, [r7, #44] ; 0x2c + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI; + 8001a74: 230a movs r3, #10 + 8001a76: 633b str r3, [r7, #48] ; 0x30 RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 800055a: 2301 movs r3, #1 - 800055c: 633b str r3, [r7, #48] ; 0x30 + 8001a78: 2301 movs r3, #1 + 8001a7a: 63fb str r3, [r7, #60] ; 0x3c RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 800055e: 2310 movs r3, #16 - 8000560: 637b str r3, [r7, #52] ; 0x34 + 8001a7c: 2310 movs r3, #16 + 8001a7e: 643b str r3, [r7, #64] ; 0x40 + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + 8001a80: 2301 movs r3, #1 + 8001a82: 647b str r3, [r7, #68] ; 0x44 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 8000562: 2302 movs r3, #2 - 8000564: 64bb str r3, [r7, #72] ; 0x48 + 8001a84: 2302 movs r3, #2 + 8001a86: 64bb str r3, [r7, #72] ; 0x48 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - 8000566: 2300 movs r3, #0 - 8000568: 64fb str r3, [r7, #76] ; 0x4c - RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; - 800056a: f44f 2300 mov.w r3, #524288 ; 0x80000 - 800056e: 653b str r3, [r7, #80] ; 0x50 - RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3; - 8000570: f44f 0300 mov.w r3, #8388608 ; 0x800000 - 8000574: 657b str r3, [r7, #84] ; 0x54 + 8001a88: 2300 movs r3, #0 + 8001a8a: 64fb str r3, [r7, #76] ; 0x4c + RCC_OscInitStruct.PLL.PLLM = 16; + 8001a8c: 2310 movs r3, #16 + 8001a8e: 653b str r3, [r7, #80] ; 0x50 + RCC_OscInitStruct.PLL.PLLN = 336; + 8001a90: f44f 73a8 mov.w r3, #336 ; 0x150 + 8001a94: 657b str r3, [r7, #84] ; 0x54 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + 8001a96: 2304 movs r3, #4 + 8001a98: 65bb str r3, [r7, #88] ; 0x58 + RCC_OscInitStruct.PLL.PLLQ = 7; + 8001a9a: 2307 movs r3, #7 + 8001a9c: 65fb str r3, [r7, #92] ; 0x5c if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - 8000576: f107 0324 add.w r3, r7, #36 ; 0x24 - 800057a: 4618 mov r0, r3 - 800057c: f000 fd1e bl 8000fbc - 8000580: 4603 mov r3, r0 - 8000582: 2b00 cmp r3, #0 - 8000584: d001 beq.n 800058a + 8001a9e: f107 0330 add.w r3, r7, #48 ; 0x30 + 8001aa2: 4618 mov r0, r3 + 8001aa4: f000 fdb4 bl 8002610 + 8001aa8: 4603 mov r3, r0 + 8001aaa: 2b00 cmp r3, #0 + 8001aac: d001 beq.n 8001ab2 { Error_Handler(); - 8000586: f000 f913 bl 80007b0 + 8001aae: f000 f91f bl 8001cf0 } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - 800058a: 230f movs r3, #15 - 800058c: 613b str r3, [r7, #16] + 8001ab2: 230f movs r3, #15 + 8001ab4: 61fb str r3, [r7, #28] |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - 800058e: 2303 movs r3, #3 - 8000590: 617b str r3, [r7, #20] + 8001ab6: 2302 movs r3, #2 + 8001ab8: 623b str r3, [r7, #32] RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 8000592: 2300 movs r3, #0 - 8000594: 61bb str r3, [r7, #24] - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - 8000596: 2300 movs r3, #0 - 8000598: 61fb str r3, [r7, #28] + 8001aba: 2300 movs r3, #0 + 8001abc: 627b str r3, [r7, #36] ; 0x24 + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 8001abe: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8001ac2: 62bb str r3, [r7, #40] ; 0x28 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 800059a: 2300 movs r3, #0 - 800059c: 623b str r3, [r7, #32] + 8001ac4: 2300 movs r3, #0 + 8001ac6: 62fb str r3, [r7, #44] ; 0x2c - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) - 800059e: f107 0310 add.w r3, r7, #16 - 80005a2: 2101 movs r1, #1 - 80005a4: 4618 mov r0, r3 - 80005a6: f001 f839 bl 800161c - 80005aa: 4603 mov r3, r0 - 80005ac: 2b00 cmp r3, #0 - 80005ae: d001 beq.n 80005b4 + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 8001ac8: f107 031c add.w r3, r7, #28 + 8001acc: 2102 movs r1, #2 + 8001ace: 4618 mov r0, r3 + 8001ad0: f001 f80e bl 8002af0 + 8001ad4: 4603 mov r3, r0 + 8001ad6: 2b00 cmp r3, #0 + 8001ad8: d001 beq.n 8001ade { Error_Handler(); - 80005b0: f000 f8fe bl 80007b0 + 8001ada: f000 f909 bl 8001cf0 } - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC; - 80005b4: 2301 movs r3, #1 - 80005b6: 607b str r3, [r7, #4] - PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; - 80005b8: f44f 3380 mov.w r3, #65536 ; 0x10000 - 80005bc: 60bb str r3, [r7, #8] - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - 80005be: 1d3b adds r3, r7, #4 - 80005c0: 4618 mov r0, r3 - 80005c2: f001 fabb bl 8001b3c - 80005c6: 4603 mov r3, r0 - 80005c8: 2b00 cmp r3, #0 - 80005ca: d001 beq.n 80005d0 + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 8001ade: 2302 movs r3, #2 + 8001ae0: 60bb str r3, [r7, #8] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + 8001ae2: f44f 7300 mov.w r3, #512 ; 0x200 + 8001ae6: 617b str r3, [r7, #20] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8001ae8: f107 0308 add.w r3, r7, #8 + 8001aec: 4618 mov r0, r3 + 8001aee: f001 f9f1 bl 8002ed4 + 8001af2: 4603 mov r3, r0 + 8001af4: 2b00 cmp r3, #0 + 8001af6: d001 beq.n 8001afc { Error_Handler(); - 80005cc: f000 f8f0 bl 80007b0 + 8001af8: f000 f8fa bl 8001cf0 } } - 80005d0: bf00 nop - 80005d2: 3758 adds r7, #88 ; 0x58 - 80005d4: 46bd mov sp, r7 - 80005d6: bd80 pop {r7, pc} - 80005d8: 40007000 .word 0x40007000 + 8001afc: bf00 nop + 8001afe: 3760 adds r7, #96 ; 0x60 + 8001b00: 46bd mov sp, r7 + 8001b02: bd80 pop {r7, pc} + 8001b04: 40023800 .word 0x40023800 + 8001b08: 40007000 .word 0x40007000 -080005dc : +08001b0c : * @brief RTC Initialization Function * @param None * @retval None */ static void MX_RTC_Init(void) { - 80005dc: b580 push {r7, lr} - 80005de: af00 add r7, sp, #0 + 8001b0c: b580 push {r7, lr} + 8001b0e: af00 add r7, sp, #0 /* USER CODE BEGIN RTC_Init 1 */ /* USER CODE END RTC_Init 1 */ /** Initialize RTC Only */ hrtc.Instance = RTC; - 80005e0: 4b26 ldr r3, [pc, #152] ; (800067c ) - 80005e2: 4a27 ldr r2, [pc, #156] ; (8000680 ) - 80005e4: 601a str r2, [r3, #0] + 8001b10: 4b26 ldr r3, [pc, #152] ; (8001bac ) + 8001b12: 4a27 ldr r2, [pc, #156] ; (8001bb0 ) + 8001b14: 601a str r2, [r3, #0] hrtc.Init.HourFormat = RTC_HOURFORMAT_24; - 80005e6: 4b25 ldr r3, [pc, #148] ; (800067c ) - 80005e8: 2200 movs r2, #0 - 80005ea: 605a str r2, [r3, #4] + 8001b16: 4b25 ldr r3, [pc, #148] ; (8001bac ) + 8001b18: 2200 movs r2, #0 + 8001b1a: 605a str r2, [r3, #4] hrtc.Init.AsynchPrediv = 127; - 80005ec: 4b23 ldr r3, [pc, #140] ; (800067c ) - 80005ee: 227f movs r2, #127 ; 0x7f - 80005f0: 609a str r2, [r3, #8] + 8001b1c: 4b23 ldr r3, [pc, #140] ; (8001bac ) + 8001b1e: 227f movs r2, #127 ; 0x7f + 8001b20: 609a str r2, [r3, #8] hrtc.Init.SynchPrediv = 255; - 80005f2: 4b22 ldr r3, [pc, #136] ; (800067c ) - 80005f4: 22ff movs r2, #255 ; 0xff - 80005f6: 60da str r2, [r3, #12] + 8001b22: 4b22 ldr r3, [pc, #136] ; (8001bac ) + 8001b24: 22ff movs r2, #255 ; 0xff + 8001b26: 60da str r2, [r3, #12] hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; - 80005f8: 4b20 ldr r3, [pc, #128] ; (800067c ) - 80005fa: 2200 movs r2, #0 - 80005fc: 611a str r2, [r3, #16] + 8001b28: 4b20 ldr r3, [pc, #128] ; (8001bac ) + 8001b2a: 2200 movs r2, #0 + 8001b2c: 611a str r2, [r3, #16] hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - 80005fe: 4b1f ldr r3, [pc, #124] ; (800067c ) - 8000600: 2200 movs r2, #0 - 8000602: 615a str r2, [r3, #20] + 8001b2e: 4b1f ldr r3, [pc, #124] ; (8001bac ) + 8001b30: 2200 movs r2, #0 + 8001b32: 615a str r2, [r3, #20] hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - 8000604: 4b1d ldr r3, [pc, #116] ; (800067c ) - 8000606: 2200 movs r2, #0 - 8000608: 619a str r2, [r3, #24] + 8001b34: 4b1d ldr r3, [pc, #116] ; (8001bac ) + 8001b36: 2200 movs r2, #0 + 8001b38: 619a str r2, [r3, #24] if (HAL_RTC_Init(&hrtc) != HAL_OK) - 800060a: 481c ldr r0, [pc, #112] ; (800067c ) - 800060c: f001 fb78 bl 8001d00 - 8000610: 4603 mov r3, r0 - 8000612: 2b00 cmp r3, #0 - 8000614: d001 beq.n 800061a + 8001b3a: 481c ldr r0, [pc, #112] ; (8001bac ) + 8001b3c: f001 fab8 bl 80030b0 + 8001b40: 4603 mov r3, r0 + 8001b42: 2b00 cmp r3, #0 + 8001b44: d001 beq.n 8001b4a { Error_Handler(); - 8000616: f000 f8cb bl 80007b0 + 8001b46: f000 f8d3 bl 8001cf0 /* USER CODE END Check_RTC_BKUP */ /** Initialize RTC and set the Time and Date */ - sTime.Hours = 23; - 800061a: 4b1a ldr r3, [pc, #104] ; (8000684 ) - 800061c: 2217 movs r2, #23 - 800061e: 701a strb r2, [r3, #0] - sTime.Minutes = 59; - 8000620: 4b18 ldr r3, [pc, #96] ; (8000684 ) - 8000622: 223b movs r2, #59 ; 0x3b - 8000624: 705a strb r2, [r3, #1] - sTime.Seconds = 45; - 8000626: 4b17 ldr r3, [pc, #92] ; (8000684 ) - 8000628: 222d movs r2, #45 ; 0x2d - 800062a: 709a strb r2, [r3, #2] + sTime.Hours = 16; + 8001b4a: 4b1a ldr r3, [pc, #104] ; (8001bb4 ) + 8001b4c: 2210 movs r2, #16 + 8001b4e: 701a strb r2, [r3, #0] + sTime.Minutes = 20; + 8001b50: 4b18 ldr r3, [pc, #96] ; (8001bb4 ) + 8001b52: 2214 movs r2, #20 + 8001b54: 705a strb r2, [r3, #1] + sTime.Seconds = 30; + 8001b56: 4b17 ldr r3, [pc, #92] ; (8001bb4 ) + 8001b58: 221e movs r2, #30 + 8001b5a: 709a strb r2, [r3, #2] sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE; - 800062c: 4b15 ldr r3, [pc, #84] ; (8000684 ) - 800062e: 2200 movs r2, #0 - 8000630: 60da str r2, [r3, #12] + 8001b5c: 4b15 ldr r3, [pc, #84] ; (8001bb4 ) + 8001b5e: 2200 movs r2, #0 + 8001b60: 60da str r2, [r3, #12] sTime.StoreOperation = RTC_STOREOPERATION_RESET; - 8000632: 4b14 ldr r3, [pc, #80] ; (8000684 ) - 8000634: 2200 movs r2, #0 - 8000636: 611a str r2, [r3, #16] + 8001b62: 4b14 ldr r3, [pc, #80] ; (8001bb4 ) + 8001b64: 2200 movs r2, #0 + 8001b66: 611a str r2, [r3, #16] if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK) - 8000638: 2200 movs r2, #0 - 800063a: 4912 ldr r1, [pc, #72] ; (8000684 ) - 800063c: 480f ldr r0, [pc, #60] ; (800067c ) - 800063e: f001 fbda bl 8001df6 - 8000642: 4603 mov r3, r0 - 8000644: 2b00 cmp r3, #0 - 8000646: d001 beq.n 800064c + 8001b68: 2200 movs r2, #0 + 8001b6a: 4912 ldr r1, [pc, #72] ; (8001bb4 ) + 8001b6c: 480f ldr r0, [pc, #60] ; (8001bac ) + 8001b6e: f001 fb30 bl 80031d2 + 8001b72: 4603 mov r3, r0 + 8001b74: 2b00 cmp r3, #0 + 8001b76: d001 beq.n 8001b7c { Error_Handler(); - 8000648: f000 f8b2 bl 80007b0 + 8001b78: f000 f8ba bl 8001cf0 } - sDate.WeekDay = RTC_WEEKDAY_SUNDAY; - 800064c: 4b0e ldr r3, [pc, #56] ; (8000688 ) - 800064e: 2207 movs r2, #7 - 8000650: 701a strb r2, [r3, #0] - sDate.Month = RTC_MONTH_DECEMBER; - 8000652: 4b0d ldr r3, [pc, #52] ; (8000688 ) - 8000654: 2212 movs r2, #18 - 8000656: 705a strb r2, [r3, #1] - sDate.Date = 31; - 8000658: 4b0b ldr r3, [pc, #44] ; (8000688 ) - 800065a: 221f movs r2, #31 - 800065c: 709a strb r2, [r3, #2] - sDate.Year = 17; - 800065e: 4b0a ldr r3, [pc, #40] ; (8000688 ) - 8000660: 2211 movs r2, #17 - 8000662: 70da strb r2, [r3, #3] + sDate.WeekDay = RTC_WEEKDAY_MONDAY; + 8001b7c: 4b0e ldr r3, [pc, #56] ; (8001bb8 ) + 8001b7e: 2201 movs r2, #1 + 8001b80: 701a strb r2, [r3, #0] + sDate.Month = RTC_MONTH_JANUARY; + 8001b82: 4b0d ldr r3, [pc, #52] ; (8001bb8 ) + 8001b84: 2201 movs r2, #1 + 8001b86: 705a strb r2, [r3, #1] + sDate.Date = 11; + 8001b88: 4b0b ldr r3, [pc, #44] ; (8001bb8 ) + 8001b8a: 220b movs r2, #11 + 8001b8c: 709a strb r2, [r3, #2] + sDate.Year = 21; + 8001b8e: 4b0a ldr r3, [pc, #40] ; (8001bb8 ) + 8001b90: 2215 movs r2, #21 + 8001b92: 70da strb r2, [r3, #3] if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK) - 8000664: 2200 movs r2, #0 - 8000666: 4908 ldr r1, [pc, #32] ; (8000688 ) - 8000668: 4804 ldr r0, [pc, #16] ; (800067c ) - 800066a: f001 fcd5 bl 8002018 - 800066e: 4603 mov r3, r0 - 8000670: 2b00 cmp r3, #0 - 8000672: d001 beq.n 8000678 + 8001b94: 2200 movs r2, #0 + 8001b96: 4908 ldr r1, [pc, #32] ; (8001bb8 ) + 8001b98: 4804 ldr r0, [pc, #16] ; (8001bac ) + 8001b9a: f001 fc35 bl 8003408 + 8001b9e: 4603 mov r3, r0 + 8001ba0: 2b00 cmp r3, #0 + 8001ba2: d001 beq.n 8001ba8 { Error_Handler(); - 8000674: f000 f89c bl 80007b0 - } + 8001ba4: f000 f8a4 bl 8001cf0 + /* USER CODE BEGIN RTC_Init 2 */ /* USER CODE END RTC_Init 2 */ } - 8000678: bf00 nop - 800067a: bd80 pop {r7, pc} - 800067c: 20000040 .word 0x20000040 - 8000680: 40002800 .word 0x40002800 - 8000684: 20000028 .word 0x20000028 - 8000688: 2000003c .word 0x2000003c + 8001ba8: bf00 nop + 8001baa: bd80 pop {r7, pc} + 8001bac: 200000e4 .word 0x200000e4 + 8001bb0: 40002800 .word 0x40002800 + 8001bb4: 200000a4 .word 0x200000a4 + 8001bb8: 200000e0 .word 0x200000e0 -0800068c : +08001bbc : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { - 800068c: b580 push {r7, lr} - 800068e: af00 add r7, sp, #0 + 8001bbc: b580 push {r7, lr} + 8001bbe: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; - 8000690: 4b11 ldr r3, [pc, #68] ; (80006d8 ) - 8000692: 4a12 ldr r2, [pc, #72] ; (80006dc ) - 8000694: 601a str r2, [r3, #0] + 8001bc0: 4b11 ldr r3, [pc, #68] ; (8001c08 ) + 8001bc2: 4a12 ldr r2, [pc, #72] ; (8001c0c ) + 8001bc4: 601a str r2, [r3, #0] huart2.Init.BaudRate = 115200; - 8000696: 4b10 ldr r3, [pc, #64] ; (80006d8 ) - 8000698: f44f 32e1 mov.w r2, #115200 ; 0x1c200 - 800069c: 605a str r2, [r3, #4] + 8001bc6: 4b10 ldr r3, [pc, #64] ; (8001c08 ) + 8001bc8: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001bcc: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; - 800069e: 4b0e ldr r3, [pc, #56] ; (80006d8 ) - 80006a0: 2200 movs r2, #0 - 80006a2: 609a str r2, [r3, #8] + 8001bce: 4b0e ldr r3, [pc, #56] ; (8001c08 ) + 8001bd0: 2200 movs r2, #0 + 8001bd2: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; - 80006a4: 4b0c ldr r3, [pc, #48] ; (80006d8 ) - 80006a6: 2200 movs r2, #0 - 80006a8: 60da str r2, [r3, #12] + 8001bd4: 4b0c ldr r3, [pc, #48] ; (8001c08 ) + 8001bd6: 2200 movs r2, #0 + 8001bd8: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; - 80006aa: 4b0b ldr r3, [pc, #44] ; (80006d8 ) - 80006ac: 2200 movs r2, #0 - 80006ae: 611a str r2, [r3, #16] + 8001bda: 4b0b ldr r3, [pc, #44] ; (8001c08 ) + 8001bdc: 2200 movs r2, #0 + 8001bde: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; - 80006b0: 4b09 ldr r3, [pc, #36] ; (80006d8 ) - 80006b2: 220c movs r2, #12 - 80006b4: 615a str r2, [r3, #20] + 8001be0: 4b09 ldr r3, [pc, #36] ; (8001c08 ) + 8001be2: 220c movs r2, #12 + 8001be4: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 80006b6: 4b08 ldr r3, [pc, #32] ; (80006d8 ) - 80006b8: 2200 movs r2, #0 - 80006ba: 619a str r2, [r3, #24] + 8001be6: 4b08 ldr r3, [pc, #32] ; (8001c08 ) + 8001be8: 2200 movs r2, #0 + 8001bea: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; - 80006bc: 4b06 ldr r3, [pc, #24] ; (80006d8 ) - 80006be: 2200 movs r2, #0 - 80006c0: 61da str r2, [r3, #28] + 8001bec: 4b06 ldr r3, [pc, #24] ; (8001c08 ) + 8001bee: 2200 movs r2, #0 + 8001bf0: 61da str r2, [r3, #28] if (HAL_UART_Init(&huart2) != HAL_OK) - 80006c2: 4805 ldr r0, [pc, #20] ; (80006d8 ) - 80006c4: f001 fe24 bl 8002310 - 80006c8: 4603 mov r3, r0 - 80006ca: 2b00 cmp r3, #0 - 80006cc: d001 beq.n 80006d2 + 8001bf2: 4805 ldr r0, [pc, #20] ; (8001c08 ) + 8001bf4: f001 ff16 bl 8003a24 + 8001bf8: 4603 mov r3, r0 + 8001bfa: 2b00 cmp r3, #0 + 8001bfc: d001 beq.n 8001c02 { Error_Handler(); - 80006ce: f000 f86f bl 80007b0 + 8001bfe: f000 f877 bl 8001cf0 } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } - 80006d2: bf00 nop - 80006d4: bd80 pop {r7, pc} - 80006d6: bf00 nop - 80006d8: 20000060 .word 0x20000060 - 80006dc: 40004400 .word 0x40004400 + 8001c02: bf00 nop + 8001c04: bd80 pop {r7, pc} + 8001c06: bf00 nop + 8001c08: 20000104 .word 0x20000104 + 8001c0c: 40004400 .word 0x40004400 -080006e0 : +08001c10 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { - 80006e0: b580 push {r7, lr} - 80006e2: b08a sub sp, #40 ; 0x28 - 80006e4: af00 add r7, sp, #0 + 8001c10: b580 push {r7, lr} + 8001c12: b08a sub sp, #40 ; 0x28 + 8001c14: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; - 80006e6: f107 0314 add.w r3, r7, #20 - 80006ea: 2200 movs r2, #0 - 80006ec: 601a str r2, [r3, #0] - 80006ee: 605a str r2, [r3, #4] - 80006f0: 609a str r2, [r3, #8] - 80006f2: 60da str r2, [r3, #12] - 80006f4: 611a str r2, [r3, #16] + 8001c16: f107 0314 add.w r3, r7, #20 + 8001c1a: 2200 movs r2, #0 + 8001c1c: 601a str r2, [r3, #0] + 8001c1e: 605a str r2, [r3, #4] + 8001c20: 609a str r2, [r3, #8] + 8001c22: 60da str r2, [r3, #12] + 8001c24: 611a str r2, [r3, #16] /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOC_CLK_ENABLE(); - 80006f6: 4b2a ldr r3, [pc, #168] ; (80007a0 ) - 80006f8: 69db ldr r3, [r3, #28] - 80006fa: 4a29 ldr r2, [pc, #164] ; (80007a0 ) - 80006fc: f043 0304 orr.w r3, r3, #4 - 8000700: 61d3 str r3, [r2, #28] - 8000702: 4b27 ldr r3, [pc, #156] ; (80007a0 ) - 8000704: 69db ldr r3, [r3, #28] - 8000706: f003 0304 and.w r3, r3, #4 - 800070a: 613b str r3, [r7, #16] - 800070c: 693b ldr r3, [r7, #16] + 8001c26: 2300 movs r3, #0 + 8001c28: 613b str r3, [r7, #16] + 8001c2a: 4b2d ldr r3, [pc, #180] ; (8001ce0 ) + 8001c2c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c2e: 4a2c ldr r2, [pc, #176] ; (8001ce0 ) + 8001c30: f043 0304 orr.w r3, r3, #4 + 8001c34: 6313 str r3, [r2, #48] ; 0x30 + 8001c36: 4b2a ldr r3, [pc, #168] ; (8001ce0 ) + 8001c38: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c3a: f003 0304 and.w r3, r3, #4 + 8001c3e: 613b str r3, [r7, #16] + 8001c40: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOH_CLK_ENABLE(); - 800070e: 4b24 ldr r3, [pc, #144] ; (80007a0 ) - 8000710: 69db ldr r3, [r3, #28] - 8000712: 4a23 ldr r2, [pc, #140] ; (80007a0 ) - 8000714: f043 0320 orr.w r3, r3, #32 - 8000718: 61d3 str r3, [r2, #28] - 800071a: 4b21 ldr r3, [pc, #132] ; (80007a0 ) - 800071c: 69db ldr r3, [r3, #28] - 800071e: f003 0320 and.w r3, r3, #32 - 8000722: 60fb str r3, [r7, #12] - 8000724: 68fb ldr r3, [r7, #12] + 8001c42: 2300 movs r3, #0 + 8001c44: 60fb str r3, [r7, #12] + 8001c46: 4b26 ldr r3, [pc, #152] ; (8001ce0 ) + 8001c48: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c4a: 4a25 ldr r2, [pc, #148] ; (8001ce0 ) + 8001c4c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8001c50: 6313 str r3, [r2, #48] ; 0x30 + 8001c52: 4b23 ldr r3, [pc, #140] ; (8001ce0 ) + 8001c54: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c56: f003 0380 and.w r3, r3, #128 ; 0x80 + 8001c5a: 60fb str r3, [r7, #12] + 8001c5c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000726: 4b1e ldr r3, [pc, #120] ; (80007a0 ) - 8000728: 69db ldr r3, [r3, #28] - 800072a: 4a1d ldr r2, [pc, #116] ; (80007a0 ) - 800072c: f043 0301 orr.w r3, r3, #1 - 8000730: 61d3 str r3, [r2, #28] - 8000732: 4b1b ldr r3, [pc, #108] ; (80007a0 ) - 8000734: 69db ldr r3, [r3, #28] - 8000736: f003 0301 and.w r3, r3, #1 - 800073a: 60bb str r3, [r7, #8] - 800073c: 68bb ldr r3, [r7, #8] + 8001c5e: 2300 movs r3, #0 + 8001c60: 60bb str r3, [r7, #8] + 8001c62: 4b1f ldr r3, [pc, #124] ; (8001ce0 ) + 8001c64: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c66: 4a1e ldr r2, [pc, #120] ; (8001ce0 ) + 8001c68: f043 0301 orr.w r3, r3, #1 + 8001c6c: 6313 str r3, [r2, #48] ; 0x30 + 8001c6e: 4b1c ldr r3, [pc, #112] ; (8001ce0 ) + 8001c70: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c72: f003 0301 and.w r3, r3, #1 + 8001c76: 60bb str r3, [r7, #8] + 8001c78: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); - 800073e: 4b18 ldr r3, [pc, #96] ; (80007a0 ) - 8000740: 69db ldr r3, [r3, #28] - 8000742: 4a17 ldr r2, [pc, #92] ; (80007a0 ) - 8000744: f043 0302 orr.w r3, r3, #2 - 8000748: 61d3 str r3, [r2, #28] - 800074a: 4b15 ldr r3, [pc, #84] ; (80007a0 ) - 800074c: 69db ldr r3, [r3, #28] - 800074e: f003 0302 and.w r3, r3, #2 - 8000752: 607b str r3, [r7, #4] - 8000754: 687b ldr r3, [r7, #4] + 8001c7a: 2300 movs r3, #0 + 8001c7c: 607b str r3, [r7, #4] + 8001c7e: 4b18 ldr r3, [pc, #96] ; (8001ce0 ) + 8001c80: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c82: 4a17 ldr r2, [pc, #92] ; (8001ce0 ) + 8001c84: f043 0302 orr.w r3, r3, #2 + 8001c88: 6313 str r3, [r2, #48] ; 0x30 + 8001c8a: 4b15 ldr r3, [pc, #84] ; (8001ce0 ) + 8001c8c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001c8e: f003 0302 and.w r3, r3, #2 + 8001c92: 607b str r3, [r7, #4] + 8001c94: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); - 8000756: 2200 movs r2, #0 - 8000758: 2120 movs r1, #32 - 800075a: 4812 ldr r0, [pc, #72] ; (80007a4 ) - 800075c: f000 fc16 bl 8000f8c + 8001c96: 2200 movs r2, #0 + 8001c98: 2120 movs r1, #32 + 8001c9a: 4812 ldr r0, [pc, #72] ; (8001ce4 ) + 8001c9c: f000 fc82 bl 80025a4 /*Configure GPIO pin : B1_Pin */ GPIO_InitStruct.Pin = B1_Pin; - 8000760: f44f 5300 mov.w r3, #8192 ; 0x2000 - 8000764: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - 8000766: 4b10 ldr r3, [pc, #64] ; (80007a8 ) - 8000768: 61bb str r3, [r7, #24] + 8001ca0: f44f 5300 mov.w r3, #8192 ; 0x2000 + 8001ca4: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 8001ca6: 4b10 ldr r3, [pc, #64] ; (8001ce8 ) + 8001ca8: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 800076a: 2300 movs r3, #0 - 800076c: 61fb str r3, [r7, #28] + 8001caa: 2300 movs r3, #0 + 8001cac: 61fb str r3, [r7, #28] HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); - 800076e: f107 0314 add.w r3, r7, #20 - 8000772: 4619 mov r1, r3 - 8000774: 480d ldr r0, [pc, #52] ; (80007ac ) - 8000776: f000 fa7b bl 8000c70 + 8001cae: f107 0314 add.w r3, r7, #20 + 8001cb2: 4619 mov r1, r3 + 8001cb4: 480d ldr r0, [pc, #52] ; (8001cec ) + 8001cb6: f000 faf3 bl 80022a0 /*Configure GPIO pin : LD2_Pin */ GPIO_InitStruct.Pin = LD2_Pin; - 800077a: 2320 movs r3, #32 - 800077c: 617b str r3, [r7, #20] + 8001cba: 2320 movs r3, #32 + 8001cbc: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 800077e: 2301 movs r3, #1 - 8000780: 61bb str r3, [r7, #24] + 8001cbe: 2301 movs r3, #1 + 8001cc0: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000782: 2300 movs r3, #0 - 8000784: 61fb str r3, [r7, #28] + 8001cc2: 2300 movs r3, #0 + 8001cc4: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000786: 2300 movs r3, #0 - 8000788: 623b str r3, [r7, #32] + 8001cc6: 2300 movs r3, #0 + 8001cc8: 623b str r3, [r7, #32] HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); - 800078a: f107 0314 add.w r3, r7, #20 - 800078e: 4619 mov r1, r3 - 8000790: 4804 ldr r0, [pc, #16] ; (80007a4 ) - 8000792: f000 fa6d bl 8000c70 + 8001cca: f107 0314 add.w r3, r7, #20 + 8001cce: 4619 mov r1, r3 + 8001cd0: 4804 ldr r0, [pc, #16] ; (8001ce4 ) + 8001cd2: f000 fae5 bl 80022a0 } - 8000796: bf00 nop - 8000798: 3728 adds r7, #40 ; 0x28 - 800079a: 46bd mov sp, r7 - 800079c: bd80 pop {r7, pc} - 800079e: bf00 nop - 80007a0: 40023800 .word 0x40023800 - 80007a4: 40020000 .word 0x40020000 - 80007a8: 10110000 .word 0x10110000 - 80007ac: 40020800 .word 0x40020800 + 8001cd6: bf00 nop + 8001cd8: 3728 adds r7, #40 ; 0x28 + 8001cda: 46bd mov sp, r7 + 8001cdc: bd80 pop {r7, pc} + 8001cde: bf00 nop + 8001ce0: 40023800 .word 0x40023800 + 8001ce4: 40020000 .word 0x40020000 + 8001ce8: 10210000 .word 0x10210000 + 8001cec: 40020800 .word 0x40020800 -080007b0 : +08001cf0 : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { - 80007b0: b480 push {r7} - 80007b2: af00 add r7, sp, #0 + 8001cf0: b480 push {r7} + 8001cf2: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8001cf4: b672 cpsid i /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 8001cf6: e7fe b.n 8001cf6 - /* USER CODE END Error_Handler_Debug */ +08001cf8 : + * @brief Alarm callback + * @param hrtc: RTC handle + * @retval None + */ +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8001cf8: b580 push {r7, lr} + 8001cfa: b082 sub sp, #8 + 8001cfc: af00 add r7, sp, #0 + 8001cfe: 6078 str r0, [r7, #4] + /* Alarm generation */ + transmit_uart("Alarm!!!!\r\n"); + 8001d00: 4803 ldr r0, [pc, #12] ; (8001d10 ) + 8001d02: f7ff fd81 bl 8001808 } - 80007b4: bf00 nop - 80007b6: 46bd mov sp, r7 - 80007b8: bc80 pop {r7} - 80007ba: 4770 bx lr + 8001d06: bf00 nop + 8001d08: 3708 adds r7, #8 + 8001d0a: 46bd mov sp, r7 + 8001d0c: bd80 pop {r7, pc} + 8001d0e: bf00 nop + 8001d10: 0800600c .word 0x0800600c -080007bc : +08001d14 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 80007bc: b580 push {r7, lr} - 80007be: b084 sub sp, #16 - 80007c0: af00 add r7, sp, #0 + 8001d14: b580 push {r7, lr} + 8001d16: b082 sub sp, #8 + 8001d18: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ - __HAL_RCC_COMP_CLK_ENABLE(); - 80007c2: 4b15 ldr r3, [pc, #84] ; (8000818 ) - 80007c4: 6a5b ldr r3, [r3, #36] ; 0x24 - 80007c6: 4a14 ldr r2, [pc, #80] ; (8000818 ) - 80007c8: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 - 80007cc: 6253 str r3, [r2, #36] ; 0x24 - 80007ce: 4b12 ldr r3, [pc, #72] ; (8000818 ) - 80007d0: 6a5b ldr r3, [r3, #36] ; 0x24 - 80007d2: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000 - 80007d6: 60fb str r3, [r7, #12] - 80007d8: 68fb ldr r3, [r7, #12] __HAL_RCC_SYSCFG_CLK_ENABLE(); - 80007da: 4b0f ldr r3, [pc, #60] ; (8000818 ) - 80007dc: 6a1b ldr r3, [r3, #32] - 80007de: 4a0e ldr r2, [pc, #56] ; (8000818 ) - 80007e0: f043 0301 orr.w r3, r3, #1 - 80007e4: 6213 str r3, [r2, #32] - 80007e6: 4b0c ldr r3, [pc, #48] ; (8000818 ) - 80007e8: 6a1b ldr r3, [r3, #32] - 80007ea: f003 0301 and.w r3, r3, #1 - 80007ee: 60bb str r3, [r7, #8] - 80007f0: 68bb ldr r3, [r7, #8] + 8001d1a: 2300 movs r3, #0 + 8001d1c: 607b str r3, [r7, #4] + 8001d1e: 4b10 ldr r3, [pc, #64] ; (8001d60 ) + 8001d20: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001d22: 4a0f ldr r2, [pc, #60] ; (8001d60 ) + 8001d24: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8001d28: 6453 str r3, [r2, #68] ; 0x44 + 8001d2a: 4b0d ldr r3, [pc, #52] ; (8001d60 ) + 8001d2c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001d2e: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001d32: 607b str r3, [r7, #4] + 8001d34: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 80007f2: 4b09 ldr r3, [pc, #36] ; (8000818 ) - 80007f4: 6a5b ldr r3, [r3, #36] ; 0x24 - 80007f6: 4a08 ldr r2, [pc, #32] ; (8000818 ) - 80007f8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 80007fc: 6253 str r3, [r2, #36] ; 0x24 - 80007fe: 4b06 ldr r3, [pc, #24] ; (8000818 ) - 8000800: 6a5b ldr r3, [r3, #36] ; 0x24 - 8000802: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8000806: 607b str r3, [r7, #4] - 8000808: 687b ldr r3, [r7, #4] + 8001d36: 2300 movs r3, #0 + 8001d38: 603b str r3, [r7, #0] + 8001d3a: 4b09 ldr r3, [pc, #36] ; (8001d60 ) + 8001d3c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001d3e: 4a08 ldr r2, [pc, #32] ; (8001d60 ) + 8001d40: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8001d44: 6413 str r3, [r2, #64] ; 0x40 + 8001d46: 4b06 ldr r3, [pc, #24] ; (8001d60 ) + 8001d48: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001d4a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001d4e: 603b str r3, [r7, #0] + 8001d50: 683b ldr r3, [r7, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); - 800080a: 2007 movs r0, #7 - 800080c: f000 f9fc bl 8000c08 + 8001d52: 2007 movs r0, #7 + 8001d54: f000 fa62 bl 800221c /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8000810: bf00 nop - 8000812: 3710 adds r7, #16 - 8000814: 46bd mov sp, r7 - 8000816: bd80 pop {r7, pc} - 8000818: 40023800 .word 0x40023800 + 8001d58: bf00 nop + 8001d5a: 3708 adds r7, #8 + 8001d5c: 46bd mov sp, r7 + 8001d5e: bd80 pop {r7, pc} + 8001d60: 40023800 .word 0x40023800 -0800081c : +08001d64 : * This function configures the hardware resources used in this example * @param hrtc: RTC handle pointer * @retval None */ void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) { - 800081c: b480 push {r7} - 800081e: b083 sub sp, #12 - 8000820: af00 add r7, sp, #0 - 8000822: 6078 str r0, [r7, #4] + 8001d64: b580 push {r7, lr} + 8001d66: b082 sub sp, #8 + 8001d68: af00 add r7, sp, #0 + 8001d6a: 6078 str r0, [r7, #4] if(hrtc->Instance==RTC) - 8000824: 687b ldr r3, [r7, #4] - 8000826: 681b ldr r3, [r3, #0] - 8000828: 4a05 ldr r2, [pc, #20] ; (8000840 ) - 800082a: 4293 cmp r3, r2 - 800082c: d102 bne.n 8000834 + 8001d6c: 687b ldr r3, [r7, #4] + 8001d6e: 681b ldr r3, [r3, #0] + 8001d70: 4a08 ldr r2, [pc, #32] ; (8001d94 ) + 8001d72: 4293 cmp r3, r2 + 8001d74: d10a bne.n 8001d8c { /* USER CODE BEGIN RTC_MspInit 0 */ /* USER CODE END RTC_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_RTC_ENABLE(); - 800082e: 4b05 ldr r3, [pc, #20] ; (8000844 ) - 8000830: 2201 movs r2, #1 - 8000832: 601a str r2, [r3, #0] + 8001d76: 4b08 ldr r3, [pc, #32] ; (8001d98 ) + 8001d78: 2201 movs r2, #1 + 8001d7a: 601a str r2, [r3, #0] + /* RTC interrupt Init */ + HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0); + 8001d7c: 2200 movs r2, #0 + 8001d7e: 2100 movs r1, #0 + 8001d80: 2029 movs r0, #41 ; 0x29 + 8001d82: f000 fa56 bl 8002232 + HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); + 8001d86: 2029 movs r0, #41 ; 0x29 + 8001d88: f000 fa6f bl 800226a /* USER CODE BEGIN RTC_MspInit 1 */ /* USER CODE END RTC_MspInit 1 */ } } - 8000834: bf00 nop - 8000836: 370c adds r7, #12 - 8000838: 46bd mov sp, r7 - 800083a: bc80 pop {r7} - 800083c: 4770 bx lr - 800083e: bf00 nop - 8000840: 40002800 .word 0x40002800 - 8000844: 424706d8 .word 0x424706d8 + 8001d8c: bf00 nop + 8001d8e: 3708 adds r7, #8 + 8001d90: 46bd mov sp, r7 + 8001d92: bd80 pop {r7, pc} + 8001d94: 40002800 .word 0x40002800 + 8001d98: 42470e3c .word 0x42470e3c -08000848 : +08001d9c : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8000848: b580 push {r7, lr} - 800084a: b08a sub sp, #40 ; 0x28 - 800084c: af00 add r7, sp, #0 - 800084e: 6078 str r0, [r7, #4] + 8001d9c: b580 push {r7, lr} + 8001d9e: b08a sub sp, #40 ; 0x28 + 8001da0: af00 add r7, sp, #0 + 8001da2: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000850: f107 0314 add.w r3, r7, #20 - 8000854: 2200 movs r2, #0 - 8000856: 601a str r2, [r3, #0] - 8000858: 605a str r2, [r3, #4] - 800085a: 609a str r2, [r3, #8] - 800085c: 60da str r2, [r3, #12] - 800085e: 611a str r2, [r3, #16] + 8001da4: f107 0314 add.w r3, r7, #20 + 8001da8: 2200 movs r2, #0 + 8001daa: 601a str r2, [r3, #0] + 8001dac: 605a str r2, [r3, #4] + 8001dae: 609a str r2, [r3, #8] + 8001db0: 60da str r2, [r3, #12] + 8001db2: 611a str r2, [r3, #16] if(huart->Instance==USART2) - 8000860: 687b ldr r3, [r7, #4] - 8000862: 681b ldr r3, [r3, #0] - 8000864: 4a17 ldr r2, [pc, #92] ; (80008c4 ) - 8000866: 4293 cmp r3, r2 - 8000868: d127 bne.n 80008ba + 8001db4: 687b ldr r3, [r7, #4] + 8001db6: 681b ldr r3, [r3, #0] + 8001db8: 4a19 ldr r2, [pc, #100] ; (8001e20 ) + 8001dba: 4293 cmp r3, r2 + 8001dbc: d12b bne.n 8001e16 { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - 800086a: 4b17 ldr r3, [pc, #92] ; (80008c8 ) - 800086c: 6a5b ldr r3, [r3, #36] ; 0x24 - 800086e: 4a16 ldr r2, [pc, #88] ; (80008c8 ) - 8000870: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8000874: 6253 str r3, [r2, #36] ; 0x24 - 8000876: 4b14 ldr r3, [pc, #80] ; (80008c8 ) - 8000878: 6a5b ldr r3, [r3, #36] ; 0x24 - 800087a: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800087e: 613b str r3, [r7, #16] - 8000880: 693b ldr r3, [r7, #16] + 8001dbe: 2300 movs r3, #0 + 8001dc0: 613b str r3, [r7, #16] + 8001dc2: 4b18 ldr r3, [pc, #96] ; (8001e24 ) + 8001dc4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001dc6: 4a17 ldr r2, [pc, #92] ; (8001e24 ) + 8001dc8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8001dcc: 6413 str r3, [r2, #64] ; 0x40 + 8001dce: 4b15 ldr r3, [pc, #84] ; (8001e24 ) + 8001dd0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001dd2: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001dd6: 613b str r3, [r7, #16] + 8001dd8: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000882: 4b11 ldr r3, [pc, #68] ; (80008c8 ) - 8000884: 69db ldr r3, [r3, #28] - 8000886: 4a10 ldr r2, [pc, #64] ; (80008c8 ) - 8000888: f043 0301 orr.w r3, r3, #1 - 800088c: 61d3 str r3, [r2, #28] - 800088e: 4b0e ldr r3, [pc, #56] ; (80008c8 ) - 8000890: 69db ldr r3, [r3, #28] - 8000892: f003 0301 and.w r3, r3, #1 - 8000896: 60fb str r3, [r7, #12] - 8000898: 68fb ldr r3, [r7, #12] + 8001dda: 2300 movs r3, #0 + 8001ddc: 60fb str r3, [r7, #12] + 8001dde: 4b11 ldr r3, [pc, #68] ; (8001e24 ) + 8001de0: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001de2: 4a10 ldr r2, [pc, #64] ; (8001e24 ) + 8001de4: f043 0301 orr.w r3, r3, #1 + 8001de8: 6313 str r3, [r2, #48] ; 0x30 + 8001dea: 4b0e ldr r3, [pc, #56] ; (8001e24 ) + 8001dec: 6b1b ldr r3, [r3, #48] ; 0x30 + 8001dee: f003 0301 and.w r3, r3, #1 + 8001df2: 60fb str r3, [r7, #12] + 8001df4: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; - 800089a: 230c movs r3, #12 - 800089c: 617b str r3, [r7, #20] + 8001df6: 230c movs r3, #12 + 8001df8: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 800089e: 2302 movs r3, #2 - 80008a0: 61bb str r3, [r7, #24] + 8001dfa: 2302 movs r3, #2 + 8001dfc: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 80008a2: 2300 movs r3, #0 - 80008a4: 61fb str r3, [r7, #28] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 80008a6: 2303 movs r3, #3 - 80008a8: 623b str r3, [r7, #32] + 8001dfe: 2300 movs r3, #0 + 8001e00: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001e02: 2300 movs r3, #0 + 8001e04: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - 80008aa: 2307 movs r3, #7 - 80008ac: 627b str r3, [r7, #36] ; 0x24 + 8001e06: 2307 movs r3, #7 + 8001e08: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 80008ae: f107 0314 add.w r3, r7, #20 - 80008b2: 4619 mov r1, r3 - 80008b4: 4805 ldr r0, [pc, #20] ; (80008cc ) - 80008b6: f000 f9db bl 8000c70 + 8001e0a: f107 0314 add.w r3, r7, #20 + 8001e0e: 4619 mov r1, r3 + 8001e10: 4805 ldr r0, [pc, #20] ; (8001e28 ) + 8001e12: f000 fa45 bl 80022a0 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } - 80008ba: bf00 nop - 80008bc: 3728 adds r7, #40 ; 0x28 - 80008be: 46bd mov sp, r7 - 80008c0: bd80 pop {r7, pc} - 80008c2: bf00 nop - 80008c4: 40004400 .word 0x40004400 - 80008c8: 40023800 .word 0x40023800 - 80008cc: 40020000 .word 0x40020000 + 8001e16: bf00 nop + 8001e18: 3728 adds r7, #40 ; 0x28 + 8001e1a: 46bd mov sp, r7 + 8001e1c: bd80 pop {r7, pc} + 8001e1e: bf00 nop + 8001e20: 40004400 .word 0x40004400 + 8001e24: 40023800 .word 0x40023800 + 8001e28: 40020000 .word 0x40020000 -080008d0 : +08001e2c : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 80008d0: b480 push {r7} - 80008d2: af00 add r7, sp, #0 + 8001e2c: b480 push {r7} + 8001e2e: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8001e30: e7fe b.n 8001e30 - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - 80008d4: bf00 nop - 80008d6: 46bd mov sp, r7 - 80008d8: bc80 pop {r7} - 80008da: 4770 bx lr - -080008dc : +08001e32 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 80008dc: b480 push {r7} - 80008de: af00 add r7, sp, #0 + 8001e32: b480 push {r7} + 8001e34: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 80008e0: e7fe b.n 80008e0 + 8001e36: e7fe b.n 8001e36 -080008e2 : +08001e38 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 80008e2: b480 push {r7} - 80008e4: af00 add r7, sp, #0 + 8001e38: b480 push {r7} + 8001e3a: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 80008e6: e7fe b.n 80008e6 + 8001e3c: e7fe b.n 8001e3c -080008e8 : +08001e3e : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 80008e8: b480 push {r7} - 80008ea: af00 add r7, sp, #0 + 8001e3e: b480 push {r7} + 8001e40: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 80008ec: e7fe b.n 80008ec + 8001e42: e7fe b.n 8001e42 -080008ee : +08001e44 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 80008ee: b480 push {r7} - 80008f0: af00 add r7, sp, #0 + 8001e44: b480 push {r7} + 8001e46: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 80008f2: e7fe b.n 80008f2 + 8001e48: e7fe b.n 8001e48 -080008f4 : +08001e4a : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { - 80008f4: b480 push {r7} - 80008f6: af00 add r7, sp, #0 + 8001e4a: b480 push {r7} + 8001e4c: af00 add r7, sp, #0 - /* USER CODE END SVC_IRQn 0 */ - /* USER CODE BEGIN SVC_IRQn 1 */ + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ - /* USER CODE END SVC_IRQn 1 */ + /* USER CODE END SVCall_IRQn 1 */ } - 80008f8: bf00 nop - 80008fa: 46bd mov sp, r7 - 80008fc: bc80 pop {r7} - 80008fe: 4770 bx lr + 8001e4e: bf00 nop + 8001e50: 46bd mov sp, r7 + 8001e52: f85d 7b04 ldr.w r7, [sp], #4 + 8001e56: 4770 bx lr -08000900 : +08001e58 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8000900: b480 push {r7} - 8000902: af00 add r7, sp, #0 + 8001e58: b480 push {r7} + 8001e5a: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8000904: bf00 nop - 8000906: 46bd mov sp, r7 - 8000908: bc80 pop {r7} - 800090a: 4770 bx lr + 8001e5c: bf00 nop + 8001e5e: 46bd mov sp, r7 + 8001e60: f85d 7b04 ldr.w r7, [sp], #4 + 8001e64: 4770 bx lr -0800090c : +08001e66 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { - 800090c: b480 push {r7} - 800090e: af00 add r7, sp, #0 + 8001e66: b480 push {r7} + 8001e68: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } - 8000910: bf00 nop - 8000912: 46bd mov sp, r7 - 8000914: bc80 pop {r7} - 8000916: 4770 bx lr + 8001e6a: bf00 nop + 8001e6c: 46bd mov sp, r7 + 8001e6e: f85d 7b04 ldr.w r7, [sp], #4 + 8001e72: 4770 bx lr -08000918 : +08001e74 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { - 8000918: b580 push {r7, lr} - 800091a: af00 add r7, sp, #0 + 8001e74: b580 push {r7, lr} + 8001e76: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); - 800091c: f000 f886 bl 8000a2c + 8001e78: f000 f89e bl 8001fb8 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } - 8000920: bf00 nop - 8000922: bd80 pop {r7, pc} + 8001e7c: bf00 nop + 8001e7e: bd80 pop {r7, pc} -08000924 : - * SystemCoreClock variable. +08001e80 : + +/** + * @brief This function handles RTC alarms A and B interrupt through EXTI line 17. + */ +void RTC_Alarm_IRQHandler(void) +{ + 8001e80: b580 push {r7, lr} + 8001e82: af00 add r7, sp, #0 + /* USER CODE BEGIN RTC_Alarm_IRQn 0 */ + + /* USER CODE END RTC_Alarm_IRQn 0 */ + HAL_RTC_AlarmIRQHandler(&hrtc); + 8001e84: 4802 ldr r0, [pc, #8] ; (8001e90 ) + 8001e86: f001 fced bl 8003864 + /* USER CODE BEGIN RTC_Alarm_IRQn 1 */ + + /* USER CODE END RTC_Alarm_IRQn 1 */ +} + 8001e8a: bf00 nop + 8001e8c: bd80 pop {r7, pc} + 8001e8e: bf00 nop + 8001e90: 200000e4 .word 0x200000e4 + +08001e94 : + * configuration. * @param None * @retval None */ -void SystemInit (void) +void SystemInit(void) { - 8000924: b480 push {r7} - 8000926: af00 add r7, sp, #0 -#endif /* DATA_IN_ExtSRAM */ - + 8001e94: b480 push {r7} + 8001e96: af00 add r7, sp, #0 + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + 8001e98: 4b08 ldr r3, [pc, #32] ; (8001ebc ) + 8001e9a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8001e9e: 4a07 ldr r2, [pc, #28] ; (8001ebc ) + 8001ea0: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8001ea4: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + + /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ - 8000928: 4b03 ldr r3, [pc, #12] ; (8000938 ) - 800092a: f04f 6200 mov.w r2, #134217728 ; 0x8000000 - 800092e: 609a str r2, [r3, #8] + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + 8001ea8: 4b04 ldr r3, [pc, #16] ; (8001ebc ) + 8001eaa: f04f 6200 mov.w r2, #134217728 ; 0x8000000 + 8001eae: 609a str r2, [r3, #8] #endif } - 8000930: bf00 nop - 8000932: 46bd mov sp, r7 - 8000934: bc80 pop {r7} - 8000936: 4770 bx lr - 8000938: e000ed00 .word 0xe000ed00 + 8001eb0: bf00 nop + 8001eb2: 46bd mov sp, r7 + 8001eb4: f85d 7b04 ldr.w r7, [sp], #4 + 8001eb8: 4770 bx lr + 8001eba: bf00 nop + 8001ebc: e000ed00 .word 0xe000ed00 -0800093c : - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: +08001ec0 : + 8001ec0: f8df d034 ldr.w sp, [pc, #52] ; 8001ef8 + 8001ec4: 2100 movs r1, #0 + 8001ec6: e003 b.n 8001ed0 -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - 800093c: 2100 movs r1, #0 - b LoopCopyDataInit - 800093e: e003 b.n 8000948 +08001ec8 : + 8001ec8: 4b0c ldr r3, [pc, #48] ; (8001efc ) + 8001eca: 585b ldr r3, [r3, r1] + 8001ecc: 5043 str r3, [r0, r1] + 8001ece: 3104 adds r1, #4 -08000940 : +08001ed0 : + 8001ed0: 480b ldr r0, [pc, #44] ; (8001f00 ) + 8001ed2: 4b0c ldr r3, [pc, #48] ; (8001f04 ) + 8001ed4: 1842 adds r2, r0, r1 + 8001ed6: 429a cmp r2, r3 + 8001ed8: d3f6 bcc.n 8001ec8 + 8001eda: 4a0b ldr r2, [pc, #44] ; (8001f08 ) + 8001edc: e002 b.n 8001ee4 -CopyDataInit: - ldr r3, =_sidata - 8000940: 4b0b ldr r3, [pc, #44] ; (8000970 ) - ldr r3, [r3, r1] - 8000942: 585b ldr r3, [r3, r1] - str r3, [r0, r1] - 8000944: 5043 str r3, [r0, r1] - adds r1, r1, #4 - 8000946: 3104 adds r1, #4 +08001ede : + 8001ede: 2300 movs r3, #0 + 8001ee0: f842 3b04 str.w r3, [r2], #4 -08000948 : +08001ee4 : + 8001ee4: 4b09 ldr r3, [pc, #36] ; (8001f0c ) + 8001ee6: 429a cmp r2, r3 + 8001ee8: d3f9 bcc.n 8001ede + 8001eea: f7ff ffd3 bl 8001e94 + 8001eee: f002 fa4b bl 8004388 <__libc_init_array> + 8001ef2: f7ff fc9f bl 8001834
+ 8001ef6: 4770 bx lr + 8001ef8: 20018000 .word 0x20018000 + 8001efc: 08006220 .word 0x08006220 + 8001f00: 20000000 .word 0x20000000 + 8001f04: 20000088 .word 0x20000088 + 8001f08: 20000088 .word 0x20000088 + 8001f0c: 20000148 .word 0x20000148 -LoopCopyDataInit: - ldr r0, =_sdata - 8000948: 480a ldr r0, [pc, #40] ; (8000974 ) - ldr r3, =_edata - 800094a: 4b0b ldr r3, [pc, #44] ; (8000978 ) - adds r2, r0, r1 - 800094c: 1842 adds r2, r0, r1 - cmp r2, r3 - 800094e: 429a cmp r2, r3 - bcc CopyDataInit - 8000950: d3f6 bcc.n 8000940 - ldr r2, =_sbss - 8000952: 4a0a ldr r2, [pc, #40] ; (800097c ) - b LoopFillZerobss - 8000954: e002 b.n 800095c +08001f10 : + 8001f10: e7fe b.n 8001f10 + ... -08000956 : -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - 8000956: 2300 movs r3, #0 - str r3, [r2], #4 - 8000958: f842 3b04 str.w r3, [r2], #4 - -0800095c : - -LoopFillZerobss: - ldr r3, = _ebss - 800095c: 4b08 ldr r3, [pc, #32] ; (8000980 ) - cmp r2, r3 - 800095e: 429a cmp r2, r3 - bcc FillZerobss - 8000960: d3f9 bcc.n 8000956 - -/* Call the clock system intitialization function.*/ - bl SystemInit - 8000962: f7ff ffdf bl 8000924 -/* Call static constructors */ - bl __libc_init_array - 8000966: f001 fe05 bl 8002574 <__libc_init_array> -/* Call the application's entry point.*/ - bl main - 800096a: f7ff fd89 bl 8000480
- bx lr - 800096e: 4770 bx lr - ldr r3, =_sidata - 8000970: 08002618 .word 0x08002618 - ldr r0, =_sdata - 8000974: 20000000 .word 0x20000000 - ldr r3, =_edata - 8000978: 2000000c .word 0x2000000c - ldr r2, =_sbss - 800097c: 2000000c .word 0x2000000c - ldr r3, = _ebss - 8000980: 200000a4 .word 0x200000a4 - -08000984 : - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - 8000984: e7fe b.n 8000984 - -08000986 : - * In the default implementation,Systick is used as source of time base. - * the tick variable is incremented each 1ms in its ISR. +08001f14 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8000986: b580 push {r7, lr} - 8000988: b082 sub sp, #8 - 800098a: af00 add r7, sp, #0 - HAL_StatusTypeDef status = HAL_OK; - 800098c: 2300 movs r3, #0 - 800098e: 71fb strb r3, [r7, #7] -#if (PREFETCH_ENABLE != 0) + 8001f14: b580 push {r7, lr} + 8001f16: af00 add r7, sp, #0 + /* Configure Flash prefetch, Instruction cache, Data cache */ +#if (INSTRUCTION_CACHE_ENABLE != 0U) + __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); + 8001f18: 4b0e ldr r3, [pc, #56] ; (8001f54 ) + 8001f1a: 681b ldr r3, [r3, #0] + 8001f1c: 4a0d ldr r2, [pc, #52] ; (8001f54 ) + 8001f1e: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8001f22: 6013 str r3, [r2, #0] +#endif /* INSTRUCTION_CACHE_ENABLE */ + +#if (DATA_CACHE_ENABLE != 0U) + __HAL_FLASH_DATA_CACHE_ENABLE(); + 8001f24: 4b0b ldr r3, [pc, #44] ; (8001f54 ) + 8001f26: 681b ldr r3, [r3, #0] + 8001f28: 4a0a ldr r2, [pc, #40] ; (8001f54 ) + 8001f2a: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8001f2e: 6013 str r3, [r2, #0] +#endif /* DATA_CACHE_ENABLE */ + +#if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + 8001f30: 4b08 ldr r3, [pc, #32] ; (8001f54 ) + 8001f32: 681b ldr r3, [r3, #0] + 8001f34: 4a07 ldr r2, [pc, #28] ; (8001f54 ) + 8001f36: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8001f3a: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8000990: 2003 movs r0, #3 - 8000992: f000 f939 bl 8000c08 + 8001f3c: 2003 movs r0, #3 + 8001f3e: f000 f96d bl 800221c - /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - 8000996: 2000 movs r0, #0 - 8000998: f000 f80e bl 80009b8 - 800099c: 4603 mov r3, r0 - 800099e: 2b00 cmp r3, #0 - 80009a0: d002 beq.n 80009a8 - { - status = HAL_ERROR; - 80009a2: 2301 movs r3, #1 - 80009a4: 71fb strb r3, [r7, #7] - 80009a6: e001 b.n 80009ac - } - else - { - /* Init the low level hardware */ - HAL_MspInit(); - 80009a8: f7ff ff08 bl 80007bc - } + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + 8001f42: 2000 movs r0, #0 + 8001f44: f000 f808 bl 8001f58 + + /* Init the low level hardware */ + HAL_MspInit(); + 8001f48: f7ff fee4 bl 8001d14 /* Return function status */ - return status; - 80009ac: 79fb ldrb r3, [r7, #7] + return HAL_OK; + 8001f4c: 2300 movs r3, #0 } - 80009ae: 4618 mov r0, r3 - 80009b0: 3708 adds r7, #8 - 80009b2: 46bd mov sp, r7 - 80009b4: bd80 pop {r7, pc} - ... + 8001f4e: 4618 mov r0, r3 + 8001f50: bd80 pop {r7, pc} + 8001f52: bf00 nop + 8001f54: 40023c00 .word 0x40023c00 -080009b8 : +08001f58 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 80009b8: b580 push {r7, lr} - 80009ba: b084 sub sp, #16 - 80009bc: af00 add r7, sp, #0 - 80009be: 6078 str r0, [r7, #4] - HAL_StatusTypeDef status = HAL_OK; - 80009c0: 2300 movs r3, #0 - 80009c2: 73fb strb r3, [r7, #15] - - if (uwTickFreq != 0U) - 80009c4: 4b16 ldr r3, [pc, #88] ; (8000a20 ) - 80009c6: 681b ldr r3, [r3, #0] - 80009c8: 2b00 cmp r3, #0 - 80009ca: d022 beq.n 8000a12 + 8001f58: b580 push {r7, lr} + 8001f5a: b082 sub sp, #8 + 8001f5c: af00 add r7, sp, #0 + 8001f5e: 6078 str r0, [r7, #4] + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + 8001f60: 4b12 ldr r3, [pc, #72] ; (8001fac ) + 8001f62: 681a ldr r2, [r3, #0] + 8001f64: 4b12 ldr r3, [pc, #72] ; (8001fb0 ) + 8001f66: 781b ldrb r3, [r3, #0] + 8001f68: 4619 mov r1, r3 + 8001f6a: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001f6e: fbb3 f3f1 udiv r3, r3, r1 + 8001f72: fbb2 f3f3 udiv r3, r2, r3 + 8001f76: 4618 mov r0, r3 + 8001f78: f000 f985 bl 8002286 + 8001f7c: 4603 mov r3, r0 + 8001f7e: 2b00 cmp r3, #0 + 8001f80: d001 beq.n 8001f86 { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) - 80009cc: 4b15 ldr r3, [pc, #84] ; (8000a24 ) - 80009ce: 681a ldr r2, [r3, #0] - 80009d0: 4b13 ldr r3, [pc, #76] ; (8000a20 ) - 80009d2: 681b ldr r3, [r3, #0] - 80009d4: f44f 717a mov.w r1, #1000 ; 0x3e8 - 80009d8: fbb1 f3f3 udiv r3, r1, r3 - 80009dc: fbb2 f3f3 udiv r3, r2, r3 - 80009e0: 4618 mov r0, r3 - 80009e2: f000 f938 bl 8000c56 - 80009e6: 4603 mov r3, r0 - 80009e8: 2b00 cmp r3, #0 - 80009ea: d10f bne.n 8000a0c - { - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 80009ec: 687b ldr r3, [r7, #4] - 80009ee: 2b0f cmp r3, #15 - 80009f0: d809 bhi.n 8000a06 - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - 80009f2: 2200 movs r2, #0 - 80009f4: 6879 ldr r1, [r7, #4] - 80009f6: f04f 30ff mov.w r0, #4294967295 - 80009fa: f000 f910 bl 8000c1e - uwTickPrio = TickPriority; - 80009fe: 4a0a ldr r2, [pc, #40] ; (8000a28 ) - 8000a00: 687b ldr r3, [r7, #4] - 8000a02: 6013 str r3, [r2, #0] - 8000a04: e007 b.n 8000a16 - } - else - { - status = HAL_ERROR; - 8000a06: 2301 movs r3, #1 - 8000a08: 73fb strb r3, [r7, #15] - 8000a0a: e004 b.n 8000a16 - } - } - else - { - status = HAL_ERROR; - 8000a0c: 2301 movs r3, #1 - 8000a0e: 73fb strb r3, [r7, #15] - 8000a10: e001 b.n 8000a16 - } + return HAL_ERROR; + 8001f82: 2301 movs r3, #1 + 8001f84: e00e b.n 8001fa4 } - else + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001f86: 687b ldr r3, [r7, #4] + 8001f88: 2b0f cmp r3, #15 + 8001f8a: d80a bhi.n 8001fa2 { - status = HAL_ERROR; - 8000a12: 2301 movs r3, #1 - 8000a14: 73fb strb r3, [r7, #15] + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001f8c: 2200 movs r2, #0 + 8001f8e: 6879 ldr r1, [r7, #4] + 8001f90: f04f 30ff mov.w r0, #4294967295 + 8001f94: f000 f94d bl 8002232 + uwTickPrio = TickPriority; + 8001f98: 4a06 ldr r2, [pc, #24] ; (8001fb4 ) + 8001f9a: 687b ldr r3, [r7, #4] + 8001f9c: 6013 str r3, [r2, #0] + { + return HAL_ERROR; } /* Return function status */ - return status; - 8000a16: 7bfb ldrb r3, [r7, #15] + return HAL_OK; + 8001f9e: 2300 movs r3, #0 + 8001fa0: e000 b.n 8001fa4 + return HAL_ERROR; + 8001fa2: 2301 movs r3, #1 } - 8000a18: 4618 mov r0, r3 - 8000a1a: 3710 adds r7, #16 - 8000a1c: 46bd mov sp, r7 - 8000a1e: bd80 pop {r7, pc} - 8000a20: 20000008 .word 0x20000008 - 8000a24: 20000000 .word 0x20000000 - 8000a28: 20000004 .word 0x20000004 + 8001fa4: 4618 mov r0, r3 + 8001fa6: 3708 adds r7, #8 + 8001fa8: 46bd mov sp, r7 + 8001faa: bd80 pop {r7, pc} + 8001fac: 20000014 .word 0x20000014 + 8001fb0: 2000001c .word 0x2000001c + 8001fb4: 20000018 .word 0x20000018 -08000a2c : - * @note This function is declared as __weak to be overwritten in case of other +08001fb8 : + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8000a2c: b480 push {r7} - 8000a2e: af00 add r7, sp, #0 + 8001fb8: b480 push {r7} + 8001fba: af00 add r7, sp, #0 uwTick += uwTickFreq; - 8000a30: 4b05 ldr r3, [pc, #20] ; (8000a48 ) - 8000a32: 681a ldr r2, [r3, #0] - 8000a34: 4b05 ldr r3, [pc, #20] ; (8000a4c ) - 8000a36: 681b ldr r3, [r3, #0] - 8000a38: 4413 add r3, r2 - 8000a3a: 4a03 ldr r2, [pc, #12] ; (8000a48 ) - 8000a3c: 6013 str r3, [r2, #0] + 8001fbc: 4b06 ldr r3, [pc, #24] ; (8001fd8 ) + 8001fbe: 781b ldrb r3, [r3, #0] + 8001fc0: 461a mov r2, r3 + 8001fc2: 4b06 ldr r3, [pc, #24] ; (8001fdc ) + 8001fc4: 681b ldr r3, [r3, #0] + 8001fc6: 4413 add r3, r2 + 8001fc8: 4a04 ldr r2, [pc, #16] ; (8001fdc ) + 8001fca: 6013 str r3, [r2, #0] } - 8000a3e: bf00 nop - 8000a40: 46bd mov sp, r7 - 8000a42: bc80 pop {r7} - 8000a44: 4770 bx lr - 8000a46: bf00 nop - 8000a48: 200000a0 .word 0x200000a0 - 8000a4c: 20000008 .word 0x20000008 + 8001fcc: bf00 nop + 8001fce: 46bd mov sp, r7 + 8001fd0: f85d 7b04 ldr.w r7, [sp], #4 + 8001fd4: 4770 bx lr + 8001fd6: bf00 nop + 8001fd8: 2000001c .word 0x2000001c + 8001fdc: 20000144 .word 0x20000144 -08000a50 : - * @note This function is declared as __weak to be overwritten in case of other +08001fe0 : + * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8000a50: b480 push {r7} - 8000a52: af00 add r7, sp, #0 + 8001fe0: b480 push {r7} + 8001fe2: af00 add r7, sp, #0 return uwTick; - 8000a54: 4b02 ldr r3, [pc, #8] ; (8000a60 ) - 8000a56: 681b ldr r3, [r3, #0] + 8001fe4: 4b03 ldr r3, [pc, #12] ; (8001ff4 ) + 8001fe6: 681b ldr r3, [r3, #0] } - 8000a58: 4618 mov r0, r3 - 8000a5a: 46bd mov sp, r7 - 8000a5c: bc80 pop {r7} - 8000a5e: 4770 bx lr - 8000a60: 200000a0 .word 0x200000a0 + 8001fe8: 4618 mov r0, r3 + 8001fea: 46bd mov sp, r7 + 8001fec: f85d 7b04 ldr.w r7, [sp], #4 + 8001ff0: 4770 bx lr + 8001ff2: bf00 nop + 8001ff4: 20000144 .word 0x20000144 -08000a64 : +08001ff8 : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { - 8000a64: b580 push {r7, lr} - 8000a66: b084 sub sp, #16 - 8000a68: af00 add r7, sp, #0 - 8000a6a: 6078 str r0, [r7, #4] + 8001ff8: b580 push {r7, lr} + 8001ffa: b084 sub sp, #16 + 8001ffc: af00 add r7, sp, #0 + 8001ffe: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); - 8000a6c: f7ff fff0 bl 8000a50 - 8000a70: 60b8 str r0, [r7, #8] + 8002000: f7ff ffee bl 8001fe0 + 8002004: 60b8 str r0, [r7, #8] uint32_t wait = Delay; - 8000a72: 687b ldr r3, [r7, #4] - 8000a74: 60fb str r3, [r7, #12] + 8002006: 687b ldr r3, [r7, #4] + 8002008: 60fb str r3, [r7, #12] - /* Add a period to guaranty minimum wait */ + /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) - 8000a76: 68fb ldr r3, [r7, #12] - 8000a78: f1b3 3fff cmp.w r3, #4294967295 - 8000a7c: d004 beq.n 8000a88 + 800200a: 68fb ldr r3, [r7, #12] + 800200c: f1b3 3fff cmp.w r3, #4294967295 + 8002010: d005 beq.n 800201e { wait += (uint32_t)(uwTickFreq); - 8000a7e: 4b09 ldr r3, [pc, #36] ; (8000aa4 ) - 8000a80: 681b ldr r3, [r3, #0] - 8000a82: 68fa ldr r2, [r7, #12] - 8000a84: 4413 add r3, r2 - 8000a86: 60fb str r3, [r7, #12] + 8002012: 4b09 ldr r3, [pc, #36] ; (8002038 ) + 8002014: 781b ldrb r3, [r3, #0] + 8002016: 461a mov r2, r3 + 8002018: 68fb ldr r3, [r7, #12] + 800201a: 4413 add r3, r2 + 800201c: 60fb str r3, [r7, #12] } while((HAL_GetTick() - tickstart) < wait) - 8000a88: bf00 nop - 8000a8a: f7ff ffe1 bl 8000a50 - 8000a8e: 4602 mov r2, r0 - 8000a90: 68bb ldr r3, [r7, #8] - 8000a92: 1ad3 subs r3, r2, r3 - 8000a94: 68fa ldr r2, [r7, #12] - 8000a96: 429a cmp r2, r3 - 8000a98: d8f7 bhi.n 8000a8a + 800201e: bf00 nop + 8002020: f7ff ffde bl 8001fe0 + 8002024: 4602 mov r2, r0 + 8002026: 68bb ldr r3, [r7, #8] + 8002028: 1ad3 subs r3, r2, r3 + 800202a: 68fa ldr r2, [r7, #12] + 800202c: 429a cmp r2, r3 + 800202e: d8f7 bhi.n 8002020 { } } - 8000a9a: bf00 nop - 8000a9c: 3710 adds r7, #16 - 8000a9e: 46bd mov sp, r7 - 8000aa0: bd80 pop {r7, pc} - 8000aa2: bf00 nop - 8000aa4: 20000008 .word 0x20000008 + 8002030: bf00 nop + 8002032: 3710 adds r7, #16 + 8002034: 46bd mov sp, r7 + 8002036: bd80 pop {r7, pc} + 8002038: 2000001c .word 0x2000001c -08000aa8 <__NVIC_SetPriorityGrouping>: +0800203c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + 800203c: b480 push {r7} + 800203e: af00 add r7, sp, #0 + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; + 8002040: 4b05 ldr r3, [pc, #20] ; (8002058 ) + 8002042: 681b ldr r3, [r3, #0] + 8002044: 4a04 ldr r2, [pc, #16] ; (8002058 ) + 8002046: f023 0302 bic.w r3, r3, #2 + 800204a: 6013 str r3, [r2, #0] +} + 800204c: bf00 nop + 800204e: 46bd mov sp, r7 + 8002050: f85d 7b04 ldr.w r7, [sp], #4 + 8002054: 4770 bx lr + 8002056: bf00 nop + 8002058: e000e010 .word 0xe000e010 + +0800205c : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + 800205c: b480 push {r7} + 800205e: af00 add r7, sp, #0 + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; + 8002060: 4b05 ldr r3, [pc, #20] ; (8002078 ) + 8002062: 681b ldr r3, [r3, #0] + 8002064: 4a04 ldr r2, [pc, #16] ; (8002078 ) + 8002066: f043 0302 orr.w r3, r3, #2 + 800206a: 6013 str r3, [r2, #0] +} + 800206c: bf00 nop + 800206e: 46bd mov sp, r7 + 8002070: f85d 7b04 ldr.w r7, [sp], #4 + 8002074: 4770 bx lr + 8002076: bf00 nop + 8002078: e000e010 .word 0xe000e010 + +0800207c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8000aa8: b480 push {r7} - 8000aaa: b085 sub sp, #20 - 8000aac: af00 add r7, sp, #0 - 8000aae: 6078 str r0, [r7, #4] + 800207c: b480 push {r7} + 800207e: b085 sub sp, #20 + 8002080: af00 add r7, sp, #0 + 8002082: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8000ab0: 687b ldr r3, [r7, #4] - 8000ab2: f003 0307 and.w r3, r3, #7 - 8000ab6: 60fb str r3, [r7, #12] + 8002084: 687b ldr r3, [r7, #4] + 8002086: f003 0307 and.w r3, r3, #7 + 800208a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8000ab8: 4b0c ldr r3, [pc, #48] ; (8000aec <__NVIC_SetPriorityGrouping+0x44>) - 8000aba: 68db ldr r3, [r3, #12] - 8000abc: 60bb str r3, [r7, #8] + 800208c: 4b0c ldr r3, [pc, #48] ; (80020c0 <__NVIC_SetPriorityGrouping+0x44>) + 800208e: 68db ldr r3, [r3, #12] + 8002090: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8000abe: 68ba ldr r2, [r7, #8] - 8000ac0: f64f 03ff movw r3, #63743 ; 0xf8ff - 8000ac4: 4013 ands r3, r2 - 8000ac6: 60bb str r3, [r7, #8] + 8002092: 68ba ldr r2, [r7, #8] + 8002094: f64f 03ff movw r3, #63743 ; 0xf8ff + 8002098: 4013 ands r3, r2 + 800209a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8000ac8: 68fb ldr r3, [r7, #12] - 8000aca: 021a lsls r2, r3, #8 + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 800209c: 68fb ldr r3, [r7, #12] + 800209e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8000acc: 68bb ldr r3, [r7, #8] - 8000ace: 4313 orrs r3, r2 + 80020a0: 68bb ldr r3, [r7, #8] + 80020a2: 4313 orrs r3, r2 reg_value = (reg_value | - 8000ad0: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 - 8000ad4: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8000ad8: 60bb str r3, [r7, #8] + 80020a4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 80020a8: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 80020ac: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8000ada: 4a04 ldr r2, [pc, #16] ; (8000aec <__NVIC_SetPriorityGrouping+0x44>) - 8000adc: 68bb ldr r3, [r7, #8] - 8000ade: 60d3 str r3, [r2, #12] + 80020ae: 4a04 ldr r2, [pc, #16] ; (80020c0 <__NVIC_SetPriorityGrouping+0x44>) + 80020b0: 68bb ldr r3, [r7, #8] + 80020b2: 60d3 str r3, [r2, #12] } - 8000ae0: bf00 nop - 8000ae2: 3714 adds r7, #20 - 8000ae4: 46bd mov sp, r7 - 8000ae6: bc80 pop {r7} - 8000ae8: 4770 bx lr - 8000aea: bf00 nop - 8000aec: e000ed00 .word 0xe000ed00 + 80020b4: bf00 nop + 80020b6: 3714 adds r7, #20 + 80020b8: 46bd mov sp, r7 + 80020ba: f85d 7b04 ldr.w r7, [sp], #4 + 80020be: 4770 bx lr + 80020c0: e000ed00 .word 0xe000ed00 -08000af0 <__NVIC_GetPriorityGrouping>: +080020c4 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8000af0: b480 push {r7} - 8000af2: af00 add r7, sp, #0 + 80020c4: b480 push {r7} + 80020c6: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8000af4: 4b04 ldr r3, [pc, #16] ; (8000b08 <__NVIC_GetPriorityGrouping+0x18>) - 8000af6: 68db ldr r3, [r3, #12] - 8000af8: 0a1b lsrs r3, r3, #8 - 8000afa: f003 0307 and.w r3, r3, #7 + 80020c8: 4b04 ldr r3, [pc, #16] ; (80020dc <__NVIC_GetPriorityGrouping+0x18>) + 80020ca: 68db ldr r3, [r3, #12] + 80020cc: 0a1b lsrs r3, r3, #8 + 80020ce: f003 0307 and.w r3, r3, #7 } - 8000afe: 4618 mov r0, r3 - 8000b00: 46bd mov sp, r7 - 8000b02: bc80 pop {r7} - 8000b04: 4770 bx lr - 8000b06: bf00 nop - 8000b08: e000ed00 .word 0xe000ed00 + 80020d2: 4618 mov r0, r3 + 80020d4: 46bd mov sp, r7 + 80020d6: f85d 7b04 ldr.w r7, [sp], #4 + 80020da: 4770 bx lr + 80020dc: e000ed00 .word 0xe000ed00 -08000b0c <__NVIC_SetPriority>: +080020e0 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 80020e0: b480 push {r7} + 80020e2: b083 sub sp, #12 + 80020e4: af00 add r7, sp, #0 + 80020e6: 4603 mov r3, r0 + 80020e8: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80020ea: f997 3007 ldrsb.w r3, [r7, #7] + 80020ee: 2b00 cmp r3, #0 + 80020f0: db0b blt.n 800210a <__NVIC_EnableIRQ+0x2a> + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80020f2: 79fb ldrb r3, [r7, #7] + 80020f4: f003 021f and.w r2, r3, #31 + 80020f8: 4907 ldr r1, [pc, #28] ; (8002118 <__NVIC_EnableIRQ+0x38>) + 80020fa: f997 3007 ldrsb.w r3, [r7, #7] + 80020fe: 095b lsrs r3, r3, #5 + 8002100: 2001 movs r0, #1 + 8002102: fa00 f202 lsl.w r2, r0, r2 + 8002106: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 800210a: bf00 nop + 800210c: 370c adds r7, #12 + 800210e: 46bd mov sp, r7 + 8002110: f85d 7b04 ldr.w r7, [sp], #4 + 8002114: 4770 bx lr + 8002116: bf00 nop + 8002118: e000e100 .word 0xe000e100 + +0800211c <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8000b0c: b480 push {r7} - 8000b0e: b083 sub sp, #12 - 8000b10: af00 add r7, sp, #0 - 8000b12: 4603 mov r3, r0 - 8000b14: 6039 str r1, [r7, #0] - 8000b16: 71fb strb r3, [r7, #7] + 800211c: b480 push {r7} + 800211e: b083 sub sp, #12 + 8002120: af00 add r7, sp, #0 + 8002122: 4603 mov r3, r0 + 8002124: 6039 str r1, [r7, #0] + 8002126: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8000b18: f997 3007 ldrsb.w r3, [r7, #7] - 8000b1c: 2b00 cmp r3, #0 - 8000b1e: db0a blt.n 8000b36 <__NVIC_SetPriority+0x2a> + 8002128: f997 3007 ldrsb.w r3, [r7, #7] + 800212c: 2b00 cmp r3, #0 + 800212e: db0a blt.n 8002146 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8000b20: 683b ldr r3, [r7, #0] - 8000b22: b2da uxtb r2, r3 - 8000b24: 490c ldr r1, [pc, #48] ; (8000b58 <__NVIC_SetPriority+0x4c>) - 8000b26: f997 3007 ldrsb.w r3, [r7, #7] - 8000b2a: 0112 lsls r2, r2, #4 - 8000b2c: b2d2 uxtb r2, r2 - 8000b2e: 440b add r3, r1 - 8000b30: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 8002130: 683b ldr r3, [r7, #0] + 8002132: b2da uxtb r2, r3 + 8002134: 490c ldr r1, [pc, #48] ; (8002168 <__NVIC_SetPriority+0x4c>) + 8002136: f997 3007 ldrsb.w r3, [r7, #7] + 800213a: 0112 lsls r2, r2, #4 + 800213c: b2d2 uxtb r2, r2 + 800213e: 440b add r3, r1 + 8002140: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8000b34: e00a b.n 8000b4c <__NVIC_SetPriority+0x40> + 8002144: e00a b.n 800215c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8000b36: 683b ldr r3, [r7, #0] - 8000b38: b2da uxtb r2, r3 - 8000b3a: 4908 ldr r1, [pc, #32] ; (8000b5c <__NVIC_SetPriority+0x50>) - 8000b3c: 79fb ldrb r3, [r7, #7] - 8000b3e: f003 030f and.w r3, r3, #15 - 8000b42: 3b04 subs r3, #4 - 8000b44: 0112 lsls r2, r2, #4 - 8000b46: b2d2 uxtb r2, r2 - 8000b48: 440b add r3, r1 - 8000b4a: 761a strb r2, [r3, #24] + 8002146: 683b ldr r3, [r7, #0] + 8002148: b2da uxtb r2, r3 + 800214a: 4908 ldr r1, [pc, #32] ; (800216c <__NVIC_SetPriority+0x50>) + 800214c: 79fb ldrb r3, [r7, #7] + 800214e: f003 030f and.w r3, r3, #15 + 8002152: 3b04 subs r3, #4 + 8002154: 0112 lsls r2, r2, #4 + 8002156: b2d2 uxtb r2, r2 + 8002158: 440b add r3, r1 + 800215a: 761a strb r2, [r3, #24] } - 8000b4c: bf00 nop - 8000b4e: 370c adds r7, #12 - 8000b50: 46bd mov sp, r7 - 8000b52: bc80 pop {r7} - 8000b54: 4770 bx lr - 8000b56: bf00 nop - 8000b58: e000e100 .word 0xe000e100 - 8000b5c: e000ed00 .word 0xe000ed00 + 800215c: bf00 nop + 800215e: 370c adds r7, #12 + 8002160: 46bd mov sp, r7 + 8002162: f85d 7b04 ldr.w r7, [sp], #4 + 8002166: 4770 bx lr + 8002168: e000e100 .word 0xe000e100 + 800216c: e000ed00 .word 0xe000ed00 -08000b60 : +08002170 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8000b60: b480 push {r7} - 8000b62: b089 sub sp, #36 ; 0x24 - 8000b64: af00 add r7, sp, #0 - 8000b66: 60f8 str r0, [r7, #12] - 8000b68: 60b9 str r1, [r7, #8] - 8000b6a: 607a str r2, [r7, #4] + 8002170: b480 push {r7} + 8002172: b089 sub sp, #36 ; 0x24 + 8002174: af00 add r7, sp, #0 + 8002176: 60f8 str r0, [r7, #12] + 8002178: 60b9 str r1, [r7, #8] + 800217a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8000b6c: 68fb ldr r3, [r7, #12] - 8000b6e: f003 0307 and.w r3, r3, #7 - 8000b72: 61fb str r3, [r7, #28] + 800217c: 68fb ldr r3, [r7, #12] + 800217e: f003 0307 and.w r3, r3, #7 + 8002182: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8000b74: 69fb ldr r3, [r7, #28] - 8000b76: f1c3 0307 rsb r3, r3, #7 - 8000b7a: 2b04 cmp r3, #4 - 8000b7c: bf28 it cs - 8000b7e: 2304 movcs r3, #4 - 8000b80: 61bb str r3, [r7, #24] + 8002184: 69fb ldr r3, [r7, #28] + 8002186: f1c3 0307 rsb r3, r3, #7 + 800218a: 2b04 cmp r3, #4 + 800218c: bf28 it cs + 800218e: 2304 movcs r3, #4 + 8002190: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8000b82: 69fb ldr r3, [r7, #28] - 8000b84: 3304 adds r3, #4 - 8000b86: 2b06 cmp r3, #6 - 8000b88: d902 bls.n 8000b90 - 8000b8a: 69fb ldr r3, [r7, #28] - 8000b8c: 3b03 subs r3, #3 - 8000b8e: e000 b.n 8000b92 - 8000b90: 2300 movs r3, #0 - 8000b92: 617b str r3, [r7, #20] + 8002192: 69fb ldr r3, [r7, #28] + 8002194: 3304 adds r3, #4 + 8002196: 2b06 cmp r3, #6 + 8002198: d902 bls.n 80021a0 + 800219a: 69fb ldr r3, [r7, #28] + 800219c: 3b03 subs r3, #3 + 800219e: e000 b.n 80021a2 + 80021a0: 2300 movs r3, #0 + 80021a2: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8000b94: f04f 32ff mov.w r2, #4294967295 - 8000b98: 69bb ldr r3, [r7, #24] - 8000b9a: fa02 f303 lsl.w r3, r2, r3 - 8000b9e: 43da mvns r2, r3 - 8000ba0: 68bb ldr r3, [r7, #8] - 8000ba2: 401a ands r2, r3 - 8000ba4: 697b ldr r3, [r7, #20] - 8000ba6: 409a lsls r2, r3 + 80021a4: f04f 32ff mov.w r2, #4294967295 + 80021a8: 69bb ldr r3, [r7, #24] + 80021aa: fa02 f303 lsl.w r3, r2, r3 + 80021ae: 43da mvns r2, r3 + 80021b0: 68bb ldr r3, [r7, #8] + 80021b2: 401a ands r2, r3 + 80021b4: 697b ldr r3, [r7, #20] + 80021b6: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8000ba8: f04f 31ff mov.w r1, #4294967295 - 8000bac: 697b ldr r3, [r7, #20] - 8000bae: fa01 f303 lsl.w r3, r1, r3 - 8000bb2: 43d9 mvns r1, r3 - 8000bb4: 687b ldr r3, [r7, #4] - 8000bb6: 400b ands r3, r1 + 80021b8: f04f 31ff mov.w r1, #4294967295 + 80021bc: 697b ldr r3, [r7, #20] + 80021be: fa01 f303 lsl.w r3, r1, r3 + 80021c2: 43d9 mvns r1, r3 + 80021c4: 687b ldr r3, [r7, #4] + 80021c6: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8000bb8: 4313 orrs r3, r2 + 80021c8: 4313 orrs r3, r2 ); } - 8000bba: 4618 mov r0, r3 - 8000bbc: 3724 adds r7, #36 ; 0x24 - 8000bbe: 46bd mov sp, r7 - 8000bc0: bc80 pop {r7} - 8000bc2: 4770 bx lr + 80021ca: 4618 mov r0, r3 + 80021cc: 3724 adds r7, #36 ; 0x24 + 80021ce: 46bd mov sp, r7 + 80021d0: f85d 7b04 ldr.w r7, [sp], #4 + 80021d4: 4770 bx lr + ... -08000bc4 : +080021d8 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - 8000bc4: b580 push {r7, lr} - 8000bc6: b082 sub sp, #8 - 8000bc8: af00 add r7, sp, #0 - 8000bca: 6078 str r0, [r7, #4] + 80021d8: b580 push {r7, lr} + 80021da: b082 sub sp, #8 + 80021dc: af00 add r7, sp, #0 + 80021de: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - 8000bcc: 687b ldr r3, [r7, #4] - 8000bce: 3b01 subs r3, #1 - 8000bd0: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 - 8000bd4: d301 bcc.n 8000bda + 80021e0: 687b ldr r3, [r7, #4] + 80021e2: 3b01 subs r3, #1 + 80021e4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 80021e8: d301 bcc.n 80021ee { return (1UL); /* Reload value impossible */ - 8000bd6: 2301 movs r3, #1 - 8000bd8: e00f b.n 8000bfa + 80021ea: 2301 movs r3, #1 + 80021ec: e00f b.n 800220e } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - 8000bda: 4a0a ldr r2, [pc, #40] ; (8000c04 ) - 8000bdc: 687b ldr r3, [r7, #4] - 8000bde: 3b01 subs r3, #1 - 8000be0: 6053 str r3, [r2, #4] + 80021ee: 4a0a ldr r2, [pc, #40] ; (8002218 ) + 80021f0: 687b ldr r3, [r7, #4] + 80021f2: 3b01 subs r3, #1 + 80021f4: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - 8000be2: 210f movs r1, #15 - 8000be4: f04f 30ff mov.w r0, #4294967295 - 8000be8: f7ff ff90 bl 8000b0c <__NVIC_SetPriority> + 80021f6: 210f movs r1, #15 + 80021f8: f04f 30ff mov.w r0, #4294967295 + 80021fc: f7ff ff8e bl 800211c <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - 8000bec: 4b05 ldr r3, [pc, #20] ; (8000c04 ) - 8000bee: 2200 movs r2, #0 - 8000bf0: 609a str r2, [r3, #8] + 8002200: 4b05 ldr r3, [pc, #20] ; (8002218 ) + 8002202: 2200 movs r2, #0 + 8002204: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - 8000bf2: 4b04 ldr r3, [pc, #16] ; (8000c04 ) - 8000bf4: 2207 movs r2, #7 - 8000bf6: 601a str r2, [r3, #0] + 8002206: 4b04 ldr r3, [pc, #16] ; (8002218 ) + 8002208: 2207 movs r2, #7 + 800220a: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ - 8000bf8: 2300 movs r3, #0 + 800220c: 2300 movs r3, #0 } - 8000bfa: 4618 mov r0, r3 - 8000bfc: 3708 adds r7, #8 - 8000bfe: 46bd mov sp, r7 - 8000c00: bd80 pop {r7, pc} - 8000c02: bf00 nop - 8000c04: e000e010 .word 0xe000e010 + 800220e: 4618 mov r0, r3 + 8002210: 3708 adds r7, #8 + 8002212: 46bd mov sp, r7 + 8002214: bd80 pop {r7, pc} + 8002216: bf00 nop + 8002218: e000e010 .word 0xe000e010 -08000c08 : - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. +0800221c : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8000c08: b580 push {r7, lr} - 8000c0a: b082 sub sp, #8 - 8000c0c: af00 add r7, sp, #0 - 8000c0e: 6078 str r0, [r7, #4] + 800221c: b580 push {r7, lr} + 800221e: b082 sub sp, #8 + 8002220: af00 add r7, sp, #0 + 8002222: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8000c10: 6878 ldr r0, [r7, #4] - 8000c12: f7ff ff49 bl 8000aa8 <__NVIC_SetPriorityGrouping> + 8002224: 6878 ldr r0, [r7, #4] + 8002226: f7ff ff29 bl 800207c <__NVIC_SetPriorityGrouping> } - 8000c16: bf00 nop - 8000c18: 3708 adds r7, #8 - 8000c1a: 46bd mov sp, r7 - 8000c1c: bd80 pop {r7, pc} + 800222a: bf00 nop + 800222c: 3708 adds r7, #8 + 800222e: 46bd mov sp, r7 + 8002230: bd80 pop {r7, pc} -08000c1e : +08002232 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - 8000c1e: b580 push {r7, lr} - 8000c20: b086 sub sp, #24 - 8000c22: af00 add r7, sp, #0 - 8000c24: 4603 mov r3, r0 - 8000c26: 60b9 str r1, [r7, #8] - 8000c28: 607a str r2, [r7, #4] - 8000c2a: 73fb strb r3, [r7, #15] - uint32_t prioritygroup = 0x00; - 8000c2c: 2300 movs r3, #0 - 8000c2e: 617b str r3, [r7, #20] +{ + 8002232: b580 push {r7, lr} + 8002234: b086 sub sp, #24 + 8002236: af00 add r7, sp, #0 + 8002238: 4603 mov r3, r0 + 800223a: 60b9 str r1, [r7, #8] + 800223c: 607a str r2, [r7, #4] + 800223e: 73fb strb r3, [r7, #15] + uint32_t prioritygroup = 0x00U; + 8002240: 2300 movs r3, #0 + 8002242: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8000c30: f7ff ff5e bl 8000af0 <__NVIC_GetPriorityGrouping> - 8000c34: 6178 str r0, [r7, #20] + 8002244: f7ff ff3e bl 80020c4 <__NVIC_GetPriorityGrouping> + 8002248: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8000c36: 687a ldr r2, [r7, #4] - 8000c38: 68b9 ldr r1, [r7, #8] - 8000c3a: 6978 ldr r0, [r7, #20] - 8000c3c: f7ff ff90 bl 8000b60 - 8000c40: 4602 mov r2, r0 - 8000c42: f997 300f ldrsb.w r3, [r7, #15] - 8000c46: 4611 mov r1, r2 - 8000c48: 4618 mov r0, r3 - 8000c4a: f7ff ff5f bl 8000b0c <__NVIC_SetPriority> + 800224a: 687a ldr r2, [r7, #4] + 800224c: 68b9 ldr r1, [r7, #8] + 800224e: 6978 ldr r0, [r7, #20] + 8002250: f7ff ff8e bl 8002170 + 8002254: 4602 mov r2, r0 + 8002256: f997 300f ldrsb.w r3, [r7, #15] + 800225a: 4611 mov r1, r2 + 800225c: 4618 mov r0, r3 + 800225e: f7ff ff5d bl 800211c <__NVIC_SetPriority> } - 8000c4e: bf00 nop - 8000c50: 3718 adds r7, #24 - 8000c52: 46bd mov sp, r7 - 8000c54: bd80 pop {r7, pc} + 8002262: bf00 nop + 8002264: 3718 adds r7, #24 + 8002266: 46bd mov sp, r7 + 8002268: bd80 pop {r7, pc} -08000c56 : +0800226a : + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 800226a: b580 push {r7, lr} + 800226c: b082 sub sp, #8 + 800226e: af00 add r7, sp, #0 + 8002270: 4603 mov r3, r0 + 8002272: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8002274: f997 3007 ldrsb.w r3, [r7, #7] + 8002278: 4618 mov r0, r3 + 800227a: f7ff ff31 bl 80020e0 <__NVIC_EnableIRQ> +} + 800227e: bf00 nop + 8002280: 3708 adds r7, #8 + 8002282: 46bd mov sp, r7 + 8002284: bd80 pop {r7, pc} + +08002286 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { - 8000c56: b580 push {r7, lr} - 8000c58: b082 sub sp, #8 - 8000c5a: af00 add r7, sp, #0 - 8000c5c: 6078 str r0, [r7, #4] + 8002286: b580 push {r7, lr} + 8002288: b082 sub sp, #8 + 800228a: af00 add r7, sp, #0 + 800228c: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); - 8000c5e: 6878 ldr r0, [r7, #4] - 8000c60: f7ff ffb0 bl 8000bc4 - 8000c64: 4603 mov r3, r0 + 800228e: 6878 ldr r0, [r7, #4] + 8002290: f7ff ffa2 bl 80021d8 + 8002294: 4603 mov r3, r0 } - 8000c66: 4618 mov r0, r3 - 8000c68: 3708 adds r7, #8 - 8000c6a: 46bd mov sp, r7 - 8000c6c: bd80 pop {r7, pc} + 8002296: 4618 mov r0, r3 + 8002298: 3708 adds r7, #8 + 800229a: 46bd mov sp, r7 + 800229c: bd80 pop {r7, pc} ... -08000c70 : +080022a0 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 8000c70: b480 push {r7} - 8000c72: b087 sub sp, #28 - 8000c74: af00 add r7, sp, #0 - 8000c76: 6078 str r0, [r7, #4] - 8000c78: 6039 str r1, [r7, #0] - uint32_t position = 0x00; - 8000c7a: 2300 movs r3, #0 - 8000c7c: 617b str r3, [r7, #20] - uint32_t iocurrent = 0x00; - 8000c7e: 2300 movs r3, #0 - 8000c80: 60fb str r3, [r7, #12] - uint32_t temp = 0x00; - 8000c82: 2300 movs r3, #0 - 8000c84: 613b str r3, [r7, #16] + 80022a0: b480 push {r7} + 80022a2: b089 sub sp, #36 ; 0x24 + 80022a4: af00 add r7, sp, #0 + 80022a6: 6078 str r0, [r7, #4] + 80022a8: 6039 str r1, [r7, #0] + uint32_t position; + uint32_t ioposition = 0x00U; + 80022aa: 2300 movs r3, #0 + 80022ac: 617b str r3, [r7, #20] + uint32_t iocurrent = 0x00U; + 80022ae: 2300 movs r3, #0 + 80022b0: 613b str r3, [r7, #16] + uint32_t temp = 0x00U; + 80022b2: 2300 movs r3, #0 + 80022b4: 61bb str r3, [r7, #24] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != 0) - 8000c86: e160 b.n 8000f4a + for(position = 0U; position < GPIO_NUMBER; position++) + 80022b6: 2300 movs r3, #0 + 80022b8: 61fb str r3, [r7, #28] + 80022ba: e159 b.n 8002570 { - /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); - 8000c88: 683b ldr r3, [r7, #0] - 8000c8a: 681a ldr r2, [r3, #0] - 8000c8c: 2101 movs r1, #1 - 8000c8e: 697b ldr r3, [r7, #20] - 8000c90: fa01 f303 lsl.w r3, r1, r3 - 8000c94: 4013 ands r3, r2 - 8000c96: 60fb str r3, [r7, #12] + /* Get the IO position */ + ioposition = 0x01U << position; + 80022bc: 2201 movs r2, #1 + 80022be: 69fb ldr r3, [r7, #28] + 80022c0: fa02 f303 lsl.w r3, r2, r3 + 80022c4: 617b str r3, [r7, #20] + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + 80022c6: 683b ldr r3, [r7, #0] + 80022c8: 681b ldr r3, [r3, #0] + 80022ca: 697a ldr r2, [r7, #20] + 80022cc: 4013 ands r3, r2 + 80022ce: 613b str r3, [r7, #16] - if (iocurrent) - 8000c98: 68fb ldr r3, [r7, #12] - 8000c9a: 2b00 cmp r3, #0 - 8000c9c: f000 8152 beq.w 8000f44 + if(iocurrent == ioposition) + 80022d0: 693a ldr r2, [r7, #16] + 80022d2: 697b ldr r3, [r7, #20] + 80022d4: 429a cmp r2, r3 + 80022d6: f040 8148 bne.w 800256a { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8000ca0: 683b ldr r3, [r7, #0] - 8000ca2: 685b ldr r3, [r3, #4] - 8000ca4: 2b01 cmp r3, #1 - 8000ca6: d00b beq.n 8000cc0 - 8000ca8: 683b ldr r3, [r7, #0] - 8000caa: 685b ldr r3, [r3, #4] - 8000cac: 2b02 cmp r3, #2 - 8000cae: d007 beq.n 8000cc0 - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8000cb0: 683b ldr r3, [r7, #0] - 8000cb2: 685b ldr r3, [r3, #4] - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - 8000cb4: 2b11 cmp r3, #17 - 8000cb6: d003 beq.n 8000cc0 - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8000cb8: 683b ldr r3, [r7, #0] - 8000cba: 685b ldr r3, [r3, #4] - 8000cbc: 2b12 cmp r3, #18 - 8000cbe: d130 bne.n 8000d22 + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 80022da: 683b ldr r3, [r7, #0] + 80022dc: 685b ldr r3, [r3, #4] + 80022de: 2b01 cmp r3, #1 + 80022e0: d00b beq.n 80022fa + 80022e2: 683b ldr r3, [r7, #0] + 80022e4: 685b ldr r3, [r3, #4] + 80022e6: 2b02 cmp r3, #2 + 80022e8: d007 beq.n 80022fa + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80022ea: 683b ldr r3, [r7, #0] + 80022ec: 685b ldr r3, [r3, #4] + if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || + 80022ee: 2b11 cmp r3, #17 + 80022f0: d003 beq.n 80022fa + (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 80022f2: 683b ldr r3, [r7, #0] + 80022f4: 685b ldr r3, [r3, #4] + 80022f6: 2b12 cmp r3, #18 + 80022f8: d130 bne.n 800235c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - 8000cc0: 687b ldr r3, [r7, #4] - 8000cc2: 689b ldr r3, [r3, #8] - 8000cc4: 613b str r3, [r7, #16] - CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - 8000cc6: 697b ldr r3, [r7, #20] - 8000cc8: 005b lsls r3, r3, #1 - 8000cca: 2203 movs r2, #3 - 8000ccc: fa02 f303 lsl.w r3, r2, r3 - 8000cd0: 43db mvns r3, r3 - 8000cd2: 693a ldr r2, [r7, #16] - 8000cd4: 4013 ands r3, r2 - 8000cd6: 613b str r3, [r7, #16] - SET_BIT(temp, GPIO_Init->Speed << (position * 2)); - 8000cd8: 683b ldr r3, [r7, #0] - 8000cda: 68da ldr r2, [r3, #12] - 8000cdc: 697b ldr r3, [r7, #20] - 8000cde: 005b lsls r3, r3, #1 - 8000ce0: fa02 f303 lsl.w r3, r2, r3 - 8000ce4: 693a ldr r2, [r7, #16] - 8000ce6: 4313 orrs r3, r2 - 8000ce8: 613b str r3, [r7, #16] + temp = GPIOx->OSPEEDR; + 80022fa: 687b ldr r3, [r7, #4] + 80022fc: 689b ldr r3, [r3, #8] + 80022fe: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); + 8002300: 69fb ldr r3, [r7, #28] + 8002302: 005b lsls r3, r3, #1 + 8002304: 2203 movs r2, #3 + 8002306: fa02 f303 lsl.w r3, r2, r3 + 800230a: 43db mvns r3, r3 + 800230c: 69ba ldr r2, [r7, #24] + 800230e: 4013 ands r3, r2 + 8002310: 61bb str r3, [r7, #24] + temp |= (GPIO_Init->Speed << (position * 2U)); + 8002312: 683b ldr r3, [r7, #0] + 8002314: 68da ldr r2, [r3, #12] + 8002316: 69fb ldr r3, [r7, #28] + 8002318: 005b lsls r3, r3, #1 + 800231a: fa02 f303 lsl.w r3, r2, r3 + 800231e: 69ba ldr r2, [r7, #24] + 8002320: 4313 orrs r3, r2 + 8002322: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; - 8000cea: 687b ldr r3, [r7, #4] - 8000cec: 693a ldr r2, [r7, #16] - 8000cee: 609a str r2, [r3, #8] + 8002324: 687b ldr r3, [r7, #4] + 8002326: 69ba ldr r2, [r7, #24] + 8002328: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8000cf0: 687b ldr r3, [r7, #4] - 8000cf2: 685b ldr r3, [r3, #4] - 8000cf4: 613b str r3, [r7, #16] - CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - 8000cf6: 2201 movs r2, #1 - 8000cf8: 697b ldr r3, [r7, #20] - 8000cfa: fa02 f303 lsl.w r3, r2, r3 - 8000cfe: 43db mvns r3, r3 - 8000d00: 693a ldr r2, [r7, #16] - 8000d02: 4013 ands r3, r2 - 8000d04: 613b str r3, [r7, #16] - SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - 8000d06: 683b ldr r3, [r7, #0] - 8000d08: 685b ldr r3, [r3, #4] - 8000d0a: 091b lsrs r3, r3, #4 - 8000d0c: f003 0201 and.w r2, r3, #1 - 8000d10: 697b ldr r3, [r7, #20] - 8000d12: fa02 f303 lsl.w r3, r2, r3 - 8000d16: 693a ldr r2, [r7, #16] - 8000d18: 4313 orrs r3, r2 - 8000d1a: 613b str r3, [r7, #16] + 800232a: 687b ldr r3, [r7, #4] + 800232c: 685b ldr r3, [r3, #4] + 800232e: 61bb str r3, [r7, #24] + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + 8002330: 2201 movs r2, #1 + 8002332: 69fb ldr r3, [r7, #28] + 8002334: fa02 f303 lsl.w r3, r2, r3 + 8002338: 43db mvns r3, r3 + 800233a: 69ba ldr r2, [r7, #24] + 800233c: 4013 ands r3, r2 + 800233e: 61bb str r3, [r7, #24] + temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + 8002340: 683b ldr r3, [r7, #0] + 8002342: 685b ldr r3, [r3, #4] + 8002344: 091b lsrs r3, r3, #4 + 8002346: f003 0201 and.w r2, r3, #1 + 800234a: 69fb ldr r3, [r7, #28] + 800234c: fa02 f303 lsl.w r3, r2, r3 + 8002350: 69ba ldr r2, [r7, #24] + 8002352: 4313 orrs r3, r2 + 8002354: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; - 8000d1c: 687b ldr r3, [r7, #4] - 8000d1e: 693a ldr r2, [r7, #16] - 8000d20: 605a str r2, [r3, #4] - } + 8002356: 687b ldr r3, [r7, #4] + 8002358: 69ba ldr r2, [r7, #24] + 800235a: 605a str r2, [r3, #4] + } /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 8000d22: 687b ldr r3, [r7, #4] - 8000d24: 68db ldr r3, [r3, #12] - 8000d26: 613b str r3, [r7, #16] - CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); - 8000d28: 697b ldr r3, [r7, #20] - 8000d2a: 005b lsls r3, r3, #1 - 8000d2c: 2203 movs r2, #3 - 8000d2e: fa02 f303 lsl.w r3, r2, r3 - 8000d32: 43db mvns r3, r3 - 8000d34: 693a ldr r2, [r7, #16] - 8000d36: 4013 ands r3, r2 - 8000d38: 613b str r3, [r7, #16] - SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); - 8000d3a: 683b ldr r3, [r7, #0] - 8000d3c: 689a ldr r2, [r3, #8] - 8000d3e: 697b ldr r3, [r7, #20] - 8000d40: 005b lsls r3, r3, #1 - 8000d42: fa02 f303 lsl.w r3, r2, r3 - 8000d46: 693a ldr r2, [r7, #16] - 8000d48: 4313 orrs r3, r2 - 8000d4a: 613b str r3, [r7, #16] + 800235c: 687b ldr r3, [r7, #4] + 800235e: 68db ldr r3, [r3, #12] + 8002360: 61bb str r3, [r7, #24] + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); + 8002362: 69fb ldr r3, [r7, #28] + 8002364: 005b lsls r3, r3, #1 + 8002366: 2203 movs r2, #3 + 8002368: fa02 f303 lsl.w r3, r2, r3 + 800236c: 43db mvns r3, r3 + 800236e: 69ba ldr r2, [r7, #24] + 8002370: 4013 ands r3, r2 + 8002372: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 8002374: 683b ldr r3, [r7, #0] + 8002376: 689a ldr r2, [r3, #8] + 8002378: 69fb ldr r3, [r7, #28] + 800237a: 005b lsls r3, r3, #1 + 800237c: fa02 f303 lsl.w r3, r2, r3 + 8002380: 69ba ldr r2, [r7, #24] + 8002382: 4313 orrs r3, r2 + 8002384: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; - 8000d4c: 687b ldr r3, [r7, #4] - 8000d4e: 693a ldr r2, [r7, #16] - 8000d50: 60da str r2, [r3, #12] + 8002386: 687b ldr r3, [r7, #4] + 8002388: 69ba ldr r2, [r7, #24] + 800238a: 60da str r2, [r3, #12] /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - 8000d52: 683b ldr r3, [r7, #0] - 8000d54: 685b ldr r3, [r3, #4] - 8000d56: 2b02 cmp r3, #2 - 8000d58: d003 beq.n 8000d62 - 8000d5a: 683b ldr r3, [r7, #0] - 8000d5c: 685b ldr r3, [r3, #4] - 8000d5e: 2b12 cmp r3, #18 - 8000d60: d123 bne.n 8000daa - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) + 800238c: 683b ldr r3, [r7, #0] + 800238e: 685b ldr r3, [r3, #4] + 8002390: 2b02 cmp r3, #2 + 8002392: d003 beq.n 800239c + 8002394: 683b ldr r3, [r7, #0] + 8002396: 685b ldr r3, [r3, #4] + 8002398: 2b12 cmp r3, #18 + 800239a: d123 bne.n 80023e4 + { + /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - /* Configure Alternate function mapped with the current IO */ - /* Identify AFRL or AFRH register based on IO position*/ - temp = GPIOx->AFR[position >> 3]; - 8000d62: 697b ldr r3, [r7, #20] - 8000d64: 08da lsrs r2, r3, #3 - 8000d66: 687b ldr r3, [r7, #4] - 8000d68: 3208 adds r2, #8 - 8000d6a: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8000d6e: 613b str r3, [r7, #16] - CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); - 8000d70: 697b ldr r3, [r7, #20] - 8000d72: f003 0307 and.w r3, r3, #7 - 8000d76: 009b lsls r3, r3, #2 - 8000d78: 220f movs r2, #15 - 8000d7a: fa02 f303 lsl.w r3, r2, r3 - 8000d7e: 43db mvns r3, r3 - 8000d80: 693a ldr r2, [r7, #16] - 8000d82: 4013 ands r3, r2 - 8000d84: 613b str r3, [r7, #16] - SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); - 8000d86: 683b ldr r3, [r7, #0] - 8000d88: 691a ldr r2, [r3, #16] - 8000d8a: 697b ldr r3, [r7, #20] - 8000d8c: f003 0307 and.w r3, r3, #7 - 8000d90: 009b lsls r3, r3, #2 - 8000d92: fa02 f303 lsl.w r3, r2, r3 - 8000d96: 693a ldr r2, [r7, #16] - 8000d98: 4313 orrs r3, r2 - 8000d9a: 613b str r3, [r7, #16] - GPIOx->AFR[position >> 3] = temp; - 8000d9c: 697b ldr r3, [r7, #20] - 8000d9e: 08da lsrs r2, r3, #3 - 8000da0: 687b ldr r3, [r7, #4] - 8000da2: 3208 adds r2, #8 - 8000da4: 6939 ldr r1, [r7, #16] - 8000da6: f843 1022 str.w r1, [r3, r2, lsl #2] + temp = GPIOx->AFR[position >> 3U]; + 800239c: 69fb ldr r3, [r7, #28] + 800239e: 08da lsrs r2, r3, #3 + 80023a0: 687b ldr r3, [r7, #4] + 80023a2: 3208 adds r2, #8 + 80023a4: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80023a8: 61bb str r3, [r7, #24] + temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; + 80023aa: 69fb ldr r3, [r7, #28] + 80023ac: f003 0307 and.w r3, r3, #7 + 80023b0: 009b lsls r3, r3, #2 + 80023b2: 220f movs r2, #15 + 80023b4: fa02 f303 lsl.w r3, r2, r3 + 80023b8: 43db mvns r3, r3 + 80023ba: 69ba ldr r2, [r7, #24] + 80023bc: 4013 ands r3, r2 + 80023be: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); + 80023c0: 683b ldr r3, [r7, #0] + 80023c2: 691a ldr r2, [r3, #16] + 80023c4: 69fb ldr r3, [r7, #28] + 80023c6: f003 0307 and.w r3, r3, #7 + 80023ca: 009b lsls r3, r3, #2 + 80023cc: fa02 f303 lsl.w r3, r2, r3 + 80023d0: 69ba ldr r2, [r7, #24] + 80023d2: 4313 orrs r3, r2 + 80023d4: 61bb str r3, [r7, #24] + GPIOx->AFR[position >> 3U] = temp; + 80023d6: 69fb ldr r3, [r7, #28] + 80023d8: 08da lsrs r2, r3, #3 + 80023da: 687b ldr r3, [r7, #4] + 80023dc: 3208 adds r2, #8 + 80023de: 69b9 ldr r1, [r7, #24] + 80023e0: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8000daa: 687b ldr r3, [r7, #4] - 8000dac: 681b ldr r3, [r3, #0] - 8000dae: 613b str r3, [r7, #16] - CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); - 8000db0: 697b ldr r3, [r7, #20] - 8000db2: 005b lsls r3, r3, #1 - 8000db4: 2203 movs r2, #3 - 8000db6: fa02 f303 lsl.w r3, r2, r3 - 8000dba: 43db mvns r3, r3 - 8000dbc: 693a ldr r2, [r7, #16] - 8000dbe: 4013 ands r3, r2 - 8000dc0: 613b str r3, [r7, #16] - SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - 8000dc2: 683b ldr r3, [r7, #0] - 8000dc4: 685b ldr r3, [r3, #4] - 8000dc6: f003 0203 and.w r2, r3, #3 - 8000dca: 697b ldr r3, [r7, #20] - 8000dcc: 005b lsls r3, r3, #1 - 8000dce: fa02 f303 lsl.w r3, r2, r3 - 8000dd2: 693a ldr r2, [r7, #16] - 8000dd4: 4313 orrs r3, r2 - 8000dd6: 613b str r3, [r7, #16] + 80023e4: 687b ldr r3, [r7, #4] + 80023e6: 681b ldr r3, [r3, #0] + 80023e8: 61bb str r3, [r7, #24] + temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); + 80023ea: 69fb ldr r3, [r7, #28] + 80023ec: 005b lsls r3, r3, #1 + 80023ee: 2203 movs r2, #3 + 80023f0: fa02 f303 lsl.w r3, r2, r3 + 80023f4: 43db mvns r3, r3 + 80023f6: 69ba ldr r2, [r7, #24] + 80023f8: 4013 ands r3, r2 + 80023fa: 61bb str r3, [r7, #24] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 80023fc: 683b ldr r3, [r7, #0] + 80023fe: 685b ldr r3, [r3, #4] + 8002400: f003 0203 and.w r2, r3, #3 + 8002404: 69fb ldr r3, [r7, #28] + 8002406: 005b lsls r3, r3, #1 + 8002408: fa02 f303 lsl.w r3, r2, r3 + 800240c: 69ba ldr r2, [r7, #24] + 800240e: 4313 orrs r3, r2 + 8002410: 61bb str r3, [r7, #24] GPIOx->MODER = temp; - 8000dd8: 687b ldr r3, [r7, #4] - 8000dda: 693a ldr r2, [r7, #16] - 8000ddc: 601a str r2, [r3, #0] + 8002412: 687b ldr r3, [r7, #4] + 8002414: 69ba ldr r2, [r7, #24] + 8002416: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - 8000dde: 683b ldr r3, [r7, #0] - 8000de0: 685b ldr r3, [r3, #4] - 8000de2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8000de6: 2b00 cmp r3, #0 - 8000de8: f000 80ac beq.w 8000f44 + if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + 8002418: 683b ldr r3, [r7, #0] + 800241a: 685b ldr r3, [r3, #4] + 800241c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002420: 2b00 cmp r3, #0 + 8002422: f000 80a2 beq.w 800256a { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000dec: 4b5d ldr r3, [pc, #372] ; (8000f64 ) - 8000dee: 6a1b ldr r3, [r3, #32] - 8000df0: 4a5c ldr r2, [pc, #368] ; (8000f64 ) - 8000df2: f043 0301 orr.w r3, r3, #1 - 8000df6: 6213 str r3, [r2, #32] - 8000df8: 4b5a ldr r3, [pc, #360] ; (8000f64 ) - 8000dfa: 6a1b ldr r3, [r3, #32] - 8000dfc: f003 0301 and.w r3, r3, #1 - 8000e00: 60bb str r3, [r7, #8] - 8000e02: 68bb ldr r3, [r7, #8] + 8002426: 2300 movs r3, #0 + 8002428: 60fb str r3, [r7, #12] + 800242a: 4b56 ldr r3, [pc, #344] ; (8002584 ) + 800242c: 6c5b ldr r3, [r3, #68] ; 0x44 + 800242e: 4a55 ldr r2, [pc, #340] ; (8002584 ) + 8002430: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8002434: 6453 str r3, [r2, #68] ; 0x44 + 8002436: 4b53 ldr r3, [pc, #332] ; (8002584 ) + 8002438: 6c5b ldr r3, [r3, #68] ; 0x44 + 800243a: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 800243e: 60fb str r3, [r7, #12] + 8002440: 68fb ldr r3, [r7, #12] - temp = SYSCFG->EXTICR[position >> 2]; - 8000e04: 4a58 ldr r2, [pc, #352] ; (8000f68 ) - 8000e06: 697b ldr r3, [r7, #20] - 8000e08: 089b lsrs r3, r3, #2 - 8000e0a: 3302 adds r3, #2 - 8000e0c: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 8000e10: 613b str r3, [r7, #16] - CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); - 8000e12: 697b ldr r3, [r7, #20] - 8000e14: f003 0303 and.w r3, r3, #3 - 8000e18: 009b lsls r3, r3, #2 - 8000e1a: 220f movs r2, #15 - 8000e1c: fa02 f303 lsl.w r3, r2, r3 - 8000e20: 43db mvns r3, r3 - 8000e22: 693a ldr r2, [r7, #16] - 8000e24: 4013 ands r3, r2 - 8000e26: 613b str r3, [r7, #16] - SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - 8000e28: 687b ldr r3, [r7, #4] - 8000e2a: 4a50 ldr r2, [pc, #320] ; (8000f6c ) - 8000e2c: 4293 cmp r3, r2 - 8000e2e: d025 beq.n 8000e7c - 8000e30: 687b ldr r3, [r7, #4] - 8000e32: 4a4f ldr r2, [pc, #316] ; (8000f70 ) - 8000e34: 4293 cmp r3, r2 - 8000e36: d01f beq.n 8000e78 - 8000e38: 687b ldr r3, [r7, #4] - 8000e3a: 4a4e ldr r2, [pc, #312] ; (8000f74 ) - 8000e3c: 4293 cmp r3, r2 - 8000e3e: d019 beq.n 8000e74 - 8000e40: 687b ldr r3, [r7, #4] - 8000e42: 4a4d ldr r2, [pc, #308] ; (8000f78 ) - 8000e44: 4293 cmp r3, r2 - 8000e46: d013 beq.n 8000e70 - 8000e48: 687b ldr r3, [r7, #4] - 8000e4a: 4a4c ldr r2, [pc, #304] ; (8000f7c ) - 8000e4c: 4293 cmp r3, r2 - 8000e4e: d00d beq.n 8000e6c - 8000e50: 687b ldr r3, [r7, #4] - 8000e52: 4a4b ldr r2, [pc, #300] ; (8000f80 ) - 8000e54: 4293 cmp r3, r2 - 8000e56: d007 beq.n 8000e68 - 8000e58: 687b ldr r3, [r7, #4] - 8000e5a: 4a4a ldr r2, [pc, #296] ; (8000f84 ) - 8000e5c: 4293 cmp r3, r2 - 8000e5e: d101 bne.n 8000e64 - 8000e60: 2306 movs r3, #6 - 8000e62: e00c b.n 8000e7e - 8000e64: 2307 movs r3, #7 - 8000e66: e00a b.n 8000e7e - 8000e68: 2305 movs r3, #5 - 8000e6a: e008 b.n 8000e7e - 8000e6c: 2304 movs r3, #4 - 8000e6e: e006 b.n 8000e7e - 8000e70: 2303 movs r3, #3 - 8000e72: e004 b.n 8000e7e - 8000e74: 2302 movs r3, #2 - 8000e76: e002 b.n 8000e7e - 8000e78: 2301 movs r3, #1 - 8000e7a: e000 b.n 8000e7e - 8000e7c: 2300 movs r3, #0 - 8000e7e: 697a ldr r2, [r7, #20] - 8000e80: f002 0203 and.w r2, r2, #3 - 8000e84: 0092 lsls r2, r2, #2 - 8000e86: 4093 lsls r3, r2 - 8000e88: 693a ldr r2, [r7, #16] - 8000e8a: 4313 orrs r3, r2 - 8000e8c: 613b str r3, [r7, #16] - SYSCFG->EXTICR[position >> 2] = temp; - 8000e8e: 4936 ldr r1, [pc, #216] ; (8000f68 ) - 8000e90: 697b ldr r3, [r7, #20] - 8000e92: 089b lsrs r3, r3, #2 - 8000e94: 3302 adds r3, #2 - 8000e96: 693a ldr r2, [r7, #16] - 8000e98: f841 2023 str.w r2, [r1, r3, lsl #2] + temp = SYSCFG->EXTICR[position >> 2U]; + 8002442: 4a51 ldr r2, [pc, #324] ; (8002588 ) + 8002444: 69fb ldr r3, [r7, #28] + 8002446: 089b lsrs r3, r3, #2 + 8002448: 3302 adds r3, #2 + 800244a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800244e: 61bb str r3, [r7, #24] + temp &= ~(0x0FU << (4U * (position & 0x03U))); + 8002450: 69fb ldr r3, [r7, #28] + 8002452: f003 0303 and.w r3, r3, #3 + 8002456: 009b lsls r3, r3, #2 + 8002458: 220f movs r2, #15 + 800245a: fa02 f303 lsl.w r3, r2, r3 + 800245e: 43db mvns r3, r3 + 8002460: 69ba ldr r2, [r7, #24] + 8002462: 4013 ands r3, r2 + 8002464: 61bb str r3, [r7, #24] + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); + 8002466: 687b ldr r3, [r7, #4] + 8002468: 4a48 ldr r2, [pc, #288] ; (800258c ) + 800246a: 4293 cmp r3, r2 + 800246c: d019 beq.n 80024a2 + 800246e: 687b ldr r3, [r7, #4] + 8002470: 4a47 ldr r2, [pc, #284] ; (8002590 ) + 8002472: 4293 cmp r3, r2 + 8002474: d013 beq.n 800249e + 8002476: 687b ldr r3, [r7, #4] + 8002478: 4a46 ldr r2, [pc, #280] ; (8002594 ) + 800247a: 4293 cmp r3, r2 + 800247c: d00d beq.n 800249a + 800247e: 687b ldr r3, [r7, #4] + 8002480: 4a45 ldr r2, [pc, #276] ; (8002598 ) + 8002482: 4293 cmp r3, r2 + 8002484: d007 beq.n 8002496 + 8002486: 687b ldr r3, [r7, #4] + 8002488: 4a44 ldr r2, [pc, #272] ; (800259c ) + 800248a: 4293 cmp r3, r2 + 800248c: d101 bne.n 8002492 + 800248e: 2304 movs r3, #4 + 8002490: e008 b.n 80024a4 + 8002492: 2307 movs r3, #7 + 8002494: e006 b.n 80024a4 + 8002496: 2303 movs r3, #3 + 8002498: e004 b.n 80024a4 + 800249a: 2302 movs r3, #2 + 800249c: e002 b.n 80024a4 + 800249e: 2301 movs r3, #1 + 80024a0: e000 b.n 80024a4 + 80024a2: 2300 movs r3, #0 + 80024a4: 69fa ldr r2, [r7, #28] + 80024a6: f002 0203 and.w r2, r2, #3 + 80024aa: 0092 lsls r2, r2, #2 + 80024ac: 4093 lsls r3, r2 + 80024ae: 69ba ldr r2, [r7, #24] + 80024b0: 4313 orrs r3, r2 + 80024b2: 61bb str r3, [r7, #24] + SYSCFG->EXTICR[position >> 2U] = temp; + 80024b4: 4934 ldr r1, [pc, #208] ; (8002588 ) + 80024b6: 69fb ldr r3, [r7, #28] + 80024b8: 089b lsrs r3, r3, #2 + 80024ba: 3302 adds r3, #2 + 80024bc: 69ba ldr r2, [r7, #24] + 80024be: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 8000e9c: 4b3a ldr r3, [pc, #232] ; (8000f88 ) - 8000e9e: 681b ldr r3, [r3, #0] - 8000ea0: 613b str r3, [r7, #16] - CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000ea2: 68fb ldr r3, [r7, #12] - 8000ea4: 43db mvns r3, r3 - 8000ea6: 693a ldr r2, [r7, #16] - 8000ea8: 4013 ands r3, r2 - 8000eaa: 613b str r3, [r7, #16] - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - 8000eac: 683b ldr r3, [r7, #0] - 8000eae: 685b ldr r3, [r3, #4] - 8000eb0: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8000eb4: 2b00 cmp r3, #0 - 8000eb6: d003 beq.n 8000ec0 + 80024c2: 4b37 ldr r3, [pc, #220] ; (80025a0 ) + 80024c4: 681b ldr r3, [r3, #0] + 80024c6: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80024c8: 693b ldr r3, [r7, #16] + 80024ca: 43db mvns r3, r3 + 80024cc: 69ba ldr r2, [r7, #24] + 80024ce: 4013 ands r3, r2 + 80024d0: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + 80024d2: 683b ldr r3, [r7, #0] + 80024d4: 685b ldr r3, [r3, #4] + 80024d6: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80024da: 2b00 cmp r3, #0 + 80024dc: d003 beq.n 80024e6 { - SET_BIT(temp, iocurrent); - 8000eb8: 693a ldr r2, [r7, #16] - 8000eba: 68fb ldr r3, [r7, #12] - 8000ebc: 4313 orrs r3, r2 - 8000ebe: 613b str r3, [r7, #16] + temp |= iocurrent; + 80024de: 69ba ldr r2, [r7, #24] + 80024e0: 693b ldr r3, [r7, #16] + 80024e2: 4313 orrs r3, r2 + 80024e4: 61bb str r3, [r7, #24] } EXTI->IMR = temp; - 8000ec0: 4a31 ldr r2, [pc, #196] ; (8000f88 ) - 8000ec2: 693b ldr r3, [r7, #16] - 8000ec4: 6013 str r3, [r2, #0] + 80024e6: 4a2e ldr r2, [pc, #184] ; (80025a0 ) + 80024e8: 69bb ldr r3, [r7, #24] + 80024ea: 6013 str r3, [r2, #0] temp = EXTI->EMR; - 8000ec6: 4b30 ldr r3, [pc, #192] ; (8000f88 ) - 8000ec8: 685b ldr r3, [r3, #4] - 8000eca: 613b str r3, [r7, #16] - CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000ecc: 68fb ldr r3, [r7, #12] - 8000ece: 43db mvns r3, r3 - 8000ed0: 693a ldr r2, [r7, #16] - 8000ed2: 4013 ands r3, r2 - 8000ed4: 613b str r3, [r7, #16] - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - 8000ed6: 683b ldr r3, [r7, #0] - 8000ed8: 685b ldr r3, [r3, #4] - 8000eda: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8000ede: 2b00 cmp r3, #0 - 8000ee0: d003 beq.n 8000eea + 80024ec: 4b2c ldr r3, [pc, #176] ; (80025a0 ) + 80024ee: 685b ldr r3, [r3, #4] + 80024f0: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 80024f2: 693b ldr r3, [r7, #16] + 80024f4: 43db mvns r3, r3 + 80024f6: 69ba ldr r2, [r7, #24] + 80024f8: 4013 ands r3, r2 + 80024fa: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + 80024fc: 683b ldr r3, [r7, #0] + 80024fe: 685b ldr r3, [r3, #4] + 8002500: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002504: 2b00 cmp r3, #0 + 8002506: d003 beq.n 8002510 { - SET_BIT(temp, iocurrent); - 8000ee2: 693a ldr r2, [r7, #16] - 8000ee4: 68fb ldr r3, [r7, #12] - 8000ee6: 4313 orrs r3, r2 - 8000ee8: 613b str r3, [r7, #16] + temp |= iocurrent; + 8002508: 69ba ldr r2, [r7, #24] + 800250a: 693b ldr r3, [r7, #16] + 800250c: 4313 orrs r3, r2 + 800250e: 61bb str r3, [r7, #24] } EXTI->EMR = temp; - 8000eea: 4a27 ldr r2, [pc, #156] ; (8000f88 ) - 8000eec: 693b ldr r3, [r7, #16] - 8000eee: 6053 str r3, [r2, #4] + 8002510: 4a23 ldr r2, [pc, #140] ; (80025a0 ) + 8002512: 69bb ldr r3, [r7, #24] + 8002514: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 8000ef0: 4b25 ldr r3, [pc, #148] ; (8000f88 ) - 8000ef2: 689b ldr r3, [r3, #8] - 8000ef4: 613b str r3, [r7, #16] - CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000ef6: 68fb ldr r3, [r7, #12] - 8000ef8: 43db mvns r3, r3 - 8000efa: 693a ldr r2, [r7, #16] - 8000efc: 4013 ands r3, r2 - 8000efe: 613b str r3, [r7, #16] - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - 8000f00: 683b ldr r3, [r7, #0] - 8000f02: 685b ldr r3, [r3, #4] - 8000f04: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8000f08: 2b00 cmp r3, #0 - 8000f0a: d003 beq.n 8000f14 + 8002516: 4b22 ldr r3, [pc, #136] ; (80025a0 ) + 8002518: 689b ldr r3, [r3, #8] + 800251a: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 800251c: 693b ldr r3, [r7, #16] + 800251e: 43db mvns r3, r3 + 8002520: 69ba ldr r2, [r7, #24] + 8002522: 4013 ands r3, r2 + 8002524: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + 8002526: 683b ldr r3, [r7, #0] + 8002528: 685b ldr r3, [r3, #4] + 800252a: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 800252e: 2b00 cmp r3, #0 + 8002530: d003 beq.n 800253a { - SET_BIT(temp, iocurrent); - 8000f0c: 693a ldr r2, [r7, #16] - 8000f0e: 68fb ldr r3, [r7, #12] - 8000f10: 4313 orrs r3, r2 - 8000f12: 613b str r3, [r7, #16] + temp |= iocurrent; + 8002532: 69ba ldr r2, [r7, #24] + 8002534: 693b ldr r3, [r7, #16] + 8002536: 4313 orrs r3, r2 + 8002538: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; - 8000f14: 4a1c ldr r2, [pc, #112] ; (8000f88 ) - 8000f16: 693b ldr r3, [r7, #16] - 8000f18: 6093 str r3, [r2, #8] + 800253a: 4a19 ldr r2, [pc, #100] ; (80025a0 ) + 800253c: 69bb ldr r3, [r7, #24] + 800253e: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 8000f1a: 4b1b ldr r3, [pc, #108] ; (8000f88 ) - 8000f1c: 68db ldr r3, [r3, #12] - 8000f1e: 613b str r3, [r7, #16] - CLEAR_BIT(temp, (uint32_t)iocurrent); - 8000f20: 68fb ldr r3, [r7, #12] - 8000f22: 43db mvns r3, r3 - 8000f24: 693a ldr r2, [r7, #16] - 8000f26: 4013 ands r3, r2 - 8000f28: 613b str r3, [r7, #16] - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - 8000f2a: 683b ldr r3, [r7, #0] - 8000f2c: 685b ldr r3, [r3, #4] - 8000f2e: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8000f32: 2b00 cmp r3, #0 - 8000f34: d003 beq.n 8000f3e + 8002540: 4b17 ldr r3, [pc, #92] ; (80025a0 ) + 8002542: 68db ldr r3, [r3, #12] + 8002544: 61bb str r3, [r7, #24] + temp &= ~((uint32_t)iocurrent); + 8002546: 693b ldr r3, [r7, #16] + 8002548: 43db mvns r3, r3 + 800254a: 69ba ldr r2, [r7, #24] + 800254c: 4013 ands r3, r2 + 800254e: 61bb str r3, [r7, #24] + if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + 8002550: 683b ldr r3, [r7, #0] + 8002552: 685b ldr r3, [r3, #4] + 8002554: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002558: 2b00 cmp r3, #0 + 800255a: d003 beq.n 8002564 { - SET_BIT(temp, iocurrent); - 8000f36: 693a ldr r2, [r7, #16] - 8000f38: 68fb ldr r3, [r7, #12] - 8000f3a: 4313 orrs r3, r2 - 8000f3c: 613b str r3, [r7, #16] + temp |= iocurrent; + 800255c: 69ba ldr r2, [r7, #24] + 800255e: 693b ldr r3, [r7, #16] + 8002560: 4313 orrs r3, r2 + 8002562: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; - 8000f3e: 4a12 ldr r2, [pc, #72] ; (8000f88 ) - 8000f40: 693b ldr r3, [r7, #16] - 8000f42: 60d3 str r3, [r2, #12] + 8002564: 4a0e ldr r2, [pc, #56] ; (80025a0 ) + 8002566: 69bb ldr r3, [r7, #24] + 8002568: 60d3 str r3, [r2, #12] + for(position = 0U; position < GPIO_NUMBER; position++) + 800256a: 69fb ldr r3, [r7, #28] + 800256c: 3301 adds r3, #1 + 800256e: 61fb str r3, [r7, #28] + 8002570: 69fb ldr r3, [r7, #28] + 8002572: 2b0f cmp r3, #15 + 8002574: f67f aea2 bls.w 80022bc } } - - position++; - 8000f44: 697b ldr r3, [r7, #20] - 8000f46: 3301 adds r3, #1 - 8000f48: 617b str r3, [r7, #20] - while (((GPIO_Init->Pin) >> position) != 0) - 8000f4a: 683b ldr r3, [r7, #0] - 8000f4c: 681a ldr r2, [r3, #0] - 8000f4e: 697b ldr r3, [r7, #20] - 8000f50: fa22 f303 lsr.w r3, r2, r3 - 8000f54: 2b00 cmp r3, #0 - 8000f56: f47f ae97 bne.w 8000c88 } } - 8000f5a: bf00 nop - 8000f5c: 371c adds r7, #28 - 8000f5e: 46bd mov sp, r7 - 8000f60: bc80 pop {r7} - 8000f62: 4770 bx lr - 8000f64: 40023800 .word 0x40023800 - 8000f68: 40010000 .word 0x40010000 - 8000f6c: 40020000 .word 0x40020000 - 8000f70: 40020400 .word 0x40020400 - 8000f74: 40020800 .word 0x40020800 - 8000f78: 40020c00 .word 0x40020c00 - 8000f7c: 40021000 .word 0x40021000 - 8000f80: 40021400 .word 0x40021400 - 8000f84: 40021800 .word 0x40021800 - 8000f88: 40010400 .word 0x40010400 + 8002578: bf00 nop + 800257a: 3724 adds r7, #36 ; 0x24 + 800257c: 46bd mov sp, r7 + 800257e: f85d 7b04 ldr.w r7, [sp], #4 + 8002582: 4770 bx lr + 8002584: 40023800 .word 0x40023800 + 8002588: 40013800 .word 0x40013800 + 800258c: 40020000 .word 0x40020000 + 8002590: 40020400 .word 0x40020400 + 8002594: 40020800 .word 0x40020800 + 8002598: 40020c00 .word 0x40020c00 + 800259c: 40021000 .word 0x40021000 + 80025a0: 40013c00 .word 0x40013c00 -08000f8c : +080025a4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8000f8c: b480 push {r7} - 8000f8e: b083 sub sp, #12 - 8000f90: af00 add r7, sp, #0 - 8000f92: 6078 str r0, [r7, #4] - 8000f94: 460b mov r3, r1 - 8000f96: 807b strh r3, [r7, #2] - 8000f98: 4613 mov r3, r2 - 8000f9a: 707b strb r3, [r7, #1] + 80025a4: b480 push {r7} + 80025a6: b083 sub sp, #12 + 80025a8: af00 add r7, sp, #0 + 80025aa: 6078 str r0, [r7, #4] + 80025ac: 460b mov r3, r1 + 80025ae: 807b strh r3, [r7, #2] + 80025b0: 4613 mov r3, r2 + 80025b2: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); - if (PinState != GPIO_PIN_RESET) - 8000f9c: 787b ldrb r3, [r7, #1] - 8000f9e: 2b00 cmp r3, #0 - 8000fa0: d003 beq.n 8000faa + if(PinState != GPIO_PIN_RESET) + 80025b4: 787b ldrb r3, [r7, #1] + 80025b6: 2b00 cmp r3, #0 + 80025b8: d003 beq.n 80025c2 { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - 8000fa2: 887a ldrh r2, [r7, #2] - 8000fa4: 687b ldr r3, [r7, #4] - 8000fa6: 619a str r2, [r3, #24] + GPIOx->BSRR = GPIO_Pin; + 80025ba: 887a ldrh r2, [r7, #2] + 80025bc: 687b ldr r3, [r7, #4] + 80025be: 619a str r2, [r3, #24] } else { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } - 8000fa8: e003 b.n 8000fb2 - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; - 8000faa: 887b ldrh r3, [r7, #2] - 8000fac: 041a lsls r2, r3, #16 - 8000fae: 687b ldr r3, [r7, #4] - 8000fb0: 619a str r2, [r3, #24] + 80025c0: e003 b.n 80025ca + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + 80025c2: 887b ldrh r3, [r7, #2] + 80025c4: 041a lsls r2, r3, #16 + 80025c6: 687b ldr r3, [r7, #4] + 80025c8: 619a str r2, [r3, #24] } - 8000fb2: bf00 nop - 8000fb4: 370c adds r7, #12 - 8000fb6: 46bd mov sp, r7 - 8000fb8: bc80 pop {r7} - 8000fba: 4770 bx lr + 80025ca: bf00 nop + 80025cc: 370c adds r7, #12 + 80025ce: 46bd mov sp, r7 + 80025d0: f85d 7b04 ldr.w r7, [sp], #4 + 80025d4: 4770 bx lr + ... -08000fbc : - * supported by this macro. User should request a transition to HSE Off +080025d8 : + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + 80025d8: b480 push {r7} + 80025da: b083 sub sp, #12 + 80025dc: af00 add r7, sp, #0 + 80025de: 6078 str r0, [r7, #4] + 80025e0: 460b mov r3, r1 + 80025e2: 70fb strb r3, [r7, #3] + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80025e4: 4b09 ldr r3, [pc, #36] ; (800260c ) + 80025e6: 691b ldr r3, [r3, #16] + 80025e8: 4a08 ldr r2, [pc, #32] ; (800260c ) + 80025ea: f023 0304 bic.w r3, r3, #4 + 80025ee: 6113 str r3, [r2, #16] + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + 80025f0: 78fb ldrb r3, [r7, #3] + 80025f2: 2b01 cmp r3, #1 + 80025f4: d101 bne.n 80025fa + { + /* Request Wait For Interrupt */ + __WFI(); + 80025f6: bf30 wfi + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + 80025f8: e002 b.n 8002600 + __SEV(); + 80025fa: bf40 sev + __WFE(); + 80025fc: bf20 wfe + __WFE(); + 80025fe: bf20 wfe +} + 8002600: bf00 nop + 8002602: 370c adds r7, #12 + 8002604: 46bd mov sp, r7 + 8002606: f85d 7b04 ldr.w r7, [sp], #4 + 800260a: 4770 bx lr + 800260c: e000ed00 .word 0xe000ed00 + +08002610 : + * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8000fbc: b580 push {r7, lr} - 8000fbe: b088 sub sp, #32 - 8000fc0: af00 add r7, sp, #0 - 8000fc2: 6078 str r0, [r7, #4] - uint32_t tickstart; - HAL_StatusTypeDef status; - uint32_t sysclk_source, pll_config; + 8002610: b580 push {r7, lr} + 8002612: b086 sub sp, #24 + 8002614: af00 add r7, sp, #0 + 8002616: 6078 str r0, [r7, #4] + uint32_t tickstart, pll_config; - /* Check the parameters */ + /* Check Null pointer */ if(RCC_OscInitStruct == NULL) - 8000fc4: 687b ldr r3, [r7, #4] - 8000fc6: 2b00 cmp r3, #0 - 8000fc8: d101 bne.n 8000fce + 8002618: 687b ldr r3, [r7, #4] + 800261a: 2b00 cmp r3, #0 + 800261c: d101 bne.n 8002622 { return HAL_ERROR; - 8000fca: 2301 movs r3, #1 - 8000fcc: e31d b.n 800160a + 800261e: 2301 movs r3, #1 + 8002620: e25b b.n 8002ada } + /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - 8000fce: 4b94 ldr r3, [pc, #592] ; (8001220 ) - 8000fd0: 689b ldr r3, [r3, #8] - 8000fd2: f003 030c and.w r3, r3, #12 - 8000fd6: 61bb str r3, [r7, #24] - pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); - 8000fd8: 4b91 ldr r3, [pc, #580] ; (8001220 ) - 8000fda: 689b ldr r3, [r3, #8] - 8000fdc: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8000fe0: 617b str r3, [r7, #20] - /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 8000fe2: 687b ldr r3, [r7, #4] - 8000fe4: 681b ldr r3, [r3, #0] - 8000fe6: f003 0301 and.w r3, r3, #1 - 8000fea: 2b00 cmp r3, #0 - 8000fec: d07b beq.n 80010e6 + 8002622: 687b ldr r3, [r7, #4] + 8002624: 681b ldr r3, [r3, #0] + 8002626: f003 0301 and.w r3, r3, #1 + 800262a: 2b00 cmp r3, #0 + 800262c: d075 beq.n 800271a { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) - 8000fee: 69bb ldr r3, [r7, #24] - 8000ff0: 2b08 cmp r3, #8 - 8000ff2: d006 beq.n 8001002 - || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) - 8000ff4: 69bb ldr r3, [r7, #24] - 8000ff6: 2b0c cmp r3, #12 - 8000ff8: d10f bne.n 800101a - 8000ffa: 697b ldr r3, [r7, #20] - 8000ffc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 8001000: d10b bne.n 800101a + /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + 800262e: 4ba3 ldr r3, [pc, #652] ; (80028bc ) + 8002630: 689b ldr r3, [r3, #8] + 8002632: f003 030c and.w r3, r3, #12 + 8002636: 2b04 cmp r3, #4 + 8002638: d00c beq.n 8002654 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 800263a: 4ba0 ldr r3, [pc, #640] ; (80028bc ) + 800263c: 689b ldr r3, [r3, #8] + 800263e: f003 030c and.w r3, r3, #12 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ + 8002642: 2b08 cmp r3, #8 + 8002644: d112 bne.n 800266c + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + 8002646: 4b9d ldr r3, [pc, #628] ; (80028bc ) + 8002648: 685b ldr r3, [r3, #4] + 800264a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800264e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8002652: d10b bne.n 800266c { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001002: 4b87 ldr r3, [pc, #540] ; (8001220 ) - 8001004: 681b ldr r3, [r3, #0] - 8001006: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800100a: 2b00 cmp r3, #0 - 800100c: d06a beq.n 80010e4 - 800100e: 687b ldr r3, [r7, #4] - 8001010: 685b ldr r3, [r3, #4] - 8001012: 2b00 cmp r3, #0 - 8001014: d166 bne.n 80010e4 + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8002654: 4b99 ldr r3, [pc, #612] ; (80028bc ) + 8002656: 681b ldr r3, [r3, #0] + 8002658: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800265c: 2b00 cmp r3, #0 + 800265e: d05b beq.n 8002718 + 8002660: 687b ldr r3, [r7, #4] + 8002662: 685b ldr r3, [r3, #4] + 8002664: 2b00 cmp r3, #0 + 8002666: d157 bne.n 8002718 { return HAL_ERROR; - 8001016: 2301 movs r3, #1 - 8001018: e2f7 b.n 800160a + 8002668: 2301 movs r3, #1 + 800266a: e236 b.n 8002ada } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 800101a: 687b ldr r3, [r7, #4] - 800101c: 685b ldr r3, [r3, #4] - 800101e: 2b01 cmp r3, #1 - 8001020: d106 bne.n 8001030 - 8001022: 4b7f ldr r3, [pc, #508] ; (8001220 ) - 8001024: 681b ldr r3, [r3, #0] - 8001026: 4a7e ldr r2, [pc, #504] ; (8001220 ) - 8001028: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 800102c: 6013 str r3, [r2, #0] - 800102e: e02d b.n 800108c - 8001030: 687b ldr r3, [r7, #4] - 8001032: 685b ldr r3, [r3, #4] - 8001034: 2b00 cmp r3, #0 - 8001036: d10c bne.n 8001052 - 8001038: 4b79 ldr r3, [pc, #484] ; (8001220 ) - 800103a: 681b ldr r3, [r3, #0] - 800103c: 4a78 ldr r2, [pc, #480] ; (8001220 ) - 800103e: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 8001042: 6013 str r3, [r2, #0] - 8001044: 4b76 ldr r3, [pc, #472] ; (8001220 ) - 8001046: 681b ldr r3, [r3, #0] - 8001048: 4a75 ldr r2, [pc, #468] ; (8001220 ) - 800104a: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 800104e: 6013 str r3, [r2, #0] - 8001050: e01c b.n 800108c - 8001052: 687b ldr r3, [r7, #4] - 8001054: 685b ldr r3, [r3, #4] - 8001056: 2b05 cmp r3, #5 - 8001058: d10c bne.n 8001074 - 800105a: 4b71 ldr r3, [pc, #452] ; (8001220 ) - 800105c: 681b ldr r3, [r3, #0] - 800105e: 4a70 ldr r2, [pc, #448] ; (8001220 ) - 8001060: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 8001064: 6013 str r3, [r2, #0] - 8001066: 4b6e ldr r3, [pc, #440] ; (8001220 ) - 8001068: 681b ldr r3, [r3, #0] - 800106a: 4a6d ldr r2, [pc, #436] ; (8001220 ) - 800106c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 8001070: 6013 str r3, [r2, #0] - 8001072: e00b b.n 800108c - 8001074: 4b6a ldr r3, [pc, #424] ; (8001220 ) - 8001076: 681b ldr r3, [r3, #0] - 8001078: 4a69 ldr r2, [pc, #420] ; (8001220 ) - 800107a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 800107e: 6013 str r3, [r2, #0] - 8001080: 4b67 ldr r3, [pc, #412] ; (8001220 ) - 8001082: 681b ldr r3, [r3, #0] - 8001084: 4a66 ldr r2, [pc, #408] ; (8001220 ) - 8001086: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 800108a: 6013 str r3, [r2, #0] + 800266c: 687b ldr r3, [r7, #4] + 800266e: 685b ldr r3, [r3, #4] + 8002670: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8002674: d106 bne.n 8002684 + 8002676: 4b91 ldr r3, [pc, #580] ; (80028bc ) + 8002678: 681b ldr r3, [r3, #0] + 800267a: 4a90 ldr r2, [pc, #576] ; (80028bc ) + 800267c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002680: 6013 str r3, [r2, #0] + 8002682: e01d b.n 80026c0 + 8002684: 687b ldr r3, [r7, #4] + 8002686: 685b ldr r3, [r3, #4] + 8002688: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 800268c: d10c bne.n 80026a8 + 800268e: 4b8b ldr r3, [pc, #556] ; (80028bc ) + 8002690: 681b ldr r3, [r3, #0] + 8002692: 4a8a ldr r2, [pc, #552] ; (80028bc ) + 8002694: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8002698: 6013 str r3, [r2, #0] + 800269a: 4b88 ldr r3, [pc, #544] ; (80028bc ) + 800269c: 681b ldr r3, [r3, #0] + 800269e: 4a87 ldr r2, [pc, #540] ; (80028bc ) + 80026a0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80026a4: 6013 str r3, [r2, #0] + 80026a6: e00b b.n 80026c0 + 80026a8: 4b84 ldr r3, [pc, #528] ; (80028bc ) + 80026aa: 681b ldr r3, [r3, #0] + 80026ac: 4a83 ldr r2, [pc, #524] ; (80028bc ) + 80026ae: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80026b2: 6013 str r3, [r2, #0] + 80026b4: 4b81 ldr r3, [pc, #516] ; (80028bc ) + 80026b6: 681b ldr r3, [r3, #0] + 80026b8: 4a80 ldr r2, [pc, #512] ; (80028bc ) + 80026ba: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 80026be: 6013 str r3, [r2, #0] /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - 800108c: 687b ldr r3, [r7, #4] - 800108e: 685b ldr r3, [r3, #4] - 8001090: 2b00 cmp r3, #0 - 8001092: d013 beq.n 80010bc + if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) + 80026c0: 687b ldr r3, [r7, #4] + 80026c2: 685b ldr r3, [r3, #4] + 80026c4: 2b00 cmp r3, #0 + 80026c6: d013 beq.n 80026f0 { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001094: f7ff fcdc bl 8000a50 - 8001098: 6138 str r0, [r7, #16] + 80026c8: f7ff fc8a bl 8001fe0 + 80026cc: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - 800109a: e008 b.n 80010ae + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80026ce: e008 b.n 80026e2 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 800109c: f7ff fcd8 bl 8000a50 - 80010a0: 4602 mov r2, r0 - 80010a2: 693b ldr r3, [r7, #16] - 80010a4: 1ad3 subs r3, r2, r3 - 80010a6: 2b64 cmp r3, #100 ; 0x64 - 80010a8: d901 bls.n 80010ae + 80026d0: f7ff fc86 bl 8001fe0 + 80026d4: 4602 mov r2, r0 + 80026d6: 693b ldr r3, [r7, #16] + 80026d8: 1ad3 subs r3, r2, r3 + 80026da: 2b64 cmp r3, #100 ; 0x64 + 80026dc: d901 bls.n 80026e2 { return HAL_TIMEOUT; - 80010aa: 2303 movs r3, #3 - 80010ac: e2ad b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - 80010ae: 4b5c ldr r3, [pc, #368] ; (8001220 ) - 80010b0: 681b ldr r3, [r3, #0] - 80010b2: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80010b6: 2b00 cmp r3, #0 - 80010b8: d0f0 beq.n 800109c - 80010ba: e014 b.n 80010e6 + 80026de: 2303 movs r3, #3 + 80026e0: e1fb b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 80026e2: 4b76 ldr r3, [pc, #472] ; (80028bc ) + 80026e4: 681b ldr r3, [r3, #0] + 80026e6: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 80026ea: 2b00 cmp r3, #0 + 80026ec: d0f0 beq.n 80026d0 + 80026ee: e014 b.n 800271a } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80010bc: f7ff fcc8 bl 8000a50 - 80010c0: 6138 str r0, [r7, #16] + 80026f0: f7ff fc76 bl 8001fe0 + 80026f4: 6138 str r0, [r7, #16] - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) - 80010c2: e008 b.n 80010d6 + /* Wait till HSE is bypassed or disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 80026f6: e008 b.n 800270a { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 80010c4: f7ff fcc4 bl 8000a50 - 80010c8: 4602 mov r2, r0 - 80010ca: 693b ldr r3, [r7, #16] - 80010cc: 1ad3 subs r3, r2, r3 - 80010ce: 2b64 cmp r3, #100 ; 0x64 - 80010d0: d901 bls.n 80010d6 + if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + 80026f8: f7ff fc72 bl 8001fe0 + 80026fc: 4602 mov r2, r0 + 80026fe: 693b ldr r3, [r7, #16] + 8002700: 1ad3 subs r3, r2, r3 + 8002702: 2b64 cmp r3, #100 ; 0x64 + 8002704: d901 bls.n 800270a { return HAL_TIMEOUT; - 80010d2: 2303 movs r3, #3 - 80010d4: e299 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) - 80010d6: 4b52 ldr r3, [pc, #328] ; (8001220 ) - 80010d8: 681b ldr r3, [r3, #0] - 80010da: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80010de: 2b00 cmp r3, #0 - 80010e0: d1f0 bne.n 80010c4 - 80010e2: e000 b.n 80010e6 - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 80010e4: bf00 nop + 8002706: 2303 movs r3, #3 + 8002708: e1e7 b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + 800270a: 4b6c ldr r3, [pc, #432] ; (80028bc ) + 800270c: 681b ldr r3, [r3, #0] + 800270e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002712: 2b00 cmp r3, #0 + 8002714: d1f0 bne.n 80026f8 + 8002716: e000 b.n 800271a + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + 8002718: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 80010e6: 687b ldr r3, [r7, #4] - 80010e8: 681b ldr r3, [r3, #0] - 80010ea: f003 0302 and.w r3, r3, #2 - 80010ee: 2b00 cmp r3, #0 - 80010f0: d05a beq.n 80011a8 + 800271a: 687b ldr r3, [r7, #4] + 800271c: 681b ldr r3, [r3, #0] + 800271e: f003 0302 and.w r3, r3, #2 + 8002722: 2b00 cmp r3, #0 + 8002724: d063 beq.n 80027ee /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) - 80010f2: 69bb ldr r3, [r7, #24] - 80010f4: 2b04 cmp r3, #4 - 80010f6: d005 beq.n 8001104 - || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) - 80010f8: 69bb ldr r3, [r7, #24] - 80010fa: 2b0c cmp r3, #12 - 80010fc: d119 bne.n 8001132 - 80010fe: 697b ldr r3, [r7, #20] - 8001100: 2b00 cmp r3, #0 - 8001102: d116 bne.n 8001132 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + 8002726: 4b65 ldr r3, [pc, #404] ; (80028bc ) + 8002728: 689b ldr r3, [r3, #8] + 800272a: f003 030c and.w r3, r3, #12 + 800272e: 2b00 cmp r3, #0 + 8002730: d00b beq.n 800274a + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 8002732: 4b62 ldr r3, [pc, #392] ; (80028bc ) + 8002734: 689b ldr r3, [r3, #8] + 8002736: f003 030c and.w r3, r3, #12 + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ + 800273a: 2b08 cmp r3, #8 + 800273c: d11c bne.n 8002778 + ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + 800273e: 4b5f ldr r3, [pc, #380] ; (80028bc ) + 8002740: 685b ldr r3, [r3, #4] + 8002742: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002746: 2b00 cmp r3, #0 + 8002748: d116 bne.n 8002778 { /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001104: 4b46 ldr r3, [pc, #280] ; (8001220 ) - 8001106: 681b ldr r3, [r3, #0] - 8001108: f003 0302 and.w r3, r3, #2 - 800110c: 2b00 cmp r3, #0 - 800110e: d005 beq.n 800111c - 8001110: 687b ldr r3, [r7, #4] - 8001112: 68db ldr r3, [r3, #12] - 8001114: 2b01 cmp r3, #1 - 8001116: d001 beq.n 800111c + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 800274a: 4b5c ldr r3, [pc, #368] ; (80028bc ) + 800274c: 681b ldr r3, [r3, #0] + 800274e: f003 0302 and.w r3, r3, #2 + 8002752: 2b00 cmp r3, #0 + 8002754: d005 beq.n 8002762 + 8002756: 687b ldr r3, [r7, #4] + 8002758: 68db ldr r3, [r3, #12] + 800275a: 2b01 cmp r3, #1 + 800275c: d001 beq.n 8002762 { return HAL_ERROR; - 8001118: 2301 movs r3, #1 - 800111a: e276 b.n 800160a + 800275e: 2301 movs r3, #1 + 8002760: e1bb b.n 8002ada } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 800111c: 4b40 ldr r3, [pc, #256] ; (8001220 ) - 800111e: 685b ldr r3, [r3, #4] - 8001120: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 - 8001124: 687b ldr r3, [r7, #4] - 8001126: 691b ldr r3, [r3, #16] - 8001128: 021b lsls r3, r3, #8 - 800112a: 493d ldr r1, [pc, #244] ; (8001220 ) - 800112c: 4313 orrs r3, r2 - 800112e: 604b str r3, [r1, #4] - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001130: e03a b.n 80011a8 + 8002762: 4b56 ldr r3, [pc, #344] ; (80028bc ) + 8002764: 681b ldr r3, [r3, #0] + 8002766: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 800276a: 687b ldr r3, [r7, #4] + 800276c: 691b ldr r3, [r3, #16] + 800276e: 00db lsls r3, r3, #3 + 8002770: 4952 ldr r1, [pc, #328] ; (80028bc ) + 8002772: 4313 orrs r3, r2 + 8002774: 600b str r3, [r1, #0] + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + 8002776: e03a b.n 80027ee } } else { /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - 8001132: 687b ldr r3, [r7, #4] - 8001134: 68db ldr r3, [r3, #12] - 8001136: 2b00 cmp r3, #0 - 8001138: d020 beq.n 800117c + if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) + 8002778: 687b ldr r3, [r7, #4] + 800277a: 68db ldr r3, [r3, #12] + 800277c: 2b00 cmp r3, #0 + 800277e: d020 beq.n 80027c2 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 800113a: 4b3a ldr r3, [pc, #232] ; (8001224 ) - 800113c: 2201 movs r2, #1 - 800113e: 601a str r2, [r3, #0] + 8002780: 4b4f ldr r3, [pc, #316] ; (80028c0 ) + 8002782: 2201 movs r2, #1 + 8002784: 601a str r2, [r3, #0] - /* Get Start Tick */ + /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001140: f7ff fc86 bl 8000a50 - 8001144: 6138 str r0, [r7, #16] + 8002786: f7ff fc2b bl 8001fe0 + 800278a: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - 8001146: e008 b.n 800115a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 800278c: e008 b.n 80027a0 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 8001148: f7ff fc82 bl 8000a50 - 800114c: 4602 mov r2, r0 - 800114e: 693b ldr r3, [r7, #16] - 8001150: 1ad3 subs r3, r2, r3 - 8001152: 2b02 cmp r3, #2 - 8001154: d901 bls.n 800115a + 800278e: f7ff fc27 bl 8001fe0 + 8002792: 4602 mov r2, r0 + 8002794: 693b ldr r3, [r7, #16] + 8002796: 1ad3 subs r3, r2, r3 + 8002798: 2b02 cmp r3, #2 + 800279a: d901 bls.n 80027a0 { return HAL_TIMEOUT; - 8001156: 2303 movs r3, #3 - 8001158: e257 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - 800115a: 4b31 ldr r3, [pc, #196] ; (8001220 ) - 800115c: 681b ldr r3, [r3, #0] - 800115e: f003 0302 and.w r3, r3, #2 - 8001162: 2b00 cmp r3, #0 - 8001164: d0f0 beq.n 8001148 + 800279c: 2303 movs r3, #3 + 800279e: e19c b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 80027a0: 4b46 ldr r3, [pc, #280] ; (80028bc ) + 80027a2: 681b ldr r3, [r3, #0] + 80027a4: f003 0302 and.w r3, r3, #2 + 80027a8: 2b00 cmp r3, #0 + 80027aa: d0f0 beq.n 800278e } } - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 8001166: 4b2e ldr r3, [pc, #184] ; (8001220 ) - 8001168: 685b ldr r3, [r3, #4] - 800116a: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 - 800116e: 687b ldr r3, [r7, #4] - 8001170: 691b ldr r3, [r3, #16] - 8001172: 021b lsls r3, r3, #8 - 8001174: 492a ldr r1, [pc, #168] ; (8001220 ) - 8001176: 4313 orrs r3, r2 - 8001178: 604b str r3, [r1, #4] - 800117a: e015 b.n 80011a8 + 80027ac: 4b43 ldr r3, [pc, #268] ; (80028bc ) + 80027ae: 681b ldr r3, [r3, #0] + 80027b0: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 80027b4: 687b ldr r3, [r7, #4] + 80027b6: 691b ldr r3, [r3, #16] + 80027b8: 00db lsls r3, r3, #3 + 80027ba: 4940 ldr r1, [pc, #256] ; (80028bc ) + 80027bc: 4313 orrs r3, r2 + 80027be: 600b str r3, [r1, #0] + 80027c0: e015 b.n 80027ee } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 800117c: 4b29 ldr r3, [pc, #164] ; (8001224 ) - 800117e: 2200 movs r2, #0 - 8001180: 601a str r2, [r3, #0] + 80027c2: 4b3f ldr r3, [pc, #252] ; (80028c0 ) + 80027c4: 2200 movs r2, #0 + 80027c6: 601a str r2, [r3, #0] - /* Get Start Tick */ + /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001182: f7ff fc65 bl 8000a50 - 8001186: 6138 str r0, [r7, #16] + 80027c8: f7ff fc0a bl 8001fe0 + 80027cc: 6138 str r0, [r7, #16] - /* Wait till HSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) - 8001188: e008 b.n 800119c + /* Wait till HSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80027ce: e008 b.n 80027e2 { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 800118a: f7ff fc61 bl 8000a50 - 800118e: 4602 mov r2, r0 - 8001190: 693b ldr r3, [r7, #16] - 8001192: 1ad3 subs r3, r2, r3 - 8001194: 2b02 cmp r3, #2 - 8001196: d901 bls.n 800119c + 80027d0: f7ff fc06 bl 8001fe0 + 80027d4: 4602 mov r2, r0 + 80027d6: 693b ldr r3, [r7, #16] + 80027d8: 1ad3 subs r3, r2, r3 + 80027da: 2b02 cmp r3, #2 + 80027dc: d901 bls.n 80027e2 { return HAL_TIMEOUT; - 8001198: 2303 movs r3, #3 - 800119a: e236 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) - 800119c: 4b20 ldr r3, [pc, #128] ; (8001220 ) - 800119e: 681b ldr r3, [r3, #0] - 80011a0: f003 0302 and.w r3, r3, #2 - 80011a4: 2b00 cmp r3, #0 - 80011a6: d1f0 bne.n 800118a - } - } - } - } - /*----------------------------- MSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - 80011a8: 687b ldr r3, [r7, #4] - 80011aa: 681b ldr r3, [r3, #0] - 80011ac: f003 0310 and.w r3, r3, #16 - 80011b0: 2b00 cmp r3, #0 - 80011b2: f000 80b8 beq.w 8001326 - { - /* When the MSI is used as system clock it will not be disabled */ - if(sysclk_source == RCC_CFGR_SWS_MSI) - 80011b6: 69bb ldr r3, [r7, #24] - 80011b8: 2b00 cmp r3, #0 - 80011ba: d170 bne.n 800129e - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - 80011bc: 4b18 ldr r3, [pc, #96] ; (8001220 ) - 80011be: 681b ldr r3, [r3, #0] - 80011c0: f403 7300 and.w r3, r3, #512 ; 0x200 - 80011c4: 2b00 cmp r3, #0 - 80011c6: d005 beq.n 80011d4 - 80011c8: 687b ldr r3, [r7, #4] - 80011ca: 699b ldr r3, [r3, #24] - 80011cc: 2b00 cmp r3, #0 - 80011ce: d101 bne.n 80011d4 - { - return HAL_ERROR; - 80011d0: 2301 movs r3, #1 - 80011d2: e21a b.n 800160a - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - 80011d4: 687b ldr r3, [r7, #4] - 80011d6: 6a1a ldr r2, [r3, #32] - 80011d8: 4b11 ldr r3, [pc, #68] ; (8001220 ) - 80011da: 685b ldr r3, [r3, #4] - 80011dc: f403 4360 and.w r3, r3, #57344 ; 0xe000 - 80011e0: 429a cmp r2, r3 - 80011e2: d921 bls.n 8001228 - { - /* First increase number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 80011e4: 687b ldr r3, [r7, #4] - 80011e6: 6a1b ldr r3, [r3, #32] - 80011e8: 4618 mov r0, r3 - 80011ea: f000 fc47 bl 8001a7c - 80011ee: 4603 mov r3, r0 - 80011f0: 2b00 cmp r3, #0 - 80011f2: d001 beq.n 80011f8 - { - return HAL_ERROR; - 80011f4: 2301 movs r3, #1 - 80011f6: e208 b.n 800160a - } - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 80011f8: 4b09 ldr r3, [pc, #36] ; (8001220 ) - 80011fa: 685b ldr r3, [r3, #4] - 80011fc: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 8001200: 687b ldr r3, [r7, #4] - 8001202: 6a1b ldr r3, [r3, #32] - 8001204: 4906 ldr r1, [pc, #24] ; (8001220 ) - 8001206: 4313 orrs r3, r2 - 8001208: 604b str r3, [r1, #4] - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 800120a: 4b05 ldr r3, [pc, #20] ; (8001220 ) - 800120c: 685b ldr r3, [r3, #4] - 800120e: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 - 8001212: 687b ldr r3, [r7, #4] - 8001214: 69db ldr r3, [r3, #28] - 8001216: 061b lsls r3, r3, #24 - 8001218: 4901 ldr r1, [pc, #4] ; (8001220 ) - 800121a: 4313 orrs r3, r2 - 800121c: 604b str r3, [r1, #4] - 800121e: e020 b.n 8001262 - 8001220: 40023800 .word 0x40023800 - 8001224: 42470000 .word 0x42470000 - } - else - { - /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 8001228: 4ba4 ldr r3, [pc, #656] ; (80014bc ) - 800122a: 685b ldr r3, [r3, #4] - 800122c: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 8001230: 687b ldr r3, [r7, #4] - 8001232: 6a1b ldr r3, [r3, #32] - 8001234: 49a1 ldr r1, [pc, #644] ; (80014bc ) - 8001236: 4313 orrs r3, r2 - 8001238: 604b str r3, [r1, #4] - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 800123a: 4ba0 ldr r3, [pc, #640] ; (80014bc ) - 800123c: 685b ldr r3, [r3, #4] - 800123e: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 - 8001242: 687b ldr r3, [r7, #4] - 8001244: 69db ldr r3, [r3, #28] - 8001246: 061b lsls r3, r3, #24 - 8001248: 499c ldr r1, [pc, #624] ; (80014bc ) - 800124a: 4313 orrs r3, r2 - 800124c: 604b str r3, [r1, #4] - - /* Decrease number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - 800124e: 687b ldr r3, [r7, #4] - 8001250: 6a1b ldr r3, [r3, #32] - 8001252: 4618 mov r0, r3 - 8001254: f000 fc12 bl 8001a7c - 8001258: 4603 mov r3, r0 - 800125a: 2b00 cmp r3, #0 - 800125c: d001 beq.n 8001262 - { - return HAL_ERROR; - 800125e: 2301 movs r3, #1 - 8001260: e1d3 b.n 800160a - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) - 8001262: 687b ldr r3, [r7, #4] - 8001264: 6a1b ldr r3, [r3, #32] - 8001266: 0b5b lsrs r3, r3, #13 - 8001268: 3301 adds r3, #1 - 800126a: f44f 4200 mov.w r2, #32768 ; 0x8000 - 800126e: fa02 f303 lsl.w r3, r2, r3 - >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; - 8001272: 4a92 ldr r2, [pc, #584] ; (80014bc ) - 8001274: 6892 ldr r2, [r2, #8] - 8001276: 0912 lsrs r2, r2, #4 - 8001278: f002 020f and.w r2, r2, #15 - 800127c: 4990 ldr r1, [pc, #576] ; (80014c0 ) - 800127e: 5c8a ldrb r2, [r1, r2] - 8001280: 40d3 lsrs r3, r2 - SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) - 8001282: 4a90 ldr r2, [pc, #576] ; (80014c4 ) - 8001284: 6013 str r3, [r2, #0] - - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - 8001286: 4b90 ldr r3, [pc, #576] ; (80014c8 ) - 8001288: 681b ldr r3, [r3, #0] - 800128a: 4618 mov r0, r3 - 800128c: f7ff fb94 bl 80009b8 - 8001290: 4603 mov r3, r0 - 8001292: 73fb strb r3, [r7, #15] - if(status != HAL_OK) - 8001294: 7bfb ldrb r3, [r7, #15] - 8001296: 2b00 cmp r3, #0 - 8001298: d045 beq.n 8001326 - { - return status; - 800129a: 7bfb ldrb r3, [r7, #15] - 800129c: e1b5 b.n 800160a - { - /* Check MSI State */ - assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - - /* Check the MSI State */ - if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - 800129e: 687b ldr r3, [r7, #4] - 80012a0: 699b ldr r3, [r3, #24] - 80012a2: 2b00 cmp r3, #0 - 80012a4: d029 beq.n 80012fa - { - /* Enable the Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - 80012a6: 4b89 ldr r3, [pc, #548] ; (80014cc ) - 80012a8: 2201 movs r2, #1 - 80012aa: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 80012ac: f7ff fbd0 bl 8000a50 - 80012b0: 6138 str r0, [r7, #16] - - /* Wait till MSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - 80012b2: e008 b.n 80012c6 - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 80012b4: f7ff fbcc bl 8000a50 - 80012b8: 4602 mov r2, r0 - 80012ba: 693b ldr r3, [r7, #16] - 80012bc: 1ad3 subs r3, r2, r3 - 80012be: 2b02 cmp r3, #2 - 80012c0: d901 bls.n 80012c6 - { - return HAL_TIMEOUT; - 80012c2: 2303 movs r3, #3 - 80012c4: e1a1 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - 80012c6: 4b7d ldr r3, [pc, #500] ; (80014bc ) - 80012c8: 681b ldr r3, [r3, #0] - 80012ca: f403 7300 and.w r3, r3, #512 ; 0x200 - 80012ce: 2b00 cmp r3, #0 - 80012d0: d0f0 beq.n 80012b4 - /* Check MSICalibrationValue and MSIClockRange input parameters */ - assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - 80012d2: 4b7a ldr r3, [pc, #488] ; (80014bc ) - 80012d4: 685b ldr r3, [r3, #4] - 80012d6: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 80012da: 687b ldr r3, [r7, #4] - 80012dc: 6a1b ldr r3, [r3, #32] - 80012de: 4977 ldr r1, [pc, #476] ; (80014bc ) - 80012e0: 4313 orrs r3, r2 - 80012e2: 604b str r3, [r1, #4] - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - 80012e4: 4b75 ldr r3, [pc, #468] ; (80014bc ) - 80012e6: 685b ldr r3, [r3, #4] - 80012e8: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000 - 80012ec: 687b ldr r3, [r7, #4] - 80012ee: 69db ldr r3, [r3, #28] - 80012f0: 061b lsls r3, r3, #24 - 80012f2: 4972 ldr r1, [pc, #456] ; (80014bc ) - 80012f4: 4313 orrs r3, r2 - 80012f6: 604b str r3, [r1, #4] - 80012f8: e015 b.n 8001326 - - } - else - { - /* Disable the Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_DISABLE(); - 80012fa: 4b74 ldr r3, [pc, #464] ; (80014cc ) - 80012fc: 2200 movs r2, #0 - 80012fe: 601a str r2, [r3, #0] - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - 8001300: f7ff fba6 bl 8000a50 - 8001304: 6138 str r0, [r7, #16] - - /* Wait till MSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) - 8001306: e008 b.n 800131a - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - 8001308: f7ff fba2 bl 8000a50 - 800130c: 4602 mov r2, r0 - 800130e: 693b ldr r3, [r7, #16] - 8001310: 1ad3 subs r3, r2, r3 - 8001312: 2b02 cmp r3, #2 - 8001314: d901 bls.n 800131a - { - return HAL_TIMEOUT; - 8001316: 2303 movs r3, #3 - 8001318: e177 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) - 800131a: 4b68 ldr r3, [pc, #416] ; (80014bc ) - 800131c: 681b ldr r3, [r3, #0] - 800131e: f403 7300 and.w r3, r3, #512 ; 0x200 - 8001322: 2b00 cmp r3, #0 - 8001324: d1f0 bne.n 8001308 + 80027de: 2303 movs r3, #3 + 80027e0: e17b b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + 80027e2: 4b36 ldr r3, [pc, #216] ; (80028bc ) + 80027e4: 681b ldr r3, [r3, #0] + 80027e6: f003 0302 and.w r3, r3, #2 + 80027ea: 2b00 cmp r3, #0 + 80027ec: d1f0 bne.n 80027d0 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8001326: 687b ldr r3, [r7, #4] - 8001328: 681b ldr r3, [r3, #0] - 800132a: f003 0308 and.w r3, r3, #8 - 800132e: 2b00 cmp r3, #0 - 8001330: d030 beq.n 8001394 + 80027ee: 687b ldr r3, [r7, #4] + 80027f0: 681b ldr r3, [r3, #0] + 80027f2: f003 0308 and.w r3, r3, #8 + 80027f6: 2b00 cmp r3, #0 + 80027f8: d030 beq.n 800285c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - 8001332: 687b ldr r3, [r7, #4] - 8001334: 695b ldr r3, [r3, #20] - 8001336: 2b00 cmp r3, #0 - 8001338: d016 beq.n 8001368 + if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) + 80027fa: 687b ldr r3, [r7, #4] + 80027fc: 695b ldr r3, [r3, #20] + 80027fe: 2b00 cmp r3, #0 + 8002800: d016 beq.n 8002830 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 800133a: 4b65 ldr r3, [pc, #404] ; (80014d0 ) - 800133c: 2201 movs r2, #1 - 800133e: 601a str r2, [r3, #0] + 8002802: 4b30 ldr r3, [pc, #192] ; (80028c4 ) + 8002804: 2201 movs r2, #1 + 8002806: 601a str r2, [r3, #0] - /* Get Start Tick */ + /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001340: f7ff fb86 bl 8000a50 - 8001344: 6138 str r0, [r7, #16] + 8002808: f7ff fbea bl 8001fe0 + 800280c: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) - 8001346: e008 b.n 800135a + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 800280e: e008 b.n 8002822 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8001348: f7ff fb82 bl 8000a50 - 800134c: 4602 mov r2, r0 - 800134e: 693b ldr r3, [r7, #16] - 8001350: 1ad3 subs r3, r2, r3 - 8001352: 2b02 cmp r3, #2 - 8001354: d901 bls.n 800135a + 8002810: f7ff fbe6 bl 8001fe0 + 8002814: 4602 mov r2, r0 + 8002816: 693b ldr r3, [r7, #16] + 8002818: 1ad3 subs r3, r2, r3 + 800281a: 2b02 cmp r3, #2 + 800281c: d901 bls.n 8002822 { return HAL_TIMEOUT; - 8001356: 2303 movs r3, #3 - 8001358: e157 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) - 800135a: 4b58 ldr r3, [pc, #352] ; (80014bc ) - 800135c: 6b5b ldr r3, [r3, #52] ; 0x34 - 800135e: f003 0302 and.w r3, r3, #2 - 8001362: 2b00 cmp r3, #0 - 8001364: d0f0 beq.n 8001348 - 8001366: e015 b.n 8001394 + 800281e: 2303 movs r3, #3 + 8002820: e15b b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + 8002822: 4b26 ldr r3, [pc, #152] ; (80028bc ) + 8002824: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002826: f003 0302 and.w r3, r3, #2 + 800282a: 2b00 cmp r3, #0 + 800282c: d0f0 beq.n 8002810 + 800282e: e015 b.n 800285c } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8001368: 4b59 ldr r3, [pc, #356] ; (80014d0 ) - 800136a: 2200 movs r2, #0 - 800136c: 601a str r2, [r3, #0] + 8002830: 4b24 ldr r3, [pc, #144] ; (80028c4 ) + 8002832: 2200 movs r2, #0 + 8002834: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 800136e: f7ff fb6f bl 8000a50 - 8001372: 6138 str r0, [r7, #16] + 8002836: f7ff fbd3 bl 8001fe0 + 800283a: 6138 str r0, [r7, #16] - /* Wait till LSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) - 8001374: e008 b.n 8001388 + /* Wait till LSI is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 800283c: e008 b.n 8002850 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8001376: f7ff fb6b bl 8000a50 - 800137a: 4602 mov r2, r0 - 800137c: 693b ldr r3, [r7, #16] - 800137e: 1ad3 subs r3, r2, r3 - 8001380: 2b02 cmp r3, #2 - 8001382: d901 bls.n 8001388 + 800283e: f7ff fbcf bl 8001fe0 + 8002842: 4602 mov r2, r0 + 8002844: 693b ldr r3, [r7, #16] + 8002846: 1ad3 subs r3, r2, r3 + 8002848: 2b02 cmp r3, #2 + 800284a: d901 bls.n 8002850 { return HAL_TIMEOUT; - 8001384: 2303 movs r3, #3 - 8001386: e140 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) - 8001388: 4b4c ldr r3, [pc, #304] ; (80014bc ) - 800138a: 6b5b ldr r3, [r3, #52] ; 0x34 - 800138c: f003 0302 and.w r3, r3, #2 - 8001390: 2b00 cmp r3, #0 - 8001392: d1f0 bne.n 8001376 + 800284c: 2303 movs r3, #3 + 800284e: e144 b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + 8002850: 4b1a ldr r3, [pc, #104] ; (80028bc ) + 8002852: 6f5b ldr r3, [r3, #116] ; 0x74 + 8002854: f003 0302 and.w r3, r3, #2 + 8002858: 2b00 cmp r3, #0 + 800285a: d1f0 bne.n 800283e } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8001394: 687b ldr r3, [r7, #4] - 8001396: 681b ldr r3, [r3, #0] - 8001398: f003 0304 and.w r3, r3, #4 - 800139c: 2b00 cmp r3, #0 - 800139e: f000 80b5 beq.w 800150c + 800285c: 687b ldr r3, [r7, #4] + 800285e: 681b ldr r3, [r3, #0] + 8002860: f003 0304 and.w r3, r3, #4 + 8002864: 2b00 cmp r3, #0 + 8002866: f000 80a0 beq.w 80029aa { FlagStatus pwrclkchanged = RESET; - 80013a2: 2300 movs r3, #0 - 80013a4: 77fb strb r3, [r7, #31] + 800286a: 2300 movs r3, #0 + 800286c: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 80013a6: 4b45 ldr r3, [pc, #276] ; (80014bc ) - 80013a8: 6a5b ldr r3, [r3, #36] ; 0x24 - 80013aa: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80013ae: 2b00 cmp r3, #0 - 80013b0: d10d bne.n 80013ce + 800286e: 4b13 ldr r3, [pc, #76] ; (80028bc ) + 8002870: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002872: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002876: 2b00 cmp r3, #0 + 8002878: d10f bne.n 800289a { __HAL_RCC_PWR_CLK_ENABLE(); - 80013b2: 4b42 ldr r3, [pc, #264] ; (80014bc ) - 80013b4: 6a5b ldr r3, [r3, #36] ; 0x24 - 80013b6: 4a41 ldr r2, [pc, #260] ; (80014bc ) - 80013b8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 80013bc: 6253 str r3, [r2, #36] ; 0x24 - 80013be: 4b3f ldr r3, [pc, #252] ; (80014bc ) - 80013c0: 6a5b ldr r3, [r3, #36] ; 0x24 - 80013c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80013c6: 60bb str r3, [r7, #8] - 80013c8: 68bb ldr r3, [r7, #8] + 800287a: 2300 movs r3, #0 + 800287c: 60bb str r3, [r7, #8] + 800287e: 4b0f ldr r3, [pc, #60] ; (80028bc ) + 8002880: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002882: 4a0e ldr r2, [pc, #56] ; (80028bc ) + 8002884: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002888: 6413 str r3, [r2, #64] ; 0x40 + 800288a: 4b0c ldr r3, [pc, #48] ; (80028bc ) + 800288c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800288e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002892: 60bb str r3, [r7, #8] + 8002894: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 80013ca: 2301 movs r3, #1 - 80013cc: 77fb strb r3, [r7, #31] + 8002896: 2301 movs r3, #1 + 8002898: 75fb strb r3, [r7, #23] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80013ce: 4b41 ldr r3, [pc, #260] ; (80014d4 ) - 80013d0: 681b ldr r3, [r3, #0] - 80013d2: f403 7380 and.w r3, r3, #256 ; 0x100 - 80013d6: 2b00 cmp r3, #0 - 80013d8: d118 bne.n 800140c + 800289a: 4b0b ldr r3, [pc, #44] ; (80028c8 ) + 800289c: 681b ldr r3, [r3, #0] + 800289e: f403 7380 and.w r3, r3, #256 ; 0x100 + 80028a2: 2b00 cmp r3, #0 + 80028a4: d121 bne.n 80028ea { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 80013da: 4b3e ldr r3, [pc, #248] ; (80014d4 ) - 80013dc: 681b ldr r3, [r3, #0] - 80013de: 4a3d ldr r2, [pc, #244] ; (80014d4 ) - 80013e0: f443 7380 orr.w r3, r3, #256 ; 0x100 - 80013e4: 6013 str r3, [r2, #0] + 80028a6: 4b08 ldr r3, [pc, #32] ; (80028c8 ) + 80028a8: 681b ldr r3, [r3, #0] + 80028aa: 4a07 ldr r2, [pc, #28] ; (80028c8 ) + 80028ac: f443 7380 orr.w r3, r3, #256 ; 0x100 + 80028b0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 80013e6: f7ff fb33 bl 8000a50 - 80013ea: 6138 str r0, [r7, #16] + 80028b2: f7ff fb95 bl 8001fe0 + 80028b6: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80013ec: e008 b.n 8001400 + 80028b8: e011 b.n 80028de + 80028ba: bf00 nop + 80028bc: 40023800 .word 0x40023800 + 80028c0: 42470000 .word 0x42470000 + 80028c4: 42470e80 .word 0x42470e80 + 80028c8: 40007000 .word 0x40007000 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80013ee: f7ff fb2f bl 8000a50 - 80013f2: 4602 mov r2, r0 - 80013f4: 693b ldr r3, [r7, #16] - 80013f6: 1ad3 subs r3, r2, r3 - 80013f8: 2b64 cmp r3, #100 ; 0x64 - 80013fa: d901 bls.n 8001400 + 80028cc: f7ff fb88 bl 8001fe0 + 80028d0: 4602 mov r2, r0 + 80028d2: 693b ldr r3, [r7, #16] + 80028d4: 1ad3 subs r3, r2, r3 + 80028d6: 2b02 cmp r3, #2 + 80028d8: d901 bls.n 80028de { return HAL_TIMEOUT; - 80013fc: 2303 movs r3, #3 - 80013fe: e104 b.n 800160a + 80028da: 2303 movs r3, #3 + 80028dc: e0fd b.n 8002ada while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001400: 4b34 ldr r3, [pc, #208] ; (80014d4 ) - 8001402: 681b ldr r3, [r3, #0] - 8001404: f403 7380 and.w r3, r3, #256 ; 0x100 - 8001408: 2b00 cmp r3, #0 - 800140a: d0f0 beq.n 80013ee + 80028de: 4b81 ldr r3, [pc, #516] ; (8002ae4 ) + 80028e0: 681b ldr r3, [r3, #0] + 80028e2: f403 7380 and.w r3, r3, #256 ; 0x100 + 80028e6: 2b00 cmp r3, #0 + 80028e8: d0f0 beq.n 80028cc } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 800140c: 687b ldr r3, [r7, #4] - 800140e: 689b ldr r3, [r3, #8] - 8001410: 2b01 cmp r3, #1 - 8001412: d106 bne.n 8001422 - 8001414: 4b29 ldr r3, [pc, #164] ; (80014bc ) - 8001416: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001418: 4a28 ldr r2, [pc, #160] ; (80014bc ) - 800141a: f443 7380 orr.w r3, r3, #256 ; 0x100 - 800141e: 6353 str r3, [r2, #52] ; 0x34 - 8001420: e02d b.n 800147e - 8001422: 687b ldr r3, [r7, #4] - 8001424: 689b ldr r3, [r3, #8] - 8001426: 2b00 cmp r3, #0 - 8001428: d10c bne.n 8001444 - 800142a: 4b24 ldr r3, [pc, #144] ; (80014bc ) - 800142c: 6b5b ldr r3, [r3, #52] ; 0x34 - 800142e: 4a23 ldr r2, [pc, #140] ; (80014bc ) - 8001430: f423 7380 bic.w r3, r3, #256 ; 0x100 - 8001434: 6353 str r3, [r2, #52] ; 0x34 - 8001436: 4b21 ldr r3, [pc, #132] ; (80014bc ) - 8001438: 6b5b ldr r3, [r3, #52] ; 0x34 - 800143a: 4a20 ldr r2, [pc, #128] ; (80014bc ) - 800143c: f423 6380 bic.w r3, r3, #1024 ; 0x400 - 8001440: 6353 str r3, [r2, #52] ; 0x34 - 8001442: e01c b.n 800147e - 8001444: 687b ldr r3, [r7, #4] - 8001446: 689b ldr r3, [r3, #8] - 8001448: 2b05 cmp r3, #5 - 800144a: d10c bne.n 8001466 - 800144c: 4b1b ldr r3, [pc, #108] ; (80014bc ) - 800144e: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001450: 4a1a ldr r2, [pc, #104] ; (80014bc ) - 8001452: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 8001456: 6353 str r3, [r2, #52] ; 0x34 - 8001458: 4b18 ldr r3, [pc, #96] ; (80014bc ) - 800145a: 6b5b ldr r3, [r3, #52] ; 0x34 - 800145c: 4a17 ldr r2, [pc, #92] ; (80014bc ) - 800145e: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8001462: 6353 str r3, [r2, #52] ; 0x34 - 8001464: e00b b.n 800147e - 8001466: 4b15 ldr r3, [pc, #84] ; (80014bc ) - 8001468: 6b5b ldr r3, [r3, #52] ; 0x34 - 800146a: 4a14 ldr r2, [pc, #80] ; (80014bc ) - 800146c: f423 7380 bic.w r3, r3, #256 ; 0x100 - 8001470: 6353 str r3, [r2, #52] ; 0x34 - 8001472: 4b12 ldr r3, [pc, #72] ; (80014bc ) - 8001474: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001476: 4a11 ldr r2, [pc, #68] ; (80014bc ) - 8001478: f423 6380 bic.w r3, r3, #1024 ; 0x400 - 800147c: 6353 str r3, [r2, #52] ; 0x34 + 80028ea: 687b ldr r3, [r7, #4] + 80028ec: 689b ldr r3, [r3, #8] + 80028ee: 2b01 cmp r3, #1 + 80028f0: d106 bne.n 8002900 + 80028f2: 4b7d ldr r3, [pc, #500] ; (8002ae8 ) + 80028f4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80028f6: 4a7c ldr r2, [pc, #496] ; (8002ae8 ) + 80028f8: f043 0301 orr.w r3, r3, #1 + 80028fc: 6713 str r3, [r2, #112] ; 0x70 + 80028fe: e01c b.n 800293a + 8002900: 687b ldr r3, [r7, #4] + 8002902: 689b ldr r3, [r3, #8] + 8002904: 2b05 cmp r3, #5 + 8002906: d10c bne.n 8002922 + 8002908: 4b77 ldr r3, [pc, #476] ; (8002ae8 ) + 800290a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800290c: 4a76 ldr r2, [pc, #472] ; (8002ae8 ) + 800290e: f043 0304 orr.w r3, r3, #4 + 8002912: 6713 str r3, [r2, #112] ; 0x70 + 8002914: 4b74 ldr r3, [pc, #464] ; (8002ae8 ) + 8002916: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002918: 4a73 ldr r2, [pc, #460] ; (8002ae8 ) + 800291a: f043 0301 orr.w r3, r3, #1 + 800291e: 6713 str r3, [r2, #112] ; 0x70 + 8002920: e00b b.n 800293a + 8002922: 4b71 ldr r3, [pc, #452] ; (8002ae8 ) + 8002924: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002926: 4a70 ldr r2, [pc, #448] ; (8002ae8 ) + 8002928: f023 0301 bic.w r3, r3, #1 + 800292c: 6713 str r3, [r2, #112] ; 0x70 + 800292e: 4b6e ldr r3, [pc, #440] ; (8002ae8 ) + 8002930: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002932: 4a6d ldr r2, [pc, #436] ; (8002ae8 ) + 8002934: f023 0304 bic.w r3, r3, #4 + 8002938: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - 800147e: 687b ldr r3, [r7, #4] - 8001480: 689b ldr r3, [r3, #8] - 8001482: 2b00 cmp r3, #0 - 8001484: d015 beq.n 80014b2 + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + 800293a: 687b ldr r3, [r7, #4] + 800293c: 689b ldr r3, [r3, #8] + 800293e: 2b00 cmp r3, #0 + 8002940: d015 beq.n 800296e { - /* Get Start Tick */ + /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001486: f7ff fae3 bl 8000a50 - 800148a: 6138 str r0, [r7, #16] + 8002942: f7ff fb4d bl 8001fe0 + 8002946: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - 800148c: e00a b.n 80014a4 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002948: e00a b.n 8002960 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 800148e: f7ff fadf bl 8000a50 - 8001492: 4602 mov r2, r0 - 8001494: 693b ldr r3, [r7, #16] - 8001496: 1ad3 subs r3, r2, r3 - 8001498: f241 3288 movw r2, #5000 ; 0x1388 - 800149c: 4293 cmp r3, r2 - 800149e: d901 bls.n 80014a4 + 800294a: f7ff fb49 bl 8001fe0 + 800294e: 4602 mov r2, r0 + 8002950: 693b ldr r3, [r7, #16] + 8002952: 1ad3 subs r3, r2, r3 + 8002954: f241 3288 movw r2, #5000 ; 0x1388 + 8002958: 4293 cmp r3, r2 + 800295a: d901 bls.n 8002960 { return HAL_TIMEOUT; - 80014a0: 2303 movs r3, #3 - 80014a2: e0b2 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - 80014a4: 4b05 ldr r3, [pc, #20] ; (80014bc ) - 80014a6: 6b5b ldr r3, [r3, #52] ; 0x34 - 80014a8: f403 7300 and.w r3, r3, #512 ; 0x200 - 80014ac: 2b00 cmp r3, #0 - 80014ae: d0ee beq.n 800148e - 80014b0: e023 b.n 80014fa + 800295c: 2303 movs r3, #3 + 800295e: e0bc b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8002960: 4b61 ldr r3, [pc, #388] ; (8002ae8 ) + 8002962: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002964: f003 0302 and.w r3, r3, #2 + 8002968: 2b00 cmp r3, #0 + 800296a: d0ee beq.n 800294a + 800296c: e014 b.n 8002998 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80014b2: f7ff facd bl 8000a50 - 80014b6: 6138 str r0, [r7, #16] + 800296e: f7ff fb37 bl 8001fe0 + 8002972: 6138 str r0, [r7, #16] - /* Wait till LSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) - 80014b8: e019 b.n 80014ee - 80014ba: bf00 nop - 80014bc: 40023800 .word 0x40023800 - 80014c0: 080025f0 .word 0x080025f0 - 80014c4: 20000000 .word 0x20000000 - 80014c8: 20000004 .word 0x20000004 - 80014cc: 42470020 .word 0x42470020 - 80014d0: 42470680 .word 0x42470680 - 80014d4: 40007000 .word 0x40007000 + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 8002974: e00a b.n 800298c { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 80014d8: f7ff faba bl 8000a50 - 80014dc: 4602 mov r2, r0 - 80014de: 693b ldr r3, [r7, #16] - 80014e0: 1ad3 subs r3, r2, r3 - 80014e2: f241 3288 movw r2, #5000 ; 0x1388 - 80014e6: 4293 cmp r3, r2 - 80014e8: d901 bls.n 80014ee + 8002976: f7ff fb33 bl 8001fe0 + 800297a: 4602 mov r2, r0 + 800297c: 693b ldr r3, [r7, #16] + 800297e: 1ad3 subs r3, r2, r3 + 8002980: f241 3288 movw r2, #5000 ; 0x1388 + 8002984: 4293 cmp r3, r2 + 8002986: d901 bls.n 800298c { return HAL_TIMEOUT; - 80014ea: 2303 movs r3, #3 - 80014ec: e08d b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) - 80014ee: 4b49 ldr r3, [pc, #292] ; (8001614 ) - 80014f0: 6b5b ldr r3, [r3, #52] ; 0x34 - 80014f2: f403 7300 and.w r3, r3, #512 ; 0x200 - 80014f6: 2b00 cmp r3, #0 - 80014f8: d1ee bne.n 80014d8 + 8002988: 2303 movs r3, #3 + 800298a: e0a6 b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + 800298c: 4b56 ldr r3, [pc, #344] ; (8002ae8 ) + 800298e: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002990: f003 0302 and.w r3, r3, #2 + 8002994: 2b00 cmp r3, #0 + 8002996: d1ee bne.n 8002976 } } } - /* Require to disable power clock if necessary */ + /* Restore clock configuration if changed */ if(pwrclkchanged == SET) - 80014fa: 7ffb ldrb r3, [r7, #31] - 80014fc: 2b01 cmp r3, #1 - 80014fe: d105 bne.n 800150c + 8002998: 7dfb ldrb r3, [r7, #23] + 800299a: 2b01 cmp r3, #1 + 800299c: d105 bne.n 80029aa { __HAL_RCC_PWR_CLK_DISABLE(); - 8001500: 4b44 ldr r3, [pc, #272] ; (8001614 ) - 8001502: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001504: 4a43 ldr r2, [pc, #268] ; (8001614 ) - 8001506: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 800150a: 6253 str r3, [r2, #36] ; 0x24 + 800299e: 4b52 ldr r3, [pc, #328] ; (8002ae8 ) + 80029a0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80029a2: 4a51 ldr r2, [pc, #324] ; (8002ae8 ) + 80029a4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80029a8: 6413 str r3, [r2, #64] ; 0x40 + } } - /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 800150c: 687b ldr r3, [r7, #4] - 800150e: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001510: 2b00 cmp r3, #0 - 8001512: d079 beq.n 8001608 + 80029aa: 687b ldr r3, [r7, #4] + 80029ac: 699b ldr r3, [r3, #24] + 80029ae: 2b00 cmp r3, #0 + 80029b0: f000 8092 beq.w 8002ad8 { /* Check if the PLL is used as system clock or not */ - if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8001514: 69bb ldr r3, [r7, #24] - 8001516: 2b0c cmp r3, #12 - 8001518: d056 beq.n 80015c8 + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + 80029b4: 4b4c ldr r3, [pc, #304] ; (8002ae8 ) + 80029b6: 689b ldr r3, [r3, #8] + 80029b8: f003 030c and.w r3, r3, #12 + 80029bc: 2b08 cmp r3, #8 + 80029be: d05c beq.n 8002a7a { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 800151a: 687b ldr r3, [r7, #4] - 800151c: 6a5b ldr r3, [r3, #36] ; 0x24 - 800151e: 2b02 cmp r3, #2 - 8001520: d13b bne.n 800159a - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); + 80029c0: 687b ldr r3, [r7, #4] + 80029c2: 699b ldr r3, [r3, #24] + 80029c4: 2b02 cmp r3, #2 + 80029c6: d141 bne.n 8002a4c + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 8001522: 4b3d ldr r3, [pc, #244] ; (8001618 ) - 8001524: 2200 movs r2, #0 - 8001526: 601a str r2, [r3, #0] + 80029c8: 4b48 ldr r3, [pc, #288] ; (8002aec ) + 80029ca: 2200 movs r2, #0 + 80029cc: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001528: f7ff fa92 bl 8000a50 - 800152c: 6138 str r0, [r7, #16] + 80029ce: f7ff fb07 bl 8001fe0 + 80029d2: 6138 str r0, [r7, #16] - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 800152e: e008 b.n 8001542 + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80029d4: e008 b.n 80029e8 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 8001530: f7ff fa8e bl 8000a50 - 8001534: 4602 mov r2, r0 - 8001536: 693b ldr r3, [r7, #16] - 8001538: 1ad3 subs r3, r2, r3 - 800153a: 2b02 cmp r3, #2 - 800153c: d901 bls.n 8001542 + 80029d6: f7ff fb03 bl 8001fe0 + 80029da: 4602 mov r2, r0 + 80029dc: 693b ldr r3, [r7, #16] + 80029de: 1ad3 subs r3, r2, r3 + 80029e0: 2b02 cmp r3, #2 + 80029e2: d901 bls.n 80029e8 { return HAL_TIMEOUT; - 800153e: 2303 movs r3, #3 - 8001540: e063 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 8001542: 4b34 ldr r3, [pc, #208] ; (8001614 ) - 8001544: 681b ldr r3, [r3, #0] - 8001546: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 800154a: 2b00 cmp r3, #0 - 800154c: d1f0 bne.n 8001530 + 80029e4: 2303 movs r3, #3 + 80029e6: e078 b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 80029e8: 4b3f ldr r3, [pc, #252] ; (8002ae8 ) + 80029ea: 681b ldr r3, [r3, #0] + 80029ec: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80029f0: 2b00 cmp r3, #0 + 80029f2: d1f0 bne.n 80029d6 } } /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - 800154e: 4b31 ldr r3, [pc, #196] ; (8001614 ) - 8001550: 689b ldr r3, [r3, #8] - 8001552: f423 027d bic.w r2, r3, #16580608 ; 0xfd0000 - 8001556: 687b ldr r3, [r7, #4] - 8001558: 6a99 ldr r1, [r3, #40] ; 0x28 - 800155a: 687b ldr r3, [r7, #4] - 800155c: 6adb ldr r3, [r3, #44] ; 0x2c - 800155e: 4319 orrs r1, r3 - 8001560: 687b ldr r3, [r7, #4] - 8001562: 6b1b ldr r3, [r3, #48] ; 0x30 - 8001564: 430b orrs r3, r1 - 8001566: 492b ldr r1, [pc, #172] ; (8001614 ) - 8001568: 4313 orrs r3, r2 - 800156a: 608b str r3, [r1, #8] - RCC_OscInitStruct->PLL.PLLMUL, - RCC_OscInitStruct->PLL.PLLDIV); + WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ + 80029f4: 687b ldr r3, [r7, #4] + 80029f6: 69da ldr r2, [r3, #28] + 80029f8: 687b ldr r3, [r7, #4] + 80029fa: 6a1b ldr r3, [r3, #32] + 80029fc: 431a orrs r2, r3 + 80029fe: 687b ldr r3, [r7, #4] + 8002a00: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002a02: 019b lsls r3, r3, #6 + 8002a04: 431a orrs r2, r3 + 8002a06: 687b ldr r3, [r7, #4] + 8002a08: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002a0a: 085b lsrs r3, r3, #1 + 8002a0c: 3b01 subs r3, #1 + 8002a0e: 041b lsls r3, r3, #16 + 8002a10: 431a orrs r2, r3 + 8002a12: 687b ldr r3, [r7, #4] + 8002a14: 6adb ldr r3, [r3, #44] ; 0x2c + 8002a16: 061b lsls r3, r3, #24 + 8002a18: 4933 ldr r1, [pc, #204] ; (8002ae8 ) + 8002a1a: 4313 orrs r3, r2 + 8002a1c: 604b str r3, [r1, #4] + RCC_OscInitStruct->PLL.PLLM | \ + (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ + (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ + (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 800156c: 4b2a ldr r3, [pc, #168] ; (8001618 ) - 800156e: 2201 movs r2, #1 - 8001570: 601a str r2, [r3, #0] + 8002a1e: 4b33 ldr r3, [pc, #204] ; (8002aec ) + 8002a20: 2201 movs r2, #1 + 8002a22: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001572: f7ff fa6d bl 8000a50 - 8001576: 6138 str r0, [r7, #16] + 8002a24: f7ff fadc bl 8001fe0 + 8002a28: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - 8001578: e008 b.n 800158c + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002a2a: e008 b.n 8002a3e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 800157a: f7ff fa69 bl 8000a50 - 800157e: 4602 mov r2, r0 - 8001580: 693b ldr r3, [r7, #16] - 8001582: 1ad3 subs r3, r2, r3 - 8001584: 2b02 cmp r3, #2 - 8001586: d901 bls.n 800158c + 8002a2c: f7ff fad8 bl 8001fe0 + 8002a30: 4602 mov r2, r0 + 8002a32: 693b ldr r3, [r7, #16] + 8002a34: 1ad3 subs r3, r2, r3 + 8002a36: 2b02 cmp r3, #2 + 8002a38: d901 bls.n 8002a3e { return HAL_TIMEOUT; - 8001588: 2303 movs r3, #3 - 800158a: e03e b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - 800158c: 4b21 ldr r3, [pc, #132] ; (8001614 ) - 800158e: 681b ldr r3, [r3, #0] - 8001590: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8001594: 2b00 cmp r3, #0 - 8001596: d0f0 beq.n 800157a - 8001598: e036 b.n 8001608 + 8002a3a: 2303 movs r3, #3 + 8002a3c: e04d b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002a3e: 4b2a ldr r3, [pc, #168] ; (8002ae8 ) + 8002a40: 681b ldr r3, [r3, #0] + 8002a42: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002a46: 2b00 cmp r3, #0 + 8002a48: d0f0 beq.n 8002a2c + 8002a4a: e045 b.n 8002ad8 } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800159a: 4b1f ldr r3, [pc, #124] ; (8001618 ) - 800159c: 2200 movs r2, #0 - 800159e: 601a str r2, [r3, #0] + 8002a4c: 4b27 ldr r3, [pc, #156] ; (8002aec ) + 8002a4e: 2200 movs r2, #0 + 8002a50: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80015a0: f7ff fa56 bl 8000a50 - 80015a4: 6138 str r0, [r7, #16] + 8002a52: f7ff fac5 bl 8001fe0 + 8002a56: 6138 str r0, [r7, #16] - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 80015a6: e008 b.n 80015ba + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002a58: e008 b.n 8002a6c { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80015a8: f7ff fa52 bl 8000a50 - 80015ac: 4602 mov r2, r0 - 80015ae: 693b ldr r3, [r7, #16] - 80015b0: 1ad3 subs r3, r2, r3 - 80015b2: 2b02 cmp r3, #2 - 80015b4: d901 bls.n 80015ba + 8002a5a: f7ff fac1 bl 8001fe0 + 8002a5e: 4602 mov r2, r0 + 8002a60: 693b ldr r3, [r7, #16] + 8002a62: 1ad3 subs r3, r2, r3 + 8002a64: 2b02 cmp r3, #2 + 8002a66: d901 bls.n 8002a6c { return HAL_TIMEOUT; - 80015b6: 2303 movs r3, #3 - 80015b8: e027 b.n 800160a - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - 80015ba: 4b16 ldr r3, [pc, #88] ; (8001614 ) - 80015bc: 681b ldr r3, [r3, #0] - 80015be: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80015c2: 2b00 cmp r3, #0 - 80015c4: d1f0 bne.n 80015a8 - 80015c6: e01f b.n 8001608 + 8002a68: 2303 movs r3, #3 + 8002a6a: e036 b.n 8002ada + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + 8002a6c: 4b1e ldr r3, [pc, #120] ; (8002ae8 ) + 8002a6e: 681b ldr r3, [r3, #0] + 8002a70: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002a74: 2b00 cmp r3, #0 + 8002a76: d1f0 bne.n 8002a5a + 8002a78: e02e b.n 8002ad8 } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 80015c8: 687b ldr r3, [r7, #4] - 80015ca: 6a5b ldr r3, [r3, #36] ; 0x24 - 80015cc: 2b01 cmp r3, #1 - 80015ce: d101 bne.n 80015d4 + 8002a7a: 687b ldr r3, [r7, #4] + 8002a7c: 699b ldr r3, [r3, #24] + 8002a7e: 2b01 cmp r3, #1 + 8002a80: d101 bne.n 8002a86 { return HAL_ERROR; - 80015d0: 2301 movs r3, #1 - 80015d2: e01a b.n 800160a + 8002a82: 2301 movs r3, #1 + 8002a84: e029 b.n 8002ada } else { /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->CFGR; - 80015d4: 4b0f ldr r3, [pc, #60] ; (8001614 ) - 80015d6: 689b ldr r3, [r3, #8] - 80015d8: 617b str r3, [r7, #20] - if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 80015da: 697b ldr r3, [r7, #20] - 80015dc: f403 3280 and.w r2, r3, #65536 ; 0x10000 - 80015e0: 687b ldr r3, [r7, #4] - 80015e2: 6a9b ldr r3, [r3, #40] ; 0x28 - 80015e4: 429a cmp r2, r3 - 80015e6: d10d bne.n 8001604 - (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || - 80015e8: 697b ldr r3, [r7, #20] - 80015ea: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000 - 80015ee: 687b ldr r3, [r7, #4] - 80015f0: 6adb ldr r3, [r3, #44] ; 0x2c - if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 80015f2: 429a cmp r2, r3 - 80015f4: d106 bne.n 8001604 - (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) - 80015f6: 697b ldr r3, [r7, #20] - 80015f8: f403 0240 and.w r2, r3, #12582912 ; 0xc00000 - 80015fc: 687b ldr r3, [r7, #4] - 80015fe: 6b1b ldr r3, [r3, #48] ; 0x30 - (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || - 8001600: 429a cmp r2, r3 - 8001602: d001 beq.n 8001608 + pll_config = RCC->PLLCFGR; + 8002a86: 4b18 ldr r3, [pc, #96] ; (8002ae8 ) + 8002a88: 685b ldr r3, [r3, #4] + 8002a8a: 60fb str r3, [r7, #12] + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002a8c: 68fb ldr r3, [r7, #12] + 8002a8e: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 8002a92: 687b ldr r3, [r7, #4] + 8002a94: 69db ldr r3, [r3, #28] + 8002a96: 429a cmp r2, r3 + 8002a98: d11c bne.n 8002ad4 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8002a9a: 68fb ldr r3, [r7, #12] + 8002a9c: f003 023f and.w r2, r3, #63 ; 0x3f + 8002aa0: 687b ldr r3, [r7, #4] + 8002aa2: 6a1b ldr r3, [r3, #32] + if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + 8002aa4: 429a cmp r2, r3 + 8002aa6: d115 bne.n 8002ad4 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || + 8002aa8: 68fa ldr r2, [r7, #12] + 8002aaa: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8002aae: 4013 ands r3, r2 + 8002ab0: 687a ldr r2, [r7, #4] + 8002ab2: 6a52 ldr r2, [r2, #36] ; 0x24 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + 8002ab4: 4293 cmp r3, r2 + 8002ab6: d10d bne.n 8002ad4 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 8002ab8: 68fb ldr r3, [r7, #12] + 8002aba: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 8002abe: 687b ldr r3, [r7, #4] + 8002ac0: 6a9b ldr r3, [r3, #40] ; 0x28 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != RCC_OscInitStruct->PLL.PLLN) || + 8002ac2: 429a cmp r2, r3 + 8002ac4: d106 bne.n 8002ad4 + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ)) + 8002ac6: 68fb ldr r3, [r7, #12] + 8002ac8: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 8002acc: 687b ldr r3, [r7, #4] + 8002ace: 6adb ldr r3, [r3, #44] ; 0x2c + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) || + 8002ad0: 429a cmp r2, r3 + 8002ad2: d001 beq.n 8002ad8 { return HAL_ERROR; - 8001604: 2301 movs r3, #1 - 8001606: e000 b.n 800160a + 8002ad4: 2301 movs r3, #1 + 8002ad6: e000 b.n 8002ada } } } } - return HAL_OK; - 8001608: 2300 movs r3, #0 + 8002ad8: 2300 movs r3, #0 } - 800160a: 4618 mov r0, r3 - 800160c: 3720 adds r7, #32 - 800160e: 46bd mov sp, r7 - 8001610: bd80 pop {r7, pc} - 8001612: bf00 nop - 8001614: 40023800 .word 0x40023800 - 8001618: 42470060 .word 0x42470060 + 8002ada: 4618 mov r0, r3 + 8002adc: 3718 adds r7, #24 + 8002ade: 46bd mov sp, r7 + 8002ae0: bd80 pop {r7, pc} + 8002ae2: bf00 nop + 8002ae4: 40007000 .word 0x40007000 + 8002ae8: 40023800 .word 0x40023800 + 8002aec: 42470060 .word 0x42470060 -0800161c : +08002af0 : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") - * @retval HAL status + * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 800161c: b580 push {r7, lr} - 800161e: b084 sub sp, #16 - 8001620: af00 add r7, sp, #0 - 8001622: 6078 str r0, [r7, #4] - 8001624: 6039 str r1, [r7, #0] + 8002af0: b580 push {r7, lr} + 8002af2: b084 sub sp, #16 + 8002af4: af00 add r7, sp, #0 + 8002af6: 6078 str r0, [r7, #4] + 8002af8: 6039 str r1, [r7, #0] uint32_t tickstart; - HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) - 8001626: 687b ldr r3, [r7, #4] - 8001628: 2b00 cmp r3, #0 - 800162a: d101 bne.n 8001630 + 8002afa: 687b ldr r3, [r7, #4] + 8002afc: 2b00 cmp r3, #0 + 8002afe: d101 bne.n 8002b04 { return HAL_ERROR; - 800162c: 2301 movs r3, #1 - 800162e: e11a b.n 8001866 + 8002b00: 2301 movs r3, #1 + 8002b02: e0cc b.n 8002c9e /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) - 8001630: 4b8f ldr r3, [pc, #572] ; (8001870 ) - 8001632: 681b ldr r3, [r3, #0] - 8001634: f003 0301 and.w r3, r3, #1 - 8001638: 683a ldr r2, [r7, #0] - 800163a: 429a cmp r2, r3 - 800163c: d919 bls.n 8001672 + 8002b04: 4b68 ldr r3, [pc, #416] ; (8002ca8 ) + 8002b06: 681b ldr r3, [r3, #0] + 8002b08: f003 030f and.w r3, r3, #15 + 8002b0c: 683a ldr r2, [r7, #0] + 8002b0e: 429a cmp r2, r3 + 8002b10: d90c bls.n 8002b2c { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 800163e: 683b ldr r3, [r7, #0] - 8001640: 2b01 cmp r3, #1 - 8001642: d105 bne.n 8001650 - 8001644: 4b8a ldr r3, [pc, #552] ; (8001870 ) - 8001646: 681b ldr r3, [r3, #0] - 8001648: 4a89 ldr r2, [pc, #548] ; (8001870 ) - 800164a: f043 0304 orr.w r3, r3, #4 - 800164e: 6013 str r3, [r2, #0] - 8001650: 4b87 ldr r3, [pc, #540] ; (8001870 ) - 8001652: 681b ldr r3, [r3, #0] - 8001654: f023 0201 bic.w r2, r3, #1 - 8001658: 4985 ldr r1, [pc, #532] ; (8001870 ) - 800165a: 683b ldr r3, [r7, #0] - 800165c: 4313 orrs r3, r2 - 800165e: 600b str r3, [r1, #0] + 8002b12: 4b65 ldr r3, [pc, #404] ; (8002ca8 ) + 8002b14: 683a ldr r2, [r7, #0] + 8002b16: b2d2 uxtb r2, r2 + 8002b18: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8001660: 4b83 ldr r3, [pc, #524] ; (8001870 ) - 8001662: 681b ldr r3, [r3, #0] - 8001664: f003 0301 and.w r3, r3, #1 - 8001668: 683a ldr r2, [r7, #0] - 800166a: 429a cmp r2, r3 - 800166c: d001 beq.n 8001672 + 8002b1a: 4b63 ldr r3, [pc, #396] ; (8002ca8 ) + 8002b1c: 681b ldr r3, [r3, #0] + 8002b1e: f003 030f and.w r3, r3, #15 + 8002b22: 683a ldr r2, [r7, #0] + 8002b24: 429a cmp r2, r3 + 8002b26: d001 beq.n 8002b2c { return HAL_ERROR; - 800166e: 2301 movs r3, #1 - 8001670: e0f9 b.n 8001866 + 8002b28: 2301 movs r3, #1 + 8002b2a: e0b8 b.n 8002c9e } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8001672: 687b ldr r3, [r7, #4] - 8001674: 681b ldr r3, [r3, #0] - 8001676: f003 0302 and.w r3, r3, #2 - 800167a: 2b00 cmp r3, #0 - 800167c: d008 beq.n 8001690 + 8002b2c: 687b ldr r3, [r7, #4] + 8002b2e: 681b ldr r3, [r3, #0] + 8002b30: f003 0302 and.w r3, r3, #2 + 8002b34: 2b00 cmp r3, #0 + 8002b36: d020 beq.n 8002b7a { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8002b38: 687b ldr r3, [r7, #4] + 8002b3a: 681b ldr r3, [r3, #0] + 8002b3c: f003 0304 and.w r3, r3, #4 + 8002b40: 2b00 cmp r3, #0 + 8002b42: d005 beq.n 8002b50 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + 8002b44: 4b59 ldr r3, [pc, #356] ; (8002cac ) + 8002b46: 689b ldr r3, [r3, #8] + 8002b48: 4a58 ldr r2, [pc, #352] ; (8002cac ) + 8002b4a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 8002b4e: 6093 str r3, [r2, #8] + } + + if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8002b50: 687b ldr r3, [r7, #4] + 8002b52: 681b ldr r3, [r3, #0] + 8002b54: f003 0308 and.w r3, r3, #8 + 8002b58: 2b00 cmp r3, #0 + 8002b5a: d005 beq.n 8002b68 + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + 8002b5c: 4b53 ldr r3, [pc, #332] ; (8002cac ) + 8002b5e: 689b ldr r3, [r3, #8] + 8002b60: 4a52 ldr r2, [pc, #328] ; (8002cac ) + 8002b62: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 8002b66: 6093 str r3, [r2, #8] + } + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 800167e: 4b7d ldr r3, [pc, #500] ; (8001874 ) - 8001680: 689b ldr r3, [r3, #8] - 8001682: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 8001686: 687b ldr r3, [r7, #4] - 8001688: 689b ldr r3, [r3, #8] - 800168a: 497a ldr r1, [pc, #488] ; (8001874 ) - 800168c: 4313 orrs r3, r2 - 800168e: 608b str r3, [r1, #8] + 8002b68: 4b50 ldr r3, [pc, #320] ; (8002cac ) + 8002b6a: 689b ldr r3, [r3, #8] + 8002b6c: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 8002b70: 687b ldr r3, [r7, #4] + 8002b72: 689b ldr r3, [r3, #8] + 8002b74: 494d ldr r1, [pc, #308] ; (8002cac ) + 8002b76: 4313 orrs r3, r2 + 8002b78: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 8001690: 687b ldr r3, [r7, #4] - 8001692: 681b ldr r3, [r3, #0] - 8001694: f003 0301 and.w r3, r3, #1 - 8001698: 2b00 cmp r3, #0 - 800169a: f000 808e beq.w 80017ba + 8002b7a: 687b ldr r3, [r7, #4] + 8002b7c: 681b ldr r3, [r3, #0] + 8002b7e: f003 0301 and.w r3, r3, #1 + 8002b82: 2b00 cmp r3, #0 + 8002b84: d044 beq.n 8002c10 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 800169e: 687b ldr r3, [r7, #4] - 80016a0: 685b ldr r3, [r3, #4] - 80016a2: 2b02 cmp r3, #2 - 80016a4: d107 bne.n 80016b6 + 8002b86: 687b ldr r3, [r7, #4] + 8002b88: 685b ldr r3, [r3, #4] + 8002b8a: 2b01 cmp r3, #1 + 8002b8c: d107 bne.n 8002b9e { /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - 80016a6: 4b73 ldr r3, [pc, #460] ; (8001874 ) - 80016a8: 681b ldr r3, [r3, #0] - 80016aa: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80016ae: 2b00 cmp r3, #0 - 80016b0: d121 bne.n 80016f6 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + 8002b8e: 4b47 ldr r3, [pc, #284] ; (8002cac ) + 8002b90: 681b ldr r3, [r3, #0] + 8002b92: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002b96: 2b00 cmp r3, #0 + 8002b98: d119 bne.n 8002bce { return HAL_ERROR; - 80016b2: 2301 movs r3, #1 - 80016b4: e0d7 b.n 8001866 + 8002b9a: 2301 movs r3, #1 + 8002b9c: e07f b.n 8002c9e } } /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 80016b6: 687b ldr r3, [r7, #4] - 80016b8: 685b ldr r3, [r3, #4] - 80016ba: 2b03 cmp r3, #3 - 80016bc: d107 bne.n 80016ce + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 8002b9e: 687b ldr r3, [r7, #4] + 8002ba0: 685b ldr r3, [r3, #4] + 8002ba2: 2b02 cmp r3, #2 + 8002ba4: d003 beq.n 8002bae + (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) + 8002ba6: 687b ldr r3, [r7, #4] + 8002ba8: 685b ldr r3, [r3, #4] + else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || + 8002baa: 2b03 cmp r3, #3 + 8002bac: d107 bne.n 8002bbe { /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - 80016be: 4b6d ldr r3, [pc, #436] ; (8001874 ) - 80016c0: 681b ldr r3, [r3, #0] - 80016c2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80016c6: 2b00 cmp r3, #0 - 80016c8: d115 bne.n 80016f6 + if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + 8002bae: 4b3f ldr r3, [pc, #252] ; (8002cac ) + 8002bb0: 681b ldr r3, [r3, #0] + 8002bb2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002bb6: 2b00 cmp r3, #0 + 8002bb8: d109 bne.n 8002bce { return HAL_ERROR; - 80016ca: 2301 movs r3, #1 - 80016cc: e0cb b.n 8001866 - } + 8002bba: 2301 movs r3, #1 + 8002bbc: e06f b.n 8002c9e } /* HSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - 80016ce: 687b ldr r3, [r7, #4] - 80016d0: 685b ldr r3, [r3, #4] - 80016d2: 2b01 cmp r3, #1 - 80016d4: d107 bne.n 80016e6 - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - 80016d6: 4b67 ldr r3, [pc, #412] ; (8001874 ) - 80016d8: 681b ldr r3, [r3, #0] - 80016da: f003 0302 and.w r3, r3, #2 - 80016de: 2b00 cmp r3, #0 - 80016e0: d109 bne.n 80016f6 - { - return HAL_ERROR; - 80016e2: 2301 movs r3, #1 - 80016e4: e0bf b.n 8001866 - } - /* MSI is selected as System Clock Source */ else { - /* Check the MSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - 80016e6: 4b63 ldr r3, [pc, #396] ; (8001874 ) - 80016e8: 681b ldr r3, [r3, #0] - 80016ea: f403 7300 and.w r3, r3, #512 ; 0x200 - 80016ee: 2b00 cmp r3, #0 - 80016f0: d101 bne.n 80016f6 + /* Check the HSI ready flag */ + if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + 8002bbe: 4b3b ldr r3, [pc, #236] ; (8002cac ) + 8002bc0: 681b ldr r3, [r3, #0] + 8002bc2: f003 0302 and.w r3, r3, #2 + 8002bc6: 2b00 cmp r3, #0 + 8002bc8: d101 bne.n 8002bce { return HAL_ERROR; - 80016f2: 2301 movs r3, #1 - 80016f4: e0b7 b.n 8001866 + 8002bca: 2301 movs r3, #1 + 8002bcc: e067 b.n 8002c9e } } + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 80016f6: 4b5f ldr r3, [pc, #380] ; (8001874 ) - 80016f8: 689b ldr r3, [r3, #8] - 80016fa: f023 0203 bic.w r2, r3, #3 - 80016fe: 687b ldr r3, [r7, #4] - 8001700: 685b ldr r3, [r3, #4] - 8001702: 495c ldr r1, [pc, #368] ; (8001874 ) - 8001704: 4313 orrs r3, r2 - 8001706: 608b str r3, [r1, #8] + 8002bce: 4b37 ldr r3, [pc, #220] ; (8002cac ) + 8002bd0: 689b ldr r3, [r3, #8] + 8002bd2: f023 0203 bic.w r2, r3, #3 + 8002bd6: 687b ldr r3, [r7, #4] + 8002bd8: 685b ldr r3, [r3, #4] + 8002bda: 4934 ldr r1, [pc, #208] ; (8002cac ) + 8002bdc: 4313 orrs r3, r2 + 8002bde: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001708: f7ff f9a2 bl 8000a50 - 800170c: 60f8 str r0, [r7, #12] + 8002be0: f7ff f9fe bl 8001fe0 + 8002be4: 60f8 str r0, [r7, #12] - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 800170e: 687b ldr r3, [r7, #4] - 8001710: 685b ldr r3, [r3, #4] - 8001712: 2b02 cmp r3, #2 - 8001714: d112 bne.n 800173c + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002be6: e00a b.n 8002bfe { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - 8001716: e00a b.n 800172e + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 8002be8: f7ff f9fa bl 8001fe0 + 8002bec: 4602 mov r2, r0 + 8002bee: 68fb ldr r3, [r7, #12] + 8002bf0: 1ad3 subs r3, r2, r3 + 8002bf2: f241 3288 movw r2, #5000 ; 0x1388 + 8002bf6: 4293 cmp r3, r2 + 8002bf8: d901 bls.n 8002bfe { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001718: f7ff f99a bl 8000a50 - 800171c: 4602 mov r2, r0 - 800171e: 68fb ldr r3, [r7, #12] - 8001720: 1ad3 subs r3, r2, r3 - 8001722: f241 3288 movw r2, #5000 ; 0x1388 - 8001726: 4293 cmp r3, r2 - 8001728: d901 bls.n 800172e - { - return HAL_TIMEOUT; - 800172a: 2303 movs r3, #3 - 800172c: e09b b.n 8001866 - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - 800172e: 4b51 ldr r3, [pc, #324] ; (8001874 ) - 8001730: 689b ldr r3, [r3, #8] - 8001732: f003 030c and.w r3, r3, #12 - 8001736: 2b08 cmp r3, #8 - 8001738: d1ee bne.n 8001718 - 800173a: e03e b.n 80017ba - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - 800173c: 687b ldr r3, [r7, #4] - 800173e: 685b ldr r3, [r3, #4] - 8001740: 2b03 cmp r3, #3 - 8001742: d112 bne.n 800176a - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 8001744: e00a b.n 800175c - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001746: f7ff f983 bl 8000a50 - 800174a: 4602 mov r2, r0 - 800174c: 68fb ldr r3, [r7, #12] - 800174e: 1ad3 subs r3, r2, r3 - 8001750: f241 3288 movw r2, #5000 ; 0x1388 - 8001754: 4293 cmp r3, r2 - 8001756: d901 bls.n 800175c - { - return HAL_TIMEOUT; - 8001758: 2303 movs r3, #3 - 800175a: e084 b.n 8001866 - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - 800175c: 4b45 ldr r3, [pc, #276] ; (8001874 ) - 800175e: 689b ldr r3, [r3, #8] - 8001760: f003 030c and.w r3, r3, #12 - 8001764: 2b0c cmp r3, #12 - 8001766: d1ee bne.n 8001746 - 8001768: e027 b.n 80017ba - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - 800176a: 687b ldr r3, [r7, #4] - 800176c: 685b ldr r3, [r3, #4] - 800176e: 2b01 cmp r3, #1 - 8001770: d11d bne.n 80017ae - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - 8001772: e00a b.n 800178a - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001774: f7ff f96c bl 8000a50 - 8001778: 4602 mov r2, r0 - 800177a: 68fb ldr r3, [r7, #12] - 800177c: 1ad3 subs r3, r2, r3 - 800177e: f241 3288 movw r2, #5000 ; 0x1388 - 8001782: 4293 cmp r3, r2 - 8001784: d901 bls.n 800178a - { - return HAL_TIMEOUT; - 8001786: 2303 movs r3, #3 - 8001788: e06d b.n 8001866 - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - 800178a: 4b3a ldr r3, [pc, #232] ; (8001874 ) - 800178c: 689b ldr r3, [r3, #8] - 800178e: f003 030c and.w r3, r3, #12 - 8001792: 2b04 cmp r3, #4 - 8001794: d1ee bne.n 8001774 - 8001796: e010 b.n 80017ba - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001798: f7ff f95a bl 8000a50 - 800179c: 4602 mov r2, r0 - 800179e: 68fb ldr r3, [r7, #12] - 80017a0: 1ad3 subs r3, r2, r3 - 80017a2: f241 3288 movw r2, #5000 ; 0x1388 - 80017a6: 4293 cmp r3, r2 - 80017a8: d901 bls.n 80017ae - { - return HAL_TIMEOUT; - 80017aa: 2303 movs r3, #3 - 80017ac: e05b b.n 8001866 - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) - 80017ae: 4b31 ldr r3, [pc, #196] ; (8001874 ) - 80017b0: 689b ldr r3, [r3, #8] - 80017b2: f003 030c and.w r3, r3, #12 - 80017b6: 2b00 cmp r3, #0 - 80017b8: d1ee bne.n 8001798 - } + return HAL_TIMEOUT; + 8002bfa: 2303 movs r3, #3 + 8002bfc: e04f b.n 8002c9e + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8002bfe: 4b2b ldr r3, [pc, #172] ; (8002cac ) + 8002c00: 689b ldr r3, [r3, #8] + 8002c02: f003 020c and.w r2, r3, #12 + 8002c06: 687b ldr r3, [r7, #4] + 8002c08: 685b ldr r3, [r3, #4] + 8002c0a: 009b lsls r3, r3, #2 + 8002c0c: 429a cmp r2, r3 + 8002c0e: d1eb bne.n 8002be8 } } } + /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) - 80017ba: 4b2d ldr r3, [pc, #180] ; (8001870 ) - 80017bc: 681b ldr r3, [r3, #0] - 80017be: f003 0301 and.w r3, r3, #1 - 80017c2: 683a ldr r2, [r7, #0] - 80017c4: 429a cmp r2, r3 - 80017c6: d219 bcs.n 80017fc + 8002c10: 4b25 ldr r3, [pc, #148] ; (8002ca8 ) + 8002c12: 681b ldr r3, [r3, #0] + 8002c14: f003 030f and.w r3, r3, #15 + 8002c18: 683a ldr r2, [r7, #0] + 8002c1a: 429a cmp r2, r3 + 8002c1c: d20c bcs.n 8002c38 { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 80017c8: 683b ldr r3, [r7, #0] - 80017ca: 2b01 cmp r3, #1 - 80017cc: d105 bne.n 80017da - 80017ce: 4b28 ldr r3, [pc, #160] ; (8001870 ) - 80017d0: 681b ldr r3, [r3, #0] - 80017d2: 4a27 ldr r2, [pc, #156] ; (8001870 ) - 80017d4: f043 0304 orr.w r3, r3, #4 - 80017d8: 6013 str r3, [r2, #0] - 80017da: 4b25 ldr r3, [pc, #148] ; (8001870 ) - 80017dc: 681b ldr r3, [r3, #0] - 80017de: f023 0201 bic.w r2, r3, #1 - 80017e2: 4923 ldr r1, [pc, #140] ; (8001870 ) - 80017e4: 683b ldr r3, [r7, #0] - 80017e6: 4313 orrs r3, r2 - 80017e8: 600b str r3, [r1, #0] + 8002c1e: 4b22 ldr r3, [pc, #136] ; (8002ca8 ) + 8002c20: 683a ldr r2, [r7, #0] + 8002c22: b2d2 uxtb r2, r2 + 8002c24: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 80017ea: 4b21 ldr r3, [pc, #132] ; (8001870 ) - 80017ec: 681b ldr r3, [r3, #0] - 80017ee: f003 0301 and.w r3, r3, #1 - 80017f2: 683a ldr r2, [r7, #0] - 80017f4: 429a cmp r2, r3 - 80017f6: d001 beq.n 80017fc + 8002c26: 4b20 ldr r3, [pc, #128] ; (8002ca8 ) + 8002c28: 681b ldr r3, [r3, #0] + 8002c2a: f003 030f and.w r3, r3, #15 + 8002c2e: 683a ldr r2, [r7, #0] + 8002c30: 429a cmp r2, r3 + 8002c32: d001 beq.n 8002c38 { return HAL_ERROR; - 80017f8: 2301 movs r3, #1 - 80017fa: e034 b.n 8001866 + 8002c34: 2301 movs r3, #1 + 8002c36: e032 b.n 8002c9e } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 80017fc: 687b ldr r3, [r7, #4] - 80017fe: 681b ldr r3, [r3, #0] - 8001800: f003 0304 and.w r3, r3, #4 - 8001804: 2b00 cmp r3, #0 - 8001806: d008 beq.n 800181a + 8002c38: 687b ldr r3, [r7, #4] + 8002c3a: 681b ldr r3, [r3, #0] + 8002c3c: f003 0304 and.w r3, r3, #4 + 8002c40: 2b00 cmp r3, #0 + 8002c42: d008 beq.n 8002c56 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 8001808: 4b1a ldr r3, [pc, #104] ; (8001874 ) - 800180a: 689b ldr r3, [r3, #8] - 800180c: f423 62e0 bic.w r2, r3, #1792 ; 0x700 - 8001810: 687b ldr r3, [r7, #4] - 8001812: 68db ldr r3, [r3, #12] - 8001814: 4917 ldr r1, [pc, #92] ; (8001874 ) - 8001816: 4313 orrs r3, r2 - 8001818: 608b str r3, [r1, #8] + 8002c44: 4b19 ldr r3, [pc, #100] ; (8002cac ) + 8002c46: 689b ldr r3, [r3, #8] + 8002c48: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 8002c4c: 687b ldr r3, [r7, #4] + 8002c4e: 68db ldr r3, [r3, #12] + 8002c50: 4916 ldr r1, [pc, #88] ; (8002cac ) + 8002c52: 4313 orrs r3, r2 + 8002c54: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 800181a: 687b ldr r3, [r7, #4] - 800181c: 681b ldr r3, [r3, #0] - 800181e: f003 0308 and.w r3, r3, #8 - 8001822: 2b00 cmp r3, #0 - 8001824: d009 beq.n 800183a + 8002c56: 687b ldr r3, [r7, #4] + 8002c58: 681b ldr r3, [r3, #0] + 8002c5a: f003 0308 and.w r3, r3, #8 + 8002c5e: 2b00 cmp r3, #0 + 8002c60: d009 beq.n 8002c76 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 8001826: 4b13 ldr r3, [pc, #76] ; (8001874 ) - 8001828: 689b ldr r3, [r3, #8] - 800182a: f423 5260 bic.w r2, r3, #14336 ; 0x3800 - 800182e: 687b ldr r3, [r7, #4] - 8001830: 691b ldr r3, [r3, #16] - 8001832: 00db lsls r3, r3, #3 - 8001834: 490f ldr r1, [pc, #60] ; (8001874 ) - 8001836: 4313 orrs r3, r2 - 8001838: 608b str r3, [r1, #8] + 8002c62: 4b12 ldr r3, [pc, #72] ; (8002cac ) + 8002c64: 689b ldr r3, [r3, #8] + 8002c66: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 8002c6a: 687b ldr r3, [r7, #4] + 8002c6c: 691b ldr r3, [r3, #16] + 8002c6e: 00db lsls r3, r3, #3 + 8002c70: 490e ldr r1, [pc, #56] ; (8002cac ) + 8002c72: 4313 orrs r3, r2 + 8002c74: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - 800183a: f000 f823 bl 8001884 - 800183e: 4601 mov r1, r0 - 8001840: 4b0c ldr r3, [pc, #48] ; (8001874 ) - 8001842: 689b ldr r3, [r3, #8] - 8001844: 091b lsrs r3, r3, #4 - 8001846: f003 030f and.w r3, r3, #15 - 800184a: 4a0b ldr r2, [pc, #44] ; (8001878 ) - 800184c: 5cd3 ldrb r3, [r2, r3] - 800184e: fa21 f303 lsr.w r3, r1, r3 - 8001852: 4a0a ldr r2, [pc, #40] ; (800187c ) - 8001854: 6013 str r3, [r2, #0] + 8002c76: f000 f821 bl 8002cbc + 8002c7a: 4601 mov r1, r0 + 8002c7c: 4b0b ldr r3, [pc, #44] ; (8002cac ) + 8002c7e: 689b ldr r3, [r3, #8] + 8002c80: 091b lsrs r3, r3, #4 + 8002c82: f003 030f and.w r3, r3, #15 + 8002c86: 4a0a ldr r2, [pc, #40] ; (8002cb0 ) + 8002c88: 5cd3 ldrb r3, [r2, r3] + 8002c8a: fa21 f303 lsr.w r3, r1, r3 + 8002c8e: 4a09 ldr r2, [pc, #36] ; (8002cb4 ) + 8002c90: 6013 str r3, [r2, #0] - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - 8001856: 4b0a ldr r3, [pc, #40] ; (8001880 ) - 8001858: 681b ldr r3, [r3, #0] - 800185a: 4618 mov r0, r3 - 800185c: f7ff f8ac bl 80009b8 - 8001860: 4603 mov r3, r0 - 8001862: 72fb strb r3, [r7, #11] + /* Configure the source of time base considering new system clocks settings */ + HAL_InitTick (uwTickPrio); + 8002c92: 4b09 ldr r3, [pc, #36] ; (8002cb8 ) + 8002c94: 681b ldr r3, [r3, #0] + 8002c96: 4618 mov r0, r3 + 8002c98: f7ff f95e bl 8001f58 - return status; - 8001864: 7afb ldrb r3, [r7, #11] + return HAL_OK; + 8002c9c: 2300 movs r3, #0 } - 8001866: 4618 mov r0, r3 - 8001868: 3710 adds r7, #16 - 800186a: 46bd mov sp, r7 - 800186c: bd80 pop {r7, pc} - 800186e: bf00 nop - 8001870: 40023c00 .word 0x40023c00 - 8001874: 40023800 .word 0x40023800 - 8001878: 080025f0 .word 0x080025f0 - 800187c: 20000000 .word 0x20000000 - 8001880: 20000004 .word 0x20000004 + 8002c9e: 4618 mov r0, r3 + 8002ca0: 3710 adds r7, #16 + 8002ca2: 46bd mov sp, r7 + 8002ca4: bd80 pop {r7, pc} + 8002ca6: bf00 nop + 8002ca8: 40023c00 .word 0x40023c00 + 8002cac: 40023800 .word 0x40023800 + 8002cb0: 08006018 .word 0x08006018 + 8002cb4: 20000014 .word 0x20000014 + 8002cb8: 20000018 .word 0x20000018 -08001884 : - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. +08002cbc : + * * * @retval SYSCLK frequency */ -uint32_t HAL_RCC_GetSysClockFreq(void) +__weak uint32_t HAL_RCC_GetSysClockFreq(void) { - 8001884: b5f0 push {r4, r5, r6, r7, lr} - 8001886: b087 sub sp, #28 - 8001888: af00 add r7, sp, #0 - uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; - - tmpreg = RCC->CFGR; - 800188a: 4b5f ldr r3, [pc, #380] ; (8001a08 ) - 800188c: 689b ldr r3, [r3, #8] - 800188e: 60fb str r3, [r7, #12] + 8002cbc: b5f0 push {r4, r5, r6, r7, lr} + 8002cbe: b085 sub sp, #20 + 8002cc0: af00 add r7, sp, #0 + uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; + 8002cc2: 2300 movs r3, #0 + 8002cc4: 607b str r3, [r7, #4] + 8002cc6: 2300 movs r3, #0 + 8002cc8: 60fb str r3, [r7, #12] + 8002cca: 2300 movs r3, #0 + 8002ccc: 603b str r3, [r7, #0] + uint32_t sysclockfreq = 0U; + 8002cce: 2300 movs r3, #0 + 8002cd0: 60bb str r3, [r7, #8] /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - 8001890: 68fb ldr r3, [r7, #12] - 8001892: f003 030c and.w r3, r3, #12 - 8001896: 2b08 cmp r3, #8 - 8001898: d007 beq.n 80018aa - 800189a: 2b0c cmp r3, #12 - 800189c: d008 beq.n 80018b0 - 800189e: 2b04 cmp r3, #4 - 80018a0: f040 809f bne.w 80019e2 + switch (RCC->CFGR & RCC_CFGR_SWS) + 8002cd2: 4b63 ldr r3, [pc, #396] ; (8002e60 ) + 8002cd4: 689b ldr r3, [r3, #8] + 8002cd6: f003 030c and.w r3, r3, #12 + 8002cda: 2b04 cmp r3, #4 + 8002cdc: d007 beq.n 8002cee + 8002cde: 2b08 cmp r3, #8 + 8002ce0: d008 beq.n 8002cf4 + 8002ce2: 2b00 cmp r3, #0 + 8002ce4: f040 80b4 bne.w 8002e50 { - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - 80018a4: 4b59 ldr r3, [pc, #356] ; (8001a0c ) - 80018a6: 613b str r3, [r7, #16] - break; - 80018a8: e0a9 b.n 80019fe + 8002ce8: 4b5e ldr r3, [pc, #376] ; (8002e64 ) + 8002cea: 60bb str r3, [r7, #8] + break; + 8002cec: e0b3 b.n 8002e56 } - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ + case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; - 80018aa: 4b59 ldr r3, [pc, #356] ; (8001a10 ) - 80018ac: 613b str r3, [r7, #16] + 8002cee: 4b5e ldr r3, [pc, #376] ; (8002e68 ) + 8002cf0: 60bb str r3, [r7, #8] break; - 80018ae: e0a6 b.n 80019fe + 8002cf2: e0b0 b.n 8002e56 } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ + case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { - pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; - 80018b0: 68fb ldr r3, [r7, #12] - 80018b2: 0c9b lsrs r3, r3, #18 - 80018b4: f003 030f and.w r3, r3, #15 - 80018b8: 4a56 ldr r2, [pc, #344] ; (8001a14 ) - 80018ba: 5cd3 ldrb r3, [r2, r3] - 80018bc: 60bb str r3, [r7, #8] - plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; - 80018be: 68fb ldr r3, [r7, #12] - 80018c0: 0d9b lsrs r3, r3, #22 - 80018c2: f003 0303 and.w r3, r3, #3 - 80018c6: 3301 adds r3, #1 - 80018c8: 607b str r3, [r7, #4] - if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - 80018ca: 4b4f ldr r3, [pc, #316] ; (8001a08 ) - 80018cc: 689b ldr r3, [r3, #8] - 80018ce: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 80018d2: 2b00 cmp r3, #0 - 80018d4: d041 beq.n 800195a + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + 8002cf4: 4b5a ldr r3, [pc, #360] ; (8002e60 ) + 8002cf6: 685b ldr r3, [r3, #4] + 8002cf8: f003 033f and.w r3, r3, #63 ; 0x3f + 8002cfc: 607b str r3, [r7, #4] + if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) + 8002cfe: 4b58 ldr r3, [pc, #352] ; (8002e60 ) + 8002d00: 685b ldr r3, [r3, #4] + 8002d02: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8002d06: 2b00 cmp r3, #0 + 8002d08: d04a beq.n 8002da0 { /* HSE used as PLL clock source */ - pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); - 80018d6: 68bb ldr r3, [r7, #8] - 80018d8: 461d mov r5, r3 - 80018da: f04f 0600 mov.w r6, #0 - 80018de: 4629 mov r1, r5 - 80018e0: 4632 mov r2, r6 - 80018e2: f04f 0300 mov.w r3, #0 - 80018e6: f04f 0400 mov.w r4, #0 - 80018ea: 0154 lsls r4, r2, #5 - 80018ec: ea44 64d1 orr.w r4, r4, r1, lsr #27 - 80018f0: 014b lsls r3, r1, #5 - 80018f2: 4619 mov r1, r3 - 80018f4: 4622 mov r2, r4 - 80018f6: 1b49 subs r1, r1, r5 - 80018f8: eb62 0206 sbc.w r2, r2, r6 - 80018fc: f04f 0300 mov.w r3, #0 - 8001900: f04f 0400 mov.w r4, #0 - 8001904: 0194 lsls r4, r2, #6 - 8001906: ea44 6491 orr.w r4, r4, r1, lsr #26 - 800190a: 018b lsls r3, r1, #6 - 800190c: 1a5b subs r3, r3, r1 - 800190e: eb64 0402 sbc.w r4, r4, r2 - 8001912: f04f 0100 mov.w r1, #0 - 8001916: f04f 0200 mov.w r2, #0 - 800191a: 00e2 lsls r2, r4, #3 - 800191c: ea42 7253 orr.w r2, r2, r3, lsr #29 - 8001920: 00d9 lsls r1, r3, #3 - 8001922: 460b mov r3, r1 - 8001924: 4614 mov r4, r2 - 8001926: 195b adds r3, r3, r5 - 8001928: eb44 0406 adc.w r4, r4, r6 - 800192c: f04f 0100 mov.w r1, #0 - 8001930: f04f 0200 mov.w r2, #0 - 8001934: 0262 lsls r2, r4, #9 - 8001936: ea42 52d3 orr.w r2, r2, r3, lsr #23 - 800193a: 0259 lsls r1, r3, #9 - 800193c: 460b mov r3, r1 - 800193e: 4614 mov r4, r2 - 8001940: 4618 mov r0, r3 - 8001942: 4621 mov r1, r4 - 8001944: 687b ldr r3, [r7, #4] - 8001946: f04f 0400 mov.w r4, #0 - 800194a: 461a mov r2, r3 - 800194c: 4623 mov r3, r4 - 800194e: f7fe fc15 bl 800017c <__aeabi_uldivmod> - 8001952: 4603 mov r3, r0 - 8001954: 460c mov r4, r1 - 8001956: 617b str r3, [r7, #20] - 8001958: e040 b.n 80019dc + pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002d0a: 4b55 ldr r3, [pc, #340] ; (8002e60 ) + 8002d0c: 685b ldr r3, [r3, #4] + 8002d0e: 099b lsrs r3, r3, #6 + 8002d10: f04f 0400 mov.w r4, #0 + 8002d14: f240 11ff movw r1, #511 ; 0x1ff + 8002d18: f04f 0200 mov.w r2, #0 + 8002d1c: ea03 0501 and.w r5, r3, r1 + 8002d20: ea04 0602 and.w r6, r4, r2 + 8002d24: 4629 mov r1, r5 + 8002d26: 4632 mov r2, r6 + 8002d28: f04f 0300 mov.w r3, #0 + 8002d2c: f04f 0400 mov.w r4, #0 + 8002d30: 0154 lsls r4, r2, #5 + 8002d32: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 8002d36: 014b lsls r3, r1, #5 + 8002d38: 4619 mov r1, r3 + 8002d3a: 4622 mov r2, r4 + 8002d3c: 1b49 subs r1, r1, r5 + 8002d3e: eb62 0206 sbc.w r2, r2, r6 + 8002d42: f04f 0300 mov.w r3, #0 + 8002d46: f04f 0400 mov.w r4, #0 + 8002d4a: 0194 lsls r4, r2, #6 + 8002d4c: ea44 6491 orr.w r4, r4, r1, lsr #26 + 8002d50: 018b lsls r3, r1, #6 + 8002d52: 1a5b subs r3, r3, r1 + 8002d54: eb64 0402 sbc.w r4, r4, r2 + 8002d58: f04f 0100 mov.w r1, #0 + 8002d5c: f04f 0200 mov.w r2, #0 + 8002d60: 00e2 lsls r2, r4, #3 + 8002d62: ea42 7253 orr.w r2, r2, r3, lsr #29 + 8002d66: 00d9 lsls r1, r3, #3 + 8002d68: 460b mov r3, r1 + 8002d6a: 4614 mov r4, r2 + 8002d6c: 195b adds r3, r3, r5 + 8002d6e: eb44 0406 adc.w r4, r4, r6 + 8002d72: f04f 0100 mov.w r1, #0 + 8002d76: f04f 0200 mov.w r2, #0 + 8002d7a: 0262 lsls r2, r4, #9 + 8002d7c: ea42 52d3 orr.w r2, r2, r3, lsr #23 + 8002d80: 0259 lsls r1, r3, #9 + 8002d82: 460b mov r3, r1 + 8002d84: 4614 mov r4, r2 + 8002d86: 4618 mov r0, r3 + 8002d88: 4621 mov r1, r4 + 8002d8a: 687b ldr r3, [r7, #4] + 8002d8c: f04f 0400 mov.w r4, #0 + 8002d90: 461a mov r2, r3 + 8002d92: 4623 mov r3, r4 + 8002d94: f7fd febc bl 8000b10 <__aeabi_uldivmod> + 8002d98: 4603 mov r3, r0 + 8002d9a: 460c mov r4, r1 + 8002d9c: 60fb str r3, [r7, #12] + 8002d9e: e049 b.n 8002e34 } else { /* HSI used as PLL clock source */ - pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); - 800195a: 68bb ldr r3, [r7, #8] - 800195c: 461d mov r5, r3 - 800195e: f04f 0600 mov.w r6, #0 - 8001962: 4629 mov r1, r5 - 8001964: 4632 mov r2, r6 - 8001966: f04f 0300 mov.w r3, #0 - 800196a: f04f 0400 mov.w r4, #0 - 800196e: 0154 lsls r4, r2, #5 - 8001970: ea44 64d1 orr.w r4, r4, r1, lsr #27 - 8001974: 014b lsls r3, r1, #5 - 8001976: 4619 mov r1, r3 - 8001978: 4622 mov r2, r4 - 800197a: 1b49 subs r1, r1, r5 - 800197c: eb62 0206 sbc.w r2, r2, r6 - 8001980: f04f 0300 mov.w r3, #0 - 8001984: f04f 0400 mov.w r4, #0 - 8001988: 0194 lsls r4, r2, #6 - 800198a: ea44 6491 orr.w r4, r4, r1, lsr #26 - 800198e: 018b lsls r3, r1, #6 - 8001990: 1a5b subs r3, r3, r1 - 8001992: eb64 0402 sbc.w r4, r4, r2 - 8001996: f04f 0100 mov.w r1, #0 - 800199a: f04f 0200 mov.w r2, #0 - 800199e: 00e2 lsls r2, r4, #3 - 80019a0: ea42 7253 orr.w r2, r2, r3, lsr #29 - 80019a4: 00d9 lsls r1, r3, #3 - 80019a6: 460b mov r3, r1 - 80019a8: 4614 mov r4, r2 - 80019aa: 195b adds r3, r3, r5 - 80019ac: eb44 0406 adc.w r4, r4, r6 - 80019b0: f04f 0100 mov.w r1, #0 - 80019b4: f04f 0200 mov.w r2, #0 - 80019b8: 02a2 lsls r2, r4, #10 - 80019ba: ea42 5293 orr.w r2, r2, r3, lsr #22 - 80019be: 0299 lsls r1, r3, #10 - 80019c0: 460b mov r3, r1 - 80019c2: 4614 mov r4, r2 - 80019c4: 4618 mov r0, r3 - 80019c6: 4621 mov r1, r4 - 80019c8: 687b ldr r3, [r7, #4] - 80019ca: f04f 0400 mov.w r4, #0 - 80019ce: 461a mov r2, r3 - 80019d0: 4623 mov r3, r4 - 80019d2: f7fe fbd3 bl 800017c <__aeabi_uldivmod> - 80019d6: 4603 mov r3, r0 - 80019d8: 460c mov r4, r1 - 80019da: 617b str r3, [r7, #20] + pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + 8002da0: 4b2f ldr r3, [pc, #188] ; (8002e60 ) + 8002da2: 685b ldr r3, [r3, #4] + 8002da4: 099b lsrs r3, r3, #6 + 8002da6: f04f 0400 mov.w r4, #0 + 8002daa: f240 11ff movw r1, #511 ; 0x1ff + 8002dae: f04f 0200 mov.w r2, #0 + 8002db2: ea03 0501 and.w r5, r3, r1 + 8002db6: ea04 0602 and.w r6, r4, r2 + 8002dba: 4629 mov r1, r5 + 8002dbc: 4632 mov r2, r6 + 8002dbe: f04f 0300 mov.w r3, #0 + 8002dc2: f04f 0400 mov.w r4, #0 + 8002dc6: 0154 lsls r4, r2, #5 + 8002dc8: ea44 64d1 orr.w r4, r4, r1, lsr #27 + 8002dcc: 014b lsls r3, r1, #5 + 8002dce: 4619 mov r1, r3 + 8002dd0: 4622 mov r2, r4 + 8002dd2: 1b49 subs r1, r1, r5 + 8002dd4: eb62 0206 sbc.w r2, r2, r6 + 8002dd8: f04f 0300 mov.w r3, #0 + 8002ddc: f04f 0400 mov.w r4, #0 + 8002de0: 0194 lsls r4, r2, #6 + 8002de2: ea44 6491 orr.w r4, r4, r1, lsr #26 + 8002de6: 018b lsls r3, r1, #6 + 8002de8: 1a5b subs r3, r3, r1 + 8002dea: eb64 0402 sbc.w r4, r4, r2 + 8002dee: f04f 0100 mov.w r1, #0 + 8002df2: f04f 0200 mov.w r2, #0 + 8002df6: 00e2 lsls r2, r4, #3 + 8002df8: ea42 7253 orr.w r2, r2, r3, lsr #29 + 8002dfc: 00d9 lsls r1, r3, #3 + 8002dfe: 460b mov r3, r1 + 8002e00: 4614 mov r4, r2 + 8002e02: 195b adds r3, r3, r5 + 8002e04: eb44 0406 adc.w r4, r4, r6 + 8002e08: f04f 0100 mov.w r1, #0 + 8002e0c: f04f 0200 mov.w r2, #0 + 8002e10: 02a2 lsls r2, r4, #10 + 8002e12: ea42 5293 orr.w r2, r2, r3, lsr #22 + 8002e16: 0299 lsls r1, r3, #10 + 8002e18: 460b mov r3, r1 + 8002e1a: 4614 mov r4, r2 + 8002e1c: 4618 mov r0, r3 + 8002e1e: 4621 mov r1, r4 + 8002e20: 687b ldr r3, [r7, #4] + 8002e22: f04f 0400 mov.w r4, #0 + 8002e26: 461a mov r2, r3 + 8002e28: 4623 mov r3, r4 + 8002e2a: f7fd fe71 bl 8000b10 <__aeabi_uldivmod> + 8002e2e: 4603 mov r3, r0 + 8002e30: 460c mov r4, r1 + 8002e32: 60fb str r3, [r7, #12] } - sysclockfreq = pllvco; - 80019dc: 697b ldr r3, [r7, #20] - 80019de: 613b str r3, [r7, #16] + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); + 8002e34: 4b0a ldr r3, [pc, #40] ; (8002e60 ) + 8002e36: 685b ldr r3, [r3, #4] + 8002e38: 0c1b lsrs r3, r3, #16 + 8002e3a: f003 0303 and.w r3, r3, #3 + 8002e3e: 3301 adds r3, #1 + 8002e40: 005b lsls r3, r3, #1 + 8002e42: 603b str r3, [r7, #0] + + sysclockfreq = pllvco/pllp; + 8002e44: 68fa ldr r2, [r7, #12] + 8002e46: 683b ldr r3, [r7, #0] + 8002e48: fbb2 f3f3 udiv r3, r2, r3 + 8002e4c: 60bb str r3, [r7, #8] break; - 80019e0: e00d b.n 80019fe + 8002e4e: e002 b.n 8002e56 } - case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ - default: /* MSI used as system clock */ + default: { - msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; - 80019e2: 4b09 ldr r3, [pc, #36] ; (8001a08 ) - 80019e4: 685b ldr r3, [r3, #4] - 80019e6: 0b5b lsrs r3, r3, #13 - 80019e8: f003 0307 and.w r3, r3, #7 - 80019ec: 603b str r3, [r7, #0] - sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); - 80019ee: 683b ldr r3, [r7, #0] - 80019f0: 3301 adds r3, #1 - 80019f2: f44f 4200 mov.w r2, #32768 ; 0x8000 - 80019f6: fa02 f303 lsl.w r3, r2, r3 - 80019fa: 613b str r3, [r7, #16] + sysclockfreq = HSI_VALUE; + 8002e50: 4b04 ldr r3, [pc, #16] ; (8002e64 ) + 8002e52: 60bb str r3, [r7, #8] break; - 80019fc: bf00 nop + 8002e54: bf00 nop } } return sysclockfreq; - 80019fe: 693b ldr r3, [r7, #16] + 8002e56: 68bb ldr r3, [r7, #8] } - 8001a00: 4618 mov r0, r3 - 8001a02: 371c adds r7, #28 - 8001a04: 46bd mov sp, r7 - 8001a06: bdf0 pop {r4, r5, r6, r7, pc} - 8001a08: 40023800 .word 0x40023800 - 8001a0c: 00f42400 .word 0x00f42400 - 8001a10: 007a1200 .word 0x007a1200 - 8001a14: 080025e4 .word 0x080025e4 + 8002e58: 4618 mov r0, r3 + 8002e5a: 3714 adds r7, #20 + 8002e5c: 46bd mov sp, r7 + 8002e5e: bdf0 pop {r4, r5, r6, r7, pc} + 8002e60: 40023800 .word 0x40023800 + 8002e64: 00f42400 .word 0x00f42400 + 8002e68: 007a1200 .word 0x007a1200 -08001a18 : +08002e6c : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8001a18: b480 push {r7} - 8001a1a: af00 add r7, sp, #0 + 8002e6c: b480 push {r7} + 8002e6e: af00 add r7, sp, #0 return SystemCoreClock; - 8001a1c: 4b02 ldr r3, [pc, #8] ; (8001a28 ) - 8001a1e: 681b ldr r3, [r3, #0] + 8002e70: 4b03 ldr r3, [pc, #12] ; (8002e80 ) + 8002e72: 681b ldr r3, [r3, #0] } - 8001a20: 4618 mov r0, r3 - 8001a22: 46bd mov sp, r7 - 8001a24: bc80 pop {r7} - 8001a26: 4770 bx lr - 8001a28: 20000000 .word 0x20000000 + 8002e74: 4618 mov r0, r3 + 8002e76: 46bd mov sp, r7 + 8002e78: f85d 7b04 ldr.w r7, [sp], #4 + 8002e7c: 4770 bx lr + 8002e7e: bf00 nop + 8002e80: 20000014 .word 0x20000014 -08001a2c : +08002e84 : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8001a2c: b580 push {r7, lr} - 8001a2e: af00 add r7, sp, #0 + 8002e84: b580 push {r7, lr} + 8002e86: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); - 8001a30: f7ff fff2 bl 8001a18 - 8001a34: 4601 mov r1, r0 - 8001a36: 4b05 ldr r3, [pc, #20] ; (8001a4c ) - 8001a38: 689b ldr r3, [r3, #8] - 8001a3a: 0a1b lsrs r3, r3, #8 - 8001a3c: f003 0307 and.w r3, r3, #7 - 8001a40: 4a03 ldr r2, [pc, #12] ; (8001a50 ) - 8001a42: 5cd3 ldrb r3, [r2, r3] - 8001a44: fa21 f303 lsr.w r3, r1, r3 + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); + 8002e88: f7ff fff0 bl 8002e6c + 8002e8c: 4601 mov r1, r0 + 8002e8e: 4b05 ldr r3, [pc, #20] ; (8002ea4 ) + 8002e90: 689b ldr r3, [r3, #8] + 8002e92: 0a9b lsrs r3, r3, #10 + 8002e94: f003 0307 and.w r3, r3, #7 + 8002e98: 4a03 ldr r2, [pc, #12] ; (8002ea8 ) + 8002e9a: 5cd3 ldrb r3, [r2, r3] + 8002e9c: fa21 f303 lsr.w r3, r1, r3 } - 8001a48: 4618 mov r0, r3 - 8001a4a: bd80 pop {r7, pc} - 8001a4c: 40023800 .word 0x40023800 - 8001a50: 08002600 .word 0x08002600 + 8002ea0: 4618 mov r0, r3 + 8002ea2: bd80 pop {r7, pc} + 8002ea4: 40023800 .word 0x40023800 + 8002ea8: 08006028 .word 0x08006028 -08001a54 : +08002eac : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 8001a54: b580 push {r7, lr} - 8001a56: af00 add r7, sp, #0 + 8002eac: b580 push {r7, lr} + 8002eae: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); - 8001a58: f7ff ffde bl 8001a18 - 8001a5c: 4601 mov r1, r0 - 8001a5e: 4b05 ldr r3, [pc, #20] ; (8001a74 ) - 8001a60: 689b ldr r3, [r3, #8] - 8001a62: 0adb lsrs r3, r3, #11 - 8001a64: f003 0307 and.w r3, r3, #7 - 8001a68: 4a03 ldr r2, [pc, #12] ; (8001a78 ) - 8001a6a: 5cd3 ldrb r3, [r2, r3] - 8001a6c: fa21 f303 lsr.w r3, r1, r3 + return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); + 8002eb0: f7ff ffdc bl 8002e6c + 8002eb4: 4601 mov r1, r0 + 8002eb6: 4b05 ldr r3, [pc, #20] ; (8002ecc ) + 8002eb8: 689b ldr r3, [r3, #8] + 8002eba: 0b5b lsrs r3, r3, #13 + 8002ebc: f003 0307 and.w r3, r3, #7 + 8002ec0: 4a03 ldr r2, [pc, #12] ; (8002ed0 ) + 8002ec2: 5cd3 ldrb r3, [r2, r3] + 8002ec4: fa21 f303 lsr.w r3, r1, r3 } - 8001a70: 4618 mov r0, r3 - 8001a72: bd80 pop {r7, pc} - 8001a74: 40023800 .word 0x40023800 - 8001a78: 08002600 .word 0x08002600 + 8002ec8: 4618 mov r0, r3 + 8002eca: bd80 pop {r7, pc} + 8002ecc: 40023800 .word 0x40023800 + 8002ed0: 08006028 .word 0x08006028 -08001a7c : - voltage range - * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 +08002ed4 : + * domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset + * * @retval HAL status */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) -{ - 8001a7c: b480 push {r7} - 8001a7e: b087 sub sp, #28 - 8001a80: af00 add r7, sp, #0 - 8001a82: 6078 str r0, [r7, #4] - uint32_t vos; - uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - 8001a84: 2300 movs r3, #0 - 8001a86: 613b str r3, [r7, #16] - - /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ - if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) - 8001a88: 4b29 ldr r3, [pc, #164] ; (8001b30 ) - 8001a8a: 689b ldr r3, [r3, #8] - 8001a8c: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8001a90: 2b00 cmp r3, #0 - 8001a92: d12c bne.n 8001aee - { - if(__HAL_RCC_PWR_IS_CLK_ENABLED()) - 8001a94: 4b26 ldr r3, [pc, #152] ; (8001b30 ) - 8001a96: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001a98: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8001a9c: 2b00 cmp r3, #0 - 8001a9e: d005 beq.n 8001aac - { - vos = READ_BIT(PWR->CR, PWR_CR_VOS); - 8001aa0: 4b24 ldr r3, [pc, #144] ; (8001b34 ) - 8001aa2: 681b ldr r3, [r3, #0] - 8001aa4: f403 53c0 and.w r3, r3, #6144 ; 0x1800 - 8001aa8: 617b str r3, [r7, #20] - 8001aaa: e016 b.n 8001ada - } - else - { - __HAL_RCC_PWR_CLK_ENABLE(); - 8001aac: 4b20 ldr r3, [pc, #128] ; (8001b30 ) - 8001aae: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001ab0: 4a1f ldr r2, [pc, #124] ; (8001b30 ) - 8001ab2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8001ab6: 6253 str r3, [r2, #36] ; 0x24 - 8001ab8: 4b1d ldr r3, [pc, #116] ; (8001b30 ) - 8001aba: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001abc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8001ac0: 60fb str r3, [r7, #12] - 8001ac2: 68fb ldr r3, [r7, #12] - vos = READ_BIT(PWR->CR, PWR_CR_VOS); - 8001ac4: 4b1b ldr r3, [pc, #108] ; (8001b34 ) - 8001ac6: 681b ldr r3, [r3, #0] - 8001ac8: f403 53c0 and.w r3, r3, #6144 ; 0x1800 - 8001acc: 617b str r3, [r7, #20] - __HAL_RCC_PWR_CLK_DISABLE(); - 8001ace: 4b18 ldr r3, [pc, #96] ; (8001b30 ) - 8001ad0: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001ad2: 4a17 ldr r2, [pc, #92] ; (8001b30 ) - 8001ad4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8001ad8: 6253 str r3, [r2, #36] ; 0x24 - } - - /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ - if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) - 8001ada: 697b ldr r3, [r7, #20] - 8001adc: f5b3 5fc0 cmp.w r3, #6144 ; 0x1800 - 8001ae0: d105 bne.n 8001aee - 8001ae2: 687b ldr r3, [r7, #4] - 8001ae4: f5b3 4f40 cmp.w r3, #49152 ; 0xc000 - 8001ae8: d101 bne.n 8001aee - { - latency = FLASH_LATENCY_1; /* 1WS */ - 8001aea: 2301 movs r3, #1 - 8001aec: 613b str r3, [r7, #16] - } - } - - __HAL_FLASH_SET_LATENCY(latency); - 8001aee: 693b ldr r3, [r7, #16] - 8001af0: 2b01 cmp r3, #1 - 8001af2: d105 bne.n 8001b00 - 8001af4: 4b10 ldr r3, [pc, #64] ; (8001b38 ) - 8001af6: 681b ldr r3, [r3, #0] - 8001af8: 4a0f ldr r2, [pc, #60] ; (8001b38 ) - 8001afa: f043 0304 orr.w r3, r3, #4 - 8001afe: 6013 str r3, [r2, #0] - 8001b00: 4b0d ldr r3, [pc, #52] ; (8001b38 ) - 8001b02: 681b ldr r3, [r3, #0] - 8001b04: f023 0201 bic.w r2, r3, #1 - 8001b08: 490b ldr r1, [pc, #44] ; (8001b38 ) - 8001b0a: 693b ldr r3, [r7, #16] - 8001b0c: 4313 orrs r3, r2 - 8001b0e: 600b str r3, [r1, #0] - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != latency) - 8001b10: 4b09 ldr r3, [pc, #36] ; (8001b38 ) - 8001b12: 681b ldr r3, [r3, #0] - 8001b14: f003 0301 and.w r3, r3, #1 - 8001b18: 693a ldr r2, [r7, #16] - 8001b1a: 429a cmp r2, r3 - 8001b1c: d001 beq.n 8001b22 - { - return HAL_ERROR; - 8001b1e: 2301 movs r3, #1 - 8001b20: e000 b.n 8001b24 - } - - return HAL_OK; - 8001b22: 2300 movs r3, #0 -} - 8001b24: 4618 mov r0, r3 - 8001b26: 371c adds r7, #28 - 8001b28: 46bd mov sp, r7 - 8001b2a: bc80 pop {r7} - 8001b2c: 4770 bx lr - 8001b2e: bf00 nop - 8001b30: 40023800 .word 0x40023800 - 8001b34: 40007000 .word 0x40007000 - 8001b38: 40023c00 .word 0x40023c00 - -08001b3c : - * @retval HAL status - * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() - * to possibly update HSE divider. - */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { - 8001b3c: b580 push {r7, lr} - 8001b3e: b086 sub sp, #24 - 8001b40: af00 add r7, sp, #0 - 8001b42: 6078 str r0, [r7, #4] + 8002ed4: b580 push {r7, lr} + 8002ed6: b086 sub sp, #24 + 8002ed8: af00 add r7, sp, #0 + 8002eda: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8002edc: 2300 movs r3, #0 + 8002ede: 617b str r3, [r7, #20] + uint32_t tmpreg1 = 0U; + 8002ee0: 2300 movs r3, #0 + 8002ee2: 613b str r3, [r7, #16] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - /*------------------------------- RTC/LCD Configuration ------------------------*/ - if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - 8001b44: 687b ldr r3, [r7, #4] - 8001b46: 681b ldr r3, [r3, #0] - 8001b48: f003 0301 and.w r3, r3, #1 - 8001b4c: 2b00 cmp r3, #0 - 8001b4e: d106 bne.n 8001b5e -#if defined(LCD) - || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) - 8001b50: 687b ldr r3, [r7, #4] - 8001b52: 681b ldr r3, [r3, #0] - 8001b54: f003 0302 and.w r3, r3, #2 - 8001b58: 2b00 cmp r3, #0 - 8001b5a: f000 80c6 beq.w 8001cea + /*---------------------------- I2S configuration ---------------------------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + 8002ee4: 687b ldr r3, [r7, #4] + 8002ee6: 681b ldr r3, [r3, #0] + 8002ee8: f003 0301 and.w r3, r3, #1 + 8002eec: 2b00 cmp r3, #0 + 8002eee: d105 bne.n 8002efc + (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + 8002ef0: 687b ldr r3, [r7, #4] + 8002ef2: 681b ldr r3, [r3, #0] + 8002ef4: f003 0304 and.w r3, r3, #4 + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || + 8002ef8: 2b00 cmp r3, #0 + 8002efa: d035 beq.n 8002f68 + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); +#if defined(STM32F411xE) + assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM)); +#endif /* STM32F411xE */ + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + 8002efc: 4b67 ldr r3, [pc, #412] ; (800309c ) + 8002efe: 2200 movs r2, #0 + 8002f00: 601a str r2, [r3, #0] + /* Get tick */ + tickstart = HAL_GetTick(); + 8002f02: f7ff f86d bl 8001fe0 + 8002f06: 6178 str r0, [r7, #20] + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8002f08: e008 b.n 8002f1c { - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); - } -#endif /* LCD */ - - FlagStatus pwrclkchanged = RESET; - 8001b5e: 2300 movs r3, #0 - 8001b60: 75fb strb r3, [r7, #23] - - /* As soon as function is called to change RTC clock source, activation of the - power domain is done. */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 8001b62: 4b64 ldr r3, [pc, #400] ; (8001cf4 ) - 8001b64: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001b66: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8001b6a: 2b00 cmp r3, #0 - 8001b6c: d10d bne.n 8001b8a - { - __HAL_RCC_PWR_CLK_ENABLE(); - 8001b6e: 4b61 ldr r3, [pc, #388] ; (8001cf4 ) - 8001b70: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001b72: 4a60 ldr r2, [pc, #384] ; (8001cf4 ) - 8001b74: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8001b78: 6253 str r3, [r2, #36] ; 0x24 - 8001b7a: 4b5e ldr r3, [pc, #376] ; (8001cf4 ) - 8001b7c: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001b7e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8001b82: 60bb str r3, [r7, #8] - 8001b84: 68bb ldr r3, [r7, #8] - pwrclkchanged = SET; - 8001b86: 2301 movs r3, #1 - 8001b88: 75fb strb r3, [r7, #23] - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001b8a: 4b5b ldr r3, [pc, #364] ; (8001cf8 ) - 8001b8c: 681b ldr r3, [r3, #0] - 8001b8e: f403 7380 and.w r3, r3, #256 ; 0x100 - 8001b92: 2b00 cmp r3, #0 - 8001b94: d118 bne.n 8001bc8 - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - 8001b96: 4b58 ldr r3, [pc, #352] ; (8001cf8 ) - 8001b98: 681b ldr r3, [r3, #0] - 8001b9a: 4a57 ldr r2, [pc, #348] ; (8001cf8 ) - 8001b9c: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8001ba0: 6013 str r3, [r2, #0] - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - 8001ba2: f7fe ff55 bl 8000a50 - 8001ba6: 6138 str r0, [r7, #16] - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001ba8: e008 b.n 8001bbc + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 8002f0a: f7ff f869 bl 8001fe0 + 8002f0e: 4602 mov r2, r0 + 8002f10: 697b ldr r3, [r7, #20] + 8002f12: 1ad3 subs r3, r2, r3 + 8002f14: 2b02 cmp r3, #2 + 8002f16: d901 bls.n 8002f1c { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 8001baa: f7fe ff51 bl 8000a50 - 8001bae: 4602 mov r2, r0 - 8001bb0: 693b ldr r3, [r7, #16] - 8001bb2: 1ad3 subs r3, r2, r3 - 8001bb4: 2b64 cmp r3, #100 ; 0x64 - 8001bb6: d901 bls.n 8001bbc - { - return HAL_TIMEOUT; - 8001bb8: 2303 movs r3, #3 - 8001bba: e097 b.n 8001cec - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001bbc: 4b4e ldr r3, [pc, #312] ; (8001cf8 ) - 8001bbe: 681b ldr r3, [r3, #0] - 8001bc0: f403 7380 and.w r3, r3, #256 ; 0x100 - 8001bc4: 2b00 cmp r3, #0 - 8001bc6: d0f0 beq.n 8001baa - } + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8002f18: 2303 movs r3, #3 + 8002f1a: e0ba b.n 8003092 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + 8002f1c: 4b60 ldr r3, [pc, #384] ; (80030a0 ) + 8002f1e: 681b ldr r3, [r3, #0] + 8002f20: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8002f24: 2b00 cmp r3, #0 + 8002f26: d1f0 bne.n 8002f0a + __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR); +#else + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR); + 8002f28: 687b ldr r3, [r7, #4] + 8002f2a: 685b ldr r3, [r3, #4] + 8002f2c: 019a lsls r2, r3, #6 + 8002f2e: 687b ldr r3, [r7, #4] + 8002f30: 689b ldr r3, [r3, #8] + 8002f32: 071b lsls r3, r3, #28 + 8002f34: 495a ldr r1, [pc, #360] ; (80030a0 ) + 8002f36: 4313 orrs r3, r2 + 8002f38: f8c1 3084 str.w r3, [r1, #132] ; 0x84 +#endif /* STM32F411xE */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + 8002f3c: 4b57 ldr r3, [pc, #348] ; (800309c ) + 8002f3e: 2201 movs r2, #1 + 8002f40: 601a str r2, [r3, #0] + /* Get tick */ + tickstart = HAL_GetTick(); + 8002f42: f7ff f84d bl 8001fe0 + 8002f46: 6178 str r0, [r7, #20] + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8002f48: e008 b.n 8002f5c + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + 8002f4a: f7ff f849 bl 8001fe0 + 8002f4e: 4602 mov r2, r0 + 8002f50: 697b ldr r3, [r7, #20] + 8002f52: 1ad3 subs r3, r2, r3 + 8002f54: 2b02 cmp r3, #2 + 8002f56: d901 bls.n 8002f5c + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + 8002f58: 2303 movs r3, #3 + 8002f5a: e09a b.n 8003092 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + 8002f5c: 4b50 ldr r3, [pc, #320] ; (80030a0 ) + 8002f5e: 681b ldr r3, [r3, #0] + 8002f60: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 + 8002f64: 2b00 cmp r3, #0 + 8002f66: d0f0 beq.n 8002f4a } } + } - /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ - temp_reg = (RCC->CR & RCC_CR_RTCPRE); - 8001bc8: 4b4a ldr r3, [pc, #296] ; (8001cf4 ) - 8001bca: 681b ldr r3, [r3, #0] - 8001bcc: f003 43c0 and.w r3, r3, #1610612736 ; 0x60000000 - 8001bd0: 60fb str r3, [r7, #12] - if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) - 8001bd2: 687b ldr r3, [r7, #4] - 8001bd4: 685b ldr r3, [r3, #4] - 8001bd6: f003 43c0 and.w r3, r3, #1610612736 ; 0x60000000 - 8001bda: 68fa ldr r2, [r7, #12] - 8001bdc: 429a cmp r2, r3 - 8001bde: d106 bne.n 8001bee -#if defined (LCD) - || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) - 8001be0: 687b ldr r3, [r7, #4] - 8001be2: 689b ldr r3, [r3, #8] - 8001be4: f003 43c0 and.w r3, r3, #1610612736 ; 0x60000000 - 8001be8: 68fa ldr r2, [r7, #12] - 8001bea: 429a cmp r2, r3 - 8001bec: d00f beq.n 8001c0e -#endif /* LCD */ - ) - { /* Check HSE State */ - if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) - 8001bee: 687b ldr r3, [r7, #4] - 8001bf0: 685b ldr r3, [r3, #4] - 8001bf2: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8001bf6: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 - 8001bfa: d108 bne.n 8001c0e + /*---------------------------- RTC configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + 8002f68: 687b ldr r3, [r7, #4] + 8002f6a: 681b ldr r3, [r3, #0] + 8002f6c: f003 0302 and.w r3, r3, #2 + 8002f70: 2b00 cmp r3, #0 + 8002f72: f000 8083 beq.w 800307c + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + 8002f76: 2300 movs r3, #0 + 8002f78: 60fb str r3, [r7, #12] + 8002f7a: 4b49 ldr r3, [pc, #292] ; (80030a0 ) + 8002f7c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002f7e: 4a48 ldr r2, [pc, #288] ; (80030a0 ) + 8002f80: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002f84: 6413 str r3, [r2, #64] ; 0x40 + 8002f86: 4b46 ldr r3, [pc, #280] ; (80030a0 ) + 8002f88: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002f8a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8002f8e: 60fb str r3, [r7, #12] + 8002f90: 68fb ldr r3, [r7, #12] + + /* Enable write access to Backup domain */ + PWR->CR |= PWR_CR_DBP; + 8002f92: 4b44 ldr r3, [pc, #272] ; (80030a4 ) + 8002f94: 681b ldr r3, [r3, #0] + 8002f96: 4a43 ldr r2, [pc, #268] ; (80030a4 ) + 8002f98: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002f9c: 6013 str r3, [r2, #0] + + /* Get tick */ + tickstart = HAL_GetTick(); + 8002f9e: f7ff f81f bl 8001fe0 + 8002fa2: 6178 str r0, [r7, #20] + + while((PWR->CR & PWR_CR_DBP) == RESET) + 8002fa4: e008 b.n 8002fb8 + { + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) + 8002fa6: f7ff f81b bl 8001fe0 + 8002faa: 4602 mov r2, r0 + 8002fac: 697b ldr r3, [r7, #20] + 8002fae: 1ad3 subs r3, r2, r3 + 8002fb0: 2b02 cmp r3, #2 + 8002fb2: d901 bls.n 8002fb8 { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - 8001bfc: 4b3d ldr r3, [pc, #244] ; (8001cf4 ) - 8001bfe: 681b ldr r3, [r3, #0] - 8001c00: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001c04: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 - 8001c08: d101 bne.n 8001c0e - { - /* To update HSE divider, first switch-OFF HSE clock oscillator*/ - return HAL_ERROR; - 8001c0a: 2301 movs r3, #1 - 8001c0c: e06e b.n 8001cec - } + return HAL_TIMEOUT; + 8002fb4: 2303 movs r3, #3 + 8002fb6: e06c b.n 8003092 + while((PWR->CR & PWR_CR_DBP) == RESET) + 8002fb8: 4b3a ldr r3, [pc, #232] ; (80030a4 ) + 8002fba: 681b ldr r3, [r3, #0] + 8002fbc: f403 7380 and.w r3, r3, #256 ; 0x100 + 8002fc0: 2b00 cmp r3, #0 + 8002fc2: d0f0 beq.n 8002fa6 } } - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); - 8001c0e: 4b39 ldr r3, [pc, #228] ; (8001cf4 ) - 8001c10: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001c12: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8001c16: 60fb str r3, [r7, #12] - - if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ - 8001c18: 68fb ldr r3, [r7, #12] - 8001c1a: 2b00 cmp r3, #0 - 8001c1c: d041 beq.n 8001ca2 - 8001c1e: 687b ldr r3, [r7, #4] - 8001c20: 685b ldr r3, [r3, #4] - 8001c22: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8001c26: 68fa ldr r2, [r7, #12] - 8001c28: 429a cmp r2, r3 - 8001c2a: d005 beq.n 8001c38 - && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) - 8001c2c: 687b ldr r3, [r7, #4] - 8001c2e: 681b ldr r3, [r3, #0] - 8001c30: f003 0301 and.w r3, r3, #1 - 8001c34: 2b00 cmp r3, #0 - 8001c36: d10c bne.n 8001c52 -#if defined(LCD) - || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ - 8001c38: 687b ldr r3, [r7, #4] - 8001c3a: 689b ldr r3, [r3, #8] - 8001c3c: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8001c40: 68fa ldr r2, [r7, #12] - 8001c42: 429a cmp r2, r3 - 8001c44: d02d beq.n 8001ca2 - && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) - 8001c46: 687b ldr r3, [r7, #4] - 8001c48: 681b ldr r3, [r3, #0] - 8001c4a: f003 0302 and.w r3, r3, #2 - 8001c4e: 2b00 cmp r3, #0 - 8001c50: d027 beq.n 8001ca2 -#endif /* LCD */ - )) + tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL); + 8002fc4: 4b36 ldr r3, [pc, #216] ; (80030a0 ) + 8002fc6: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002fc8: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002fcc: 613b str r3, [r7, #16] + if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + 8002fce: 693b ldr r3, [r7, #16] + 8002fd0: 2b00 cmp r3, #0 + 8002fd2: d02f beq.n 8003034 + 8002fd4: 687b ldr r3, [r7, #4] + 8002fd6: 68db ldr r3, [r3, #12] + 8002fd8: f403 7340 and.w r3, r3, #768 ; 0x300 + 8002fdc: 693a ldr r2, [r7, #16] + 8002fde: 429a cmp r2, r3 + 8002fe0: d028 beq.n 8003034 { - /* Store the content of CSR register before the reset of Backup Domain */ - temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); - 8001c52: 4b28 ldr r3, [pc, #160] ; (8001cf4 ) - 8001c54: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001c56: f423 3340 bic.w r3, r3, #196608 ; 0x30000 - 8001c5a: 60fb str r3, [r7, #12] - + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + 8002fe2: 4b2f ldr r3, [pc, #188] ; (80030a0 ) + 8002fe4: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002fe6: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002fea: 613b str r3, [r7, #16] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); - 8001c5c: 4b27 ldr r3, [pc, #156] ; (8001cfc ) - 8001c5e: 2201 movs r2, #1 - 8001c60: 601a str r2, [r3, #0] + 8002fec: 4b2e ldr r3, [pc, #184] ; (80030a8 ) + 8002fee: 2201 movs r2, #1 + 8002ff0: 601a str r2, [r3, #0] __HAL_RCC_BACKUPRESET_RELEASE(); - 8001c62: 4b26 ldr r3, [pc, #152] ; (8001cfc ) - 8001c64: 2200 movs r2, #0 - 8001c66: 601a str r2, [r3, #0] + 8002ff2: 4b2d ldr r3, [pc, #180] ; (80030a8 ) + 8002ff4: 2200 movs r2, #0 + 8002ff6: 601a str r2, [r3, #0] + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg1; + 8002ff8: 4a29 ldr r2, [pc, #164] ; (80030a0 ) + 8002ffa: 693b ldr r3, [r7, #16] + 8002ffc: 6713 str r3, [r2, #112] ; 0x70 - /* Restore the Content of CSR register */ - RCC->CSR = temp_reg; - 8001c68: 4a22 ldr r2, [pc, #136] ; (8001cf4 ) - 8001c6a: 68fb ldr r3, [r7, #12] - 8001c6c: 6353 str r3, [r2, #52] ; 0x34 - - /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) - 8001c6e: 68fb ldr r3, [r7, #12] - 8001c70: f403 7380 and.w r3, r3, #256 ; 0x100 - 8001c74: 2b00 cmp r3, #0 - 8001c76: d014 beq.n 8001ca2 + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + 8002ffe: 4b28 ldr r3, [pc, #160] ; (80030a0 ) + 8003000: 6f1b ldr r3, [r3, #112] ; 0x70 + 8003002: f003 0301 and.w r3, r3, #1 + 8003006: 2b01 cmp r3, #1 + 8003008: d114 bne.n 8003034 { - /* Get Start Tick */ + /* Get tick */ tickstart = HAL_GetTick(); - 8001c78: f7fe feea bl 8000a50 - 8001c7c: 6138 str r0, [r7, #16] + 800300a: f7fe ffe9 bl 8001fe0 + 800300e: 6178 str r0, [r7, #20] /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - 8001c7e: e00a b.n 8001c96 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8003010: e00a b.n 8003028 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 8001c80: f7fe fee6 bl 8000a50 - 8001c84: 4602 mov r2, r0 - 8001c86: 693b ldr r3, [r7, #16] - 8001c88: 1ad3 subs r3, r2, r3 - 8001c8a: f241 3288 movw r2, #5000 ; 0x1388 - 8001c8e: 4293 cmp r3, r2 - 8001c90: d901 bls.n 8001c96 + 8003012: f7fe ffe5 bl 8001fe0 + 8003016: 4602 mov r2, r0 + 8003018: 697b ldr r3, [r7, #20] + 800301a: 1ad3 subs r3, r2, r3 + 800301c: f241 3288 movw r2, #5000 ; 0x1388 + 8003020: 4293 cmp r3, r2 + 8003022: d901 bls.n 8003028 { return HAL_TIMEOUT; - 8001c92: 2303 movs r3, #3 - 8001c94: e02a b.n 8001cec - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - 8001c96: 4b17 ldr r3, [pc, #92] ; (8001cf4 ) - 8001c98: 6b5b ldr r3, [r3, #52] ; 0x34 - 8001c9a: f403 7300 and.w r3, r3, #512 ; 0x200 - 8001c9e: 2b00 cmp r3, #0 - 8001ca0: d0ee beq.n 8001c80 + 8003024: 2303 movs r3, #3 + 8003026: e034 b.n 8003092 + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + 8003028: 4b1d ldr r3, [pc, #116] ; (80030a0 ) + 800302a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800302c: f003 0302 and.w r3, r3, #2 + 8003030: 2b00 cmp r3, #0 + 8003032: d0ee beq.n 8003012 } } } } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - 8001ca2: 687b ldr r3, [r7, #4] - 8001ca4: 685b ldr r3, [r3, #4] - 8001ca6: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8001caa: f5b3 3f40 cmp.w r3, #196608 ; 0x30000 - 8001cae: d10a bne.n 8001cc6 - 8001cb0: 4b10 ldr r3, [pc, #64] ; (8001cf4 ) - 8001cb2: 681b ldr r3, [r3, #0] - 8001cb4: f023 42c0 bic.w r2, r3, #1610612736 ; 0x60000000 - 8001cb8: 687b ldr r3, [r7, #4] - 8001cba: 685b ldr r3, [r3, #4] - 8001cbc: f003 43c0 and.w r3, r3, #1610612736 ; 0x60000000 - 8001cc0: 490c ldr r1, [pc, #48] ; (8001cf4 ) - 8001cc2: 4313 orrs r3, r2 - 8001cc4: 600b str r3, [r1, #0] - 8001cc6: 4b0b ldr r3, [pc, #44] ; (8001cf4 ) - 8001cc8: 6b5a ldr r2, [r3, #52] ; 0x34 - 8001cca: 687b ldr r3, [r7, #4] - 8001ccc: 685b ldr r3, [r3, #4] - 8001cce: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 8001cd2: 4908 ldr r1, [pc, #32] ; (8001cf4 ) - 8001cd4: 4313 orrs r3, r2 - 8001cd6: 634b str r3, [r1, #52] ; 0x34 - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - 8001cd8: 7dfb ldrb r3, [r7, #23] - 8001cda: 2b01 cmp r3, #1 - 8001cdc: d105 bne.n 8001cea - { - __HAL_RCC_PWR_CLK_DISABLE(); - 8001cde: 4b05 ldr r3, [pc, #20] ; (8001cf4 ) - 8001ce0: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001ce2: 4a04 ldr r2, [pc, #16] ; (8001cf4 ) - 8001ce4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 8001ce8: 6253 str r3, [r2, #36] ; 0x24 - } + 8003034: 687b ldr r3, [r7, #4] + 8003036: 68db ldr r3, [r3, #12] + 8003038: f403 7340 and.w r3, r3, #768 ; 0x300 + 800303c: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 8003040: d10d bne.n 800305e + 8003042: 4b17 ldr r3, [pc, #92] ; (80030a0 ) + 8003044: 689b ldr r3, [r3, #8] + 8003046: f423 12f8 bic.w r2, r3, #2031616 ; 0x1f0000 + 800304a: 687b ldr r3, [r7, #4] + 800304c: 68db ldr r3, [r3, #12] + 800304e: f023 4370 bic.w r3, r3, #4026531840 ; 0xf0000000 + 8003052: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8003056: 4912 ldr r1, [pc, #72] ; (80030a0 ) + 8003058: 4313 orrs r3, r2 + 800305a: 608b str r3, [r1, #8] + 800305c: e005 b.n 800306a + 800305e: 4b10 ldr r3, [pc, #64] ; (80030a0 ) + 8003060: 689b ldr r3, [r3, #8] + 8003062: 4a0f ldr r2, [pc, #60] ; (80030a0 ) + 8003064: f423 13f8 bic.w r3, r3, #2031616 ; 0x1f0000 + 8003068: 6093 str r3, [r2, #8] + 800306a: 4b0d ldr r3, [pc, #52] ; (80030a0 ) + 800306c: 6f1a ldr r2, [r3, #112] ; 0x70 + 800306e: 687b ldr r3, [r7, #4] + 8003070: 68db ldr r3, [r3, #12] + 8003072: f3c3 030b ubfx r3, r3, #0, #12 + 8003076: 490a ldr r1, [pc, #40] ; (80030a0 ) + 8003078: 4313 orrs r3, r2 + 800307a: 670b str r3, [r1, #112] ; 0x70 } - +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + /*---------------------------- TIM configuration ---------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + 800307c: 687b ldr r3, [r7, #4] + 800307e: 681b ldr r3, [r3, #0] + 8003080: f003 0308 and.w r3, r3, #8 + 8003084: 2b00 cmp r3, #0 + 8003086: d003 beq.n 8003090 + { + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + 8003088: 687b ldr r3, [r7, #4] + 800308a: 7c1a ldrb r2, [r3, #16] + 800308c: 4b07 ldr r3, [pc, #28] ; (80030ac ) + 800308e: 601a str r2, [r3, #0] + } +#endif /* STM32F401xC || STM32F401xE || STM32F411xE */ return HAL_OK; - 8001cea: 2300 movs r3, #0 + 8003090: 2300 movs r3, #0 } - 8001cec: 4618 mov r0, r3 - 8001cee: 3718 adds r7, #24 - 8001cf0: 46bd mov sp, r7 - 8001cf2: bd80 pop {r7, pc} - 8001cf4: 40023800 .word 0x40023800 - 8001cf8: 40007000 .word 0x40007000 - 8001cfc: 424706dc .word 0x424706dc + 8003092: 4618 mov r0, r3 + 8003094: 3718 adds r7, #24 + 8003096: 46bd mov sp, r7 + 8003098: bd80 pop {r7, pc} + 800309a: bf00 nop + 800309c: 42470068 .word 0x42470068 + 80030a0: 40023800 .word 0x40023800 + 80030a4: 40007000 .word 0x40007000 + 80030a8: 42470e40 .word 0x42470e40 + 80030ac: 424711e0 .word 0x424711e0 -08001d00 : - * @brief Initialize the RTC peripheral - * @param hrtc RTC handle +080030b0 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { - 8001d00: b580 push {r7, lr} - 8001d02: b082 sub sp, #8 - 8001d04: af00 add r7, sp, #0 - 8001d06: 6078 str r0, [r7, #4] + 80030b0: b580 push {r7, lr} + 80030b2: b082 sub sp, #8 + 80030b4: af00 add r7, sp, #0 + 80030b6: 6078 str r0, [r7, #4] /* Check the RTC peripheral state */ - if (hrtc == NULL) - 8001d08: 687b ldr r3, [r7, #4] - 8001d0a: 2b00 cmp r3, #0 - 8001d0c: d101 bne.n 8001d12 + if(hrtc == NULL) + 80030b8: 687b ldr r3, [r7, #4] + 80030ba: 2b00 cmp r3, #0 + 80030bc: d101 bne.n 80030c2 { - return HAL_ERROR; - 8001d0e: 2301 movs r3, #1 - 8001d10: e06d b.n 8001dee + return HAL_ERROR; + 80030be: 2301 movs r3, #1 + 80030c0: e083 b.n 80031ca { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } #else - if (hrtc->State == HAL_RTC_STATE_RESET) - 8001d12: 687b ldr r3, [r7, #4] - 8001d14: 7f5b ldrb r3, [r3, #29] - 8001d16: b2db uxtb r3, r3 - 8001d18: 2b00 cmp r3, #0 - 8001d1a: d105 bne.n 8001d28 + if(hrtc->State == HAL_RTC_STATE_RESET) + 80030c2: 687b ldr r3, [r7, #4] + 80030c4: 7f5b ldrb r3, [r3, #29] + 80030c6: b2db uxtb r3, r3 + 80030c8: 2b00 cmp r3, #0 + 80030ca: d105 bne.n 80030d8 { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; - 8001d1c: 687b ldr r3, [r7, #4] - 8001d1e: 2200 movs r2, #0 - 8001d20: 771a strb r2, [r3, #28] + 80030cc: 687b ldr r3, [r7, #4] + 80030ce: 2200 movs r2, #0 + 80030d0: 771a strb r2, [r3, #28] /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); - 8001d22: 6878 ldr r0, [r7, #4] - 8001d24: f7fe fd7a bl 800081c + 80030d2: 6878 ldr r0, [r7, #4] + 80030d4: f7fe fe46 bl 8001d64 } #endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - 8001d28: 687b ldr r3, [r7, #4] - 8001d2a: 2202 movs r2, #2 - 8001d2c: 775a strb r2, [r3, #29] + 80030d8: 687b ldr r3, [r7, #4] + 80030da: 2202 movs r2, #2 + 80030dc: 775a strb r2, [r3, #29] /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - 8001d2e: 687b ldr r3, [r7, #4] - 8001d30: 681b ldr r3, [r3, #0] - 8001d32: 22ca movs r2, #202 ; 0xca - 8001d34: 625a str r2, [r3, #36] ; 0x24 - 8001d36: 687b ldr r3, [r7, #4] - 8001d38: 681b ldr r3, [r3, #0] - 8001d3a: 2253 movs r2, #83 ; 0x53 - 8001d3c: 625a str r2, [r3, #36] ; 0x24 + 80030de: 687b ldr r3, [r7, #4] + 80030e0: 681b ldr r3, [r3, #0] + 80030e2: 22ca movs r2, #202 ; 0xca + 80030e4: 625a str r2, [r3, #36] ; 0x24 + 80030e6: 687b ldr r3, [r7, #4] + 80030e8: 681b ldr r3, [r3, #0] + 80030ea: 2253 movs r2, #83 ; 0x53 + 80030ec: 625a str r2, [r3, #36] ; 0x24 /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - 8001d3e: 6878 ldr r0, [r7, #4] - 8001d40: f000 fa82 bl 8002248 - 8001d44: 4603 mov r3, r0 - 8001d46: 2b00 cmp r3, #0 - 8001d48: d008 beq.n 8001d5c + if(RTC_EnterInitMode(hrtc) != HAL_OK) + 80030ee: 6878 ldr r0, [r7, #4] + 80030f0: f000 fc26 bl 8003940 + 80030f4: 4603 mov r3, r0 + 80030f6: 2b00 cmp r3, #0 + 80030f8: d008 beq.n 800310c { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8001d4a: 687b ldr r3, [r7, #4] - 8001d4c: 681b ldr r3, [r3, #0] - 8001d4e: 22ff movs r2, #255 ; 0xff - 8001d50: 625a str r2, [r3, #36] ; 0x24 + 80030fa: 687b ldr r3, [r7, #4] + 80030fc: 681b ldr r3, [r3, #0] + 80030fe: 22ff movs r2, #255 ; 0xff + 8003100: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; - 8001d52: 687b ldr r3, [r7, #4] - 8001d54: 2204 movs r2, #4 - 8001d56: 775a strb r2, [r3, #29] + 8003102: 687b ldr r3, [r7, #4] + 8003104: 2204 movs r2, #4 + 8003106: 775a strb r2, [r3, #29] return HAL_ERROR; - 8001d58: 2301 movs r3, #1 - 8001d5a: e048 b.n 8001dee + 8003108: 2301 movs r3, #1 + 800310a: e05e b.n 80031ca } else { /* Clear RTC_CR FMT, OSEL and POL Bits */ hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - 8001d5c: 687b ldr r3, [r7, #4] - 8001d5e: 681b ldr r3, [r3, #0] - 8001d60: 689b ldr r3, [r3, #8] - 8001d62: 687a ldr r2, [r7, #4] - 8001d64: 6812 ldr r2, [r2, #0] - 8001d66: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 - 8001d6a: f023 0340 bic.w r3, r3, #64 ; 0x40 - 8001d6e: 6093 str r3, [r2, #8] + 800310c: 687b ldr r3, [r7, #4] + 800310e: 681b ldr r3, [r3, #0] + 8003110: 689b ldr r3, [r3, #8] + 8003112: 687a ldr r2, [r7, #4] + 8003114: 6812 ldr r2, [r2, #0] + 8003116: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 800311a: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800311e: 6093 str r3, [r2, #8] /* Set RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - 8001d70: 687b ldr r3, [r7, #4] - 8001d72: 681b ldr r3, [r3, #0] - 8001d74: 6899 ldr r1, [r3, #8] - 8001d76: 687b ldr r3, [r7, #4] - 8001d78: 685a ldr r2, [r3, #4] - 8001d7a: 687b ldr r3, [r7, #4] - 8001d7c: 691b ldr r3, [r3, #16] - 8001d7e: 431a orrs r2, r3 - 8001d80: 687b ldr r3, [r7, #4] - 8001d82: 695b ldr r3, [r3, #20] - 8001d84: 431a orrs r2, r3 - 8001d86: 687b ldr r3, [r7, #4] - 8001d88: 681b ldr r3, [r3, #0] - 8001d8a: 430a orrs r2, r1 - 8001d8c: 609a str r2, [r3, #8] + 8003120: 687b ldr r3, [r7, #4] + 8003122: 681b ldr r3, [r3, #0] + 8003124: 6899 ldr r1, [r3, #8] + 8003126: 687b ldr r3, [r7, #4] + 8003128: 685a ldr r2, [r3, #4] + 800312a: 687b ldr r3, [r7, #4] + 800312c: 691b ldr r3, [r3, #16] + 800312e: 431a orrs r2, r3 + 8003130: 687b ldr r3, [r7, #4] + 8003132: 695b ldr r3, [r3, #20] + 8003134: 431a orrs r2, r3 + 8003136: 687b ldr r3, [r7, #4] + 8003138: 681b ldr r3, [r3, #0] + 800313a: 430a orrs r2, r1 + 800313c: 609a str r2, [r3, #8] /* Configure the RTC PRER */ hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - 8001d8e: 687b ldr r3, [r7, #4] - 8001d90: 681b ldr r3, [r3, #0] - 8001d92: 687a ldr r2, [r7, #4] - 8001d94: 68d2 ldr r2, [r2, #12] - 8001d96: 611a str r2, [r3, #16] + 800313e: 687b ldr r3, [r7, #4] + 8003140: 681b ldr r3, [r3, #0] + 8003142: 687a ldr r2, [r7, #4] + 8003144: 68d2 ldr r2, [r2, #12] + 8003146: 611a str r2, [r3, #16] hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); - 8001d98: 687b ldr r3, [r7, #4] - 8001d9a: 681b ldr r3, [r3, #0] - 8001d9c: 6919 ldr r1, [r3, #16] - 8001d9e: 687b ldr r3, [r7, #4] - 8001da0: 689b ldr r3, [r3, #8] - 8001da2: 041a lsls r2, r3, #16 - 8001da4: 687b ldr r3, [r7, #4] - 8001da6: 681b ldr r3, [r3, #0] - 8001da8: 430a orrs r2, r1 - 8001daa: 611a str r2, [r3, #16] + 8003148: 687b ldr r3, [r7, #4] + 800314a: 681b ldr r3, [r3, #0] + 800314c: 6919 ldr r1, [r3, #16] + 800314e: 687b ldr r3, [r7, #4] + 8003150: 689b ldr r3, [r3, #8] + 8003152: 041a lsls r2, r3, #16 + 8003154: 687b ldr r3, [r7, #4] + 8003156: 681b ldr r3, [r3, #0] + 8003158: 430a orrs r2, r1 + 800315a: 611a str r2, [r3, #16] /* Exit Initialization mode */ hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - 8001dac: 687b ldr r3, [r7, #4] - 8001dae: 681b ldr r3, [r3, #0] - 8001db0: 68da ldr r2, [r3, #12] - 8001db2: 687b ldr r3, [r7, #4] - 8001db4: 681b ldr r3, [r3, #0] - 8001db6: f022 0280 bic.w r2, r2, #128 ; 0x80 - 8001dba: 60da str r2, [r3, #12] + 800315c: 687b ldr r3, [r7, #4] + 800315e: 681b ldr r3, [r3, #0] + 8003160: 68da ldr r2, [r3, #12] + 8003162: 687b ldr r3, [r7, #4] + 8003164: 681b ldr r3, [r3, #0] + 8003166: f022 0280 bic.w r2, r2, #128 ; 0x80 + 800316a: 60da str r2, [r3, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 800316c: 687b ldr r3, [r7, #4] + 800316e: 681b ldr r3, [r3, #0] + 8003170: 689b ldr r3, [r3, #8] + 8003172: f003 0320 and.w r3, r3, #32 + 8003176: 2b00 cmp r3, #0 + 8003178: d10e bne.n 8003198 + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 800317a: 6878 ldr r0, [r7, #4] + 800317c: f000 fbb8 bl 80038f0 + 8003180: 4603 mov r3, r0 + 8003182: 2b00 cmp r3, #0 + 8003184: d008 beq.n 8003198 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003186: 687b ldr r3, [r7, #4] + 8003188: 681b ldr r3, [r3, #0] + 800318a: 22ff movs r2, #255 ; 0xff + 800318c: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_ERROR; + 800318e: 687b ldr r3, [r7, #4] + 8003190: 2204 movs r2, #4 + 8003192: 775a strb r2, [r3, #29] + + return HAL_ERROR; + 8003194: 2301 movs r3, #1 + 8003196: e018 b.n 80031ca + } + } hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; - 8001dbc: 687b ldr r3, [r7, #4] - 8001dbe: 681b ldr r3, [r3, #0] - 8001dc0: 6c1a ldr r2, [r3, #64] ; 0x40 - 8001dc2: 687b ldr r3, [r7, #4] - 8001dc4: 681b ldr r3, [r3, #0] - 8001dc6: f422 2280 bic.w r2, r2, #262144 ; 0x40000 - 8001dca: 641a str r2, [r3, #64] ; 0x40 + 8003198: 687b ldr r3, [r7, #4] + 800319a: 681b ldr r3, [r3, #0] + 800319c: 6c1a ldr r2, [r3, #64] ; 0x40 + 800319e: 687b ldr r3, [r7, #4] + 80031a0: 681b ldr r3, [r3, #0] + 80031a2: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 80031a6: 641a str r2, [r3, #64] ; 0x40 hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); - 8001dcc: 687b ldr r3, [r7, #4] - 8001dce: 681b ldr r3, [r3, #0] - 8001dd0: 6c19 ldr r1, [r3, #64] ; 0x40 - 8001dd2: 687b ldr r3, [r7, #4] - 8001dd4: 699a ldr r2, [r3, #24] - 8001dd6: 687b ldr r3, [r7, #4] - 8001dd8: 681b ldr r3, [r3, #0] - 8001dda: 430a orrs r2, r1 - 8001ddc: 641a str r2, [r3, #64] ; 0x40 + 80031a8: 687b ldr r3, [r7, #4] + 80031aa: 681b ldr r3, [r3, #0] + 80031ac: 6c19 ldr r1, [r3, #64] ; 0x40 + 80031ae: 687b ldr r3, [r7, #4] + 80031b0: 699a ldr r2, [r3, #24] + 80031b2: 687b ldr r3, [r7, #4] + 80031b4: 681b ldr r3, [r3, #0] + 80031b6: 430a orrs r2, r1 + 80031b8: 641a str r2, [r3, #64] ; 0x40 /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8001dde: 687b ldr r3, [r7, #4] - 8001de0: 681b ldr r3, [r3, #0] - 8001de2: 22ff movs r2, #255 ; 0xff - 8001de4: 625a str r2, [r3, #36] ; 0x24 + 80031ba: 687b ldr r3, [r7, #4] + 80031bc: 681b ldr r3, [r3, #0] + 80031be: 22ff movs r2, #255 ; 0xff + 80031c0: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state */ hrtc->State = HAL_RTC_STATE_READY; - 8001de6: 687b ldr r3, [r7, #4] - 8001de8: 2201 movs r2, #1 - 8001dea: 775a strb r2, [r3, #29] + 80031c2: 687b ldr r3, [r7, #4] + 80031c4: 2201 movs r2, #1 + 80031c6: 775a strb r2, [r3, #29] return HAL_OK; - 8001dec: 2300 movs r3, #0 + 80031c8: 2300 movs r3, #0 } } - 8001dee: 4618 mov r0, r3 - 8001df0: 3708 adds r7, #8 - 8001df2: 46bd mov sp, r7 - 8001df4: bd80 pop {r7, pc} + 80031ca: 4618 mov r0, r3 + 80031cc: 3708 adds r7, #8 + 80031ce: 46bd mov sp, r7 + 80031d0: bd80 pop {r7, pc} -08001df6 : +080031d2 : * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - 8001df6: b590 push {r4, r7, lr} - 8001df8: b087 sub sp, #28 - 8001dfa: af00 add r7, sp, #0 - 8001dfc: 60f8 str r0, [r7, #12] - 8001dfe: 60b9 str r1, [r7, #8] - 8001e00: 607a str r2, [r7, #4] + 80031d2: b590 push {r4, r7, lr} + 80031d4: b087 sub sp, #28 + 80031d6: af00 add r7, sp, #0 + 80031d8: 60f8 str r0, [r7, #12] + 80031da: 60b9 str r1, [r7, #8] + 80031dc: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 80031de: 2300 movs r3, #0 + 80031e0: 617b str r3, [r7, #20] assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); /* Process Locked */ __HAL_LOCK(hrtc); - 8001e02: 68fb ldr r3, [r7, #12] - 8001e04: 7f1b ldrb r3, [r3, #28] - 8001e06: 2b01 cmp r3, #1 - 8001e08: d101 bne.n 8001e0e - 8001e0a: 2302 movs r3, #2 - 8001e0c: e0a3 b.n 8001f56 - 8001e0e: 68fb ldr r3, [r7, #12] - 8001e10: 2201 movs r2, #1 - 8001e12: 771a strb r2, [r3, #28] + 80031e2: 68fb ldr r3, [r7, #12] + 80031e4: 7f1b ldrb r3, [r3, #28] + 80031e6: 2b01 cmp r3, #1 + 80031e8: d101 bne.n 80031ee + 80031ea: 2302 movs r3, #2 + 80031ec: e0aa b.n 8003344 + 80031ee: 68fb ldr r3, [r7, #12] + 80031f0: 2201 movs r2, #1 + 80031f2: 771a strb r2, [r3, #28] hrtc->State = HAL_RTC_STATE_BUSY; - 8001e14: 68fb ldr r3, [r7, #12] - 8001e16: 2202 movs r2, #2 - 8001e18: 775a strb r2, [r3, #29] + 80031f4: 68fb ldr r3, [r7, #12] + 80031f6: 2202 movs r2, #2 + 80031f8: 775a strb r2, [r3, #29] - if (Format == RTC_FORMAT_BIN) - 8001e1a: 687b ldr r3, [r7, #4] - 8001e1c: 2b00 cmp r3, #0 - 8001e1e: d126 bne.n 8001e6e + if(Format == RTC_FORMAT_BIN) + 80031fa: 687b ldr r3, [r7, #4] + 80031fc: 2b00 cmp r3, #0 + 80031fe: d126 bne.n 800324e { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - 8001e20: 68fb ldr r3, [r7, #12] - 8001e22: 681b ldr r3, [r3, #0] - 8001e24: 689b ldr r3, [r3, #8] - 8001e26: f003 0340 and.w r3, r3, #64 ; 0x40 - 8001e2a: 2b00 cmp r3, #0 - 8001e2c: d102 bne.n 8001e34 + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 8003200: 68fb ldr r3, [r7, #12] + 8003202: 681b ldr r3, [r3, #0] + 8003204: 689b ldr r3, [r3, #8] + 8003206: f003 0340 and.w r3, r3, #64 ; 0x40 + 800320a: 2b00 cmp r3, #0 + 800320c: d102 bne.n 8003214 assert_param(IS_RTC_HOUR12(sTime->Hours)); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); } else { sTime->TimeFormat = 0x00U; - 8001e2e: 68bb ldr r3, [r7, #8] - 8001e30: 2200 movs r2, #0 - 8001e32: 70da strb r2, [r3, #3] + 800320e: 68bb ldr r3, [r7, #8] + 8003210: 2200 movs r2, #0 + 8003212: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(sTime->Hours)); } assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - 8001e34: 68bb ldr r3, [r7, #8] - 8001e36: 781b ldrb r3, [r3, #0] - 8001e38: 4618 mov r0, r3 - 8001e3a: f000 fa2f bl 800229c - 8001e3e: 4603 mov r3, r0 - 8001e40: 041c lsls r4, r3, #16 + 8003214: 68bb ldr r3, [r7, #8] + 8003216: 781b ldrb r3, [r3, #0] + 8003218: 4618 mov r0, r3 + 800321a: f000 fbbd bl 8003998 + 800321e: 4603 mov r3, r0 + 8003220: 041c lsls r4, r3, #16 ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ - 8001e42: 68bb ldr r3, [r7, #8] - 8001e44: 785b ldrb r3, [r3, #1] - 8001e46: 4618 mov r0, r3 - 8001e48: f000 fa28 bl 800229c - 8001e4c: 4603 mov r3, r0 - 8001e4e: 021b lsls r3, r3, #8 + 8003222: 68bb ldr r3, [r7, #8] + 8003224: 785b ldrb r3, [r3, #1] + 8003226: 4618 mov r0, r3 + 8003228: f000 fbb6 bl 8003998 + 800322c: 4603 mov r3, r0 + 800322e: 021b lsls r3, r3, #8 tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - 8001e50: 431c orrs r4, r3 + 8003230: 431c orrs r4, r3 ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - 8001e52: 68bb ldr r3, [r7, #8] - 8001e54: 789b ldrb r3, [r3, #2] - 8001e56: 4618 mov r0, r3 - 8001e58: f000 fa20 bl 800229c - 8001e5c: 4603 mov r3, r0 + 8003232: 68bb ldr r3, [r7, #8] + 8003234: 789b ldrb r3, [r3, #2] + 8003236: 4618 mov r0, r3 + 8003238: f000 fbae bl 8003998 + 800323c: 4603 mov r3, r0 ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ - 8001e5e: ea44 0203 orr.w r2, r4, r3 + 800323e: ea44 0203 orr.w r2, r4, r3 (((uint32_t)sTime->TimeFormat) << 16U)); - 8001e62: 68bb ldr r3, [r7, #8] - 8001e64: 78db ldrb r3, [r3, #3] - 8001e66: 041b lsls r3, r3, #16 + 8003242: 68bb ldr r3, [r7, #8] + 8003244: 78db ldrb r3, [r3, #3] + 8003246: 041b lsls r3, r3, #16 tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - 8001e68: 4313 orrs r3, r2 - 8001e6a: 617b str r3, [r7, #20] - 8001e6c: e018 b.n 8001ea0 + 8003248: 4313 orrs r3, r2 + 800324a: 617b str r3, [r7, #20] + 800324c: e018 b.n 8003280 } else { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - 8001e6e: 68fb ldr r3, [r7, #12] - 8001e70: 681b ldr r3, [r3, #0] - 8001e72: 689b ldr r3, [r3, #8] - 8001e74: f003 0340 and.w r3, r3, #64 ; 0x40 - 8001e78: 2b00 cmp r3, #0 - 8001e7a: d102 bne.n 8001e82 + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 800324e: 68fb ldr r3, [r7, #12] + 8003250: 681b ldr r3, [r3, #0] + 8003252: 689b ldr r3, [r3, #8] + 8003254: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003258: 2b00 cmp r3, #0 + 800325a: d102 bne.n 8003262 assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); } else { sTime->TimeFormat = 0x00U; - 8001e7c: 68bb ldr r3, [r7, #8] - 8001e7e: 2200 movs r2, #0 - 8001e80: 70da strb r2, [r3, #3] + 800325c: 68bb ldr r3, [r7, #8] + 800325e: 2200 movs r2, #0 + 8003260: 70da strb r2, [r3, #3] assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - 8001e82: 68bb ldr r3, [r7, #8] - 8001e84: 781b ldrb r3, [r3, #0] - 8001e86: 041a lsls r2, r3, #16 + 8003262: 68bb ldr r3, [r7, #8] + 8003264: 781b ldrb r3, [r3, #0] + 8003266: 041a lsls r2, r3, #16 ((uint32_t)(sTime->Minutes) << 8U) | \ - 8001e88: 68bb ldr r3, [r7, #8] - 8001e8a: 785b ldrb r3, [r3, #1] - 8001e8c: 021b lsls r3, r3, #8 + 8003268: 68bb ldr r3, [r7, #8] + 800326a: 785b ldrb r3, [r3, #1] + 800326c: 021b lsls r3, r3, #8 tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - 8001e8e: 4313 orrs r3, r2 + 800326e: 4313 orrs r3, r2 ((uint32_t)sTime->Seconds) | \ - 8001e90: 68ba ldr r2, [r7, #8] - 8001e92: 7892 ldrb r2, [r2, #2] + 8003270: 68ba ldr r2, [r7, #8] + 8003272: 7892 ldrb r2, [r2, #2] ((uint32_t)(sTime->Minutes) << 8U) | \ - 8001e94: 431a orrs r2, r3 + 8003274: 431a orrs r2, r3 ((uint32_t)(sTime->TimeFormat) << 16U)); - 8001e96: 68bb ldr r3, [r7, #8] - 8001e98: 78db ldrb r3, [r3, #3] - 8001e9a: 041b lsls r3, r3, #16 + 8003276: 68bb ldr r3, [r7, #8] + 8003278: 78db ldrb r3, [r3, #3] + 800327a: 041b lsls r3, r3, #16 tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - 8001e9c: 4313 orrs r3, r2 - 8001e9e: 617b str r3, [r7, #20] + 800327c: 4313 orrs r3, r2 + 800327e: 617b str r3, [r7, #20] } - UNUSED(tmpreg); + /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - 8001ea0: 68fb ldr r3, [r7, #12] - 8001ea2: 681b ldr r3, [r3, #0] - 8001ea4: 22ca movs r2, #202 ; 0xca - 8001ea6: 625a str r2, [r3, #36] ; 0x24 - 8001ea8: 68fb ldr r3, [r7, #12] - 8001eaa: 681b ldr r3, [r3, #0] - 8001eac: 2253 movs r2, #83 ; 0x53 - 8001eae: 625a str r2, [r3, #36] ; 0x24 + 8003280: 68fb ldr r3, [r7, #12] + 8003282: 681b ldr r3, [r3, #0] + 8003284: 22ca movs r2, #202 ; 0xca + 8003286: 625a str r2, [r3, #36] ; 0x24 + 8003288: 68fb ldr r3, [r7, #12] + 800328a: 681b ldr r3, [r3, #0] + 800328c: 2253 movs r2, #83 ; 0x53 + 800328e: 625a str r2, [r3, #36] ; 0x24 /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - 8001eb0: 68f8 ldr r0, [r7, #12] - 8001eb2: f000 f9c9 bl 8002248 - 8001eb6: 4603 mov r3, r0 - 8001eb8: 2b00 cmp r3, #0 - 8001eba: d00b beq.n 8001ed4 + if(RTC_EnterInitMode(hrtc) != HAL_OK) + 8003290: 68f8 ldr r0, [r7, #12] + 8003292: f000 fb55 bl 8003940 + 8003296: 4603 mov r3, r0 + 8003298: 2b00 cmp r3, #0 + 800329a: d00b beq.n 80032b4 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8001ebc: 68fb ldr r3, [r7, #12] - 8001ebe: 681b ldr r3, [r3, #0] - 8001ec0: 22ff movs r2, #255 ; 0xff - 8001ec2: 625a str r2, [r3, #36] ; 0x24 + 800329c: 68fb ldr r3, [r7, #12] + 800329e: 681b ldr r3, [r3, #0] + 80032a0: 22ff movs r2, #255 ; 0xff + 80032a2: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state */ hrtc->State = HAL_RTC_STATE_ERROR; - 8001ec4: 68fb ldr r3, [r7, #12] - 8001ec6: 2204 movs r2, #4 - 8001ec8: 775a strb r2, [r3, #29] + 80032a4: 68fb ldr r3, [r7, #12] + 80032a6: 2204 movs r2, #4 + 80032a8: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); - 8001eca: 68fb ldr r3, [r7, #12] - 8001ecc: 2200 movs r2, #0 - 8001ece: 771a strb r2, [r3, #28] + 80032aa: 68fb ldr r3, [r7, #12] + 80032ac: 2200 movs r2, #0 + 80032ae: 771a strb r2, [r3, #28] return HAL_ERROR; - 8001ed0: 2301 movs r3, #1 - 8001ed2: e040 b.n 8001f56 + 80032b0: 2301 movs r3, #1 + 80032b2: e047 b.n 8003344 } else { /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - 8001ed4: 68fb ldr r3, [r7, #12] - 8001ed6: 681a ldr r2, [r3, #0] - 8001ed8: 697b ldr r3, [r7, #20] - 8001eda: f003 337f and.w r3, r3, #2139062143 ; 0x7f7f7f7f - 8001ede: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 - 8001ee2: 6013 str r3, [r2, #0] + 80032b4: 68fb ldr r3, [r7, #12] + 80032b6: 681a ldr r2, [r3, #0] + 80032b8: 697b ldr r3, [r7, #20] + 80032ba: f003 337f and.w r3, r3, #2139062143 ; 0x7f7f7f7f + 80032be: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 + 80032c2: 6013 str r3, [r2, #0] /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); - 8001ee4: 68fb ldr r3, [r7, #12] - 8001ee6: 681b ldr r3, [r3, #0] - 8001ee8: 689a ldr r2, [r3, #8] - 8001eea: 68fb ldr r3, [r7, #12] - 8001eec: 681b ldr r3, [r3, #0] - 8001eee: f422 2280 bic.w r2, r2, #262144 ; 0x40000 - 8001ef2: 609a str r2, [r3, #8] + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + 80032c4: 68fb ldr r3, [r7, #12] + 80032c6: 681b ldr r3, [r3, #0] + 80032c8: 689a ldr r2, [r3, #8] + 80032ca: 68fb ldr r3, [r7, #12] + 80032cc: 681b ldr r3, [r3, #0] + 80032ce: f422 2280 bic.w r2, r2, #262144 ; 0x40000 + 80032d2: 609a str r2, [r3, #8] /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - 8001ef4: 68fb ldr r3, [r7, #12] - 8001ef6: 681b ldr r3, [r3, #0] - 8001ef8: 6899 ldr r1, [r3, #8] - 8001efa: 68bb ldr r3, [r7, #8] - 8001efc: 68da ldr r2, [r3, #12] - 8001efe: 68bb ldr r3, [r7, #8] - 8001f00: 691b ldr r3, [r3, #16] - 8001f02: 431a orrs r2, r3 - 8001f04: 68fb ldr r3, [r7, #12] - 8001f06: 681b ldr r3, [r3, #0] - 8001f08: 430a orrs r2, r1 - 8001f0a: 609a str r2, [r3, #8] + 80032d4: 68fb ldr r3, [r7, #12] + 80032d6: 681b ldr r3, [r3, #0] + 80032d8: 6899 ldr r1, [r3, #8] + 80032da: 68bb ldr r3, [r7, #8] + 80032dc: 68da ldr r2, [r3, #12] + 80032de: 68bb ldr r3, [r7, #8] + 80032e0: 691b ldr r3, [r3, #16] + 80032e2: 431a orrs r2, r3 + 80032e4: 68fb ldr r3, [r7, #12] + 80032e6: 681b ldr r3, [r3, #0] + 80032e8: 430a orrs r2, r1 + 80032ea: 609a str r2, [r3, #8] /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - 8001f0c: 68fb ldr r3, [r7, #12] - 8001f0e: 681b ldr r3, [r3, #0] - 8001f10: 68da ldr r2, [r3, #12] - 8001f12: 68fb ldr r3, [r7, #12] - 8001f14: 681b ldr r3, [r3, #0] - 8001f16: f022 0280 bic.w r2, r2, #128 ; 0x80 - 8001f1a: 60da str r2, [r3, #12] + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 80032ec: 68fb ldr r3, [r7, #12] + 80032ee: 681b ldr r3, [r3, #0] + 80032f0: 68da ldr r2, [r3, #12] + 80032f2: 68fb ldr r3, [r7, #12] + 80032f4: 681b ldr r3, [r3, #0] + 80032f6: f022 0280 bic.w r2, r2, #128 ; 0x80 + 80032fa: 60da str r2, [r3, #12] - /* Wait for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - 8001f1c: 68f8 ldr r0, [r7, #12] - 8001f1e: f000 f966 bl 80021ee - 8001f22: 4603 mov r3, r0 - 8001f24: 2b00 cmp r3, #0 - 8001f26: d00b beq.n 8001f40 + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 80032fc: 68fb ldr r3, [r7, #12] + 80032fe: 681b ldr r3, [r3, #0] + 8003300: 689b ldr r3, [r3, #8] + 8003302: f003 0320 and.w r3, r3, #32 + 8003306: 2b00 cmp r3, #0 + 8003308: d111 bne.n 800332e { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8001f28: 68fb ldr r3, [r7, #12] - 8001f2a: 681b ldr r3, [r3, #0] - 8001f2c: 22ff movs r2, #255 ; 0xff - 8001f2e: 625a str r2, [r3, #36] ; 0x24 + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 800330a: 68f8 ldr r0, [r7, #12] + 800330c: f000 faf0 bl 80038f0 + 8003310: 4603 mov r3, r0 + 8003312: 2b00 cmp r3, #0 + 8003314: d00b beq.n 800332e + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003316: 68fb ldr r3, [r7, #12] + 8003318: 681b ldr r3, [r3, #0] + 800331a: 22ff movs r2, #255 ; 0xff + 800331c: 625a str r2, [r3, #36] ; 0x24 - hrtc->State = HAL_RTC_STATE_ERROR; - 8001f30: 68fb ldr r3, [r7, #12] - 8001f32: 2204 movs r2, #4 - 8001f34: 775a strb r2, [r3, #29] + hrtc->State = HAL_RTC_STATE_ERROR; + 800331e: 68fb ldr r3, [r7, #12] + 8003320: 2204 movs r2, #4 + 8003322: 775a strb r2, [r3, #29] - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - 8001f36: 68fb ldr r3, [r7, #12] - 8001f38: 2200 movs r2, #0 - 8001f3a: 771a strb r2, [r3, #28] + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003324: 68fb ldr r3, [r7, #12] + 8003326: 2200 movs r2, #0 + 8003328: 771a strb r2, [r3, #28] - return HAL_ERROR; - 8001f3c: 2301 movs r3, #1 - 8001f3e: e00a b.n 8001f56 + return HAL_ERROR; + 800332a: 2301 movs r3, #1 + 800332c: e00a b.n 8003344 + } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8001f40: 68fb ldr r3, [r7, #12] - 8001f42: 681b ldr r3, [r3, #0] - 8001f44: 22ff movs r2, #255 ; 0xff - 8001f46: 625a str r2, [r3, #36] ; 0x24 + 800332e: 68fb ldr r3, [r7, #12] + 8003330: 681b ldr r3, [r3, #0] + 8003332: 22ff movs r2, #255 ; 0xff + 8003334: 625a str r2, [r3, #36] ; 0x24 - hrtc->State = HAL_RTC_STATE_READY; - 8001f48: 68fb ldr r3, [r7, #12] - 8001f4a: 2201 movs r2, #1 - 8001f4c: 775a strb r2, [r3, #29] + hrtc->State = HAL_RTC_STATE_READY; + 8003336: 68fb ldr r3, [r7, #12] + 8003338: 2201 movs r2, #1 + 800333a: 775a strb r2, [r3, #29] - __HAL_UNLOCK(hrtc); - 8001f4e: 68fb ldr r3, [r7, #12] - 8001f50: 2200 movs r2, #0 - 8001f52: 771a strb r2, [r3, #28] + __HAL_UNLOCK(hrtc); + 800333c: 68fb ldr r3, [r7, #12] + 800333e: 2200 movs r2, #0 + 8003340: 771a strb r2, [r3, #28] - return HAL_OK; - 8001f54: 2300 movs r3, #0 + return HAL_OK; + 8003342: 2300 movs r3, #0 } } - 8001f56: 4618 mov r0, r3 - 8001f58: 371c adds r7, #28 - 8001f5a: 46bd mov sp, r7 - 8001f5c: bd90 pop {r4, r7, pc} + 8003344: 4618 mov r0, r3 + 8003346: 371c adds r7, #28 + 8003348: 46bd mov sp, r7 + 800334a: bd90 pop {r4, r7, pc} -08001f5e : - * Reading RTC current time locks the values in calendar shadow registers until Current date is read - * to ensure consistency between the time and date values. +0800334c : + * in the higher-order calendar shadow registers to ensure consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers until current date is read. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { - 8001f5e: b580 push {r7, lr} - 8001f60: b086 sub sp, #24 - 8001f62: af00 add r7, sp, #0 - 8001f64: 60f8 str r0, [r7, #12] - 8001f66: 60b9 str r1, [r7, #8] - 8001f68: 607a str r2, [r7, #4] + 800334c: b580 push {r7, lr} + 800334e: b086 sub sp, #24 + 8003350: af00 add r7, sp, #0 + 8003352: 60f8 str r0, [r7, #12] + 8003354: 60b9 str r1, [r7, #8] + 8003356: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U; + 8003358: 2300 movs r3, #0 + 800335a: 617b str r3, [r7, #20] + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Get subseconds structure field from the corresponding register*/ - sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS); - 8001f6a: 68fb ldr r3, [r7, #12] - 8001f6c: 681b ldr r3, [r3, #0] - 8001f6e: 6a9b ldr r3, [r3, #40] ; 0x28 - 8001f70: b29a uxth r2, r3 - 8001f72: 68bb ldr r3, [r7, #8] - 8001f74: 605a str r2, [r3, #4] + /* Get subseconds structure field from the corresponding register */ + sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); + 800335c: 68fb ldr r3, [r7, #12] + 800335e: 681b ldr r3, [r3, #0] + 8003360: 6a9a ldr r2, [r3, #40] ; 0x28 + 8003362: 68bb ldr r3, [r7, #8] + 8003364: 605a str r2, [r3, #4] /* Get SecondFraction structure field from the corresponding register field*/ sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - 8001f76: 68fb ldr r3, [r7, #12] - 8001f78: 681b ldr r3, [r3, #0] - 8001f7a: 691b ldr r3, [r3, #16] - 8001f7c: f3c3 020e ubfx r2, r3, #0, #15 - 8001f80: 68bb ldr r3, [r7, #8] - 8001f82: 609a str r2, [r3, #8] -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + 8003366: 68fb ldr r3, [r7, #12] + 8003368: 681b ldr r3, [r3, #0] + 800336a: 691b ldr r3, [r3, #16] + 800336c: f3c3 020e ubfx r2, r3, #0, #15 + 8003370: 68bb ldr r3, [r7, #8] + 8003372: 609a str r2, [r3, #8] /* Get the TR register */ tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - 8001f84: 68fb ldr r3, [r7, #12] - 8001f86: 681b ldr r3, [r3, #0] - 8001f88: 681b ldr r3, [r3, #0] - 8001f8a: f003 337f and.w r3, r3, #2139062143 ; 0x7f7f7f7f - 8001f8e: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 - 8001f92: 617b str r3, [r7, #20] + 8003374: 68fb ldr r3, [r7, #12] + 8003376: 681b ldr r3, [r3, #0] + 8003378: 681b ldr r3, [r3, #0] + 800337a: f003 337f and.w r3, r3, #2139062143 ; 0x7f7f7f7f + 800337e: f023 43fe bic.w r3, r3, #2130706432 ; 0x7f000000 + 8003382: 617b str r3, [r7, #20] /* Fill the structure fields with the read parameters */ sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - 8001f94: 697b ldr r3, [r7, #20] - 8001f96: 0c1b lsrs r3, r3, #16 - 8001f98: b2db uxtb r3, r3 - 8001f9a: f003 033f and.w r3, r3, #63 ; 0x3f - 8001f9e: b2da uxtb r2, r3 - 8001fa0: 68bb ldr r3, [r7, #8] - 8001fa2: 701a strb r2, [r3, #0] + 8003384: 697b ldr r3, [r7, #20] + 8003386: 0c1b lsrs r3, r3, #16 + 8003388: b2db uxtb r3, r3 + 800338a: f003 033f and.w r3, r3, #63 ; 0x3f + 800338e: b2da uxtb r2, r3 + 8003390: 68bb ldr r3, [r7, #8] + 8003392: 701a strb r2, [r3, #0] sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - 8001fa4: 697b ldr r3, [r7, #20] - 8001fa6: 0a1b lsrs r3, r3, #8 - 8001fa8: b2db uxtb r3, r3 - 8001faa: f003 037f and.w r3, r3, #127 ; 0x7f - 8001fae: b2da uxtb r2, r3 - 8001fb0: 68bb ldr r3, [r7, #8] - 8001fb2: 705a strb r2, [r3, #1] + 8003394: 697b ldr r3, [r7, #20] + 8003396: 0a1b lsrs r3, r3, #8 + 8003398: b2db uxtb r3, r3 + 800339a: f003 037f and.w r3, r3, #127 ; 0x7f + 800339e: b2da uxtb r2, r3 + 80033a0: 68bb ldr r3, [r7, #8] + 80033a2: 705a strb r2, [r3, #1] sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - 8001fb4: 697b ldr r3, [r7, #20] - 8001fb6: b2db uxtb r3, r3 - 8001fb8: f003 037f and.w r3, r3, #127 ; 0x7f - 8001fbc: b2da uxtb r2, r3 - 8001fbe: 68bb ldr r3, [r7, #8] - 8001fc0: 709a strb r2, [r3, #2] + 80033a4: 697b ldr r3, [r7, #20] + 80033a6: b2db uxtb r3, r3 + 80033a8: f003 037f and.w r3, r3, #127 ; 0x7f + 80033ac: b2da uxtb r2, r3 + 80033ae: 68bb ldr r3, [r7, #8] + 80033b0: 709a strb r2, [r3, #2] sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); - 8001fc2: 697b ldr r3, [r7, #20] - 8001fc4: 0c1b lsrs r3, r3, #16 - 8001fc6: b2db uxtb r3, r3 - 8001fc8: f003 0340 and.w r3, r3, #64 ; 0x40 - 8001fcc: b2da uxtb r2, r3 - 8001fce: 68bb ldr r3, [r7, #8] - 8001fd0: 70da strb r2, [r3, #3] + 80033b2: 697b ldr r3, [r7, #20] + 80033b4: 0c1b lsrs r3, r3, #16 + 80033b6: b2db uxtb r3, r3 + 80033b8: f003 0340 and.w r3, r3, #64 ; 0x40 + 80033bc: b2da uxtb r2, r3 + 80033be: 68bb ldr r3, [r7, #8] + 80033c0: 70da strb r2, [r3, #3] /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - 8001fd2: 687b ldr r3, [r7, #4] - 8001fd4: 2b00 cmp r3, #0 - 8001fd6: d11a bne.n 800200e + if(Format == RTC_FORMAT_BIN) + 80033c2: 687b ldr r3, [r7, #4] + 80033c4: 2b00 cmp r3, #0 + 80033c6: d11a bne.n 80033fe { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - 8001fd8: 68bb ldr r3, [r7, #8] - 8001fda: 781b ldrb r3, [r3, #0] - 8001fdc: 4618 mov r0, r3 - 8001fde: f000 f97c bl 80022da - 8001fe2: 4603 mov r3, r0 - 8001fe4: 461a mov r2, r3 - 8001fe6: 68bb ldr r3, [r7, #8] - 8001fe8: 701a strb r2, [r3, #0] + 80033c8: 68bb ldr r3, [r7, #8] + 80033ca: 781b ldrb r3, [r3, #0] + 80033cc: 4618 mov r0, r3 + 80033ce: f000 fb01 bl 80039d4 + 80033d2: 4603 mov r3, r0 + 80033d4: 461a mov r2, r3 + 80033d6: 68bb ldr r3, [r7, #8] + 80033d8: 701a strb r2, [r3, #0] sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - 8001fea: 68bb ldr r3, [r7, #8] - 8001fec: 785b ldrb r3, [r3, #1] - 8001fee: 4618 mov r0, r3 - 8001ff0: f000 f973 bl 80022da - 8001ff4: 4603 mov r3, r0 - 8001ff6: 461a mov r2, r3 - 8001ff8: 68bb ldr r3, [r7, #8] - 8001ffa: 705a strb r2, [r3, #1] + 80033da: 68bb ldr r3, [r7, #8] + 80033dc: 785b ldrb r3, [r3, #1] + 80033de: 4618 mov r0, r3 + 80033e0: f000 faf8 bl 80039d4 + 80033e4: 4603 mov r3, r0 + 80033e6: 461a mov r2, r3 + 80033e8: 68bb ldr r3, [r7, #8] + 80033ea: 705a strb r2, [r3, #1] sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - 8001ffc: 68bb ldr r3, [r7, #8] - 8001ffe: 789b ldrb r3, [r3, #2] - 8002000: 4618 mov r0, r3 - 8002002: f000 f96a bl 80022da - 8002006: 4603 mov r3, r0 - 8002008: 461a mov r2, r3 - 800200a: 68bb ldr r3, [r7, #8] - 800200c: 709a strb r2, [r3, #2] + 80033ec: 68bb ldr r3, [r7, #8] + 80033ee: 789b ldrb r3, [r3, #2] + 80033f0: 4618 mov r0, r3 + 80033f2: f000 faef bl 80039d4 + 80033f6: 4603 mov r3, r0 + 80033f8: 461a mov r2, r3 + 80033fa: 68bb ldr r3, [r7, #8] + 80033fc: 709a strb r2, [r3, #2] } return HAL_OK; - 800200e: 2300 movs r3, #0 + 80033fe: 2300 movs r3, #0 } - 8002010: 4618 mov r0, r3 - 8002012: 3718 adds r7, #24 - 8002014: 46bd mov sp, r7 - 8002016: bd80 pop {r7, pc} + 8003400: 4618 mov r0, r3 + 8003402: 3718 adds r7, #24 + 8003404: 46bd mov sp, r7 + 8003406: bd80 pop {r7, pc} -08002018 : +08003408 : * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - 8002018: b590 push {r4, r7, lr} - 800201a: b087 sub sp, #28 - 800201c: af00 add r7, sp, #0 - 800201e: 60f8 str r0, [r7, #12] - 8002020: 60b9 str r1, [r7, #8] - 8002022: 607a str r2, [r7, #4] + 8003408: b590 push {r4, r7, lr} + 800340a: b087 sub sp, #28 + 800340c: af00 add r7, sp, #0 + 800340e: 60f8 str r0, [r7, #12] + 8003410: 60b9 str r1, [r7, #8] + 8003412: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 8003414: 2300 movs r3, #0 + 8003416: 617b str r3, [r7, #20] - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Process Locked */ - __HAL_LOCK(hrtc); - 8002024: 68fb ldr r3, [r7, #12] - 8002026: 7f1b ldrb r3, [r3, #28] - 8002028: 2b01 cmp r3, #1 - 800202a: d101 bne.n 8002030 - 800202c: 2302 movs r3, #2 - 800202e: e08d b.n 800214c - 8002030: 68fb ldr r3, [r7, #12] - 8002032: 2201 movs r2, #1 - 8002034: 771a strb r2, [r3, #28] + /* Process Locked */ + __HAL_LOCK(hrtc); + 8003418: 68fb ldr r3, [r7, #12] + 800341a: 7f1b ldrb r3, [r3, #28] + 800341c: 2b01 cmp r3, #1 + 800341e: d101 bne.n 8003424 + 8003420: 2302 movs r3, #2 + 8003422: e094 b.n 800354e + 8003424: 68fb ldr r3, [r7, #12] + 8003426: 2201 movs r2, #1 + 8003428: 771a strb r2, [r3, #28] hrtc->State = HAL_RTC_STATE_BUSY; - 8002036: 68fb ldr r3, [r7, #12] - 8002038: 2202 movs r2, #2 - 800203a: 775a strb r2, [r3, #29] + 800342a: 68fb ldr r3, [r7, #12] + 800342c: 2202 movs r2, #2 + 800342e: 775a strb r2, [r3, #29] - if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) - 800203c: 687b ldr r3, [r7, #4] - 800203e: 2b00 cmp r3, #0 - 8002040: d10e bne.n 8002060 - 8002042: 68bb ldr r3, [r7, #8] - 8002044: 785b ldrb r3, [r3, #1] - 8002046: f003 0310 and.w r3, r3, #16 - 800204a: 2b00 cmp r3, #0 - 800204c: d008 beq.n 8002060 + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + 8003430: 687b ldr r3, [r7, #4] + 8003432: 2b00 cmp r3, #0 + 8003434: d10e bne.n 8003454 + 8003436: 68bb ldr r3, [r7, #8] + 8003438: 785b ldrb r3, [r3, #1] + 800343a: f003 0310 and.w r3, r3, #16 + 800343e: 2b00 cmp r3, #0 + 8003440: d008 beq.n 8003454 { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); - 800204e: 68bb ldr r3, [r7, #8] - 8002050: 785b ldrb r3, [r3, #1] - 8002052: f023 0310 bic.w r3, r3, #16 - 8002056: b2db uxtb r3, r3 - 8002058: 330a adds r3, #10 - 800205a: b2da uxtb r2, r3 - 800205c: 68bb ldr r3, [r7, #8] - 800205e: 705a strb r2, [r3, #1] + 8003442: 68bb ldr r3, [r7, #8] + 8003444: 785b ldrb r3, [r3, #1] + 8003446: f023 0310 bic.w r3, r3, #16 + 800344a: b2db uxtb r3, r3 + 800344c: 330a adds r3, #10 + 800344e: b2da uxtb r2, r3 + 8003450: 68bb ldr r3, [r7, #8] + 8003452: 705a strb r2, [r3, #1] } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if (Format == RTC_FORMAT_BIN) - 8002060: 687b ldr r3, [r7, #4] - 8002062: 2b00 cmp r3, #0 - 8002064: d11c bne.n 80020a0 + if(Format == RTC_FORMAT_BIN) + 8003454: 687b ldr r3, [r7, #4] + 8003456: 2b00 cmp r3, #0 + 8003458: d11c bne.n 8003494 { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - 8002066: 68bb ldr r3, [r7, #8] - 8002068: 78db ldrb r3, [r3, #3] - 800206a: 4618 mov r0, r3 - 800206c: f000 f916 bl 800229c - 8002070: 4603 mov r3, r0 - 8002072: 041c lsls r4, r3, #16 - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ - 8002074: 68bb ldr r3, [r7, #8] - 8002076: 785b ldrb r3, [r3, #1] - 8002078: 4618 mov r0, r3 - 800207a: f000 f90f bl 800229c - 800207e: 4603 mov r3, r0 - 8002080: 021b lsls r3, r3, #8 - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - 8002082: 431c orrs r4, r3 - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - 8002084: 68bb ldr r3, [r7, #8] - 8002086: 789b ldrb r3, [r3, #2] - 8002088: 4618 mov r0, r3 - 800208a: f000 f907 bl 800229c - 800208e: 4603 mov r3, r0 - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ - 8002090: ea44 0203 orr.w r2, r4, r3 - ((uint32_t)sDate->WeekDay << 13U)); - 8002094: 68bb ldr r3, [r7, #8] - 8002096: 781b ldrb r3, [r3, #0] - 8002098: 035b lsls r3, r3, #13 - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - 800209a: 4313 orrs r3, r2 - 800209c: 617b str r3, [r7, #20] - 800209e: e00e b.n 80020be + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ + 800345a: 68bb ldr r3, [r7, #8] + 800345c: 78db ldrb r3, [r3, #3] + 800345e: 4618 mov r0, r3 + 8003460: f000 fa9a bl 8003998 + 8003464: 4603 mov r3, r0 + 8003466: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 8003468: 68bb ldr r3, [r7, #8] + 800346a: 785b ldrb r3, [r3, #1] + 800346c: 4618 mov r0, r3 + 800346e: f000 fa93 bl 8003998 + 8003472: 4603 mov r3, r0 + 8003474: 021b lsls r3, r3, #8 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ + 8003476: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + 8003478: 68bb ldr r3, [r7, #8] + 800347a: 789b ldrb r3, [r3, #2] + 800347c: 4618 mov r0, r3 + 800347e: f000 fa8b bl 8003998 + 8003482: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ + 8003484: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sDate->WeekDay << 13U)); + 8003488: 68bb ldr r3, [r7, #8] + 800348a: 781b ldrb r3, [r3, #0] + 800348c: 035b lsls r3, r3, #13 + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ + 800348e: 4313 orrs r3, r2 + 8003490: 617b str r3, [r7, #20] + 8003492: e00e b.n 80034b2 { assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - 80020a0: 68bb ldr r3, [r7, #8] - 80020a2: 78db ldrb r3, [r3, #3] - 80020a4: 041a lsls r2, r3, #16 + 8003494: 68bb ldr r3, [r7, #8] + 8003496: 78db ldrb r3, [r3, #3] + 8003498: 041a lsls r2, r3, #16 (((uint32_t)sDate->Month) << 8U) | \ - 80020a6: 68bb ldr r3, [r7, #8] - 80020a8: 785b ldrb r3, [r3, #1] - 80020aa: 021b lsls r3, r3, #8 + 800349a: 68bb ldr r3, [r7, #8] + 800349c: 785b ldrb r3, [r3, #1] + 800349e: 021b lsls r3, r3, #8 datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - 80020ac: 4313 orrs r3, r2 + 80034a0: 4313 orrs r3, r2 ((uint32_t)sDate->Date) | \ - 80020ae: 68ba ldr r2, [r7, #8] - 80020b0: 7892 ldrb r2, [r2, #2] + 80034a2: 68ba ldr r2, [r7, #8] + 80034a4: 7892 ldrb r2, [r2, #2] (((uint32_t)sDate->Month) << 8U) | \ - 80020b2: 431a orrs r2, r3 + 80034a6: 431a orrs r2, r3 (((uint32_t)sDate->WeekDay) << 13U)); - 80020b4: 68bb ldr r3, [r7, #8] - 80020b6: 781b ldrb r3, [r3, #0] - 80020b8: 035b lsls r3, r3, #13 + 80034a8: 68bb ldr r3, [r7, #8] + 80034aa: 781b ldrb r3, [r3, #0] + 80034ac: 035b lsls r3, r3, #13 datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - 80020ba: 4313 orrs r3, r2 - 80020bc: 617b str r3, [r7, #20] + 80034ae: 4313 orrs r3, r2 + 80034b0: 617b str r3, [r7, #20] } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - 80020be: 68fb ldr r3, [r7, #12] - 80020c0: 681b ldr r3, [r3, #0] - 80020c2: 22ca movs r2, #202 ; 0xca - 80020c4: 625a str r2, [r3, #36] ; 0x24 - 80020c6: 68fb ldr r3, [r7, #12] - 80020c8: 681b ldr r3, [r3, #0] - 80020ca: 2253 movs r2, #83 ; 0x53 - 80020cc: 625a str r2, [r3, #36] ; 0x24 + 80034b2: 68fb ldr r3, [r7, #12] + 80034b4: 681b ldr r3, [r3, #0] + 80034b6: 22ca movs r2, #202 ; 0xca + 80034b8: 625a str r2, [r3, #36] ; 0x24 + 80034ba: 68fb ldr r3, [r7, #12] + 80034bc: 681b ldr r3, [r3, #0] + 80034be: 2253 movs r2, #83 ; 0x53 + 80034c0: 625a str r2, [r3, #36] ; 0x24 /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - 80020ce: 68f8 ldr r0, [r7, #12] - 80020d0: f000 f8ba bl 8002248 - 80020d4: 4603 mov r3, r0 - 80020d6: 2b00 cmp r3, #0 - 80020d8: d00b beq.n 80020f2 + if(RTC_EnterInitMode(hrtc) != HAL_OK) + 80034c2: 68f8 ldr r0, [r7, #12] + 80034c4: f000 fa3c bl 8003940 + 80034c8: 4603 mov r3, r0 + 80034ca: 2b00 cmp r3, #0 + 80034cc: d00b beq.n 80034e6 { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 80020da: 68fb ldr r3, [r7, #12] - 80020dc: 681b ldr r3, [r3, #0] - 80020de: 22ff movs r2, #255 ; 0xff - 80020e0: 625a str r2, [r3, #36] ; 0x24 + 80034ce: 68fb ldr r3, [r7, #12] + 80034d0: 681b ldr r3, [r3, #0] + 80034d2: 22ff movs r2, #255 ; 0xff + 80034d4: 625a str r2, [r3, #36] ; 0x24 /* Set RTC state*/ hrtc->State = HAL_RTC_STATE_ERROR; - 80020e2: 68fb ldr r3, [r7, #12] - 80020e4: 2204 movs r2, #4 - 80020e6: 775a strb r2, [r3, #29] + 80034d6: 68fb ldr r3, [r7, #12] + 80034d8: 2204 movs r2, #4 + 80034da: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); - 80020e8: 68fb ldr r3, [r7, #12] - 80020ea: 2200 movs r2, #0 - 80020ec: 771a strb r2, [r3, #28] + 80034dc: 68fb ldr r3, [r7, #12] + 80034de: 2200 movs r2, #0 + 80034e0: 771a strb r2, [r3, #28] return HAL_ERROR; - 80020ee: 2301 movs r3, #1 - 80020f0: e02c b.n 800214c + 80034e2: 2301 movs r3, #1 + 80034e4: e033 b.n 800354e } else { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - 80020f2: 68fb ldr r3, [r7, #12] - 80020f4: 681a ldr r2, [r3, #0] - 80020f6: 697b ldr r3, [r7, #20] - 80020f8: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 - 80020fc: f023 03c0 bic.w r3, r3, #192 ; 0xc0 - 8002100: 6053 str r3, [r2, #4] + 80034e6: 68fb ldr r3, [r7, #12] + 80034e8: 681a ldr r2, [r3, #0] + 80034ea: 697b ldr r3, [r7, #20] + 80034ec: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 + 80034f0: f023 03c0 bic.w r3, r3, #192 ; 0xc0 + 80034f4: 6053 str r3, [r2, #4] /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - 8002102: 68fb ldr r3, [r7, #12] - 8002104: 681b ldr r3, [r3, #0] - 8002106: 68da ldr r2, [r3, #12] - 8002108: 68fb ldr r3, [r7, #12] - 800210a: 681b ldr r3, [r3, #0] - 800210c: f022 0280 bic.w r2, r2, #128 ; 0x80 - 8002110: 60da str r2, [r3, #12] + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + 80034f6: 68fb ldr r3, [r7, #12] + 80034f8: 681b ldr r3, [r3, #0] + 80034fa: 68da ldr r2, [r3, #12] + 80034fc: 68fb ldr r3, [r7, #12] + 80034fe: 681b ldr r3, [r3, #0] + 8003500: f022 0280 bic.w r2, r2, #128 ; 0x80 + 8003504: 60da str r2, [r3, #12] - /* Wait for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - 8002112: 68f8 ldr r0, [r7, #12] - 8002114: f000 f86b bl 80021ee - 8002118: 4603 mov r3, r0 - 800211a: 2b00 cmp r3, #0 - 800211c: d00b beq.n 8002136 + /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + 8003506: 68fb ldr r3, [r7, #12] + 8003508: 681b ldr r3, [r3, #0] + 800350a: 689b ldr r3, [r3, #8] + 800350c: f003 0320 and.w r3, r3, #32 + 8003510: 2b00 cmp r3, #0 + 8003512: d111 bne.n 8003538 { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 800211e: 68fb ldr r3, [r7, #12] - 8002120: 681b ldr r3, [r3, #0] - 8002122: 22ff movs r2, #255 ; 0xff - 8002124: 625a str r2, [r3, #36] ; 0x24 + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8003514: 68f8 ldr r0, [r7, #12] + 8003516: f000 f9eb bl 80038f0 + 800351a: 4603 mov r3, r0 + 800351c: 2b00 cmp r3, #0 + 800351e: d00b beq.n 8003538 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003520: 68fb ldr r3, [r7, #12] + 8003522: 681b ldr r3, [r3, #0] + 8003524: 22ff movs r2, #255 ; 0xff + 8003526: 625a str r2, [r3, #36] ; 0x24 - hrtc->State = HAL_RTC_STATE_ERROR; - 8002126: 68fb ldr r3, [r7, #12] - 8002128: 2204 movs r2, #4 - 800212a: 775a strb r2, [r3, #29] + hrtc->State = HAL_RTC_STATE_ERROR; + 8003528: 68fb ldr r3, [r7, #12] + 800352a: 2204 movs r2, #4 + 800352c: 775a strb r2, [r3, #29] - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - 800212c: 68fb ldr r3, [r7, #12] - 800212e: 2200 movs r2, #0 - 8002130: 771a strb r2, [r3, #28] + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 800352e: 68fb ldr r3, [r7, #12] + 8003530: 2200 movs r2, #0 + 8003532: 771a strb r2, [r3, #28] - return HAL_ERROR; - 8002132: 2301 movs r3, #1 - 8002134: e00a b.n 800214c + return HAL_ERROR; + 8003534: 2301 movs r3, #1 + 8003536: e00a b.n 800354e + } } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - 8002136: 68fb ldr r3, [r7, #12] - 8002138: 681b ldr r3, [r3, #0] - 800213a: 22ff movs r2, #255 ; 0xff - 800213c: 625a str r2, [r3, #36] ; 0x24 + 8003538: 68fb ldr r3, [r7, #12] + 800353a: 681b ldr r3, [r3, #0] + 800353c: 22ff movs r2, #255 ; 0xff + 800353e: 625a str r2, [r3, #36] ; 0x24 hrtc->State = HAL_RTC_STATE_READY ; - 800213e: 68fb ldr r3, [r7, #12] - 8002140: 2201 movs r2, #1 - 8002142: 775a strb r2, [r3, #29] + 8003540: 68fb ldr r3, [r7, #12] + 8003542: 2201 movs r2, #1 + 8003544: 775a strb r2, [r3, #29] /* Process Unlocked */ __HAL_UNLOCK(hrtc); - 8002144: 68fb ldr r3, [r7, #12] - 8002146: 2200 movs r2, #0 - 8002148: 771a strb r2, [r3, #28] + 8003546: 68fb ldr r3, [r7, #12] + 8003548: 2200 movs r2, #0 + 800354a: 771a strb r2, [r3, #28] return HAL_OK; - 800214a: 2300 movs r3, #0 + 800354c: 2300 movs r3, #0 } } - 800214c: 4618 mov r0, r3 - 800214e: 371c adds r7, #28 - 8002150: 46bd mov sp, r7 - 8002152: bd90 pop {r4, r7, pc} + 800354e: 4618 mov r0, r3 + 8003550: 371c adds r7, #28 + 8003552: 46bd mov sp, r7 + 8003554: bd90 pop {r4, r7, pc} -08002154 : +08003556 : * in the higher-order calendar shadow registers to ensure consistency between the time and date values. * Reading RTC current time locks the values in calendar shadow registers until Current date is read. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { - 8002154: b580 push {r7, lr} - 8002156: b086 sub sp, #24 - 8002158: af00 add r7, sp, #0 - 800215a: 60f8 str r0, [r7, #12] - 800215c: 60b9 str r1, [r7, #8] - 800215e: 607a str r2, [r7, #4] + 8003556: b580 push {r7, lr} + 8003558: b086 sub sp, #24 + 800355a: af00 add r7, sp, #0 + 800355c: 60f8 str r0, [r7, #12] + 800355e: 60b9 str r1, [r7, #8] + 8003560: 607a str r2, [r7, #4] + uint32_t datetmpreg = 0U; + 8003562: 2300 movs r3, #0 + 8003564: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); /* Get the DR register */ datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - 8002160: 68fb ldr r3, [r7, #12] - 8002162: 681b ldr r3, [r3, #0] - 8002164: 685b ldr r3, [r3, #4] - 8002166: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 - 800216a: f023 03c0 bic.w r3, r3, #192 ; 0xc0 - 800216e: 617b str r3, [r7, #20] + 8003566: 68fb ldr r3, [r7, #12] + 8003568: 681b ldr r3, [r3, #0] + 800356a: 685b ldr r3, [r3, #4] + 800356c: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000 + 8003570: f023 03c0 bic.w r3, r3, #192 ; 0xc0 + 8003574: 617b str r3, [r7, #20] /* Fill the structure fields with the read parameters */ sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); - 8002170: 697b ldr r3, [r7, #20] - 8002172: 0c1b lsrs r3, r3, #16 - 8002174: b2da uxtb r2, r3 - 8002176: 68bb ldr r3, [r7, #8] - 8002178: 70da strb r2, [r3, #3] + 8003576: 697b ldr r3, [r7, #20] + 8003578: 0c1b lsrs r3, r3, #16 + 800357a: b2da uxtb r2, r3 + 800357c: 68bb ldr r3, [r7, #8] + 800357e: 70da strb r2, [r3, #3] sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - 800217a: 697b ldr r3, [r7, #20] - 800217c: 0a1b lsrs r3, r3, #8 - 800217e: b2db uxtb r3, r3 - 8002180: f003 031f and.w r3, r3, #31 - 8002184: b2da uxtb r2, r3 - 8002186: 68bb ldr r3, [r7, #8] - 8002188: 705a strb r2, [r3, #1] + 8003580: 697b ldr r3, [r7, #20] + 8003582: 0a1b lsrs r3, r3, #8 + 8003584: b2db uxtb r3, r3 + 8003586: f003 031f and.w r3, r3, #31 + 800358a: b2da uxtb r2, r3 + 800358c: 68bb ldr r3, [r7, #8] + 800358e: 705a strb r2, [r3, #1] sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - 800218a: 697b ldr r3, [r7, #20] - 800218c: b2db uxtb r3, r3 - 800218e: f003 033f and.w r3, r3, #63 ; 0x3f - 8002192: b2da uxtb r2, r3 - 8002194: 68bb ldr r3, [r7, #8] - 8002196: 709a strb r2, [r3, #2] + 8003590: 697b ldr r3, [r7, #20] + 8003592: b2db uxtb r3, r3 + 8003594: f003 033f and.w r3, r3, #63 ; 0x3f + 8003598: b2da uxtb r2, r3 + 800359a: 68bb ldr r3, [r7, #8] + 800359c: 709a strb r2, [r3, #2] sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); - 8002198: 697b ldr r3, [r7, #20] - 800219a: 0b5b lsrs r3, r3, #13 - 800219c: b2db uxtb r3, r3 - 800219e: f003 0307 and.w r3, r3, #7 - 80021a2: b2da uxtb r2, r3 - 80021a4: 68bb ldr r3, [r7, #8] - 80021a6: 701a strb r2, [r3, #0] + 800359e: 697b ldr r3, [r7, #20] + 80035a0: 0b5b lsrs r3, r3, #13 + 80035a2: b2db uxtb r3, r3 + 80035a4: f003 0307 and.w r3, r3, #7 + 80035a8: b2da uxtb r2, r3 + 80035aa: 68bb ldr r3, [r7, #8] + 80035ac: 701a strb r2, [r3, #0] /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - 80021a8: 687b ldr r3, [r7, #4] - 80021aa: 2b00 cmp r3, #0 - 80021ac: d11a bne.n 80021e4 + if(Format == RTC_FORMAT_BIN) + 80035ae: 687b ldr r3, [r7, #4] + 80035b0: 2b00 cmp r3, #0 + 80035b2: d11a bne.n 80035ea { /* Convert the date structure parameters to Binary format */ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - 80021ae: 68bb ldr r3, [r7, #8] - 80021b0: 78db ldrb r3, [r3, #3] - 80021b2: 4618 mov r0, r3 - 80021b4: f000 f891 bl 80022da - 80021b8: 4603 mov r3, r0 - 80021ba: 461a mov r2, r3 - 80021bc: 68bb ldr r3, [r7, #8] - 80021be: 70da strb r2, [r3, #3] + 80035b4: 68bb ldr r3, [r7, #8] + 80035b6: 78db ldrb r3, [r3, #3] + 80035b8: 4618 mov r0, r3 + 80035ba: f000 fa0b bl 80039d4 + 80035be: 4603 mov r3, r0 + 80035c0: 461a mov r2, r3 + 80035c2: 68bb ldr r3, [r7, #8] + 80035c4: 70da strb r2, [r3, #3] sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - 80021c0: 68bb ldr r3, [r7, #8] - 80021c2: 785b ldrb r3, [r3, #1] - 80021c4: 4618 mov r0, r3 - 80021c6: f000 f888 bl 80022da - 80021ca: 4603 mov r3, r0 - 80021cc: 461a mov r2, r3 - 80021ce: 68bb ldr r3, [r7, #8] - 80021d0: 705a strb r2, [r3, #1] + 80035c6: 68bb ldr r3, [r7, #8] + 80035c8: 785b ldrb r3, [r3, #1] + 80035ca: 4618 mov r0, r3 + 80035cc: f000 fa02 bl 80039d4 + 80035d0: 4603 mov r3, r0 + 80035d2: 461a mov r2, r3 + 80035d4: 68bb ldr r3, [r7, #8] + 80035d6: 705a strb r2, [r3, #1] sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - 80021d2: 68bb ldr r3, [r7, #8] - 80021d4: 789b ldrb r3, [r3, #2] - 80021d6: 4618 mov r0, r3 - 80021d8: f000 f87f bl 80022da - 80021dc: 4603 mov r3, r0 - 80021de: 461a mov r2, r3 - 80021e0: 68bb ldr r3, [r7, #8] - 80021e2: 709a strb r2, [r3, #2] + 80035d8: 68bb ldr r3, [r7, #8] + 80035da: 789b ldrb r3, [r3, #2] + 80035dc: 4618 mov r0, r3 + 80035de: f000 f9f9 bl 80039d4 + 80035e2: 4603 mov r3, r0 + 80035e4: 461a mov r2, r3 + 80035e6: 68bb ldr r3, [r7, #8] + 80035e8: 709a strb r2, [r3, #2] } return HAL_OK; - 80021e4: 2300 movs r3, #0 + 80035ea: 2300 movs r3, #0 } - 80021e6: 4618 mov r0, r3 - 80021e8: 3718 adds r7, #24 - 80021ea: 46bd mov sp, r7 - 80021ec: bd80 pop {r7, pc} + 80035ec: 4618 mov r0, r3 + 80035ee: 3718 adds r7, #24 + 80035f0: 46bd mov sp, r7 + 80035f2: bd80 pop {r7, pc} -080021ee : - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc RTC handle +080035f4 : + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - 80021ee: b580 push {r7, lr} - 80021f0: b084 sub sp, #16 - 80021f2: af00 add r7, sp, #0 - 80021f4: 6078 str r0, [r7, #4] - uint32_t tickstart; + 80035f4: b590 push {r4, r7, lr} + 80035f6: b089 sub sp, #36 ; 0x24 + 80035f8: af00 add r7, sp, #0 + 80035fa: 60f8 str r0, [r7, #12] + 80035fc: 60b9 str r1, [r7, #8] + 80035fe: 607a str r2, [r7, #4] + uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + 8003600: 2300 movs r3, #0 + 8003602: 61fb str r3, [r7, #28] + 8003604: 2300 movs r3, #0 + 8003606: 61bb str r3, [r7, #24] + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ; + 8003608: 4b93 ldr r3, [pc, #588] ; (8003858 ) + 800360a: 681b ldr r3, [r3, #0] + 800360c: 4a93 ldr r2, [pc, #588] ; (800385c ) + 800360e: fba2 2303 umull r2, r3, r2, r3 + 8003612: 0adb lsrs r3, r3, #11 + 8003614: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8003618: fb02 f303 mul.w r3, r2, r3 + 800361c: 617b str r3, [r7, #20] + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - 80021f6: 687b ldr r3, [r7, #4] - 80021f8: 681b ldr r3, [r3, #0] - 80021fa: 689b ldr r3, [r3, #8] - 80021fc: f003 0320 and.w r3, r3, #32 - 8002200: 2b00 cmp r3, #0 - 8002202: d11c bne.n 800223e -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ + /* Process Locked */ + __HAL_LOCK(hrtc); + 800361e: 68fb ldr r3, [r7, #12] + 8003620: 7f1b ldrb r3, [r3, #28] + 8003622: 2b01 cmp r3, #1 + 8003624: d101 bne.n 800362a + 8003626: 2302 movs r3, #2 + 8003628: e111 b.n 800384e + 800362a: 68fb ldr r3, [r7, #12] + 800362c: 2201 movs r2, #1 + 800362e: 771a strb r2, [r3, #28] + + hrtc->State = HAL_RTC_STATE_BUSY; + 8003630: 68fb ldr r3, [r7, #12] + 8003632: 2202 movs r2, #2 + 8003634: 775a strb r2, [r3, #29] + + if(Format == RTC_FORMAT_BIN) + 8003636: 687b ldr r3, [r7, #4] + 8003638: 2b00 cmp r3, #0 + 800363a: d137 bne.n 80036ac { - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - 8002204: 687b ldr r3, [r7, #4] - 8002206: 681b ldr r3, [r3, #0] - 8002208: 68da ldr r2, [r3, #12] - 800220a: 687b ldr r3, [r7, #4] - 800220c: 681b ldr r3, [r3, #0] - 800220e: f022 02a0 bic.w r2, r2, #160 ; 0xa0 - 8002212: 60da str r2, [r3, #12] - - tickstart = HAL_GetTick(); - 8002214: f7fe fc1c bl 8000a50 - 8002218: 60f8 str r0, [r7, #12] - - /* Wait the registers to be synchronised */ - while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) - 800221a: e009 b.n 8002230 + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 800363c: 68fb ldr r3, [r7, #12] + 800363e: 681b ldr r3, [r3, #0] + 8003640: 689b ldr r3, [r3, #8] + 8003642: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003646: 2b00 cmp r3, #0 + 8003648: d102 bne.n 8003650 + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 800221c: f7fe fc18 bl 8000a50 - 8002220: 4602 mov r2, r0 - 8002222: 68fb ldr r3, [r7, #12] - 8002224: 1ad3 subs r3, r2, r3 - 8002226: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 - 800222a: d901 bls.n 8002230 + sAlarm->AlarmTime.TimeFormat = 0x00U; + 800364a: 68bb ldr r3, [r7, #8] + 800364c: 2200 movs r2, #0 + 800364e: 70da strb r2, [r3, #3] + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + 8003650: 68bb ldr r3, [r7, #8] + 8003652: 781b ldrb r3, [r3, #0] + 8003654: 4618 mov r0, r3 + 8003656: f000 f99f bl 8003998 + 800365a: 4603 mov r3, r0 + 800365c: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 800365e: 68bb ldr r3, [r7, #8] + 8003660: 785b ldrb r3, [r3, #1] + 8003662: 4618 mov r0, r3 + 8003664: f000 f998 bl 8003998 + 8003668: 4603 mov r3, r0 + 800366a: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + 800366c: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 800366e: 68bb ldr r3, [r7, #8] + 8003670: 789b ldrb r3, [r3, #2] + 8003672: 4618 mov r0, r3 + 8003674: f000 f990 bl 8003998 + 8003678: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ + 800367a: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 800367e: 68bb ldr r3, [r7, #8] + 8003680: 78db ldrb r3, [r3, #3] + 8003682: 041b lsls r3, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + 8003684: ea42 0403 orr.w r4, r2, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 8003688: 68bb ldr r3, [r7, #8] + 800368a: f893 3020 ldrb.w r3, [r3, #32] + 800368e: 4618 mov r0, r3 + 8003690: f000 f982 bl 8003998 + 8003694: 4603 mov r3, r0 + 8003696: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 8003698: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 800369c: 68bb ldr r3, [r7, #8] + 800369e: 69db ldr r3, [r3, #28] + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ + 80036a0: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 80036a2: 68bb ldr r3, [r7, #8] + 80036a4: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ + 80036a6: 4313 orrs r3, r2 + 80036a8: 61fb str r3, [r7, #28] + 80036aa: e023 b.n 80036f4 + } + else + { + if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + 80036ac: 68fb ldr r3, [r7, #12] + 80036ae: 681b ldr r3, [r3, #0] + 80036b0: 689b ldr r3, [r3, #8] + 80036b2: f003 0340 and.w r3, r3, #64 ; 0x40 + 80036b6: 2b00 cmp r3, #0 + 80036b8: d102 bne.n 80036c0 + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 80036ba: 68bb ldr r3, [r7, #8] + 80036bc: 2200 movs r2, #0 + 80036be: 70da strb r2, [r3, #3] + } + else + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + 80036c0: 68bb ldr r3, [r7, #8] + 80036c2: 781b ldrb r3, [r3, #0] + 80036c4: 041a lsls r2, r3, #16 + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 80036c6: 68bb ldr r3, [r7, #8] + 80036c8: 785b ldrb r3, [r3, #1] + 80036ca: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + 80036cc: 4313 orrs r3, r2 + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 80036ce: 68ba ldr r2, [r7, #8] + 80036d0: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ + 80036d2: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 80036d4: 68bb ldr r3, [r7, #8] + 80036d6: 78db ldrb r3, [r3, #3] + 80036d8: 041b lsls r3, r3, #16 + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + 80036da: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 80036dc: 68bb ldr r3, [r7, #8] + 80036de: f893 3020 ldrb.w r3, [r3, #32] + 80036e2: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ + 80036e4: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 80036e6: 68bb ldr r3, [r7, #8] + 80036e8: 69db ldr r3, [r3, #28] + ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ + 80036ea: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 80036ec: 68bb ldr r3, [r7, #8] + 80036ee: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ + 80036f0: 4313 orrs r3, r2 + 80036f2: 61fb str r3, [r7, #28] + } + /* Configure the Alarm A or Alarm B Sub Second registers */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + 80036f4: 68bb ldr r3, [r7, #8] + 80036f6: 685a ldr r2, [r3, #4] + 80036f8: 68bb ldr r3, [r7, #8] + 80036fa: 699b ldr r3, [r3, #24] + 80036fc: 4313 orrs r3, r2 + 80036fe: 61bb str r3, [r7, #24] + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8003700: 68fb ldr r3, [r7, #12] + 8003702: 681b ldr r3, [r3, #0] + 8003704: 22ca movs r2, #202 ; 0xca + 8003706: 625a str r2, [r3, #36] ; 0x24 + 8003708: 68fb ldr r3, [r7, #12] + 800370a: 681b ldr r3, [r3, #0] + 800370c: 2253 movs r2, #83 ; 0x53 + 800370e: 625a str r2, [r3, #36] ; 0x24 + + /* Configure the Alarm register */ + if(sAlarm->Alarm == RTC_ALARM_A) + 8003710: 68bb ldr r3, [r7, #8] + 8003712: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003714: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8003718: d141 bne.n 800379e + { + /* Disable the Alarm A interrupt */ + __HAL_RTC_ALARMA_DISABLE(hrtc); + 800371a: 68fb ldr r3, [r7, #12] + 800371c: 681b ldr r3, [r3, #0] + 800371e: 689a ldr r2, [r3, #8] + 8003720: 68fb ldr r3, [r7, #12] + 8003722: 681b ldr r3, [r3, #0] + 8003724: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8003728: 609a str r2, [r3, #8] + + /* Clear flag alarm A */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + 800372a: 68fb ldr r3, [r7, #12] + 800372c: 681b ldr r3, [r3, #0] + 800372e: 68db ldr r3, [r3, #12] + 8003730: b2da uxtb r2, r3 + 8003732: 68fb ldr r3, [r7, #12] + 8003734: 681b ldr r3, [r3, #0] + 8003736: f462 72c0 orn r2, r2, #384 ; 0x180 + 800373a: 60da str r2, [r3, #12] + + /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + do + { + if (count-- == 0U) + 800373c: 697b ldr r3, [r7, #20] + 800373e: 1e5a subs r2, r3, #1 + 8003740: 617a str r2, [r7, #20] + 8003742: 2b00 cmp r3, #0 + 8003744: d10b bne.n 800375e { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003746: 68fb ldr r3, [r7, #12] + 8003748: 681b ldr r3, [r3, #0] + 800374a: 22ff movs r2, #255 ; 0xff + 800374c: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 800374e: 68fb ldr r3, [r7, #12] + 8003750: 2203 movs r2, #3 + 8003752: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003754: 68fb ldr r3, [r7, #12] + 8003756: 2200 movs r2, #0 + 8003758: 771a strb r2, [r3, #28] + return HAL_TIMEOUT; - 800222c: 2303 movs r3, #3 - 800222e: e007 b.n 8002240 - while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) - 8002230: 687b ldr r3, [r7, #4] - 8002232: 681b ldr r3, [r3, #0] - 8002234: 68db ldr r3, [r3, #12] - 8002236: f003 0320 and.w r3, r3, #32 - 800223a: 2b00 cmp r3, #0 - 800223c: d0ee beq.n 800221c + 800375a: 2303 movs r3, #3 + 800375c: e077 b.n 800384e } } + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET); + 800375e: 68fb ldr r3, [r7, #12] + 8003760: 681b ldr r3, [r3, #0] + 8003762: 68db ldr r3, [r3, #12] + 8003764: f003 0301 and.w r3, r3, #1 + 8003768: 2b00 cmp r3, #0 + 800376a: d0e7 beq.n 800373c + + hrtc->Instance->ALRMAR = (uint32_t)tmpreg; + 800376c: 68fb ldr r3, [r7, #12] + 800376e: 681b ldr r3, [r3, #0] + 8003770: 69fa ldr r2, [r7, #28] + 8003772: 61da str r2, [r3, #28] + /* Configure the Alarm A Sub Second register */ + hrtc->Instance->ALRMASSR = subsecondtmpreg; + 8003774: 68fb ldr r3, [r7, #12] + 8003776: 681b ldr r3, [r3, #0] + 8003778: 69ba ldr r2, [r7, #24] + 800377a: 645a str r2, [r3, #68] ; 0x44 + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMA_ENABLE(hrtc); + 800377c: 68fb ldr r3, [r7, #12] + 800377e: 681b ldr r3, [r3, #0] + 8003780: 689a ldr r2, [r3, #8] + 8003782: 68fb ldr r3, [r7, #12] + 8003784: 681b ldr r3, [r3, #0] + 8003786: f442 7280 orr.w r2, r2, #256 ; 0x100 + 800378a: 609a str r2, [r3, #8] + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); + 800378c: 68fb ldr r3, [r7, #12] + 800378e: 681b ldr r3, [r3, #0] + 8003790: 689a ldr r2, [r3, #8] + 8003792: 68fb ldr r3, [r7, #12] + 8003794: 681b ldr r3, [r3, #0] + 8003796: f442 5280 orr.w r2, r2, #4096 ; 0x1000 + 800379a: 609a str r2, [r3, #8] + 800379c: e040 b.n 8003820 + } + else + { + /* Disable the Alarm B interrupt */ + __HAL_RTC_ALARMB_DISABLE(hrtc); + 800379e: 68fb ldr r3, [r7, #12] + 80037a0: 681b ldr r3, [r3, #0] + 80037a2: 689a ldr r2, [r3, #8] + 80037a4: 68fb ldr r3, [r7, #12] + 80037a6: 681b ldr r3, [r3, #0] + 80037a8: f422 7200 bic.w r2, r2, #512 ; 0x200 + 80037ac: 609a str r2, [r3, #8] + + /* Clear flag alarm B */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + 80037ae: 68fb ldr r3, [r7, #12] + 80037b0: 681b ldr r3, [r3, #0] + 80037b2: 68db ldr r3, [r3, #12] + 80037b4: b2da uxtb r2, r3 + 80037b6: 68fb ldr r3, [r7, #12] + 80037b8: 681b ldr r3, [r3, #0] + 80037ba: f462 7220 orn r2, r2, #640 ; 0x280 + 80037be: 60da str r2, [r3, #12] + + /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + do + { + if (count-- == 0U) + 80037c0: 697b ldr r3, [r7, #20] + 80037c2: 1e5a subs r2, r3, #1 + 80037c4: 617a str r2, [r7, #20] + 80037c6: 2b00 cmp r3, #0 + 80037c8: d10b bne.n 80037e2 + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80037ca: 68fb ldr r3, [r7, #12] + 80037cc: 681b ldr r3, [r3, #0] + 80037ce: 22ff movs r2, #255 ; 0xff + 80037d0: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 80037d2: 68fb ldr r3, [r7, #12] + 80037d4: 2203 movs r2, #3 + 80037d6: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 80037d8: 68fb ldr r3, [r7, #12] + 80037da: 2200 movs r2, #0 + 80037dc: 771a strb r2, [r3, #28] + + return HAL_TIMEOUT; + 80037de: 2303 movs r3, #3 + 80037e0: e035 b.n 800384e + } + } + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET); + 80037e2: 68fb ldr r3, [r7, #12] + 80037e4: 681b ldr r3, [r3, #0] + 80037e6: 68db ldr r3, [r3, #12] + 80037e8: f003 0302 and.w r3, r3, #2 + 80037ec: 2b00 cmp r3, #0 + 80037ee: d0e7 beq.n 80037c0 + + hrtc->Instance->ALRMBR = (uint32_t)tmpreg; + 80037f0: 68fb ldr r3, [r7, #12] + 80037f2: 681b ldr r3, [r3, #0] + 80037f4: 69fa ldr r2, [r7, #28] + 80037f6: 621a str r2, [r3, #32] + /* Configure the Alarm B Sub Second register */ + hrtc->Instance->ALRMBSSR = subsecondtmpreg; + 80037f8: 68fb ldr r3, [r7, #12] + 80037fa: 681b ldr r3, [r3, #0] + 80037fc: 69ba ldr r2, [r7, #24] + 80037fe: 649a str r2, [r3, #72] ; 0x48 + /* Configure the Alarm state: Enable Alarm */ + __HAL_RTC_ALARMB_ENABLE(hrtc); + 8003800: 68fb ldr r3, [r7, #12] + 8003802: 681b ldr r3, [r3, #0] + 8003804: 689a ldr r2, [r3, #8] + 8003806: 68fb ldr r3, [r7, #12] + 8003808: 681b ldr r3, [r3, #0] + 800380a: f442 7200 orr.w r2, r2, #512 ; 0x200 + 800380e: 609a str r2, [r3, #8] + /* Configure the Alarm interrupt */ + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); + 8003810: 68fb ldr r3, [r7, #12] + 8003812: 681b ldr r3, [r3, #0] + 8003814: 689a ldr r2, [r3, #8] + 8003816: 68fb ldr r3, [r7, #12] + 8003818: 681b ldr r3, [r3, #0] + 800381a: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 800381e: 609a str r2, [r3, #8] + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + 8003820: 4b0f ldr r3, [pc, #60] ; (8003860 ) + 8003822: 681b ldr r3, [r3, #0] + 8003824: 4a0e ldr r2, [pc, #56] ; (8003860 ) + 8003826: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800382a: 6013 str r3, [r2, #0] + + EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + 800382c: 4b0c ldr r3, [pc, #48] ; (8003860 ) + 800382e: 689b ldr r3, [r3, #8] + 8003830: 4a0b ldr r2, [pc, #44] ; (8003860 ) + 8003832: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8003836: 6093 str r3, [r2, #8] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8003838: 68fb ldr r3, [r7, #12] + 800383a: 681b ldr r3, [r3, #0] + 800383c: 22ff movs r2, #255 ; 0xff + 800383e: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8003840: 68fb ldr r3, [r7, #12] + 8003842: 2201 movs r2, #1 + 8003844: 775a strb r2, [r3, #29] + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8003846: 68fb ldr r3, [r7, #12] + 8003848: 2200 movs r2, #0 + 800384a: 771a strb r2, [r3, #28] + + return HAL_OK; + 800384c: 2300 movs r3, #0 +} + 800384e: 4618 mov r0, r3 + 8003850: 3724 adds r7, #36 ; 0x24 + 8003852: 46bd mov sp, r7 + 8003854: bd90 pop {r4, r7, pc} + 8003856: bf00 nop + 8003858: 20000014 .word 0x20000014 + 800385c: 10624dd3 .word 0x10624dd3 + 8003860: 40013c00 .word 0x40013c00 + +08003864 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +{ + 8003864: b580 push {r7, lr} + 8003866: b082 sub sp, #8 + 8003868: af00 add r7, sp, #0 + 800386a: 6078 str r0, [r7, #4] + /* Get the AlarmA interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET) + 800386c: 687b ldr r3, [r7, #4] + 800386e: 681b ldr r3, [r3, #0] + 8003870: 689b ldr r3, [r3, #8] + 8003872: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8003876: 2b00 cmp r3, #0 + 8003878: d012 beq.n 80038a0 + { + /* Get the pending status of the AlarmA Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) + 800387a: 687b ldr r3, [r7, #4] + 800387c: 681b ldr r3, [r3, #0] + 800387e: 68db ldr r3, [r3, #12] + 8003880: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003884: 2b00 cmp r3, #0 + 8003886: d00b beq.n 80038a0 + { + /* AlarmA callback */ + #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmAEventCallback(hrtc); + #else + HAL_RTC_AlarmAEventCallback(hrtc); + 8003888: 6878 ldr r0, [r7, #4] + 800388a: f7fe fa35 bl 8001cf8 + #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the AlarmA interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + 800388e: 687b ldr r3, [r7, #4] + 8003890: 681b ldr r3, [r3, #0] + 8003892: 68db ldr r3, [r3, #12] + 8003894: b2da uxtb r2, r3 + 8003896: 687b ldr r3, [r7, #4] + 8003898: 681b ldr r3, [r3, #0] + 800389a: f462 72c0 orn r2, r2, #384 ; 0x180 + 800389e: 60da str r2, [r3, #12] + } + } + + /* Get the AlarmB interrupt source enable status */ + if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET) + 80038a0: 687b ldr r3, [r7, #4] + 80038a2: 681b ldr r3, [r3, #0] + 80038a4: 689b ldr r3, [r3, #8] + 80038a6: f403 5300 and.w r3, r3, #8192 ; 0x2000 + 80038aa: 2b00 cmp r3, #0 + 80038ac: d012 beq.n 80038d4 + { + /* Get the pending status of the AlarmB Interrupt */ + if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET) + 80038ae: 687b ldr r3, [r7, #4] + 80038b0: 681b ldr r3, [r3, #0] + 80038b2: 68db ldr r3, [r3, #12] + 80038b4: f403 7300 and.w r3, r3, #512 ; 0x200 + 80038b8: 2b00 cmp r3, #0 + 80038ba: d00b beq.n 80038d4 + { + /* AlarmB callback */ + #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + hrtc->AlarmBEventCallback(hrtc); + #else + HAL_RTCEx_AlarmBEventCallback(hrtc); + 80038bc: 6878 ldr r0, [r7, #4] + 80038be: f000 f8a7 bl 8003a10 + #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + + /* Clear the AlarmB interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); + 80038c2: 687b ldr r3, [r7, #4] + 80038c4: 681b ldr r3, [r3, #0] + 80038c6: 68db ldr r3, [r3, #12] + 80038c8: b2da uxtb r2, r3 + 80038ca: 687b ldr r3, [r7, #4] + 80038cc: 681b ldr r3, [r3, #0] + 80038ce: f462 7220 orn r2, r2, #640 ; 0x280 + 80038d2: 60da str r2, [r3, #12] + } + } + + /* Clear the EXTI's line Flag for RTC Alarm */ + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); + 80038d4: 4b05 ldr r3, [pc, #20] ; (80038ec ) + 80038d6: f44f 3200 mov.w r2, #131072 ; 0x20000 + 80038da: 615a str r2, [r3, #20] + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 80038dc: 687b ldr r3, [r7, #4] + 80038de: 2201 movs r2, #1 + 80038e0: 775a strb r2, [r3, #29] +} + 80038e2: bf00 nop + 80038e4: 3708 adds r7, #8 + 80038e6: 46bd mov sp, r7 + 80038e8: bd80 pop {r7, pc} + 80038ea: bf00 nop + 80038ec: 40013c00 .word 0x40013c00 + +080038f0 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +{ + 80038f0: b580 push {r7, lr} + 80038f2: b084 sub sp, #16 + 80038f4: af00 add r7, sp, #0 + 80038f6: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 80038f8: 2300 movs r3, #0 + 80038fa: 60fb str r3, [r7, #12] + + /* Clear RSF flag */ + hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; + 80038fc: 687b ldr r3, [r7, #4] + 80038fe: 681b ldr r3, [r3, #0] + 8003900: 68da ldr r2, [r3, #12] + 8003902: 687b ldr r3, [r7, #4] + 8003904: 681b ldr r3, [r3, #0] + 8003906: f022 02a0 bic.w r2, r2, #160 ; 0xa0 + 800390a: 60da str r2, [r3, #12] + + /* Get tick */ + tickstart = HAL_GetTick(); + 800390c: f7fe fb68 bl 8001fe0 + 8003910: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + 8003912: e009 b.n 8003928 + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 8003914: f7fe fb64 bl 8001fe0 + 8003918: 4602 mov r2, r0 + 800391a: 68fb ldr r3, [r7, #12] + 800391c: 1ad3 subs r3, r2, r3 + 800391e: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8003922: d901 bls.n 8003928 + { + return HAL_TIMEOUT; + 8003924: 2303 movs r3, #3 + 8003926: e007 b.n 8003938 + while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + 8003928: 687b ldr r3, [r7, #4] + 800392a: 681b ldr r3, [r3, #0] + 800392c: 68db ldr r3, [r3, #12] + 800392e: f003 0320 and.w r3, r3, #32 + 8003932: 2b00 cmp r3, #0 + 8003934: d0ee beq.n 8003914 + } } return HAL_OK; - 800223e: 2300 movs r3, #0 + 8003936: 2300 movs r3, #0 } - 8002240: 4618 mov r0, r3 - 8002242: 3710 adds r7, #16 - 8002244: 46bd mov sp, r7 - 8002246: bd80 pop {r7, pc} + 8003938: 4618 mov r0, r3 + 800393a: 3710 adds r7, #16 + 800393c: 46bd mov sp, r7 + 800393e: bd80 pop {r7, pc} -08002248 : - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc RTC handle +08003940 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - 8002248: b580 push {r7, lr} - 800224a: b084 sub sp, #16 - 800224c: af00 add r7, sp, #0 - 800224e: 6078 str r0, [r7, #4] - uint32_t tickstart; + 8003940: b580 push {r7, lr} + 8003942: b084 sub sp, #16 + 8003944: af00 add r7, sp, #0 + 8003946: 6078 str r0, [r7, #4] + uint32_t tickstart = 0U; + 8003948: 2300 movs r3, #0 + 800394a: 60fb str r3, [r7, #12] /* Check if the Initialization mode is set */ - if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) - 8002250: 687b ldr r3, [r7, #4] - 8002252: 681b ldr r3, [r3, #0] - 8002254: 68db ldr r3, [r3, #12] - 8002256: f003 0340 and.w r3, r3, #64 ; 0x40 - 800225a: 2b00 cmp r3, #0 - 800225c: d119 bne.n 8002292 + if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + 800394c: 687b ldr r3, [r7, #4] + 800394e: 681b ldr r3, [r3, #0] + 8003950: 68db ldr r3, [r3, #12] + 8003952: f003 0340 and.w r3, r3, #64 ; 0x40 + 8003956: 2b00 cmp r3, #0 + 8003958: d119 bne.n 800398e { /* Set the Initialization mode */ hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - 800225e: 687b ldr r3, [r7, #4] - 8002260: 681b ldr r3, [r3, #0] - 8002262: f04f 32ff mov.w r2, #4294967295 - 8002266: 60da str r2, [r3, #12] + 800395a: 687b ldr r3, [r7, #4] + 800395c: 681b ldr r3, [r3, #0] + 800395e: f04f 32ff mov.w r2, #4294967295 + 8003962: 60da str r2, [r3, #12] + /* Get tick */ tickstart = HAL_GetTick(); - 8002268: f7fe fbf2 bl 8000a50 - 800226c: 60f8 str r0, [r7, #12] + 8003964: f7fe fb3c bl 8001fe0 + 8003968: 60f8 str r0, [r7, #12] + /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) - 800226e: e009 b.n 8002284 + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + 800396a: e009 b.n 8003980 { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - 8002270: f7fe fbee bl 8000a50 - 8002274: 4602 mov r2, r0 - 8002276: 68fb ldr r3, [r7, #12] - 8002278: 1ad3 subs r3, r2, r3 - 800227a: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 - 800227e: d901 bls.n 8002284 + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + 800396c: f7fe fb38 bl 8001fe0 + 8003970: 4602 mov r2, r0 + 8003972: 68fb ldr r3, [r7, #12] + 8003974: 1ad3 subs r3, r2, r3 + 8003976: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 800397a: d901 bls.n 8003980 { return HAL_TIMEOUT; - 8002280: 2303 movs r3, #3 - 8002282: e007 b.n 8002294 - while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) - 8002284: 687b ldr r3, [r7, #4] - 8002286: 681b ldr r3, [r3, #0] - 8002288: 68db ldr r3, [r3, #12] - 800228a: f003 0340 and.w r3, r3, #64 ; 0x40 - 800228e: 2b00 cmp r3, #0 - 8002290: d0ee beq.n 8002270 + 800397c: 2303 movs r3, #3 + 800397e: e007 b.n 8003990 + while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + 8003980: 687b ldr r3, [r7, #4] + 8003982: 681b ldr r3, [r3, #0] + 8003984: 68db ldr r3, [r3, #12] + 8003986: f003 0340 and.w r3, r3, #64 ; 0x40 + 800398a: 2b00 cmp r3, #0 + 800398c: d0ee beq.n 800396c } } } return HAL_OK; - 8002292: 2300 movs r3, #0 + 800398e: 2300 movs r3, #0 } - 8002294: 4618 mov r0, r3 - 8002296: 3710 adds r7, #16 - 8002298: 46bd mov sp, r7 - 800229a: bd80 pop {r7, pc} + 8003990: 4618 mov r0, r3 + 8003992: 3710 adds r7, #16 + 8003994: 46bd mov sp, r7 + 8003996: bd80 pop {r7, pc} -0800229c : - * @brief Convert a 2 digit decimal to BCD format. +08003998 : + * @brief Converts a 2 digit decimal to BCD format. * @param Value Byte to be converted * @retval Converted byte */ uint8_t RTC_ByteToBcd2(uint8_t Value) { - 800229c: b480 push {r7} - 800229e: b085 sub sp, #20 - 80022a0: af00 add r7, sp, #0 - 80022a2: 4603 mov r3, r0 - 80022a4: 71fb strb r3, [r7, #7] + 8003998: b480 push {r7} + 800399a: b085 sub sp, #20 + 800399c: af00 add r7, sp, #0 + 800399e: 4603 mov r3, r0 + 80039a0: 71fb strb r3, [r7, #7] uint32_t bcdhigh = 0U; - 80022a6: 2300 movs r3, #0 - 80022a8: 60fb str r3, [r7, #12] - uint8_t Param = Value; - 80022aa: 79fb ldrb r3, [r7, #7] - 80022ac: 72fb strb r3, [r7, #11] + 80039a2: 2300 movs r3, #0 + 80039a4: 60fb str r3, [r7, #12] - while (Param >= 10U) - 80022ae: e005 b.n 80022bc + while(Value >= 10U) + 80039a6: e005 b.n 80039b4 { bcdhigh++; - 80022b0: 68fb ldr r3, [r7, #12] - 80022b2: 3301 adds r3, #1 - 80022b4: 60fb str r3, [r7, #12] - Param -= 10U; - 80022b6: 7afb ldrb r3, [r7, #11] - 80022b8: 3b0a subs r3, #10 - 80022ba: 72fb strb r3, [r7, #11] - while (Param >= 10U) - 80022bc: 7afb ldrb r3, [r7, #11] - 80022be: 2b09 cmp r3, #9 - 80022c0: d8f6 bhi.n 80022b0 + 80039a8: 68fb ldr r3, [r7, #12] + 80039aa: 3301 adds r3, #1 + 80039ac: 60fb str r3, [r7, #12] + Value -= 10U; + 80039ae: 79fb ldrb r3, [r7, #7] + 80039b0: 3b0a subs r3, #10 + 80039b2: 71fb strb r3, [r7, #7] + while(Value >= 10U) + 80039b4: 79fb ldrb r3, [r7, #7] + 80039b6: 2b09 cmp r3, #9 + 80039b8: d8f6 bhi.n 80039a8 } - return ((uint8_t)(bcdhigh << 4U) | Param); - 80022c2: 68fb ldr r3, [r7, #12] - 80022c4: b2db uxtb r3, r3 - 80022c6: 011b lsls r3, r3, #4 - 80022c8: b2da uxtb r2, r3 - 80022ca: 7afb ldrb r3, [r7, #11] - 80022cc: 4313 orrs r3, r2 - 80022ce: b2db uxtb r3, r3 + return ((uint8_t)(bcdhigh << 4U) | Value); + 80039ba: 68fb ldr r3, [r7, #12] + 80039bc: b2db uxtb r3, r3 + 80039be: 011b lsls r3, r3, #4 + 80039c0: b2da uxtb r2, r3 + 80039c2: 79fb ldrb r3, [r7, #7] + 80039c4: 4313 orrs r3, r2 + 80039c6: b2db uxtb r3, r3 } - 80022d0: 4618 mov r0, r3 - 80022d2: 3714 adds r7, #20 - 80022d4: 46bd mov sp, r7 - 80022d6: bc80 pop {r7} - 80022d8: 4770 bx lr + 80039c8: 4618 mov r0, r3 + 80039ca: 3714 adds r7, #20 + 80039cc: 46bd mov sp, r7 + 80039ce: f85d 7b04 ldr.w r7, [sp], #4 + 80039d2: 4770 bx lr -080022da : - * @brief Convert from 2 digit BCD to Binary. +080039d4 : + * @brief Converts from 2 digit BCD to Binary. * @param Value BCD value to be converted * @retval Converted word */ uint8_t RTC_Bcd2ToByte(uint8_t Value) { - 80022da: b480 push {r7} - 80022dc: b085 sub sp, #20 - 80022de: af00 add r7, sp, #0 - 80022e0: 4603 mov r3, r0 - 80022e2: 71fb strb r3, [r7, #7] - uint32_t tmp; - tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U; - 80022e4: 79fb ldrb r3, [r7, #7] - 80022e6: 091b lsrs r3, r3, #4 - 80022e8: b2db uxtb r3, r3 - 80022ea: 461a mov r2, r3 - 80022ec: 4613 mov r3, r2 - 80022ee: 009b lsls r3, r3, #2 - 80022f0: 4413 add r3, r2 - 80022f2: 005b lsls r3, r3, #1 - 80022f4: 60fb str r3, [r7, #12] - return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); - 80022f6: 68fb ldr r3, [r7, #12] - 80022f8: b2da uxtb r2, r3 - 80022fa: 79fb ldrb r3, [r7, #7] - 80022fc: f003 030f and.w r3, r3, #15 - 8002300: b2db uxtb r3, r3 - 8002302: 4413 add r3, r2 - 8002304: b2db uxtb r3, r3 + 80039d4: b480 push {r7} + 80039d6: b085 sub sp, #20 + 80039d8: af00 add r7, sp, #0 + 80039da: 4603 mov r3, r0 + 80039dc: 71fb strb r3, [r7, #7] + uint32_t tmp = 0U; + 80039de: 2300 movs r3, #0 + 80039e0: 60fb str r3, [r7, #12] + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + 80039e2: 79fb ldrb r3, [r7, #7] + 80039e4: 091b lsrs r3, r3, #4 + 80039e6: b2db uxtb r3, r3 + 80039e8: 461a mov r2, r3 + 80039ea: 4613 mov r3, r2 + 80039ec: 009b lsls r3, r3, #2 + 80039ee: 4413 add r3, r2 + 80039f0: 005b lsls r3, r3, #1 + 80039f2: 60fb str r3, [r7, #12] + return (tmp + (Value & (uint8_t)0x0F)); + 80039f4: 79fb ldrb r3, [r7, #7] + 80039f6: f003 030f and.w r3, r3, #15 + 80039fa: b2da uxtb r2, r3 + 80039fc: 68fb ldr r3, [r7, #12] + 80039fe: b2db uxtb r3, r3 + 8003a00: 4413 add r3, r2 + 8003a02: b2db uxtb r3, r3 } - 8002306: 4618 mov r0, r3 - 8002308: 3714 adds r7, #20 - 800230a: 46bd mov sp, r7 - 800230c: bc80 pop {r7} - 800230e: 4770 bx lr + 8003a04: 4618 mov r0, r3 + 8003a06: 3714 adds r7, #20 + 8003a08: 46bd mov sp, r7 + 8003a0a: f85d 7b04 ldr.w r7, [sp], #4 + 8003a0e: 4770 bx lr -08002310 : +08003a10 : + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval None + */ +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8003a10: b480 push {r7} + 8003a12: b083 sub sp, #12 + 8003a14: af00 add r7, sp, #0 + 8003a16: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(hrtc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmBEventCallback could be implemented in the user file + */ +} + 8003a18: bf00 nop + 8003a1a: 370c adds r7, #12 + 8003a1c: 46bd mov sp, r7 + 8003a1e: f85d 7b04 ldr.w r7, [sp], #4 + 8003a22: 4770 bx lr + +08003a24 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 8002310: b580 push {r7, lr} - 8002312: b082 sub sp, #8 - 8002314: af00 add r7, sp, #0 - 8002316: 6078 str r0, [r7, #4] + 8003a24: b580 push {r7, lr} + 8003a26: b082 sub sp, #8 + 8003a28: af00 add r7, sp, #0 + 8003a2a: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 8002318: 687b ldr r3, [r7, #4] - 800231a: 2b00 cmp r3, #0 - 800231c: d101 bne.n 8002322 + 8003a2c: 687b ldr r3, [r7, #4] + 8003a2e: 2b00 cmp r3, #0 + 8003a30: d101 bne.n 8003a36 { return HAL_ERROR; - 800231e: 2301 movs r3, #1 - 8002320: e03f b.n 80023a2 + 8003a32: 2301 movs r3, #1 + 8003a34: e03f b.n 8003ab6 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) - 8002322: 687b ldr r3, [r7, #4] - 8002324: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 - 8002328: b2db uxtb r3, r3 - 800232a: 2b00 cmp r3, #0 - 800232c: d106 bne.n 800233c + 8003a36: 687b ldr r3, [r7, #4] + 8003a38: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 8003a3c: b2db uxtb r3, r3 + 8003a3e: 2b00 cmp r3, #0 + 8003a40: d106 bne.n 8003a50 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 800232e: 687b ldr r3, [r7, #4] - 8002330: 2200 movs r2, #0 - 8002332: f883 2038 strb.w r2, [r3, #56] ; 0x38 + 8003a42: 687b ldr r3, [r7, #4] + 8003a44: 2200 movs r2, #0 + 8003a46: f883 2038 strb.w r2, [r3, #56] ; 0x38 /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 8002336: 6878 ldr r0, [r7, #4] - 8002338: f7fe fa86 bl 8000848 + 8003a4a: 6878 ldr r0, [r7, #4] + 8003a4c: f7fe f9a6 bl 8001d9c #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 800233c: 687b ldr r3, [r7, #4] - 800233e: 2224 movs r2, #36 ; 0x24 - 8002340: f883 2039 strb.w r2, [r3, #57] ; 0x39 + 8003a50: 687b ldr r3, [r7, #4] + 8003a52: 2224 movs r2, #36 ; 0x24 + 8003a54: f883 2039 strb.w r2, [r3, #57] ; 0x39 /* Disable the peripheral */ __HAL_UART_DISABLE(huart); - 8002344: 687b ldr r3, [r7, #4] - 8002346: 681b ldr r3, [r3, #0] - 8002348: 68da ldr r2, [r3, #12] - 800234a: 687b ldr r3, [r7, #4] - 800234c: 681b ldr r3, [r3, #0] - 800234e: f422 5200 bic.w r2, r2, #8192 ; 0x2000 - 8002352: 60da str r2, [r3, #12] + 8003a58: 687b ldr r3, [r7, #4] + 8003a5a: 681b ldr r3, [r3, #0] + 8003a5c: 68da ldr r2, [r3, #12] + 8003a5e: 687b ldr r3, [r7, #4] + 8003a60: 681b ldr r3, [r3, #0] + 8003a62: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 8003a66: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); - 8002354: 6878 ldr r0, [r7, #4] - 8002356: f000 f829 bl 80023ac + 8003a68: 6878 ldr r0, [r7, #4] + 8003a6a: f000 f90b bl 8003c84 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 800235a: 687b ldr r3, [r7, #4] - 800235c: 681b ldr r3, [r3, #0] - 800235e: 691a ldr r2, [r3, #16] - 8002360: 687b ldr r3, [r7, #4] - 8002362: 681b ldr r3, [r3, #0] - 8002364: f422 4290 bic.w r2, r2, #18432 ; 0x4800 - 8002368: 611a str r2, [r3, #16] + 8003a6e: 687b ldr r3, [r7, #4] + 8003a70: 681b ldr r3, [r3, #0] + 8003a72: 691a ldr r2, [r3, #16] + 8003a74: 687b ldr r3, [r7, #4] + 8003a76: 681b ldr r3, [r3, #0] + 8003a78: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8003a7c: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 800236a: 687b ldr r3, [r7, #4] - 800236c: 681b ldr r3, [r3, #0] - 800236e: 695a ldr r2, [r3, #20] - 8002370: 687b ldr r3, [r7, #4] - 8002372: 681b ldr r3, [r3, #0] - 8002374: f022 022a bic.w r2, r2, #42 ; 0x2a - 8002378: 615a str r2, [r3, #20] + 8003a7e: 687b ldr r3, [r7, #4] + 8003a80: 681b ldr r3, [r3, #0] + 8003a82: 695a ldr r2, [r3, #20] + 8003a84: 687b ldr r3, [r7, #4] + 8003a86: 681b ldr r3, [r3, #0] + 8003a88: f022 022a bic.w r2, r2, #42 ; 0x2a + 8003a8c: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); - 800237a: 687b ldr r3, [r7, #4] - 800237c: 681b ldr r3, [r3, #0] - 800237e: 68da ldr r2, [r3, #12] - 8002380: 687b ldr r3, [r7, #4] - 8002382: 681b ldr r3, [r3, #0] - 8002384: f442 5200 orr.w r2, r2, #8192 ; 0x2000 - 8002388: 60da str r2, [r3, #12] + 8003a8e: 687b ldr r3, [r7, #4] + 8003a90: 681b ldr r3, [r3, #0] + 8003a92: 68da ldr r2, [r3, #12] + 8003a94: 687b ldr r3, [r7, #4] + 8003a96: 681b ldr r3, [r3, #0] + 8003a98: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8003a9c: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 800238a: 687b ldr r3, [r7, #4] - 800238c: 2200 movs r2, #0 - 800238e: 63da str r2, [r3, #60] ; 0x3c + 8003a9e: 687b ldr r3, [r7, #4] + 8003aa0: 2200 movs r2, #0 + 8003aa2: 63da str r2, [r3, #60] ; 0x3c huart->gState = HAL_UART_STATE_READY; - 8002390: 687b ldr r3, [r7, #4] - 8002392: 2220 movs r2, #32 - 8002394: f883 2039 strb.w r2, [r3, #57] ; 0x39 + 8003aa4: 687b ldr r3, [r7, #4] + 8003aa6: 2220 movs r2, #32 + 8003aa8: f883 2039 strb.w r2, [r3, #57] ; 0x39 huart->RxState = HAL_UART_STATE_READY; - 8002398: 687b ldr r3, [r7, #4] - 800239a: 2220 movs r2, #32 - 800239c: f883 203a strb.w r2, [r3, #58] ; 0x3a + 8003aac: 687b ldr r3, [r7, #4] + 8003aae: 2220 movs r2, #32 + 8003ab0: f883 203a strb.w r2, [r3, #58] ; 0x3a return HAL_OK; - 80023a0: 2300 movs r3, #0 + 8003ab4: 2300 movs r3, #0 } - 80023a2: 4618 mov r0, r3 - 80023a4: 3708 adds r7, #8 - 80023a6: 46bd mov sp, r7 - 80023a8: bd80 pop {r7, pc} - ... + 8003ab6: 4618 mov r0, r3 + 8003ab8: 3708 adds r7, #8 + 8003aba: 46bd mov sp, r7 + 8003abc: bd80 pop {r7, pc} -080023ac : +08003abe : + * @param Size Amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8003abe: b580 push {r7, lr} + 8003ac0: b088 sub sp, #32 + 8003ac2: af02 add r7, sp, #8 + 8003ac4: 60f8 str r0, [r7, #12] + 8003ac6: 60b9 str r1, [r7, #8] + 8003ac8: 603b str r3, [r7, #0] + 8003aca: 4613 mov r3, r2 + 8003acc: 80fb strh r3, [r7, #6] + uint16_t *tmp; + uint32_t tickstart = 0U; + 8003ace: 2300 movs r3, #0 + 8003ad0: 617b str r3, [r7, #20] + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8003ad2: 68fb ldr r3, [r7, #12] + 8003ad4: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 + 8003ad8: b2db uxtb r3, r3 + 8003ada: 2b20 cmp r3, #32 + 8003adc: f040 8083 bne.w 8003be6 + { + if ((pData == NULL) || (Size == 0U)) + 8003ae0: 68bb ldr r3, [r7, #8] + 8003ae2: 2b00 cmp r3, #0 + 8003ae4: d002 beq.n 8003aec + 8003ae6: 88fb ldrh r3, [r7, #6] + 8003ae8: 2b00 cmp r3, #0 + 8003aea: d101 bne.n 8003af0 + { + return HAL_ERROR; + 8003aec: 2301 movs r3, #1 + 8003aee: e07b b.n 8003be8 + } + + /* Process Locked */ + __HAL_LOCK(huart); + 8003af0: 68fb ldr r3, [r7, #12] + 8003af2: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 + 8003af6: 2b01 cmp r3, #1 + 8003af8: d101 bne.n 8003afe + 8003afa: 2302 movs r3, #2 + 8003afc: e074 b.n 8003be8 + 8003afe: 68fb ldr r3, [r7, #12] + 8003b00: 2201 movs r2, #1 + 8003b02: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8003b06: 68fb ldr r3, [r7, #12] + 8003b08: 2200 movs r2, #0 + 8003b0a: 63da str r2, [r3, #60] ; 0x3c + huart->gState = HAL_UART_STATE_BUSY_TX; + 8003b0c: 68fb ldr r3, [r7, #12] + 8003b0e: 2221 movs r2, #33 ; 0x21 + 8003b10: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + /* Init tickstart for timeout managment */ + tickstart = HAL_GetTick(); + 8003b14: f7fe fa64 bl 8001fe0 + 8003b18: 6178 str r0, [r7, #20] + + huart->TxXferSize = Size; + 8003b1a: 68fb ldr r3, [r7, #12] + 8003b1c: 88fa ldrh r2, [r7, #6] + 8003b1e: 849a strh r2, [r3, #36] ; 0x24 + huart->TxXferCount = Size; + 8003b20: 68fb ldr r3, [r7, #12] + 8003b22: 88fa ldrh r2, [r7, #6] + 8003b24: 84da strh r2, [r3, #38] ; 0x26 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8003b26: 68fb ldr r3, [r7, #12] + 8003b28: 2200 movs r2, #0 + 8003b2a: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + while (huart->TxXferCount > 0U) + 8003b2e: e042 b.n 8003bb6 + { + huart->TxXferCount--; + 8003b30: 68fb ldr r3, [r7, #12] + 8003b32: 8cdb ldrh r3, [r3, #38] ; 0x26 + 8003b34: b29b uxth r3, r3 + 8003b36: 3b01 subs r3, #1 + 8003b38: b29a uxth r2, r3 + 8003b3a: 68fb ldr r3, [r7, #12] + 8003b3c: 84da strh r2, [r3, #38] ; 0x26 + if (huart->Init.WordLength == UART_WORDLENGTH_9B) + 8003b3e: 68fb ldr r3, [r7, #12] + 8003b40: 689b ldr r3, [r3, #8] + 8003b42: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8003b46: d122 bne.n 8003b8e + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 8003b48: 683b ldr r3, [r7, #0] + 8003b4a: 9300 str r3, [sp, #0] + 8003b4c: 697b ldr r3, [r7, #20] + 8003b4e: 2200 movs r2, #0 + 8003b50: 2180 movs r1, #128 ; 0x80 + 8003b52: 68f8 ldr r0, [r7, #12] + 8003b54: f000 f84c bl 8003bf0 + 8003b58: 4603 mov r3, r0 + 8003b5a: 2b00 cmp r3, #0 + 8003b5c: d001 beq.n 8003b62 + { + return HAL_TIMEOUT; + 8003b5e: 2303 movs r3, #3 + 8003b60: e042 b.n 8003be8 + } + tmp = (uint16_t *) pData; + 8003b62: 68bb ldr r3, [r7, #8] + 8003b64: 613b str r3, [r7, #16] + huart->Instance->DR = (*tmp & (uint16_t)0x01FF); + 8003b66: 693b ldr r3, [r7, #16] + 8003b68: 881b ldrh r3, [r3, #0] + 8003b6a: 461a mov r2, r3 + 8003b6c: 68fb ldr r3, [r7, #12] + 8003b6e: 681b ldr r3, [r3, #0] + 8003b70: f3c2 0208 ubfx r2, r2, #0, #9 + 8003b74: 605a str r2, [r3, #4] + if (huart->Init.Parity == UART_PARITY_NONE) + 8003b76: 68fb ldr r3, [r7, #12] + 8003b78: 691b ldr r3, [r3, #16] + 8003b7a: 2b00 cmp r3, #0 + 8003b7c: d103 bne.n 8003b86 + { + pData += 2U; + 8003b7e: 68bb ldr r3, [r7, #8] + 8003b80: 3302 adds r3, #2 + 8003b82: 60bb str r3, [r7, #8] + 8003b84: e017 b.n 8003bb6 + } + else + { + pData += 1U; + 8003b86: 68bb ldr r3, [r7, #8] + 8003b88: 3301 adds r3, #1 + 8003b8a: 60bb str r3, [r7, #8] + 8003b8c: e013 b.n 8003bb6 + } + } + else + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + 8003b8e: 683b ldr r3, [r7, #0] + 8003b90: 9300 str r3, [sp, #0] + 8003b92: 697b ldr r3, [r7, #20] + 8003b94: 2200 movs r2, #0 + 8003b96: 2180 movs r1, #128 ; 0x80 + 8003b98: 68f8 ldr r0, [r7, #12] + 8003b9a: f000 f829 bl 8003bf0 + 8003b9e: 4603 mov r3, r0 + 8003ba0: 2b00 cmp r3, #0 + 8003ba2: d001 beq.n 8003ba8 + { + return HAL_TIMEOUT; + 8003ba4: 2303 movs r3, #3 + 8003ba6: e01f b.n 8003be8 + } + huart->Instance->DR = (*pData++ & (uint8_t)0xFF); + 8003ba8: 68bb ldr r3, [r7, #8] + 8003baa: 1c5a adds r2, r3, #1 + 8003bac: 60ba str r2, [r7, #8] + 8003bae: 781a ldrb r2, [r3, #0] + 8003bb0: 68fb ldr r3, [r7, #12] + 8003bb2: 681b ldr r3, [r3, #0] + 8003bb4: 605a str r2, [r3, #4] + while (huart->TxXferCount > 0U) + 8003bb6: 68fb ldr r3, [r7, #12] + 8003bb8: 8cdb ldrh r3, [r3, #38] ; 0x26 + 8003bba: b29b uxth r3, r3 + 8003bbc: 2b00 cmp r3, #0 + 8003bbe: d1b7 bne.n 8003b30 + } + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + 8003bc0: 683b ldr r3, [r7, #0] + 8003bc2: 9300 str r3, [sp, #0] + 8003bc4: 697b ldr r3, [r7, #20] + 8003bc6: 2200 movs r2, #0 + 8003bc8: 2140 movs r1, #64 ; 0x40 + 8003bca: 68f8 ldr r0, [r7, #12] + 8003bcc: f000 f810 bl 8003bf0 + 8003bd0: 4603 mov r3, r0 + 8003bd2: 2b00 cmp r3, #0 + 8003bd4: d001 beq.n 8003bda + { + return HAL_TIMEOUT; + 8003bd6: 2303 movs r3, #3 + 8003bd8: e006 b.n 8003be8 + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8003bda: 68fb ldr r3, [r7, #12] + 8003bdc: 2220 movs r2, #32 + 8003bde: f883 2039 strb.w r2, [r3, #57] ; 0x39 + + return HAL_OK; + 8003be2: 2300 movs r3, #0 + 8003be4: e000 b.n 8003be8 + } + else + { + return HAL_BUSY; + 8003be6: 2302 movs r3, #2 + } +} + 8003be8: 4618 mov r0, r3 + 8003bea: 3718 adds r7, #24 + 8003bec: 46bd mov sp, r7 + 8003bee: bd80 pop {r7, pc} + +08003bf0 : + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +{ + 8003bf0: b580 push {r7, lr} + 8003bf2: b084 sub sp, #16 + 8003bf4: af00 add r7, sp, #0 + 8003bf6: 60f8 str r0, [r7, #12] + 8003bf8: 60b9 str r1, [r7, #8] + 8003bfa: 603b str r3, [r7, #0] + 8003bfc: 4613 mov r3, r2 + 8003bfe: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8003c00: e02c b.n 8003c5c + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8003c02: 69bb ldr r3, [r7, #24] + 8003c04: f1b3 3fff cmp.w r3, #4294967295 + 8003c08: d028 beq.n 8003c5c + { + if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) + 8003c0a: 69bb ldr r3, [r7, #24] + 8003c0c: 2b00 cmp r3, #0 + 8003c0e: d007 beq.n 8003c20 + 8003c10: f7fe f9e6 bl 8001fe0 + 8003c14: 4602 mov r2, r0 + 8003c16: 683b ldr r3, [r7, #0] + 8003c18: 1ad3 subs r3, r2, r3 + 8003c1a: 69ba ldr r2, [r7, #24] + 8003c1c: 429a cmp r2, r3 + 8003c1e: d21d bcs.n 8003c5c + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ + CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + 8003c20: 68fb ldr r3, [r7, #12] + 8003c22: 681b ldr r3, [r3, #0] + 8003c24: 68da ldr r2, [r3, #12] + 8003c26: 68fb ldr r3, [r7, #12] + 8003c28: 681b ldr r3, [r3, #0] + 8003c2a: f422 72d0 bic.w r2, r2, #416 ; 0x1a0 + 8003c2e: 60da str r2, [r3, #12] + CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8003c30: 68fb ldr r3, [r7, #12] + 8003c32: 681b ldr r3, [r3, #0] + 8003c34: 695a ldr r2, [r3, #20] + 8003c36: 68fb ldr r3, [r7, #12] + 8003c38: 681b ldr r3, [r3, #0] + 8003c3a: f022 0201 bic.w r2, r2, #1 + 8003c3e: 615a str r2, [r3, #20] + + huart->gState = HAL_UART_STATE_READY; + 8003c40: 68fb ldr r3, [r7, #12] + 8003c42: 2220 movs r2, #32 + 8003c44: f883 2039 strb.w r2, [r3, #57] ; 0x39 + huart->RxState = HAL_UART_STATE_READY; + 8003c48: 68fb ldr r3, [r7, #12] + 8003c4a: 2220 movs r2, #32 + 8003c4c: f883 203a strb.w r2, [r3, #58] ; 0x3a + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8003c50: 68fb ldr r3, [r7, #12] + 8003c52: 2200 movs r2, #0 + 8003c54: f883 2038 strb.w r2, [r3, #56] ; 0x38 + + return HAL_TIMEOUT; + 8003c58: 2303 movs r3, #3 + 8003c5a: e00f b.n 8003c7c + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8003c5c: 68fb ldr r3, [r7, #12] + 8003c5e: 681b ldr r3, [r3, #0] + 8003c60: 681a ldr r2, [r3, #0] + 8003c62: 68bb ldr r3, [r7, #8] + 8003c64: 4013 ands r3, r2 + 8003c66: 68ba ldr r2, [r7, #8] + 8003c68: 429a cmp r2, r3 + 8003c6a: bf0c ite eq + 8003c6c: 2301 moveq r3, #1 + 8003c6e: 2300 movne r3, #0 + 8003c70: b2db uxtb r3, r3 + 8003c72: 461a mov r2, r3 + 8003c74: 79fb ldrb r3, [r7, #7] + 8003c76: 429a cmp r2, r3 + 8003c78: d0c3 beq.n 8003c02 + } + } + } + return HAL_OK; + 8003c7a: 2300 movs r3, #0 +} + 8003c7c: 4618 mov r0, r3 + 8003c7e: 3710 adds r7, #16 + 8003c80: 46bd mov sp, r7 + 8003c82: bd80 pop {r7, pc} + +08003c84 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { - 80023ac: b580 push {r7, lr} - 80023ae: b084 sub sp, #16 - 80023b0: af00 add r7, sp, #0 - 80023b2: 6078 str r0, [r7, #4] + 8003c84: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8003c88: b085 sub sp, #20 + 8003c8a: af00 add r7, sp, #0 + 8003c8c: 6078 str r0, [r7, #4] assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 80023b4: 687b ldr r3, [r7, #4] - 80023b6: 681b ldr r3, [r3, #0] - 80023b8: 691b ldr r3, [r3, #16] - 80023ba: f423 5140 bic.w r1, r3, #12288 ; 0x3000 - 80023be: 687b ldr r3, [r7, #4] - 80023c0: 68da ldr r2, [r3, #12] - 80023c2: 687b ldr r3, [r7, #4] - 80023c4: 681b ldr r3, [r3, #0] - 80023c6: 430a orrs r2, r1 - 80023c8: 611a str r2, [r3, #16] + 8003c8e: 687b ldr r3, [r7, #4] + 8003c90: 681b ldr r3, [r3, #0] + 8003c92: 691b ldr r3, [r3, #16] + 8003c94: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8003c98: 687b ldr r3, [r7, #4] + 8003c9a: 68da ldr r2, [r3, #12] + 8003c9c: 687b ldr r3, [r7, #4] + 8003c9e: 681b ldr r3, [r3, #0] + 8003ca0: 430a orrs r2, r1 + 8003ca2: 611a str r2, [r3, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; - 80023ca: 687b ldr r3, [r7, #4] - 80023cc: 689a ldr r2, [r3, #8] - 80023ce: 687b ldr r3, [r7, #4] - 80023d0: 691b ldr r3, [r3, #16] - 80023d2: 431a orrs r2, r3 - 80023d4: 687b ldr r3, [r7, #4] - 80023d6: 695b ldr r3, [r3, #20] - 80023d8: 431a orrs r2, r3 - 80023da: 687b ldr r3, [r7, #4] - 80023dc: 69db ldr r3, [r3, #28] - 80023de: 4313 orrs r3, r2 - 80023e0: 60bb str r3, [r7, #8] + 8003ca4: 687b ldr r3, [r7, #4] + 8003ca6: 689a ldr r2, [r3, #8] + 8003ca8: 687b ldr r3, [r7, #4] + 8003caa: 691b ldr r3, [r3, #16] + 8003cac: 431a orrs r2, r3 + 8003cae: 687b ldr r3, [r7, #4] + 8003cb0: 695b ldr r3, [r3, #20] + 8003cb2: 431a orrs r2, r3 + 8003cb4: 687b ldr r3, [r7, #4] + 8003cb6: 69db ldr r3, [r3, #28] + 8003cb8: 4313 orrs r3, r2 + 8003cba: 60fb str r3, [r7, #12] MODIFY_REG(huart->Instance->CR1, - 80023e2: 687b ldr r3, [r7, #4] - 80023e4: 681b ldr r3, [r3, #0] - 80023e6: 68db ldr r3, [r3, #12] - 80023e8: f423 4316 bic.w r3, r3, #38400 ; 0x9600 - 80023ec: f023 030c bic.w r3, r3, #12 - 80023f0: 687a ldr r2, [r7, #4] - 80023f2: 6812 ldr r2, [r2, #0] - 80023f4: 68b9 ldr r1, [r7, #8] - 80023f6: 430b orrs r3, r1 - 80023f8: 60d3 str r3, [r2, #12] + 8003cbc: 687b ldr r3, [r7, #4] + 8003cbe: 681b ldr r3, [r3, #0] + 8003cc0: 68db ldr r3, [r3, #12] + 8003cc2: f423 4316 bic.w r3, r3, #38400 ; 0x9600 + 8003cc6: f023 030c bic.w r3, r3, #12 + 8003cca: 687a ldr r2, [r7, #4] + 8003ccc: 6812 ldr r2, [r2, #0] + 8003cce: 68f9 ldr r1, [r7, #12] + 8003cd0: 430b orrs r3, r1 + 8003cd2: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - 80023fa: 687b ldr r3, [r7, #4] - 80023fc: 681b ldr r3, [r3, #0] - 80023fe: 695b ldr r3, [r3, #20] - 8002400: f423 7140 bic.w r1, r3, #768 ; 0x300 - 8002404: 687b ldr r3, [r7, #4] - 8002406: 699a ldr r2, [r3, #24] - 8002408: 687b ldr r3, [r7, #4] - 800240a: 681b ldr r3, [r3, #0] - 800240c: 430a orrs r2, r1 - 800240e: 615a str r2, [r3, #20] + 8003cd4: 687b ldr r3, [r7, #4] + 8003cd6: 681b ldr r3, [r3, #0] + 8003cd8: 695b ldr r3, [r3, #20] + 8003cda: f423 7140 bic.w r1, r3, #768 ; 0x300 + 8003cde: 687b ldr r3, [r7, #4] + 8003ce0: 699a ldr r2, [r3, #24] + 8003ce2: 687b ldr r3, [r7, #4] + 8003ce4: 681b ldr r3, [r3, #0] + 8003ce6: 430a orrs r2, r1 + 8003ce8: 615a str r2, [r3, #20] - - if((huart->Instance == USART1)) - 8002410: 687b ldr r3, [r7, #4] - 8002412: 681b ldr r3, [r3, #0] - 8002414: 4a55 ldr r2, [pc, #340] ; (800256c ) - 8002416: 4293 cmp r3, r2 - 8002418: d103 bne.n 8002422 - { - pclk = HAL_RCC_GetPCLK2Freq(); - 800241a: f7ff fb1b bl 8001a54 - 800241e: 60f8 str r0, [r7, #12] - 8002420: e002 b.n 8002428 - } - else - { - pclk = HAL_RCC_GetPCLK1Freq(); - 8002422: f7ff fb03 bl 8001a2c - 8002426: 60f8 str r0, [r7, #12] - } - - /*-------------------------- USART BRR Configuration ---------------------*/ + /* Check the Over Sampling */ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 8002428: 687b ldr r3, [r7, #4] - 800242a: 69db ldr r3, [r3, #28] - 800242c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8002430: d14c bne.n 80024cc - { - huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); - 8002432: 68fa ldr r2, [r7, #12] - 8002434: 4613 mov r3, r2 - 8002436: 009b lsls r3, r3, #2 - 8002438: 4413 add r3, r2 - 800243a: 009a lsls r2, r3, #2 - 800243c: 441a add r2, r3 - 800243e: 687b ldr r3, [r7, #4] - 8002440: 685b ldr r3, [r3, #4] - 8002442: 005b lsls r3, r3, #1 - 8002444: fbb2 f3f3 udiv r3, r2, r3 - 8002448: 4a49 ldr r2, [pc, #292] ; (8002570 ) - 800244a: fba2 2303 umull r2, r3, r2, r3 - 800244e: 095b lsrs r3, r3, #5 - 8002450: 0119 lsls r1, r3, #4 - 8002452: 68fa ldr r2, [r7, #12] - 8002454: 4613 mov r3, r2 - 8002456: 009b lsls r3, r3, #2 - 8002458: 4413 add r3, r2 - 800245a: 009a lsls r2, r3, #2 - 800245c: 441a add r2, r3 - 800245e: 687b ldr r3, [r7, #4] - 8002460: 685b ldr r3, [r3, #4] - 8002462: 005b lsls r3, r3, #1 - 8002464: fbb2 f2f3 udiv r2, r2, r3 - 8002468: 4b41 ldr r3, [pc, #260] ; (8002570 ) - 800246a: fba3 0302 umull r0, r3, r3, r2 - 800246e: 095b lsrs r3, r3, #5 - 8002470: 2064 movs r0, #100 ; 0x64 - 8002472: fb00 f303 mul.w r3, r0, r3 - 8002476: 1ad3 subs r3, r2, r3 - 8002478: 00db lsls r3, r3, #3 - 800247a: 3332 adds r3, #50 ; 0x32 - 800247c: 4a3c ldr r2, [pc, #240] ; (8002570 ) - 800247e: fba2 2303 umull r2, r3, r2, r3 - 8002482: 095b lsrs r3, r3, #5 - 8002484: 005b lsls r3, r3, #1 - 8002486: f403 73f8 and.w r3, r3, #496 ; 0x1f0 - 800248a: 4419 add r1, r3 - 800248c: 68fa ldr r2, [r7, #12] - 800248e: 4613 mov r3, r2 - 8002490: 009b lsls r3, r3, #2 - 8002492: 4413 add r3, r2 - 8002494: 009a lsls r2, r3, #2 - 8002496: 441a add r2, r3 - 8002498: 687b ldr r3, [r7, #4] - 800249a: 685b ldr r3, [r3, #4] - 800249c: 005b lsls r3, r3, #1 - 800249e: fbb2 f2f3 udiv r2, r2, r3 - 80024a2: 4b33 ldr r3, [pc, #204] ; (8002570 ) - 80024a4: fba3 0302 umull r0, r3, r3, r2 - 80024a8: 095b lsrs r3, r3, #5 - 80024aa: 2064 movs r0, #100 ; 0x64 - 80024ac: fb00 f303 mul.w r3, r0, r3 - 80024b0: 1ad3 subs r3, r2, r3 - 80024b2: 00db lsls r3, r3, #3 - 80024b4: 3332 adds r3, #50 ; 0x32 - 80024b6: 4a2e ldr r2, [pc, #184] ; (8002570 ) - 80024b8: fba2 2303 umull r2, r3, r2, r3 - 80024bc: 095b lsrs r3, r3, #5 - 80024be: f003 0207 and.w r2, r3, #7 - 80024c2: 687b ldr r3, [r7, #4] - 80024c4: 681b ldr r3, [r3, #0] - 80024c6: 440a add r2, r1 - 80024c8: 609a str r2, [r3, #8] - } - else - { - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8003cea: 687b ldr r3, [r7, #4] + 8003cec: 69db ldr r3, [r3, #28] + 8003cee: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8003cf2: f040 818b bne.w 800400c + { + pclk = HAL_RCC_GetPCLK2Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#elif defined(USART6) + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + 8003cf6: 687b ldr r3, [r7, #4] + 8003cf8: 681b ldr r3, [r3, #0] + 8003cfa: 4ac1 ldr r2, [pc, #772] ; (8004000 ) + 8003cfc: 4293 cmp r3, r2 + 8003cfe: d005 beq.n 8003d0c + 8003d00: 687b ldr r3, [r7, #4] + 8003d02: 681b ldr r3, [r3, #0] + 8003d04: 4abf ldr r2, [pc, #764] ; (8004004 ) + 8003d06: 4293 cmp r3, r2 + 8003d08: f040 80bd bne.w 8003e86 + { + pclk = HAL_RCC_GetPCLK2Freq(); + 8003d0c: f7ff f8ce bl 8002eac + 8003d10: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + 8003d12: 68bb ldr r3, [r7, #8] + 8003d14: 461d mov r5, r3 + 8003d16: f04f 0600 mov.w r6, #0 + 8003d1a: 46a8 mov r8, r5 + 8003d1c: 46b1 mov r9, r6 + 8003d1e: eb18 0308 adds.w r3, r8, r8 + 8003d22: eb49 0409 adc.w r4, r9, r9 + 8003d26: 4698 mov r8, r3 + 8003d28: 46a1 mov r9, r4 + 8003d2a: eb18 0805 adds.w r8, r8, r5 + 8003d2e: eb49 0906 adc.w r9, r9, r6 + 8003d32: f04f 0100 mov.w r1, #0 + 8003d36: f04f 0200 mov.w r2, #0 + 8003d3a: ea4f 02c9 mov.w r2, r9, lsl #3 + 8003d3e: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8003d42: ea4f 01c8 mov.w r1, r8, lsl #3 + 8003d46: 4688 mov r8, r1 + 8003d48: 4691 mov r9, r2 + 8003d4a: eb18 0005 adds.w r0, r8, r5 + 8003d4e: eb49 0106 adc.w r1, r9, r6 + 8003d52: 687b ldr r3, [r7, #4] + 8003d54: 685b ldr r3, [r3, #4] + 8003d56: 461d mov r5, r3 + 8003d58: f04f 0600 mov.w r6, #0 + 8003d5c: 196b adds r3, r5, r5 + 8003d5e: eb46 0406 adc.w r4, r6, r6 + 8003d62: 461a mov r2, r3 + 8003d64: 4623 mov r3, r4 + 8003d66: f7fc fed3 bl 8000b10 <__aeabi_uldivmod> + 8003d6a: 4603 mov r3, r0 + 8003d6c: 460c mov r4, r1 + 8003d6e: 461a mov r2, r3 + 8003d70: 4ba5 ldr r3, [pc, #660] ; (8004008 ) + 8003d72: fba3 2302 umull r2, r3, r3, r2 + 8003d76: 095b lsrs r3, r3, #5 + 8003d78: ea4f 1803 mov.w r8, r3, lsl #4 + 8003d7c: 68bb ldr r3, [r7, #8] + 8003d7e: 461d mov r5, r3 + 8003d80: f04f 0600 mov.w r6, #0 + 8003d84: 46a9 mov r9, r5 + 8003d86: 46b2 mov sl, r6 + 8003d88: eb19 0309 adds.w r3, r9, r9 + 8003d8c: eb4a 040a adc.w r4, sl, sl + 8003d90: 4699 mov r9, r3 + 8003d92: 46a2 mov sl, r4 + 8003d94: eb19 0905 adds.w r9, r9, r5 + 8003d98: eb4a 0a06 adc.w sl, sl, r6 + 8003d9c: f04f 0100 mov.w r1, #0 + 8003da0: f04f 0200 mov.w r2, #0 + 8003da4: ea4f 02ca mov.w r2, sl, lsl #3 + 8003da8: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8003dac: ea4f 01c9 mov.w r1, r9, lsl #3 + 8003db0: 4689 mov r9, r1 + 8003db2: 4692 mov sl, r2 + 8003db4: eb19 0005 adds.w r0, r9, r5 + 8003db8: eb4a 0106 adc.w r1, sl, r6 + 8003dbc: 687b ldr r3, [r7, #4] + 8003dbe: 685b ldr r3, [r3, #4] + 8003dc0: 461d mov r5, r3 + 8003dc2: f04f 0600 mov.w r6, #0 + 8003dc6: 196b adds r3, r5, r5 + 8003dc8: eb46 0406 adc.w r4, r6, r6 + 8003dcc: 461a mov r2, r3 + 8003dce: 4623 mov r3, r4 + 8003dd0: f7fc fe9e bl 8000b10 <__aeabi_uldivmod> + 8003dd4: 4603 mov r3, r0 + 8003dd6: 460c mov r4, r1 + 8003dd8: 461a mov r2, r3 + 8003dda: 4b8b ldr r3, [pc, #556] ; (8004008 ) + 8003ddc: fba3 1302 umull r1, r3, r3, r2 + 8003de0: 095b lsrs r3, r3, #5 + 8003de2: 2164 movs r1, #100 ; 0x64 + 8003de4: fb01 f303 mul.w r3, r1, r3 + 8003de8: 1ad3 subs r3, r2, r3 + 8003dea: 00db lsls r3, r3, #3 + 8003dec: 3332 adds r3, #50 ; 0x32 + 8003dee: 4a86 ldr r2, [pc, #536] ; (8004008 ) + 8003df0: fba2 2303 umull r2, r3, r2, r3 + 8003df4: 095b lsrs r3, r3, #5 + 8003df6: 005b lsls r3, r3, #1 + 8003df8: f403 73f8 and.w r3, r3, #496 ; 0x1f0 + 8003dfc: 4498 add r8, r3 + 8003dfe: 68bb ldr r3, [r7, #8] + 8003e00: 461d mov r5, r3 + 8003e02: f04f 0600 mov.w r6, #0 + 8003e06: 46a9 mov r9, r5 + 8003e08: 46b2 mov sl, r6 + 8003e0a: eb19 0309 adds.w r3, r9, r9 + 8003e0e: eb4a 040a adc.w r4, sl, sl + 8003e12: 4699 mov r9, r3 + 8003e14: 46a2 mov sl, r4 + 8003e16: eb19 0905 adds.w r9, r9, r5 + 8003e1a: eb4a 0a06 adc.w sl, sl, r6 + 8003e1e: f04f 0100 mov.w r1, #0 + 8003e22: f04f 0200 mov.w r2, #0 + 8003e26: ea4f 02ca mov.w r2, sl, lsl #3 + 8003e2a: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8003e2e: ea4f 01c9 mov.w r1, r9, lsl #3 + 8003e32: 4689 mov r9, r1 + 8003e34: 4692 mov sl, r2 + 8003e36: eb19 0005 adds.w r0, r9, r5 + 8003e3a: eb4a 0106 adc.w r1, sl, r6 + 8003e3e: 687b ldr r3, [r7, #4] + 8003e40: 685b ldr r3, [r3, #4] + 8003e42: 461d mov r5, r3 + 8003e44: f04f 0600 mov.w r6, #0 + 8003e48: 196b adds r3, r5, r5 + 8003e4a: eb46 0406 adc.w r4, r6, r6 + 8003e4e: 461a mov r2, r3 + 8003e50: 4623 mov r3, r4 + 8003e52: f7fc fe5d bl 8000b10 <__aeabi_uldivmod> + 8003e56: 4603 mov r3, r0 + 8003e58: 460c mov r4, r1 + 8003e5a: 461a mov r2, r3 + 8003e5c: 4b6a ldr r3, [pc, #424] ; (8004008 ) + 8003e5e: fba3 1302 umull r1, r3, r3, r2 + 8003e62: 095b lsrs r3, r3, #5 + 8003e64: 2164 movs r1, #100 ; 0x64 + 8003e66: fb01 f303 mul.w r3, r1, r3 + 8003e6a: 1ad3 subs r3, r2, r3 + 8003e6c: 00db lsls r3, r3, #3 + 8003e6e: 3332 adds r3, #50 ; 0x32 + 8003e70: 4a65 ldr r2, [pc, #404] ; (8004008 ) + 8003e72: fba2 2303 umull r2, r3, r2, r3 + 8003e76: 095b lsrs r3, r3, #5 + 8003e78: f003 0207 and.w r2, r3, #7 + 8003e7c: 687b ldr r3, [r7, #4] + 8003e7e: 681b ldr r3, [r3, #0] + 8003e80: 4442 add r2, r8 + 8003e82: 609a str r2, [r3, #8] + 8003e84: e26f b.n 8004366 + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + } +#endif /* USART6 */ + else + { + pclk = HAL_RCC_GetPCLK1Freq(); + 8003e86: f7fe fffd bl 8002e84 + 8003e8a: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); + 8003e8c: 68bb ldr r3, [r7, #8] + 8003e8e: 461d mov r5, r3 + 8003e90: f04f 0600 mov.w r6, #0 + 8003e94: 46a8 mov r8, r5 + 8003e96: 46b1 mov r9, r6 + 8003e98: eb18 0308 adds.w r3, r8, r8 + 8003e9c: eb49 0409 adc.w r4, r9, r9 + 8003ea0: 4698 mov r8, r3 + 8003ea2: 46a1 mov r9, r4 + 8003ea4: eb18 0805 adds.w r8, r8, r5 + 8003ea8: eb49 0906 adc.w r9, r9, r6 + 8003eac: f04f 0100 mov.w r1, #0 + 8003eb0: f04f 0200 mov.w r2, #0 + 8003eb4: ea4f 02c9 mov.w r2, r9, lsl #3 + 8003eb8: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8003ebc: ea4f 01c8 mov.w r1, r8, lsl #3 + 8003ec0: 4688 mov r8, r1 + 8003ec2: 4691 mov r9, r2 + 8003ec4: eb18 0005 adds.w r0, r8, r5 + 8003ec8: eb49 0106 adc.w r1, r9, r6 + 8003ecc: 687b ldr r3, [r7, #4] + 8003ece: 685b ldr r3, [r3, #4] + 8003ed0: 461d mov r5, r3 + 8003ed2: f04f 0600 mov.w r6, #0 + 8003ed6: 196b adds r3, r5, r5 + 8003ed8: eb46 0406 adc.w r4, r6, r6 + 8003edc: 461a mov r2, r3 + 8003ede: 4623 mov r3, r4 + 8003ee0: f7fc fe16 bl 8000b10 <__aeabi_uldivmod> + 8003ee4: 4603 mov r3, r0 + 8003ee6: 460c mov r4, r1 + 8003ee8: 461a mov r2, r3 + 8003eea: 4b47 ldr r3, [pc, #284] ; (8004008 ) + 8003eec: fba3 2302 umull r2, r3, r3, r2 + 8003ef0: 095b lsrs r3, r3, #5 + 8003ef2: ea4f 1803 mov.w r8, r3, lsl #4 + 8003ef6: 68bb ldr r3, [r7, #8] + 8003ef8: 461d mov r5, r3 + 8003efa: f04f 0600 mov.w r6, #0 + 8003efe: 46a9 mov r9, r5 + 8003f00: 46b2 mov sl, r6 + 8003f02: eb19 0309 adds.w r3, r9, r9 + 8003f06: eb4a 040a adc.w r4, sl, sl + 8003f0a: 4699 mov r9, r3 + 8003f0c: 46a2 mov sl, r4 + 8003f0e: eb19 0905 adds.w r9, r9, r5 + 8003f12: eb4a 0a06 adc.w sl, sl, r6 + 8003f16: f04f 0100 mov.w r1, #0 + 8003f1a: f04f 0200 mov.w r2, #0 + 8003f1e: ea4f 02ca mov.w r2, sl, lsl #3 + 8003f22: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8003f26: ea4f 01c9 mov.w r1, r9, lsl #3 + 8003f2a: 4689 mov r9, r1 + 8003f2c: 4692 mov sl, r2 + 8003f2e: eb19 0005 adds.w r0, r9, r5 + 8003f32: eb4a 0106 adc.w r1, sl, r6 + 8003f36: 687b ldr r3, [r7, #4] + 8003f38: 685b ldr r3, [r3, #4] + 8003f3a: 461d mov r5, r3 + 8003f3c: f04f 0600 mov.w r6, #0 + 8003f40: 196b adds r3, r5, r5 + 8003f42: eb46 0406 adc.w r4, r6, r6 + 8003f46: 461a mov r2, r3 + 8003f48: 4623 mov r3, r4 + 8003f4a: f7fc fde1 bl 8000b10 <__aeabi_uldivmod> + 8003f4e: 4603 mov r3, r0 + 8003f50: 460c mov r4, r1 + 8003f52: 461a mov r2, r3 + 8003f54: 4b2c ldr r3, [pc, #176] ; (8004008 ) + 8003f56: fba3 1302 umull r1, r3, r3, r2 + 8003f5a: 095b lsrs r3, r3, #5 + 8003f5c: 2164 movs r1, #100 ; 0x64 + 8003f5e: fb01 f303 mul.w r3, r1, r3 + 8003f62: 1ad3 subs r3, r2, r3 + 8003f64: 00db lsls r3, r3, #3 + 8003f66: 3332 adds r3, #50 ; 0x32 + 8003f68: 4a27 ldr r2, [pc, #156] ; (8004008 ) + 8003f6a: fba2 2303 umull r2, r3, r2, r3 + 8003f6e: 095b lsrs r3, r3, #5 + 8003f70: 005b lsls r3, r3, #1 + 8003f72: f403 73f8 and.w r3, r3, #496 ; 0x1f0 + 8003f76: 4498 add r8, r3 + 8003f78: 68bb ldr r3, [r7, #8] + 8003f7a: 461d mov r5, r3 + 8003f7c: f04f 0600 mov.w r6, #0 + 8003f80: 46a9 mov r9, r5 + 8003f82: 46b2 mov sl, r6 + 8003f84: eb19 0309 adds.w r3, r9, r9 + 8003f88: eb4a 040a adc.w r4, sl, sl + 8003f8c: 4699 mov r9, r3 + 8003f8e: 46a2 mov sl, r4 + 8003f90: eb19 0905 adds.w r9, r9, r5 + 8003f94: eb4a 0a06 adc.w sl, sl, r6 + 8003f98: f04f 0100 mov.w r1, #0 + 8003f9c: f04f 0200 mov.w r2, #0 + 8003fa0: ea4f 02ca mov.w r2, sl, lsl #3 + 8003fa4: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8003fa8: ea4f 01c9 mov.w r1, r9, lsl #3 + 8003fac: 4689 mov r9, r1 + 8003fae: 4692 mov sl, r2 + 8003fb0: eb19 0005 adds.w r0, r9, r5 + 8003fb4: eb4a 0106 adc.w r1, sl, r6 + 8003fb8: 687b ldr r3, [r7, #4] + 8003fba: 685b ldr r3, [r3, #4] + 8003fbc: 461d mov r5, r3 + 8003fbe: f04f 0600 mov.w r6, #0 + 8003fc2: 196b adds r3, r5, r5 + 8003fc4: eb46 0406 adc.w r4, r6, r6 + 8003fc8: 461a mov r2, r3 + 8003fca: 4623 mov r3, r4 + 8003fcc: f7fc fda0 bl 8000b10 <__aeabi_uldivmod> + 8003fd0: 4603 mov r3, r0 + 8003fd2: 460c mov r4, r1 + 8003fd4: 461a mov r2, r3 + 8003fd6: 4b0c ldr r3, [pc, #48] ; (8004008 ) + 8003fd8: fba3 1302 umull r1, r3, r3, r2 + 8003fdc: 095b lsrs r3, r3, #5 + 8003fde: 2164 movs r1, #100 ; 0x64 + 8003fe0: fb01 f303 mul.w r3, r1, r3 + 8003fe4: 1ad3 subs r3, r2, r3 + 8003fe6: 00db lsls r3, r3, #3 + 8003fe8: 3332 adds r3, #50 ; 0x32 + 8003fea: 4a07 ldr r2, [pc, #28] ; (8004008 ) + 8003fec: fba2 2303 umull r2, r3, r2, r3 + 8003ff0: 095b lsrs r3, r3, #5 + 8003ff2: f003 0207 and.w r2, r3, #7 + 8003ff6: 687b ldr r3, [r7, #4] + 8003ff8: 681b ldr r3, [r3, #0] + 8003ffa: 4442 add r2, r8 + 8003ffc: 609a str r2, [r3, #8] + { + pclk = HAL_RCC_GetPCLK1Freq(); + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + } } } - 80024ca: e04a b.n 8002562 - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - 80024cc: 68fa ldr r2, [r7, #12] - 80024ce: 4613 mov r3, r2 - 80024d0: 009b lsls r3, r3, #2 - 80024d2: 4413 add r3, r2 - 80024d4: 009a lsls r2, r3, #2 - 80024d6: 441a add r2, r3 - 80024d8: 687b ldr r3, [r7, #4] - 80024da: 685b ldr r3, [r3, #4] - 80024dc: 009b lsls r3, r3, #2 - 80024de: fbb2 f3f3 udiv r3, r2, r3 - 80024e2: 4a23 ldr r2, [pc, #140] ; (8002570 ) - 80024e4: fba2 2303 umull r2, r3, r2, r3 - 80024e8: 095b lsrs r3, r3, #5 - 80024ea: 0119 lsls r1, r3, #4 - 80024ec: 68fa ldr r2, [r7, #12] - 80024ee: 4613 mov r3, r2 - 80024f0: 009b lsls r3, r3, #2 - 80024f2: 4413 add r3, r2 - 80024f4: 009a lsls r2, r3, #2 - 80024f6: 441a add r2, r3 - 80024f8: 687b ldr r3, [r7, #4] - 80024fa: 685b ldr r3, [r3, #4] - 80024fc: 009b lsls r3, r3, #2 - 80024fe: fbb2 f2f3 udiv r2, r2, r3 - 8002502: 4b1b ldr r3, [pc, #108] ; (8002570 ) - 8002504: fba3 0302 umull r0, r3, r3, r2 - 8002508: 095b lsrs r3, r3, #5 - 800250a: 2064 movs r0, #100 ; 0x64 - 800250c: fb00 f303 mul.w r3, r0, r3 - 8002510: 1ad3 subs r3, r2, r3 - 8002512: 011b lsls r3, r3, #4 - 8002514: 3332 adds r3, #50 ; 0x32 - 8002516: 4a16 ldr r2, [pc, #88] ; (8002570 ) - 8002518: fba2 2303 umull r2, r3, r2, r3 - 800251c: 095b lsrs r3, r3, #5 - 800251e: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 8002522: 4419 add r1, r3 - 8002524: 68fa ldr r2, [r7, #12] - 8002526: 4613 mov r3, r2 - 8002528: 009b lsls r3, r3, #2 - 800252a: 4413 add r3, r2 - 800252c: 009a lsls r2, r3, #2 - 800252e: 441a add r2, r3 - 8002530: 687b ldr r3, [r7, #4] - 8002532: 685b ldr r3, [r3, #4] - 8002534: 009b lsls r3, r3, #2 - 8002536: fbb2 f2f3 udiv r2, r2, r3 - 800253a: 4b0d ldr r3, [pc, #52] ; (8002570 ) - 800253c: fba3 0302 umull r0, r3, r3, r2 - 8002540: 095b lsrs r3, r3, #5 - 8002542: 2064 movs r0, #100 ; 0x64 - 8002544: fb00 f303 mul.w r3, r0, r3 - 8002548: 1ad3 subs r3, r2, r3 - 800254a: 011b lsls r3, r3, #4 - 800254c: 3332 adds r3, #50 ; 0x32 - 800254e: 4a08 ldr r2, [pc, #32] ; (8002570 ) - 8002550: fba2 2303 umull r2, r3, r2, r3 - 8002554: 095b lsrs r3, r3, #5 - 8002556: f003 020f and.w r2, r3, #15 - 800255a: 687b ldr r3, [r7, #4] - 800255c: 681b ldr r3, [r3, #0] - 800255e: 440a add r2, r1 - 8002560: 609a str r2, [r3, #8] + 8003ffe: e1b2 b.n 8004366 + 8004000: 40011000 .word 0x40011000 + 8004004: 40011400 .word 0x40011400 + 8004008: 51eb851f .word 0x51eb851f + if ((huart->Instance == USART1) || (huart->Instance == USART6)) + 800400c: 687b ldr r3, [r7, #4] + 800400e: 681b ldr r3, [r3, #0] + 8004010: 4ad7 ldr r2, [pc, #860] ; (8004370 ) + 8004012: 4293 cmp r3, r2 + 8004014: d005 beq.n 8004022 + 8004016: 687b ldr r3, [r7, #4] + 8004018: 681b ldr r3, [r3, #0] + 800401a: 4ad6 ldr r2, [pc, #856] ; (8004374 ) + 800401c: 4293 cmp r3, r2 + 800401e: f040 80d1 bne.w 80041c4 + pclk = HAL_RCC_GetPCLK2Freq(); + 8004022: f7fe ff43 bl 8002eac + 8004026: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 8004028: 68bb ldr r3, [r7, #8] + 800402a: 469a mov sl, r3 + 800402c: f04f 0b00 mov.w fp, #0 + 8004030: 46d0 mov r8, sl + 8004032: 46d9 mov r9, fp + 8004034: eb18 0308 adds.w r3, r8, r8 + 8004038: eb49 0409 adc.w r4, r9, r9 + 800403c: 4698 mov r8, r3 + 800403e: 46a1 mov r9, r4 + 8004040: eb18 080a adds.w r8, r8, sl + 8004044: eb49 090b adc.w r9, r9, fp + 8004048: f04f 0100 mov.w r1, #0 + 800404c: f04f 0200 mov.w r2, #0 + 8004050: ea4f 02c9 mov.w r2, r9, lsl #3 + 8004054: ea42 7258 orr.w r2, r2, r8, lsr #29 + 8004058: ea4f 01c8 mov.w r1, r8, lsl #3 + 800405c: 4688 mov r8, r1 + 800405e: 4691 mov r9, r2 + 8004060: eb1a 0508 adds.w r5, sl, r8 + 8004064: eb4b 0609 adc.w r6, fp, r9 + 8004068: 687b ldr r3, [r7, #4] + 800406a: 685b ldr r3, [r3, #4] + 800406c: 4619 mov r1, r3 + 800406e: f04f 0200 mov.w r2, #0 + 8004072: f04f 0300 mov.w r3, #0 + 8004076: f04f 0400 mov.w r4, #0 + 800407a: 0094 lsls r4, r2, #2 + 800407c: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8004080: 008b lsls r3, r1, #2 + 8004082: 461a mov r2, r3 + 8004084: 4623 mov r3, r4 + 8004086: 4628 mov r0, r5 + 8004088: 4631 mov r1, r6 + 800408a: f7fc fd41 bl 8000b10 <__aeabi_uldivmod> + 800408e: 4603 mov r3, r0 + 8004090: 460c mov r4, r1 + 8004092: 461a mov r2, r3 + 8004094: 4bb8 ldr r3, [pc, #736] ; (8004378 ) + 8004096: fba3 2302 umull r2, r3, r3, r2 + 800409a: 095b lsrs r3, r3, #5 + 800409c: ea4f 1803 mov.w r8, r3, lsl #4 + 80040a0: 68bb ldr r3, [r7, #8] + 80040a2: 469b mov fp, r3 + 80040a4: f04f 0c00 mov.w ip, #0 + 80040a8: 46d9 mov r9, fp + 80040aa: 46e2 mov sl, ip + 80040ac: eb19 0309 adds.w r3, r9, r9 + 80040b0: eb4a 040a adc.w r4, sl, sl + 80040b4: 4699 mov r9, r3 + 80040b6: 46a2 mov sl, r4 + 80040b8: eb19 090b adds.w r9, r9, fp + 80040bc: eb4a 0a0c adc.w sl, sl, ip + 80040c0: f04f 0100 mov.w r1, #0 + 80040c4: f04f 0200 mov.w r2, #0 + 80040c8: ea4f 02ca mov.w r2, sl, lsl #3 + 80040cc: ea42 7259 orr.w r2, r2, r9, lsr #29 + 80040d0: ea4f 01c9 mov.w r1, r9, lsl #3 + 80040d4: 4689 mov r9, r1 + 80040d6: 4692 mov sl, r2 + 80040d8: eb1b 0509 adds.w r5, fp, r9 + 80040dc: eb4c 060a adc.w r6, ip, sl + 80040e0: 687b ldr r3, [r7, #4] + 80040e2: 685b ldr r3, [r3, #4] + 80040e4: 4619 mov r1, r3 + 80040e6: f04f 0200 mov.w r2, #0 + 80040ea: f04f 0300 mov.w r3, #0 + 80040ee: f04f 0400 mov.w r4, #0 + 80040f2: 0094 lsls r4, r2, #2 + 80040f4: ea44 7491 orr.w r4, r4, r1, lsr #30 + 80040f8: 008b lsls r3, r1, #2 + 80040fa: 461a mov r2, r3 + 80040fc: 4623 mov r3, r4 + 80040fe: 4628 mov r0, r5 + 8004100: 4631 mov r1, r6 + 8004102: f7fc fd05 bl 8000b10 <__aeabi_uldivmod> + 8004106: 4603 mov r3, r0 + 8004108: 460c mov r4, r1 + 800410a: 461a mov r2, r3 + 800410c: 4b9a ldr r3, [pc, #616] ; (8004378 ) + 800410e: fba3 1302 umull r1, r3, r3, r2 + 8004112: 095b lsrs r3, r3, #5 + 8004114: 2164 movs r1, #100 ; 0x64 + 8004116: fb01 f303 mul.w r3, r1, r3 + 800411a: 1ad3 subs r3, r2, r3 + 800411c: 011b lsls r3, r3, #4 + 800411e: 3332 adds r3, #50 ; 0x32 + 8004120: 4a95 ldr r2, [pc, #596] ; (8004378 ) + 8004122: fba2 2303 umull r2, r3, r2, r3 + 8004126: 095b lsrs r3, r3, #5 + 8004128: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 800412c: 4498 add r8, r3 + 800412e: 68bb ldr r3, [r7, #8] + 8004130: 469b mov fp, r3 + 8004132: f04f 0c00 mov.w ip, #0 + 8004136: 46d9 mov r9, fp + 8004138: 46e2 mov sl, ip + 800413a: eb19 0309 adds.w r3, r9, r9 + 800413e: eb4a 040a adc.w r4, sl, sl + 8004142: 4699 mov r9, r3 + 8004144: 46a2 mov sl, r4 + 8004146: eb19 090b adds.w r9, r9, fp + 800414a: eb4a 0a0c adc.w sl, sl, ip + 800414e: f04f 0100 mov.w r1, #0 + 8004152: f04f 0200 mov.w r2, #0 + 8004156: ea4f 02ca mov.w r2, sl, lsl #3 + 800415a: ea42 7259 orr.w r2, r2, r9, lsr #29 + 800415e: ea4f 01c9 mov.w r1, r9, lsl #3 + 8004162: 4689 mov r9, r1 + 8004164: 4692 mov sl, r2 + 8004166: eb1b 0509 adds.w r5, fp, r9 + 800416a: eb4c 060a adc.w r6, ip, sl + 800416e: 687b ldr r3, [r7, #4] + 8004170: 685b ldr r3, [r3, #4] + 8004172: 4619 mov r1, r3 + 8004174: f04f 0200 mov.w r2, #0 + 8004178: f04f 0300 mov.w r3, #0 + 800417c: f04f 0400 mov.w r4, #0 + 8004180: 0094 lsls r4, r2, #2 + 8004182: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8004186: 008b lsls r3, r1, #2 + 8004188: 461a mov r2, r3 + 800418a: 4623 mov r3, r4 + 800418c: 4628 mov r0, r5 + 800418e: 4631 mov r1, r6 + 8004190: f7fc fcbe bl 8000b10 <__aeabi_uldivmod> + 8004194: 4603 mov r3, r0 + 8004196: 460c mov r4, r1 + 8004198: 461a mov r2, r3 + 800419a: 4b77 ldr r3, [pc, #476] ; (8004378 ) + 800419c: fba3 1302 umull r1, r3, r3, r2 + 80041a0: 095b lsrs r3, r3, #5 + 80041a2: 2164 movs r1, #100 ; 0x64 + 80041a4: fb01 f303 mul.w r3, r1, r3 + 80041a8: 1ad3 subs r3, r2, r3 + 80041aa: 011b lsls r3, r3, #4 + 80041ac: 3332 adds r3, #50 ; 0x32 + 80041ae: 4a72 ldr r2, [pc, #456] ; (8004378 ) + 80041b0: fba2 2303 umull r2, r3, r2, r3 + 80041b4: 095b lsrs r3, r3, #5 + 80041b6: f003 020f and.w r2, r3, #15 + 80041ba: 687b ldr r3, [r7, #4] + 80041bc: 681b ldr r3, [r3, #0] + 80041be: 4442 add r2, r8 + 80041c0: 609a str r2, [r3, #8] + 80041c2: e0d0 b.n 8004366 + pclk = HAL_RCC_GetPCLK1Freq(); + 80041c4: f7fe fe5e bl 8002e84 + 80041c8: 60b8 str r0, [r7, #8] + huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); + 80041ca: 68bb ldr r3, [r7, #8] + 80041cc: 469a mov sl, r3 + 80041ce: f04f 0b00 mov.w fp, #0 + 80041d2: 46d0 mov r8, sl + 80041d4: 46d9 mov r9, fp + 80041d6: eb18 0308 adds.w r3, r8, r8 + 80041da: eb49 0409 adc.w r4, r9, r9 + 80041de: 4698 mov r8, r3 + 80041e0: 46a1 mov r9, r4 + 80041e2: eb18 080a adds.w r8, r8, sl + 80041e6: eb49 090b adc.w r9, r9, fp + 80041ea: f04f 0100 mov.w r1, #0 + 80041ee: f04f 0200 mov.w r2, #0 + 80041f2: ea4f 02c9 mov.w r2, r9, lsl #3 + 80041f6: ea42 7258 orr.w r2, r2, r8, lsr #29 + 80041fa: ea4f 01c8 mov.w r1, r8, lsl #3 + 80041fe: 4688 mov r8, r1 + 8004200: 4691 mov r9, r2 + 8004202: eb1a 0508 adds.w r5, sl, r8 + 8004206: eb4b 0609 adc.w r6, fp, r9 + 800420a: 687b ldr r3, [r7, #4] + 800420c: 685b ldr r3, [r3, #4] + 800420e: 4619 mov r1, r3 + 8004210: f04f 0200 mov.w r2, #0 + 8004214: f04f 0300 mov.w r3, #0 + 8004218: f04f 0400 mov.w r4, #0 + 800421c: 0094 lsls r4, r2, #2 + 800421e: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8004222: 008b lsls r3, r1, #2 + 8004224: 461a mov r2, r3 + 8004226: 4623 mov r3, r4 + 8004228: 4628 mov r0, r5 + 800422a: 4631 mov r1, r6 + 800422c: f7fc fc70 bl 8000b10 <__aeabi_uldivmod> + 8004230: 4603 mov r3, r0 + 8004232: 460c mov r4, r1 + 8004234: 461a mov r2, r3 + 8004236: 4b50 ldr r3, [pc, #320] ; (8004378 ) + 8004238: fba3 2302 umull r2, r3, r3, r2 + 800423c: 095b lsrs r3, r3, #5 + 800423e: ea4f 1803 mov.w r8, r3, lsl #4 + 8004242: 68bb ldr r3, [r7, #8] + 8004244: 469b mov fp, r3 + 8004246: f04f 0c00 mov.w ip, #0 + 800424a: 46d9 mov r9, fp + 800424c: 46e2 mov sl, ip + 800424e: eb19 0309 adds.w r3, r9, r9 + 8004252: eb4a 040a adc.w r4, sl, sl + 8004256: 4699 mov r9, r3 + 8004258: 46a2 mov sl, r4 + 800425a: eb19 090b adds.w r9, r9, fp + 800425e: eb4a 0a0c adc.w sl, sl, ip + 8004262: f04f 0100 mov.w r1, #0 + 8004266: f04f 0200 mov.w r2, #0 + 800426a: ea4f 02ca mov.w r2, sl, lsl #3 + 800426e: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8004272: ea4f 01c9 mov.w r1, r9, lsl #3 + 8004276: 4689 mov r9, r1 + 8004278: 4692 mov sl, r2 + 800427a: eb1b 0509 adds.w r5, fp, r9 + 800427e: eb4c 060a adc.w r6, ip, sl + 8004282: 687b ldr r3, [r7, #4] + 8004284: 685b ldr r3, [r3, #4] + 8004286: 4619 mov r1, r3 + 8004288: f04f 0200 mov.w r2, #0 + 800428c: f04f 0300 mov.w r3, #0 + 8004290: f04f 0400 mov.w r4, #0 + 8004294: 0094 lsls r4, r2, #2 + 8004296: ea44 7491 orr.w r4, r4, r1, lsr #30 + 800429a: 008b lsls r3, r1, #2 + 800429c: 461a mov r2, r3 + 800429e: 4623 mov r3, r4 + 80042a0: 4628 mov r0, r5 + 80042a2: 4631 mov r1, r6 + 80042a4: f7fc fc34 bl 8000b10 <__aeabi_uldivmod> + 80042a8: 4603 mov r3, r0 + 80042aa: 460c mov r4, r1 + 80042ac: 461a mov r2, r3 + 80042ae: 4b32 ldr r3, [pc, #200] ; (8004378 ) + 80042b0: fba3 1302 umull r1, r3, r3, r2 + 80042b4: 095b lsrs r3, r3, #5 + 80042b6: 2164 movs r1, #100 ; 0x64 + 80042b8: fb01 f303 mul.w r3, r1, r3 + 80042bc: 1ad3 subs r3, r2, r3 + 80042be: 011b lsls r3, r3, #4 + 80042c0: 3332 adds r3, #50 ; 0x32 + 80042c2: 4a2d ldr r2, [pc, #180] ; (8004378 ) + 80042c4: fba2 2303 umull r2, r3, r2, r3 + 80042c8: 095b lsrs r3, r3, #5 + 80042ca: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 80042ce: 4498 add r8, r3 + 80042d0: 68bb ldr r3, [r7, #8] + 80042d2: 469b mov fp, r3 + 80042d4: f04f 0c00 mov.w ip, #0 + 80042d8: 46d9 mov r9, fp + 80042da: 46e2 mov sl, ip + 80042dc: eb19 0309 adds.w r3, r9, r9 + 80042e0: eb4a 040a adc.w r4, sl, sl + 80042e4: 4699 mov r9, r3 + 80042e6: 46a2 mov sl, r4 + 80042e8: eb19 090b adds.w r9, r9, fp + 80042ec: eb4a 0a0c adc.w sl, sl, ip + 80042f0: f04f 0100 mov.w r1, #0 + 80042f4: f04f 0200 mov.w r2, #0 + 80042f8: ea4f 02ca mov.w r2, sl, lsl #3 + 80042fc: ea42 7259 orr.w r2, r2, r9, lsr #29 + 8004300: ea4f 01c9 mov.w r1, r9, lsl #3 + 8004304: 4689 mov r9, r1 + 8004306: 4692 mov sl, r2 + 8004308: eb1b 0509 adds.w r5, fp, r9 + 800430c: eb4c 060a adc.w r6, ip, sl + 8004310: 687b ldr r3, [r7, #4] + 8004312: 685b ldr r3, [r3, #4] + 8004314: 4619 mov r1, r3 + 8004316: f04f 0200 mov.w r2, #0 + 800431a: f04f 0300 mov.w r3, #0 + 800431e: f04f 0400 mov.w r4, #0 + 8004322: 0094 lsls r4, r2, #2 + 8004324: ea44 7491 orr.w r4, r4, r1, lsr #30 + 8004328: 008b lsls r3, r1, #2 + 800432a: 461a mov r2, r3 + 800432c: 4623 mov r3, r4 + 800432e: 4628 mov r0, r5 + 8004330: 4631 mov r1, r6 + 8004332: f7fc fbed bl 8000b10 <__aeabi_uldivmod> + 8004336: 4603 mov r3, r0 + 8004338: 460c mov r4, r1 + 800433a: 461a mov r2, r3 + 800433c: 4b0e ldr r3, [pc, #56] ; (8004378 ) + 800433e: fba3 1302 umull r1, r3, r3, r2 + 8004342: 095b lsrs r3, r3, #5 + 8004344: 2164 movs r1, #100 ; 0x64 + 8004346: fb01 f303 mul.w r3, r1, r3 + 800434a: 1ad3 subs r3, r2, r3 + 800434c: 011b lsls r3, r3, #4 + 800434e: 3332 adds r3, #50 ; 0x32 + 8004350: 4a09 ldr r2, [pc, #36] ; (8004378 ) + 8004352: fba2 2303 umull r2, r3, r2, r3 + 8004356: 095b lsrs r3, r3, #5 + 8004358: f003 020f and.w r2, r3, #15 + 800435c: 687b ldr r3, [r7, #4] + 800435e: 681b ldr r3, [r3, #0] + 8004360: 4442 add r2, r8 + 8004362: 609a str r2, [r3, #8] } - 8002562: bf00 nop - 8002564: 3710 adds r7, #16 - 8002566: 46bd mov sp, r7 - 8002568: bd80 pop {r7, pc} - 800256a: bf00 nop - 800256c: 40013800 .word 0x40013800 - 8002570: 51eb851f .word 0x51eb851f + 8004364: e7ff b.n 8004366 + 8004366: bf00 nop + 8004368: 3714 adds r7, #20 + 800436a: 46bd mov sp, r7 + 800436c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8004370: 40011000 .word 0x40011000 + 8004374: 40011400 .word 0x40011400 + 8004378: 51eb851f .word 0x51eb851f -08002574 <__libc_init_array>: - 8002574: b570 push {r4, r5, r6, lr} - 8002576: 2500 movs r5, #0 - 8002578: 4e0c ldr r6, [pc, #48] ; (80025ac <__libc_init_array+0x38>) - 800257a: 4c0d ldr r4, [pc, #52] ; (80025b0 <__libc_init_array+0x3c>) - 800257c: 1ba4 subs r4, r4, r6 - 800257e: 10a4 asrs r4, r4, #2 - 8002580: 42a5 cmp r5, r4 - 8002582: d109 bne.n 8002598 <__libc_init_array+0x24> - 8002584: f000 f822 bl 80025cc <_init> - 8002588: 2500 movs r5, #0 - 800258a: 4e0a ldr r6, [pc, #40] ; (80025b4 <__libc_init_array+0x40>) - 800258c: 4c0a ldr r4, [pc, #40] ; (80025b8 <__libc_init_array+0x44>) - 800258e: 1ba4 subs r4, r4, r6 - 8002590: 10a4 asrs r4, r4, #2 - 8002592: 42a5 cmp r5, r4 - 8002594: d105 bne.n 80025a2 <__libc_init_array+0x2e> - 8002596: bd70 pop {r4, r5, r6, pc} - 8002598: f856 3025 ldr.w r3, [r6, r5, lsl #2] - 800259c: 4798 blx r3 - 800259e: 3501 adds r5, #1 - 80025a0: e7ee b.n 8002580 <__libc_init_array+0xc> - 80025a2: f856 3025 ldr.w r3, [r6, r5, lsl #2] - 80025a6: 4798 blx r3 - 80025a8: 3501 adds r5, #1 - 80025aa: e7f2 b.n 8002592 <__libc_init_array+0x1e> - 80025ac: 08002610 .word 0x08002610 - 80025b0: 08002610 .word 0x08002610 - 80025b4: 08002610 .word 0x08002610 - 80025b8: 08002614 .word 0x08002614 +0800437c <__errno>: + 800437c: 4b01 ldr r3, [pc, #4] ; (8004384 <__errno+0x8>) + 800437e: 6818 ldr r0, [r3, #0] + 8004380: 4770 bx lr + 8004382: bf00 nop + 8004384: 20000020 .word 0x20000020 -080025bc : - 80025bc: 4603 mov r3, r0 - 80025be: 4402 add r2, r0 - 80025c0: 4293 cmp r3, r2 - 80025c2: d100 bne.n 80025c6 - 80025c4: 4770 bx lr - 80025c6: f803 1b01 strb.w r1, [r3], #1 - 80025ca: e7f9 b.n 80025c0 +08004388 <__libc_init_array>: + 8004388: b570 push {r4, r5, r6, lr} + 800438a: 4e0d ldr r6, [pc, #52] ; (80043c0 <__libc_init_array+0x38>) + 800438c: 4c0d ldr r4, [pc, #52] ; (80043c4 <__libc_init_array+0x3c>) + 800438e: 1ba4 subs r4, r4, r6 + 8004390: 10a4 asrs r4, r4, #2 + 8004392: 2500 movs r5, #0 + 8004394: 42a5 cmp r5, r4 + 8004396: d109 bne.n 80043ac <__libc_init_array+0x24> + 8004398: 4e0b ldr r6, [pc, #44] ; (80043c8 <__libc_init_array+0x40>) + 800439a: 4c0c ldr r4, [pc, #48] ; (80043cc <__libc_init_array+0x44>) + 800439c: f001 fde2 bl 8005f64 <_init> + 80043a0: 1ba4 subs r4, r4, r6 + 80043a2: 10a4 asrs r4, r4, #2 + 80043a4: 2500 movs r5, #0 + 80043a6: 42a5 cmp r5, r4 + 80043a8: d105 bne.n 80043b6 <__libc_init_array+0x2e> + 80043aa: bd70 pop {r4, r5, r6, pc} + 80043ac: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 80043b0: 4798 blx r3 + 80043b2: 3501 adds r5, #1 + 80043b4: e7ee b.n 8004394 <__libc_init_array+0xc> + 80043b6: f856 3025 ldr.w r3, [r6, r5, lsl #2] + 80043ba: 4798 blx r3 + 80043bc: 3501 adds r5, #1 + 80043be: e7f2 b.n 80043a6 <__libc_init_array+0x1e> + 80043c0: 08006218 .word 0x08006218 + 80043c4: 08006218 .word 0x08006218 + 80043c8: 08006218 .word 0x08006218 + 80043cc: 0800621c .word 0x0800621c -080025cc <_init>: - 80025cc: b5f8 push {r3, r4, r5, r6, r7, lr} - 80025ce: bf00 nop - 80025d0: bcf8 pop {r3, r4, r5, r6, r7} - 80025d2: bc08 pop {r3} - 80025d4: 469e mov lr, r3 - 80025d6: 4770 bx lr +080043d0 : + 80043d0: 4402 add r2, r0 + 80043d2: 4603 mov r3, r0 + 80043d4: 4293 cmp r3, r2 + 80043d6: d100 bne.n 80043da + 80043d8: 4770 bx lr + 80043da: f803 1b01 strb.w r1, [r3], #1 + 80043de: e7f9 b.n 80043d4 -080025d8 <_fini>: - 80025d8: b5f8 push {r3, r4, r5, r6, r7, lr} - 80025da: bf00 nop - 80025dc: bcf8 pop {r3, r4, r5, r6, r7} - 80025de: bc08 pop {r3} - 80025e0: 469e mov lr, r3 - 80025e2: 4770 bx lr +080043e0 : + 80043e0: b51f push {r0, r1, r2, r3, r4, lr} + 80043e2: ec51 0b10 vmov r0, r1, d0 + 80043e6: 4a1e ldr r2, [pc, #120] ; (8004460 ) + 80043e8: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 80043ec: 4293 cmp r3, r2 + 80043ee: dc06 bgt.n 80043fe + 80043f0: ed9f 1b19 vldr d1, [pc, #100] ; 8004458 + 80043f4: f000 fe8c bl 8005110 <__kernel_cos> + 80043f8: ec51 0b10 vmov r0, r1, d0 + 80043fc: e007 b.n 800440e + 80043fe: 4a19 ldr r2, [pc, #100] ; (8004464 ) + 8004400: 4293 cmp r3, r2 + 8004402: dd09 ble.n 8004418 + 8004404: ee10 2a10 vmov r2, s0 + 8004408: 460b mov r3, r1 + 800440a: f7fb fef1 bl 80001f0 <__aeabi_dsub> + 800440e: ec41 0b10 vmov d0, r0, r1 + 8004412: b005 add sp, #20 + 8004414: f85d fb04 ldr.w pc, [sp], #4 + 8004418: 4668 mov r0, sp + 800441a: f000 fbd5 bl 8004bc8 <__ieee754_rem_pio2> + 800441e: f000 0003 and.w r0, r0, #3 + 8004422: 2801 cmp r0, #1 + 8004424: ed9d 1b02 vldr d1, [sp, #8] + 8004428: ed9d 0b00 vldr d0, [sp] + 800442c: d007 beq.n 800443e + 800442e: 2802 cmp r0, #2 + 8004430: d00e beq.n 8004450 + 8004432: 2800 cmp r0, #0 + 8004434: d0de beq.n 80043f4 + 8004436: 2001 movs r0, #1 + 8004438: f001 fa72 bl 8005920 <__kernel_sin> + 800443c: e7dc b.n 80043f8 + 800443e: f001 fa6f bl 8005920 <__kernel_sin> + 8004442: ec53 2b10 vmov r2, r3, d0 + 8004446: ee10 0a10 vmov r0, s0 + 800444a: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 + 800444e: e7de b.n 800440e + 8004450: f000 fe5e bl 8005110 <__kernel_cos> + 8004454: e7f5 b.n 8004442 + 8004456: bf00 nop + ... + 8004460: 3fe921fb .word 0x3fe921fb + 8004464: 7fefffff .word 0x7fefffff + +08004468 : + 8004468: ec51 0b10 vmov r0, r1, d0 + 800446c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8004470: f3c1 570a ubfx r7, r1, #20, #11 + 8004474: f2a7 36ff subw r6, r7, #1023 ; 0x3ff + 8004478: 2e13 cmp r6, #19 + 800447a: 460c mov r4, r1 + 800447c: ee10 5a10 vmov r5, s0 + 8004480: 4680 mov r8, r0 + 8004482: dc34 bgt.n 80044ee + 8004484: 2e00 cmp r6, #0 + 8004486: da16 bge.n 80044b6 + 8004488: a335 add r3, pc, #212 ; (adr r3, 8004560 ) + 800448a: e9d3 2300 ldrd r2, r3, [r3] + 800448e: f7fb feb1 bl 80001f4 <__adddf3> + 8004492: 2200 movs r2, #0 + 8004494: 2300 movs r3, #0 + 8004496: f7fc faf3 bl 8000a80 <__aeabi_dcmpgt> + 800449a: b148 cbz r0, 80044b0 + 800449c: 2c00 cmp r4, #0 + 800449e: da59 bge.n 8004554 + 80044a0: f024 4300 bic.w r3, r4, #2147483648 ; 0x80000000 + 80044a4: 4a30 ldr r2, [pc, #192] ; (8004568 ) + 80044a6: 432b orrs r3, r5 + 80044a8: 2500 movs r5, #0 + 80044aa: 42ab cmp r3, r5 + 80044ac: bf18 it ne + 80044ae: 4614 movne r4, r2 + 80044b0: 4621 mov r1, r4 + 80044b2: 4628 mov r0, r5 + 80044b4: e025 b.n 8004502 + 80044b6: 4f2d ldr r7, [pc, #180] ; (800456c ) + 80044b8: 4137 asrs r7, r6 + 80044ba: ea01 0307 and.w r3, r1, r7 + 80044be: 4303 orrs r3, r0 + 80044c0: d01f beq.n 8004502 + 80044c2: a327 add r3, pc, #156 ; (adr r3, 8004560 ) + 80044c4: e9d3 2300 ldrd r2, r3, [r3] + 80044c8: f7fb fe94 bl 80001f4 <__adddf3> + 80044cc: 2200 movs r2, #0 + 80044ce: 2300 movs r3, #0 + 80044d0: f7fc fad6 bl 8000a80 <__aeabi_dcmpgt> + 80044d4: 2800 cmp r0, #0 + 80044d6: d0eb beq.n 80044b0 + 80044d8: 2c00 cmp r4, #0 + 80044da: bfbe ittt lt + 80044dc: f44f 1380 movlt.w r3, #1048576 ; 0x100000 + 80044e0: fa43 f606 asrlt.w r6, r3, r6 + 80044e4: 19a4 addlt r4, r4, r6 + 80044e6: ea24 0407 bic.w r4, r4, r7 + 80044ea: 2500 movs r5, #0 + 80044ec: e7e0 b.n 80044b0 + 80044ee: 2e33 cmp r6, #51 ; 0x33 + 80044f0: dd0b ble.n 800450a + 80044f2: f5b6 6f80 cmp.w r6, #1024 ; 0x400 + 80044f6: d104 bne.n 8004502 + 80044f8: ee10 2a10 vmov r2, s0 + 80044fc: 460b mov r3, r1 + 80044fe: f7fb fe79 bl 80001f4 <__adddf3> + 8004502: ec41 0b10 vmov d0, r0, r1 + 8004506: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 800450a: f2a7 4713 subw r7, r7, #1043 ; 0x413 + 800450e: f04f 33ff mov.w r3, #4294967295 + 8004512: fa23 f707 lsr.w r7, r3, r7 + 8004516: 4207 tst r7, r0 + 8004518: d0f3 beq.n 8004502 + 800451a: a311 add r3, pc, #68 ; (adr r3, 8004560 ) + 800451c: e9d3 2300 ldrd r2, r3, [r3] + 8004520: f7fb fe68 bl 80001f4 <__adddf3> + 8004524: 2200 movs r2, #0 + 8004526: 2300 movs r3, #0 + 8004528: f7fc faaa bl 8000a80 <__aeabi_dcmpgt> + 800452c: 2800 cmp r0, #0 + 800452e: d0bf beq.n 80044b0 + 8004530: 2c00 cmp r4, #0 + 8004532: da02 bge.n 800453a + 8004534: 2e14 cmp r6, #20 + 8004536: d103 bne.n 8004540 + 8004538: 3401 adds r4, #1 + 800453a: ea25 0507 bic.w r5, r5, r7 + 800453e: e7b7 b.n 80044b0 + 8004540: 2301 movs r3, #1 + 8004542: f1c6 0634 rsb r6, r6, #52 ; 0x34 + 8004546: fa03 f606 lsl.w r6, r3, r6 + 800454a: 4435 add r5, r6 + 800454c: 4545 cmp r5, r8 + 800454e: bf38 it cc + 8004550: 18e4 addcc r4, r4, r3 + 8004552: e7f2 b.n 800453a + 8004554: 2500 movs r5, #0 + 8004556: 462c mov r4, r5 + 8004558: e7aa b.n 80044b0 + 800455a: bf00 nop + 800455c: f3af 8000 nop.w + 8004560: 8800759c .word 0x8800759c + 8004564: 7e37e43c .word 0x7e37e43c + 8004568: bff00000 .word 0xbff00000 + 800456c: 000fffff .word 0x000fffff + +08004570 : + 8004570: b51f push {r0, r1, r2, r3, r4, lr} + 8004572: ec51 0b10 vmov r0, r1, d0 + 8004576: 4a20 ldr r2, [pc, #128] ; (80045f8 ) + 8004578: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800457c: 4293 cmp r3, r2 + 800457e: dc07 bgt.n 8004590 + 8004580: ed9f 1b1b vldr d1, [pc, #108] ; 80045f0 + 8004584: 2000 movs r0, #0 + 8004586: f001 f9cb bl 8005920 <__kernel_sin> + 800458a: ec51 0b10 vmov r0, r1, d0 + 800458e: e007 b.n 80045a0 + 8004590: 4a1a ldr r2, [pc, #104] ; (80045fc ) + 8004592: 4293 cmp r3, r2 + 8004594: dd09 ble.n 80045aa + 8004596: ee10 2a10 vmov r2, s0 + 800459a: 460b mov r3, r1 + 800459c: f7fb fe28 bl 80001f0 <__aeabi_dsub> + 80045a0: ec41 0b10 vmov d0, r0, r1 + 80045a4: b005 add sp, #20 + 80045a6: f85d fb04 ldr.w pc, [sp], #4 + 80045aa: 4668 mov r0, sp + 80045ac: f000 fb0c bl 8004bc8 <__ieee754_rem_pio2> + 80045b0: f000 0003 and.w r0, r0, #3 + 80045b4: 2801 cmp r0, #1 + 80045b6: ed9d 1b02 vldr d1, [sp, #8] + 80045ba: ed9d 0b00 vldr d0, [sp] + 80045be: d004 beq.n 80045ca + 80045c0: 2802 cmp r0, #2 + 80045c2: d005 beq.n 80045d0 + 80045c4: b970 cbnz r0, 80045e4 + 80045c6: 2001 movs r0, #1 + 80045c8: e7dd b.n 8004586 + 80045ca: f000 fda1 bl 8005110 <__kernel_cos> + 80045ce: e7dc b.n 800458a + 80045d0: 2001 movs r0, #1 + 80045d2: f001 f9a5 bl 8005920 <__kernel_sin> + 80045d6: ec53 2b10 vmov r2, r3, d0 + 80045da: ee10 0a10 vmov r0, s0 + 80045de: f103 4100 add.w r1, r3, #2147483648 ; 0x80000000 + 80045e2: e7dd b.n 80045a0 + 80045e4: f000 fd94 bl 8005110 <__kernel_cos> + 80045e8: e7f5 b.n 80045d6 + 80045ea: bf00 nop + 80045ec: f3af 8000 nop.w + ... + 80045f8: 3fe921fb .word 0x3fe921fb + 80045fc: 7fefffff .word 0x7fefffff + +08004600 : + 8004600: b51f push {r0, r1, r2, r3, r4, lr} + 8004602: ec51 0b10 vmov r0, r1, d0 + 8004606: 4a14 ldr r2, [pc, #80] ; (8004658 ) + 8004608: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 800460c: 4293 cmp r3, r2 + 800460e: dc05 bgt.n 800461c + 8004610: ed9f 1b0f vldr d1, [pc, #60] ; 8004650 + 8004614: 2001 movs r0, #1 + 8004616: f001 fa3f bl 8005a98 <__kernel_tan> + 800461a: e009 b.n 8004630 + 800461c: 4a0f ldr r2, [pc, #60] ; (800465c ) + 800461e: 4293 cmp r3, r2 + 8004620: dd09 ble.n 8004636 + 8004622: ee10 2a10 vmov r2, s0 + 8004626: 460b mov r3, r1 + 8004628: f7fb fde2 bl 80001f0 <__aeabi_dsub> + 800462c: ec41 0b10 vmov d0, r0, r1 + 8004630: b005 add sp, #20 + 8004632: f85d fb04 ldr.w pc, [sp], #4 + 8004636: 4668 mov r0, sp + 8004638: f000 fac6 bl 8004bc8 <__ieee754_rem_pio2> + 800463c: 0040 lsls r0, r0, #1 + 800463e: f000 0002 and.w r0, r0, #2 + 8004642: f1c0 0001 rsb r0, r0, #1 + 8004646: ed9d 1b02 vldr d1, [sp, #8] + 800464a: ed9d 0b00 vldr d0, [sp] + 800464e: e7e2 b.n 8004616 + ... + 8004658: 3fe921fb .word 0x3fe921fb + 800465c: 7fefffff .word 0x7fefffff + +08004660 : + 8004660: b5f0 push {r4, r5, r6, r7, lr} + 8004662: ed2d 8b02 vpush {d8} + 8004666: 4e26 ldr r6, [pc, #152] ; (8004700 ) + 8004668: b08b sub sp, #44 ; 0x2c + 800466a: ec55 4b10 vmov r4, r5, d0 + 800466e: f000 f84f bl 8004710 <__ieee754_acos> + 8004672: f996 3000 ldrsb.w r3, [r6] + 8004676: eeb0 8a40 vmov.f32 s16, s0 + 800467a: eef0 8a60 vmov.f32 s17, s1 + 800467e: 3301 adds r3, #1 + 8004680: d036 beq.n 80046f0 + 8004682: 4622 mov r2, r4 + 8004684: 462b mov r3, r5 + 8004686: 4620 mov r0, r4 + 8004688: 4629 mov r1, r5 + 800468a: f7fc fa03 bl 8000a94 <__aeabi_dcmpun> + 800468e: 4607 mov r7, r0 + 8004690: bb70 cbnz r0, 80046f0 + 8004692: ec45 4b10 vmov d0, r4, r5 + 8004696: f001 fbcb bl 8005e30 + 800469a: 2200 movs r2, #0 + 800469c: 4b19 ldr r3, [pc, #100] ; (8004704 ) + 800469e: ec51 0b10 vmov r0, r1, d0 + 80046a2: f7fc f9ed bl 8000a80 <__aeabi_dcmpgt> + 80046a6: b318 cbz r0, 80046f0 + 80046a8: 2301 movs r3, #1 + 80046aa: 9300 str r3, [sp, #0] + 80046ac: 4816 ldr r0, [pc, #88] ; (8004708 ) + 80046ae: 4b17 ldr r3, [pc, #92] ; (800470c ) + 80046b0: 9301 str r3, [sp, #4] + 80046b2: 9708 str r7, [sp, #32] + 80046b4: e9cd 4504 strd r4, r5, [sp, #16] + 80046b8: e9cd 4502 strd r4, r5, [sp, #8] + 80046bc: f001 fbc4 bl 8005e48 + 80046c0: f996 3000 ldrsb.w r3, [r6] + 80046c4: 2b02 cmp r3, #2 + 80046c6: ed8d 0b06 vstr d0, [sp, #24] + 80046ca: d104 bne.n 80046d6 + 80046cc: f7ff fe56 bl 800437c <__errno> + 80046d0: 2321 movs r3, #33 ; 0x21 + 80046d2: 6003 str r3, [r0, #0] + 80046d4: e004 b.n 80046e0 + 80046d6: 4668 mov r0, sp + 80046d8: f001 fbb3 bl 8005e42 + 80046dc: 2800 cmp r0, #0 + 80046de: d0f5 beq.n 80046cc + 80046e0: 9b08 ldr r3, [sp, #32] + 80046e2: b11b cbz r3, 80046ec + 80046e4: f7ff fe4a bl 800437c <__errno> + 80046e8: 9b08 ldr r3, [sp, #32] + 80046ea: 6003 str r3, [r0, #0] + 80046ec: ed9d 8b06 vldr d8, [sp, #24] + 80046f0: eeb0 0a48 vmov.f32 s0, s16 + 80046f4: eef0 0a68 vmov.f32 s1, s17 + 80046f8: b00b add sp, #44 ; 0x2c + 80046fa: ecbd 8b02 vpop {d8} + 80046fe: bdf0 pop {r4, r5, r6, r7, pc} + 8004700: 20000084 .word 0x20000084 + 8004704: 3ff00000 .word 0x3ff00000 + 8004708: 08006034 .word 0x08006034 + 800470c: 08006030 .word 0x08006030 + +08004710 <__ieee754_acos>: + 8004710: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8004714: ec55 4b10 vmov r4, r5, d0 + 8004718: 49b7 ldr r1, [pc, #732] ; (80049f8 <__ieee754_acos+0x2e8>) + 800471a: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 800471e: 428b cmp r3, r1 + 8004720: dd1b ble.n 800475a <__ieee754_acos+0x4a> + 8004722: f103 4340 add.w r3, r3, #3221225472 ; 0xc0000000 + 8004726: f503 1380 add.w r3, r3, #1048576 ; 0x100000 + 800472a: 4323 orrs r3, r4 + 800472c: d109 bne.n 8004742 <__ieee754_acos+0x32> + 800472e: 2d00 cmp r5, #0 + 8004730: f300 8211 bgt.w 8004b56 <__ieee754_acos+0x446> + 8004734: a196 add r1, pc, #600 ; (adr r1, 8004990 <__ieee754_acos+0x280>) + 8004736: e9d1 0100 ldrd r0, r1, [r1] + 800473a: ec41 0b10 vmov d0, r0, r1 + 800473e: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8004742: ee10 2a10 vmov r2, s0 + 8004746: 462b mov r3, r5 + 8004748: 4620 mov r0, r4 + 800474a: 4629 mov r1, r5 + 800474c: f7fb fd50 bl 80001f0 <__aeabi_dsub> + 8004750: 4602 mov r2, r0 + 8004752: 460b mov r3, r1 + 8004754: f7fc f82e bl 80007b4 <__aeabi_ddiv> + 8004758: e7ef b.n 800473a <__ieee754_acos+0x2a> + 800475a: 49a8 ldr r1, [pc, #672] ; (80049fc <__ieee754_acos+0x2ec>) + 800475c: 428b cmp r3, r1 + 800475e: f300 8087 bgt.w 8004870 <__ieee754_acos+0x160> + 8004762: 4aa7 ldr r2, [pc, #668] ; (8004a00 <__ieee754_acos+0x2f0>) + 8004764: 4293 cmp r3, r2 + 8004766: f340 81f9 ble.w 8004b5c <__ieee754_acos+0x44c> + 800476a: ee10 2a10 vmov r2, s0 + 800476e: ee10 0a10 vmov r0, s0 + 8004772: 462b mov r3, r5 + 8004774: 4629 mov r1, r5 + 8004776: f7fb fef3 bl 8000560 <__aeabi_dmul> + 800477a: a387 add r3, pc, #540 ; (adr r3, 8004998 <__ieee754_acos+0x288>) + 800477c: e9d3 2300 ldrd r2, r3, [r3] + 8004780: 4606 mov r6, r0 + 8004782: 460f mov r7, r1 + 8004784: f7fb feec bl 8000560 <__aeabi_dmul> + 8004788: a385 add r3, pc, #532 ; (adr r3, 80049a0 <__ieee754_acos+0x290>) + 800478a: e9d3 2300 ldrd r2, r3, [r3] + 800478e: f7fb fd31 bl 80001f4 <__adddf3> + 8004792: 4632 mov r2, r6 + 8004794: 463b mov r3, r7 + 8004796: f7fb fee3 bl 8000560 <__aeabi_dmul> + 800479a: a383 add r3, pc, #524 ; (adr r3, 80049a8 <__ieee754_acos+0x298>) + 800479c: e9d3 2300 ldrd r2, r3, [r3] + 80047a0: f7fb fd26 bl 80001f0 <__aeabi_dsub> + 80047a4: 4632 mov r2, r6 + 80047a6: 463b mov r3, r7 + 80047a8: f7fb feda bl 8000560 <__aeabi_dmul> + 80047ac: a380 add r3, pc, #512 ; (adr r3, 80049b0 <__ieee754_acos+0x2a0>) + 80047ae: e9d3 2300 ldrd r2, r3, [r3] + 80047b2: f7fb fd1f bl 80001f4 <__adddf3> + 80047b6: 4632 mov r2, r6 + 80047b8: 463b mov r3, r7 + 80047ba: f7fb fed1 bl 8000560 <__aeabi_dmul> + 80047be: a37e add r3, pc, #504 ; (adr r3, 80049b8 <__ieee754_acos+0x2a8>) + 80047c0: e9d3 2300 ldrd r2, r3, [r3] + 80047c4: f7fb fd14 bl 80001f0 <__aeabi_dsub> + 80047c8: 4632 mov r2, r6 + 80047ca: 463b mov r3, r7 + 80047cc: f7fb fec8 bl 8000560 <__aeabi_dmul> + 80047d0: a37b add r3, pc, #492 ; (adr r3, 80049c0 <__ieee754_acos+0x2b0>) + 80047d2: e9d3 2300 ldrd r2, r3, [r3] + 80047d6: f7fb fd0d bl 80001f4 <__adddf3> + 80047da: 4632 mov r2, r6 + 80047dc: 463b mov r3, r7 + 80047de: f7fb febf bl 8000560 <__aeabi_dmul> + 80047e2: a379 add r3, pc, #484 ; (adr r3, 80049c8 <__ieee754_acos+0x2b8>) + 80047e4: e9d3 2300 ldrd r2, r3, [r3] + 80047e8: 4680 mov r8, r0 + 80047ea: 4689 mov r9, r1 + 80047ec: 4630 mov r0, r6 + 80047ee: 4639 mov r1, r7 + 80047f0: f7fb feb6 bl 8000560 <__aeabi_dmul> + 80047f4: a376 add r3, pc, #472 ; (adr r3, 80049d0 <__ieee754_acos+0x2c0>) + 80047f6: e9d3 2300 ldrd r2, r3, [r3] + 80047fa: f7fb fcf9 bl 80001f0 <__aeabi_dsub> + 80047fe: 4632 mov r2, r6 + 8004800: 463b mov r3, r7 + 8004802: f7fb fead bl 8000560 <__aeabi_dmul> + 8004806: a374 add r3, pc, #464 ; (adr r3, 80049d8 <__ieee754_acos+0x2c8>) + 8004808: e9d3 2300 ldrd r2, r3, [r3] + 800480c: f7fb fcf2 bl 80001f4 <__adddf3> + 8004810: 4632 mov r2, r6 + 8004812: 463b mov r3, r7 + 8004814: f7fb fea4 bl 8000560 <__aeabi_dmul> + 8004818: a371 add r3, pc, #452 ; (adr r3, 80049e0 <__ieee754_acos+0x2d0>) + 800481a: e9d3 2300 ldrd r2, r3, [r3] + 800481e: f7fb fce7 bl 80001f0 <__aeabi_dsub> + 8004822: 4632 mov r2, r6 + 8004824: 463b mov r3, r7 + 8004826: f7fb fe9b bl 8000560 <__aeabi_dmul> + 800482a: 2200 movs r2, #0 + 800482c: 4b75 ldr r3, [pc, #468] ; (8004a04 <__ieee754_acos+0x2f4>) + 800482e: f7fb fce1 bl 80001f4 <__adddf3> + 8004832: 4602 mov r2, r0 + 8004834: 460b mov r3, r1 + 8004836: 4640 mov r0, r8 + 8004838: 4649 mov r1, r9 + 800483a: f7fb ffbb bl 80007b4 <__aeabi_ddiv> + 800483e: 4622 mov r2, r4 + 8004840: 462b mov r3, r5 + 8004842: f7fb fe8d bl 8000560 <__aeabi_dmul> + 8004846: 4602 mov r2, r0 + 8004848: 460b mov r3, r1 + 800484a: a167 add r1, pc, #412 ; (adr r1, 80049e8 <__ieee754_acos+0x2d8>) + 800484c: e9d1 0100 ldrd r0, r1, [r1] + 8004850: f7fb fcce bl 80001f0 <__aeabi_dsub> + 8004854: 4602 mov r2, r0 + 8004856: 460b mov r3, r1 + 8004858: 4620 mov r0, r4 + 800485a: 4629 mov r1, r5 + 800485c: f7fb fcc8 bl 80001f0 <__aeabi_dsub> + 8004860: 4602 mov r2, r0 + 8004862: 460b mov r3, r1 + 8004864: a162 add r1, pc, #392 ; (adr r1, 80049f0 <__ieee754_acos+0x2e0>) + 8004866: e9d1 0100 ldrd r0, r1, [r1] + 800486a: f7fb fcc1 bl 80001f0 <__aeabi_dsub> + 800486e: e764 b.n 800473a <__ieee754_acos+0x2a> + 8004870: 2d00 cmp r5, #0 + 8004872: f280 80cb bge.w 8004a0c <__ieee754_acos+0x2fc> + 8004876: ee10 0a10 vmov r0, s0 + 800487a: 2200 movs r2, #0 + 800487c: 4b61 ldr r3, [pc, #388] ; (8004a04 <__ieee754_acos+0x2f4>) + 800487e: 4629 mov r1, r5 + 8004880: f7fb fcb8 bl 80001f4 <__adddf3> + 8004884: 2200 movs r2, #0 + 8004886: 4b60 ldr r3, [pc, #384] ; (8004a08 <__ieee754_acos+0x2f8>) + 8004888: f7fb fe6a bl 8000560 <__aeabi_dmul> + 800488c: a342 add r3, pc, #264 ; (adr r3, 8004998 <__ieee754_acos+0x288>) + 800488e: e9d3 2300 ldrd r2, r3, [r3] + 8004892: 4604 mov r4, r0 + 8004894: 460d mov r5, r1 + 8004896: f7fb fe63 bl 8000560 <__aeabi_dmul> + 800489a: a341 add r3, pc, #260 ; (adr r3, 80049a0 <__ieee754_acos+0x290>) + 800489c: e9d3 2300 ldrd r2, r3, [r3] + 80048a0: f7fb fca8 bl 80001f4 <__adddf3> + 80048a4: 4622 mov r2, r4 + 80048a6: 462b mov r3, r5 + 80048a8: f7fb fe5a bl 8000560 <__aeabi_dmul> + 80048ac: a33e add r3, pc, #248 ; (adr r3, 80049a8 <__ieee754_acos+0x298>) + 80048ae: e9d3 2300 ldrd r2, r3, [r3] + 80048b2: f7fb fc9d bl 80001f0 <__aeabi_dsub> + 80048b6: 4622 mov r2, r4 + 80048b8: 462b mov r3, r5 + 80048ba: f7fb fe51 bl 8000560 <__aeabi_dmul> + 80048be: a33c add r3, pc, #240 ; (adr r3, 80049b0 <__ieee754_acos+0x2a0>) + 80048c0: e9d3 2300 ldrd r2, r3, [r3] + 80048c4: f7fb fc96 bl 80001f4 <__adddf3> + 80048c8: 4622 mov r2, r4 + 80048ca: 462b mov r3, r5 + 80048cc: f7fb fe48 bl 8000560 <__aeabi_dmul> + 80048d0: a339 add r3, pc, #228 ; (adr r3, 80049b8 <__ieee754_acos+0x2a8>) + 80048d2: e9d3 2300 ldrd r2, r3, [r3] + 80048d6: f7fb fc8b bl 80001f0 <__aeabi_dsub> + 80048da: 4622 mov r2, r4 + 80048dc: 462b mov r3, r5 + 80048de: f7fb fe3f bl 8000560 <__aeabi_dmul> + 80048e2: a337 add r3, pc, #220 ; (adr r3, 80049c0 <__ieee754_acos+0x2b0>) + 80048e4: e9d3 2300 ldrd r2, r3, [r3] + 80048e8: f7fb fc84 bl 80001f4 <__adddf3> + 80048ec: 4622 mov r2, r4 + 80048ee: 462b mov r3, r5 + 80048f0: f7fb fe36 bl 8000560 <__aeabi_dmul> + 80048f4: ec45 4b10 vmov d0, r4, r5 + 80048f8: 4680 mov r8, r0 + 80048fa: 4689 mov r9, r1 + 80048fc: f000 fb56 bl 8004fac <__ieee754_sqrt> + 8004900: a331 add r3, pc, #196 ; (adr r3, 80049c8 <__ieee754_acos+0x2b8>) + 8004902: e9d3 2300 ldrd r2, r3, [r3] + 8004906: 4620 mov r0, r4 + 8004908: 4629 mov r1, r5 + 800490a: ec57 6b10 vmov r6, r7, d0 + 800490e: f7fb fe27 bl 8000560 <__aeabi_dmul> + 8004912: a32f add r3, pc, #188 ; (adr r3, 80049d0 <__ieee754_acos+0x2c0>) + 8004914: e9d3 2300 ldrd r2, r3, [r3] + 8004918: f7fb fc6a bl 80001f0 <__aeabi_dsub> + 800491c: 4622 mov r2, r4 + 800491e: 462b mov r3, r5 + 8004920: f7fb fe1e bl 8000560 <__aeabi_dmul> + 8004924: a32c add r3, pc, #176 ; (adr r3, 80049d8 <__ieee754_acos+0x2c8>) + 8004926: e9d3 2300 ldrd r2, r3, [r3] + 800492a: f7fb fc63 bl 80001f4 <__adddf3> + 800492e: 4622 mov r2, r4 + 8004930: 462b mov r3, r5 + 8004932: f7fb fe15 bl 8000560 <__aeabi_dmul> + 8004936: a32a add r3, pc, #168 ; (adr r3, 80049e0 <__ieee754_acos+0x2d0>) + 8004938: e9d3 2300 ldrd r2, r3, [r3] + 800493c: f7fb fc58 bl 80001f0 <__aeabi_dsub> + 8004940: 4622 mov r2, r4 + 8004942: 462b mov r3, r5 + 8004944: f7fb fe0c bl 8000560 <__aeabi_dmul> + 8004948: 2200 movs r2, #0 + 800494a: 4b2e ldr r3, [pc, #184] ; (8004a04 <__ieee754_acos+0x2f4>) + 800494c: f7fb fc52 bl 80001f4 <__adddf3> + 8004950: 4602 mov r2, r0 + 8004952: 460b mov r3, r1 + 8004954: 4640 mov r0, r8 + 8004956: 4649 mov r1, r9 + 8004958: f7fb ff2c bl 80007b4 <__aeabi_ddiv> + 800495c: 4632 mov r2, r6 + 800495e: 463b mov r3, r7 + 8004960: f7fb fdfe bl 8000560 <__aeabi_dmul> + 8004964: a320 add r3, pc, #128 ; (adr r3, 80049e8 <__ieee754_acos+0x2d8>) + 8004966: e9d3 2300 ldrd r2, r3, [r3] + 800496a: f7fb fc41 bl 80001f0 <__aeabi_dsub> + 800496e: 4632 mov r2, r6 + 8004970: 463b mov r3, r7 + 8004972: f7fb fc3f bl 80001f4 <__adddf3> + 8004976: 4602 mov r2, r0 + 8004978: 460b mov r3, r1 + 800497a: f7fb fc3b bl 80001f4 <__adddf3> + 800497e: 4602 mov r2, r0 + 8004980: 460b mov r3, r1 + 8004982: a103 add r1, pc, #12 ; (adr r1, 8004990 <__ieee754_acos+0x280>) + 8004984: e9d1 0100 ldrd r0, r1, [r1] + 8004988: e76f b.n 800486a <__ieee754_acos+0x15a> + 800498a: bf00 nop + 800498c: f3af 8000 nop.w + 8004990: 54442d18 .word 0x54442d18 + 8004994: 400921fb .word 0x400921fb + 8004998: 0dfdf709 .word 0x0dfdf709 + 800499c: 3f023de1 .word 0x3f023de1 + 80049a0: 7501b288 .word 0x7501b288 + 80049a4: 3f49efe0 .word 0x3f49efe0 + 80049a8: b5688f3b .word 0xb5688f3b + 80049ac: 3fa48228 .word 0x3fa48228 + 80049b0: 0e884455 .word 0x0e884455 + 80049b4: 3fc9c155 .word 0x3fc9c155 + 80049b8: 03eb6f7d .word 0x03eb6f7d + 80049bc: 3fd4d612 .word 0x3fd4d612 + 80049c0: 55555555 .word 0x55555555 + 80049c4: 3fc55555 .word 0x3fc55555 + 80049c8: b12e9282 .word 0xb12e9282 + 80049cc: 3fb3b8c5 .word 0x3fb3b8c5 + 80049d0: 1b8d0159 .word 0x1b8d0159 + 80049d4: 3fe6066c .word 0x3fe6066c + 80049d8: 9c598ac8 .word 0x9c598ac8 + 80049dc: 40002ae5 .word 0x40002ae5 + 80049e0: 1c8a2d4b .word 0x1c8a2d4b + 80049e4: 40033a27 .word 0x40033a27 + 80049e8: 33145c07 .word 0x33145c07 + 80049ec: 3c91a626 .word 0x3c91a626 + 80049f0: 54442d18 .word 0x54442d18 + 80049f4: 3ff921fb .word 0x3ff921fb + 80049f8: 3fefffff .word 0x3fefffff + 80049fc: 3fdfffff .word 0x3fdfffff + 8004a00: 3c600000 .word 0x3c600000 + 8004a04: 3ff00000 .word 0x3ff00000 + 8004a08: 3fe00000 .word 0x3fe00000 + 8004a0c: ee10 2a10 vmov r2, s0 + 8004a10: 462b mov r3, r5 + 8004a12: 2000 movs r0, #0 + 8004a14: 496a ldr r1, [pc, #424] ; (8004bc0 <__ieee754_acos+0x4b0>) + 8004a16: f7fb fbeb bl 80001f0 <__aeabi_dsub> + 8004a1a: 2200 movs r2, #0 + 8004a1c: 4b69 ldr r3, [pc, #420] ; (8004bc4 <__ieee754_acos+0x4b4>) + 8004a1e: f7fb fd9f bl 8000560 <__aeabi_dmul> + 8004a22: 4604 mov r4, r0 + 8004a24: 460d mov r5, r1 + 8004a26: ec45 4b10 vmov d0, r4, r5 + 8004a2a: f000 fabf bl 8004fac <__ieee754_sqrt> + 8004a2e: a34e add r3, pc, #312 ; (adr r3, 8004b68 <__ieee754_acos+0x458>) + 8004a30: e9d3 2300 ldrd r2, r3, [r3] + 8004a34: 4620 mov r0, r4 + 8004a36: 4629 mov r1, r5 + 8004a38: ec59 8b10 vmov r8, r9, d0 + 8004a3c: f7fb fd90 bl 8000560 <__aeabi_dmul> + 8004a40: a34b add r3, pc, #300 ; (adr r3, 8004b70 <__ieee754_acos+0x460>) + 8004a42: e9d3 2300 ldrd r2, r3, [r3] + 8004a46: f7fb fbd5 bl 80001f4 <__adddf3> + 8004a4a: 4622 mov r2, r4 + 8004a4c: 462b mov r3, r5 + 8004a4e: f7fb fd87 bl 8000560 <__aeabi_dmul> + 8004a52: a349 add r3, pc, #292 ; (adr r3, 8004b78 <__ieee754_acos+0x468>) + 8004a54: e9d3 2300 ldrd r2, r3, [r3] + 8004a58: f7fb fbca bl 80001f0 <__aeabi_dsub> + 8004a5c: 4622 mov r2, r4 + 8004a5e: 462b mov r3, r5 + 8004a60: f7fb fd7e bl 8000560 <__aeabi_dmul> + 8004a64: a346 add r3, pc, #280 ; (adr r3, 8004b80 <__ieee754_acos+0x470>) + 8004a66: e9d3 2300 ldrd r2, r3, [r3] + 8004a6a: f7fb fbc3 bl 80001f4 <__adddf3> + 8004a6e: 4622 mov r2, r4 + 8004a70: 462b mov r3, r5 + 8004a72: f7fb fd75 bl 8000560 <__aeabi_dmul> + 8004a76: a344 add r3, pc, #272 ; (adr r3, 8004b88 <__ieee754_acos+0x478>) + 8004a78: e9d3 2300 ldrd r2, r3, [r3] + 8004a7c: f7fb fbb8 bl 80001f0 <__aeabi_dsub> + 8004a80: 4622 mov r2, r4 + 8004a82: 462b mov r3, r5 + 8004a84: f7fb fd6c bl 8000560 <__aeabi_dmul> + 8004a88: a341 add r3, pc, #260 ; (adr r3, 8004b90 <__ieee754_acos+0x480>) + 8004a8a: e9d3 2300 ldrd r2, r3, [r3] + 8004a8e: f7fb fbb1 bl 80001f4 <__adddf3> + 8004a92: 4622 mov r2, r4 + 8004a94: 462b mov r3, r5 + 8004a96: f7fb fd63 bl 8000560 <__aeabi_dmul> + 8004a9a: a33f add r3, pc, #252 ; (adr r3, 8004b98 <__ieee754_acos+0x488>) + 8004a9c: e9d3 2300 ldrd r2, r3, [r3] + 8004aa0: 4682 mov sl, r0 + 8004aa2: 468b mov fp, r1 + 8004aa4: 4620 mov r0, r4 + 8004aa6: 4629 mov r1, r5 + 8004aa8: f7fb fd5a bl 8000560 <__aeabi_dmul> + 8004aac: a33c add r3, pc, #240 ; (adr r3, 8004ba0 <__ieee754_acos+0x490>) + 8004aae: e9d3 2300 ldrd r2, r3, [r3] + 8004ab2: f7fb fb9d bl 80001f0 <__aeabi_dsub> + 8004ab6: 4622 mov r2, r4 + 8004ab8: 462b mov r3, r5 + 8004aba: f7fb fd51 bl 8000560 <__aeabi_dmul> + 8004abe: a33a add r3, pc, #232 ; (adr r3, 8004ba8 <__ieee754_acos+0x498>) + 8004ac0: e9d3 2300 ldrd r2, r3, [r3] + 8004ac4: f7fb fb96 bl 80001f4 <__adddf3> + 8004ac8: 4622 mov r2, r4 + 8004aca: 462b mov r3, r5 + 8004acc: f7fb fd48 bl 8000560 <__aeabi_dmul> + 8004ad0: a337 add r3, pc, #220 ; (adr r3, 8004bb0 <__ieee754_acos+0x4a0>) + 8004ad2: e9d3 2300 ldrd r2, r3, [r3] + 8004ad6: f7fb fb8b bl 80001f0 <__aeabi_dsub> + 8004ada: 4622 mov r2, r4 + 8004adc: 462b mov r3, r5 + 8004ade: f7fb fd3f bl 8000560 <__aeabi_dmul> + 8004ae2: 2200 movs r2, #0 + 8004ae4: 4b36 ldr r3, [pc, #216] ; (8004bc0 <__ieee754_acos+0x4b0>) + 8004ae6: f7fb fb85 bl 80001f4 <__adddf3> + 8004aea: 4602 mov r2, r0 + 8004aec: 460b mov r3, r1 + 8004aee: 4650 mov r0, sl + 8004af0: 4659 mov r1, fp + 8004af2: f7fb fe5f bl 80007b4 <__aeabi_ddiv> + 8004af6: 4642 mov r2, r8 + 8004af8: 464b mov r3, r9 + 8004afa: f7fb fd31 bl 8000560 <__aeabi_dmul> + 8004afe: 2600 movs r6, #0 + 8004b00: 4682 mov sl, r0 + 8004b02: 468b mov fp, r1 + 8004b04: 4632 mov r2, r6 + 8004b06: 464b mov r3, r9 + 8004b08: 4630 mov r0, r6 + 8004b0a: 4649 mov r1, r9 + 8004b0c: f7fb fd28 bl 8000560 <__aeabi_dmul> + 8004b10: 4602 mov r2, r0 + 8004b12: 460b mov r3, r1 + 8004b14: 4620 mov r0, r4 + 8004b16: 4629 mov r1, r5 + 8004b18: f7fb fb6a bl 80001f0 <__aeabi_dsub> + 8004b1c: 4632 mov r2, r6 + 8004b1e: 4604 mov r4, r0 + 8004b20: 460d mov r5, r1 + 8004b22: 464b mov r3, r9 + 8004b24: 4640 mov r0, r8 + 8004b26: 4649 mov r1, r9 + 8004b28: f7fb fb64 bl 80001f4 <__adddf3> + 8004b2c: 4602 mov r2, r0 + 8004b2e: 460b mov r3, r1 + 8004b30: 4620 mov r0, r4 + 8004b32: 4629 mov r1, r5 + 8004b34: f7fb fe3e bl 80007b4 <__aeabi_ddiv> + 8004b38: 4602 mov r2, r0 + 8004b3a: 460b mov r3, r1 + 8004b3c: 4650 mov r0, sl + 8004b3e: 4659 mov r1, fp + 8004b40: f7fb fb58 bl 80001f4 <__adddf3> + 8004b44: 4632 mov r2, r6 + 8004b46: 464b mov r3, r9 + 8004b48: f7fb fb54 bl 80001f4 <__adddf3> + 8004b4c: 4602 mov r2, r0 + 8004b4e: 460b mov r3, r1 + 8004b50: f7fb fb50 bl 80001f4 <__adddf3> + 8004b54: e5f1 b.n 800473a <__ieee754_acos+0x2a> + 8004b56: 2000 movs r0, #0 + 8004b58: 2100 movs r1, #0 + 8004b5a: e5ee b.n 800473a <__ieee754_acos+0x2a> + 8004b5c: a116 add r1, pc, #88 ; (adr r1, 8004bb8 <__ieee754_acos+0x4a8>) + 8004b5e: e9d1 0100 ldrd r0, r1, [r1] + 8004b62: e5ea b.n 800473a <__ieee754_acos+0x2a> + 8004b64: f3af 8000 nop.w + 8004b68: 0dfdf709 .word 0x0dfdf709 + 8004b6c: 3f023de1 .word 0x3f023de1 + 8004b70: 7501b288 .word 0x7501b288 + 8004b74: 3f49efe0 .word 0x3f49efe0 + 8004b78: b5688f3b .word 0xb5688f3b + 8004b7c: 3fa48228 .word 0x3fa48228 + 8004b80: 0e884455 .word 0x0e884455 + 8004b84: 3fc9c155 .word 0x3fc9c155 + 8004b88: 03eb6f7d .word 0x03eb6f7d + 8004b8c: 3fd4d612 .word 0x3fd4d612 + 8004b90: 55555555 .word 0x55555555 + 8004b94: 3fc55555 .word 0x3fc55555 + 8004b98: b12e9282 .word 0xb12e9282 + 8004b9c: 3fb3b8c5 .word 0x3fb3b8c5 + 8004ba0: 1b8d0159 .word 0x1b8d0159 + 8004ba4: 3fe6066c .word 0x3fe6066c + 8004ba8: 9c598ac8 .word 0x9c598ac8 + 8004bac: 40002ae5 .word 0x40002ae5 + 8004bb0: 1c8a2d4b .word 0x1c8a2d4b + 8004bb4: 40033a27 .word 0x40033a27 + 8004bb8: 54442d18 .word 0x54442d18 + 8004bbc: 3ff921fb .word 0x3ff921fb + 8004bc0: 3ff00000 .word 0x3ff00000 + 8004bc4: 3fe00000 .word 0x3fe00000 + +08004bc8 <__ieee754_rem_pio2>: + 8004bc8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8004bcc: ec57 6b10 vmov r6, r7, d0 + 8004bd0: 4bc3 ldr r3, [pc, #780] ; (8004ee0 <__ieee754_rem_pio2+0x318>) + 8004bd2: b08d sub sp, #52 ; 0x34 + 8004bd4: f027 4800 bic.w r8, r7, #2147483648 ; 0x80000000 + 8004bd8: 4598 cmp r8, r3 + 8004bda: 4604 mov r4, r0 + 8004bdc: 9704 str r7, [sp, #16] + 8004bde: dc07 bgt.n 8004bf0 <__ieee754_rem_pio2+0x28> + 8004be0: 2200 movs r2, #0 + 8004be2: 2300 movs r3, #0 + 8004be4: ed84 0b00 vstr d0, [r4] + 8004be8: e9c0 2302 strd r2, r3, [r0, #8] + 8004bec: 2500 movs r5, #0 + 8004bee: e027 b.n 8004c40 <__ieee754_rem_pio2+0x78> + 8004bf0: 4bbc ldr r3, [pc, #752] ; (8004ee4 <__ieee754_rem_pio2+0x31c>) + 8004bf2: 4598 cmp r8, r3 + 8004bf4: dc75 bgt.n 8004ce2 <__ieee754_rem_pio2+0x11a> + 8004bf6: 9b04 ldr r3, [sp, #16] + 8004bf8: 4dbb ldr r5, [pc, #748] ; (8004ee8 <__ieee754_rem_pio2+0x320>) + 8004bfa: 2b00 cmp r3, #0 + 8004bfc: ee10 0a10 vmov r0, s0 + 8004c00: a3a9 add r3, pc, #676 ; (adr r3, 8004ea8 <__ieee754_rem_pio2+0x2e0>) + 8004c02: e9d3 2300 ldrd r2, r3, [r3] + 8004c06: 4639 mov r1, r7 + 8004c08: dd36 ble.n 8004c78 <__ieee754_rem_pio2+0xb0> + 8004c0a: f7fb faf1 bl 80001f0 <__aeabi_dsub> + 8004c0e: 45a8 cmp r8, r5 + 8004c10: 4606 mov r6, r0 + 8004c12: 460f mov r7, r1 + 8004c14: d018 beq.n 8004c48 <__ieee754_rem_pio2+0x80> + 8004c16: a3a6 add r3, pc, #664 ; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>) + 8004c18: e9d3 2300 ldrd r2, r3, [r3] + 8004c1c: f7fb fae8 bl 80001f0 <__aeabi_dsub> + 8004c20: 4602 mov r2, r0 + 8004c22: 460b mov r3, r1 + 8004c24: e9c4 2300 strd r2, r3, [r4] + 8004c28: 4630 mov r0, r6 + 8004c2a: 4639 mov r1, r7 + 8004c2c: f7fb fae0 bl 80001f0 <__aeabi_dsub> + 8004c30: a39f add r3, pc, #636 ; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>) + 8004c32: e9d3 2300 ldrd r2, r3, [r3] + 8004c36: f7fb fadb bl 80001f0 <__aeabi_dsub> + 8004c3a: e9c4 0102 strd r0, r1, [r4, #8] + 8004c3e: 2501 movs r5, #1 + 8004c40: 4628 mov r0, r5 + 8004c42: b00d add sp, #52 ; 0x34 + 8004c44: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8004c48: a39b add r3, pc, #620 ; (adr r3, 8004eb8 <__ieee754_rem_pio2+0x2f0>) + 8004c4a: e9d3 2300 ldrd r2, r3, [r3] + 8004c4e: f7fb facf bl 80001f0 <__aeabi_dsub> + 8004c52: a39b add r3, pc, #620 ; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>) + 8004c54: e9d3 2300 ldrd r2, r3, [r3] + 8004c58: 4606 mov r6, r0 + 8004c5a: 460f mov r7, r1 + 8004c5c: f7fb fac8 bl 80001f0 <__aeabi_dsub> + 8004c60: 4602 mov r2, r0 + 8004c62: 460b mov r3, r1 + 8004c64: e9c4 2300 strd r2, r3, [r4] + 8004c68: 4630 mov r0, r6 + 8004c6a: 4639 mov r1, r7 + 8004c6c: f7fb fac0 bl 80001f0 <__aeabi_dsub> + 8004c70: a393 add r3, pc, #588 ; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>) + 8004c72: e9d3 2300 ldrd r2, r3, [r3] + 8004c76: e7de b.n 8004c36 <__ieee754_rem_pio2+0x6e> + 8004c78: f7fb fabc bl 80001f4 <__adddf3> + 8004c7c: 45a8 cmp r8, r5 + 8004c7e: 4606 mov r6, r0 + 8004c80: 460f mov r7, r1 + 8004c82: d016 beq.n 8004cb2 <__ieee754_rem_pio2+0xea> + 8004c84: a38a add r3, pc, #552 ; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>) + 8004c86: e9d3 2300 ldrd r2, r3, [r3] + 8004c8a: f7fb fab3 bl 80001f4 <__adddf3> + 8004c8e: 4602 mov r2, r0 + 8004c90: 460b mov r3, r1 + 8004c92: e9c4 2300 strd r2, r3, [r4] + 8004c96: 4630 mov r0, r6 + 8004c98: 4639 mov r1, r7 + 8004c9a: f7fb faa9 bl 80001f0 <__aeabi_dsub> + 8004c9e: a384 add r3, pc, #528 ; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>) + 8004ca0: e9d3 2300 ldrd r2, r3, [r3] + 8004ca4: f7fb faa6 bl 80001f4 <__adddf3> + 8004ca8: f04f 35ff mov.w r5, #4294967295 + 8004cac: e9c4 0102 strd r0, r1, [r4, #8] + 8004cb0: e7c6 b.n 8004c40 <__ieee754_rem_pio2+0x78> + 8004cb2: a381 add r3, pc, #516 ; (adr r3, 8004eb8 <__ieee754_rem_pio2+0x2f0>) + 8004cb4: e9d3 2300 ldrd r2, r3, [r3] + 8004cb8: f7fb fa9c bl 80001f4 <__adddf3> + 8004cbc: a380 add r3, pc, #512 ; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>) + 8004cbe: e9d3 2300 ldrd r2, r3, [r3] + 8004cc2: 4606 mov r6, r0 + 8004cc4: 460f mov r7, r1 + 8004cc6: f7fb fa95 bl 80001f4 <__adddf3> + 8004cca: 4602 mov r2, r0 + 8004ccc: 460b mov r3, r1 + 8004cce: e9c4 2300 strd r2, r3, [r4] + 8004cd2: 4630 mov r0, r6 + 8004cd4: 4639 mov r1, r7 + 8004cd6: f7fb fa8b bl 80001f0 <__aeabi_dsub> + 8004cda: a379 add r3, pc, #484 ; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>) + 8004cdc: e9d3 2300 ldrd r2, r3, [r3] + 8004ce0: e7e0 b.n 8004ca4 <__ieee754_rem_pio2+0xdc> + 8004ce2: 4b82 ldr r3, [pc, #520] ; (8004eec <__ieee754_rem_pio2+0x324>) + 8004ce4: 4598 cmp r8, r3 + 8004ce6: f300 80d0 bgt.w 8004e8a <__ieee754_rem_pio2+0x2c2> + 8004cea: f001 f8a1 bl 8005e30 + 8004cee: ec57 6b10 vmov r6, r7, d0 + 8004cf2: ee10 0a10 vmov r0, s0 + 8004cf6: a374 add r3, pc, #464 ; (adr r3, 8004ec8 <__ieee754_rem_pio2+0x300>) + 8004cf8: e9d3 2300 ldrd r2, r3, [r3] + 8004cfc: 4639 mov r1, r7 + 8004cfe: f7fb fc2f bl 8000560 <__aeabi_dmul> + 8004d02: 2200 movs r2, #0 + 8004d04: 4b7a ldr r3, [pc, #488] ; (8004ef0 <__ieee754_rem_pio2+0x328>) + 8004d06: f7fb fa75 bl 80001f4 <__adddf3> + 8004d0a: f7fb fed9 bl 8000ac0 <__aeabi_d2iz> + 8004d0e: 4605 mov r5, r0 + 8004d10: f7fb fbbc bl 800048c <__aeabi_i2d> + 8004d14: a364 add r3, pc, #400 ; (adr r3, 8004ea8 <__ieee754_rem_pio2+0x2e0>) + 8004d16: e9d3 2300 ldrd r2, r3, [r3] + 8004d1a: e9cd 0102 strd r0, r1, [sp, #8] + 8004d1e: f7fb fc1f bl 8000560 <__aeabi_dmul> + 8004d22: 4602 mov r2, r0 + 8004d24: 460b mov r3, r1 + 8004d26: 4630 mov r0, r6 + 8004d28: 4639 mov r1, r7 + 8004d2a: f7fb fa61 bl 80001f0 <__aeabi_dsub> + 8004d2e: a360 add r3, pc, #384 ; (adr r3, 8004eb0 <__ieee754_rem_pio2+0x2e8>) + 8004d30: e9d3 2300 ldrd r2, r3, [r3] + 8004d34: 4682 mov sl, r0 + 8004d36: 468b mov fp, r1 + 8004d38: e9dd 0102 ldrd r0, r1, [sp, #8] + 8004d3c: f7fb fc10 bl 8000560 <__aeabi_dmul> + 8004d40: 2d1f cmp r5, #31 + 8004d42: 4606 mov r6, r0 + 8004d44: 460f mov r7, r1 + 8004d46: dc0c bgt.n 8004d62 <__ieee754_rem_pio2+0x19a> + 8004d48: 1e6a subs r2, r5, #1 + 8004d4a: 4b6a ldr r3, [pc, #424] ; (8004ef4 <__ieee754_rem_pio2+0x32c>) + 8004d4c: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8004d50: 4543 cmp r3, r8 + 8004d52: d006 beq.n 8004d62 <__ieee754_rem_pio2+0x19a> + 8004d54: 4632 mov r2, r6 + 8004d56: 463b mov r3, r7 + 8004d58: 4650 mov r0, sl + 8004d5a: 4659 mov r1, fp + 8004d5c: f7fb fa48 bl 80001f0 <__aeabi_dsub> + 8004d60: e00e b.n 8004d80 <__ieee754_rem_pio2+0x1b8> + 8004d62: 4632 mov r2, r6 + 8004d64: 463b mov r3, r7 + 8004d66: 4650 mov r0, sl + 8004d68: 4659 mov r1, fp + 8004d6a: f7fb fa41 bl 80001f0 <__aeabi_dsub> + 8004d6e: ea4f 5328 mov.w r3, r8, asr #20 + 8004d72: 9305 str r3, [sp, #20] + 8004d74: 9a05 ldr r2, [sp, #20] + 8004d76: f3c1 530a ubfx r3, r1, #20, #11 + 8004d7a: 1ad3 subs r3, r2, r3 + 8004d7c: 2b10 cmp r3, #16 + 8004d7e: dc02 bgt.n 8004d86 <__ieee754_rem_pio2+0x1be> + 8004d80: e9c4 0100 strd r0, r1, [r4] + 8004d84: e039 b.n 8004dfa <__ieee754_rem_pio2+0x232> + 8004d86: a34c add r3, pc, #304 ; (adr r3, 8004eb8 <__ieee754_rem_pio2+0x2f0>) + 8004d88: e9d3 2300 ldrd r2, r3, [r3] + 8004d8c: e9dd 0102 ldrd r0, r1, [sp, #8] + 8004d90: f7fb fbe6 bl 8000560 <__aeabi_dmul> + 8004d94: 4606 mov r6, r0 + 8004d96: 460f mov r7, r1 + 8004d98: 4602 mov r2, r0 + 8004d9a: 460b mov r3, r1 + 8004d9c: 4650 mov r0, sl + 8004d9e: 4659 mov r1, fp + 8004da0: f7fb fa26 bl 80001f0 <__aeabi_dsub> + 8004da4: 4602 mov r2, r0 + 8004da6: 460b mov r3, r1 + 8004da8: 4680 mov r8, r0 + 8004daa: 4689 mov r9, r1 + 8004dac: 4650 mov r0, sl + 8004dae: 4659 mov r1, fp + 8004db0: f7fb fa1e bl 80001f0 <__aeabi_dsub> + 8004db4: 4632 mov r2, r6 + 8004db6: 463b mov r3, r7 + 8004db8: f7fb fa1a bl 80001f0 <__aeabi_dsub> + 8004dbc: a340 add r3, pc, #256 ; (adr r3, 8004ec0 <__ieee754_rem_pio2+0x2f8>) + 8004dbe: e9d3 2300 ldrd r2, r3, [r3] + 8004dc2: 4606 mov r6, r0 + 8004dc4: 460f mov r7, r1 + 8004dc6: e9dd 0102 ldrd r0, r1, [sp, #8] + 8004dca: f7fb fbc9 bl 8000560 <__aeabi_dmul> + 8004dce: 4632 mov r2, r6 + 8004dd0: 463b mov r3, r7 + 8004dd2: f7fb fa0d bl 80001f0 <__aeabi_dsub> + 8004dd6: 4602 mov r2, r0 + 8004dd8: 460b mov r3, r1 + 8004dda: 4606 mov r6, r0 + 8004ddc: 460f mov r7, r1 + 8004dde: 4640 mov r0, r8 + 8004de0: 4649 mov r1, r9 + 8004de2: f7fb fa05 bl 80001f0 <__aeabi_dsub> + 8004de6: 9a05 ldr r2, [sp, #20] + 8004de8: f3c1 530a ubfx r3, r1, #20, #11 + 8004dec: 1ad3 subs r3, r2, r3 + 8004dee: 2b31 cmp r3, #49 ; 0x31 + 8004df0: dc20 bgt.n 8004e34 <__ieee754_rem_pio2+0x26c> + 8004df2: e9c4 0100 strd r0, r1, [r4] + 8004df6: 46c2 mov sl, r8 + 8004df8: 46cb mov fp, r9 + 8004dfa: e9d4 8900 ldrd r8, r9, [r4] + 8004dfe: 4650 mov r0, sl + 8004e00: 4642 mov r2, r8 + 8004e02: 464b mov r3, r9 + 8004e04: 4659 mov r1, fp + 8004e06: f7fb f9f3 bl 80001f0 <__aeabi_dsub> + 8004e0a: 463b mov r3, r7 + 8004e0c: 4632 mov r2, r6 + 8004e0e: f7fb f9ef bl 80001f0 <__aeabi_dsub> + 8004e12: 9b04 ldr r3, [sp, #16] + 8004e14: 2b00 cmp r3, #0 + 8004e16: e9c4 0102 strd r0, r1, [r4, #8] + 8004e1a: f6bf af11 bge.w 8004c40 <__ieee754_rem_pio2+0x78> + 8004e1e: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 + 8004e22: 6063 str r3, [r4, #4] + 8004e24: f8c4 8000 str.w r8, [r4] + 8004e28: 60a0 str r0, [r4, #8] + 8004e2a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8004e2e: 60e3 str r3, [r4, #12] + 8004e30: 426d negs r5, r5 + 8004e32: e705 b.n 8004c40 <__ieee754_rem_pio2+0x78> + 8004e34: a326 add r3, pc, #152 ; (adr r3, 8004ed0 <__ieee754_rem_pio2+0x308>) + 8004e36: e9d3 2300 ldrd r2, r3, [r3] + 8004e3a: e9dd 0102 ldrd r0, r1, [sp, #8] + 8004e3e: f7fb fb8f bl 8000560 <__aeabi_dmul> + 8004e42: 4606 mov r6, r0 + 8004e44: 460f mov r7, r1 + 8004e46: 4602 mov r2, r0 + 8004e48: 460b mov r3, r1 + 8004e4a: 4640 mov r0, r8 + 8004e4c: 4649 mov r1, r9 + 8004e4e: f7fb f9cf bl 80001f0 <__aeabi_dsub> + 8004e52: 4602 mov r2, r0 + 8004e54: 460b mov r3, r1 + 8004e56: 4682 mov sl, r0 + 8004e58: 468b mov fp, r1 + 8004e5a: 4640 mov r0, r8 + 8004e5c: 4649 mov r1, r9 + 8004e5e: f7fb f9c7 bl 80001f0 <__aeabi_dsub> + 8004e62: 4632 mov r2, r6 + 8004e64: 463b mov r3, r7 + 8004e66: f7fb f9c3 bl 80001f0 <__aeabi_dsub> + 8004e6a: a31b add r3, pc, #108 ; (adr r3, 8004ed8 <__ieee754_rem_pio2+0x310>) + 8004e6c: e9d3 2300 ldrd r2, r3, [r3] + 8004e70: 4606 mov r6, r0 + 8004e72: 460f mov r7, r1 + 8004e74: e9dd 0102 ldrd r0, r1, [sp, #8] + 8004e78: f7fb fb72 bl 8000560 <__aeabi_dmul> + 8004e7c: 4632 mov r2, r6 + 8004e7e: 463b mov r3, r7 + 8004e80: f7fb f9b6 bl 80001f0 <__aeabi_dsub> + 8004e84: 4606 mov r6, r0 + 8004e86: 460f mov r7, r1 + 8004e88: e764 b.n 8004d54 <__ieee754_rem_pio2+0x18c> + 8004e8a: 4b1b ldr r3, [pc, #108] ; (8004ef8 <__ieee754_rem_pio2+0x330>) + 8004e8c: 4598 cmp r8, r3 + 8004e8e: dd35 ble.n 8004efc <__ieee754_rem_pio2+0x334> + 8004e90: ee10 2a10 vmov r2, s0 + 8004e94: 463b mov r3, r7 + 8004e96: 4630 mov r0, r6 + 8004e98: 4639 mov r1, r7 + 8004e9a: f7fb f9a9 bl 80001f0 <__aeabi_dsub> + 8004e9e: e9c4 0102 strd r0, r1, [r4, #8] + 8004ea2: e9c4 0100 strd r0, r1, [r4] + 8004ea6: e6a1 b.n 8004bec <__ieee754_rem_pio2+0x24> + 8004ea8: 54400000 .word 0x54400000 + 8004eac: 3ff921fb .word 0x3ff921fb + 8004eb0: 1a626331 .word 0x1a626331 + 8004eb4: 3dd0b461 .word 0x3dd0b461 + 8004eb8: 1a600000 .word 0x1a600000 + 8004ebc: 3dd0b461 .word 0x3dd0b461 + 8004ec0: 2e037073 .word 0x2e037073 + 8004ec4: 3ba3198a .word 0x3ba3198a + 8004ec8: 6dc9c883 .word 0x6dc9c883 + 8004ecc: 3fe45f30 .word 0x3fe45f30 + 8004ed0: 2e000000 .word 0x2e000000 + 8004ed4: 3ba3198a .word 0x3ba3198a + 8004ed8: 252049c1 .word 0x252049c1 + 8004edc: 397b839a .word 0x397b839a + 8004ee0: 3fe921fb .word 0x3fe921fb + 8004ee4: 4002d97b .word 0x4002d97b + 8004ee8: 3ff921fb .word 0x3ff921fb + 8004eec: 413921fb .word 0x413921fb + 8004ef0: 3fe00000 .word 0x3fe00000 + 8004ef4: 08006038 .word 0x08006038 + 8004ef8: 7fefffff .word 0x7fefffff + 8004efc: ea4f 5528 mov.w r5, r8, asr #20 + 8004f00: f2a5 4516 subw r5, r5, #1046 ; 0x416 + 8004f04: eba8 5105 sub.w r1, r8, r5, lsl #20 + 8004f08: 4630 mov r0, r6 + 8004f0a: 460f mov r7, r1 + 8004f0c: f7fb fdd8 bl 8000ac0 <__aeabi_d2iz> + 8004f10: f7fb fabc bl 800048c <__aeabi_i2d> + 8004f14: 4602 mov r2, r0 + 8004f16: 460b mov r3, r1 + 8004f18: 4630 mov r0, r6 + 8004f1a: 4639 mov r1, r7 + 8004f1c: e9cd 2306 strd r2, r3, [sp, #24] + 8004f20: f7fb f966 bl 80001f0 <__aeabi_dsub> + 8004f24: 2200 movs r2, #0 + 8004f26: 4b1f ldr r3, [pc, #124] ; (8004fa4 <__ieee754_rem_pio2+0x3dc>) + 8004f28: f7fb fb1a bl 8000560 <__aeabi_dmul> + 8004f2c: 460f mov r7, r1 + 8004f2e: 4606 mov r6, r0 + 8004f30: f7fb fdc6 bl 8000ac0 <__aeabi_d2iz> + 8004f34: f7fb faaa bl 800048c <__aeabi_i2d> + 8004f38: 4602 mov r2, r0 + 8004f3a: 460b mov r3, r1 + 8004f3c: 4630 mov r0, r6 + 8004f3e: 4639 mov r1, r7 + 8004f40: e9cd 2308 strd r2, r3, [sp, #32] + 8004f44: f7fb f954 bl 80001f0 <__aeabi_dsub> + 8004f48: 2200 movs r2, #0 + 8004f4a: 4b16 ldr r3, [pc, #88] ; (8004fa4 <__ieee754_rem_pio2+0x3dc>) + 8004f4c: f7fb fb08 bl 8000560 <__aeabi_dmul> + 8004f50: e9cd 010a strd r0, r1, [sp, #40] ; 0x28 + 8004f54: f10d 0930 add.w r9, sp, #48 ; 0x30 + 8004f58: f04f 0803 mov.w r8, #3 + 8004f5c: 2600 movs r6, #0 + 8004f5e: 2700 movs r7, #0 + 8004f60: 4632 mov r2, r6 + 8004f62: 463b mov r3, r7 + 8004f64: e979 0102 ldrd r0, r1, [r9, #-8]! + 8004f68: f108 3aff add.w sl, r8, #4294967295 + 8004f6c: f7fb fd60 bl 8000a30 <__aeabi_dcmpeq> + 8004f70: b9b0 cbnz r0, 8004fa0 <__ieee754_rem_pio2+0x3d8> + 8004f72: 4b0d ldr r3, [pc, #52] ; (8004fa8 <__ieee754_rem_pio2+0x3e0>) + 8004f74: 9301 str r3, [sp, #4] + 8004f76: 2302 movs r3, #2 + 8004f78: 9300 str r3, [sp, #0] + 8004f7a: 462a mov r2, r5 + 8004f7c: 4643 mov r3, r8 + 8004f7e: 4621 mov r1, r4 + 8004f80: a806 add r0, sp, #24 + 8004f82: f000 f98d bl 80052a0 <__kernel_rem_pio2> + 8004f86: 9b04 ldr r3, [sp, #16] + 8004f88: 2b00 cmp r3, #0 + 8004f8a: 4605 mov r5, r0 + 8004f8c: f6bf ae58 bge.w 8004c40 <__ieee754_rem_pio2+0x78> + 8004f90: 6863 ldr r3, [r4, #4] + 8004f92: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000 + 8004f96: 6063 str r3, [r4, #4] + 8004f98: 68e3 ldr r3, [r4, #12] + 8004f9a: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000 + 8004f9e: e746 b.n 8004e2e <__ieee754_rem_pio2+0x266> + 8004fa0: 46d0 mov r8, sl + 8004fa2: e7dd b.n 8004f60 <__ieee754_rem_pio2+0x398> + 8004fa4: 41700000 .word 0x41700000 + 8004fa8: 080060b8 .word 0x080060b8 + +08004fac <__ieee754_sqrt>: + 8004fac: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 8004fb0: 4955 ldr r1, [pc, #340] ; (8005108 <__ieee754_sqrt+0x15c>) + 8004fb2: ec55 4b10 vmov r4, r5, d0 + 8004fb6: 43a9 bics r1, r5 + 8004fb8: 462b mov r3, r5 + 8004fba: 462a mov r2, r5 + 8004fbc: d112 bne.n 8004fe4 <__ieee754_sqrt+0x38> + 8004fbe: ee10 2a10 vmov r2, s0 + 8004fc2: ee10 0a10 vmov r0, s0 + 8004fc6: 4629 mov r1, r5 + 8004fc8: f7fb faca bl 8000560 <__aeabi_dmul> + 8004fcc: 4602 mov r2, r0 + 8004fce: 460b mov r3, r1 + 8004fd0: 4620 mov r0, r4 + 8004fd2: 4629 mov r1, r5 + 8004fd4: f7fb f90e bl 80001f4 <__adddf3> + 8004fd8: 4604 mov r4, r0 + 8004fda: 460d mov r5, r1 + 8004fdc: ec45 4b10 vmov d0, r4, r5 + 8004fe0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 8004fe4: 2d00 cmp r5, #0 + 8004fe6: ee10 0a10 vmov r0, s0 + 8004fea: 4621 mov r1, r4 + 8004fec: dc0f bgt.n 800500e <__ieee754_sqrt+0x62> + 8004fee: f025 4600 bic.w r6, r5, #2147483648 ; 0x80000000 + 8004ff2: 4330 orrs r0, r6 + 8004ff4: d0f2 beq.n 8004fdc <__ieee754_sqrt+0x30> + 8004ff6: b155 cbz r5, 800500e <__ieee754_sqrt+0x62> + 8004ff8: ee10 2a10 vmov r2, s0 + 8004ffc: 4620 mov r0, r4 + 8004ffe: 4629 mov r1, r5 + 8005000: f7fb f8f6 bl 80001f0 <__aeabi_dsub> + 8005004: 4602 mov r2, r0 + 8005006: 460b mov r3, r1 + 8005008: f7fb fbd4 bl 80007b4 <__aeabi_ddiv> + 800500c: e7e4 b.n 8004fd8 <__ieee754_sqrt+0x2c> + 800500e: 151b asrs r3, r3, #20 + 8005010: d073 beq.n 80050fa <__ieee754_sqrt+0x14e> + 8005012: f2a3 33ff subw r3, r3, #1023 ; 0x3ff + 8005016: 07dd lsls r5, r3, #31 + 8005018: f3c2 0213 ubfx r2, r2, #0, #20 + 800501c: bf48 it mi + 800501e: 0fc8 lsrmi r0, r1, #31 + 8005020: f442 1280 orr.w r2, r2, #1048576 ; 0x100000 + 8005024: bf44 itt mi + 8005026: 0049 lslmi r1, r1, #1 + 8005028: eb00 0242 addmi.w r2, r0, r2, lsl #1 + 800502c: 2500 movs r5, #0 + 800502e: 1058 asrs r0, r3, #1 + 8005030: 0fcb lsrs r3, r1, #31 + 8005032: eb03 0242 add.w r2, r3, r2, lsl #1 + 8005036: 0049 lsls r1, r1, #1 + 8005038: 2316 movs r3, #22 + 800503a: 462c mov r4, r5 + 800503c: f44f 1600 mov.w r6, #2097152 ; 0x200000 + 8005040: 19a7 adds r7, r4, r6 + 8005042: 4297 cmp r7, r2 + 8005044: bfde ittt le + 8005046: 19bc addle r4, r7, r6 + 8005048: 1bd2 suble r2, r2, r7 + 800504a: 19ad addle r5, r5, r6 + 800504c: 0fcf lsrs r7, r1, #31 + 800504e: 3b01 subs r3, #1 + 8005050: eb07 0242 add.w r2, r7, r2, lsl #1 + 8005054: ea4f 0141 mov.w r1, r1, lsl #1 + 8005058: ea4f 0656 mov.w r6, r6, lsr #1 + 800505c: d1f0 bne.n 8005040 <__ieee754_sqrt+0x94> + 800505e: f04f 0c20 mov.w ip, #32 + 8005062: 469e mov lr, r3 + 8005064: f04f 4600 mov.w r6, #2147483648 ; 0x80000000 + 8005068: 42a2 cmp r2, r4 + 800506a: eb06 070e add.w r7, r6, lr + 800506e: dc02 bgt.n 8005076 <__ieee754_sqrt+0xca> + 8005070: d112 bne.n 8005098 <__ieee754_sqrt+0xec> + 8005072: 428f cmp r7, r1 + 8005074: d810 bhi.n 8005098 <__ieee754_sqrt+0xec> + 8005076: 2f00 cmp r7, #0 + 8005078: eb07 0e06 add.w lr, r7, r6 + 800507c: da42 bge.n 8005104 <__ieee754_sqrt+0x158> + 800507e: f1be 0f00 cmp.w lr, #0 + 8005082: db3f blt.n 8005104 <__ieee754_sqrt+0x158> + 8005084: f104 0801 add.w r8, r4, #1 + 8005088: 1b12 subs r2, r2, r4 + 800508a: 428f cmp r7, r1 + 800508c: bf88 it hi + 800508e: f102 32ff addhi.w r2, r2, #4294967295 + 8005092: 1bc9 subs r1, r1, r7 + 8005094: 4433 add r3, r6 + 8005096: 4644 mov r4, r8 + 8005098: 0052 lsls r2, r2, #1 + 800509a: f1bc 0c01 subs.w ip, ip, #1 + 800509e: eb02 72d1 add.w r2, r2, r1, lsr #31 + 80050a2: ea4f 0656 mov.w r6, r6, lsr #1 + 80050a6: ea4f 0141 mov.w r1, r1, lsl #1 + 80050aa: d1dd bne.n 8005068 <__ieee754_sqrt+0xbc> + 80050ac: 430a orrs r2, r1 + 80050ae: d006 beq.n 80050be <__ieee754_sqrt+0x112> + 80050b0: 1c5c adds r4, r3, #1 + 80050b2: bf13 iteet ne + 80050b4: 3301 addne r3, #1 + 80050b6: 3501 addeq r5, #1 + 80050b8: 4663 moveq r3, ip + 80050ba: f023 0301 bicne.w r3, r3, #1 + 80050be: 106a asrs r2, r5, #1 + 80050c0: 085b lsrs r3, r3, #1 + 80050c2: 07e9 lsls r1, r5, #31 + 80050c4: f102 527f add.w r2, r2, #1069547520 ; 0x3fc00000 + 80050c8: f502 1200 add.w r2, r2, #2097152 ; 0x200000 + 80050cc: bf48 it mi + 80050ce: f043 4300 orrmi.w r3, r3, #2147483648 ; 0x80000000 + 80050d2: eb02 5500 add.w r5, r2, r0, lsl #20 + 80050d6: 461c mov r4, r3 + 80050d8: e780 b.n 8004fdc <__ieee754_sqrt+0x30> + 80050da: 0aca lsrs r2, r1, #11 + 80050dc: 3815 subs r0, #21 + 80050de: 0549 lsls r1, r1, #21 + 80050e0: 2a00 cmp r2, #0 + 80050e2: d0fa beq.n 80050da <__ieee754_sqrt+0x12e> + 80050e4: 02d6 lsls r6, r2, #11 + 80050e6: d50a bpl.n 80050fe <__ieee754_sqrt+0x152> + 80050e8: f1c3 0420 rsb r4, r3, #32 + 80050ec: fa21 f404 lsr.w r4, r1, r4 + 80050f0: 1e5d subs r5, r3, #1 + 80050f2: 4099 lsls r1, r3 + 80050f4: 4322 orrs r2, r4 + 80050f6: 1b43 subs r3, r0, r5 + 80050f8: e78b b.n 8005012 <__ieee754_sqrt+0x66> + 80050fa: 4618 mov r0, r3 + 80050fc: e7f0 b.n 80050e0 <__ieee754_sqrt+0x134> + 80050fe: 0052 lsls r2, r2, #1 + 8005100: 3301 adds r3, #1 + 8005102: e7ef b.n 80050e4 <__ieee754_sqrt+0x138> + 8005104: 46a0 mov r8, r4 + 8005106: e7bf b.n 8005088 <__ieee754_sqrt+0xdc> + 8005108: 7ff00000 .word 0x7ff00000 + 800510c: 00000000 .word 0x00000000 + +08005110 <__kernel_cos>: + 8005110: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005114: ec59 8b10 vmov r8, r9, d0 + 8005118: f029 4600 bic.w r6, r9, #2147483648 ; 0x80000000 + 800511c: f1b6 5f79 cmp.w r6, #1044381696 ; 0x3e400000 + 8005120: ed2d 8b02 vpush {d8} + 8005124: eeb0 8a41 vmov.f32 s16, s2 + 8005128: eef0 8a61 vmov.f32 s17, s3 + 800512c: da07 bge.n 800513e <__kernel_cos+0x2e> + 800512e: ee10 0a10 vmov r0, s0 + 8005132: 4649 mov r1, r9 + 8005134: f7fb fcc4 bl 8000ac0 <__aeabi_d2iz> + 8005138: 2800 cmp r0, #0 + 800513a: f000 8089 beq.w 8005250 <__kernel_cos+0x140> + 800513e: 4642 mov r2, r8 + 8005140: 464b mov r3, r9 + 8005142: 4640 mov r0, r8 + 8005144: 4649 mov r1, r9 + 8005146: f7fb fa0b bl 8000560 <__aeabi_dmul> + 800514a: 2200 movs r2, #0 + 800514c: 4b4e ldr r3, [pc, #312] ; (8005288 <__kernel_cos+0x178>) + 800514e: 4604 mov r4, r0 + 8005150: 460d mov r5, r1 + 8005152: f7fb fa05 bl 8000560 <__aeabi_dmul> + 8005156: a340 add r3, pc, #256 ; (adr r3, 8005258 <__kernel_cos+0x148>) + 8005158: e9d3 2300 ldrd r2, r3, [r3] + 800515c: 4682 mov sl, r0 + 800515e: 468b mov fp, r1 + 8005160: 4620 mov r0, r4 + 8005162: 4629 mov r1, r5 + 8005164: f7fb f9fc bl 8000560 <__aeabi_dmul> + 8005168: a33d add r3, pc, #244 ; (adr r3, 8005260 <__kernel_cos+0x150>) + 800516a: e9d3 2300 ldrd r2, r3, [r3] + 800516e: f7fb f841 bl 80001f4 <__adddf3> + 8005172: 4622 mov r2, r4 + 8005174: 462b mov r3, r5 + 8005176: f7fb f9f3 bl 8000560 <__aeabi_dmul> + 800517a: a33b add r3, pc, #236 ; (adr r3, 8005268 <__kernel_cos+0x158>) + 800517c: e9d3 2300 ldrd r2, r3, [r3] + 8005180: f7fb f836 bl 80001f0 <__aeabi_dsub> + 8005184: 4622 mov r2, r4 + 8005186: 462b mov r3, r5 + 8005188: f7fb f9ea bl 8000560 <__aeabi_dmul> + 800518c: a338 add r3, pc, #224 ; (adr r3, 8005270 <__kernel_cos+0x160>) + 800518e: e9d3 2300 ldrd r2, r3, [r3] + 8005192: f7fb f82f bl 80001f4 <__adddf3> + 8005196: 4622 mov r2, r4 + 8005198: 462b mov r3, r5 + 800519a: f7fb f9e1 bl 8000560 <__aeabi_dmul> + 800519e: a336 add r3, pc, #216 ; (adr r3, 8005278 <__kernel_cos+0x168>) + 80051a0: e9d3 2300 ldrd r2, r3, [r3] + 80051a4: f7fb f824 bl 80001f0 <__aeabi_dsub> + 80051a8: 4622 mov r2, r4 + 80051aa: 462b mov r3, r5 + 80051ac: f7fb f9d8 bl 8000560 <__aeabi_dmul> + 80051b0: a333 add r3, pc, #204 ; (adr r3, 8005280 <__kernel_cos+0x170>) + 80051b2: e9d3 2300 ldrd r2, r3, [r3] + 80051b6: f7fb f81d bl 80001f4 <__adddf3> + 80051ba: 4622 mov r2, r4 + 80051bc: 462b mov r3, r5 + 80051be: f7fb f9cf bl 8000560 <__aeabi_dmul> + 80051c2: 4622 mov r2, r4 + 80051c4: 462b mov r3, r5 + 80051c6: f7fb f9cb bl 8000560 <__aeabi_dmul> + 80051ca: ec53 2b18 vmov r2, r3, d8 + 80051ce: 4604 mov r4, r0 + 80051d0: 460d mov r5, r1 + 80051d2: 4640 mov r0, r8 + 80051d4: 4649 mov r1, r9 + 80051d6: f7fb f9c3 bl 8000560 <__aeabi_dmul> + 80051da: 460b mov r3, r1 + 80051dc: 4602 mov r2, r0 + 80051de: 4629 mov r1, r5 + 80051e0: 4620 mov r0, r4 + 80051e2: f7fb f805 bl 80001f0 <__aeabi_dsub> + 80051e6: 4b29 ldr r3, [pc, #164] ; (800528c <__kernel_cos+0x17c>) + 80051e8: 429e cmp r6, r3 + 80051ea: 4680 mov r8, r0 + 80051ec: 4689 mov r9, r1 + 80051ee: dc11 bgt.n 8005214 <__kernel_cos+0x104> + 80051f0: 4602 mov r2, r0 + 80051f2: 460b mov r3, r1 + 80051f4: 4650 mov r0, sl + 80051f6: 4659 mov r1, fp + 80051f8: f7fa fffa bl 80001f0 <__aeabi_dsub> + 80051fc: 460b mov r3, r1 + 80051fe: 4924 ldr r1, [pc, #144] ; (8005290 <__kernel_cos+0x180>) + 8005200: 4602 mov r2, r0 + 8005202: 2000 movs r0, #0 + 8005204: f7fa fff4 bl 80001f0 <__aeabi_dsub> + 8005208: ecbd 8b02 vpop {d8} + 800520c: ec41 0b10 vmov d0, r0, r1 + 8005210: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8005214: 4b1f ldr r3, [pc, #124] ; (8005294 <__kernel_cos+0x184>) + 8005216: 491e ldr r1, [pc, #120] ; (8005290 <__kernel_cos+0x180>) + 8005218: 429e cmp r6, r3 + 800521a: bfcc ite gt + 800521c: 4d1e ldrgt r5, [pc, #120] ; (8005298 <__kernel_cos+0x188>) + 800521e: f5a6 1500 suble.w r5, r6, #2097152 ; 0x200000 + 8005222: 2400 movs r4, #0 + 8005224: 4622 mov r2, r4 + 8005226: 462b mov r3, r5 + 8005228: 2000 movs r0, #0 + 800522a: f7fa ffe1 bl 80001f0 <__aeabi_dsub> + 800522e: 4622 mov r2, r4 + 8005230: 4606 mov r6, r0 + 8005232: 460f mov r7, r1 + 8005234: 462b mov r3, r5 + 8005236: 4650 mov r0, sl + 8005238: 4659 mov r1, fp + 800523a: f7fa ffd9 bl 80001f0 <__aeabi_dsub> + 800523e: 4642 mov r2, r8 + 8005240: 464b mov r3, r9 + 8005242: f7fa ffd5 bl 80001f0 <__aeabi_dsub> + 8005246: 4602 mov r2, r0 + 8005248: 460b mov r3, r1 + 800524a: 4630 mov r0, r6 + 800524c: 4639 mov r1, r7 + 800524e: e7d9 b.n 8005204 <__kernel_cos+0xf4> + 8005250: 2000 movs r0, #0 + 8005252: 490f ldr r1, [pc, #60] ; (8005290 <__kernel_cos+0x180>) + 8005254: e7d8 b.n 8005208 <__kernel_cos+0xf8> + 8005256: bf00 nop + 8005258: be8838d4 .word 0xbe8838d4 + 800525c: bda8fae9 .word 0xbda8fae9 + 8005260: bdb4b1c4 .word 0xbdb4b1c4 + 8005264: 3e21ee9e .word 0x3e21ee9e + 8005268: 809c52ad .word 0x809c52ad + 800526c: 3e927e4f .word 0x3e927e4f + 8005270: 19cb1590 .word 0x19cb1590 + 8005274: 3efa01a0 .word 0x3efa01a0 + 8005278: 16c15177 .word 0x16c15177 + 800527c: 3f56c16c .word 0x3f56c16c + 8005280: 5555554c .word 0x5555554c + 8005284: 3fa55555 .word 0x3fa55555 + 8005288: 3fe00000 .word 0x3fe00000 + 800528c: 3fd33332 .word 0x3fd33332 + 8005290: 3ff00000 .word 0x3ff00000 + 8005294: 3fe90000 .word 0x3fe90000 + 8005298: 3fd20000 .word 0x3fd20000 + 800529c: 00000000 .word 0x00000000 + +080052a0 <__kernel_rem_pio2>: + 80052a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80052a4: ed2d 8b02 vpush {d8} + 80052a8: f5ad 7d1b sub.w sp, sp, #620 ; 0x26c + 80052ac: 1ed4 subs r4, r2, #3 + 80052ae: 9308 str r3, [sp, #32] + 80052b0: 9101 str r1, [sp, #4] + 80052b2: 4bc5 ldr r3, [pc, #788] ; (80055c8 <__kernel_rem_pio2+0x328>) + 80052b4: 99a6 ldr r1, [sp, #664] ; 0x298 + 80052b6: 9009 str r0, [sp, #36] ; 0x24 + 80052b8: f853 3021 ldr.w r3, [r3, r1, lsl #2] + 80052bc: 9304 str r3, [sp, #16] + 80052be: 9b08 ldr r3, [sp, #32] + 80052c0: 3b01 subs r3, #1 + 80052c2: 9307 str r3, [sp, #28] + 80052c4: 2318 movs r3, #24 + 80052c6: fb94 f4f3 sdiv r4, r4, r3 + 80052ca: f06f 0317 mvn.w r3, #23 + 80052ce: ea24 74e4 bic.w r4, r4, r4, asr #31 + 80052d2: fb04 3303 mla r3, r4, r3, r3 + 80052d6: eb03 0a02 add.w sl, r3, r2 + 80052da: 9b04 ldr r3, [sp, #16] + 80052dc: 9a07 ldr r2, [sp, #28] + 80052de: ed9f 8bb6 vldr d8, [pc, #728] ; 80055b8 <__kernel_rem_pio2+0x318> + 80052e2: eb03 0802 add.w r8, r3, r2 + 80052e6: 9ba7 ldr r3, [sp, #668] ; 0x29c + 80052e8: 1aa7 subs r7, r4, r2 + 80052ea: eb03 0987 add.w r9, r3, r7, lsl #2 + 80052ee: ae22 add r6, sp, #136 ; 0x88 + 80052f0: 2500 movs r5, #0 + 80052f2: 4545 cmp r5, r8 + 80052f4: dd13 ble.n 800531e <__kernel_rem_pio2+0x7e> + 80052f6: ed9f 8bb0 vldr d8, [pc, #704] ; 80055b8 <__kernel_rem_pio2+0x318> + 80052fa: f50d 7be4 add.w fp, sp, #456 ; 0x1c8 + 80052fe: 2600 movs r6, #0 + 8005300: 9b04 ldr r3, [sp, #16] + 8005302: 429e cmp r6, r3 + 8005304: dc32 bgt.n 800536c <__kernel_rem_pio2+0xcc> + 8005306: 9b09 ldr r3, [sp, #36] ; 0x24 + 8005308: 9302 str r3, [sp, #8] + 800530a: 9b08 ldr r3, [sp, #32] + 800530c: 199d adds r5, r3, r6 + 800530e: ab22 add r3, sp, #136 ; 0x88 + 8005310: eb03 03c5 add.w r3, r3, r5, lsl #3 + 8005314: 9306 str r3, [sp, #24] + 8005316: ec59 8b18 vmov r8, r9, d8 + 800531a: 2700 movs r7, #0 + 800531c: e01f b.n 800535e <__kernel_rem_pio2+0xbe> + 800531e: 42ef cmn r7, r5 + 8005320: d407 bmi.n 8005332 <__kernel_rem_pio2+0x92> + 8005322: f859 0025 ldr.w r0, [r9, r5, lsl #2] + 8005326: f7fb f8b1 bl 800048c <__aeabi_i2d> + 800532a: e8e6 0102 strd r0, r1, [r6], #8 + 800532e: 3501 adds r5, #1 + 8005330: e7df b.n 80052f2 <__kernel_rem_pio2+0x52> + 8005332: ec51 0b18 vmov r0, r1, d8 + 8005336: e7f8 b.n 800532a <__kernel_rem_pio2+0x8a> + 8005338: 9906 ldr r1, [sp, #24] + 800533a: 9d02 ldr r5, [sp, #8] + 800533c: e971 2302 ldrd r2, r3, [r1, #-8]! + 8005340: 9106 str r1, [sp, #24] + 8005342: e8f5 0102 ldrd r0, r1, [r5], #8 + 8005346: 9502 str r5, [sp, #8] + 8005348: f7fb f90a bl 8000560 <__aeabi_dmul> + 800534c: 4602 mov r2, r0 + 800534e: 460b mov r3, r1 + 8005350: 4640 mov r0, r8 + 8005352: 4649 mov r1, r9 + 8005354: f7fa ff4e bl 80001f4 <__adddf3> + 8005358: 3701 adds r7, #1 + 800535a: 4680 mov r8, r0 + 800535c: 4689 mov r9, r1 + 800535e: 9b07 ldr r3, [sp, #28] + 8005360: 429f cmp r7, r3 + 8005362: dde9 ble.n 8005338 <__kernel_rem_pio2+0x98> + 8005364: e8eb 8902 strd r8, r9, [fp], #8 + 8005368: 3601 adds r6, #1 + 800536a: e7c9 b.n 8005300 <__kernel_rem_pio2+0x60> + 800536c: 9b04 ldr r3, [sp, #16] + 800536e: aa0e add r2, sp, #56 ; 0x38 + 8005370: eb02 0383 add.w r3, r2, r3, lsl #2 + 8005374: 930c str r3, [sp, #48] ; 0x30 + 8005376: 9ba7 ldr r3, [sp, #668] ; 0x29c + 8005378: eb03 0384 add.w r3, r3, r4, lsl #2 + 800537c: 9c04 ldr r4, [sp, #16] + 800537e: 930b str r3, [sp, #44] ; 0x2c + 8005380: ab9a add r3, sp, #616 ; 0x268 + 8005382: f104 5b00 add.w fp, r4, #536870912 ; 0x20000000 + 8005386: eb03 03c4 add.w r3, r3, r4, lsl #3 + 800538a: f10b 3bff add.w fp, fp, #4294967295 + 800538e: e953 8928 ldrd r8, r9, [r3, #-160] ; 0xa0 + 8005392: ea4f 0bcb mov.w fp, fp, lsl #3 + 8005396: ab9a add r3, sp, #616 ; 0x268 + 8005398: 445b add r3, fp + 800539a: f1a3 0698 sub.w r6, r3, #152 ; 0x98 + 800539e: 2500 movs r5, #0 + 80053a0: 1b63 subs r3, r4, r5 + 80053a2: 2b00 cmp r3, #0 + 80053a4: dc78 bgt.n 8005498 <__kernel_rem_pio2+0x1f8> + 80053a6: 4650 mov r0, sl + 80053a8: ec49 8b10 vmov d0, r8, r9 + 80053ac: f000 fd54 bl 8005e58 + 80053b0: ec57 6b10 vmov r6, r7, d0 + 80053b4: 2200 movs r2, #0 + 80053b6: f04f 537f mov.w r3, #1069547520 ; 0x3fc00000 + 80053ba: ee10 0a10 vmov r0, s0 + 80053be: 4639 mov r1, r7 + 80053c0: f7fb f8ce bl 8000560 <__aeabi_dmul> + 80053c4: ec41 0b10 vmov d0, r0, r1 + 80053c8: f7ff f84e bl 8004468 + 80053cc: 2200 movs r2, #0 + 80053ce: ec51 0b10 vmov r0, r1, d0 + 80053d2: 4b7e ldr r3, [pc, #504] ; (80055cc <__kernel_rem_pio2+0x32c>) + 80053d4: f7fb f8c4 bl 8000560 <__aeabi_dmul> + 80053d8: 4602 mov r2, r0 + 80053da: 460b mov r3, r1 + 80053dc: 4630 mov r0, r6 + 80053de: 4639 mov r1, r7 + 80053e0: f7fa ff06 bl 80001f0 <__aeabi_dsub> + 80053e4: 460f mov r7, r1 + 80053e6: 4606 mov r6, r0 + 80053e8: f7fb fb6a bl 8000ac0 <__aeabi_d2iz> + 80053ec: 9006 str r0, [sp, #24] + 80053ee: f7fb f84d bl 800048c <__aeabi_i2d> + 80053f2: 4602 mov r2, r0 + 80053f4: 460b mov r3, r1 + 80053f6: 4630 mov r0, r6 + 80053f8: 4639 mov r1, r7 + 80053fa: f7fa fef9 bl 80001f0 <__aeabi_dsub> + 80053fe: f1ba 0f00 cmp.w sl, #0 + 8005402: 4606 mov r6, r0 + 8005404: 460f mov r7, r1 + 8005406: dd6c ble.n 80054e2 <__kernel_rem_pio2+0x242> + 8005408: 1e62 subs r2, r4, #1 + 800540a: ab0e add r3, sp, #56 ; 0x38 + 800540c: f1ca 0118 rsb r1, sl, #24 + 8005410: f853 0022 ldr.w r0, [r3, r2, lsl #2] + 8005414: 9d06 ldr r5, [sp, #24] + 8005416: fa40 f301 asr.w r3, r0, r1 + 800541a: 441d add r5, r3 + 800541c: 408b lsls r3, r1 + 800541e: 1ac0 subs r0, r0, r3 + 8005420: ab0e add r3, sp, #56 ; 0x38 + 8005422: 9506 str r5, [sp, #24] + 8005424: f843 0022 str.w r0, [r3, r2, lsl #2] + 8005428: f1ca 0317 rsb r3, sl, #23 + 800542c: fa40 f303 asr.w r3, r0, r3 + 8005430: 9302 str r3, [sp, #8] + 8005432: 9b02 ldr r3, [sp, #8] + 8005434: 2b00 cmp r3, #0 + 8005436: dd62 ble.n 80054fe <__kernel_rem_pio2+0x25e> + 8005438: 9b06 ldr r3, [sp, #24] + 800543a: 2200 movs r2, #0 + 800543c: 3301 adds r3, #1 + 800543e: 9306 str r3, [sp, #24] + 8005440: 4615 mov r5, r2 + 8005442: f06f 417f mvn.w r1, #4278190080 ; 0xff000000 + 8005446: 4294 cmp r4, r2 + 8005448: f300 8095 bgt.w 8005576 <__kernel_rem_pio2+0x2d6> + 800544c: f1ba 0f00 cmp.w sl, #0 + 8005450: dd07 ble.n 8005462 <__kernel_rem_pio2+0x1c2> + 8005452: f1ba 0f01 cmp.w sl, #1 + 8005456: f000 80a2 beq.w 800559e <__kernel_rem_pio2+0x2fe> + 800545a: f1ba 0f02 cmp.w sl, #2 + 800545e: f000 80c1 beq.w 80055e4 <__kernel_rem_pio2+0x344> + 8005462: 9b02 ldr r3, [sp, #8] + 8005464: 2b02 cmp r3, #2 + 8005466: d14a bne.n 80054fe <__kernel_rem_pio2+0x25e> + 8005468: 4632 mov r2, r6 + 800546a: 463b mov r3, r7 + 800546c: 2000 movs r0, #0 + 800546e: 4958 ldr r1, [pc, #352] ; (80055d0 <__kernel_rem_pio2+0x330>) + 8005470: f7fa febe bl 80001f0 <__aeabi_dsub> + 8005474: 4606 mov r6, r0 + 8005476: 460f mov r7, r1 + 8005478: 2d00 cmp r5, #0 + 800547a: d040 beq.n 80054fe <__kernel_rem_pio2+0x25e> + 800547c: 4650 mov r0, sl + 800547e: ed9f 0b50 vldr d0, [pc, #320] ; 80055c0 <__kernel_rem_pio2+0x320> + 8005482: f000 fce9 bl 8005e58 + 8005486: 4630 mov r0, r6 + 8005488: 4639 mov r1, r7 + 800548a: ec53 2b10 vmov r2, r3, d0 + 800548e: f7fa feaf bl 80001f0 <__aeabi_dsub> + 8005492: 4606 mov r6, r0 + 8005494: 460f mov r7, r1 + 8005496: e032 b.n 80054fe <__kernel_rem_pio2+0x25e> + 8005498: 2200 movs r2, #0 + 800549a: 4b4e ldr r3, [pc, #312] ; (80055d4 <__kernel_rem_pio2+0x334>) + 800549c: 4640 mov r0, r8 + 800549e: 4649 mov r1, r9 + 80054a0: f7fb f85e bl 8000560 <__aeabi_dmul> + 80054a4: f7fb fb0c bl 8000ac0 <__aeabi_d2iz> + 80054a8: f7fa fff0 bl 800048c <__aeabi_i2d> + 80054ac: 2200 movs r2, #0 + 80054ae: 4b4a ldr r3, [pc, #296] ; (80055d8 <__kernel_rem_pio2+0x338>) + 80054b0: e9cd 0102 strd r0, r1, [sp, #8] + 80054b4: f7fb f854 bl 8000560 <__aeabi_dmul> + 80054b8: 4602 mov r2, r0 + 80054ba: 460b mov r3, r1 + 80054bc: 4640 mov r0, r8 + 80054be: 4649 mov r1, r9 + 80054c0: f7fa fe96 bl 80001f0 <__aeabi_dsub> + 80054c4: f7fb fafc bl 8000ac0 <__aeabi_d2iz> + 80054c8: ab0e add r3, sp, #56 ; 0x38 + 80054ca: f843 0025 str.w r0, [r3, r5, lsl #2] + 80054ce: e976 2302 ldrd r2, r3, [r6, #-8]! + 80054d2: e9dd 0102 ldrd r0, r1, [sp, #8] + 80054d6: f7fa fe8d bl 80001f4 <__adddf3> + 80054da: 3501 adds r5, #1 + 80054dc: 4680 mov r8, r0 + 80054de: 4689 mov r9, r1 + 80054e0: e75e b.n 80053a0 <__kernel_rem_pio2+0x100> + 80054e2: d105 bne.n 80054f0 <__kernel_rem_pio2+0x250> + 80054e4: 1e63 subs r3, r4, #1 + 80054e6: aa0e add r2, sp, #56 ; 0x38 + 80054e8: f852 0023 ldr.w r0, [r2, r3, lsl #2] + 80054ec: 15c3 asrs r3, r0, #23 + 80054ee: e79f b.n 8005430 <__kernel_rem_pio2+0x190> + 80054f0: 2200 movs r2, #0 + 80054f2: 4b3a ldr r3, [pc, #232] ; (80055dc <__kernel_rem_pio2+0x33c>) + 80054f4: f7fb faba bl 8000a6c <__aeabi_dcmpge> + 80054f8: 2800 cmp r0, #0 + 80054fa: d139 bne.n 8005570 <__kernel_rem_pio2+0x2d0> + 80054fc: 9002 str r0, [sp, #8] + 80054fe: 2200 movs r2, #0 + 8005500: 2300 movs r3, #0 + 8005502: 4630 mov r0, r6 + 8005504: 4639 mov r1, r7 + 8005506: f7fb fa93 bl 8000a30 <__aeabi_dcmpeq> + 800550a: 2800 cmp r0, #0 + 800550c: f000 80c7 beq.w 800569e <__kernel_rem_pio2+0x3fe> + 8005510: 1e65 subs r5, r4, #1 + 8005512: 462b mov r3, r5 + 8005514: 2200 movs r2, #0 + 8005516: 9904 ldr r1, [sp, #16] + 8005518: 428b cmp r3, r1 + 800551a: da6a bge.n 80055f2 <__kernel_rem_pio2+0x352> + 800551c: 2a00 cmp r2, #0 + 800551e: f000 8088 beq.w 8005632 <__kernel_rem_pio2+0x392> + 8005522: ab0e add r3, sp, #56 ; 0x38 + 8005524: f1aa 0a18 sub.w sl, sl, #24 + 8005528: f853 3025 ldr.w r3, [r3, r5, lsl #2] + 800552c: 2b00 cmp r3, #0 + 800552e: f000 80b4 beq.w 800569a <__kernel_rem_pio2+0x3fa> + 8005532: 4650 mov r0, sl + 8005534: ed9f 0b22 vldr d0, [pc, #136] ; 80055c0 <__kernel_rem_pio2+0x320> + 8005538: f000 fc8e bl 8005e58 + 800553c: 00ec lsls r4, r5, #3 + 800553e: ab72 add r3, sp, #456 ; 0x1c8 + 8005540: 191e adds r6, r3, r4 + 8005542: ec59 8b10 vmov r8, r9, d0 + 8005546: f106 0a08 add.w sl, r6, #8 + 800554a: 462f mov r7, r5 + 800554c: 2f00 cmp r7, #0 + 800554e: f280 80df bge.w 8005710 <__kernel_rem_pio2+0x470> + 8005552: ed9f 8b19 vldr d8, [pc, #100] ; 80055b8 <__kernel_rem_pio2+0x318> + 8005556: f04f 0a00 mov.w sl, #0 + 800555a: eba5 030a sub.w r3, r5, sl + 800555e: 2b00 cmp r3, #0 + 8005560: f2c0 810a blt.w 8005778 <__kernel_rem_pio2+0x4d8> + 8005564: f8df b078 ldr.w fp, [pc, #120] ; 80055e0 <__kernel_rem_pio2+0x340> + 8005568: ec59 8b18 vmov r8, r9, d8 + 800556c: 2700 movs r7, #0 + 800556e: e0f5 b.n 800575c <__kernel_rem_pio2+0x4bc> + 8005570: 2302 movs r3, #2 + 8005572: 9302 str r3, [sp, #8] + 8005574: e760 b.n 8005438 <__kernel_rem_pio2+0x198> + 8005576: ab0e add r3, sp, #56 ; 0x38 + 8005578: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 800557c: b94d cbnz r5, 8005592 <__kernel_rem_pio2+0x2f2> + 800557e: b12b cbz r3, 800558c <__kernel_rem_pio2+0x2ec> + 8005580: a80e add r0, sp, #56 ; 0x38 + 8005582: f1c3 7380 rsb r3, r3, #16777216 ; 0x1000000 + 8005586: f840 3022 str.w r3, [r0, r2, lsl #2] + 800558a: 2301 movs r3, #1 + 800558c: 3201 adds r2, #1 + 800558e: 461d mov r5, r3 + 8005590: e759 b.n 8005446 <__kernel_rem_pio2+0x1a6> + 8005592: a80e add r0, sp, #56 ; 0x38 + 8005594: 1acb subs r3, r1, r3 + 8005596: f840 3022 str.w r3, [r0, r2, lsl #2] + 800559a: 462b mov r3, r5 + 800559c: e7f6 b.n 800558c <__kernel_rem_pio2+0x2ec> + 800559e: 1e62 subs r2, r4, #1 + 80055a0: ab0e add r3, sp, #56 ; 0x38 + 80055a2: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80055a6: f3c3 0316 ubfx r3, r3, #0, #23 + 80055aa: a90e add r1, sp, #56 ; 0x38 + 80055ac: f841 3022 str.w r3, [r1, r2, lsl #2] + 80055b0: e757 b.n 8005462 <__kernel_rem_pio2+0x1c2> + 80055b2: bf00 nop + 80055b4: f3af 8000 nop.w + ... + 80055c4: 3ff00000 .word 0x3ff00000 + 80055c8: 08006200 .word 0x08006200 + 80055cc: 40200000 .word 0x40200000 + 80055d0: 3ff00000 .word 0x3ff00000 + 80055d4: 3e700000 .word 0x3e700000 + 80055d8: 41700000 .word 0x41700000 + 80055dc: 3fe00000 .word 0x3fe00000 + 80055e0: 080061c0 .word 0x080061c0 + 80055e4: 1e62 subs r2, r4, #1 + 80055e6: ab0e add r3, sp, #56 ; 0x38 + 80055e8: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 80055ec: f3c3 0315 ubfx r3, r3, #0, #22 + 80055f0: e7db b.n 80055aa <__kernel_rem_pio2+0x30a> + 80055f2: a90e add r1, sp, #56 ; 0x38 + 80055f4: f851 1023 ldr.w r1, [r1, r3, lsl #2] + 80055f8: 3b01 subs r3, #1 + 80055fa: 430a orrs r2, r1 + 80055fc: e78b b.n 8005516 <__kernel_rem_pio2+0x276> + 80055fe: 3301 adds r3, #1 + 8005600: f852 1d04 ldr.w r1, [r2, #-4]! + 8005604: 2900 cmp r1, #0 + 8005606: d0fa beq.n 80055fe <__kernel_rem_pio2+0x35e> + 8005608: 9a08 ldr r2, [sp, #32] + 800560a: 4422 add r2, r4 + 800560c: 00d2 lsls r2, r2, #3 + 800560e: a922 add r1, sp, #136 ; 0x88 + 8005610: 18e3 adds r3, r4, r3 + 8005612: 9206 str r2, [sp, #24] + 8005614: 440a add r2, r1 + 8005616: 9302 str r3, [sp, #8] + 8005618: f10b 0108 add.w r1, fp, #8 + 800561c: f102 0308 add.w r3, r2, #8 + 8005620: 1c66 adds r6, r4, #1 + 8005622: 910a str r1, [sp, #40] ; 0x28 + 8005624: 2500 movs r5, #0 + 8005626: 930d str r3, [sp, #52] ; 0x34 + 8005628: 9b02 ldr r3, [sp, #8] + 800562a: 42b3 cmp r3, r6 + 800562c: da04 bge.n 8005638 <__kernel_rem_pio2+0x398> + 800562e: 461c mov r4, r3 + 8005630: e6a6 b.n 8005380 <__kernel_rem_pio2+0xe0> + 8005632: 9a0c ldr r2, [sp, #48] ; 0x30 + 8005634: 2301 movs r3, #1 + 8005636: e7e3 b.n 8005600 <__kernel_rem_pio2+0x360> + 8005638: 9b06 ldr r3, [sp, #24] + 800563a: 18ef adds r7, r5, r3 + 800563c: ab22 add r3, sp, #136 ; 0x88 + 800563e: 441f add r7, r3 + 8005640: 9b0b ldr r3, [sp, #44] ; 0x2c + 8005642: f853 0026 ldr.w r0, [r3, r6, lsl #2] + 8005646: f7fa ff21 bl 800048c <__aeabi_i2d> + 800564a: 9b09 ldr r3, [sp, #36] ; 0x24 + 800564c: 461c mov r4, r3 + 800564e: 9b0d ldr r3, [sp, #52] ; 0x34 + 8005650: e9c7 0100 strd r0, r1, [r7] + 8005654: eb03 0b05 add.w fp, r3, r5 + 8005658: 2700 movs r7, #0 + 800565a: f04f 0800 mov.w r8, #0 + 800565e: f04f 0900 mov.w r9, #0 + 8005662: 9b07 ldr r3, [sp, #28] + 8005664: 429f cmp r7, r3 + 8005666: dd08 ble.n 800567a <__kernel_rem_pio2+0x3da> + 8005668: 9b0a ldr r3, [sp, #40] ; 0x28 + 800566a: aa72 add r2, sp, #456 ; 0x1c8 + 800566c: 18eb adds r3, r5, r3 + 800566e: 4413 add r3, r2 + 8005670: e9c3 8902 strd r8, r9, [r3, #8] + 8005674: 3601 adds r6, #1 + 8005676: 3508 adds r5, #8 + 8005678: e7d6 b.n 8005628 <__kernel_rem_pio2+0x388> + 800567a: e97b 2302 ldrd r2, r3, [fp, #-8]! + 800567e: e8f4 0102 ldrd r0, r1, [r4], #8 + 8005682: f7fa ff6d bl 8000560 <__aeabi_dmul> + 8005686: 4602 mov r2, r0 + 8005688: 460b mov r3, r1 + 800568a: 4640 mov r0, r8 + 800568c: 4649 mov r1, r9 + 800568e: f7fa fdb1 bl 80001f4 <__adddf3> + 8005692: 3701 adds r7, #1 + 8005694: 4680 mov r8, r0 + 8005696: 4689 mov r9, r1 + 8005698: e7e3 b.n 8005662 <__kernel_rem_pio2+0x3c2> + 800569a: 3d01 subs r5, #1 + 800569c: e741 b.n 8005522 <__kernel_rem_pio2+0x282> + 800569e: f1ca 0000 rsb r0, sl, #0 + 80056a2: ec47 6b10 vmov d0, r6, r7 + 80056a6: f000 fbd7 bl 8005e58 + 80056aa: ec57 6b10 vmov r6, r7, d0 + 80056ae: 2200 movs r2, #0 + 80056b0: 4b99 ldr r3, [pc, #612] ; (8005918 <__kernel_rem_pio2+0x678>) + 80056b2: ee10 0a10 vmov r0, s0 + 80056b6: 4639 mov r1, r7 + 80056b8: f7fb f9d8 bl 8000a6c <__aeabi_dcmpge> + 80056bc: b1f8 cbz r0, 80056fe <__kernel_rem_pio2+0x45e> + 80056be: 2200 movs r2, #0 + 80056c0: 4b96 ldr r3, [pc, #600] ; (800591c <__kernel_rem_pio2+0x67c>) + 80056c2: 4630 mov r0, r6 + 80056c4: 4639 mov r1, r7 + 80056c6: f7fa ff4b bl 8000560 <__aeabi_dmul> + 80056ca: f7fb f9f9 bl 8000ac0 <__aeabi_d2iz> + 80056ce: 4680 mov r8, r0 + 80056d0: f7fa fedc bl 800048c <__aeabi_i2d> + 80056d4: 2200 movs r2, #0 + 80056d6: 4b90 ldr r3, [pc, #576] ; (8005918 <__kernel_rem_pio2+0x678>) + 80056d8: f7fa ff42 bl 8000560 <__aeabi_dmul> + 80056dc: 460b mov r3, r1 + 80056de: 4602 mov r2, r0 + 80056e0: 4639 mov r1, r7 + 80056e2: 4630 mov r0, r6 + 80056e4: f7fa fd84 bl 80001f0 <__aeabi_dsub> + 80056e8: f7fb f9ea bl 8000ac0 <__aeabi_d2iz> + 80056ec: 1c65 adds r5, r4, #1 + 80056ee: ab0e add r3, sp, #56 ; 0x38 + 80056f0: f10a 0a18 add.w sl, sl, #24 + 80056f4: f843 0024 str.w r0, [r3, r4, lsl #2] + 80056f8: f843 8025 str.w r8, [r3, r5, lsl #2] + 80056fc: e719 b.n 8005532 <__kernel_rem_pio2+0x292> + 80056fe: 4630 mov r0, r6 + 8005700: 4639 mov r1, r7 + 8005702: f7fb f9dd bl 8000ac0 <__aeabi_d2iz> + 8005706: ab0e add r3, sp, #56 ; 0x38 + 8005708: 4625 mov r5, r4 + 800570a: f843 0024 str.w r0, [r3, r4, lsl #2] + 800570e: e710 b.n 8005532 <__kernel_rem_pio2+0x292> + 8005710: ab0e add r3, sp, #56 ; 0x38 + 8005712: f853 0027 ldr.w r0, [r3, r7, lsl #2] + 8005716: f7fa feb9 bl 800048c <__aeabi_i2d> + 800571a: 4642 mov r2, r8 + 800571c: 464b mov r3, r9 + 800571e: f7fa ff1f bl 8000560 <__aeabi_dmul> + 8005722: 2200 movs r2, #0 + 8005724: e96a 0102 strd r0, r1, [sl, #-8]! + 8005728: 4b7c ldr r3, [pc, #496] ; (800591c <__kernel_rem_pio2+0x67c>) + 800572a: 4640 mov r0, r8 + 800572c: 4649 mov r1, r9 + 800572e: f7fa ff17 bl 8000560 <__aeabi_dmul> + 8005732: 3f01 subs r7, #1 + 8005734: 4680 mov r8, r0 + 8005736: 4689 mov r9, r1 + 8005738: e708 b.n 800554c <__kernel_rem_pio2+0x2ac> + 800573a: eb06 03c7 add.w r3, r6, r7, lsl #3 + 800573e: e9d3 2300 ldrd r2, r3, [r3] + 8005742: e8fb 0102 ldrd r0, r1, [fp], #8 + 8005746: f7fa ff0b bl 8000560 <__aeabi_dmul> + 800574a: 4602 mov r2, r0 + 800574c: 460b mov r3, r1 + 800574e: 4640 mov r0, r8 + 8005750: 4649 mov r1, r9 + 8005752: f7fa fd4f bl 80001f4 <__adddf3> + 8005756: 3701 adds r7, #1 + 8005758: 4680 mov r8, r0 + 800575a: 4689 mov r9, r1 + 800575c: 9b04 ldr r3, [sp, #16] + 800575e: 429f cmp r7, r3 + 8005760: dc01 bgt.n 8005766 <__kernel_rem_pio2+0x4c6> + 8005762: 45ba cmp sl, r7 + 8005764: dae9 bge.n 800573a <__kernel_rem_pio2+0x49a> + 8005766: ab4a add r3, sp, #296 ; 0x128 + 8005768: eb03 03ca add.w r3, r3, sl, lsl #3 + 800576c: e9c3 8900 strd r8, r9, [r3] + 8005770: f10a 0a01 add.w sl, sl, #1 + 8005774: 3e08 subs r6, #8 + 8005776: e6f0 b.n 800555a <__kernel_rem_pio2+0x2ba> + 8005778: 9ba6 ldr r3, [sp, #664] ; 0x298 + 800577a: 2b03 cmp r3, #3 + 800577c: d85b bhi.n 8005836 <__kernel_rem_pio2+0x596> + 800577e: e8df f003 tbb [pc, r3] + 8005782: 264a .short 0x264a + 8005784: 0226 .short 0x0226 + 8005786: ab9a add r3, sp, #616 ; 0x268 + 8005788: 441c add r4, r3 + 800578a: f5a4 749c sub.w r4, r4, #312 ; 0x138 + 800578e: 46a2 mov sl, r4 + 8005790: 46ab mov fp, r5 + 8005792: f1bb 0f00 cmp.w fp, #0 + 8005796: dc6c bgt.n 8005872 <__kernel_rem_pio2+0x5d2> + 8005798: 46a2 mov sl, r4 + 800579a: 46ab mov fp, r5 + 800579c: f1bb 0f01 cmp.w fp, #1 + 80057a0: f300 8086 bgt.w 80058b0 <__kernel_rem_pio2+0x610> + 80057a4: 2000 movs r0, #0 + 80057a6: 2100 movs r1, #0 + 80057a8: 2d01 cmp r5, #1 + 80057aa: f300 80a0 bgt.w 80058ee <__kernel_rem_pio2+0x64e> + 80057ae: 9b02 ldr r3, [sp, #8] + 80057b0: e9dd 784a ldrd r7, r8, [sp, #296] ; 0x128 + 80057b4: e9dd 564c ldrd r5, r6, [sp, #304] ; 0x130 + 80057b8: 2b00 cmp r3, #0 + 80057ba: f040 809e bne.w 80058fa <__kernel_rem_pio2+0x65a> + 80057be: 9b01 ldr r3, [sp, #4] + 80057c0: e9c3 7800 strd r7, r8, [r3] + 80057c4: e9c3 5602 strd r5, r6, [r3, #8] + 80057c8: e9c3 0104 strd r0, r1, [r3, #16] + 80057cc: e033 b.n 8005836 <__kernel_rem_pio2+0x596> + 80057ce: 3408 adds r4, #8 + 80057d0: ab4a add r3, sp, #296 ; 0x128 + 80057d2: 441c add r4, r3 + 80057d4: 462e mov r6, r5 + 80057d6: 2000 movs r0, #0 + 80057d8: 2100 movs r1, #0 + 80057da: 2e00 cmp r6, #0 + 80057dc: da3a bge.n 8005854 <__kernel_rem_pio2+0x5b4> + 80057de: 9b02 ldr r3, [sp, #8] + 80057e0: 2b00 cmp r3, #0 + 80057e2: d03d beq.n 8005860 <__kernel_rem_pio2+0x5c0> + 80057e4: 4602 mov r2, r0 + 80057e6: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 80057ea: 9c01 ldr r4, [sp, #4] + 80057ec: e9c4 2300 strd r2, r3, [r4] + 80057f0: 4602 mov r2, r0 + 80057f2: 460b mov r3, r1 + 80057f4: e9dd 014a ldrd r0, r1, [sp, #296] ; 0x128 + 80057f8: f7fa fcfa bl 80001f0 <__aeabi_dsub> + 80057fc: ae4c add r6, sp, #304 ; 0x130 + 80057fe: 2401 movs r4, #1 + 8005800: 42a5 cmp r5, r4 + 8005802: da30 bge.n 8005866 <__kernel_rem_pio2+0x5c6> + 8005804: 9b02 ldr r3, [sp, #8] + 8005806: b113 cbz r3, 800580e <__kernel_rem_pio2+0x56e> + 8005808: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 800580c: 4619 mov r1, r3 + 800580e: 9b01 ldr r3, [sp, #4] + 8005810: e9c3 0102 strd r0, r1, [r3, #8] + 8005814: e00f b.n 8005836 <__kernel_rem_pio2+0x596> + 8005816: ab9a add r3, sp, #616 ; 0x268 + 8005818: 441c add r4, r3 + 800581a: f5a4 749c sub.w r4, r4, #312 ; 0x138 + 800581e: 2000 movs r0, #0 + 8005820: 2100 movs r1, #0 + 8005822: 2d00 cmp r5, #0 + 8005824: da10 bge.n 8005848 <__kernel_rem_pio2+0x5a8> + 8005826: 9b02 ldr r3, [sp, #8] + 8005828: b113 cbz r3, 8005830 <__kernel_rem_pio2+0x590> + 800582a: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 800582e: 4619 mov r1, r3 + 8005830: 9b01 ldr r3, [sp, #4] + 8005832: e9c3 0100 strd r0, r1, [r3] + 8005836: 9b06 ldr r3, [sp, #24] + 8005838: f003 0007 and.w r0, r3, #7 + 800583c: f50d 7d1b add.w sp, sp, #620 ; 0x26c + 8005840: ecbd 8b02 vpop {d8} + 8005844: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8005848: e974 2302 ldrd r2, r3, [r4, #-8]! + 800584c: f7fa fcd2 bl 80001f4 <__adddf3> + 8005850: 3d01 subs r5, #1 + 8005852: e7e6 b.n 8005822 <__kernel_rem_pio2+0x582> + 8005854: e974 2302 ldrd r2, r3, [r4, #-8]! + 8005858: f7fa fccc bl 80001f4 <__adddf3> + 800585c: 3e01 subs r6, #1 + 800585e: e7bc b.n 80057da <__kernel_rem_pio2+0x53a> + 8005860: 4602 mov r2, r0 + 8005862: 460b mov r3, r1 + 8005864: e7c1 b.n 80057ea <__kernel_rem_pio2+0x54a> + 8005866: e8f6 2302 ldrd r2, r3, [r6], #8 + 800586a: f7fa fcc3 bl 80001f4 <__adddf3> + 800586e: 3401 adds r4, #1 + 8005870: e7c6 b.n 8005800 <__kernel_rem_pio2+0x560> + 8005872: e95a 8904 ldrd r8, r9, [sl, #-16] + 8005876: ed3a 7b02 vldmdb sl!, {d7} + 800587a: 4640 mov r0, r8 + 800587c: ec53 2b17 vmov r2, r3, d7 + 8005880: 4649 mov r1, r9 + 8005882: ed8d 7b04 vstr d7, [sp, #16] + 8005886: f7fa fcb5 bl 80001f4 <__adddf3> + 800588a: 4602 mov r2, r0 + 800588c: 460b mov r3, r1 + 800588e: 4606 mov r6, r0 + 8005890: 460f mov r7, r1 + 8005892: 4640 mov r0, r8 + 8005894: 4649 mov r1, r9 + 8005896: f7fa fcab bl 80001f0 <__aeabi_dsub> + 800589a: e9dd 2304 ldrd r2, r3, [sp, #16] + 800589e: f7fa fca9 bl 80001f4 <__adddf3> + 80058a2: f10b 3bff add.w fp, fp, #4294967295 + 80058a6: e9ca 0100 strd r0, r1, [sl] + 80058aa: e94a 6702 strd r6, r7, [sl, #-8] + 80058ae: e770 b.n 8005792 <__kernel_rem_pio2+0x4f2> + 80058b0: e95a 6704 ldrd r6, r7, [sl, #-16] + 80058b4: ed3a 7b02 vldmdb sl!, {d7} + 80058b8: 4630 mov r0, r6 + 80058ba: ec53 2b17 vmov r2, r3, d7 + 80058be: 4639 mov r1, r7 + 80058c0: ed8d 7b04 vstr d7, [sp, #16] + 80058c4: f7fa fc96 bl 80001f4 <__adddf3> + 80058c8: 4602 mov r2, r0 + 80058ca: 460b mov r3, r1 + 80058cc: 4680 mov r8, r0 + 80058ce: 4689 mov r9, r1 + 80058d0: 4630 mov r0, r6 + 80058d2: 4639 mov r1, r7 + 80058d4: f7fa fc8c bl 80001f0 <__aeabi_dsub> + 80058d8: e9dd 2304 ldrd r2, r3, [sp, #16] + 80058dc: f7fa fc8a bl 80001f4 <__adddf3> + 80058e0: f10b 3bff add.w fp, fp, #4294967295 + 80058e4: e9ca 0100 strd r0, r1, [sl] + 80058e8: e94a 8902 strd r8, r9, [sl, #-8] + 80058ec: e756 b.n 800579c <__kernel_rem_pio2+0x4fc> + 80058ee: e974 2302 ldrd r2, r3, [r4, #-8]! + 80058f2: f7fa fc7f bl 80001f4 <__adddf3> + 80058f6: 3d01 subs r5, #1 + 80058f8: e756 b.n 80057a8 <__kernel_rem_pio2+0x508> + 80058fa: 9b01 ldr r3, [sp, #4] + 80058fc: 9a01 ldr r2, [sp, #4] + 80058fe: 601f str r7, [r3, #0] + 8005900: f108 4400 add.w r4, r8, #2147483648 ; 0x80000000 + 8005904: 605c str r4, [r3, #4] + 8005906: 609d str r5, [r3, #8] + 8005908: f106 4300 add.w r3, r6, #2147483648 ; 0x80000000 + 800590c: 60d3 str r3, [r2, #12] + 800590e: f101 4300 add.w r3, r1, #2147483648 ; 0x80000000 + 8005912: 6110 str r0, [r2, #16] + 8005914: 6153 str r3, [r2, #20] + 8005916: e78e b.n 8005836 <__kernel_rem_pio2+0x596> + 8005918: 41700000 .word 0x41700000 + 800591c: 3e700000 .word 0x3e700000 + +08005920 <__kernel_sin>: + 8005920: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005924: ec55 4b10 vmov r4, r5, d0 + 8005928: b085 sub sp, #20 + 800592a: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 800592e: f1b3 5f79 cmp.w r3, #1044381696 ; 0x3e400000 + 8005932: ed8d 1b00 vstr d1, [sp] + 8005936: 9002 str r0, [sp, #8] + 8005938: da06 bge.n 8005948 <__kernel_sin+0x28> + 800593a: ee10 0a10 vmov r0, s0 + 800593e: 4629 mov r1, r5 + 8005940: f7fb f8be bl 8000ac0 <__aeabi_d2iz> + 8005944: 2800 cmp r0, #0 + 8005946: d051 beq.n 80059ec <__kernel_sin+0xcc> + 8005948: 4622 mov r2, r4 + 800594a: 462b mov r3, r5 + 800594c: 4620 mov r0, r4 + 800594e: 4629 mov r1, r5 + 8005950: f7fa fe06 bl 8000560 <__aeabi_dmul> + 8005954: 4682 mov sl, r0 + 8005956: 468b mov fp, r1 + 8005958: 4602 mov r2, r0 + 800595a: 460b mov r3, r1 + 800595c: 4620 mov r0, r4 + 800595e: 4629 mov r1, r5 + 8005960: f7fa fdfe bl 8000560 <__aeabi_dmul> + 8005964: a341 add r3, pc, #260 ; (adr r3, 8005a6c <__kernel_sin+0x14c>) + 8005966: e9d3 2300 ldrd r2, r3, [r3] + 800596a: 4680 mov r8, r0 + 800596c: 4689 mov r9, r1 + 800596e: 4650 mov r0, sl + 8005970: 4659 mov r1, fp + 8005972: f7fa fdf5 bl 8000560 <__aeabi_dmul> + 8005976: a33f add r3, pc, #252 ; (adr r3, 8005a74 <__kernel_sin+0x154>) + 8005978: e9d3 2300 ldrd r2, r3, [r3] + 800597c: f7fa fc38 bl 80001f0 <__aeabi_dsub> + 8005980: 4652 mov r2, sl + 8005982: 465b mov r3, fp + 8005984: f7fa fdec bl 8000560 <__aeabi_dmul> + 8005988: a33c add r3, pc, #240 ; (adr r3, 8005a7c <__kernel_sin+0x15c>) + 800598a: e9d3 2300 ldrd r2, r3, [r3] + 800598e: f7fa fc31 bl 80001f4 <__adddf3> + 8005992: 4652 mov r2, sl + 8005994: 465b mov r3, fp + 8005996: f7fa fde3 bl 8000560 <__aeabi_dmul> + 800599a: a33a add r3, pc, #232 ; (adr r3, 8005a84 <__kernel_sin+0x164>) + 800599c: e9d3 2300 ldrd r2, r3, [r3] + 80059a0: f7fa fc26 bl 80001f0 <__aeabi_dsub> + 80059a4: 4652 mov r2, sl + 80059a6: 465b mov r3, fp + 80059a8: f7fa fdda bl 8000560 <__aeabi_dmul> + 80059ac: a337 add r3, pc, #220 ; (adr r3, 8005a8c <__kernel_sin+0x16c>) + 80059ae: e9d3 2300 ldrd r2, r3, [r3] + 80059b2: f7fa fc1f bl 80001f4 <__adddf3> + 80059b6: 9b02 ldr r3, [sp, #8] + 80059b8: 4606 mov r6, r0 + 80059ba: 460f mov r7, r1 + 80059bc: b9db cbnz r3, 80059f6 <__kernel_sin+0xd6> + 80059be: 4602 mov r2, r0 + 80059c0: 460b mov r3, r1 + 80059c2: 4650 mov r0, sl + 80059c4: 4659 mov r1, fp + 80059c6: f7fa fdcb bl 8000560 <__aeabi_dmul> + 80059ca: a325 add r3, pc, #148 ; (adr r3, 8005a60 <__kernel_sin+0x140>) + 80059cc: e9d3 2300 ldrd r2, r3, [r3] + 80059d0: f7fa fc0e bl 80001f0 <__aeabi_dsub> + 80059d4: 4642 mov r2, r8 + 80059d6: 464b mov r3, r9 + 80059d8: f7fa fdc2 bl 8000560 <__aeabi_dmul> + 80059dc: 4602 mov r2, r0 + 80059de: 460b mov r3, r1 + 80059e0: 4620 mov r0, r4 + 80059e2: 4629 mov r1, r5 + 80059e4: f7fa fc06 bl 80001f4 <__adddf3> + 80059e8: 4604 mov r4, r0 + 80059ea: 460d mov r5, r1 + 80059ec: ec45 4b10 vmov d0, r4, r5 + 80059f0: b005 add sp, #20 + 80059f2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 80059f6: 2200 movs r2, #0 + 80059f8: 4b1b ldr r3, [pc, #108] ; (8005a68 <__kernel_sin+0x148>) + 80059fa: e9dd 0100 ldrd r0, r1, [sp] + 80059fe: f7fa fdaf bl 8000560 <__aeabi_dmul> + 8005a02: 4632 mov r2, r6 + 8005a04: e9cd 0102 strd r0, r1, [sp, #8] + 8005a08: 463b mov r3, r7 + 8005a0a: 4640 mov r0, r8 + 8005a0c: 4649 mov r1, r9 + 8005a0e: f7fa fda7 bl 8000560 <__aeabi_dmul> + 8005a12: 4602 mov r2, r0 + 8005a14: 460b mov r3, r1 + 8005a16: e9dd 0102 ldrd r0, r1, [sp, #8] + 8005a1a: f7fa fbe9 bl 80001f0 <__aeabi_dsub> + 8005a1e: 4652 mov r2, sl + 8005a20: 465b mov r3, fp + 8005a22: f7fa fd9d bl 8000560 <__aeabi_dmul> + 8005a26: e9dd 2300 ldrd r2, r3, [sp] + 8005a2a: f7fa fbe1 bl 80001f0 <__aeabi_dsub> + 8005a2e: a30c add r3, pc, #48 ; (adr r3, 8005a60 <__kernel_sin+0x140>) + 8005a30: e9d3 2300 ldrd r2, r3, [r3] + 8005a34: 4606 mov r6, r0 + 8005a36: 460f mov r7, r1 + 8005a38: 4640 mov r0, r8 + 8005a3a: 4649 mov r1, r9 + 8005a3c: f7fa fd90 bl 8000560 <__aeabi_dmul> + 8005a40: 4602 mov r2, r0 + 8005a42: 460b mov r3, r1 + 8005a44: 4630 mov r0, r6 + 8005a46: 4639 mov r1, r7 + 8005a48: f7fa fbd4 bl 80001f4 <__adddf3> + 8005a4c: 4602 mov r2, r0 + 8005a4e: 460b mov r3, r1 + 8005a50: 4620 mov r0, r4 + 8005a52: 4629 mov r1, r5 + 8005a54: f7fa fbcc bl 80001f0 <__aeabi_dsub> + 8005a58: e7c6 b.n 80059e8 <__kernel_sin+0xc8> + 8005a5a: bf00 nop + 8005a5c: f3af 8000 nop.w + 8005a60: 55555549 .word 0x55555549 + 8005a64: 3fc55555 .word 0x3fc55555 + 8005a68: 3fe00000 .word 0x3fe00000 + 8005a6c: 5acfd57c .word 0x5acfd57c + 8005a70: 3de5d93a .word 0x3de5d93a + 8005a74: 8a2b9ceb .word 0x8a2b9ceb + 8005a78: 3e5ae5e6 .word 0x3e5ae5e6 + 8005a7c: 57b1fe7d .word 0x57b1fe7d + 8005a80: 3ec71de3 .word 0x3ec71de3 + 8005a84: 19c161d5 .word 0x19c161d5 + 8005a88: 3f2a01a0 .word 0x3f2a01a0 + 8005a8c: 1110f8a6 .word 0x1110f8a6 + 8005a90: 3f811111 .word 0x3f811111 + 8005a94: 00000000 .word 0x00000000 + +08005a98 <__kernel_tan>: + 8005a98: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005a9c: ec5b ab10 vmov sl, fp, d0 + 8005aa0: 4bbf ldr r3, [pc, #764] ; (8005da0 <__kernel_tan+0x308>) + 8005aa2: b089 sub sp, #36 ; 0x24 + 8005aa4: f02b 4700 bic.w r7, fp, #2147483648 ; 0x80000000 + 8005aa8: 429f cmp r7, r3 + 8005aaa: ec59 8b11 vmov r8, r9, d1 + 8005aae: 4606 mov r6, r0 + 8005ab0: f8cd b008 str.w fp, [sp, #8] + 8005ab4: dc22 bgt.n 8005afc <__kernel_tan+0x64> + 8005ab6: ee10 0a10 vmov r0, s0 + 8005aba: 4659 mov r1, fp + 8005abc: f7fb f800 bl 8000ac0 <__aeabi_d2iz> + 8005ac0: 2800 cmp r0, #0 + 8005ac2: d145 bne.n 8005b50 <__kernel_tan+0xb8> + 8005ac4: 1c73 adds r3, r6, #1 + 8005ac6: 4652 mov r2, sl + 8005ac8: 4313 orrs r3, r2 + 8005aca: 433b orrs r3, r7 + 8005acc: d110 bne.n 8005af0 <__kernel_tan+0x58> + 8005ace: ec4b ab10 vmov d0, sl, fp + 8005ad2: f000 f9ad bl 8005e30 + 8005ad6: 49b3 ldr r1, [pc, #716] ; (8005da4 <__kernel_tan+0x30c>) + 8005ad8: ec53 2b10 vmov r2, r3, d0 + 8005adc: 2000 movs r0, #0 + 8005ade: f7fa fe69 bl 80007b4 <__aeabi_ddiv> + 8005ae2: 4682 mov sl, r0 + 8005ae4: 468b mov fp, r1 + 8005ae6: ec4b ab10 vmov d0, sl, fp + 8005aea: b009 add sp, #36 ; 0x24 + 8005aec: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 8005af0: 2e01 cmp r6, #1 + 8005af2: d0f8 beq.n 8005ae6 <__kernel_tan+0x4e> + 8005af4: 465b mov r3, fp + 8005af6: 2000 movs r0, #0 + 8005af8: 49ab ldr r1, [pc, #684] ; (8005da8 <__kernel_tan+0x310>) + 8005afa: e7f0 b.n 8005ade <__kernel_tan+0x46> + 8005afc: 4bab ldr r3, [pc, #684] ; (8005dac <__kernel_tan+0x314>) + 8005afe: 429f cmp r7, r3 + 8005b00: dd26 ble.n 8005b50 <__kernel_tan+0xb8> + 8005b02: 9b02 ldr r3, [sp, #8] + 8005b04: 2b00 cmp r3, #0 + 8005b06: da09 bge.n 8005b1c <__kernel_tan+0x84> + 8005b08: f10b 4300 add.w r3, fp, #2147483648 ; 0x80000000 + 8005b0c: 469b mov fp, r3 + 8005b0e: ee10 aa10 vmov sl, s0 + 8005b12: f109 4300 add.w r3, r9, #2147483648 ; 0x80000000 + 8005b16: ee11 8a10 vmov r8, s2 + 8005b1a: 4699 mov r9, r3 + 8005b1c: 4652 mov r2, sl + 8005b1e: 465b mov r3, fp + 8005b20: a181 add r1, pc, #516 ; (adr r1, 8005d28 <__kernel_tan+0x290>) + 8005b22: e9d1 0100 ldrd r0, r1, [r1] + 8005b26: f7fa fb63 bl 80001f0 <__aeabi_dsub> + 8005b2a: 4642 mov r2, r8 + 8005b2c: 464b mov r3, r9 + 8005b2e: 4604 mov r4, r0 + 8005b30: 460d mov r5, r1 + 8005b32: a17f add r1, pc, #508 ; (adr r1, 8005d30 <__kernel_tan+0x298>) + 8005b34: e9d1 0100 ldrd r0, r1, [r1] + 8005b38: f7fa fb5a bl 80001f0 <__aeabi_dsub> + 8005b3c: 4622 mov r2, r4 + 8005b3e: 462b mov r3, r5 + 8005b40: f7fa fb58 bl 80001f4 <__adddf3> + 8005b44: f04f 0800 mov.w r8, #0 + 8005b48: 4682 mov sl, r0 + 8005b4a: 468b mov fp, r1 + 8005b4c: f04f 0900 mov.w r9, #0 + 8005b50: 4652 mov r2, sl + 8005b52: 465b mov r3, fp + 8005b54: 4650 mov r0, sl + 8005b56: 4659 mov r1, fp + 8005b58: f7fa fd02 bl 8000560 <__aeabi_dmul> + 8005b5c: 4602 mov r2, r0 + 8005b5e: 460b mov r3, r1 + 8005b60: e9cd 0100 strd r0, r1, [sp] + 8005b64: f7fa fcfc bl 8000560 <__aeabi_dmul> + 8005b68: e9dd 2300 ldrd r2, r3, [sp] + 8005b6c: 4604 mov r4, r0 + 8005b6e: 460d mov r5, r1 + 8005b70: 4650 mov r0, sl + 8005b72: 4659 mov r1, fp + 8005b74: f7fa fcf4 bl 8000560 <__aeabi_dmul> + 8005b78: a36f add r3, pc, #444 ; (adr r3, 8005d38 <__kernel_tan+0x2a0>) + 8005b7a: e9d3 2300 ldrd r2, r3, [r3] + 8005b7e: e9cd 0104 strd r0, r1, [sp, #16] + 8005b82: 4620 mov r0, r4 + 8005b84: 4629 mov r1, r5 + 8005b86: f7fa fceb bl 8000560 <__aeabi_dmul> + 8005b8a: a36d add r3, pc, #436 ; (adr r3, 8005d40 <__kernel_tan+0x2a8>) + 8005b8c: e9d3 2300 ldrd r2, r3, [r3] + 8005b90: f7fa fb30 bl 80001f4 <__adddf3> + 8005b94: 4622 mov r2, r4 + 8005b96: 462b mov r3, r5 + 8005b98: f7fa fce2 bl 8000560 <__aeabi_dmul> + 8005b9c: a36a add r3, pc, #424 ; (adr r3, 8005d48 <__kernel_tan+0x2b0>) + 8005b9e: e9d3 2300 ldrd r2, r3, [r3] + 8005ba2: f7fa fb27 bl 80001f4 <__adddf3> + 8005ba6: 4622 mov r2, r4 + 8005ba8: 462b mov r3, r5 + 8005baa: f7fa fcd9 bl 8000560 <__aeabi_dmul> + 8005bae: a368 add r3, pc, #416 ; (adr r3, 8005d50 <__kernel_tan+0x2b8>) + 8005bb0: e9d3 2300 ldrd r2, r3, [r3] + 8005bb4: f7fa fb1e bl 80001f4 <__adddf3> + 8005bb8: 4622 mov r2, r4 + 8005bba: 462b mov r3, r5 + 8005bbc: f7fa fcd0 bl 8000560 <__aeabi_dmul> + 8005bc0: a365 add r3, pc, #404 ; (adr r3, 8005d58 <__kernel_tan+0x2c0>) + 8005bc2: e9d3 2300 ldrd r2, r3, [r3] + 8005bc6: f7fa fb15 bl 80001f4 <__adddf3> + 8005bca: 4622 mov r2, r4 + 8005bcc: 462b mov r3, r5 + 8005bce: f7fa fcc7 bl 8000560 <__aeabi_dmul> + 8005bd2: a363 add r3, pc, #396 ; (adr r3, 8005d60 <__kernel_tan+0x2c8>) + 8005bd4: e9d3 2300 ldrd r2, r3, [r3] + 8005bd8: f7fa fb0c bl 80001f4 <__adddf3> + 8005bdc: e9dd 2300 ldrd r2, r3, [sp] + 8005be0: f7fa fcbe bl 8000560 <__aeabi_dmul> + 8005be4: a360 add r3, pc, #384 ; (adr r3, 8005d68 <__kernel_tan+0x2d0>) + 8005be6: e9d3 2300 ldrd r2, r3, [r3] + 8005bea: e9cd 0106 strd r0, r1, [sp, #24] + 8005bee: 4620 mov r0, r4 + 8005bf0: 4629 mov r1, r5 + 8005bf2: f7fa fcb5 bl 8000560 <__aeabi_dmul> + 8005bf6: a35e add r3, pc, #376 ; (adr r3, 8005d70 <__kernel_tan+0x2d8>) + 8005bf8: e9d3 2300 ldrd r2, r3, [r3] + 8005bfc: f7fa fafa bl 80001f4 <__adddf3> + 8005c00: 4622 mov r2, r4 + 8005c02: 462b mov r3, r5 + 8005c04: f7fa fcac bl 8000560 <__aeabi_dmul> + 8005c08: a35b add r3, pc, #364 ; (adr r3, 8005d78 <__kernel_tan+0x2e0>) + 8005c0a: e9d3 2300 ldrd r2, r3, [r3] + 8005c0e: f7fa faf1 bl 80001f4 <__adddf3> + 8005c12: 4622 mov r2, r4 + 8005c14: 462b mov r3, r5 + 8005c16: f7fa fca3 bl 8000560 <__aeabi_dmul> + 8005c1a: a359 add r3, pc, #356 ; (adr r3, 8005d80 <__kernel_tan+0x2e8>) + 8005c1c: e9d3 2300 ldrd r2, r3, [r3] + 8005c20: f7fa fae8 bl 80001f4 <__adddf3> + 8005c24: 4622 mov r2, r4 + 8005c26: 462b mov r3, r5 + 8005c28: f7fa fc9a bl 8000560 <__aeabi_dmul> + 8005c2c: a356 add r3, pc, #344 ; (adr r3, 8005d88 <__kernel_tan+0x2f0>) + 8005c2e: e9d3 2300 ldrd r2, r3, [r3] + 8005c32: f7fa fadf bl 80001f4 <__adddf3> + 8005c36: 4622 mov r2, r4 + 8005c38: 462b mov r3, r5 + 8005c3a: f7fa fc91 bl 8000560 <__aeabi_dmul> + 8005c3e: a354 add r3, pc, #336 ; (adr r3, 8005d90 <__kernel_tan+0x2f8>) + 8005c40: e9d3 2300 ldrd r2, r3, [r3] + 8005c44: f7fa fad6 bl 80001f4 <__adddf3> + 8005c48: 4602 mov r2, r0 + 8005c4a: 460b mov r3, r1 + 8005c4c: e9dd 0106 ldrd r0, r1, [sp, #24] + 8005c50: f7fa fad0 bl 80001f4 <__adddf3> + 8005c54: e9dd 2304 ldrd r2, r3, [sp, #16] + 8005c58: f7fa fc82 bl 8000560 <__aeabi_dmul> + 8005c5c: 4642 mov r2, r8 + 8005c5e: 464b mov r3, r9 + 8005c60: f7fa fac8 bl 80001f4 <__adddf3> + 8005c64: e9dd 2300 ldrd r2, r3, [sp] + 8005c68: f7fa fc7a bl 8000560 <__aeabi_dmul> + 8005c6c: 4642 mov r2, r8 + 8005c6e: 464b mov r3, r9 + 8005c70: f7fa fac0 bl 80001f4 <__adddf3> + 8005c74: a348 add r3, pc, #288 ; (adr r3, 8005d98 <__kernel_tan+0x300>) + 8005c76: e9d3 2300 ldrd r2, r3, [r3] + 8005c7a: 4604 mov r4, r0 + 8005c7c: 460d mov r5, r1 + 8005c7e: e9dd 0104 ldrd r0, r1, [sp, #16] + 8005c82: f7fa fc6d bl 8000560 <__aeabi_dmul> + 8005c86: 4622 mov r2, r4 + 8005c88: 462b mov r3, r5 + 8005c8a: f7fa fab3 bl 80001f4 <__adddf3> + 8005c8e: e9cd 0100 strd r0, r1, [sp] + 8005c92: 460b mov r3, r1 + 8005c94: 4602 mov r2, r0 + 8005c96: 4659 mov r1, fp + 8005c98: 4650 mov r0, sl + 8005c9a: f7fa faab bl 80001f4 <__adddf3> + 8005c9e: 4b43 ldr r3, [pc, #268] ; (8005dac <__kernel_tan+0x314>) + 8005ca0: 429f cmp r7, r3 + 8005ca2: 4604 mov r4, r0 + 8005ca4: 460d mov r5, r1 + 8005ca6: f340 8083 ble.w 8005db0 <__kernel_tan+0x318> + 8005caa: 4630 mov r0, r6 + 8005cac: f7fa fbee bl 800048c <__aeabi_i2d> + 8005cb0: 4622 mov r2, r4 + 8005cb2: 4680 mov r8, r0 + 8005cb4: 4689 mov r9, r1 + 8005cb6: 462b mov r3, r5 + 8005cb8: 4620 mov r0, r4 + 8005cba: 4629 mov r1, r5 + 8005cbc: f7fa fc50 bl 8000560 <__aeabi_dmul> + 8005cc0: 4642 mov r2, r8 + 8005cc2: 4606 mov r6, r0 + 8005cc4: 460f mov r7, r1 + 8005cc6: 464b mov r3, r9 + 8005cc8: 4620 mov r0, r4 + 8005cca: 4629 mov r1, r5 + 8005ccc: f7fa fa92 bl 80001f4 <__adddf3> + 8005cd0: 4602 mov r2, r0 + 8005cd2: 460b mov r3, r1 + 8005cd4: 4630 mov r0, r6 + 8005cd6: 4639 mov r1, r7 + 8005cd8: f7fa fd6c bl 80007b4 <__aeabi_ddiv> + 8005cdc: e9dd 2300 ldrd r2, r3, [sp] + 8005ce0: f7fa fa86 bl 80001f0 <__aeabi_dsub> + 8005ce4: 4602 mov r2, r0 + 8005ce6: 460b mov r3, r1 + 8005ce8: 4650 mov r0, sl + 8005cea: 4659 mov r1, fp + 8005cec: f7fa fa80 bl 80001f0 <__aeabi_dsub> + 8005cf0: 4602 mov r2, r0 + 8005cf2: 460b mov r3, r1 + 8005cf4: f7fa fa7e bl 80001f4 <__adddf3> + 8005cf8: 4602 mov r2, r0 + 8005cfa: 460b mov r3, r1 + 8005cfc: 4640 mov r0, r8 + 8005cfe: 4649 mov r1, r9 + 8005d00: f7fa fa76 bl 80001f0 <__aeabi_dsub> + 8005d04: 9b02 ldr r3, [sp, #8] + 8005d06: 4604 mov r4, r0 + 8005d08: 1798 asrs r0, r3, #30 + 8005d0a: f000 0002 and.w r0, r0, #2 + 8005d0e: f1c0 0001 rsb r0, r0, #1 + 8005d12: 460d mov r5, r1 + 8005d14: f7fa fbba bl 800048c <__aeabi_i2d> + 8005d18: 4602 mov r2, r0 + 8005d1a: 460b mov r3, r1 + 8005d1c: 4620 mov r0, r4 + 8005d1e: 4629 mov r1, r5 + 8005d20: f7fa fc1e bl 8000560 <__aeabi_dmul> + 8005d24: e6dd b.n 8005ae2 <__kernel_tan+0x4a> + 8005d26: bf00 nop + 8005d28: 54442d18 .word 0x54442d18 + 8005d2c: 3fe921fb .word 0x3fe921fb + 8005d30: 33145c07 .word 0x33145c07 + 8005d34: 3c81a626 .word 0x3c81a626 + 8005d38: 74bf7ad4 .word 0x74bf7ad4 + 8005d3c: 3efb2a70 .word 0x3efb2a70 + 8005d40: 32f0a7e9 .word 0x32f0a7e9 + 8005d44: 3f12b80f .word 0x3f12b80f + 8005d48: 1a8d1068 .word 0x1a8d1068 + 8005d4c: 3f3026f7 .word 0x3f3026f7 + 8005d50: fee08315 .word 0xfee08315 + 8005d54: 3f57dbc8 .word 0x3f57dbc8 + 8005d58: e96e8493 .word 0xe96e8493 + 8005d5c: 3f8226e3 .word 0x3f8226e3 + 8005d60: 1bb341fe .word 0x1bb341fe + 8005d64: 3faba1ba .word 0x3faba1ba + 8005d68: db605373 .word 0xdb605373 + 8005d6c: bef375cb .word 0xbef375cb + 8005d70: a03792a6 .word 0xa03792a6 + 8005d74: 3f147e88 .word 0x3f147e88 + 8005d78: f2f26501 .word 0xf2f26501 + 8005d7c: 3f4344d8 .word 0x3f4344d8 + 8005d80: c9560328 .word 0xc9560328 + 8005d84: 3f6d6d22 .word 0x3f6d6d22 + 8005d88: 8406d637 .word 0x8406d637 + 8005d8c: 3f9664f4 .word 0x3f9664f4 + 8005d90: 1110fe7a .word 0x1110fe7a + 8005d94: 3fc11111 .word 0x3fc11111 + 8005d98: 55555563 .word 0x55555563 + 8005d9c: 3fd55555 .word 0x3fd55555 + 8005da0: 3e2fffff .word 0x3e2fffff + 8005da4: 3ff00000 .word 0x3ff00000 + 8005da8: bff00000 .word 0xbff00000 + 8005dac: 3fe59427 .word 0x3fe59427 + 8005db0: 2e01 cmp r6, #1 + 8005db2: d036 beq.n 8005e22 <__kernel_tan+0x38a> + 8005db4: 460f mov r7, r1 + 8005db6: 4602 mov r2, r0 + 8005db8: 460b mov r3, r1 + 8005dba: 2000 movs r0, #0 + 8005dbc: 491a ldr r1, [pc, #104] ; (8005e28 <__kernel_tan+0x390>) + 8005dbe: f7fa fcf9 bl 80007b4 <__aeabi_ddiv> + 8005dc2: 2600 movs r6, #0 + 8005dc4: e9cd 0102 strd r0, r1, [sp, #8] + 8005dc8: 4652 mov r2, sl + 8005dca: 465b mov r3, fp + 8005dcc: 4630 mov r0, r6 + 8005dce: 4639 mov r1, r7 + 8005dd0: f7fa fa0e bl 80001f0 <__aeabi_dsub> + 8005dd4: e9dd 4502 ldrd r4, r5, [sp, #8] + 8005dd8: 4602 mov r2, r0 + 8005dda: 460b mov r3, r1 + 8005ddc: e9dd 0100 ldrd r0, r1, [sp] + 8005de0: f7fa fa06 bl 80001f0 <__aeabi_dsub> + 8005de4: 4632 mov r2, r6 + 8005de6: 462b mov r3, r5 + 8005de8: f7fa fbba bl 8000560 <__aeabi_dmul> + 8005dec: 4632 mov r2, r6 + 8005dee: 4682 mov sl, r0 + 8005df0: 468b mov fp, r1 + 8005df2: 462b mov r3, r5 + 8005df4: 4630 mov r0, r6 + 8005df6: 4639 mov r1, r7 + 8005df8: f7fa fbb2 bl 8000560 <__aeabi_dmul> + 8005dfc: 2200 movs r2, #0 + 8005dfe: 4b0b ldr r3, [pc, #44] ; (8005e2c <__kernel_tan+0x394>) + 8005e00: f7fa f9f8 bl 80001f4 <__adddf3> + 8005e04: 4602 mov r2, r0 + 8005e06: 460b mov r3, r1 + 8005e08: 4650 mov r0, sl + 8005e0a: 4659 mov r1, fp + 8005e0c: f7fa f9f2 bl 80001f4 <__adddf3> + 8005e10: e9dd 2302 ldrd r2, r3, [sp, #8] + 8005e14: f7fa fba4 bl 8000560 <__aeabi_dmul> + 8005e18: 4632 mov r2, r6 + 8005e1a: 462b mov r3, r5 + 8005e1c: f7fa f9ea bl 80001f4 <__adddf3> + 8005e20: e65f b.n 8005ae2 <__kernel_tan+0x4a> + 8005e22: 4682 mov sl, r0 + 8005e24: 468b mov fp, r1 + 8005e26: e65e b.n 8005ae6 <__kernel_tan+0x4e> + 8005e28: bff00000 .word 0xbff00000 + 8005e2c: 3ff00000 .word 0x3ff00000 + +08005e30 : + 8005e30: ec51 0b10 vmov r0, r1, d0 + 8005e34: ee10 2a10 vmov r2, s0 + 8005e38: f021 4300 bic.w r3, r1, #2147483648 ; 0x80000000 + 8005e3c: ec43 2b10 vmov d0, r2, r3 + 8005e40: 4770 bx lr + +08005e42 : + 8005e42: 2000 movs r0, #0 + 8005e44: 4770 bx lr + ... + +08005e48 : + 8005e48: ed9f 0b01 vldr d0, [pc, #4] ; 8005e50 + 8005e4c: 4770 bx lr + 8005e4e: bf00 nop + 8005e50: 00000000 .word 0x00000000 + 8005e54: 7ff80000 .word 0x7ff80000 + +08005e58 : + 8005e58: b570 push {r4, r5, r6, lr} + 8005e5a: ec55 4b10 vmov r4, r5, d0 + 8005e5e: f3c5 520a ubfx r2, r5, #20, #11 + 8005e62: 4606 mov r6, r0 + 8005e64: 462b mov r3, r5 + 8005e66: b9aa cbnz r2, 8005e94 + 8005e68: f025 4300 bic.w r3, r5, #2147483648 ; 0x80000000 + 8005e6c: 4323 orrs r3, r4 + 8005e6e: d03b beq.n 8005ee8 + 8005e70: 4b31 ldr r3, [pc, #196] ; (8005f38 ) + 8005e72: 4629 mov r1, r5 + 8005e74: 2200 movs r2, #0 + 8005e76: ee10 0a10 vmov r0, s0 + 8005e7a: f7fa fb71 bl 8000560 <__aeabi_dmul> + 8005e7e: 4b2f ldr r3, [pc, #188] ; (8005f3c ) + 8005e80: 429e cmp r6, r3 + 8005e82: 4604 mov r4, r0 + 8005e84: 460d mov r5, r1 + 8005e86: da12 bge.n 8005eae + 8005e88: a327 add r3, pc, #156 ; (adr r3, 8005f28 ) + 8005e8a: e9d3 2300 ldrd r2, r3, [r3] + 8005e8e: f7fa fb67 bl 8000560 <__aeabi_dmul> + 8005e92: e009 b.n 8005ea8 + 8005e94: f240 71ff movw r1, #2047 ; 0x7ff + 8005e98: 428a cmp r2, r1 + 8005e9a: d10c bne.n 8005eb6 + 8005e9c: ee10 2a10 vmov r2, s0 + 8005ea0: 4620 mov r0, r4 + 8005ea2: 4629 mov r1, r5 + 8005ea4: f7fa f9a6 bl 80001f4 <__adddf3> + 8005ea8: 4604 mov r4, r0 + 8005eaa: 460d mov r5, r1 + 8005eac: e01c b.n 8005ee8 + 8005eae: f3c1 520a ubfx r2, r1, #20, #11 + 8005eb2: 460b mov r3, r1 + 8005eb4: 3a36 subs r2, #54 ; 0x36 + 8005eb6: 4432 add r2, r6 + 8005eb8: f240 71fe movw r1, #2046 ; 0x7fe + 8005ebc: 428a cmp r2, r1 + 8005ebe: dd0b ble.n 8005ed8 + 8005ec0: ec45 4b11 vmov d1, r4, r5 + 8005ec4: ed9f 0b1a vldr d0, [pc, #104] ; 8005f30 + 8005ec8: f000 f83c bl 8005f44 + 8005ecc: a318 add r3, pc, #96 ; (adr r3, 8005f30 ) + 8005ece: e9d3 2300 ldrd r2, r3, [r3] + 8005ed2: ec51 0b10 vmov r0, r1, d0 + 8005ed6: e7da b.n 8005e8e + 8005ed8: 2a00 cmp r2, #0 + 8005eda: dd08 ble.n 8005eee + 8005edc: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 8005ee0: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 8005ee4: ea43 5502 orr.w r5, r3, r2, lsl #20 + 8005ee8: ec45 4b10 vmov d0, r4, r5 + 8005eec: bd70 pop {r4, r5, r6, pc} + 8005eee: f112 0f35 cmn.w r2, #53 ; 0x35 + 8005ef2: da0d bge.n 8005f10 + 8005ef4: f24c 3350 movw r3, #50000 ; 0xc350 + 8005ef8: 429e cmp r6, r3 + 8005efa: ec45 4b11 vmov d1, r4, r5 + 8005efe: dce1 bgt.n 8005ec4 + 8005f00: ed9f 0b09 vldr d0, [pc, #36] ; 8005f28 + 8005f04: f000 f81e bl 8005f44 + 8005f08: a307 add r3, pc, #28 ; (adr r3, 8005f28 ) + 8005f0a: e9d3 2300 ldrd r2, r3, [r3] + 8005f0e: e7e0 b.n 8005ed2 + 8005f10: f023 43ff bic.w r3, r3, #2139095040 ; 0x7f800000 + 8005f14: 3236 adds r2, #54 ; 0x36 + 8005f16: f423 03e0 bic.w r3, r3, #7340032 ; 0x700000 + 8005f1a: ea43 5502 orr.w r5, r3, r2, lsl #20 + 8005f1e: 4620 mov r0, r4 + 8005f20: 4629 mov r1, r5 + 8005f22: 2200 movs r2, #0 + 8005f24: 4b06 ldr r3, [pc, #24] ; (8005f40 ) + 8005f26: e7b2 b.n 8005e8e + 8005f28: c2f8f359 .word 0xc2f8f359 + 8005f2c: 01a56e1f .word 0x01a56e1f + 8005f30: 8800759c .word 0x8800759c + 8005f34: 7e37e43c .word 0x7e37e43c + 8005f38: 43500000 .word 0x43500000 + 8005f3c: ffff3cb0 .word 0xffff3cb0 + 8005f40: 3c900000 .word 0x3c900000 + +08005f44 : + 8005f44: ec51 0b10 vmov r0, r1, d0 + 8005f48: ee11 0a90 vmov r0, s3 + 8005f4c: ee10 2a10 vmov r2, s0 + 8005f50: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 + 8005f54: f000 4000 and.w r0, r0, #2147483648 ; 0x80000000 + 8005f58: ea41 0300 orr.w r3, r1, r0 + 8005f5c: ec43 2b10 vmov d0, r2, r3 + 8005f60: 4770 bx lr + ... + +08005f64 <_init>: + 8005f64: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005f66: bf00 nop + 8005f68: bcf8 pop {r3, r4, r5, r6, r7} + 8005f6a: bc08 pop {r3} + 8005f6c: 469e mov lr, r3 + 8005f6e: 4770 bx lr + +08005f70 <_fini>: + 8005f70: b5f8 push {r3, r4, r5, r6, r7, lr} + 8005f72: bf00 nop + 8005f74: bcf8 pop {r3, r4, r5, r6, r7} + 8005f76: bc08 pop {r3} + 8005f78: 469e mov lr, r3 + 8005f7a: 4770 bx lr diff --git a/RTC/Debug/RTC.map b/RTC/Debug/RTC.map index e04689a..02b236a 100644 --- a/RTC/Debug/RTC.map +++ b/RTC/Debug/RTC.map @@ -1,45 +1,110 @@ Archive member included to satisfy reference by file (symbol) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) Core/Src/syscalls.o (__errno) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o (exit) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) - c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) (_global_impure_ptr) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) - c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o (__libc_init_array) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) - c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o (memset) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) - Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o (__aeabi_uldivmod) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) - c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) -c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_dvmd_tls.o) - c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o (exit) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o (__libc_init_array) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o (memset) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-strlen.o) + Core/Src/main.o (strlen) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + Core/Src/main.o (cos) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + Core/Src/main.o (floor) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + Core/Src/main.o (sin) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + Core/Src/main.o (tan) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + Core/Src/main.o (acos) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) (__ieee754_acos) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) (__ieee754_rem_pio2) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) (__ieee754_sqrt) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) (__kernel_cos) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) (__kernel_rem_pio2) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) (__kernel_sin) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) (__kernel_tan) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) (fabs) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_lib_ver.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) (__fdlib_version) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) (matherr) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) (nan) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) (scalbn) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) (copysign) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_addsubdf3.o) + Core/Src/main.o (__aeabi_dsub) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_muldivdf3.o) + Core/Src/main.o (__aeabi_dmul) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_cmpdf2.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) (__aeabi_dcmpeq) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_unorddf2.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) (__aeabi_dcmpun) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_fixdfsi.o) + Core/Src/main.o (__aeabi_d2iz) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) + Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o (__aeabi_uldivmod) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4) +c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_dvmd_tls.o) + c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0) Allocating common symbols Common symbol size file sTime 0x14 Core/Src/main.o -uwTick 0x4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o -pFlash 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o +uwTick 0x4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o +sAlarm 0x28 Core/Src/main.o +pFlash 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o sDate 0x4 Core/Src/main.o hrtc 0x20 Core/Src/main.o huart2 0x40 Core/Src/main.o Discarded input sections - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o - .data 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o - .text 0x0000000000000000 0x74 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o - .ARM.extab 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o - .ARM.exidx 0x0000000000000000 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + .data 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + .text 0x0000000000000000 0x74 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .ARM.extab 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .ARM.exidx 0x0000000000000000 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o .ARM.attributes - 0x0000000000000000 0x1b c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o + 0x0000000000000000 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o + .group 0x0000000000000000 0xc Core/Src/main.o .group 0x0000000000000000 0xc Core/Src/main.o .group 0x0000000000000000 0xc Core/Src/main.o .group 0x0000000000000000 0xc Core/Src/main.o @@ -80,164 +145,180 @@ Discarded input sections .text 0x0000000000000000 0x0 Core/Src/main.o .data 0x0000000000000000 0x0 Core/Src/main.o .bss 0x0000000000000000 0x0 Core/Src/main.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_hal_msp.o - .text 0x0000000000000000 0x0 Core/Src/stm32l1xx_hal_msp.o - .data 0x0000000000000000 0x0 Core/Src/stm32l1xx_hal_msp.o - .bss 0x0000000000000000 0x0 Core/Src/stm32l1xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_hal_msp.o + .text 0x0000000000000000 0x0 Core/Src/stm32f4xx_hal_msp.o + .data 0x0000000000000000 0x0 Core/Src/stm32f4xx_hal_msp.o + .bss 0x0000000000000000 0x0 Core/Src/stm32f4xx_hal_msp.o .text.HAL_RTC_MspDeInit - 0x0000000000000000 0x2c Core/Src/stm32l1xx_hal_msp.o + 0x0000000000000000 0x30 Core/Src/stm32f4xx_hal_msp.o .text.HAL_UART_MspDeInit - 0x0000000000000000 0x3c Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x112 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x2e Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x8e Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x51 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xef Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x6a Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x1df Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x1c Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xc3 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xe49 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x11f Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xb52b Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x43 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x34a0 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x174 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x5b Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xe38 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x35b Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x13b Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0xc5 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x21e Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x236 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x10e Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x567 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x1e9 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x287 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x5cc Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x12 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x287 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x170 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x492 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x0000000000000000 0x58 Core/Src/stm32l1xx_hal_msp.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .group 0x0000000000000000 0xc Core/Src/stm32l1xx_it.o - .text 0x0000000000000000 0x0 Core/Src/stm32l1xx_it.o - .data 0x0000000000000000 0x0 Core/Src/stm32l1xx_it.o - .bss 0x0000000000000000 0x0 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x112 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x2e Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x8e Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x51 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xef Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x6a Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x1df Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x1c Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xc3 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xe49 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x11f Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xb52b Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x43 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x34a0 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x174 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x5b Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xe38 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x35b Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x13b Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0xc5 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x21e Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x236 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x10e Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x567 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x1e9 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x22 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x287 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x5cc Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x12 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x287 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x170 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x492 Core/Src/stm32l1xx_it.o - .debug_macro 0x0000000000000000 0x58 Core/Src/stm32l1xx_it.o + 0x0000000000000000 0x3c Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x294 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x102d Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xb850 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x3659 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x9fe Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xf8 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x15f Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x287 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x5f Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x132 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x264 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x11a Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x85 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x89 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x31a Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x405 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xe4 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x287 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x126 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc Core/Src/stm32f4xx_it.o + .text 0x0000000000000000 0x0 Core/Src/stm32f4xx_it.o + .data 0x0000000000000000 0x0 Core/Src/stm32f4xx_it.o + .bss 0x0000000000000000 0x0 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x294 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x28 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x8e Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x51 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xef Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x6a Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x1df Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x1c Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x22 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xdf Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x102d Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x11f Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xb850 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x43 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x3659 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x174 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x5a Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x416 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x9fe Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x117 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xf8 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x27 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x15f Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x287 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x5f Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x236 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x132 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x264 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x2e Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x11a Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x85 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x89 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x31a Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x405 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xe4 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x287 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x126 Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x58 Core/Src/stm32f4xx_it.o .group 0x0000000000000000 0xc Core/Src/syscalls.o .group 0x0000000000000000 0xc Core/Src/syscalls.o .group 0x0000000000000000 0xc Core/Src/syscalls.o @@ -288,21 +369,21 @@ Discarded input sections .bss.__env 0x0000000000000000 0x4 Core/Src/syscalls.o .data.environ 0x0000000000000000 0x4 Core/Src/syscalls.o .text.initialise_monitor_handles - 0x0000000000000000 0xc Core/Src/syscalls.o - .text._getpid 0x0000000000000000 0xe Core/Src/syscalls.o + 0x0000000000000000 0xe Core/Src/syscalls.o + .text._getpid 0x0000000000000000 0x10 Core/Src/syscalls.o .text._kill 0x0000000000000000 0x20 Core/Src/syscalls.o .text._exit 0x0000000000000000 0x14 Core/Src/syscalls.o .text._read 0x0000000000000000 0x3a Core/Src/syscalls.o .text._write 0x0000000000000000 0x38 Core/Src/syscalls.o - .text._close 0x0000000000000000 0x16 Core/Src/syscalls.o - .text._fstat 0x0000000000000000 0x1e Core/Src/syscalls.o - .text._isatty 0x0000000000000000 0x14 Core/Src/syscalls.o - .text._lseek 0x0000000000000000 0x18 Core/Src/syscalls.o - .text._open 0x0000000000000000 0x1a Core/Src/syscalls.o + .text._close 0x0000000000000000 0x18 Core/Src/syscalls.o + .text._fstat 0x0000000000000000 0x20 Core/Src/syscalls.o + .text._isatty 0x0000000000000000 0x16 Core/Src/syscalls.o + .text._lseek 0x0000000000000000 0x1a Core/Src/syscalls.o + .text._open 0x0000000000000000 0x1c Core/Src/syscalls.o .text._wait 0x0000000000000000 0x1e Core/Src/syscalls.o .text._unlink 0x0000000000000000 0x1e Core/Src/syscalls.o - .text._times 0x0000000000000000 0x16 Core/Src/syscalls.o - .text._stat 0x0000000000000000 0x1e Core/Src/syscalls.o + .text._times 0x0000000000000000 0x18 Core/Src/syscalls.o + .text._stat 0x0000000000000000 0x20 Core/Src/syscalls.o .text._link 0x0000000000000000 0x20 Core/Src/syscalls.o .text._fork 0x0000000000000000 0x16 Core/Src/syscalls.o .text._execve 0x0000000000000000 0x22 Core/Src/syscalls.o @@ -357,11 +438,11 @@ Discarded input sections .debug_macro 0x0000000000000000 0x16 Core/Src/syscalls.o .debug_macro 0x0000000000000000 0x88 Core/Src/syscalls.o .debug_line 0x0000000000000000 0x73e Core/Src/syscalls.o - .debug_str 0x0000000000000000 0x887e Core/Src/syscalls.o + .debug_str 0x0000000000000000 0x8890 Core/Src/syscalls.o .comment 0x0000000000000000 0x7c Core/Src/syscalls.o .debug_frame 0x0000000000000000 0x2ac Core/Src/syscalls.o .ARM.attributes - 0x0000000000000000 0x33 Core/Src/syscalls.o + 0x0000000000000000 0x39 Core/Src/syscalls.o .group 0x0000000000000000 0xc Core/Src/sysmem.o .group 0x0000000000000000 0xc Core/Src/sysmem.o .group 0x0000000000000000 0xc Core/Src/sysmem.o @@ -413,2474 +494,2917 @@ Discarded input sections .debug_macro 0x0000000000000000 0x6a Core/Src/sysmem.o .debug_macro 0x0000000000000000 0x1df Core/Src/sysmem.o .debug_line 0x0000000000000000 0x4c7 Core/Src/sysmem.o - .debug_str 0x0000000000000000 0x5f4c Core/Src/sysmem.o + .debug_str 0x0000000000000000 0x5f5e Core/Src/sysmem.o .comment 0x0000000000000000 0x7c Core/Src/sysmem.o .debug_frame 0x0000000000000000 0x34 Core/Src/sysmem.o .ARM.attributes - 0x0000000000000000 0x33 Core/Src/sysmem.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .group 0x0000000000000000 0xc Core/Src/system_stm32l1xx.o - .text 0x0000000000000000 0x0 Core/Src/system_stm32l1xx.o - .data 0x0000000000000000 0x0 Core/Src/system_stm32l1xx.o - .bss 0x0000000000000000 0x0 Core/Src/system_stm32l1xx.o + 0x0000000000000000 0x39 Core/Src/sysmem.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc Core/Src/system_stm32f4xx.o + .text 0x0000000000000000 0x0 Core/Src/system_stm32f4xx.o + .data 0x0000000000000000 0x0 Core/Src/system_stm32f4xx.o + .bss 0x0000000000000000 0x0 Core/Src/system_stm32f4xx.o .text.SystemCoreClockUpdate - 0x0000000000000000 0x154 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xa5a Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x2e Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x8e Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x51 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xef Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x6a Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x1df Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x1c Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xc3 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xe49 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x11f Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xb52b Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x43 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x112 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x34a0 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x174 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x5b Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xe38 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x35b Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x13b Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0xc5 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x21e Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x236 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x10e Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x567 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x1e9 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x287 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x5cc Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x12 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x287 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x170 Core/Src/system_stm32l1xx.o - .debug_macro 0x0000000000000000 0x492 Core/Src/system_stm32l1xx.o - .text 0x0000000000000000 0x14 Core/Startup/startup_stm32l152retx.o - .data 0x0000000000000000 0x0 Core/Startup/startup_stm32l152retx.o - .bss 0x0000000000000000 0x0 Core/Startup/startup_stm32l152retx.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0xf4 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xa5a Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x2e Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x28 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x8e Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x51 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xef Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x6a Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x1df Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x1c Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x22 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xdf Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x102d Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x11f Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xb850 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x43 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x294 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x3659 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x174 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x5a Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x416 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x9fe Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x117 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xf8 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x27 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x15f Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x287 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x5f Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x236 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x132 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x264 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x2e Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x11a Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x85 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x89 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x31a Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x405 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xe4 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x287 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x126 Core/Src/system_stm32f4xx.o + .text 0x0000000000000000 0x14 Core/Startup/startup_stm32f401retx.o + .data 0x0000000000000000 0x0 Core/Startup/startup_stm32f401retx.o + .bss 0x0000000000000000 0x0 Core/Startup/startup_stm32f401retx.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DeInit - 0x0000000000000000 0x3c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x58 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_MspInit - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0xe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_MspDeInit - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0xe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_GetTickPrio - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_SetTickFreq - 0x0000000000000000 0x50 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x50 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_GetTickFreq - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text.HAL_SuspendTick - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text.HAL_ResumeTick - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_GetHalVersion - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_GetREVID - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_GetDEVID - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text.HAL_GetUIDw0 - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text.HAL_GetUIDw1 - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .text.HAL_GetUIDw2 - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DBGMCU_EnableDBGSleepMode - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DBGMCU_DisableDBGSleepMode - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DBGMCU_EnableDBGStopMode - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DBGMCU_DisableDBGStopMode - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DBGMCU_EnableDBGStandbyMode - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text.HAL_DBGMCU_DisableDBGStandbyMode - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .text.__NVIC_EnableIRQ - 0x0000000000000000 0x38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .text.HAL_EnableCompensationCell + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .text.HAL_DisableCompensationCell + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .text.HAL_GetUIDw0 + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .text.HAL_GetUIDw1 + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .text.HAL_GetUIDw2 + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_DisableIRQ - 0x0000000000000000 0x44 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_GetPendingIRQ - 0x0000000000000000 0x40 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_SetPendingIRQ - 0x0000000000000000 0x3c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_ClearPendingIRQ - 0x0000000000000000 0x3c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_GetActive - 0x0000000000000000 0x40 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_GetPriority - 0x0000000000000000 0x4c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x50 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.NVIC_DecodePriority - 0x0000000000000000 0x6c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x6e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_SystemReset - 0x0000000000000000 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .text.HAL_NVIC_EnableIRQ - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_DisableIRQ - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_SystemReset - 0x0000000000000000 0x8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .text.HAL_MPU_Enable - 0x0000000000000000 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_MPU_Disable - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x2c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .text.HAL_MPU_Enable + 0x0000000000000000 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_MPU_ConfigRegion - 0x0000000000000000 0x88 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x88 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_GetPriorityGrouping - 0x0000000000000000 0xe Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0xe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_GetPriority - 0x0000000000000000 0x2c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x2c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_SetPendingIRQ - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_GetPendingIRQ - 0x0000000000000000 0x1e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x1e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_ClearPendingIRQ - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_GetActive - 0x0000000000000000 0x1e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x1e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_SYSTICK_CLKSourceConfig - 0x0000000000000000 0x38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0x38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_SYSTICK_IRQHandler - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_SYSTICK_Callback - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0xe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Init - 0x0000000000000000 0xe8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x15c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_DeInit - 0x0000000000000000 0xdc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0xbc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Start - 0x0000000000000000 0x86 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x76 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Start_IT - 0x0000000000000000 0xc0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0xb0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Abort - 0x0000000000000000 0x7a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0xe0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_Abort_IT - 0x0000000000000000 0x82 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_PollForTransfer - 0x0000000000000000 0x14e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x1be Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_IRQHandler - 0x0000000000000000 0x15e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x314 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_RegisterCallback - 0x0000000000000000 0x90 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0xa8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_UnRegisterCallback - 0x0000000000000000 0xb0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0xd4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_GetState - 0x0000000000000000 0x1a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.HAL_DMA_GetError - 0x0000000000000000 0x16 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text.DMA_SetConfig - 0x0000000000000000 0x5e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_info 0x0000000000000000 0x798 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_abbrev 0x0000000000000000 0x1f5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x5c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .text.DMA_CalcBaseAndBitshift + 0x0000000000000000 0x6c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .text.DMA_CheckFifoParam + 0x0000000000000000 0xf4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .rodata.flagBitshiftOffset.7666 + 0x0000000000000000 0x8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_info 0x0000000000000000 0x960 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_abbrev 0x0000000000000000 0x1f1 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_aranges - 0x0000000000000000 0x80 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_ranges 0x0000000000000000 0x70 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_line 0x0000000000000000 0x8b6 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_str 0x0000000000000000 0x83cd3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .debug_frame 0x0000000000000000 0x204 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o + 0x0000000000000000 0x90 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_ranges 0x0000000000000000 0x80 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1d9 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_line 0x0000000000000000 0x994 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_str 0x0000000000000000 0x83e7f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_frame 0x0000000000000000 0x250 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .text.HAL_DMAEx_MultiBufferStart + 0x0000000000000000 0x96 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .text.HAL_DMAEx_MultiBufferStart_IT + 0x0000000000000000 0x1290 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .text.HAL_DMAEx_ChangeMemory + 0x0000000000000000 0x34 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .text.DMA_MultiBufferSetConfig + 0x0000000000000000 0x4c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_info 0x0000000000000000 0x5c5 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_abbrev 0x0000000000000000 0x187 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_aranges + 0x0000000000000000 0x38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_ranges 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_line 0x0000000000000000 0x125d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_str 0x0000000000000000 0x83c67 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_frame 0x0000000000000000 0xac Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .ARM.attributes + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_SetConfigLine - 0x0000000000000000 0x14c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x150 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_GetConfigLine - 0x0000000000000000 0x104 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x104 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_ClearConfigLine - 0x0000000000000000 0xc0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0xc0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_RegisterCallback - 0x0000000000000000 0x32 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x34 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_GetHandle - 0x0000000000000000 0x26 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_IRQHandler - 0x0000000000000000 0x48 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_GetPending - 0x0000000000000000 0x40 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x40 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_ClearPending - 0x0000000000000000 0x30 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text.HAL_EXTI_GenerateSWI - 0x0000000000000000 0x2c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_info 0x0000000000000000 0x5b1 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_abbrev 0x0000000000000000 0x1bc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_info 0x0000000000000000 0x5e1 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_abbrev 0x0000000000000000 0x1cb Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_aranges - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_ranges 0x0000000000000000 0x50 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_line 0x0000000000000000 0x7a4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_str 0x0000000000000000 0x83a90 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .debug_frame 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o + 0x0000000000000000 0x60 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_ranges 0x0000000000000000 0x50 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_line 0x0000000000000000 0x7be Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_str 0x0000000000000000 0x83aff Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_frame 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_Program - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0xa8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_Program_IT - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x9c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_IRQHandler - 0x0000000000000000 0x160 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x140 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_EndOfOperationCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_OperationErrorCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_Unlock - 0x0000000000000000 0x74 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_Lock - 0x0000000000000000 0x20 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_OB_Unlock - 0x0000000000000000 0x74 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_OB_Lock - 0x0000000000000000 0x20 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_OB_Launch - 0x0000000000000000 0x24 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.HAL_FLASH_GetError - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.FLASH_WaitForLastOperation - 0x0000000000000000 0xa0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0x80 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .text.FLASH_Program_DoubleWord + 0x0000000000000000 0x60 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .text.FLASH_Program_Word + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .text.FLASH_Program_HalfWord + 0x0000000000000000 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .text.FLASH_Program_Byte + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text.FLASH_SetErrorCode - 0x0000000000000000 0xac Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_info 0x0000000000000000 0x51e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_abbrev 0x0000000000000000 0x209 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0xcc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_info 0x0000000000000000 0x61d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_abbrev 0x0000000000000000 0x24a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_aranges - 0x0000000000000000 0x80 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_ranges 0x0000000000000000 0x70 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x1b5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_line 0x0000000000000000 0x849 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_str 0x0000000000000000 0x83b3d Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .debug_frame 0x0000000000000000 0x1d8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o + 0x0000000000000000 0xa0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_ranges 0x0000000000000000 0x90 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1d9 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_line 0x0000000000000000 0x8ad Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_str 0x0000000000000000 0x83c40 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_frame 0x0000000000000000 0x274 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - COMMON 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + COMMON 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.HAL_FLASHEx_Erase - 0x0000000000000000 0xb0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0xe0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.HAL_FLASHEx_Erase_IT - 0x0000000000000000 0x84 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0xac Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.HAL_FLASHEx_OBProgram - 0x0000000000000000 0x108 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0xdc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.HAL_FLASHEx_OBGetConfig - 0x0000000000000000 0x64 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0x46 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.HAL_FLASHEx_AdvOBProgram - 0x0000000000000000 0x32 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.HAL_FLASHEx_AdvOBGetConfig - 0x0000000000000000 0x3c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.HAL_FLASHEx_DATAEEPROM_Unlock - 0x0000000000000000 0x38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.HAL_FLASHEx_DATAEEPROM_Lock - 0x0000000000000000 0x20 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.HAL_FLASHEx_DATAEEPROM_Erase - 0x0000000000000000 0x64 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.HAL_FLASHEx_DATAEEPROM_Program - 0x0000000000000000 0xdc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_RDPConfig - 0x0000000000000000 0x88 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_BORConfig - 0x0000000000000000 0x78 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_GetUser - 0x0000000000000000 0x20 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_GetRDP - 0x0000000000000000 0x2c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_GetBOR - 0x0000000000000000 0x20 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_WRPConfig - 0x0000000000000000 0x9c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_WRPConfigWRP1OrPCROP1 - 0x0000000000000000 0xc4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_WRPConfigWRP2OrPCROP2 - 0x0000000000000000 0xc4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_WRPConfigWRP3 - 0x0000000000000000 0xc4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_WRPConfigWRP4 - 0x0000000000000000 0xd4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0x24 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.HAL_FLASHEx_OB_SelectPCROP + 0x0000000000000000 0x34 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.HAL_FLASHEx_OB_DeSelectPCROP + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_MassErase + 0x0000000000000000 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_Erase_Sector + 0x0000000000000000 0x90 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_EnableWRP + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_DisableWRP + 0x0000000000000000 0x40 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_EnablePCROP + 0x0000000000000000 0x40 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_DisablePCROP + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_RDP_LevelConfig + 0x0000000000000000 0x34 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text.FLASH_OB_UserConfig - 0x0000000000000000 0x9c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_OB_BootConfig - 0x0000000000000000 0x78 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_DATAEEPROM_FastProgramByte - 0x0000000000000000 0x50 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_DATAEEPROM_FastProgramHalfWord - 0x0000000000000000 0x50 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_DATAEEPROM_FastProgramWord - 0x0000000000000000 0x4c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_DATAEEPROM_ProgramByte - 0x0000000000000000 0x3e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_DATAEEPROM_ProgramHalfWord - 0x0000000000000000 0x3e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_DATAEEPROM_ProgramWord - 0x0000000000000000 0x3c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .text.FLASH_PageErase - 0x0000000000000000 0x44 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_info 0x0000000000000000 0xd25 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_abbrev 0x0000000000000000 0x249 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0x60 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_BOR_LevelConfig + 0x0000000000000000 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_GetUser + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_GetWRP + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_GetRDP + 0x0000000000000000 0x40 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_OB_GetBOR + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .text.FLASH_FlushCaches + 0x0000000000000000 0x8c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_info 0x0000000000000000 0x87f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_abbrev 0x0000000000000000 0x23e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_aranges - 0x0000000000000000 0x110 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_ranges 0x0000000000000000 0x100 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_line 0x0000000000000000 0xa73 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_str 0x0000000000000000 0x83f88 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .debug_frame 0x0000000000000000 0x470 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o + 0x0000000000000000 0xc8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_ranges 0x0000000000000000 0xb8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1d9 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0x91d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0x83d79 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_frame 0x0000000000000000 0x334 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .RamFunc 0x0000000000000000 0x524 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_info 0x0000000000000000 0x725 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_abbrev 0x0000000000000000 0x288 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_info 0x0000000000000000 0x169 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_abbrev 0x0000000000000000 0x92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_aranges - 0x0000000000000000 0x68 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_ranges 0x0000000000000000 0x58 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_line 0x0000000000000000 0x7eb Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_str 0x0000000000000000 0x83be2 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .debug_frame 0x0000000000000000 0x17c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_line 0x0000000000000000 0x6c6 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_str 0x0000000000000000 0x838ec Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_DeInit - 0x0000000000000000 0x1e0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000000 0x1c4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_ReadPin - 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_TogglePin - 0x0000000000000000 0x32 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000000 0x36 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_LockPin - 0x0000000000000000 0x4e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000000 0x50 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_EXTI_IRQHandler - 0x0000000000000000 0x30 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text.HAL_GPIO_EXTI_Callback - 0x0000000000000000 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x16 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_DeInit - 0x0000000000000000 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x2c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_EnableBkUpAccess - 0x0000000000000000 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_DisableBkUpAccess - 0x0000000000000000 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_ConfigPVD - 0x0000000000000000 0xbc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0xc0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_EnablePVD - 0x0000000000000000 0x34 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_DisablePVD - 0x0000000000000000 0x34 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_EnableWakeUpPin - 0x0000000000000000 0x38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x24 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_DisableWakeUpPin - 0x0000000000000000 0x38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .text.HAL_PWR_EnterSLEEPMode - 0x0000000000000000 0x4c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_EnterSTOPMode - 0x0000000000000000 0x58 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x58 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_EnterSTANDBYMode - 0x0000000000000000 0x30 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .text.HAL_PWR_EnableSleepOnExit - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .text.HAL_PWR_DisableSleepOnExit - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .text.HAL_PWR_EnableSEVOnPend - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .text.HAL_PWR_DisableSEVOnPend - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_PVD_IRQHandler - 0x0000000000000000 0x24 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o + 0x0000000000000000 0x24 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text.HAL_PWR_PVDCallback - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_info 0x0000000000000000 0x7b5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_abbrev 0x0000000000000000 0x1eb Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_aranges - 0x0000000000000000 0xa0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_ranges 0x0000000000000000 0x90 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x1cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_line 0x0000000000000000 0x847 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_str 0x0000000000000000 0x83bdc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .debug_frame 0x0000000000000000 0x274 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o + 0x0000000000000000 0xe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .text.HAL_PWR_EnableSleepOnExit + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .text.HAL_PWR_DisableSleepOnExit + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .text.HAL_PWR_EnableSEVOnPend + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .text.HAL_PWR_DisableSEVOnPend + 0x0000000000000000 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableBkUpReg + 0x0000000000000000 0x4c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableBkUpReg + 0x0000000000000000 0x4c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableFlashPowerDown + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableFlashPowerDown + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .text.HAL_PWREx_GetVoltageRange - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text.HAL_PWREx_EnableFastWakeUp - 0x0000000000000000 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text.HAL_PWREx_DisableFastWakeUp - 0x0000000000000000 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text.HAL_PWREx_EnableUltraLowPower - 0x0000000000000000 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text.HAL_PWREx_DisableUltraLowPower - 0x0000000000000000 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text.HAL_PWREx_EnableLowPowerRunMode - 0x0000000000000000 0x5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .text.HAL_PWREx_DisableLowPowerRunMode - 0x0000000000000000 0x5c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_info 0x0000000000000000 0x3f8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_abbrev 0x0000000000000000 0x175 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_ControlVoltageScaling + 0x0000000000000000 0xf4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableMainRegulatorLowVoltage + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableMainRegulatorLowVoltage + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_EnableLowRegulatorLowVoltage + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .text.HAL_PWREx_DisableLowRegulatorLowVoltage + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_info 0x0000000000000000 0x514 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_abbrev 0x0000000000000000 0x1b4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_aranges - 0x0000000000000000 0x50 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_ranges 0x0000000000000000 0x40 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_line 0x0000000000000000 0x796 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_str 0x0000000000000000 0x839bb Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .debug_frame 0x0000000000000000 0x120 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o + 0x0000000000000000 0x68 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_ranges 0x0000000000000000 0x58 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1eb Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_line 0x0000000000000000 0x79d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_str 0x0000000000000000 0x83c38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_frame 0x0000000000000000 0x15c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_DeInit - 0x0000000000000000 0x114 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x10 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_MCOConfig - 0x0000000000000000 0x6c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0xd0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_EnableCSS - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_DisableCSS - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_GetOscConfig - 0x0000000000000000 0x138 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x128 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_GetClockConfig - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x64 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_NMI_IRQHandler - 0x0000000000000000 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text.HAL_RCC_CSSCallback - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o + 0x0000000000000000 0xe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .text.HAL_RCCEx_GetPeriphCLKConfig - 0x0000000000000000 0x5c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o + 0x0000000000000000 0x74 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .text.HAL_RCCEx_GetPeriphCLKFreq - 0x0000000000000000 0xd0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .text.HAL_RCCEx_EnableLSECSS - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .text.HAL_RCCEx_DisableLSECSS - 0x0000000000000000 0x2c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .text.HAL_RCCEx_EnableLSECSS_IT - 0x0000000000000000 0x48 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .text.HAL_RCCEx_LSECSS_IRQHandler - 0x0000000000000000 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .text.HAL_RCCEx_LSECSS_Callback - 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0xb8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .text.HAL_RCCEx_EnablePLLI2S + 0x0000000000000000 0x88 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .text.HAL_RCCEx_DisablePLLI2S + 0x0000000000000000 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .text.HAL_RCC_DeInit + 0x0000000000000000 0x19c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_DeInit - 0x0000000000000000 0x144 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x158 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_MspInit - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_MspDeInit - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_SetAlarm - 0x0000000000000000 0x228 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .text.HAL_RTC_SetAlarm_IT - 0x0000000000000000 0x270 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x230 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_DeactivateAlarm - 0x0000000000000000 0x116 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_GetAlarm - 0x0000000000000000 0x116 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .text.HAL_RTC_AlarmIRQHandler - 0x0000000000000000 0x8c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x11e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_AlarmAEventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_PollForAlarmAEvent - 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000000 0x6e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .text.HAL_RTC_GetState - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x1a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetTimeStamp - 0x0000000000000000 0x82 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xaa Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetTimeStamp_IT - 0x0000000000000000 0xb0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xe8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DeactivateTimeStamp - 0x0000000000000000 0x78 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x7e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_GetTimeStamp - 0x0000000000000000 0x13a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x140 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetTamper - 0x0000000000000000 0xb2 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xb6 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetTamper_IT - 0x0000000000000000 0xe0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x110 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DeactivateTamper - 0x0000000000000000 0x4c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x4e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_TamperTimeStampIRQHandler - 0x0000000000000000 0xf8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xc0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_TimeStampEventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_Tamper1EventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_Tamper2EventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .text.HAL_RTCEx_Tamper3EventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_PollForTimeStampEvent - 0x0000000000000000 0x82 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x86 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_PollForTamper1Event - 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x6e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_PollForTamper2Event - 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .text.HAL_RTCEx_PollForTamper3Event - 0x0000000000000000 0x70 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x6e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetWakeUpTimer - 0x0000000000000000 0x124 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x128 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetWakeUpTimer_IT - 0x0000000000000000 0x164 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x180 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DeactivateWakeUpTimer - 0x0000000000000000 0xac Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xb0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_GetWakeUpTimer - 0x0000000000000000 0x1a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_WakeUpTimerIRQHandler - 0x0000000000000000 0x48 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_WakeUpTimerEventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_PollForWakeUpTimerEvent - 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x6e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_BKUPWrite - 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x34 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_BKUPRead - 0x0000000000000000 0x2a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetCoarseCalib - 0x0000000000000000 0xa2 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xa2 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DeactivateCoarseCalib - 0x0000000000000000 0x92 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetSmoothCalib - 0x0000000000000000 0xb2 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xb6 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetSynchroShift - 0x0000000000000000 0xe6 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetCalibrationOutPut - 0x0000000000000000 0x82 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x84 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DeactivateCalibrationOutPut - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x62 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_SetRefClock - 0x0000000000000000 0x92 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DeactivateRefClock - 0x0000000000000000 0x92 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_EnableBypassShadow - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x62 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_DisableBypassShadow - 0x0000000000000000 0x60 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .text.HAL_RTCEx_AlarmBEventCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x62 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .text.HAL_RTCEx_PollForAlarmBEvent - 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_info 0x0000000000000000 0xfc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_abbrev 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x6e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_info 0x0000000000000000 0x169 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_abbrev 0x0000000000000000 0x92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_aranges - 0x0000000000000000 0x140 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_ranges 0x0000000000000000 0x130 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_line 0x0000000000000000 0xd96 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_str 0x0000000000000000 0x8416a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .debug_frame 0x0000000000000000 0x590 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1d4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_line 0x0000000000000000 0x6bc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_str 0x0000000000000000 0x838e2 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_info 0x0000000000000000 0x15b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_abbrev 0x0000000000000000 0x78 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_info 0x0000000000000000 0x169 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_abbrev 0x0000000000000000 0x92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_aranges - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x1b5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_line 0x0000000000000000 0x6a2 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .debug_str 0x0000000000000000 0x83882 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_line 0x0000000000000000 0x6bf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_str 0x0000000000000000 0x838e5 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .comment 0x0000000000000000 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_info 0x0000000000000000 0x15b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_abbrev 0x0000000000000000 0x78 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_aranges - 0x0000000000000000 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_line 0x0000000000000000 0x6a5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .debug_str 0x0000000000000000 0x83885 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .comment 0x0000000000000000 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .ARM.attributes - 0x0000000000000000 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .group 0x0000000000000000 0xc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .text 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .data 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .bss 0x0000000000000000 0x0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .data 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .bss 0x0000000000000000 0x0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_HalfDuplex_Init - 0x0000000000000000 0xaa Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xaa Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_LIN_Init - 0x0000000000000000 0xcc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xcc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_MultiProcessor_Init - 0x0000000000000000 0xe0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xe0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_DeInit - 0x0000000000000000 0x58 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x58 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_MspInit - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_MspDeInit - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .text.HAL_UART_Transmit - 0x0000000000000000 0x132 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Receive - 0x0000000000000000 0x14c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Transmit_IT - 0x0000000000000000 0x88 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x8a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Receive_IT - 0x0000000000000000 0xa8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xaa Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Transmit_DMA - 0x0000000000000000 0xd8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xd8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Receive_DMA - 0x0000000000000000 0x100 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x100 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_DMAPause - 0x0000000000000000 0xc6 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xc8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_DMAResume - 0x0000000000000000 0xa0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xa2 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_DMAStop - 0x0000000000000000 0xb6 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xb6 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Abort - 0x0000000000000000 0x104 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x104 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortTransmit - 0x0000000000000000 0x88 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x88 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortReceive - 0x0000000000000000 0x98 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x98 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_Abort_IT - 0x0000000000000000 0x148 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x148 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortTransmit_IT - 0x0000000000000000 0xa0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xa0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortReceive_IT - 0x0000000000000000 0xb0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xb0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_IRQHandler - 0x0000000000000000 0x200 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x200 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_TxCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_TxHalfCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_RxCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_RxHalfCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_ErrorCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortTransmitCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_AbortReceiveCpltCallback - 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_LIN_SendBreak - 0x0000000000000000 0x52 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x54 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_MultiProcessor_EnterMuteMode - 0x0000000000000000 0x52 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x54 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_MultiProcessor_ExitMuteMode - 0x0000000000000000 0x52 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x54 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_HalfDuplex_EnableTransmitter - 0x0000000000000000 0x66 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x68 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_HalfDuplex_EnableReceiver - 0x0000000000000000 0x66 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x68 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_GetState - 0x0000000000000000 0x3a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.HAL_UART_GetError - 0x0000000000000000 0x16 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMATransmitCplt - 0x0000000000000000 0x52 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x52 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMATxHalfCplt - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMAReceiveCplt - 0x0000000000000000 0x68 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x68 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMARxHalfCplt - 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMAError - 0x0000000000000000 0x94 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .text.UART_WaitOnFlagUntilTimeout - 0x0000000000000000 0x94 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x94 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_EndTxTransfer - 0x0000000000000000 0x2a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x2c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_EndRxTransfer - 0x0000000000000000 0x3a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMAAbortOnError - 0x0000000000000000 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMATxAbortCallback - 0x0000000000000000 0x5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMARxAbortCallback - 0x0000000000000000 0x5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMATxOnlyAbortCallback - 0x0000000000000000 0x2a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x2a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_DMARxOnlyAbortCallback - 0x0000000000000000 0x2a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x2a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_Transmit_IT - 0x0000000000000000 0xaa Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0xac Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_EndTransmit_IT - 0x0000000000000000 0x30 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000000 0x30 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_Receive_IT - 0x0000000000000000 0x102 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xa5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x112 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x2e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x8e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x51 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xef Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x6a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x1df Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xc3 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xe49 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x11f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xb52b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x43 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x34a0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x174 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x5b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xe38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x35b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x13b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0xc5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x21e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x236 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x10e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x567 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x1e9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x22 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x5cc Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x12 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x287 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x170 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_macro 0x0000000000000000 0x492 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) - .text.__errno 0x0000000000000000 0xc c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) - .debug_frame 0x0000000000000000 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) + 0x0000000000000000 0x102 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xa5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x294 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x8e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x51 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xef Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x6a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1df Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x22 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xdf Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x102d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x11f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xb850 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x43 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x3659 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x174 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x5a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x416 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x9fe Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x117 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xf8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x27 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x15f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x5f Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x236 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x264 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x11a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x85 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x89 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x31a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x405 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xe4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x287 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x126 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) + .text.exit 0x0000000000000000 0x28 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) + .debug_frame 0x0000000000000000 0x28 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) .ARM.attributes - 0x0000000000000000 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-errno.o) - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - .text.exit 0x0000000000000000 0x28 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - .debug_frame 0x0000000000000000 0x28 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - .ARM.attributes - 0x0000000000000000 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-exit.o) - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) - .data._impure_ptr - 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) - .data.impure_data - 0x0000000000000000 0x60 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) + 0x0000000000000000 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-exit.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) .rodata._global_impure_ptr - 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) + 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-strlen.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-strlen.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_lib_ver.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_lib_ver.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_lib_ver.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_addsubdf3.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_addsubdf3.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_muldivdf3.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_muldivdf3.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_cmpdf2.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_cmpdf2.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_unorddf2.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_unorddf2.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_fixdfsi.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_fixdfsi.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + .ARM.extab 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_dvmd_tls.o) + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_dvmd_tls.o) + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .eh_frame 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o .ARM.attributes - 0x0000000000000000 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-impure.o) - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) - .ARM.extab 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_dvmd_tls.o) - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_dvmd_tls.o) - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtend.o - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtend.o - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtend.o - .eh_frame 0x0000000000000000 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtend.o - .ARM.attributes - 0x0000000000000000 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtend.o - .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o - .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o - .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o + 0x0000000000000000 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o + .text 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + .data 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + .bss 0x0000000000000000 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o Memory Configuration Name Origin Length Attributes -RAM 0x0000000020000000 0x0000000000014000 xrw +RAM 0x0000000020000000 0x0000000000018000 xrw FLASH 0x0000000008000000 0x0000000000080000 xr *default* 0x0000000000000000 0xffffffffffffffff Linker script and memory map -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m/crt0.o +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard/crt0.o LOAD Core/Src/main.o -LOAD Core/Src/stm32l1xx_hal_msp.o -LOAD Core/Src/stm32l1xx_it.o +LOAD Core/Src/stm32f4xx_hal_msp.o +LOAD Core/Src/stm32f4xx_it.o LOAD Core/Src/syscalls.o LOAD Core/Src/sysmem.o -LOAD Core/Src/system_stm32l1xx.o -LOAD Core/Startup/startup_stm32l152retx.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o -LOAD Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o +LOAD Core/Src/system_stm32f4xx.o +LOAD Core/Startup/startup_stm32f401retx.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o +LOAD Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o START GROUP -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libm.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a END GROUP START GROUP -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a END GROUP START GROUP -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libnosys.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libnosys.a END GROUP START GROUP -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libnosys.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libnosys.a END GROUP -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtend.o -LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o - 0x0000000020014000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtend.o +LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + 0x0000000020018000 _estack = (ORIGIN (RAM) + LENGTH (RAM)) 0x0000000000000200 _Min_Heap_Size = 0x200 0x0000000000000400 _Min_Stack_Size = 0x400 -.isr_vector 0x0000000008000000 0x13c +.isr_vector 0x0000000008000000 0x194 0x0000000008000000 . = ALIGN (0x4) *(.isr_vector) - .isr_vector 0x0000000008000000 0x13c Core/Startup/startup_stm32l152retx.o + .isr_vector 0x0000000008000000 0x194 Core/Startup/startup_stm32f401retx.o 0x0000000008000000 g_pfnVectors - 0x000000000800013c . = ALIGN (0x4) + 0x0000000008000194 . = ALIGN (0x4) -.text 0x000000000800013c 0x24a8 - 0x000000000800013c . = ALIGN (0x4) +.text 0x0000000008000198 0x5de4 + 0x0000000008000198 . = ALIGN (0x4) *(.text) - .text 0x000000000800013c 0x40 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o - .text 0x000000000800017c 0x30 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) - 0x000000000800017c __aeabi_uldivmod - .text 0x00000000080001ac 0x2d0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) - 0x00000000080001ac __udivmoddi4 - .text 0x000000000800047c 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_dvmd_tls.o) - 0x000000000800047c __aeabi_idiv0 - 0x000000000800047c __aeabi_ldiv0 + .text 0x0000000008000198 0x40 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + .text 0x00000000080001d8 0x10 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-strlen.o) + 0x00000000080001d8 strlen + .text 0x00000000080001e8 0x378 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_addsubdf3.o) + 0x00000000080001e8 __aeabi_drsub + 0x00000000080001f0 __aeabi_dsub + 0x00000000080001f0 __subdf3 + 0x00000000080001f4 __aeabi_dadd + 0x00000000080001f4 __adddf3 + 0x000000000800046c __floatunsidf + 0x000000000800046c __aeabi_ui2d + 0x000000000800048c __floatsidf + 0x000000000800048c __aeabi_i2d + 0x00000000080004b0 __aeabi_f2d + 0x00000000080004b0 __extendsfdf2 + 0x00000000080004f4 __floatundidf + 0x00000000080004f4 __aeabi_ul2d + 0x0000000008000504 __floatdidf + 0x0000000008000504 __aeabi_l2d + .text 0x0000000008000560 0x424 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_muldivdf3.o) + 0x0000000008000560 __aeabi_dmul + 0x0000000008000560 __muldf3 + 0x00000000080007b4 __divdf3 + 0x00000000080007b4 __aeabi_ddiv + .text 0x0000000008000984 0x110 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_cmpdf2.o) + 0x0000000008000984 __gtdf2 + 0x0000000008000984 __gedf2 + 0x000000000800098c __ltdf2 + 0x000000000800098c __ledf2 + 0x0000000008000994 __nedf2 + 0x0000000008000994 __eqdf2 + 0x0000000008000994 __cmpdf2 + 0x0000000008000a10 __aeabi_cdrcmple + 0x0000000008000a20 __aeabi_cdcmpeq + 0x0000000008000a20 __aeabi_cdcmple + 0x0000000008000a30 __aeabi_dcmpeq + 0x0000000008000a44 __aeabi_dcmplt + 0x0000000008000a58 __aeabi_dcmple + 0x0000000008000a6c __aeabi_dcmpge + 0x0000000008000a80 __aeabi_dcmpgt + .text 0x0000000008000a94 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_unorddf2.o) + 0x0000000008000a94 __unorddf2 + 0x0000000008000a94 __aeabi_dcmpun + .text 0x0000000008000ac0 0x50 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_fixdfsi.o) + 0x0000000008000ac0 __aeabi_d2iz + 0x0000000008000ac0 __fixdfsi + .text 0x0000000008000b10 0x30 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) + 0x0000000008000b10 __aeabi_uldivmod + .text 0x0000000008000b40 0x2cc c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + 0x0000000008000b40 __udivmoddi4 + .text 0x0000000008000e0c 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_dvmd_tls.o) + 0x0000000008000e0c __aeabi_idiv0 + 0x0000000008000e0c __aeabi_ldiv0 *(.text*) - .text.main 0x0000000008000480 0x94 Core/Src/main.o - 0x0000000008000480 main + .text.deg_to_rad + 0x0000000008000e10 0x40 Core/Src/main.o + 0x0000000008000e10 deg_to_rad + .text.rad_to_deg + 0x0000000008000e50 0x40 Core/Src/main.o + 0x0000000008000e50 rad_to_deg + .text.leap_year_check + 0x0000000008000e90 0x60 Core/Src/main.o + 0x0000000008000e90 leap_year_check + .text.calc_day_of_year + 0x0000000008000ef0 0xfc Core/Src/main.o + 0x0000000008000ef0 calc_day_of_year + *fill* 0x0000000008000fec 0x4 + .text.calc_sunrise_sunset + 0x0000000008000ff0 0x710 Core/Src/main.o + 0x0000000008000ff0 calc_sunrise_sunset + .text.calc_tomorrows_date + 0x0000000008001700 0x88 Core/Src/main.o + 0x0000000008001700 calc_tomorrows_date + .text.set_Alarm + 0x0000000008001788 0x80 Core/Src/main.o + 0x0000000008001788 set_Alarm + .text.transmit_uart + 0x0000000008001808 0x2c Core/Src/main.o + 0x0000000008001808 transmit_uart + .text.main 0x0000000008001834 0x1d0 Core/Src/main.o + 0x0000000008001834 main .text.SystemClock_Config - 0x0000000008000514 0xc8 Core/Src/main.o - 0x0000000008000514 SystemClock_Config + 0x0000000008001a04 0x108 Core/Src/main.o + 0x0000000008001a04 SystemClock_Config .text.MX_RTC_Init - 0x00000000080005dc 0xb0 Core/Src/main.o + 0x0000000008001b0c 0xb0 Core/Src/main.o .text.MX_USART2_UART_Init - 0x000000000800068c 0x54 Core/Src/main.o + 0x0000000008001bbc 0x54 Core/Src/main.o .text.MX_GPIO_Init - 0x00000000080006e0 0xd0 Core/Src/main.o + 0x0000000008001c10 0xe0 Core/Src/main.o .text.Error_Handler - 0x00000000080007b0 0xc Core/Src/main.o - 0x00000000080007b0 Error_Handler + 0x0000000008001cf0 0x8 Core/Src/main.o + 0x0000000008001cf0 Error_Handler + .text.HAL_RTC_AlarmAEventCallback + 0x0000000008001cf8 0x1c Core/Src/main.o + 0x0000000008001cf8 HAL_RTC_AlarmAEventCallback .text.HAL_MspInit - 0x00000000080007bc 0x60 Core/Src/stm32l1xx_hal_msp.o - 0x00000000080007bc HAL_MspInit + 0x0000000008001d14 0x50 Core/Src/stm32f4xx_hal_msp.o + 0x0000000008001d14 HAL_MspInit .text.HAL_RTC_MspInit - 0x000000000800081c 0x2c Core/Src/stm32l1xx_hal_msp.o - 0x000000000800081c HAL_RTC_MspInit + 0x0000000008001d64 0x38 Core/Src/stm32f4xx_hal_msp.o + 0x0000000008001d64 HAL_RTC_MspInit .text.HAL_UART_MspInit - 0x0000000008000848 0x88 Core/Src/stm32l1xx_hal_msp.o - 0x0000000008000848 HAL_UART_MspInit + 0x0000000008001d9c 0x90 Core/Src/stm32f4xx_hal_msp.o + 0x0000000008001d9c HAL_UART_MspInit .text.NMI_Handler - 0x00000000080008d0 0xc Core/Src/stm32l1xx_it.o - 0x00000000080008d0 NMI_Handler + 0x0000000008001e2c 0x6 Core/Src/stm32f4xx_it.o + 0x0000000008001e2c NMI_Handler .text.HardFault_Handler - 0x00000000080008dc 0x6 Core/Src/stm32l1xx_it.o - 0x00000000080008dc HardFault_Handler + 0x0000000008001e32 0x6 Core/Src/stm32f4xx_it.o + 0x0000000008001e32 HardFault_Handler .text.MemManage_Handler - 0x00000000080008e2 0x6 Core/Src/stm32l1xx_it.o - 0x00000000080008e2 MemManage_Handler + 0x0000000008001e38 0x6 Core/Src/stm32f4xx_it.o + 0x0000000008001e38 MemManage_Handler .text.BusFault_Handler - 0x00000000080008e8 0x6 Core/Src/stm32l1xx_it.o - 0x00000000080008e8 BusFault_Handler + 0x0000000008001e3e 0x6 Core/Src/stm32f4xx_it.o + 0x0000000008001e3e BusFault_Handler .text.UsageFault_Handler - 0x00000000080008ee 0x6 Core/Src/stm32l1xx_it.o - 0x00000000080008ee UsageFault_Handler + 0x0000000008001e44 0x6 Core/Src/stm32f4xx_it.o + 0x0000000008001e44 UsageFault_Handler .text.SVC_Handler - 0x00000000080008f4 0xc Core/Src/stm32l1xx_it.o - 0x00000000080008f4 SVC_Handler + 0x0000000008001e4a 0xe Core/Src/stm32f4xx_it.o + 0x0000000008001e4a SVC_Handler .text.DebugMon_Handler - 0x0000000008000900 0xc Core/Src/stm32l1xx_it.o - 0x0000000008000900 DebugMon_Handler + 0x0000000008001e58 0xe Core/Src/stm32f4xx_it.o + 0x0000000008001e58 DebugMon_Handler .text.PendSV_Handler - 0x000000000800090c 0xc Core/Src/stm32l1xx_it.o - 0x000000000800090c PendSV_Handler + 0x0000000008001e66 0xe Core/Src/stm32f4xx_it.o + 0x0000000008001e66 PendSV_Handler .text.SysTick_Handler - 0x0000000008000918 0xc Core/Src/stm32l1xx_it.o - 0x0000000008000918 SysTick_Handler + 0x0000000008001e74 0xc Core/Src/stm32f4xx_it.o + 0x0000000008001e74 SysTick_Handler + .text.RTC_Alarm_IRQHandler + 0x0000000008001e80 0x14 Core/Src/stm32f4xx_it.o + 0x0000000008001e80 RTC_Alarm_IRQHandler .text.SystemInit - 0x0000000008000924 0x18 Core/Src/system_stm32l1xx.o - 0x0000000008000924 SystemInit + 0x0000000008001e94 0x2c Core/Src/system_stm32f4xx.o + 0x0000000008001e94 SystemInit .text.Reset_Handler - 0x000000000800093c 0x48 Core/Startup/startup_stm32l152retx.o - 0x000000000800093c Reset_Handler + 0x0000000008001ec0 0x50 Core/Startup/startup_stm32f401retx.o + 0x0000000008001ec0 Reset_Handler .text.Default_Handler - 0x0000000008000984 0x2 Core/Startup/startup_stm32l152retx.o - 0x0000000008000984 RTC_Alarm_IRQHandler - 0x0000000008000984 EXTI2_IRQHandler - 0x0000000008000984 COMP_ACQ_IRQHandler - 0x0000000008000984 TIM10_IRQHandler - 0x0000000008000984 USB_HP_IRQHandler - 0x0000000008000984 TIM6_IRQHandler - 0x0000000008000984 PVD_IRQHandler - 0x0000000008000984 EXTI3_IRQHandler - 0x0000000008000984 EXTI0_IRQHandler - 0x0000000008000984 I2C2_EV_IRQHandler - 0x0000000008000984 SPI1_IRQHandler - 0x0000000008000984 USB_FS_WKUP_IRQHandler - 0x0000000008000984 DMA2_Channel2_IRQHandler - 0x0000000008000984 DMA1_Channel4_IRQHandler - 0x0000000008000984 ADC1_IRQHandler - 0x0000000008000984 USART3_IRQHandler - 0x0000000008000984 DMA1_Channel7_IRQHandler - 0x0000000008000984 LCD_IRQHandler - 0x0000000008000984 UART5_IRQHandler - 0x0000000008000984 TIM4_IRQHandler - 0x0000000008000984 DMA2_Channel1_IRQHandler - 0x0000000008000984 I2C1_EV_IRQHandler - 0x0000000008000984 DMA1_Channel6_IRQHandler - 0x0000000008000984 UART4_IRQHandler - 0x0000000008000984 DMA2_Channel4_IRQHandler - 0x0000000008000984 TIM3_IRQHandler - 0x0000000008000984 RCC_IRQHandler - 0x0000000008000984 DMA1_Channel1_IRQHandler - 0x0000000008000984 Default_Handler - 0x0000000008000984 EXTI15_10_IRQHandler - 0x0000000008000984 TIM7_IRQHandler - 0x0000000008000984 TIM5_IRQHandler - 0x0000000008000984 EXTI9_5_IRQHandler - 0x0000000008000984 TIM9_IRQHandler - 0x0000000008000984 TAMPER_STAMP_IRQHandler - 0x0000000008000984 RTC_WKUP_IRQHandler - 0x0000000008000984 SPI2_IRQHandler - 0x0000000008000984 DMA2_Channel5_IRQHandler - 0x0000000008000984 DMA1_Channel5_IRQHandler - 0x0000000008000984 USB_LP_IRQHandler - 0x0000000008000984 EXTI4_IRQHandler - 0x0000000008000984 DMA1_Channel3_IRQHandler - 0x0000000008000984 COMP_IRQHandler - 0x0000000008000984 WWDG_IRQHandler - 0x0000000008000984 TIM2_IRQHandler - 0x0000000008000984 DAC_IRQHandler - 0x0000000008000984 EXTI1_IRQHandler - 0x0000000008000984 TIM11_IRQHandler - 0x0000000008000984 USART2_IRQHandler - 0x0000000008000984 I2C2_ER_IRQHandler - 0x0000000008000984 DMA1_Channel2_IRQHandler - 0x0000000008000984 FLASH_IRQHandler - 0x0000000008000984 USART1_IRQHandler - 0x0000000008000984 SPI3_IRQHandler - 0x0000000008000984 I2C1_ER_IRQHandler - 0x0000000008000984 DMA2_Channel3_IRQHandler + 0x0000000008001f10 0x2 Core/Startup/startup_stm32f401retx.o + 0x0000000008001f10 EXTI2_IRQHandler + 0x0000000008001f10 SPI4_IRQHandler + 0x0000000008001f10 TIM1_CC_IRQHandler + 0x0000000008001f10 DMA2_Stream5_IRQHandler + 0x0000000008001f10 DMA1_Stream5_IRQHandler + 0x0000000008001f10 PVD_IRQHandler + 0x0000000008001f10 SDIO_IRQHandler + 0x0000000008001f10 TAMP_STAMP_IRQHandler + 0x0000000008001f10 EXTI3_IRQHandler + 0x0000000008001f10 TIM1_UP_TIM10_IRQHandler + 0x0000000008001f10 I2C3_ER_IRQHandler + 0x0000000008001f10 EXTI0_IRQHandler + 0x0000000008001f10 I2C2_EV_IRQHandler + 0x0000000008001f10 DMA1_Stream2_IRQHandler + 0x0000000008001f10 FPU_IRQHandler + 0x0000000008001f10 DMA2_Stream2_IRQHandler + 0x0000000008001f10 SPI1_IRQHandler + 0x0000000008001f10 TIM1_BRK_TIM9_IRQHandler + 0x0000000008001f10 DMA2_Stream3_IRQHandler + 0x0000000008001f10 USART6_IRQHandler + 0x0000000008001f10 DMA2_Stream0_IRQHandler + 0x0000000008001f10 TIM4_IRQHandler + 0x0000000008001f10 I2C1_EV_IRQHandler + 0x0000000008001f10 DMA1_Stream6_IRQHandler + 0x0000000008001f10 DMA1_Stream1_IRQHandler + 0x0000000008001f10 TIM3_IRQHandler + 0x0000000008001f10 RCC_IRQHandler + 0x0000000008001f10 Default_Handler + 0x0000000008001f10 EXTI15_10_IRQHandler + 0x0000000008001f10 ADC_IRQHandler + 0x0000000008001f10 DMA1_Stream7_IRQHandler + 0x0000000008001f10 TIM5_IRQHandler + 0x0000000008001f10 DMA2_Stream7_IRQHandler + 0x0000000008001f10 I2C3_EV_IRQHandler + 0x0000000008001f10 EXTI9_5_IRQHandler + 0x0000000008001f10 RTC_WKUP_IRQHandler + 0x0000000008001f10 SPI2_IRQHandler + 0x0000000008001f10 DMA1_Stream0_IRQHandler + 0x0000000008001f10 EXTI4_IRQHandler + 0x0000000008001f10 WWDG_IRQHandler + 0x0000000008001f10 TIM2_IRQHandler + 0x0000000008001f10 OTG_FS_WKUP_IRQHandler + 0x0000000008001f10 TIM1_TRG_COM_TIM11_IRQHandler + 0x0000000008001f10 EXTI1_IRQHandler + 0x0000000008001f10 USART2_IRQHandler + 0x0000000008001f10 I2C2_ER_IRQHandler + 0x0000000008001f10 DMA2_Stream1_IRQHandler + 0x0000000008001f10 FLASH_IRQHandler + 0x0000000008001f10 DMA2_Stream4_IRQHandler + 0x0000000008001f10 USART1_IRQHandler + 0x0000000008001f10 OTG_FS_IRQHandler + 0x0000000008001f10 SPI3_IRQHandler + 0x0000000008001f10 DMA1_Stream4_IRQHandler + 0x0000000008001f10 I2C1_ER_IRQHandler + 0x0000000008001f10 DMA2_Stream6_IRQHandler + 0x0000000008001f10 DMA1_Stream3_IRQHandler + *fill* 0x0000000008001f12 0x2 .text.HAL_Init - 0x0000000008000986 0x30 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x0000000008000986 HAL_Init - *fill* 0x00000000080009b6 0x2 + 0x0000000008001f14 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000008001f14 HAL_Init .text.HAL_InitTick - 0x00000000080009b8 0x74 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x00000000080009b8 HAL_InitTick + 0x0000000008001f58 0x60 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000008001f58 HAL_InitTick .text.HAL_IncTick - 0x0000000008000a2c 0x24 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x0000000008000a2c HAL_IncTick + 0x0000000008001fb8 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000008001fb8 HAL_IncTick .text.HAL_GetTick - 0x0000000008000a50 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x0000000008000a50 HAL_GetTick + 0x0000000008001fe0 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000008001fe0 HAL_GetTick .text.HAL_Delay - 0x0000000008000a64 0x44 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x0000000008000a64 HAL_Delay + 0x0000000008001ff8 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000008001ff8 HAL_Delay + .text.HAL_SuspendTick + 0x000000000800203c 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x000000000800203c HAL_SuspendTick + .text.HAL_ResumeTick + 0x000000000800205c 0x20 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x000000000800205c HAL_ResumeTick .text.__NVIC_SetPriorityGrouping - 0x0000000008000aa8 0x48 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x000000000800207c 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_GetPriorityGrouping - 0x0000000008000af0 0x1c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x00000000080020c4 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .text.__NVIC_EnableIRQ + 0x00000000080020e0 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.__NVIC_SetPriority - 0x0000000008000b0c 0x54 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x000000000800211c 0x54 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.NVIC_EncodePriority - 0x0000000008000b60 0x64 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000008002170 0x66 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + *fill* 0x00000000080021d6 0x2 .text.SysTick_Config - 0x0000000008000bc4 0x44 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x00000000080021d8 0x44 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .text.HAL_NVIC_SetPriorityGrouping - 0x0000000008000c08 0x16 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x0000000008000c08 HAL_NVIC_SetPriorityGrouping + 0x000000000800221c 0x16 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x000000000800221c HAL_NVIC_SetPriorityGrouping .text.HAL_NVIC_SetPriority - 0x0000000008000c1e 0x38 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x0000000008000c1e HAL_NVIC_SetPriority + 0x0000000008002232 0x38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x0000000008002232 HAL_NVIC_SetPriority + .text.HAL_NVIC_EnableIRQ + 0x000000000800226a 0x1c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x000000000800226a HAL_NVIC_EnableIRQ .text.HAL_SYSTICK_Config - 0x0000000008000c56 0x18 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x0000000008000c56 HAL_SYSTICK_Config - *fill* 0x0000000008000c6e 0x2 + 0x0000000008002286 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x0000000008002286 HAL_SYSTICK_Config + *fill* 0x000000000800229e 0x2 .text.HAL_GPIO_Init - 0x0000000008000c70 0x31c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - 0x0000000008000c70 HAL_GPIO_Init + 0x00000000080022a0 0x304 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x00000000080022a0 HAL_GPIO_Init .text.HAL_GPIO_WritePin - 0x0000000008000f8c 0x30 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - 0x0000000008000f8c HAL_GPIO_WritePin + 0x00000000080025a4 0x32 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x00000000080025a4 HAL_GPIO_WritePin + *fill* 0x00000000080025d6 0x2 + .text.HAL_PWR_EnterSLEEPMode + 0x00000000080025d8 0x38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + 0x00000000080025d8 HAL_PWR_EnterSLEEPMode .text.HAL_RCC_OscConfig - 0x0000000008000fbc 0x660 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x0000000008000fbc HAL_RCC_OscConfig + 0x0000000008002610 0x4e0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000008002610 HAL_RCC_OscConfig .text.HAL_RCC_ClockConfig - 0x000000000800161c 0x268 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x000000000800161c HAL_RCC_ClockConfig + 0x0000000008002af0 0x1cc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000008002af0 HAL_RCC_ClockConfig .text.HAL_RCC_GetSysClockFreq - 0x0000000008001884 0x194 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x0000000008001884 HAL_RCC_GetSysClockFreq + 0x0000000008002cbc 0x1b0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000008002cbc HAL_RCC_GetSysClockFreq .text.HAL_RCC_GetHCLKFreq - 0x0000000008001a18 0x14 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x0000000008001a18 HAL_RCC_GetHCLKFreq + 0x0000000008002e6c 0x18 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000008002e6c HAL_RCC_GetHCLKFreq .text.HAL_RCC_GetPCLK1Freq - 0x0000000008001a2c 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x0000000008001a2c HAL_RCC_GetPCLK1Freq + 0x0000000008002e84 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000008002e84 HAL_RCC_GetPCLK1Freq .text.HAL_RCC_GetPCLK2Freq - 0x0000000008001a54 0x28 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x0000000008001a54 HAL_RCC_GetPCLK2Freq - .text.RCC_SetFlashLatencyFromMSIRange - 0x0000000008001a7c 0xc0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000008002eac 0x28 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000008002eac HAL_RCC_GetPCLK2Freq .text.HAL_RCCEx_PeriphCLKConfig - 0x0000000008001b3c 0x1c4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - 0x0000000008001b3c HAL_RCCEx_PeriphCLKConfig + 0x0000000008002ed4 0x1dc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + 0x0000000008002ed4 HAL_RCCEx_PeriphCLKConfig .text.HAL_RTC_Init - 0x0000000008001d00 0xf6 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x0000000008001d00 HAL_RTC_Init + 0x00000000080030b0 0x122 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x00000000080030b0 HAL_RTC_Init .text.HAL_RTC_SetTime - 0x0000000008001df6 0x168 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x0000000008001df6 HAL_RTC_SetTime + 0x00000000080031d2 0x17a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x00000000080031d2 HAL_RTC_SetTime .text.HAL_RTC_GetTime - 0x0000000008001f5e 0xba Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x0000000008001f5e HAL_RTC_GetTime + 0x000000000800334c 0xbc Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x000000000800334c HAL_RTC_GetTime .text.HAL_RTC_SetDate - 0x0000000008002018 0x13c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x0000000008002018 HAL_RTC_SetDate + 0x0000000008003408 0x14e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x0000000008003408 HAL_RTC_SetDate .text.HAL_RTC_GetDate - 0x0000000008002154 0x9a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x0000000008002154 HAL_RTC_GetDate + 0x0000000008003556 0x9e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x0000000008003556 HAL_RTC_GetDate + .text.HAL_RTC_SetAlarm_IT + 0x00000000080035f4 0x270 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x00000000080035f4 HAL_RTC_SetAlarm_IT + .text.HAL_RTC_AlarmIRQHandler + 0x0000000008003864 0x8c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x0000000008003864 HAL_RTC_AlarmIRQHandler .text.HAL_RTC_WaitForSynchro - 0x00000000080021ee 0x5a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x00000000080021ee HAL_RTC_WaitForSynchro + 0x00000000080038f0 0x50 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x00000000080038f0 HAL_RTC_WaitForSynchro .text.RTC_EnterInitMode - 0x0000000008002248 0x54 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x0000000008002248 RTC_EnterInitMode + 0x0000000008003940 0x58 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x0000000008003940 RTC_EnterInitMode .text.RTC_ByteToBcd2 - 0x000000000800229c 0x3e Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x000000000800229c RTC_ByteToBcd2 + 0x0000000008003998 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x0000000008003998 RTC_ByteToBcd2 .text.RTC_Bcd2ToByte - 0x00000000080022da 0x36 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x00000000080022da RTC_Bcd2ToByte + 0x00000000080039d4 0x3c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x00000000080039d4 RTC_Bcd2ToByte + .text.HAL_RTCEx_AlarmBEventCallback + 0x0000000008003a10 0x14 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + 0x0000000008003a10 HAL_RTCEx_AlarmBEventCallback .text.HAL_UART_Init - 0x0000000008002310 0x9a Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - 0x0000000008002310 HAL_UART_Init - *fill* 0x00000000080023aa 0x2 + 0x0000000008003a24 0x9a Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + 0x0000000008003a24 HAL_UART_Init + .text.HAL_UART_Transmit + 0x0000000008003abe 0x132 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + 0x0000000008003abe HAL_UART_Transmit + .text.UART_WaitOnFlagUntilTimeout + 0x0000000008003bf0 0x94 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text.UART_SetConfig - 0x00000000080023ac 0x1c8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000008003c84 0x6f8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .text.__errno 0x000000000800437c 0xc c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) + 0x000000000800437c __errno .text.__libc_init_array - 0x0000000008002574 0x48 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) - 0x0000000008002574 __libc_init_array - .text.memset 0x00000000080025bc 0x10 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) - 0x00000000080025bc memset + 0x0000000008004388 0x48 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) + 0x0000000008004388 __libc_init_array + .text.memset 0x00000000080043d0 0x10 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + 0x00000000080043d0 memset + .text.cos 0x00000000080043e0 0x88 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + 0x00000000080043e0 cos + .text.floor 0x0000000008004468 0x108 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + 0x0000000008004468 floor + .text.sin 0x0000000008004570 0x90 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + 0x0000000008004570 sin + .text.tan 0x0000000008004600 0x60 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + 0x0000000008004600 tan + .text.acos 0x0000000008004660 0xb0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + 0x0000000008004660 acos + .text.__ieee754_acos + 0x0000000008004710 0x4b8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + 0x0000000008004710 __ieee754_acos + .text.__ieee754_rem_pio2 + 0x0000000008004bc8 0x3e4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + 0x0000000008004bc8 __ieee754_rem_pio2 + .text.__ieee754_sqrt + 0x0000000008004fac 0x160 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + 0x0000000008004fac __ieee754_sqrt + *fill* 0x000000000800510c 0x4 + .text.__kernel_cos + 0x0000000008005110 0x18c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + 0x0000000008005110 __kernel_cos + *fill* 0x000000000800529c 0x4 + .text.__kernel_rem_pio2 + 0x00000000080052a0 0x680 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + 0x00000000080052a0 __kernel_rem_pio2 + .text.__kernel_sin + 0x0000000008005920 0x174 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + 0x0000000008005920 __kernel_sin + *fill* 0x0000000008005a94 0x4 + .text.__kernel_tan + 0x0000000008005a98 0x398 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + 0x0000000008005a98 __kernel_tan + .text.fabs 0x0000000008005e30 0x12 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + 0x0000000008005e30 fabs + .text.matherr 0x0000000008005e42 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + 0x0000000008005e42 matherr + *fill* 0x0000000008005e46 0x2 + .text.nan 0x0000000008005e48 0x10 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + 0x0000000008005e48 nan + .text.scalbn 0x0000000008005e58 0xec c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + 0x0000000008005e58 scalbn + .text.copysign + 0x0000000008005f44 0x1e c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + 0x0000000008005f44 copysign *(.glue_7) - .glue_7 0x00000000080025cc 0x0 linker stubs + .glue_7 0x0000000008005f62 0x0 linker stubs *(.glue_7t) - .glue_7t 0x00000000080025cc 0x0 linker stubs + .glue_7t 0x0000000008005f62 0x0 linker stubs *(.eh_frame) - .eh_frame 0x00000000080025cc 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o + *fill* 0x0000000008005f62 0x2 + .eh_frame 0x0000000008005f64 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o *(.init) - .init 0x00000000080025cc 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o - 0x00000000080025cc _init - .init 0x00000000080025d0 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o + .init 0x0000000008005f64 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + 0x0000000008005f64 _init + .init 0x0000000008005f68 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o *(.fini) - .fini 0x00000000080025d8 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o - 0x00000000080025d8 _fini - .fini 0x00000000080025dc 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o - 0x00000000080025e4 . = ALIGN (0x4) - 0x00000000080025e4 _etext = . + .fini 0x0000000008005f70 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o + 0x0000000008005f70 _fini + .fini 0x0000000008005f74 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o + 0x0000000008005f7c . = ALIGN (0x4) + 0x0000000008005f7c _etext = . -.vfp11_veneer 0x00000000080025e4 0x0 - .vfp11_veneer 0x00000000080025e4 0x0 linker stubs +.vfp11_veneer 0x0000000008005f7c 0x0 + .vfp11_veneer 0x0000000008005f7c 0x0 linker stubs -.v4_bx 0x00000000080025e4 0x0 - .v4_bx 0x00000000080025e4 0x0 linker stubs +.v4_bx 0x0000000008005f7c 0x0 + .v4_bx 0x0000000008005f7c 0x0 linker stubs -.iplt 0x00000000080025e4 0x0 - .iplt 0x00000000080025e4 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o +.iplt 0x0000000008005f7c 0x0 + .iplt 0x0000000008005f7c 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o -.rodata 0x00000000080025e4 0x24 - 0x00000000080025e4 . = ALIGN (0x4) +.rodata 0x0000000008005f80 0x290 + 0x0000000008005f80 . = ALIGN (0x4) *(.rodata) + .rodata 0x0000000008005f80 0x98 Core/Src/main.o *(.rodata*) - .rodata.PLLMulTable - 0x00000000080025e4 0x9 Core/Src/system_stm32l1xx.o - 0x00000000080025e4 PLLMulTable - *fill* 0x00000000080025ed 0x3 .rodata.AHBPrescTable - 0x00000000080025f0 0x10 Core/Src/system_stm32l1xx.o - 0x00000000080025f0 AHBPrescTable + 0x0000000008006018 0x10 Core/Src/system_stm32f4xx.o + 0x0000000008006018 AHBPrescTable .rodata.APBPrescTable - 0x0000000008002600 0x8 Core/Src/system_stm32l1xx.o - 0x0000000008002600 APBPrescTable - 0x0000000008002608 . = ALIGN (0x4) + 0x0000000008006028 0x8 Core/Src/system_stm32f4xx.o + 0x0000000008006028 APBPrescTable + .rodata.acos.str1.1 + 0x0000000008006030 0x5 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + 0x6 (size before relaxing) + *fill* 0x0000000008006035 0x3 + .rodata.npio2_hw + 0x0000000008006038 0x80 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .rodata.two_over_pi + 0x00000000080060b8 0x108 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .rodata.PIo2 0x00000000080061c0 0x40 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + .rodata.init_jk + 0x0000000008006200 0x10 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + 0x0000000008006210 . = ALIGN (0x4) -.ARM.extab 0x0000000008002608 0x0 - 0x0000000008002608 . = ALIGN (0x4) +.ARM.extab 0x0000000008006210 0x0 + 0x0000000008006210 . = ALIGN (0x4) *(.ARM.extab* .gnu.linkonce.armextab.*) - 0x0000000008002608 . = ALIGN (0x4) + 0x0000000008006210 . = ALIGN (0x4) -.ARM 0x0000000008002608 0x8 - 0x0000000008002608 . = ALIGN (0x4) - 0x0000000008002608 __exidx_start = . +.ARM 0x0000000008006210 0x8 + 0x0000000008006210 . = ALIGN (0x4) + 0x0000000008006210 __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x0000000008002608 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) - 0x0000000008002610 __exidx_end = . - 0x0000000008002610 . = ALIGN (0x4) + .ARM.exidx 0x0000000008006210 0x8 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + 0x0000000008006218 __exidx_end = . + 0x0000000008006218 . = ALIGN (0x4) -.rel.dyn 0x0000000008002610 0x0 - .rel.iplt 0x0000000008002610 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o +.rel.dyn 0x0000000008006218 0x0 + .rel.iplt 0x0000000008006218 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o -.preinit_array 0x0000000008002610 0x0 - 0x0000000008002610 . = ALIGN (0x4) - 0x0000000008002610 PROVIDE (__preinit_array_start = .) +.preinit_array 0x0000000008006218 0x0 + 0x0000000008006218 . = ALIGN (0x4) + 0x0000000008006218 PROVIDE (__preinit_array_start = .) *(.preinit_array*) - 0x0000000008002610 PROVIDE (__preinit_array_end = .) - 0x0000000008002610 . = ALIGN (0x4) + 0x0000000008006218 PROVIDE (__preinit_array_end = .) + 0x0000000008006218 . = ALIGN (0x4) -.init_array 0x0000000008002610 0x4 - 0x0000000008002610 . = ALIGN (0x4) - 0x0000000008002610 PROVIDE (__init_array_start = .) +.init_array 0x0000000008006218 0x4 + 0x0000000008006218 . = ALIGN (0x4) + 0x0000000008006218 PROVIDE (__init_array_start = .) *(SORT_BY_NAME(.init_array.*)) *(.init_array*) - .init_array 0x0000000008002610 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o - 0x0000000008002614 PROVIDE (__init_array_end = .) - 0x0000000008002614 . = ALIGN (0x4) + .init_array 0x0000000008006218 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + 0x000000000800621c PROVIDE (__init_array_end = .) + 0x000000000800621c . = ALIGN (0x4) -.fini_array 0x0000000008002614 0x4 - 0x0000000008002614 . = ALIGN (0x4) +.fini_array 0x000000000800621c 0x4 + 0x000000000800621c . = ALIGN (0x4) [!provide] PROVIDE (__fini_array_start = .) *(SORT_BY_NAME(.fini_array.*)) *(.fini_array*) - .fini_array 0x0000000008002614 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o + .fini_array 0x000000000800621c 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o [!provide] PROVIDE (__fini_array_end = .) - 0x0000000008002618 . = ALIGN (0x4) - 0x0000000008002618 _sidata = LOADADDR (.data) + 0x0000000008006220 . = ALIGN (0x4) + 0x0000000008006220 _sidata = LOADADDR (.data) -.data 0x0000000020000000 0xc load address 0x0000000008002618 +.data 0x0000000020000000 0x88 load address 0x0000000008006220 0x0000000020000000 . = ALIGN (0x4) 0x0000000020000000 _sdata = . *(.data) *(.data*) + .data.latitude_nbg + 0x0000000020000000 0x4 Core/Src/main.o + 0x0000000020000000 latitude_nbg + .data.longitude_nbg + 0x0000000020000004 0x4 Core/Src/main.o + 0x0000000020000004 longitude_nbg + .data.UTC_DER_sum + 0x0000000020000008 0x4 Core/Src/main.o + 0x0000000020000008 UTC_DER_sum + .data.UTC_DER_win + 0x000000002000000c 0x4 Core/Src/main.o + 0x000000002000000c UTC_DER_win + .data.winterTime + 0x0000000020000010 0x1 Core/Src/main.o + 0x0000000020000010 winterTime + *fill* 0x0000000020000011 0x3 .data.SystemCoreClock - 0x0000000020000000 0x4 Core/Src/system_stm32l1xx.o - 0x0000000020000000 SystemCoreClock + 0x0000000020000014 0x4 Core/Src/system_stm32f4xx.o + 0x0000000020000014 SystemCoreClock .data.uwTickPrio - 0x0000000020000004 0x4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x0000000020000004 uwTickPrio + 0x0000000020000018 0x4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000020000018 uwTickPrio .data.uwTickFreq - 0x0000000020000008 0x4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x0000000020000008 uwTickFreq - 0x000000002000000c . = ALIGN (0x4) - 0x000000002000000c _edata = . + 0x000000002000001c 0x1 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x000000002000001c uwTickFreq + *fill* 0x000000002000001d 0x3 + .data._impure_ptr + 0x0000000020000020 0x4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) + 0x0000000020000020 _impure_ptr + .data.impure_data + 0x0000000020000024 0x60 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) + .data.__fdlib_version + 0x0000000020000084 0x1 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_lib_ver.o) + 0x0000000020000084 __fdlib_version + *(.RamFunc) + *(.RamFunc*) + 0x0000000020000088 . = ALIGN (0x4) + *fill* 0x0000000020000085 0x3 + 0x0000000020000088 _edata = . -.igot.plt 0x000000002000000c 0x0 load address 0x0000000008002624 - .igot.plt 0x000000002000000c 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o - 0x000000002000000c . = ALIGN (0x4) +.igot.plt 0x0000000020000088 0x0 load address 0x00000000080062a8 + .igot.plt 0x0000000020000088 0x0 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o + 0x0000000020000088 . = ALIGN (0x4) -.bss 0x000000002000000c 0x98 load address 0x0000000008002624 - 0x000000002000000c _sbss = . - 0x000000002000000c __bss_start__ = _sbss +.bss 0x0000000020000088 0xc0 load address 0x00000000080062a8 + 0x0000000020000088 _sbss = . + 0x0000000020000088 __bss_start__ = _sbss *(.bss) - .bss 0x000000002000000c 0x1c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o + .bss 0x0000000020000088 0x1c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o *(.bss*) *(COMMON) - COMMON 0x0000000020000028 0x78 Core/Src/main.o - 0x0000000020000028 sTime - 0x000000002000003c sDate - 0x0000000020000040 hrtc - 0x0000000020000060 huart2 - COMMON 0x00000000200000a0 0x4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x00000000200000a0 uwTick - 0x00000000200000a4 . = ALIGN (0x4) - 0x00000000200000a4 _ebss = . - 0x00000000200000a4 __bss_end__ = _ebss + COMMON 0x00000000200000a4 0xa0 Core/Src/main.o + 0x00000000200000a4 sTime + 0x00000000200000b8 sAlarm + 0x00000000200000e0 sDate + 0x00000000200000e4 hrtc + 0x0000000020000104 huart2 + COMMON 0x0000000020000144 0x4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x0000000020000144 uwTick + 0x0000000020000148 . = ALIGN (0x4) + 0x0000000020000148 _ebss = . + 0x0000000020000148 __bss_end__ = _ebss ._user_heap_stack - 0x00000000200000a4 0x604 load address 0x0000000008002624 - 0x00000000200000a8 . = ALIGN (0x8) - *fill* 0x00000000200000a4 0x4 + 0x0000000020000148 0x600 load address 0x00000000080062a8 + 0x0000000020000148 . = ALIGN (0x8) [!provide] PROVIDE (end = .) - 0x00000000200000a8 PROVIDE (_end = .) - 0x00000000200002a8 . = (. + _Min_Heap_Size) - *fill* 0x00000000200000a8 0x200 - 0x00000000200006a8 . = (. + _Min_Stack_Size) - *fill* 0x00000000200002a8 0x400 - 0x00000000200006a8 . = ALIGN (0x8) + 0x0000000020000148 PROVIDE (_end = .) + 0x0000000020000348 . = (. + _Min_Heap_Size) + *fill* 0x0000000020000148 0x200 + 0x0000000020000748 . = (. + _Min_Stack_Size) + *fill* 0x0000000020000348 0x400 + 0x0000000020000748 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -2888,235 +3412,351 @@ LOAD c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.exte libgcc.a(*) .ARM.attributes - 0x0000000000000000 0x29 + 0x0000000000000000 0x30 *(.ARM.attributes) .ARM.attributes - 0x0000000000000000 0x1d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crti.o + 0x0000000000000000 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crti.o .ARM.attributes - 0x000000000000001d 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtbegin.o + 0x0000000000000022 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtbegin.o .ARM.attributes - 0x000000000000004a 0x33 Core/Src/main.o + 0x0000000000000056 0x39 Core/Src/main.o .ARM.attributes - 0x000000000000007d 0x33 Core/Src/stm32l1xx_hal_msp.o + 0x000000000000008f 0x39 Core/Src/stm32f4xx_hal_msp.o .ARM.attributes - 0x00000000000000b0 0x33 Core/Src/stm32l1xx_it.o + 0x00000000000000c8 0x39 Core/Src/stm32f4xx_it.o .ARM.attributes - 0x00000000000000e3 0x33 Core/Src/system_stm32l1xx.o + 0x0000000000000101 0x39 Core/Src/system_stm32f4xx.o .ARM.attributes - 0x0000000000000116 0x21 Core/Startup/startup_stm32l152retx.o + 0x000000000000013a 0x21 Core/Startup/startup_stm32f401retx.o .ARM.attributes - 0x0000000000000137 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x000000000000015b 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .ARM.attributes - 0x000000000000016a 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000194 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .ARM.attributes - 0x000000000000019d 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x00000000000001cd 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .ARM.attributes - 0x00000000000001d0 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x0000000000000206 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .ARM.attributes - 0x0000000000000203 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o + 0x000000000000023f 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .ARM.attributes - 0x0000000000000236 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000278 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .ARM.attributes - 0x0000000000000269 0x33 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x00000000000002b1 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o .ARM.attributes - 0x000000000000029c 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) + 0x00000000000002ea 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o .ARM.attributes - 0x00000000000002c9 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) + 0x0000000000000323 0x39 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .ARM.attributes - 0x00000000000002f6 0x1d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) + 0x000000000000035c 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) .ARM.attributes - 0x0000000000000313 0x2d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) + 0x0000000000000390 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-impure.o) .ARM.attributes - 0x0000000000000340 0x1d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_dvmd_tls.o) + 0x00000000000003c4 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) .ARM.attributes - 0x000000000000035d 0x1d c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m/crtn.o + 0x00000000000003f8 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x000000000000042c 0x1b c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-strlen.o) + .ARM.attributes + 0x0000000000000447 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + .ARM.attributes + 0x000000000000047b 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + .ARM.attributes + 0x00000000000004af 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + .ARM.attributes + 0x00000000000004e3 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + .ARM.attributes + 0x0000000000000517 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + .ARM.attributes + 0x000000000000054b 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + .ARM.attributes + 0x000000000000057f 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .ARM.attributes + 0x00000000000005b3 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + .ARM.attributes + 0x00000000000005e7 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + .ARM.attributes + 0x000000000000061b 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + .ARM.attributes + 0x000000000000064f 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + .ARM.attributes + 0x0000000000000683 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + .ARM.attributes + 0x00000000000006b7 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + .ARM.attributes + 0x00000000000006eb 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_lib_ver.o) + .ARM.attributes + 0x000000000000071f 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + .ARM.attributes + 0x0000000000000753 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + .ARM.attributes + 0x0000000000000787 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + .ARM.attributes + 0x00000000000007bb 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + .ARM.attributes + 0x00000000000007ef 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_addsubdf3.o) + .ARM.attributes + 0x0000000000000811 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_muldivdf3.o) + .ARM.attributes + 0x0000000000000833 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_cmpdf2.o) + .ARM.attributes + 0x0000000000000855 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_unorddf2.o) + .ARM.attributes + 0x0000000000000877 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_fixdfsi.o) + .ARM.attributes + 0x0000000000000899 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x00000000000008bb 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x00000000000008ef 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000000911 0x22 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard/crtn.o OUTPUT(RTC.elf elf32-littlearm) -.debug_info 0x0000000000000000 0x6999 - .debug_info 0x0000000000000000 0xf37 Core/Src/main.o - .debug_info 0x0000000000000f37 0xc39 Core/Src/stm32l1xx_hal_msp.o - .debug_info 0x0000000000001b70 0x1fc Core/Src/stm32l1xx_it.o - .debug_info 0x0000000000001d6c 0x473 Core/Src/system_stm32l1xx.o - .debug_info 0x00000000000021df 0x22 Core/Startup/startup_stm32l152retx.o - .debug_info 0x0000000000002201 0x72b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_info 0x000000000000292c 0xd84 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_info 0x00000000000036b0 0x6ac Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_info 0x0000000000003d5c 0x94f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_info 0x00000000000046ab 0x4b2 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_info 0x0000000000004b5d 0xc58 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_info 0x00000000000057b5 0x11e4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o +.debug_info 0x0000000000000000 0x98e6 + .debug_info 0x0000000000000000 0x1df7 Core/Src/main.o + .debug_info 0x0000000000001df7 0xe56 Core/Src/stm32f4xx_hal_msp.o + .debug_info 0x0000000000002c4d 0x548 Core/Src/stm32f4xx_it.o + .debug_info 0x0000000000003195 0x57e Core/Src/system_stm32f4xx.o + .debug_info 0x0000000000003713 0x22 Core/Startup/startup_stm32f401retx.o + .debug_info 0x0000000000003735 0x8ce Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_info 0x0000000000004003 0xd92 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_info 0x0000000000004d95 0x7d7 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_info 0x000000000000556c 0x789 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_info 0x0000000000005cf5 0x929 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_info 0x000000000000661e 0x5e5 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_info 0x0000000000006c03 0xbb3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_info 0x00000000000077b6 0xeec Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_info 0x00000000000086a2 0x1244 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_abbrev 0x0000000000000000 0x1431 - .debug_abbrev 0x0000000000000000 0x1e5 Core/Src/main.o - .debug_abbrev 0x00000000000001e5 0x1a6 Core/Src/stm32l1xx_hal_msp.o - .debug_abbrev 0x000000000000038b 0xac Core/Src/stm32l1xx_it.o - .debug_abbrev 0x0000000000000437 0x111 Core/Src/system_stm32l1xx.o - .debug_abbrev 0x0000000000000548 0x12 Core/Startup/startup_stm32l152retx.o - .debug_abbrev 0x000000000000055a 0x21b Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_abbrev 0x0000000000000775 0x2fa Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_abbrev 0x0000000000000a6f 0x1c9 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_abbrev 0x0000000000000c38 0x238 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_abbrev 0x0000000000000e70 0x1c1 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_abbrev 0x0000000000001031 0x1be Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_abbrev 0x00000000000011ef 0x242 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o +.debug_abbrev 0x0000000000000000 0x196e + .debug_abbrev 0x0000000000000000 0x351 Core/Src/main.o + .debug_abbrev 0x0000000000000351 0x195 Core/Src/stm32f4xx_hal_msp.o + .debug_abbrev 0x00000000000004e6 0x123 Core/Src/stm32f4xx_it.o + .debug_abbrev 0x0000000000000609 0x12b Core/Src/system_stm32f4xx.o + .debug_abbrev 0x0000000000000734 0x12 Core/Startup/startup_stm32f401retx.o + .debug_abbrev 0x0000000000000746 0x1f2 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_abbrev 0x0000000000000938 0x2fa Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_abbrev 0x0000000000000c32 0x1c9 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_abbrev 0x0000000000000dfb 0x1a5 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_abbrev 0x0000000000000fa0 0x245 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_abbrev 0x00000000000011e5 0x173 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_abbrev 0x0000000000001358 0x1cd Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_abbrev 0x0000000000001525 0x1f8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_abbrev 0x000000000000171d 0x251 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_aranges 0x0000000000000000 0x6f8 +.debug_aranges 0x0000000000000000 0x910 .debug_aranges - 0x0000000000000000 0x48 Core/Src/main.o + 0x0000000000000000 0x90 Core/Src/main.o .debug_aranges - 0x0000000000000048 0x40 Core/Src/stm32l1xx_hal_msp.o + 0x0000000000000090 0x40 Core/Src/stm32f4xx_hal_msp.o .debug_aranges - 0x0000000000000088 0x60 Core/Src/stm32l1xx_it.o + 0x00000000000000d0 0x68 Core/Src/stm32f4xx_it.o .debug_aranges - 0x00000000000000e8 0x28 Core/Src/system_stm32l1xx.o + 0x0000000000000138 0x28 Core/Src/system_stm32f4xx.o .debug_aranges - 0x0000000000000110 0x28 Core/Startup/startup_stm32l152retx.o + 0x0000000000000160 0x28 Core/Startup/startup_stm32f401retx.o .debug_aranges - 0x0000000000000138 0xe0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o + 0x0000000000000188 0xf0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_aranges - 0x0000000000000218 0x118 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o + 0x0000000000000278 0x118 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_aranges - 0x0000000000000330 0x58 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o + 0x0000000000000390 0x58 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_aranges - 0x0000000000000388 0x90 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o + 0x00000000000003e8 0xa0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_aranges - 0x0000000000000418 0x58 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o + 0x0000000000000488 0x88 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_aranges - 0x0000000000000470 0xb8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o + 0x0000000000000510 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_aranges - 0x0000000000000528 0x1d0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + 0x0000000000000558 0xb8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_aranges + 0x0000000000000610 0x130 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_aranges + 0x0000000000000740 0x1d0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_ranges 0x0000000000000000 0x640 - .debug_ranges 0x0000000000000000 0x38 Core/Src/main.o - .debug_ranges 0x0000000000000038 0x30 Core/Src/stm32l1xx_hal_msp.o - .debug_ranges 0x0000000000000068 0x50 Core/Src/stm32l1xx_it.o - .debug_ranges 0x00000000000000b8 0x18 Core/Src/system_stm32l1xx.o - .debug_ranges 0x00000000000000d0 0x20 Core/Startup/startup_stm32l152retx.o - .debug_ranges 0x00000000000000f0 0xd0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_ranges 0x00000000000001c0 0x108 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_ranges 0x00000000000002c8 0x48 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_ranges 0x0000000000000310 0x80 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_ranges 0x0000000000000390 0x48 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_ranges 0x00000000000003d8 0xa8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_ranges 0x0000000000000480 0x1c0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o +.debug_ranges 0x0000000000000000 0x838 + .debug_ranges 0x0000000000000000 0x80 Core/Src/main.o + .debug_ranges 0x0000000000000080 0x30 Core/Src/stm32f4xx_hal_msp.o + .debug_ranges 0x00000000000000b0 0x58 Core/Src/stm32f4xx_it.o + .debug_ranges 0x0000000000000108 0x18 Core/Src/system_stm32f4xx.o + .debug_ranges 0x0000000000000120 0x20 Core/Startup/startup_stm32f401retx.o + .debug_ranges 0x0000000000000140 0xe0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_ranges 0x0000000000000220 0x108 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_ranges 0x0000000000000328 0x48 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_ranges 0x0000000000000370 0x90 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_ranges 0x0000000000000400 0x78 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_ranges 0x0000000000000478 0x38 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_ranges 0x00000000000004b0 0xa8 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_ranges 0x0000000000000558 0x120 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_ranges 0x0000000000000678 0x1c0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_macro 0x0000000000000000 0x15151 - .debug_macro 0x0000000000000000 0x1c3 Core/Src/main.o - .debug_macro 0x00000000000001c3 0xa5a Core/Src/main.o - .debug_macro 0x0000000000000c1d 0x112 Core/Src/main.o - .debug_macro 0x0000000000000d2f 0x2e Core/Src/main.o - .debug_macro 0x0000000000000d5d 0x22 Core/Src/main.o - .debug_macro 0x0000000000000d7f 0x22 Core/Src/main.o - .debug_macro 0x0000000000000da1 0x8e Core/Src/main.o - .debug_macro 0x0000000000000e2f 0x51 Core/Src/main.o - .debug_macro 0x0000000000000e80 0xef Core/Src/main.o - .debug_macro 0x0000000000000f6f 0x6a Core/Src/main.o - .debug_macro 0x0000000000000fd9 0x1df Core/Src/main.o - .debug_macro 0x00000000000011b8 0x1c Core/Src/main.o - .debug_macro 0x00000000000011d4 0x22 Core/Src/main.o - .debug_macro 0x00000000000011f6 0xc3 Core/Src/main.o - .debug_macro 0x00000000000012b9 0xe49 Core/Src/main.o - .debug_macro 0x0000000000002102 0x11f Core/Src/main.o - .debug_macro 0x0000000000002221 0xb52b Core/Src/main.o - .debug_macro 0x000000000000d74c 0x43 Core/Src/main.o - .debug_macro 0x000000000000d78f 0x34a0 Core/Src/main.o - .debug_macro 0x0000000000010c2f 0x174 Core/Src/main.o - .debug_macro 0x0000000000010da3 0x5b Core/Src/main.o - .debug_macro 0x0000000000010dfe 0xe38 Core/Src/main.o - .debug_macro 0x0000000000011c36 0x35b Core/Src/main.o - .debug_macro 0x0000000000011f91 0x13b Core/Src/main.o - .debug_macro 0x00000000000120cc 0xc5 Core/Src/main.o - .debug_macro 0x0000000000012191 0x21e Core/Src/main.o - .debug_macro 0x00000000000123af 0x236 Core/Src/main.o - .debug_macro 0x00000000000125e5 0x10e Core/Src/main.o - .debug_macro 0x00000000000126f3 0x567 Core/Src/main.o - .debug_macro 0x0000000000012c5a 0x1e9 Core/Src/main.o - .debug_macro 0x0000000000012e43 0x22 Core/Src/main.o - .debug_macro 0x0000000000012e65 0x287 Core/Src/main.o - .debug_macro 0x00000000000130ec 0x5cc Core/Src/main.o - .debug_macro 0x00000000000136b8 0x12 Core/Src/main.o - .debug_macro 0x00000000000136ca 0x287 Core/Src/main.o - .debug_macro 0x0000000000013951 0x170 Core/Src/main.o - .debug_macro 0x0000000000013ac1 0x492 Core/Src/main.o - .debug_macro 0x0000000000013f53 0x58 Core/Src/main.o - .debug_macro 0x0000000000013fab 0x1c3 Core/Src/stm32l1xx_hal_msp.o - .debug_macro 0x000000000001416e 0x1cd Core/Src/stm32l1xx_it.o - .debug_macro 0x000000000001433b 0x1ba Core/Src/system_stm32l1xx.o - .debug_macro 0x00000000000144f5 0x1d8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_macro 0x00000000000146cd 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_macro 0x0000000000014881 0x1ec Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_macro 0x0000000000014a6d 0x1c6 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_macro 0x0000000000014c33 0x1b4 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_macro 0x0000000000014de7 0x1b5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_macro 0x0000000000014f9c 0x1b5 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o +.debug_macro 0x0000000000000000 0x15f3a + .debug_macro 0x0000000000000000 0x289 Core/Src/main.o + .debug_macro 0x0000000000000289 0xa5a Core/Src/main.o + .debug_macro 0x0000000000000ce3 0x294 Core/Src/main.o + .debug_macro 0x0000000000000f77 0x2e Core/Src/main.o + .debug_macro 0x0000000000000fa5 0x28 Core/Src/main.o + .debug_macro 0x0000000000000fcd 0x22 Core/Src/main.o + .debug_macro 0x0000000000000fef 0x8e Core/Src/main.o + .debug_macro 0x000000000000107d 0x51 Core/Src/main.o + .debug_macro 0x00000000000010ce 0xef Core/Src/main.o + .debug_macro 0x00000000000011bd 0x6a Core/Src/main.o + .debug_macro 0x0000000000001227 0x1df Core/Src/main.o + .debug_macro 0x0000000000001406 0x1c Core/Src/main.o + .debug_macro 0x0000000000001422 0x22 Core/Src/main.o + .debug_macro 0x0000000000001444 0xdf Core/Src/main.o + .debug_macro 0x0000000000001523 0x102d Core/Src/main.o + .debug_macro 0x0000000000002550 0x11f Core/Src/main.o + .debug_macro 0x000000000000266f 0xb850 Core/Src/main.o + .debug_macro 0x000000000000debf 0x43 Core/Src/main.o + .debug_macro 0x000000000000df02 0x3659 Core/Src/main.o + .debug_macro 0x000000000001155b 0x174 Core/Src/main.o + .debug_macro 0x00000000000116cf 0x5a Core/Src/main.o + .debug_macro 0x0000000000011729 0x416 Core/Src/main.o + .debug_macro 0x0000000000011b3f 0x9fe Core/Src/main.o + .debug_macro 0x000000000001253d 0x117 Core/Src/main.o + .debug_macro 0x0000000000012654 0xf8 Core/Src/main.o + .debug_macro 0x000000000001274c 0x27 Core/Src/main.o + .debug_macro 0x0000000000012773 0x15f Core/Src/main.o + .debug_macro 0x00000000000128d2 0x287 Core/Src/main.o + .debug_macro 0x0000000000012b59 0x5f Core/Src/main.o + .debug_macro 0x0000000000012bb8 0x236 Core/Src/main.o + .debug_macro 0x0000000000012dee 0x132 Core/Src/main.o + .debug_macro 0x0000000000012f20 0x264 Core/Src/main.o + .debug_macro 0x0000000000013184 0x2e Core/Src/main.o + .debug_macro 0x00000000000131b2 0x11a Core/Src/main.o + .debug_macro 0x00000000000132cc 0x85 Core/Src/main.o + .debug_macro 0x0000000000013351 0x89 Core/Src/main.o + .debug_macro 0x00000000000133da 0x31a Core/Src/main.o + .debug_macro 0x00000000000136f4 0x405 Core/Src/main.o + .debug_macro 0x0000000000013af9 0xe4 Core/Src/main.o + .debug_macro 0x0000000000013bdd 0x287 Core/Src/main.o + .debug_macro 0x0000000000013e64 0x126 Core/Src/main.o + .debug_macro 0x0000000000013f8a 0x58 Core/Src/main.o + .debug_macro 0x0000000000013fe2 0x46 Core/Src/main.o + .debug_macro 0x0000000000014028 0x18 Core/Src/main.o + .debug_macro 0x0000000000014040 0x3c Core/Src/main.o + .debug_macro 0x000000000001407c 0x34 Core/Src/main.o + .debug_macro 0x00000000000140b0 0x52 Core/Src/main.o + .debug_macro 0x0000000000014102 0x1f Core/Src/main.o + .debug_macro 0x0000000000014121 0x43 Core/Src/main.o + .debug_macro 0x0000000000014164 0x20 Core/Src/main.o + .debug_macro 0x0000000000014184 0x1a3 Core/Src/main.o + .debug_macro 0x0000000000014327 0x32a Core/Src/main.o + .debug_macro 0x0000000000014651 0x1e1 Core/Src/main.o + .debug_macro 0x0000000000014832 0x22 Core/Src/main.o + .debug_macro 0x0000000000014854 0x1e2 Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000014a36 0x1ec Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000014c22 0x1d9 Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000014dfb 0x233 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x000000000001502e 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000015201 0x209 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x000000000001540a 0x1eb Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x00000000000155f5 0x1f7 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x00000000000157ec 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x00000000000159bf 0x1d4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_macro 0x0000000000015b93 0x1d3 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_macro 0x0000000000015d66 0x1d4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_line 0x0000000000000000 0x62c4 - .debug_line 0x0000000000000000 0x755 Core/Src/main.o - .debug_line 0x0000000000000755 0x6fe Core/Src/stm32l1xx_hal_msp.o - .debug_line 0x0000000000000e53 0x74b Core/Src/stm32l1xx_it.o - .debug_line 0x000000000000159e 0x6c6 Core/Src/system_stm32l1xx.o - .debug_line 0x0000000000001c64 0x84 Core/Startup/startup_stm32l152retx.o - .debug_line 0x0000000000001ce8 0x885 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_line 0x000000000000256d 0x9ce Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_line 0x0000000000002f3b 0x85f Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_line 0x000000000000379a 0x9b0 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_line 0x000000000000414a 0x7a8 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_line 0x00000000000048f2 0xa3d Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_line 0x000000000000532f 0xf95 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o +.debug_line 0x0000000000000000 0x7bf1 + .debug_line 0x0000000000000000 0xa11 Core/Src/main.o + .debug_line 0x0000000000000a11 0x71a Core/Src/stm32f4xx_hal_msp.o + .debug_line 0x000000000000112b 0x77b Core/Src/stm32f4xx_it.o + .debug_line 0x00000000000018a6 0x6dc Core/Src/system_stm32f4xx.o + .debug_line 0x0000000000001f82 0x85 Core/Startup/startup_stm32f401retx.o + .debug_line 0x0000000000002007 0x8c6 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_line 0x00000000000028cd 0x9ea Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_line 0x00000000000032b7 0x869 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_line 0x0000000000003b20 0x80d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_line 0x000000000000432d 0x91e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_line 0x0000000000004c4b 0x7e9 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_line 0x0000000000005434 0xa56 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_line 0x0000000000005e8a 0xd93 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_line 0x0000000000006c1d 0xfd4 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_str 0x0000000000000000 0x859c4 - .debug_str 0x0000000000000000 0x84049 Core/Src/main.o - 0x84326 (size before relaxing) - .debug_str 0x0000000000084049 0x78 Core/Src/stm32l1xx_hal_msp.o - 0x84094 (size before relaxing) - .debug_str 0x00000000000840c1 0xbd Core/Src/stm32l1xx_it.o - 0x83a37 (size before relaxing) - .debug_str 0x000000000008417e 0xd5 Core/Src/system_stm32l1xx.o - 0x83984 (size before relaxing) - .debug_str 0x0000000000084253 0x36 Core/Startup/startup_stm32l152retx.o - 0x7c (size before relaxing) - .debug_str 0x0000000000084289 0x652 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - 0x84003 (size before relaxing) - .debug_str 0x00000000000848db 0x3c1 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - 0x84135 (size before relaxing) - .debug_str 0x0000000000084c9c 0x214 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - 0x83ba8 (size before relaxing) - .debug_str 0x0000000000084eb0 0x2a7 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - 0x83d9a (size before relaxing) - .debug_str 0x0000000000085157 0x130 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - 0x83adf (size before relaxing) - .debug_str 0x0000000000085287 0x216 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - 0x83e0b (size before relaxing) - .debug_str 0x000000000008549d 0x527 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - 0x841cd (size before relaxing) +.debug_str 0x0000000000000000 0x89db1 + .debug_str 0x0000000000000000 0x87a8c Core/Src/main.o + 0x87eaf (size before relaxing) + .debug_str 0x0000000000087a8c 0x3fa Core/Src/stm32f4xx_hal_msp.o + 0x84540 (size before relaxing) + .debug_str 0x0000000000087e86 0xd2 Core/Src/stm32f4xx_it.o + 0x83cbd (size before relaxing) + .debug_str 0x0000000000087f58 0xc4 Core/Src/system_stm32f4xx.o + 0x83a7c (size before relaxing) + .debug_str 0x000000000008801c 0x6b Core/Startup/startup_stm32f401retx.o + .debug_str 0x0000000000088087 0x58d Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + 0x843e7 (size before relaxing) + .debug_str 0x0000000000088614 0x399 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x841c4 (size before relaxing) + .debug_str 0x00000000000889ad 0x20c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x83cbb (size before relaxing) + .debug_str 0x0000000000088bb9 0x25e Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + 0x83cbf (size before relaxing) + .debug_str 0x0000000000088e17 0x259 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x83e69 (size before relaxing) + .debug_str 0x0000000000089070 0x113 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + 0x83bc2 (size before relaxing) + .debug_str 0x0000000000089183 0x190 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + 0x83e17 (size before relaxing) + .debug_str 0x0000000000089313 0x577 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + 0x8415d (size before relaxing) + .debug_str 0x000000000008988a 0x527 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + 0x842b6 (size before relaxing) .comment 0x0000000000000000 0x7b .comment 0x0000000000000000 0x7b Core/Src/main.o 0x7c (size before relaxing) - .comment 0x000000000000007b 0x7c Core/Src/stm32l1xx_hal_msp.o - .comment 0x000000000000007b 0x7c Core/Src/stm32l1xx_it.o - .comment 0x000000000000007b 0x7c Core/Src/system_stm32l1xx.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .comment 0x000000000000007b 0x7c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o + .comment 0x000000000000007b 0x7c Core/Src/stm32f4xx_hal_msp.o + .comment 0x000000000000007b 0x7c Core/Src/stm32f4xx_it.o + .comment 0x000000000000007b 0x7c Core/Src/system_stm32f4xx.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .comment 0x000000000000007b 0x7c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o -.debug_frame 0x0000000000000000 0x1b48 - .debug_frame 0x0000000000000000 0xd0 Core/Src/main.o - .debug_frame 0x00000000000000d0 0xcc Core/Src/stm32l1xx_hal_msp.o - .debug_frame 0x000000000000019c 0x10c Core/Src/stm32l1xx_it.o - .debug_frame 0x00000000000002a8 0x58 Core/Src/system_stm32l1xx.o - .debug_frame 0x0000000000000300 0x33c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o - .debug_frame 0x000000000000063c 0x498 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o - .debug_frame 0x0000000000000ad4 0x14c Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o - .debug_frame 0x0000000000000c20 0x220 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o - .debug_frame 0x0000000000000e40 0x120 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o - .debug_frame 0x0000000000000f60 0x308 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o - .debug_frame 0x0000000000001268 0x834 Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o - .debug_frame 0x0000000000001a9c 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-init.o) - .debug_frame 0x0000000000001ac8 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7-m\libc_nano.a(lib_a-memset.o) - .debug_frame 0x0000000000001ae8 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_aeabi_uldivmod.o) - .debug_frame 0x0000000000001b14 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.4.0.202007081208/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7-m\libgcc.a(_udivmoddi4.o) +.debug_frame 0x0000000000000000 0x29c4 + .debug_frame 0x0000000000000000 0x22c Core/Src/main.o + .debug_frame 0x000000000000022c 0xc4 Core/Src/stm32f4xx_hal_msp.o + .debug_frame 0x00000000000002f0 0x120 Core/Src/stm32f4xx_it.o + .debug_frame 0x0000000000000410 0x58 Core/Src/system_stm32f4xx.o + .debug_frame 0x0000000000000468 0x374 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_frame 0x00000000000007dc 0x498 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_frame 0x0000000000000c74 0x14c Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_frame 0x0000000000000dc0 0x254 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_frame 0x0000000000001014 0x1f0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_frame 0x0000000000001204 0xf0 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_frame 0x00000000000012f4 0x308 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o + .debug_frame 0x00000000000015fc 0x548 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o + .debug_frame 0x0000000000001b44 0x844 Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_frame 0x0000000000002388 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-errno.o) + .debug_frame 0x00000000000023a8 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-init.o) + .debug_frame 0x00000000000023d4 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libc_nano.a(lib_a-memset.o) + .debug_frame 0x00000000000023f4 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_cos.o) + .debug_frame 0x0000000000002420 0x30 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_floor.o) + .debug_frame 0x0000000000002450 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_sin.o) + .debug_frame 0x000000000000247c 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_tan.o) + .debug_frame 0x00000000000024a8 0x44 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-w_acos.o) + .debug_frame 0x00000000000024ec 0x38 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_acos.o) + .debug_frame 0x0000000000002524 0x40 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_rem_pio2.o) + .debug_frame 0x0000000000002564 0x30 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-e_sqrt.o) + .debug_frame 0x0000000000002594 0x4c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_cos.o) + .debug_frame 0x00000000000025e0 0x54 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_rem_pio2.o) + .debug_frame 0x0000000000002634 0x40 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_sin.o) + .debug_frame 0x0000000000002674 0x40 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-k_tan.o) + .debug_frame 0x00000000000026b4 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_fabs.o) + .debug_frame 0x00000000000026d4 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_matherr.o) + .debug_frame 0x00000000000026f4 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_nan.o) + .debug_frame 0x0000000000002714 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_scalbn.o) + .debug_frame 0x0000000000002740 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/fpv4-sp/hard\libm.a(lib_a-s_copysign.o) + .debug_frame 0x0000000000002760 0xac c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_addsubdf3.o) + .debug_frame 0x000000000000280c 0x50 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_muldivdf3.o) + .debug_frame 0x000000000000285c 0xc4 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_cmpdf2.o) + .debug_frame 0x0000000000002920 0x20 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_unorddf2.o) + .debug_frame 0x0000000000002940 0x24 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_arm_fixdfsi.o) + .debug_frame 0x0000000000002964 0x2c c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x0000000000002990 0x34 c:/st/stm32cubeide_1.4.0/stm32cubeide/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.7-2018-q2-update.win32_1.5.0.202011040924/tools/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v7e-m/fpv4-sp/hard\libgcc.a(_udivmoddi4.o) diff --git a/RTC/Debug/makefile b/RTC/Debug/makefile index a04082e..9c6e96b 100644 --- a/RTC/Debug/makefile +++ b/RTC/Debug/makefile @@ -8,7 +8,7 @@ RM := rm -rf # All of the sources participating in the build are defined here -include sources.mk --include Drivers/STM32L1xx_HAL_Driver/Src/subdir.mk +-include Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk -include Core/Startup/subdir.mk -include Core/Src/subdir.mk -include subdir.mk @@ -28,6 +28,11 @@ endif -include ../makefile.defs +BUILD_ARTIFACT_NAME := RTC +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME).$(BUILD_ARTIFACT_EXTENSION) + # Add inputs and outputs from these tool invocations to the build variables EXECUTABLES += \ RTC.elf \ @@ -43,11 +48,14 @@ RTC.bin \ # All Target -all: RTC.elf secondary-outputs +all: main-build + +# Main-build Target +main-build: RTC.elf secondary-outputs # Tool invocations -RTC.elf: $(OBJS) $(USER_OBJS) C:\Users\Gregor\Desktop\Projektarbeit\Workspace_Solar_Panel\RTC\STM32L152RETX_FLASH.ld - arm-none-eabi-gcc -o "RTC.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m3 -T"C:\Users\Gregor\Desktop\Projektarbeit\Workspace_Solar_Panel\RTC\STM32L152RETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="RTC.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group +RTC.elf: $(OBJS) $(USER_OBJS) C:\Users\Gregor\Desktop\Projektarbeit\Workspace\RTC\STM32F401RETX_FLASH.ld + arm-none-eabi-gcc -o "RTC.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"C:\Users\Gregor\Desktop\Projektarbeit\Workspace\RTC\STM32F401RETX_FLASH.ld" --specs=nosys.specs -Wl,-Map="RTC.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -Wl,--end-group @echo 'Finished building target: $@' @echo ' ' @@ -73,7 +81,14 @@ clean: secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) $(OBJCOPY_BIN) -.PHONY: all clean dependents +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents fail-specified-linker-script-missing warn-no-linker-script-specified .SECONDARY: -include ../makefile.targets diff --git a/RTC/Debug/objects.list b/RTC/Debug/objects.list index 9527e50..8c5be49 100644 --- a/RTC/Debug/objects.list +++ b/RTC/Debug/objects.list @@ -1,24 +1,25 @@ "Core/Src/main.o" -"Core/Src/stm32l1xx_hal_msp.o" -"Core/Src/stm32l1xx_it.o" +"Core/Src/stm32f4xx_hal_msp.o" +"Core/Src/stm32f4xx_it.o" "Core/Src/syscalls.o" "Core/Src/sysmem.o" -"Core/Src/system_stm32l1xx.o" -"Core/Startup/startup_stm32l152retx.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.o" -"Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.o" +"Core/Src/system_stm32f4xx.o" +"Core/Startup/startup_stm32f401retx.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rtc_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" +"Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o" diff --git a/RTC/Debug/sources.mk b/RTC/Debug/sources.mk index db270a2..90bb192 100644 --- a/RTC/Debug/sources.mk +++ b/RTC/Debug/sources.mk @@ -21,5 +21,5 @@ OBJCOPY_BIN := SUBDIRS := \ Core/Src \ Core/Startup \ -Drivers/STM32L1xx_HAL_Driver/Src \ +Drivers/STM32F4xx_HAL_Driver/Src \ diff --git a/RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h b/RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h deleted file mode 100644 index 89f2e37..0000000 --- a/RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/stm32l152xe.h +++ /dev/null @@ -1,8917 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l152xe.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L1xx devices. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l152xe - * @{ - */ - -#ifndef __STM32L152xE_H -#define __STM32L152xE_H - -#ifdef __cplusplus - extern "C" { -#endif - - - /** @addtogroup Configuration_section_for_CMSIS - * @{ - */ -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x200U /*!< Cortex-M3 Revision r2p0 */ -#define __MPU_PRESENT 1U /*!< STM32L1xx provides MPU */ -#define __NVIC_PRIO_BITS 4U /*!< STM32L1xx uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ - -/** - * @} - */ - -/** @addtogroup Peripheral_interrupt_number_definition - * @{ - */ - -/** - * @brief STM32L1xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ - - /*!< Interrupt Number Definition */ -typedef enum -{ -/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ - -/****** STM32L specific Interrupt Numbers ***********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ - DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ - DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ - DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ - DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ - DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ - DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ - ADC1_IRQn = 18, /*!< ADC1 global Interrupt */ - USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */ - USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */ - DAC_IRQn = 21, /*!< DAC Interrupt */ - COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - LCD_IRQn = 24, /*!< LCD Interrupt */ - TIM9_IRQn = 25, /*!< TIM9 global Interrupt */ - TIM10_IRQn = 26, /*!< TIM10 global Interrupt */ - TIM11_IRQn = 27, /*!< TIM11 global Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ - USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */ - TIM6_IRQn = 43, /*!< TIM6 global Interrupt */ - TIM7_IRQn = 44, /*!< TIM7 global Interrupt */ - TIM5_IRQn = 46, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 47, /*!< SPI3 global Interrupt */ - UART4_IRQn = 48, /*!< UART4 global Interrupt */ - UART5_IRQn = 49, /*!< UART5 global Interrupt */ - DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */ - DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */ - DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */ - DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */ - DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */ - COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm3.h" -#include "system_stm32l1xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ - __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */ - __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ -} ADC_Common_TypeDef; - -/** - * @brief Comparator - */ - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ -} COMP_Common_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ - uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ -} DMA_Channel_TypeDef; - -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*! 0x7C */ - __IO uint32_t WRP1213; /*!< write protection register 12 13, Address offset: 0x80 */ - __IO uint32_t WRP1415; /*!< write protection register 14 15, Address offset: 0x84 */ -} OB_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control and status register, used for bits common to several OPAMP instances, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */ -} OPAMP_Common_TypeDef; - -/** - * @brief General Purpose IO - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ -} GPIO_TypeDef; - -/** - * @brief SysTem Configuration - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ - __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief LCD - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */ - __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */ - __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */ - __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */ -} LCD_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */ - __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */ - __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */ - __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */ -} RCC_TypeDef; - -/** - * @brief Routing Interface - */ - -typedef struct -{ - __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */ - __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */ - __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */ - __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */ - __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */ - __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */ - __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */ - __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */ - __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */ - __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */ - __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */ - __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */ - __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */ - __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */ - __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */ - __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */ - __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x40 */ - __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x44 */ - __IO uint32_t CICR4; /*!< RI Channel Iden for capture register 4, Address offset: 0x48 */ - __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x4C */ - __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x50 */ - __IO uint32_t CICR5; /*!< RI Channel Iden for capture register 5, Address offset: 0x54 */ -} RI_TypeDef; - -/** - * @brief Real-Time Clock - */ -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - uint32_t RESERVED12; /*!< Reserved, 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - uint32_t RESERVED17; /*!< Reserved, 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ -} TIM_TypeDef; -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ -} USART_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ - -typedef struct -{ - __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ - __IO uint16_t RESERVED0; /*!< Reserved */ - __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ - __IO uint16_t RESERVED1; /*!< Reserved */ - __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ - __IO uint16_t RESERVED2; /*!< Reserved */ - __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ - __IO uint16_t RESERVED3; /*!< Reserved */ - __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ - __IO uint16_t RESERVED4; /*!< Reserved */ - __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ - __IO uint16_t RESERVED5; /*!< Reserved */ - __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ - __IO uint16_t RESERVED6; /*!< Reserved */ - __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ - __IO uint16_t RESERVED7[17]; /*!< Reserved */ - __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ - __IO uint16_t RESERVED8; /*!< Reserved */ - __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ - __IO uint16_t RESERVED9; /*!< Reserved */ - __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ - __IO uint16_t RESERVEDA; /*!< Reserved */ - __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ - __IO uint16_t RESERVEDB; /*!< Reserved */ - __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ - __IO uint16_t RESERVEDC; /*!< Reserved */ -} USB_TypeDef; - -/** - * @brief Window WATCHDOG - */ -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Universal Serial Bus Full Speed Device - */ -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE (0x08000000UL) /*!< FLASH base address in the alias region */ -#define FLASH_EEPROM_BASE (FLASH_BASE + 0x80000UL) /*!< FLASH EEPROM base address in the alias region */ -#define SRAM_BASE (0x20000000UL) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address in the alias region */ -#define SRAM_BB_BASE (0x22000000UL) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */ -#define FLASH_BANK2_BASE (0x08040000UL) /*!< FLASH BANK2 base address in the alias region */ -#define FLASH_BANK1_END (0x0803FFFFUL) /*!< Program end FLASH BANK1 address */ -#define FLASH_BANK2_END (0x0807FFFFUL) /*!< Program end FLASH BANK2 address */ -#define FLASH_EEPROM_END (0x08083FFFUL) /*!< FLASH EEPROM end address (16KB) */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) -#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) -#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) -#define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) -#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) -#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) -#define LCD_BASE (APB1PERIPH_BASE + 0x00002400UL) -#define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) -#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) -#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) -#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) -#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) -#define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) -#define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) -#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) -#define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) -#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) -#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) - -/* USB device FS */ -#define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */ -#define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */ - -/* USB device FS SRAM */ -#define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) -#define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) -#define COMP_BASE (APB1PERIPH_BASE + 0x00007C00UL) -#define RI_BASE (APB1PERIPH_BASE + 0x00007C04UL) -#define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5CUL) - -/*!< APB2 peripherals */ -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000UL) -#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) -#define TIM9_BASE (APB2PERIPH_BASE + 0x00000800UL) -#define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00UL) -#define TIM11_BASE (APB2PERIPH_BASE + 0x00001000UL) -#define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) -#define ADC_BASE (APB2PERIPH_BASE + 0x00002700UL) -#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) -#define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) - -/*!< AHB peripherals */ -#define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000UL) -#define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400UL) -#define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800UL) -#define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00UL) -#define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000UL) -#define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400UL) -#define GPIOF_BASE (AHBPERIPH_BASE + 0x00001800UL) -#define GPIOG_BASE (AHBPERIPH_BASE + 0x00001C00UL) -#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) -#define RCC_BASE (AHBPERIPH_BASE + 0x00003800UL) -#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00UL) /*!< FLASH registers base address */ -#define OB_BASE (0x1FF80000UL) /*!< FLASH Option Bytes base address */ -#define FLASHSIZE_BASE (0x1FF800CCUL) /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ -#define UID_BASE (0x1FF800D0UL) /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */ -#define DMA1_BASE (AHBPERIPH_BASE + 0x00006000UL) -#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) -#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) -#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) -#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) -#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) -#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) -#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) -#define DMA2_BASE (AHBPERIPH_BASE + 0x00006400UL) -#define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008UL) -#define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001CUL) -#define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030UL) -#define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044UL) -#define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058UL) -#define DBGMCU_BASE (0xE0042000UL) /*!< Debug MCU registers base address */ - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ - -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define LCD ((LCD_TypeDef *) LCD_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -/* USB device FS */ -#define USB ((USB_TypeDef *) USB_BASE) -/* USB device FS SRAM */ -#define PWR ((PWR_TypeDef *) PWR_BASE) - -#define DAC1 ((DAC_TypeDef *) DAC_BASE) -/* Legacy define */ -#define DAC DAC1 - -#define COMP ((COMP_TypeDef *) COMP_BASE) /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */ -#define COMP1 ((COMP_TypeDef *) COMP_BASE) /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ -#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */ -#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP_BASE) /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */ - -#define RI ((RI_TypeDef *) RI_BASE) - -#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE) -#define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U)) -#define OPAMP12_COMMON ((OPAMP_Common_TypeDef *) OPAMP_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) - -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) -/* Legacy defines */ -#define ADC ADC1_COMMON - -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define OB ((OB_TypeDef *) OB_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) -#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) -#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) -#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) -#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) -#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) -#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) -#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) -#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) -#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) -#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - - /** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - -/** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers Bits Definition */ -/******************************************************************************/ -/******************************************************************************/ -/* */ -/* Analog to Digital Converter (ADC) */ -/* */ -/******************************************************************************/ -#define VREFINT_CAL_ADDR_CMSIS 0x1FF800F8 /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx - * @{ - */ - -#ifndef __STM32L1XX_H -#define __STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32L1) -#define STM32L1 -#endif /* STM32L1 */ - - -/* Uncomment the line below according to the target STM32L device used in your - application - */ - -#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \ - !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xDX) && !defined (STM32L151xE) && \ - !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xDX) && !defined (STM32L152xE) && \ - !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xDX) && !defined (STM32L162xE) - /* #define STM32L100xB */ /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */ - /* #define STM32L100xBA */ /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */ - /* #define STM32L100xC */ /*!< STM32L100RC Devices */ - /* #define STM32L151xB */ /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */ - /* #define STM32L151xBA */ /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ - /* #define STM32L151xC */ /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */ - /* #define STM32L151xCA */ /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */ - /* #define STM32L151xD */ /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */ - /* #define STM32L151xDX */ /*!< STM32L151VD-X Devices */ - /* #define STM32L151xE */ /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */ - /* #define STM32L152xB */ /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */ - /* #define STM32L152xBA */ /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */ - /* #define STM32L152xC */ /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */ - /* #define STM32L152xCA */ /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */ - /* #define STM32L152xD */ /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */ - /* #define STM32L152xDX */ /*!< STM32L152VD-X Devices */ - /* #define STM32L152xE */ /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */ - /* #define STM32L162xC */ /*!< STM32L162RC and STM32L162VC */ - /* #define STM32L162xCA */ /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */ - /* #define STM32L162xD */ /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */ - /* #define STM32L162xDX */ /*!< STM32L162VD-X Devices */ - /* #define STM32L162xE */ /*!< STM32L162RE, STM32L162VE and STM32L162ZE */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number V2.3.1 - */ -#define __STM32L1xx_CMSIS_VERSION_MAIN (0x02) /*!< [31:24] main version */ -#define __STM32L1xx_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32L1xx_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32L1xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_CMSIS_VERSION ((__STM32L1xx_CMSIS_VERSION_MAIN << 24)\ - |(__STM32L1xx_CMSIS_VERSION_SUB1 << 16)\ - |(__STM32L1xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32L100xB) - #include "stm32l100xb.h" -#elif defined(STM32L100xBA) - #include "stm32l100xba.h" -#elif defined(STM32L100xC) - #include "stm32l100xc.h" -#elif defined(STM32L151xB) - #include "stm32l151xb.h" -#elif defined(STM32L151xBA) - #include "stm32l151xba.h" -#elif defined(STM32L151xC) - #include "stm32l151xc.h" -#elif defined(STM32L151xCA) - #include "stm32l151xca.h" -#elif defined(STM32L151xD) - #include "stm32l151xd.h" -#elif defined(STM32L151xDX) - #include "stm32l151xdx.h" -#elif defined(STM32L151xE) - #include "stm32l151xe.h" -#elif defined(STM32L152xB) - #include "stm32l152xb.h" -#elif defined(STM32L152xBA) - #include "stm32l152xba.h" -#elif defined(STM32L152xC) - #include "stm32l152xc.h" -#elif defined(STM32L152xCA) - #include "stm32l152xca.h" -#elif defined(STM32L152xD) - #include "stm32l152xd.h" -#elif defined(STM32L152xDX) - #include "stm32l152xdx.h" -#elif defined(STM32L152xE) - #include "stm32l152xe.h" -#elif defined(STM32L162xC) - #include "stm32l162xc.h" -#elif defined(STM32L162xCA) - #include "stm32l162xca.h" -#elif defined(STM32L162xD) - #include "stm32l162xd.h" -#elif defined(STM32L162xDX) - #include "stm32l162xdx.h" -#elif defined(STM32L162xE) - #include "stm32l162xe.h" -#else - #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - SUCCESS = 0, - ERROR = !SUCCESS -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32l1xx_hal.h" -#endif /* USE_HAL_DRIVER */ - - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* __STM32L1xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h b/RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h deleted file mode 100644 index 6fa05ff..0000000 --- a/RTC/Drivers/CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device System Source File for STM32L1xx devices. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32L1XX_H -#define __SYSTEM_STM32L1XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32L1xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32L1xx_System_Exported_types - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -/* -*/ -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint8_t PLLMulTable[9]; /*!< PLL multipiers table values */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32L1XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h deleted file mode 100644 index e57e823..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,3784 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32_HAL_LEGACY -#define STM32_HAL_LEGACY - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR - -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 - -#if defined(STM32H7) -#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT -#endif /* STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -#if defined(STM32G4) || defined(STM32H7) -#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL -#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL -#endif - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) -#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID -#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID -#endif - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - -#if defined(STM32L4) - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif - -#endif /* STM32L4 */ - -#if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 -#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM -#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM - -#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM -#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM -#endif - -#if defined(STM32H7) - -#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - -#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX -#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 -#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT - -#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT -#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) -#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE -#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH -#else -#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE -#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE -#endif -#if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) -#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE -#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE -#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET -#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -#if defined(STM32G4) - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster -#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD -#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD -#endif /* STM32G4 */ -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32H7) -#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 -#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 -#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 -#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 -#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 -#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 - -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ - defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) -#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS -#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS -#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ -#endif /* STM32H7 */ - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/ - -#if defined(STM32L1) - #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) - #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW - #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM - #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE - -#if defined(STM32G4) -#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig -#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable -#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable -#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset -#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A -#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B -#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL -#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL -#endif /* STM32G4 */ - -#if defined(STM32H7) -#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 - -#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 -#endif /* STM32H7 */ - -#if defined(STM32F3) -/** @brief Constants defining available sources associated to external events. - */ -#define HRTIM_EVENTSRC_1 (0x00000000U) -#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) -#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) -#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) - -/** @brief Constants defining the events that can be selected to configure the - * set/reset crossbar of a timer output - */ -#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) -#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) -#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) -#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) -#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) -#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) -#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) -#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) -#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) - -#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) -#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) -#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) -#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) -#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) -#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) -#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) -#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) -#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) - -/** @brief Constants defining the event filtering applied to external events - * by a timer - */ -#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) -#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) -#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) - -/** @brief Constants defining the DLL calibration periods (in micro seconds) - */ -#define HRTIM_CALIBRATIONRATE_7300 0x00000000U -#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) -#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) -#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - -#endif /* STM32F3 */ -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) -#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID -#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID -#endif - - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS - -#if defined(STM32H7) - #define I2S_IT_TXE I2S_IT_TXP - #define I2S_IT_RXNE I2S_IT_RXP - - #define I2S_FLAG_TXE I2S_FLAG_TXP - #define I2S_FLAG_RXNE I2S_FLAG_RXP -#endif - -#if defined(STM32F7) - #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -#if defined(STM32H7) -#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X -#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT - -#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 -#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 -#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -#if defined(STM32H7) - - #define SPI_FLAG_TXE SPI_FLAG_TXP - #define SPI_FLAG_RXNE SPI_FLAG_RXP - - #define SPI_IT_TXE SPI_IT_TXP - #define SPI_IT_RXNE SPI_IT_RXP - - #define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET - #define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET - #define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET - #define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -#if defined(STM32L0) -#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO -#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO -#endif - -#if defined(STM32F3) -#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE -#endif - -#if defined(STM32H7) -#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 -#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 -#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 -#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 -#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 -#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 -#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 -#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 -#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 -#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 -#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 -#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 -#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 -#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 -#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 -#endif - -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY - -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) - -#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt -#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End -#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT -#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT - -#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt -#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End -#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT -#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT - -#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt -#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End -#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT -#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT - -#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt -#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End -#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT -#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT - -#endif /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) -#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode -#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode -#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode -#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode -#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - - /** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT -#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT -#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT -#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA -#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA -#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA -#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ - -#if defined(STM32F4) -#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT -#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT -#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT -#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT -#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA -#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA -#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA -#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA -#endif /* STM32F4 */ - /** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ - -#if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler -#endif -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - - /** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) -#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro -#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT -#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback -#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent -#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT -#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#if defined(STM32H7) - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 -#else - #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG - #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG - #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG - #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#endif /* STM32H7 */ -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -#if defined(STM32H7) - #define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG -#endif - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET - -#if defined(STM32H7) -#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE -#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE - -#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ -#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ - - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED -#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED -#endif - -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET - -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32L1) -#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#endif /* STM32L1 */ - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) || defined(STM32L5) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose - * @{ - */ -#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop -#endif -/** - * @} - */ - -/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) -#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif /* STM32L4 || STM32F4 || STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_HAL_LEGACY */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h deleted file mode 100644 index e3d4967..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal.h +++ /dev/null @@ -1,996 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_H -#define __STM32L1xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_conf.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -/** @defgroup HAL_TICK_FREQ Tick Frequency - * @{ - */ -#define HAL_TICK_FREQ_10HZ 100U -#define HAL_TICK_FREQ_100HZ 10U -#define HAL_TICK_FREQ_1KHZ 1U -#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ - -#define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ) || \ - ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \ - ((__FREQ__) == HAL_TICK_FREQ_1KHZ)) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants - * @{ - */ - -/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG - * @{ - */ - -/** @defgroup SYSCFG_BootMode Boot Mode - * @{ - */ - -#define SYSCFG_BOOT_MAINFLASH (0x00000000U) -#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0) -#if defined(FSMC_R_BASE) -#define SYSCFG_BOOT_FSMC ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1) -#endif /* FSMC_R_BASE */ -#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RI_Constants RI: Routing Interface - * @{ - */ - -/** @defgroup RI_InputCapture Input Capture - * @{ - */ - -#define RI_INPUTCAPTURE_IC1 RI_ICR_IC1 /*!< Input Capture 1 */ -#define RI_INPUTCAPTURE_IC2 RI_ICR_IC2 /*!< Input Capture 2 */ -#define RI_INPUTCAPTURE_IC3 RI_ICR_IC3 /*!< Input Capture 3 */ -#define RI_INPUTCAPTURE_IC4 RI_ICR_IC4 /*!< Input Capture 4 */ - -/** - * @} - */ - -/** @defgroup TIM_Select TIM Select - * @{ - */ - -#define TIM_SELECT_NONE (0x00000000U) /*!< None selected */ -#define TIM_SELECT_TIM2 ((uint32_t)RI_ICR_TIM_0) /*!< Timer 2 selected */ -#define TIM_SELECT_TIM3 ((uint32_t)RI_ICR_TIM_1) /*!< Timer 3 selected */ -#define TIM_SELECT_TIM4 ((uint32_t)RI_ICR_TIM) /*!< Timer 4 selected */ - -#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \ - ((__TIM__) == TIM_SELECT_TIM2) || \ - ((__TIM__) == TIM_SELECT_TIM3) || \ - ((__TIM__) == TIM_SELECT_TIM4)) - -/** - * @} - */ - -/** @defgroup RI_InputCaptureRouting Input Capture Routing - * @{ - */ - /* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */ -#define RI_INPUTCAPTUREROUTING_0 (0x00000000U) /* PA0 PA1 PA2 PA3 */ -#define RI_INPUTCAPTUREROUTING_1 (0x00000001U) /* PA4 PA5 PA6 PA7 */ -#define RI_INPUTCAPTUREROUTING_2 (0x00000002U) /* PA8 PA9 PA10 PA11 */ -#define RI_INPUTCAPTUREROUTING_3 (0x00000003U) /* PA12 PA13 PA14 PA15 */ -#define RI_INPUTCAPTUREROUTING_4 (0x00000004U) /* PC0 PC1 PC2 PC3 */ -#define RI_INPUTCAPTUREROUTING_5 (0x00000005U) /* PC4 PC5 PC6 PC7 */ -#define RI_INPUTCAPTUREROUTING_6 (0x00000006U) /* PC8 PC9 PC10 PC11 */ -#define RI_INPUTCAPTUREROUTING_7 (0x00000007U) /* PC12 PC13 PC14 PC15 */ -#define RI_INPUTCAPTUREROUTING_8 (0x00000008U) /* PD0 PD1 PD2 PD3 */ -#define RI_INPUTCAPTUREROUTING_9 (0x00000009U) /* PD4 PD5 PD6 PD7 */ -#define RI_INPUTCAPTUREROUTING_10 (0x0000000AU) /* PD8 PD9 PD10 PD11 */ -#define RI_INPUTCAPTUREROUTING_11 (0x0000000BU) /* PD12 PD13 PD14 PD15 */ -#define RI_INPUTCAPTUREROUTING_12 (0x0000000CU) /* PE0 PE1 PE2 PE3 */ -#define RI_INPUTCAPTUREROUTING_13 (0x0000000DU) /* PE4 PE5 PE6 PE7 */ -#define RI_INPUTCAPTUREROUTING_14 (0x0000000EU) /* PE8 PE9 PE10 PE11 */ -#define RI_INPUTCAPTUREROUTING_15 (0x0000000FU) /* PE12 PE13 PE14 PE15 */ - -#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \ - ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15)) - -/** - * @} - */ - -/** @defgroup RI_IOSwitch IO Switch - * @{ - */ -#define RI_ASCR1_REGISTER (0x80000000U) -/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */ -#define RI_IOSWITCH_CH0 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0) -#define RI_IOSWITCH_CH1 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1) -#define RI_IOSWITCH_CH2 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2) -#define RI_IOSWITCH_CH3 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3) -#define RI_IOSWITCH_CH4 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4) -#define RI_IOSWITCH_CH5 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5) -#define RI_IOSWITCH_CH6 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6) -#define RI_IOSWITCH_CH7 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7) -#define RI_IOSWITCH_CH8 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8) -#define RI_IOSWITCH_CH9 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9) -#define RI_IOSWITCH_CH10 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10) -#define RI_IOSWITCH_CH11 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11) -#define RI_IOSWITCH_CH12 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12) -#define RI_IOSWITCH_CH13 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13) -#define RI_IOSWITCH_CH14 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14) -#define RI_IOSWITCH_CH15 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15) -#define RI_IOSWITCH_CH18 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18) -#define RI_IOSWITCH_CH19 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19) -#define RI_IOSWITCH_CH20 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20) -#define RI_IOSWITCH_CH21 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21) -#define RI_IOSWITCH_CH22 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22) -#define RI_IOSWITCH_CH23 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23) -#define RI_IOSWITCH_CH24 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24) -#define RI_IOSWITCH_CH25 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25) -#define RI_IOSWITCH_VCOMP ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */ -#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ -#define RI_IOSWITCH_CH27 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27) -#define RI_IOSWITCH_CH28 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28) -#define RI_IOSWITCH_CH29 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29) -#define RI_IOSWITCH_CH30 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30) -#define RI_IOSWITCH_CH31 ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31) -#endif /* RI_ASCR2_CH1b */ - -/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */ -#define RI_IOSWITCH_GR10_1 ((uint32_t)RI_ASCR2_GR10_1) -#define RI_IOSWITCH_GR10_2 ((uint32_t)RI_ASCR2_GR10_2) -#define RI_IOSWITCH_GR10_3 ((uint32_t)RI_ASCR2_GR10_3) -#define RI_IOSWITCH_GR10_4 ((uint32_t)RI_ASCR2_GR10_4) -#define RI_IOSWITCH_GR6_1 ((uint32_t)RI_ASCR2_GR6_1) -#define RI_IOSWITCH_GR6_2 ((uint32_t)RI_ASCR2_GR6_2) -#define RI_IOSWITCH_GR5_1 ((uint32_t)RI_ASCR2_GR5_1) -#define RI_IOSWITCH_GR5_2 ((uint32_t)RI_ASCR2_GR5_2) -#define RI_IOSWITCH_GR5_3 ((uint32_t)RI_ASCR2_GR5_3) -#define RI_IOSWITCH_GR4_1 ((uint32_t)RI_ASCR2_GR4_1) -#define RI_IOSWITCH_GR4_2 ((uint32_t)RI_ASCR2_GR4_2) -#define RI_IOSWITCH_GR4_3 ((uint32_t)RI_ASCR2_GR4_3) -#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */ -#define RI_IOSWITCH_CH0b ((uint32_t)RI_ASCR2_CH0b) -#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ -#define RI_IOSWITCH_CH1b ((uint32_t)RI_ASCR2_CH1b) -#define RI_IOSWITCH_CH2b ((uint32_t)RI_ASCR2_CH2b) -#define RI_IOSWITCH_CH3b ((uint32_t)RI_ASCR2_CH3b) -#define RI_IOSWITCH_CH6b ((uint32_t)RI_ASCR2_CH6b) -#define RI_IOSWITCH_CH7b ((uint32_t)RI_ASCR2_CH7b) -#define RI_IOSWITCH_CH8b ((uint32_t)RI_ASCR2_CH8b) -#define RI_IOSWITCH_CH9b ((uint32_t)RI_ASCR2_CH9b) -#define RI_IOSWITCH_CH10b ((uint32_t)RI_ASCR2_CH10b) -#define RI_IOSWITCH_CH11b ((uint32_t)RI_ASCR2_CH11b) -#define RI_IOSWITCH_CH12b ((uint32_t)RI_ASCR2_CH12b) -#endif /* RI_ASCR2_CH1b */ -#define RI_IOSWITCH_GR6_3 ((uint32_t)RI_ASCR2_GR6_3) -#define RI_IOSWITCH_GR6_4 ((uint32_t)RI_ASCR2_GR6_4) -#endif /* RI_ASCR2_CH0b */ - - -#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */ - -#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ - ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_CH27) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH28) || ((__IOSWITCH__) == RI_IOSWITCH_CH29) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH30) || ((__IOSWITCH__) == RI_IOSWITCH_CH31) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH0b) || ((__IOSWITCH__) == RI_IOSWITCH_CH1b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2b) || ((__IOSWITCH__) == RI_IOSWITCH_CH3b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6b) || ((__IOSWITCH__) == RI_IOSWITCH_CH7b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8b) || ((__IOSWITCH__) == RI_IOSWITCH_CH9b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10b) || ((__IOSWITCH__) == RI_IOSWITCH_CH11b) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12b)) - -#else /* !RI_ASCR2_CH1b */ - -#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */ - -#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ - ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_3) || ((__IOSWITCH__) == RI_IOSWITCH_CH0b)) - -#else /* !RI_ASCR2_CH0b */ /* STM32L1 devices category Cat.1 and Cat.2 */ - -#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH2) || ((__IOSWITCH__) == RI_IOSWITCH_CH3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH4) || ((__IOSWITCH__) == RI_IOSWITCH_CH5) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH6) || ((__IOSWITCH__) == RI_IOSWITCH_CH7) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH8) || ((__IOSWITCH__) == RI_IOSWITCH_CH9) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH10) || ((__IOSWITCH__) == RI_IOSWITCH_CH11) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH12) || ((__IOSWITCH__) == RI_IOSWITCH_CH13) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH14) || ((__IOSWITCH__) == RI_IOSWITCH_CH15) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH18) || ((__IOSWITCH__) == RI_IOSWITCH_CH19) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH20) || ((__IOSWITCH__) == RI_IOSWITCH_CH21) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH22) || ((__IOSWITCH__) == RI_IOSWITCH_CH23) || \ - ((__IOSWITCH__) == RI_IOSWITCH_CH24) || ((__IOSWITCH__) == RI_IOSWITCH_CH25) || \ - ((__IOSWITCH__) == RI_IOSWITCH_VCOMP) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR6_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR5_2) || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_1) || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2) || \ - ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)) - -#endif /* RI_ASCR2_CH0b */ -#endif /* RI_ASCR2_CH1b */ - -/** - * @} - */ - -/** @defgroup RI_Pin PIN define - * @{ - */ -#define RI_PIN_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ -#define RI_PIN_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ -#define RI_PIN_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ -#define RI_PIN_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ -#define RI_PIN_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ -#define RI_PIN_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ -#define RI_PIN_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ -#define RI_PIN_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ -#define RI_PIN_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ -#define RI_PIN_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ -#define RI_PIN_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ -#define RI_PIN_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ -#define RI_PIN_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ -#define RI_PIN_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ -#define RI_PIN_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ -#define RI_PIN_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ -#define RI_PIN_ALL ((uint16_t)0xFFFF) /*!< All pins selected */ - -#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU - * @{ - */ - -/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode - * @brief Freeze/Unfreeze Peripherals in Debug mode - * @{ - */ - -/** - * @brief TIM2 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP) -#endif - -/** - * @brief TIM3 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP) -#endif - -/** - * @brief TIM4 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP) -#endif - -/** - * @brief TIM5 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP) -#endif - -/** - * @brief TIM6 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) -#endif - -/** - * @brief TIM7 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) -#endif - -/** - * @brief RTC Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) -#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) -#endif - -/** - * @brief WWDG Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) -#endif - -/** - * @brief IWDG Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) -#endif - -/** - * @brief I2C1 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) -#endif - -/** - * @brief I2C2 Peripherals Debug mode - */ -#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT) -#endif - -/** - * @brief TIM9 Peripherals Debug mode - */ -#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#define __HAL_DBGMCU_FREEZE_TIM9() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM9() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP) -#endif - -/** - * @brief TIM10 Peripherals Debug mode - */ -#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define __HAL_DBGMCU_FREEZE_TIM10() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM10() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP) -#endif - -/** - * @brief TIM11 Peripherals Debug mode - */ -#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#define __HAL_DBGMCU_FREEZE_TIM11() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM11() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP) -#endif - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG - * @{ - */ - -/** @defgroup SYSCFG_VrefInt VREFINT configuration - * @{ - */ - -/** - * @brief Enables or disables the output of internal reference voltage - * (VrefInt) on I/O pin. - * @note The VrefInt output can be routed to any I/O in group 3: - * - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1). - * - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2). - * - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), - * CH1b (PF11) or CH2b (PF12). - * Note: Comparator peripheral clock must be preliminarily enabled, - * either in COMP user function "HAL_COMP_MspInit()" (should be - * done if comparators are used) or by direct clock enable: - * Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()". - * Note: In addition with this macro, VrefInt output buffer must be - * connected to the selected I/O pin. Refer to macro - * "__HAL_RI_IOSWITCH_CLOSE()". - * @note VrefInt output enable: Internal reference voltage connected to I/O group 3 - * VrefInt output disable: Internal reference voltage disconnected from I/O group 3 - * @retval None - */ -#define __HAL_SYSCFG_VREFINT_OUT_ENABLE() SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) -#define __HAL_SYSCFG_VREFINT_OUT_DISABLE() CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN) - -/** - * @} - */ - -/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration - * @{ - */ - -/** - * @brief Main Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) - -/** @brief System Flash memory mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) - -/** @brief Embedded SRAM mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1) - -#if defined(FSMC_R_BASE) -/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FSMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) - -#endif /* FSMC_R_BASE */ - -/** - * @brief Returns the boot mode as configured by user. - * @retval The boot mode as configured by user. The returned value can be one - * of the following values: - * @arg SYSCFG_BOOT_MAINFLASH - * @arg SYSCFG_BOOT_SYSTEMFLASH - * @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD) - * @arg SYSCFG_BOOT_SRAM - */ -#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE) - -/** - * @} - */ - -/** @defgroup SYSCFG_USBConfig USB DP line Configuration - * @{ - */ - -/** - * @brief Control the internal pull-up on USB DP line. - */ -#define __HAL_SYSCFG_USBPULLUP_ENABLE() SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) - -#define __HAL_SYSCFG_USBPULLUP_DISABLE() CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU) - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RI_Macris RI: Routing Interface - * @{ - */ - -/** @defgroup RI_InputCaputureConfig Input Capture configuration - * @{ - */ - -/** - * @brief Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin. - * @param __TIMSELECT__ Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__ selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * e.g. - * __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1) - * allows routing of Input capture IC1 of TIM2 to PA4. - * For details about correspondence between RI_INPUTCAPTUREROUTING_x - * and I/O pins refer to the parameters' description in the header file - * or refer to the product reference manual. - * @note Input capture selection bits are not reset by this function. - * To reset input capture selection bits, use SYSCFG_RIDeInit() function. - * @note The I/O should be configured in alternate function mode (AF14) using - * GPIO_PinAFConfig() function. - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \ - MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \ - }while(0) - -/** - * @brief Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin. - * @param __TIMSELECT__ Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__ selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \ - MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \ - }while(0) - -/** - * @brief Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin. - * @param __TIMSELECT__ Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__ selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \ - MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \ - }while(0) - -/** - * @brief Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin. - * @param __TIMSELECT__ Timer select. - * This parameter can be one of the following values: - * @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled. - * @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed. - * @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed. - * @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed. - * @param __INPUT__ selects which pin to be routed to Input Capture. - * This parameter must be a value of @ref RI_InputCaptureRouting - * @retval None. - */ -#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__) \ - do {assert_param(IS_RI_TIM(__TIMSELECT__)); \ - assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \ - MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \ - SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \ - MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \ - }while(0) - -/** - * @} - */ - -/** @defgroup RI_SwitchControlConfig Switch Control configuration - * @{ - */ - -/** - * @brief Enable or disable the switch control mode. - * @note ENABLE: ADC analog switches closed if the corresponding - * I/O switch is also closed. - * When using COMP1, switch control mode must be enabled. - * @note DISABLE: ADC analog switches open or controlled by the ADC interface. - * When using the ADC for acquisition, switch control mode - * must be disabled. - * @note COMP1 comparator and ADC cannot be used at the same time since - * they share the ADC switch matrix. - * @retval None - */ -#define __HAL_RI_SWITCHCONTROLMODE_ENABLE() SET_BIT(RI->ASCR1, RI_ASCR1_SCM) - -#define __HAL_RI_SWITCHCONTROLMODE_DISABLE() CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM) - -/* - * @brief Close or Open the routing interface Input Output switches. - * @param __IOSWITCH__ selects the I/O analog switch number. - * This parameter must be a value of @ref RI_IOSwitch - * @retval None - */ -#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ - if ((__IOSWITCH__) >> 31 != 0 ) \ - { \ - SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ - } \ - else \ - { \ - SET_BIT(RI->ASCR2, (__IOSWITCH__)); \ - } \ - }while(0) - -#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \ - if ((__IOSWITCH__) >> 31 != 0 ) \ - { \ - CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \ - } \ - else \ - { \ - CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \ - } \ - }while(0) - -#if defined (COMP_CSR_SW1) -/** - * @brief Close or open the internal switch COMP1_SW1. - * This switch connects I/O pin PC3 (can be used as ADC channel 13) - * and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel - * 26) and COMP1 non-inverting input. - * Pin PC3 connection depends on another switch setting, refer to - * macro "__HAL_ADC_CHANNEL_SPEED_FAST()". - * @retval None. - */ -#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE() SET_BIT(COMP->CSR, COMP_CSR_SW1) - -#define __HAL_RI_SWITCH_COMP1_SW1_OPEN() CLEAR_BIT(COMP->CSR, COMP_CSR_SW1) -#endif /* COMP_CSR_SW1 */ - -/** - * @} - */ - -/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation - * @{ - */ - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports A - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR1, (__IOPIN__)); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports B - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports C - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR2, (__IOPIN__)); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports D - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \ - } while(0) - -#if defined (GPIOE_BASE) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports E - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR3, (__IOPIN__)); \ - } while(0) - -#endif /* GPIOE_BASE */ - -#if defined(GPIOF_BASE) || defined(GPIOG_BASE) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports F - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \ - } while(0) - -/** - * @brief Enable or disable Hysteresis of the input schmitt triger of Ports G - * When the I/Os are programmed in input mode by standard I/O port - * registers, the Schmitt trigger and the hysteresis are enabled by default. - * When hysteresis is disabled, it is possible to read the - * corresponding port with a trigger level of VDDIO/2. - * @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis. - * This parameter must be a value of @ref RI_Pin - * @retval None - */ -#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \ - } while(0) - -#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \ - SET_BIT(RI->HYSCR4, (__IOPIN__)); \ - } while(0) - -#endif /* GPIOF_BASE || GPIOG_BASE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported variables --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Variables HAL Exported Variables - * @{ - */ -extern __IO uint32_t uwTick; -extern uint32_t uwTickPrio; -extern uint32_t uwTickFreq; -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); -uint32_t HAL_GetTickFreq(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group3 - * @{ - */ - -/* DBGMCU Peripheral Control functions *****************************************/ -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h deleted file mode 100644 index 2ce2cac..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_cortex.h +++ /dev/null @@ -1,437 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_CORTEX_H -#define __STM32L1xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types Cortex Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ - -#define NVIC_PRIORITYGROUP_0 (0x00000007U) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 (0x00000006U) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 (0x00000005U) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 (0x00000004U) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 (0x00000003U) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) -#define SYSTICK_CLKSOURCE_HCLK (0x00000004U) - -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE (0x00000000U) -#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) -#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) -#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) - -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01) -#define MPU_REGION_DISABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07) -/** - * @} - */ -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/* Exported Macros -----------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group_Macro CORTEX Preemption Priority Group - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ - -/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source - * @{ - */ -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @brief CORTEX private functions - * @{ - */ - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -#if (__MPU_PRESENT == 1) -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_CORTEX_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h deleted file mode 100644 index 57728e7..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_def.h +++ /dev/null @@ -1,198 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_DEF -#define __STM32L1xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx.h" -#include "Legacy/stm32_hal_legacy.h" -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ - -#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \ - (__DMA_HANDLE_).Parent = (__HANDLE__); \ - } while(0) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) - -#if (USE_RTOS == 1) - - /* Reserved for future use */ - #error "USE_RTOS should be 0 in the current HAL release" - -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__GNUC__) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32L1xx_HAL_DEF */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h deleted file mode 100644 index 2baafbc..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_dma.h +++ /dev/null @@ -1,652 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32L1xx_HAL_DMA_H -#define STM32L1xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Types DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Channel */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. - This parameter can be a value of @ref DMA_Priority_level */ -} DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - - -/** - * @brief HAL DMA Callback ID structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ - - uint32_t ChannelIndex; /*!< DMA Channel Index */ - -}DMA_HandleTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ -#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ - -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @{ - */ -#define DMA_NORMAL 0x00000000U /*!< Normal mode */ -#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @{ - */ -#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ -#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ -#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @{ - */ -#define DMA_IT_TC DMA_CCR_TCIE -#define DMA_IT_HT DMA_CCR_HTIE -#define DMA_IT_TE DMA_CCR_TEIE -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @{ - */ -#define DMA_FLAG_GL1 DMA_ISR_GIF1 -#define DMA_FLAG_TC1 DMA_ISR_TCIF1 -#define DMA_FLAG_HT1 DMA_ISR_HTIF1 -#define DMA_FLAG_TE1 DMA_ISR_TEIF1 -#define DMA_FLAG_GL2 DMA_ISR_GIF2 -#define DMA_FLAG_TC2 DMA_ISR_TCIF2 -#define DMA_FLAG_HT2 DMA_ISR_HTIF2 -#define DMA_FLAG_TE2 DMA_ISR_TEIF2 -#define DMA_FLAG_GL3 DMA_ISR_GIF3 -#define DMA_FLAG_TC3 DMA_ISR_TCIF3 -#define DMA_FLAG_HT3 DMA_ISR_HTIF3 -#define DMA_FLAG_TE3 DMA_ISR_TEIF3 -#define DMA_FLAG_GL4 DMA_ISR_GIF4 -#define DMA_FLAG_TC4 DMA_ISR_TCIF4 -#define DMA_FLAG_HT4 DMA_ISR_HTIF4 -#define DMA_FLAG_TE4 DMA_ISR_TEIF4 -#define DMA_FLAG_GL5 DMA_ISR_GIF5 -#define DMA_FLAG_TC5 DMA_ISR_TCIF5 -#define DMA_FLAG_HT5 DMA_ISR_HTIF5 -#define DMA_FLAG_TE5 DMA_ISR_TEIF5 -#define DMA_FLAG_GL6 DMA_ISR_GIF6 -#define DMA_FLAG_TC6 DMA_ISR_TCIF6 -#define DMA_FLAG_HT6 DMA_ISR_HTIF6 -#define DMA_FLAG_TE6 DMA_ISR_TEIF6 -#define DMA_FLAG_GL7 DMA_ISR_GIF7 -#define DMA_FLAG_TC7 DMA_ISR_TCIF7 -#define DMA_FLAG_HT7 DMA_ISR_HTIF7 -#define DMA_FLAG_TE7 DMA_ISR_TEIF7 -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) - - -/* Interrupt & Flag management */ -#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \ - defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \ - defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - -/** - * @brief Return the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ - -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Return the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Return the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ - DMA_ISR_GIF7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) - -/** - * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ -(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) - -#else -/** - * @brief Return the current DMA Channel transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ - -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ - DMA_FLAG_TC7) - -/** - * @brief Return the current DMA Channel half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ - DMA_FLAG_HT7) - -/** - * @brief Return the current DMA Channel transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ - DMA_FLAG_TE7) - -/** - * @brief Return the current DMA Channel Global interrupt flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ - DMA_ISR_GIF7) - -/** - * @brief Get the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag - * @arg DMA_FLAG_HTIFx: Half transfer complete flag - * @arg DMA_FLAG_TEIFx: Transfer error flag - * @arg DMA_ISR_GIFx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__)) - -/** - * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCx: Transfer complete flag - * @arg DMA_FLAG_HTx: Half transfer complete flag - * @arg DMA_FLAG_TEx: Transfer error flag - * @arg DMA_FLAG_GLx: Global interrupt flag - * Where x can be from 1 to 7 to select the DMA Channel x flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @brief Enable the specified DMA Channel interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified DMA Channel interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified DMA Channel interrupt is enabled or not. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) - -/** - * @brief Return the number of remaining data units in the current DMA Channel transfer. - * @param __HANDLE__ DMA handle - * @retval The number of remaining data units in the current DMA Channel transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @{ - */ - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32L1xx_HAL_DMA_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h deleted file mode 100644 index b67f6ac..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_exti.h +++ /dev/null @@ -1,316 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_exti.h - * @author MCD Application Team - * @brief Header file of EXTI HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32L1xx_HAL_EXTI_H -#define STM32L1xx_HAL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup EXTI EXTI - * @brief EXTI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Types EXTI Exported Types - * @{ - */ -typedef enum -{ - HAL_EXTI_COMMON_CB_ID = 0x00U -} EXTI_CallbackIDTypeDef; - -/** - * @brief EXTI Handle structure definition - */ -typedef struct -{ - uint32_t Line; /*!< Exti line number */ - void (* PendingCallback)(void); /*!< Exti pending callback */ -} EXTI_HandleTypeDef; - -/** - * @brief EXTI Configuration structure definition - */ -typedef struct -{ - uint32_t Line; /*!< The Exti line to be configured. This parameter - can be a value of @ref EXTI_Line */ - uint32_t Mode; /*!< The Exit Mode to be configured for a core. - This parameter can be a combination of @ref EXTI_Mode */ - uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter - can be a value of @ref EXTI_Trigger */ - uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. - This parameter is only possible for line 0 to 15. It - can be a value of @ref EXTI_GPIOSel */ -} EXTI_ConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_Line EXTI Line - * @{ - */ -#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ -#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ -#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ -#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ -#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ -#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ -#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ -#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ -#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ -#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ -#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ -#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ -#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ -#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ -#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ -#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ -#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB Device FS Wakeup from suspend event */ -#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ -#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the Comparator 1 output */ -#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the Comparator 2 output */ -#if defined(EXTI_IMR_IM23) -#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the channel acquisition interrupt */ -#endif /* EXTI_IMR_IM23 */ - -/** - * @} - */ - -/** @defgroup EXTI_Mode EXTI Mode - * @{ - */ -#define EXTI_MODE_NONE 0x00000000u -#define EXTI_MODE_INTERRUPT 0x00000001u -#define EXTI_MODE_EVENT 0x00000002u -/** - * @} - */ - -/** @defgroup EXTI_Trigger EXTI Trigger - * @{ - */ - -#define EXTI_TRIGGER_NONE 0x00000000u -#define EXTI_TRIGGER_RISING 0x00000001u -#define EXTI_TRIGGER_FALLING 0x00000002u -#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) -/** - * @} - */ - -/** @defgroup EXTI_GPIOSel EXTI GPIOSel - * @brief - * @{ - */ -#define EXTI_GPIOA 0x00000000u -#define EXTI_GPIOB 0x00000001u -#define EXTI_GPIOC 0x00000002u -#define EXTI_GPIOD 0x00000003u -#if defined (GPIOE) -#define EXTI_GPIOE 0x00000004u -#endif /* GPIOE */ -#if defined (GPIOF) -#define EXTI_GPIOF 0x00000005u -#endif /* GPIOF */ -#if defined (GPIOG) -#define EXTI_GPIOG 0x00000006u -#endif /* GPIOG */ -#define EXTI_GPIOH 0x00000007u - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ -/** - * @brief EXTI Line property definition - */ -#define EXTI_PROPERTY_SHIFT 24u -#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) -#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) - -/** - * @brief EXTI bit usage - */ -#define EXTI_PIN_MASK 0x0000001Fu - -/** - * @brief EXTI Mask for interrupt & event mode - */ -#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) - -/** - * @brief EXTI Mask for trigger possibilities - */ -#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) - -/** - * @brief EXTI Line number - */ -#if defined(EXTI_IMR_IM23) -#define EXTI_LINE_NB 24UL -#else -#define EXTI_LINE_NB 23UL -#endif /* EXTI_IMR_IM23 */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup EXTI_Private_Macros EXTI Private Macros - * @{ - */ -#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) - -#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) - -#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) - -#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) - -#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) - -#if !defined (GPIOE) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOH)) -#elif !defined (GPIOF) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOH)) -#else -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH)) -#endif /* GPIOE */ - -#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Functions EXTI Exported Functions - * @brief EXTI Exported Functions - * @{ - */ - -/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions - * @brief Configuration functions - * @{ - */ -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32l1xx_HAL_EXTI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h deleted file mode 100644 index 39fa45b..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash.h +++ /dev/null @@ -1,409 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of Flash HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_FLASH_H -#define __STM32L1xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ -/** - * @} - */ - -/** @addtogroup FLASH_Private_Macros - * @{ - */ - -#define IS_FLASH_TYPEPROGRAM(_VALUE_) ((_VALUE_) == FLASH_TYPEPROGRAM_WORD) - -#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ - ((__LATENCY__) == FLASH_LATENCY_1)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_PAGEERASE = 1U, - FLASH_PROC_PROGRAM = 2U, -} FLASH_ProcedureTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ - - __IO uint32_t NbPagesToErase; /*!< Internal variable to save the remaining sectors to erase in IT context*/ - - __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ - - __IO uint32_t Page; /*!< Internal variable to define the current page which is erasing */ - - HAL_LockTypeDef Lock; /*!< FLASH locking object */ - - __IO uint32_t ErrorCode; /*!< FLASH error code - This parameter can be a value of @ref FLASH_Error_Codes */ -} FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error_Codes FLASH Error Codes - * @{ - */ - -#define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ -#define HAL_FLASH_ERROR_PGA 0x01U /*!< Programming alignment error */ -#define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPTV 0x04U /*!< Option validity error */ -#define HAL_FLASH_ERROR_SIZE 0x08U /*!< */ -#define HAL_FLASH_ERROR_RD 0x10U /*!< Read protected error */ -#define HAL_FLASH_ERROR_OPTVUSR 0x20U /*!< Option UserValidity Error. */ -#define HAL_FLASH_ERROR_OPERATION 0x40U /*!< Not used */ - -/** - * @} - */ - -/** @defgroup FLASH_Page_Size FLASH size information - * @{ - */ - -#define FLASH_SIZE (uint32_t)((*((uint32_t *)FLASHSIZE_BASE)&0xFFFFU) * 1024U) -#define FLASH_PAGE_SIZE (256U) /*!< FLASH Page Size in bytes */ - -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_WORD (0x02U) /*!PECR), (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt - * @arg @ref FLASH_IT_ERR Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->PECR), (uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg @ref FLASH_FLAG_BSY FLASH Busy flag - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_ENDHV FLASH End of High Voltage flag - * @arg @ref FLASH_FLAG_READY FLASH Ready flag after low power mode - * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag - * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag - * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag -@if STM32L100xB -@elif STM32L100xBA - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) -@elif STM32L151xB -@elif STM32L151xBA - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) -@elif STM32L152xB -@elif STM32L152xBA - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) -@elif STM32L100xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@elif STM32L151xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@elif STM32L152xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@elif STM32L162xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@else - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@endif - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag - * @arg @ref FLASH_FLAG_PGAERR FLASH Programming Alignment error flag - * @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag - * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error error flag -@if STM32L100xB -@elif STM32L100xBA - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) -@elif STM32L151xB -@elif STM32L151xBA - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) -@elif STM32L152xB -@elif STM32L152xBA - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) -@elif STM32L100xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@elif STM32L151xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@elif STM32L152xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@elif STM32L162xC - * @arg @ref FLASH_FLAG_RDERR FLASH Read Protection error flag (PCROP) - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@else - * @arg @ref FLASH_FLAG_OPTVERRUSR FLASH Option User validity error -@endif - * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32l1xx_hal_flash_ex.h" -#include "stm32l1xx_hal_flash_ramfunc.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data); - -/* FLASH IRQ handler function */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); - -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -uint32_t HAL_FLASH_GetError(void); - -/** - * @} - */ - -/** - * @} - */ - -/* Private function -------------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_FLASH_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h deleted file mode 100644 index 0d5cd2a..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ex.h +++ /dev/null @@ -1,968 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of Flash HAL Extended module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_FLASH_EX_H -#define __STM32L1xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/** @addtogroup FLASHEx_Private_Constants - * @{ - */ -#if defined(FLASH_SR_RDERR) && defined(FLASH_SR_OPTVERRUSR) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR) - -#elif defined(FLASH_SR_RDERR) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_RDERR) - -#elif defined(FLASH_SR_OPTVERRUSR) - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \ - FLASH_FLAG_OPTVERRUSR) - -#else - -#define FLASH_FLAG_MASK ( FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_OPTVERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR) - -#endif /* FLASH_SR_RDERR & FLASH_SR_OPTVERRUSR */ - -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ - || defined(STM32L151xBA) || defined(STM32L152xBA) - -/******* Devices with FLASH 128K *******/ -#define FLASH_NBPAGES_MAX 512U /* 512 pages from page 0 to page 511U */ - -#elif defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ - || defined(STM32L151xCA) || defined(STM32L152xCA) || defined(STM32L162xCA) - -/******* Devices with FLASH 256K *******/ -#define FLASH_NBPAGES_MAX 1025U /* 1025 pages from page 0 to page 1024U */ - -#elif defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ - || defined(STM32L162xD) || defined(STM32L162xDX) - -/******* Devices with FLASH 384K *******/ -#define FLASH_NBPAGES_MAX 1536U /* 1536 pages from page 0 to page 1535U */ - -#elif defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) - -/******* Devices with FLASH 512K *******/ -#define FLASH_NBPAGES_MAX 2048U /* 2048 pages from page 0 to page 2047U */ - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */ - -#define WRP_MASK_LOW (0x0000FFFFU) -#define WRP_MASK_HIGH (0xFFFF0000U) - -/** - * @} - */ - -/** @addtogroup FLASHEx_Private_Macros - * @{ - */ - -#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) - -#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR))) - -#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ - ((__VALUE__) == OB_WRPSTATE_ENABLE)) - -#define IS_OB_WRP(__PAGE__) (((__PAGE__) != 0x0000000U)) - -#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL_0) ||\ - ((__LEVEL__) == OB_RDP_LEVEL_1) ||\ - ((__LEVEL__) == OB_RDP_LEVEL_2)) - -#define IS_OB_BOR_LEVEL(__LEVEL__) (((__LEVEL__) == OB_BOR_OFF) || \ - ((__LEVEL__) == OB_BOR_LEVEL1) || \ - ((__LEVEL__) == OB_BOR_LEVEL2) || \ - ((__LEVEL__) == OB_BOR_LEVEL3) || \ - ((__LEVEL__) == OB_BOR_LEVEL4) || \ - ((__LEVEL__) == OB_BOR_LEVEL5)) - -#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) - -#if defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2) - -#define IS_OBEX(__VALUE__) (((__VALUE__) == OPTIONBYTE_PCROP) || ((__VALUE__) == OPTIONBYTE_BOOTCONFIG)) - -#elif defined(FLASH_OBR_SPRMOD) && !defined(FLASH_OBR_nRST_BFB2) - -#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_PCROP) - -#elif !defined(FLASH_OBR_SPRMOD) && defined(FLASH_OBR_nRST_BFB2) - -#define IS_OBEX(__VALUE__) ((__VALUE__) == OPTIONBYTE_BOOTCONFIG) - -#endif /* FLASH_OBR_SPRMOD && FLASH_OBR_nRST_BFB2 */ - -#if defined(FLASH_OBR_SPRMOD) - -#define IS_PCROPSTATE(__VALUE__) (((__VALUE__) == OB_PCROP_STATE_DISABLE) || \ - ((__VALUE__) == OB_PCROP_STATE_ENABLE)) - -#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000U)) -#endif /* FLASH_OBR_SPRMOD */ - -#if defined(FLASH_OBR_nRST_BFB2) - -#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) - -#endif /* FLASH_OBR_nRST_BFB2 */ - -#define IS_TYPEERASEDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEERASEDATA_BYTE) || \ - ((__VALUE__) == FLASH_TYPEERASEDATA_HALFWORD) || \ - ((__VALUE__) == FLASH_TYPEERASEDATA_WORD)) -#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ - ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \ - ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD) || \ - ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTBYTE) || \ - ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) || \ - ((__VALUE__) == FLASH_TYPEPROGRAMDATA_FASTWORD)) - - -/** @defgroup FLASHEx_Address FLASHEx Address - * @{ - */ - -#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END)) - -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L100xBA) \ - || defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L100xC) || defined(STM32L151xC) \ - || defined(STM32L152xC) || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L152xCA) \ - || defined(STM32L162xCA) - -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END)) - -#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) -#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END)) -#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END)) - -#endif /* STM32L100xB || STM32L151xB || STM32L152xB || (...) || STM32L151xCA || STM32L152xCA || STM32L162xCA */ - -#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1U) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) - -/** - * @} - */ - -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Page Erase only. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - - uint32_t PageAddress; /*!< PageAddress: Initial FLASH address to be erased - This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ - - uint32_t NbPages; /*!< NbPages: Number of pages to be erased. - This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes PROGRAM structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ - - uint32_t WRPSector0To31; /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ - || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ - || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) - uint32_t WRPSector32To63; /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ - || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ - || defined(STM32L162xE) - uint32_t WRPSector64To95; /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95 - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */ -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ - || defined(STM32L152xDX) || defined(STM32L162xDX) - uint32_t WRPSector96To127; /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127 or - Sectors 96 to 111 for STM32L1xxxDX devices. - This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */ -#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ - - uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - - uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ - - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, - @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/ -} FLASH_OBProgramInitTypeDef; - -#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) -/** - * @brief FLASH Advanced Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . - This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ - -#if defined(FLASH_OBR_SPRMOD) - uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. - This parameter can be a value of @ref FLASHEx_PCROP_State */ - - uint32_t PCROPSector0To31; /*!< PCROPSector0To31: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */ - -#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) - uint32_t PCROPSector32To63; /*!< PCROPSector32To63: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ -#endif /* STM32L151xC || STM32L152xC || STM32L162xC */ -#endif /* FLASH_OBR_SPRMOD */ - -#if defined(FLASH_OBR_nRST_BFB2) - uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */ -#endif /* FLASH_OBR_nRST_BFB2*/ -} FLASH_AdvOBProgramInitTypeDef; - -/** - * @} - */ -#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase - * @{ - */ -#define FLASH_TYPEERASE_PAGES (0x00U) /*!= 256KB*/ -#define OB_WRP3_PAGES1024TO1039 (0x00000001U) /* Write protection of Sector64 */ -#define OB_WRP3_PAGES1040TO1055 (0x00000002U) /* Write protection of Sector65 */ -#define OB_WRP3_PAGES1056TO1071 (0x00000004U) /* Write protection of Sector66 */ -#define OB_WRP3_PAGES1072TO1087 (0x00000008U) /* Write protection of Sector67 */ -#define OB_WRP3_PAGES1088TO1103 (0x00000010U) /* Write protection of Sector68 */ -#define OB_WRP3_PAGES1104TO1119 (0x00000020U) /* Write protection of Sector69 */ -#define OB_WRP3_PAGES1120TO1135 (0x00000040U) /* Write protection of Sector70 */ -#define OB_WRP3_PAGES1136TO1151 (0x00000080U) /* Write protection of Sector71 */ -#define OB_WRP3_PAGES1152TO1167 (0x00000100U) /* Write protection of Sector72 */ -#define OB_WRP3_PAGES1168TO1183 (0x00000200U) /* Write protection of Sector73 */ -#define OB_WRP3_PAGES1184TO1199 (0x00000400U) /* Write protection of Sector74 */ -#define OB_WRP3_PAGES1200TO1215 (0x00000800U) /* Write protection of Sector75 */ -#define OB_WRP3_PAGES1216TO1231 (0x00001000U) /* Write protection of Sector76 */ -#define OB_WRP3_PAGES1232TO1247 (0x00002000U) /* Write protection of Sector77 */ -#define OB_WRP3_PAGES1248TO1263 (0x00004000U) /* Write protection of Sector78 */ -#define OB_WRP3_PAGES1264TO1279 (0x00008000U) /* Write protection of Sector79 */ -#define OB_WRP3_PAGES1280TO1295 (0x00010000U) /* Write protection of Sector80 */ -#define OB_WRP3_PAGES1296TO1311 (0x00020000U) /* Write protection of Sector81 */ -#define OB_WRP3_PAGES1312TO1327 (0x00040000U) /* Write protection of Sector82 */ -#define OB_WRP3_PAGES1328TO1343 (0x00080000U) /* Write protection of Sector83 */ -#define OB_WRP3_PAGES1344TO1359 (0x00100000U) /* Write protection of Sector84 */ -#define OB_WRP3_PAGES1360TO1375 (0x00200000U) /* Write protection of Sector85 */ -#define OB_WRP3_PAGES1376TO1391 (0x00400000U) /* Write protection of Sector86 */ -#define OB_WRP3_PAGES1392TO1407 (0x00800000U) /* Write protection of Sector87 */ -#define OB_WRP3_PAGES1408TO1423 (0x01000000U) /* Write protection of Sector88 */ -#define OB_WRP3_PAGES1424TO1439 (0x02000000U) /* Write protection of Sector89 */ -#define OB_WRP3_PAGES1440TO1455 (0x04000000U) /* Write protection of Sector90 */ -#define OB_WRP3_PAGES1456TO1471 (0x08000000U) /* Write protection of Sector91 */ -#define OB_WRP3_PAGES1472TO1487 (0x10000000U) /* Write protection of Sector92 */ -#define OB_WRP3_PAGES1488TO1503 (0x20000000U) /* Write protection of Sector93 */ -#define OB_WRP3_PAGES1504TO1519 (0x40000000U) /* Write protection of Sector94 */ -#define OB_WRP3_PAGES1520TO1535 (0x80000000U) /* Write protection of Sector95 */ - -#define OB_WRP3_ALLPAGES ((uint32_t)FLASH_WRPR3_WRP) /*!< Write protection of all Sectors */ - -/** - * @} - */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/ - -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ - || defined(STM32L152xDX) || defined(STM32L162xDX) - -/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4 - * @{ - */ - -/* Pages for Cat5 devices*/ -#define OB_WRP4_PAGES1536TO1551 (0x00000001U)/* Write protection of Sector96*/ -#define OB_WRP4_PAGES1552TO1567 (0x00000002U)/* Write protection of Sector97*/ -#define OB_WRP4_PAGES1568TO1583 (0x00000004U)/* Write protection of Sector98*/ -#define OB_WRP4_PAGES1584TO1599 (0x00000008U)/* Write protection of Sector99*/ -#define OB_WRP4_PAGES1600TO1615 (0x00000010U) /* Write protection of Sector100*/ -#define OB_WRP4_PAGES1616TO1631 (0x00000020U) /* Write protection of Sector101*/ -#define OB_WRP4_PAGES1632TO1647 (0x00000040U) /* Write protection of Sector102*/ -#define OB_WRP4_PAGES1648TO1663 (0x00000080U) /* Write protection of Sector103*/ -#define OB_WRP4_PAGES1664TO1679 (0x00000100U) /* Write protection of Sector104*/ -#define OB_WRP4_PAGES1680TO1695 (0x00000200U) /* Write protection of Sector105*/ -#define OB_WRP4_PAGES1696TO1711 (0x00000400U) /* Write protection of Sector106*/ -#define OB_WRP4_PAGES1712TO1727 (0x00000800U) /* Write protection of Sector107*/ -#define OB_WRP4_PAGES1728TO1743 (0x00001000U) /* Write protection of Sector108*/ -#define OB_WRP4_PAGES1744TO1759 (0x00002000U) /* Write protection of Sector109*/ -#define OB_WRP4_PAGES1760TO1775 (0x00004000U) /* Write protection of Sector110*/ -#define OB_WRP4_PAGES1776TO1791 (0x00008000U) /* Write protection of Sector111*/ - -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) - -#define OB_WRP4_PAGES1792TO1807 (0x00010000U) /* Write protection of Sector112*/ -#define OB_WRP4_PAGES1808TO1823 (0x00020000U) /* Write protection of Sector113*/ -#define OB_WRP4_PAGES1824TO1839 (0x00040000U) /* Write protection of Sector114*/ -#define OB_WRP4_PAGES1840TO1855 (0x00080000U) /* Write protection of Sector115*/ -#define OB_WRP4_PAGES1856TO1871 (0x00100000U) /* Write protection of Sector116*/ -#define OB_WRP4_PAGES1872TO1887 (0x00200000U) /* Write protection of Sector117*/ -#define OB_WRP4_PAGES1888TO1903 (0x00400000U) /* Write protection of Sector118*/ -#define OB_WRP4_PAGES1904TO1919 (0x00800000U) /* Write protection of Sector119*/ -#define OB_WRP4_PAGES1920TO1935 (0x01000000U) /* Write protection of Sector120*/ -#define OB_WRP4_PAGES1936TO1951 (0x02000000U) /* Write protection of Sector121*/ -#define OB_WRP4_PAGES1952TO1967 (0x04000000U) /* Write protection of Sector122*/ -#define OB_WRP4_PAGES1968TO1983 (0x08000000U) /* Write protection of Sector123*/ -#define OB_WRP4_PAGES1984TO1999 (0x10000000U) /* Write protection of Sector124*/ -#define OB_WRP4_PAGES2000TO2015 (0x20000000U) /* Write protection of Sector125*/ -#define OB_WRP4_PAGES2016TO2031 (0x40000000U) /* Write protection of Sector126*/ -#define OB_WRP4_PAGES2032TO2047 (0x80000000U) /* Write protection of Sector127*/ - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE */ - -#define OB_WRP4_ALLPAGES ((uint32_t)FLASH_WRPR4_WRP) /*!< Write protection of all Sectors */ - -/** - * @} - */ - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ - -/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection - * @{ - */ -#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) -#define OB_RDP_LEVEL_1 ((uint8_t)0xBBU) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /* Warning: When enabling read protection level 2 - it is no more possible to go back to level 1 or 0 */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level - * @{ - */ - -#define OB_BOR_OFF ((uint8_t)0x00U) /*!< BOR is disabled at power down, the reset is asserted when the VDD - power supply reaches the PDR(Power Down Reset) threshold (1.5V) */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08U) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */ -#define OB_BOR_LEVEL2 ((uint8_t)0x09U) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */ -#define OB_BOR_LEVEL3 ((uint8_t)0x0AU) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */ -#define OB_BOR_LEVEL4 ((uint8_t)0x0BU) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */ -#define OB_BOR_LEVEL5 ((uint8_t)0x0CU) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog - * @{ - */ - -#define OB_IWDG_SW ((uint8_t)0x10U) /*!< Software WDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00U) /*!< Hardware WDG selected */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP - * @{ - */ - -#define OB_STOP_NORST ((uint8_t)0x20U) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STOP */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY - * @{ - */ - -#define OB_STDBY_NORST ((uint8_t)0x40U) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00U) /*!< Reset generated when entering in STANDBY */ - -/** - * @} - */ - -#if defined(FLASH_OBR_SPRMOD) - -/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type - * @{ - */ - -#define OPTIONBYTE_PCROP (0x01U) /*!> 16U)) /*!< At startup, if boot pins are set in boot from user Flash position - and this parameter is selected the device will boot from Bank1(Default) */ - -/** - * @} - */ -#endif /* FLASH_OBR_nRST_BFB2 */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros - * @{ - */ - -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency - * This parameter can be one of the following values: - * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle - * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle - * @retval none - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) do { \ - if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \ - MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \ - } while(0U) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * This parameter can be one of the following values: - * @arg @ref FLASH_LATENCY_0 FLASH Zero Latency cycle - * @arg @ref FLASH_LATENCY_1 FLASH One Latency cycle - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @brief Enable the FLASH 64-bit access. - * @note Read access 64 bit is used. - * @note This bit cannot be written at the same time as the LATENCY and - * PRFTEN bits. - * @retval none - */ -#define __HAL_FLASH_ACC64_ENABLE() (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64)) - - /** - * @brief Disable the FLASH 64-bit access. - * @note Read access 32 bit is used - * @note To reset this bit, the LATENCY should be zero wait state and the - * prefetch off. - * @retval none - */ -#define __HAL_FLASH_ACC64_DISABLE() (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64)) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() do { __HAL_FLASH_ACC64_ENABLE(); \ - SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \ - } while(0U) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) - -/** - * @brief Enable the FLASH power down during Sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Disable the FLASH power down during Sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Enable the Flash Run power down mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ -#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ - FLASH->PDKEYR = FLASH_PDKEY2; \ - SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ - } while (0U) - -/** - * @brief Disable the Flash Run power down mode. - * @note Writing this bit to 0 this bit, automatically the keys are - * loss and a new unlock sequence is necessary to re-write it to 1. - */ -#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ - FLASH->PDKEYR = FLASH_PDKEY2; \ - CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ - } while (0U) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); - -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); - -#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) - -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); -void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); - -#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ - -#if defined(FLASH_OBR_SPRMOD) - -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); - -#endif /* FLASH_OBR_SPRMOD */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group3 - * @{ - */ - -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); - -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address); -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); -void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); -void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_FLASH_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h deleted file mode 100644 index 49a2f2e..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_flash_ramfunc.h +++ /dev/null @@ -1,119 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ramfunc.h - * @author MCD Application Team - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_FLASH_RAMFUNC_H -#define __STM32L1xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH_RAMFUNC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions - * @{ - */ - -/* - * @brief FLASH memory functions that should be executed from internal SRAM. - * These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c" - * file. - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 - * @{ - */ - -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void); -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void); - -/** - * @} - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group2 - * @{ - */ - -#if defined(FLASH_PECR_PARALLBANK) - -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); - -#endif /* FLASH_PECR_PARALLBANK */ - -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); - -/** - * @} - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group3 - * @{ - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t *Error); -/** - * @} - */ - -/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group4 - * @{ - */ - -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address); -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_FLASH_RAMFUNC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h deleted file mode 100644 index 544661b..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio.h +++ /dev/null @@ -1,320 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_GPIO_H -#define __STM32L1xx_HAL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -} GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -} GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ - - -/** @defgroup GPIO_pins GPIO pins - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ - -#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode GPIO mode - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) - * @{ - */ -#define GPIO_MODE_INPUT (0x00000000U) /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG (0x00000003U) /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (0x10120000U) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */ - -/** - * @} - */ - -/** @defgroup GPIO_speed GPIO speed - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< max: 400 KHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< max: 1 MHz to 2 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< max: 2 MHz to 10 MHz, please refer to the product datasheet */ -#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< max: 8 MHz to 50 MHz, please refer to the product datasheet */ - -/** - * @} - */ - -/** @defgroup GPIO_pull GPIO pull - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ - -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) - -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__ specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) - -/** - * @} - */ - -/* Include GPIO HAL Extension module */ -#include "stm32l1xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @brief GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_GPIO_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h deleted file mode 100644 index ebddd83..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_gpio_ex.h +++ /dev/null @@ -1,205 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_GPIO_EX_H -#define __STM32L1xx_HAL_GPIO_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -/* AF 0 selection */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */ -#define GPIO_AF0_TAMPER ((uint8_t)0x00) /*!< TAMPER Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /*!< SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /*!< RTC_OUT Alternate Function mapping */ - -/* AF 1 selection */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */ - -/* AF 2 selection */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */ -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC) -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ - -/* AF 3 selection */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */ - - -/* AF 4 selection */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */ - -/* AF 5 selection */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /*!< SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /*!< SPI2/I2S2 Alternate Function mapping */ - -/* AF 6 selection */ -#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\ - defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) - -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /*!< SPI3/I2S3 Alternate Function mapping */ - -#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE || STM32L162xDX */ - - -/* AF 7 selection */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */ - -/* AF 8 selection */ -#if defined (STM32L151xD) || defined (STM32L151xE) || defined (STM32L151xDX) ||\ - defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ - defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) - -#define GPIO_AF8_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */ - -#endif /* STM32L151xD || STM32L151xE || STM32L151xDX || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE || STM32L162xDX */ - - -/* AF 9 selection */ - -/* AF 10 selection */ - -/* AF 11 selection */ -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\ - defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) || defined (STM32L152xDX) ||\ - defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE) || defined (STM32L162xDX) - -#define GPIO_AF11_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */ - -#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ - -/* AF 12 selection */ -#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) - -#define GPIO_AF12_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */ -#define GPIO_AF12_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */ - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ -/* AF 13 selection */ - -/* AF 14 selection */ -#define GPIO_AF14_TIM_IC1 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC2 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC3 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ -#define GPIO_AF14_TIM_IC4 ((uint8_t)0x0E) /*!< TIMER INPUT CAPTURE Alternate Function mapping */ - -/* AF 15 selection */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */ - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros - * @{ - */ - - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOH))? 5U :\ - ((__GPIOx__) == (GPIOF))? 6U : 7U) -#endif - -#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U : 5U) -#endif - -#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) -#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U : 5U) -#endif - - - -/** - * @} - */ - - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_GPIO_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h deleted file mode 100644 index d7fdc08..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr.h +++ /dev/null @@ -1,486 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_PWR_H -#define __STM32L1xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ -}PWR_PVDTypeDef; - -/** - * @} - */ - -/* Internal constants --------------------------------------------------------*/ - -/** @addtogroup PWR_Private_Constants - * @{ - */ -#define PWR_EXTI_LINE_PVD (0x00010000U) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ - -/** - * @} - */ - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_register_alias_address PWR Register alias address - * @{ - */ -/* ------------- PWR registers bit address in the alias region ---------------*/ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) -#define PWR_CR_OFFSET 0x00 -#define PWR_CSR_OFFSET 0x04 -#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) -#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) -/** - * @} - */ - -/** @defgroup PWR_CR_register_alias PWR CR Register alias address - * @{ - */ -/* --- CR Register ---*/ -/* Alias word address of LPSDSR bit */ -#define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR) -#define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4))) - -/* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) -#define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))) - -/* Alias word address of LPRUN bit */ -#define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN) -#define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4))) - -/* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) -#define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))) - -/* Alias word address of FWU bit */ -#define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU) -#define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4))) - -/* Alias word address of ULP bit */ -#define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP) -#define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4))) -/** - * @} - */ - -/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address - * @{ - */ - -/* --- CSR Register ---*/ -/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */ -#define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4))) -/** - * @} - */ - -/** @defgroup PWR_PVD_detection_level PWR PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage - (Compare internally to VREFINT) */ - -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ - - /** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON (0x00000000U) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR - -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) - -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale - * @{ - */ - -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS - - -/** - * @} - */ - -/** @defgroup PWR_Flag PWR Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#define PWR_FLAG_VOS PWR_CSR_VOSF -#define PWR_FLAG_REGLP PWR_CSR_REGLPF - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__ specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, - * System frequency up to 32 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, - * System frequency up to 16 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, - * System frequency up to 4.2 MHz - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) - -/** @brief Check PWR flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm B), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. - * This bit indicates the state of the internal voltage reference, VREFINT. - * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for - * the internal regulator to be ready after the voltage range is changed. - * The VOSF bit indicates that the regulator has reached the voltage level - * defined with bits VOS of PWR_CR register. - * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run - * mode, this bit stays at 1 until the regulator is ready in main mode. - * A polling on this bit is recommended to wait for the regulator main mode. - * This bit is reset by hardware when the regulator is ready. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2)) - -/** - * @brief Enable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable interrupt on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief PVD EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - - - -/** - * @brief Check whether the specified PVD EXTI interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD EXTI flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup PWR_Private_Macros PWR Private Macros - * @{ - */ - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - - -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) - - -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) - -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) - -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) - - -/** - * @} - */ - - - -/* Include PWR HAL Extension module */ -#include "stm32l1xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *******************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); - -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* WakeUp pins configuration functions ****************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes configuration functions ************************************/ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - - - -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h deleted file mode 100644 index 0c71d68..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_pwr_ex.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_PWR_EX_H -#define __STM32L1xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ - - -/** @defgroup PWREx_WakeUp_Pins PWREx Wakeup Pins - * @{ - */ - -#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC) - -#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 -#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2) || \ - ((PIN) == PWR_WAKEUP_PIN3)) -#else -#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2)) -#endif - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ - -/* Peripheral Control methods ************************************************/ -uint32_t HAL_PWREx_GetVoltageRange(void); -void HAL_PWREx_EnableFastWakeUp(void); -void HAL_PWREx_DisableFastWakeUp(void); -void HAL_PWREx_EnableUltraLowPower(void); -void HAL_PWREx_DisableUltraLowPower(void); -void HAL_PWREx_EnableLowPowerRunMode(void); -HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32L1xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h deleted file mode 100644 index 2cc00c4..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc.h +++ /dev/null @@ -1,1898 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RCC_H -#define __STM32L1xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/** @addtogroup RCC_Private_Constants - * @{ - */ - -/** @defgroup RCC_Timeout RCC Timeout - * @{ - */ - -/* Disable Backup domain write protection state change timeout */ -#define RCC_DBP_TIMEOUT_VALUE (100U) /* 100 ms */ -/* LSE state change timeout */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define LSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -#define PLL_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1U) */ -/** - * @} - */ - -/** @defgroup RCC_Register_Offset Register offsets - * @{ - */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -#define RCC_CR_OFFSET 0x00 -#define RCC_CFGR_OFFSET 0x08 -#define RCC_CIR_OFFSET 0x0C -#define RCC_CSR_OFFSET 0x34 -/** - * @} - */ - -/** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion - * @brief RCC registers bit address in the alias region - * @{ - */ -#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) -#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) -#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) -#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) - -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos -#define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) -/* Alias word address of MSION bit */ -#define RCC_MSION_BIT_NUMBER RCC_CR_MSION_Pos -#define RCC_CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_MSION_BIT_NUMBER * 4U))) -/* Alias word address of HSEON bit */ -#define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos -#define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) -/* Alias word address of CSSON bit */ -#define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos -#define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) -/* Alias word address of PLLON bit */ -#define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos -#define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos -#define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) - -/* Alias word address of RMVF bit */ -#define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos -#define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) - -/* Alias word address of LSEON bit */ -#define RCC_LSEON_BIT_NUMBER RCC_CSR_LSEON_Pos -#define RCC_CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) - -/* Alias word address of LSEON bit */ -#define RCC_LSEBYP_BIT_NUMBER RCC_CSR_LSEBYP_Pos -#define RCC_CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) - -/* Alias word address of RTCEN bit */ -#define RCC_RTCEN_BIT_NUMBER RCC_CSR_RTCEN_Pos -#define RCC_CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) - -/* Alias word address of RTCRST bit */ -#define RCC_RTCRST_BIT_NUMBER RCC_CSR_RTCRST_Pos -#define RCC_CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RTCRST_BIT_NUMBER * 4U))) - -/** - * @} - */ - -/* CR register byte 2 (Bits[23:16]) base address */ -#define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) - -/* CIR register byte 1 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) - -/* CIR register byte 2 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) - -/* Defines used for Flags */ -#define CR_REG_INDEX ((uint8_t)1U) -#define CSR_REG_INDEX ((uint8_t)2U) - -#define RCC_FLAG_MASK ((uint8_t)0x1FU) - -/** - * @} - */ - -/** @addtogroup RCC_Private_Macros - * @{ - */ -#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ - ((__SOURCE__) == RCC_PLLSOURCE_HSE)) -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \ - (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)) -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS)) -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_BYPASS)) -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) -#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFFU) -#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ - ((__RANGE__) == RCC_MSIRANGE_1) || \ - ((__RANGE__) == RCC_MSIRANGE_2) || \ - ((__RANGE__) == RCC_MSIRANGE_3) || \ - ((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6)) -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) -#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) - -#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ - ((__PLL__) == RCC_PLL_ON)) -#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \ - ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4)) - -#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) || ((__MUL__) == RCC_PLL_MUL4) || \ - ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL8) || \ - ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \ - ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \ - ((__MUL__) == RCC_PLL_MUL48)) -#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ - (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ - (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) -#define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) -#define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ - ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ - ((__DIV__) == RCC_MCODIV_16)) -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \ - || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK)) -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< PLLState: The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/ - - uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock - This parameter must be a value of @ref RCC_PLL_Division_Factor*/ -} RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1FU */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - uint32_t MSIState; /*!< The new state of the MSI. - This parameter can be a value of @ref RCC_MSI_Config */ - - uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFU */ - - uint32_t MSIClockRange; /*!< The MSI frequency range. - This parameter can be a value of @ref RCC_MSI_Clock_Range */ - - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -} RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ -} RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ - -#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ -#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ - -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE (0x00000000U) -#define RCC_OSCILLATORTYPE_HSE (0x00000001U) -#define RCC_OSCILLATORTYPE_HSI (0x00000002U) -#define RCC_OSCILLATORTYPE_LSE (0x00000004U) -#define RCC_OSCILLATORTYPE_LSI (0x00000008U) -#define RCC_OSCILLATORTYPE_MSI (0x00000010U) -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF (0x00000000U) /*!< HSE clock deactivation */ -#define RCC_HSE_ON (0x00000001U) /*!< HSE clock activation */ -#define RCC_HSE_BYPASS (0x00000005U) /*!< External clock source for HSE clock */ -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF (0x00000000U) /*!< LSE clock deactivation */ -#define RCC_LSE_ON (0x00000001U) /*!< LSE clock activation */ -#define RCC_LSE_BYPASS (0x00000005U) /*!< External clock source for LSE clock */ - -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF (0x00000000U) /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ - -#define RCC_HSICALIBRATION_DEFAULT (0x10U) /* Default HSI calibration trimming value */ - -/** - * @} - */ - -/** @defgroup RCC_MSI_Clock_Range MSI Clock Range - * @{ - */ - -#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */ -#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */ -#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */ -#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */ -#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */ -#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ -#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ - -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF (0x00000000U) /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ - -/** - * @} - */ - -/** @defgroup RCC_MSI_Config MSI Config - * @{ - */ -#define RCC_MSI_OFF (0x00000000U) -#define RCC_MSI_ON (0x00000001U) - -#define RCC_MSICALIBRATION_DEFAULT (0x00000000U) /* Default MSI calibration trimming value */ - -/** - * @} - */ - -/** @defgroup RCC_PLL_Config PLL Config - * @{ - */ -#define RCC_PLL_NONE (0x00000000U) /*!< PLL is not configured */ -#define RCC_PLL_OFF (0x00000001U) /*!< PLL deactivation */ -#define RCC_PLL_ON (0x00000002U) /*!< PLL activation */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK (0x00000001U) /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK (0x00000002U) /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 (0x00000004U) /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 (0x00000008U) /*!< PCLK2 to configure */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /*!< MSI selected as system clock */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /*!< MSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ - -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ - -/** - * @} - */ - -/** @defgroup RCC_HAL_EC_RTC_HSE_DIV RTC HSE Prescaler - * @{ - */ -#define RCC_RTC_HSE_DIV_2 0x00000000U /*!< HSE is divided by 2 for RTC clock */ -#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /*!< HSE is divided by 4 for RTC clock */ -#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /*!< HSE is divided by 8 for RTC clock */ -#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /*!< HSE is divided by 16 for RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_RTC_LCD_Clock_Source RTC LCD Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK (0x00000000U) /*!< No clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE /*!< HSE oscillator clock divided by X used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV2 (RCC_RTC_HSE_DIV_2 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 2 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV4 (RCC_RTC_HSE_DIV_4 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 4 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV8 (RCC_RTC_HSE_DIV_8 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 8 used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV16 (RCC_RTC_HSE_DIV_16 | RCC_CSR_RTCSEL_HSE) /*!< HSE oscillator clock divided by 16 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Division_Factor PLL Division Factor - * @{ - */ - -#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2 -#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3 -#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4 - -/** - * @} - */ - -/** @defgroup RCC_PLL_Multiplication_Factor PLL Multiplication Factor - * @{ - */ - -#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3 -#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4 -#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6 -#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8 -#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12 -#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16 -#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24 -#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32 -#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48 - -/** - * @} - */ - -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 (0x00000000U) -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ - -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1) -#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2) -#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4) -#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8) -#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16) - -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK -#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK -#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI -#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI -#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE -#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE -#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL - -/** - * @} - */ -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ -#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ -#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ -#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ -#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF) /*!< MSI Ready Interrupt flag */ -#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSSF) /*!< LSE Clock Security System Interrupt flag */ -#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ -#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIRDY_Pos)) /*!< MSI clock ready flag */ -#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ -#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ -#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSECSSD_Pos)) /*!< CSS on LSE failure Detection */ -#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Options bytes loading reset flag */ -#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ -#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ -#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ -#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOHEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FLITF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN)) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN)) -#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN)) - -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) -#define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_COMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_COMPEN);\ - UNUSED(tmpreg); \ - } while(0U) - - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __HAL_RCC_COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */\ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) -#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) - -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST)) -#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST)) - -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) -#define __HAL_RCC_FLITF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST)) -#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) - -#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00000000U) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST)) -#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST)) - -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST)) -#define __HAL_RCC_FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST)) -#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_COMP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00000000U) -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST)) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) -#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00000000U) -#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) -#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) - -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN)) - -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN)) - -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN)) - -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN)) -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) - -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) - -/** - * @} - */ - -/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) != 0U) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) != 0U) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) != 0U) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != 0U) -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) != 0U) -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != 0U) -#define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != 0U) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != 0U) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOAEN)) == 0U) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOBEN)) == 0U) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOCEN)) == 0U) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == 0U) -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOHEN)) == 0U) -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == 0U) -#define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == 0U) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != 0U) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != 0U) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != 0U) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != 0U) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != 0U) -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != 0U) -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != 0U) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != 0U) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != 0U) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != 0U) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != 0U) -#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != 0U) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != 0U) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != 0U) -#define __HAL_RCC_COMP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) != 0U) -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == 0U) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == 0U) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == 0U) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == 0U) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == 0U) -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == 0U) -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == 0U) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == 0U) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == 0U) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == 0U) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == 0U) -#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == 0U) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == 0U) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == 0U) -#define __HAL_RCC_COMP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_COMPEN)) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != 0U) -#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != 0U) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != 0U) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != 0U) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != 0U) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != 0U) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != 0U) -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == 0U) -#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == 0U) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == 0U) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == 0U) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == 0U) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the AHB peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) != 0U) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) != 0U) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) != 0U) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) != 0U) -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) != 0U) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) != 0U) -#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) != 0U) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) != 0U) -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOALPEN)) == 0U) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOBLPEN)) == 0U) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOCLPEN)) == 0U) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIODLPEN)) == 0U) -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOHLPEN)) == 0U) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_CRCLPEN)) == 0U) -#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FLITFLPEN)) == 0U) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA1LPEN)) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != 0U) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != 0U) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != 0U) -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != 0U) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != 0U) -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != 0U) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != 0U) -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != 0U) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != 0U) -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != 0U) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != 0U) -#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) != 0U) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != 0U) -#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != 0U) -#define __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) != 0U) -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == 0U) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == 0U) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == 0U) -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == 0U) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == 0U) -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == 0U) -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == 0U) -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == 0U) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == 0U) -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == 0U) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == 0U) -#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USBLPEN)) == 0U) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == 0U) -#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == 0U) -#define __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_COMPLPEN)) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != 0U) -#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != 0U) -#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != 0U) -#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != 0U) -#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != 0U) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U) -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U) -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == 0U) -#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == 0U) -#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == 0U) -#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == 0U) -#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == 0U) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U) -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) -#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x1F. - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_ICSCR_HSITRIM_Pos)) - -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macro to enable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - */ -#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) - -/** @brief Macro to disable the Internal Low Speed oscillator (LSI). - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) - -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON turn ON the HSE oscillator - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_OFF) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - }while(0U) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do{ \ - if ((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ - } \ - else if ((__STATE__) == RCC_LSE_OFF) \ - { \ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ - } \ - else if ((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ - SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ - } \ - }while(0U) - -/** - * @} - */ - -/** @defgroup RCC_MSI_Configuration MSI Configuration - * @{ - */ - -/** @brief Macro to enable Internal Multi Speed oscillator (MSI). - * @note After enabling the MSI, the application software should wait on MSIRDY - * flag to be set indicating that MSI clock is stable and can be used as - * system clock source. - */ -#define __HAL_RCC_MSI_ENABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = ENABLE) - -/** @brief Macro to disable the Internal Multi Speed oscillator (MSI). - * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note MSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the MSI. - * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator - * clock cycles. - */ -#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) RCC_CR_MSION_BB = DISABLE) - -/** @brief Macro adjusts Internal Multi Speed oscillator (MSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal MSI RC. - * @param _MSICALIBRATIONVALUE_ specifies the calibration trimming value. - * (default is RCC_MSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0xFF. - */ -#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \ - (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << RCC_ICSCR_MSITRIM_Pos)) - -/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range. - * @note After restart from Reset or wakeup from STANDBY, the MSI clock is - * around 2.097 MHz. The MSI clock does not change after wake-up from - * STOP mode. - * @note The MSI clock range can be modified on the fly. - * @param _MSIRANGEVALUE_ specifies the MSI Clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz - */ -#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, \ - RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_))) - -/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode - * @retval MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 65.536 KHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 131.072 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 262.144 KHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 524.288 KHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 1.048 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY) - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 4.194 MHz - */ -#define __HAL_RCC_GET_MSI_RANGE() (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE)) - -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macro to enable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) - -/** @brief Macro to disable the main PLL. - * @note The main PLL can not be disabled if it is used as system clock source - */ -#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) - -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry - * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock - * This parameter can be one of the following values: - * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 - * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 - * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 - * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 - * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 - * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 - * @arg @ref RCC_PLL_MUL24 PLLVCO = PLL clock entry x 24 - * @arg @ref RCC_PLL_MUL32 PLLVCO = PLL clock entry x 32 - * @arg @ref RCC_PLL_MUL48 PLLVCO = PLL clock entry x 48 - * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in - * Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is - * in Range 3. - * - * @param __PLLDIV__ specifies the division factor for PLL VCO input clock - * This parameter can be one of the following values: - * @arg @ref RCC_PLL_DIV2 PLL clock output = PLLVCO / 2 - * @arg @ref RCC_PLL_DIV3 PLL clock output = PLLVCO / 3 - * @arg @ref RCC_PLL_DIV4 PLL clock output = PLLVCO / 4 - * - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__))) - -/** @brief Get oscillator clock selected as PLL input clock - * @retval The clock source used for PLL entry. The returned value can be one - * of the following: - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL input clock - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) - -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. - * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock - * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) - -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI oscillator clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE oscillator clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 - * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 - * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 - * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 - * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 - */ -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** - * @} - */ - - /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ - -/** @brief Macro to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it cannot be changed unless the - * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1). - * - * @param __RTC_CLKSOURCE__ specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as RTC clock - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \ - if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \ - { \ - MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \ - } \ - } while (0U) - -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \ - __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \ - RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \ - } while (0U) - -/** @brief Macro to get the RTC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)) - -/** - * @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK). - * - * @retval Returned value can be one of the following values: - * @arg @ref RCC_RTC_HSE_DIV_2 HSE divided by 2 selected as RTC clock - * @arg @ref RCC_RTC_HSE_DIV_4 HSE divided by 4 selected as RTC clock - * @arg @ref RCC_RTC_HSE_DIV_8 HSE divided by 8 selected as RTC clock - * @arg @ref RCC_RTC_HSE_DIV_16 HSE divided by 16 selected as RTC clock - * - */ -#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE))) - -/** @brief Macro to enable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = ENABLE) - -/** @brief Macro to disable the the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_CSR_RTCEN_BB = DISABLE) - -/** @brief Macro to force the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = ENABLE) - -/** @brief Macros to release the Backup domain reset. - */ -#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_CSR_RTCRST_BB = DISABLE) - -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt. - * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) - * @arg @ref RCC_IT_CSS Clock Security System interrupt - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. - * @arg @ref RCC_IT_LSERDY LSE ready interrupt. - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. - * @arg @ref RCC_IT_HSERDY HSE ready interrupt. - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_LSECSS LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB devices) - * @arg @ref RCC_IT_CSS Clock Security System interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. - * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready. - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. - * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. - * @arg @ref RCC_FLAG_LSECSS CSS on LSE failure Detection (*) - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. - * @arg @ref RCC_FLAG_OBLRST Option Byte Load reset - * @arg @ref RCC_FLAG_PINRST Pin reset. - * @arg @ref RCC_FLAG_PORRST POR/PDR reset. - * @arg @ref RCC_FLAG_SFTRST Software reset. - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. - * @arg @ref RCC_FLAG_LPWRRST Low Power reset. - * @note (*) This bit is available in high and medium+ density devices only. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) - -/** - * @} - */ - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32l1xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RCC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h deleted file mode 100644 index 89f0a48..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rcc_ex.h +++ /dev/null @@ -1,1030 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - *

© Copyright(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RCC_EX_H -#define __STM32L1xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/** @addtogroup RCCEx_Private_Constants - * @{ - */ - -#if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\ - || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\ - || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -/* Alias word address of LSECSSON bit */ -#define LSECSSON_BITNUMBER RCC_CSR_LSECSSON_Pos -#define CSR_LSECSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U))) - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/ - -/** - * @} - */ - -/** @addtogroup RCCEx_Private_Macros - * @{ - */ -#if defined(LCD) - -#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD)) - -#else /* Not LCD LINE */ - -#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC) - -#endif /* LCD */ - -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - uint32_t RTCClockSelection; /*!< specifies the RTC clock source. - This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ - -#if defined(LCD) - - uint32_t LCDClockSelection; /*!< specifies the LCD clock source. - This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */ - -#endif /* LCD */ -} RCC_PeriphCLKInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_RTC (0x00000001U) - -#if defined(LCD) - -#define RCC_PERIPHCLK_LCD (0x00000002U) - -#endif /* LCD */ - -/** - * @} - */ - -#if defined(RCC_LSECSS_SUPPORT) -/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line - * @{ - */ -#define RCC_EXTI_LINE_LSECSS (EXTI_IMR_IM19) /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */ -/** - * @} - */ -#endif /* RCC_LSECSS_SUPPORT */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ - || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_AESEN)) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_FSMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ - || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ - || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_LCD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN)) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\ - || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ - || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) - -#define __HAL_RCC_OPAMP_CLK_ENABLE() __HAL_RCC_COMP_CLK_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __HAL_RCC_OPAMP_CLK_DISABLE() __HAL_RCC_COMP_CLK_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */ - -/** @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_SDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\ - UNUSED(tmpreg); \ - } while(0U) -#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - - -/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset - * @brief Forces or releases AHB peripheral reset. - * @{ - */ -#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ - || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST)) - -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST)) -#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST)) -#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST)) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST)) -#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ - || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ - || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) -#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST)) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** @brief Forces or releases APB1 peripheral reset. - */ -#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) - -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ - || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) - -#define __HAL_RCC_OPAMP_FORCE_RESET() __HAL_RCC_COMP_FORCE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __HAL_RCC_OPAMP_RELEASE_RESET() __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -/** @brief Forces or releases APB2 peripheral reset. - */ -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST)) -#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ - || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN)) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN)) - -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN)) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN)) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN)) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN)) -#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ - || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ - || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN)) -#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN)) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) - -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ - || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() __HAL_RCC_COMP_CLK_SLEEP_ENABLE() /* Peripherals COMP and OPAMP share the same clock domain */ -#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() __HAL_RCC_COMP_CLK_SLEEP_DISABLE() /* Peripherals COMP and OPAMP share the same clock domain */ - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -/** @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN)) -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN)) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ - || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U) -#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U) -#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ - || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ - || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_LCD_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U) -#define __HAL_RCC_LCD_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ - || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) - -#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() __HAL_RCC_COMP_IS_CLK_ENABLED() -#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() __HAL_RCC_COMP_IS_CLK_DISABLED() - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U) -#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -#if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\ - || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U) - -#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U) - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U) -#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U) - -#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U) -#define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -#if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\ - || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\ - || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U) -#define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U) - -#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U) - -#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\ - || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\ - || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\ - || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\ - || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U) -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U) - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX) - -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\ - || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\ - || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\ - || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC) - -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED() -#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED() - -#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */ - -#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD) - -#define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U) -#define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U) - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD */ - -/** - * @} - */ - - -#if defined(RCC_LSECSS_SUPPORT) - -/** - * @brief Enable interrupt on RCC LSE CSS EXTI Line 19. - * @retval None - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable interrupt on RCC LSE CSS EXTI Line 19. - * @retval None - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Enable event on RCC LSE CSS EXTI Line 19. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable event on RCC LSE CSS EXTI Line 19. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief RCC LSE CSS EXTI line configuration: set falling edge trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS) - - -/** - * @brief RCC LSE CSS EXTI line configuration: set rising edge trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS) - -/** - * @brief RCC LSE CSS EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do { \ - __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. - * @retval EXTI RCC LSE CSS Line Status. - */ -#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (EXTI->PR & (RCC_EXTI_LINE_LSECSS)) - -/** - * @brief Clear the RCC LSE CSS EXTI flag. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() (EXTI->PR = (RCC_EXTI_LINE_LSECSS)) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS) - -#endif /* RCC_LSECSS_SUPPORT */ - -#if defined(LCD) - -/** @defgroup RCCEx_LCD_Configuration LCD Configuration - * @brief Macros to configure clock source of LCD peripherals. - * @{ - */ - -/** @brief Macro to configures LCD clock (LCDCLK). - * @note LCD and RTC use the same configuration - * @note LCD can however be used in the Stop low power mode if the LSE or LSI is used as the - * LCD clock source. - * - * @param __LCD_CLKSOURCE__ specifies the LCD clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock - */ -#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__) - -/** @brief Macro to get the LCD clock source. - */ -#define __HAL_RCC_GET_LCD_SOURCE() __HAL_RCC_GET_RTC_SOURCE() - -/** @brief Macro to get the LCD clock pre-scaler. - */ -#define __HAL_RCC_GET_LCD_HSE_PRESCALER() __HAL_RCC_GET_RTC_HSE_PRESCALER() - -/** - * @} - */ - -#endif /* LCD */ - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); - -#if defined(RCC_LSECSS_SUPPORT) - -void HAL_RCCEx_EnableLSECSS(void); -void HAL_RCCEx_DisableLSECSS(void); -void HAL_RCCEx_EnableLSECSS_IT(void); -void HAL_RCCEx_LSECSS_IRQHandler(void); -void HAL_RCCEx_LSECSS_Callback(void); - -#endif /* RCC_LSECSS_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RCC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h deleted file mode 100644 index 731ec9e..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc.h +++ /dev/null @@ -1,808 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc.h - * @author MCD Application Team - * @brief Header file of RTC HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RTC_H -#define __STM32L1xx_HAL_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTC_Exported_Types RTC Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ - -} HAL_RTCStateTypeDef; - -/** - * @brief RTC Configuration Structure definition - */ -typedef struct -{ - uint32_t HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - - uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. - This parameter can be a value of @ref RTCEx_Output_selection_Definitions */ - - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. - This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ - - uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. - This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -} RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity */ - - uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content - corresponding to Synchronous pre-scaler factor value (PREDIV_S) - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity. - This field will be used only by HAL_RTC_GetTime function */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. - This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ - - uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit - in CR register to store the operation. - This parameter can be a value of @ref RTC_StoreOperation_Definitions */ -} RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - -} RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - - uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. - This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint32_t Alarm; /*!< Specifies the alarm . - This parameter can be a value of @ref RTC_Alarms_Definitions */ -} RTC_AlarmTypeDef; - -/** - * @brief RTC Handle Structure definition - */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -typedef struct __RTC_HandleTypeDef -#else -typedef struct -#endif -{ - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - - void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ - - void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */ - - void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ - - void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ - - void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - - void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ - -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - -} RTC_HandleTypeDef; - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL LPTIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ - HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ - HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */ - HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */ - HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ - HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ - HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ -} HAL_RTC_CallbackIDTypeDef; - -/** - * @brief HAL RTC Callback pointer definition - */ -typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Constants RTC Exported Constants - * @{ - */ - -/** @defgroup RTC_Hour_Formats RTC Hour Formats - * @{ - */ -#define RTC_HOURFORMAT_24 (0x00000000U) -#define RTC_HOURFORMAT_12 (0x00000040U) - -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) -/** - * @} - */ - - -/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions - * @{ - */ -#define RTC_OUTPUT_POLARITY_HIGH (0x00000000U) -#define RTC_OUTPUT_POLARITY_LOW (0x00100000U) - -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT - * @{ - */ -#define RTC_OUTPUT_TYPE_OPENDRAIN (0x00000000U) -#define RTC_OUTPUT_TYPE_PUSHPULL (0x00040000U) - -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) - -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions Time Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions AM PM Definitions - * @{ - */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) - -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving - * @{ - */ -#define RTC_DAYLIGHTSAVING_SUB1H (0x00020000U) -#define RTC_DAYLIGHTSAVING_ADD1H (0x00010000U) -#define RTC_DAYLIGHTSAVING_NONE (0x00000000U) - -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) -/** - * @} - */ - -/** @defgroup RTC_StoreOperation_Definitions StoreOperation - * @{ - */ -#define RTC_STOREOPERATION_RESET (0x00000000U) -#define RTC_STOREOPERATION_SET (0x00040000U) - -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format - * @{ - */ -#define RTC_FORMAT_BIN (0x000000000U) -#define RTC_FORMAT_BCD (0x000000001U) - -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions Year Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions Month Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) - -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions - * @{ - */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) - -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Definitions Alarm Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions - * @{ - */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE (0x00000000U) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY (0x40000000U) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions - * @{ - */ -#define RTC_ALARMMASK_NONE (0x00000000U) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL (0x80808080U) - -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions Alarms Definitions - * @{ - */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE - -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RTC_Exported_macros RTC Exported Macros - * @{ - */ - -/** @brief Reset RTC handle state - * @param __HANDLE__ RTC handle. - * @retval None - */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) -#else -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @brief Disable the write protection for RTC registers. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xCAU; \ - (__HANDLE__)->Instance->WPR = 0x53U; \ - } while(0U) - -/** - * @brief Enable the write protection for RTC registers. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xFFU; \ - } while(0U) - -/** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) - -/** - * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) - -/** - * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) - -/** - * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) - -/** - * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != 0U)? 1U : 0U) - -/** - * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - -/** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to check. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF - * @retval None - */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) - -/** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @retval None - */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable interrupt on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable interrupt on the RTC Alarm associated Exti line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable event on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable event on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Clear the RTC Alarm associated Exti line flag. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Generate a Software interrupt on RTC Alarm associated Exti line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @} - */ - -/* Include RTC HAL Extended module */ -#include "stm32l1xx_hal_rtc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); - -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @{ - */ -/* RTC Time and Date functions ************************************************/ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @{ - */ -/* RTC Alarm functions ********************************************************/ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @{ - */ -/* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTC_Private_Constants RTC Private Constants - * @{ - */ -#define RTC_TIMEOUT_VALUE 1000U - -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RTC_Private_Macros RTC Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private functions -------------------------------------------------------------*/ -/** @defgroup RTC_Private_Functions RTC Private Functions - * @{ - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); -uint8_t RTC_ByteToBcd2(uint8_t Value); -uint8_t RTC_Bcd2ToByte(uint8_t Value); -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h deleted file mode 100644 index 1c3a224..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_rtc_ex.h +++ /dev/null @@ -1,1218 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc_ex.h - * @author MCD Application Team - * @brief Header file of RTC HAL Extended module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_RTC_EX_H -#define __STM32L1xx_HAL_RTC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup RTCEx RTCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Types RTCEx Exported Types - * @{ - */ - -/** - * @brief RTC Tamper structure definition - */ -typedef struct -{ - uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ - - uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. - This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ - - uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. - This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ - - uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . - This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ - - uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */ - - uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -} RTC_TamperTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants - * @{ - */ - -/** @defgroup RTCEx_Output_selection_Definition RTCEx Output Selection Definition - * @{ - */ -#define RTC_TR_RESERVED_MASK (0x007F7F7FU) -#define RTC_DR_RESERVED_MASK (0x00FFFF3FU) -#define RTC_INIT_MASK (0xFFFFFFFFU) -#define RTC_RSF_MASK (0xFFFFFF5FU) - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ - RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ - RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ - RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ - RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \ - RTC_FLAG_RECALPF)) -#else -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \ - RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \ - RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \ - RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ - RTC_FLAG_TAMP1F | \ - RTC_FLAG_RECALPF)) - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -/** - * @} - */ - -/** @defgroup RTCEx_Backup_Registers_Definition RTCEx Backup Registers Definition - * @{ - */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) -#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFFU) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) -#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) -#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) -#define RTC_IT_TAMP1 ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP1E)) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define RTC_IT_TAMP2 ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP2E)) -#define RTC_IT_TAMP3 ((uint32_t)(RTC_TAFCR_TAMPIE | RTC_TAFCR_TAMP3E)) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions Flags Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F) -#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F) -#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF) -#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF) -#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) -#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) -#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) -#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) -#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) -#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF) -#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF) -#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF) -/** - * @} - */ - -/** @defgroup RTCEx_Output_selection_Definitions Output selection Definitions - * @{ - */ -#define RTC_OUTPUT_DISABLE (0x00000000U) -#define RTC_OUTPUT_ALARMA (0x00200000U) -#define RTC_OUTPUT_ALARMB (0x00400000U) -#define RTC_OUTPUT_WAKEUP (0x00600000U) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) -/** - * @} - */ - -/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions - * @{ - */ -#if RTC_BKP_NUMBER > 0 -#define RTC_BKP_DR0 (0x00000000U) -#define RTC_BKP_DR1 (0x00000001U) -#define RTC_BKP_DR2 (0x00000002U) -#define RTC_BKP_DR3 (0x00000003U) -#define RTC_BKP_DR4 (0x00000004U) -#endif /* RTC_BKP_NUMBER > 0 */ - -#if RTC_BKP_NUMBER > 5 -#define RTC_BKP_DR5 (0x00000005U) -#define RTC_BKP_DR6 (0x00000006U) -#define RTC_BKP_DR7 (0x00000007U) -#define RTC_BKP_DR8 (0x00000008U) -#define RTC_BKP_DR9 (0x00000009U) -#define RTC_BKP_DR10 (0x0000000AU) -#define RTC_BKP_DR11 (0x0000000BU) -#define RTC_BKP_DR12 (0x0000000CU) -#define RTC_BKP_DR13 (0x0000000DU) -#define RTC_BKP_DR14 (0x0000000EU) -#define RTC_BKP_DR15 (0x0000000FU) -#define RTC_BKP_DR16 (0x00000010U) -#define RTC_BKP_DR17 (0x00000011U) -#define RTC_BKP_DR18 (0x00000012U) -#define RTC_BKP_DR19 (0x00000013U) -#endif /* RTC_BKP_NUMBER > 5 */ - -#if RTC_BKP_NUMBER > 20 -#define RTC_BKP_DR20 (0x00000014U) -#define RTC_BKP_DR21 (0x00000015U) -#define RTC_BKP_DR22 (0x00000016U) -#define RTC_BKP_DR23 (0x00000017U) -#define RTC_BKP_DR24 (0x00000018U) -#define RTC_BKP_DR25 (0x00000019U) -#define RTC_BKP_DR26 (0x0000001AU) -#define RTC_BKP_DR27 (0x0000001BU) -#define RTC_BKP_DR28 (0x0000001CU) -#define RTC_BKP_DR29 (0x0000001DU) -#define RTC_BKP_DR30 (0x0000001EU) -#define RTC_BKP_DR31 (0x0000001FU) -#endif /* RTC_BKP_NUMBER > 20 */ - -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) -/** - * @} - */ - -/** @defgroup RTCEx_Time_Stamp_Edges_Definitions Time Stamp Edges Definitions - * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING (0x00000000U) -#define RTC_TIMESTAMPEDGE_FALLING (0x00000008U) - -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions - * @{ - */ -#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define RTC_TAMPER_2 RTC_TAFCR_TAMP2E -#define RTC_TAMPER_3 RTC_TAFCR_TAMP3E -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define IS_RTC_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET)) -#else -#define IS_RTC_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_RISINGEDGE (0x00000000U) -#define RTC_TAMPERTRIGGER_FALLINGEDGE (0x00000002U) -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) -#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -/** - * @} - */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** @defgroup RTCEx_Tamper_Filter_Definitions RTCex Tamper Filter Definitions - * @{ - */ -#define RTC_TAMPERFILTER_DISABLE (0x00000000U) /*!< Tamper filter is disabled */ - -#define RTC_TAMPERFILTER_2SAMPLE (0x00000800U) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE (0x00001000U) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE (0x00001800U) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ - -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 (0x00000000U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 (0x00000100U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 (0x00000200U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (0x00000300U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 (0x00000400U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (0x00000500U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (0x00000600U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (0x00000700U) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ - -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions - * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK (0x00000000U) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK (0x00002000U) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK (0x00004000U) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (0x00006000U) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions TimeStampOnTamperDetection Definitions - * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event is not saved */ - -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pull_Up_Definitions Tamper Pull-Up Definitions - * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE (0x00000000U) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE (RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ - -#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) -/** - * @} - */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions - * @{ - */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 (0x00000000U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 (0x00000001U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 (0x00000002U) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (0x00000003U) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS (0x00000004U) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (0x00000006U) - -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) - -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTCEx_Digital_Calibration_Definitions Digital Calibration Definitions - * @{ - */ -#define RTC_CALIBSIGN_POSITIVE (0x00000000U) -#define RTC_CALIBSIGN_NEGATIVE (0x00000080U) - -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \ - ((SIGN) == RTC_CALIBSIGN_NEGATIVE)) - -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_Calib_Period_Definitions Smooth Calib Period Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC (0x00000000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC (0x00002000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC (0x00004000U) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ - -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_Calib_Plus_Pulses_Definitions Smooth Calib Plus Pulses Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET (0x00008000U) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET (0x00000000U) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ - -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_Calib_Minus_Pulses_Definitions Smooth Calib Minus Pulses Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU) -/** - * @} - */ - -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions Add 1 Second Parameter Definitions - * @{ - */ -#define RTC_SHIFTADD1S_RESET (0x00000000U) -#define RTC_SHIFTADD1S_SET (0x80000000U) - -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) -/** - * @} - */ - -/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value Substract Fraction Of Second Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU) -/** - * @} - */ - -/** @defgroup RTCEx_Calib_Output_Selection_Definitions Calib Output Selection Definitions - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ (0x00000000U) -#define RTC_CALIBOUTPUT_1HZ (0x00080000U) - -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) -/** - * @} - */ - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value - * @{ - */ -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions Alarm Sub Seconds Masks Definitions - * @{ - */ -#define RTC_ALARMSUBSECONDMASK_ALL (0x00000000U) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 (0x01000000U) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 (0x02000000U) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 (0x03000000U) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 (0x04000000U) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 (0x05000000U) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 (0x06000000U) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 (0x07000000U) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 (0x08000000U) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 (0x09000000U) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 (0x0A000000U) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 (0x0B000000U) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 (0x0C000000U) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 (0x0D000000U) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 (0x0E000000U) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE (0x0F000000U) /*!< SS[14:0] are compared and must match - to activate alarm. */ - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) -/** - * @} - */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros - * @{ - */ - -/* ---------------------------------WAKEUPTIMER---------------------------------*/ -/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer - * @{ - */ -/** - * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) - -/** - * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) - -/** - * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) - -/** - * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) - -/** - * @brief Enable the Coarse calibration process. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE)) - -/** - * @brief Disable the Coarse calibration process. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE)) - -/** - * @brief Enable the RTC calibration output. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) - -/** - * @brief Disable the calibration output. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) - -/** - * @brief Enable the clock reference detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) - -/** - * @brief Disable the clock reference detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) - -/** - * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP1E) - -/** - * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP1E) - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC)\ - || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA)\ - || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA)\ - || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP2E) - -/** - * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP2E) - -/** - * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP3E) - -/** - * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->TAFCR, RTC_TAFCR_TAMP3E) - - -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt - * @arg RTC_IT_TAMP3: Tamper3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP1F) != RESET) ? SET : RESET) : \ - ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP2F) != RESET) ? SET : RESET) : \ - (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP3F) != RESET) ? SET : RESET)) -#else -/** - * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & RTC_ISR_TAMP1F) != RESET) ? SET : RESET) - -#endif - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) - * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) - * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, - * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, - * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE - * STM32L151xDX, STM32L152xDX, STM32L162xDX - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT(((__HANDLE__)->Instance->TAFCR), RTC_TAFCR_TAMPIE) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) - * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) - * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, - * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, - * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE - * STM32L151xDX, STM32L152xDX, STM32L162xDX - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT(((__HANDLE__)->Instance->TAFCR), RTC_TAFCR_TAMPIE) - -/** - * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP1: Tamper1 interrupt - * @arg RTC_IT_TAMP2: Tamper2 interrupt (*) - * @arg RTC_IT_TAMP3: Tamper3 interrupt (*) - * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, - * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, - * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE - * STM32L151xDX, STM32L152xDX, STM32L162xDX - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & RTC_TAFCR_TAMPIE) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET) - -/** - * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != RESET)? SET : RESET) - -/** - * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** - * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC TimeStamp Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC WakeUpTimer Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @arg RTC_FLAG_TAMP2F (*) - * @arg RTC_FLAG_TAMP3F (*) - * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, - * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, - * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE - * STM32L151xDX, STM32L152xDX, STM32L162xDX - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC)\ - || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA)\ - || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA)\ - || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF - * @retval None - */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @arg RTC_FLAG_TAMP2F (*) - * @arg RTC_FLAG_TAMP3F (*) - * @note (*) Available only on devices STM32L100xBA, STM32L151xBA, STM32L152xBA, STM32L100xC, - * STM32L151xC, STM32L152xC, STM32L162xC, STM32L151xCA, STM32L151xD, STM32L152xCA, - * STM32L152xD, STM32L162xCA, STM32L162xD, STM32L151xE, STM32L152xE, STM32L162xE - * STM32L151xDX, STM32L152xDX, STM32L162xDX - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_WUTF - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable event on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable event on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); } while(0); - -/** - * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. - * This parameter can be: - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); } while(0); - -/** - * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Clear the RTC WakeUp Timer associated Exti line flag. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); } while(0); - -/** - * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. - * This parameter can be: - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); } while(0); - -/** - * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - -/* RTC TimeStamp and Tamper functions *****************************************/ -/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -/** - * @} - */ - -/* RTC Wake-up functions ******************************************************/ -/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions - * @{ - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/* Extended Control functions ************************************************/ -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @{ - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); - -HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value); -HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); -#else -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/* Extended RTC features functions *******************************************/ -/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @{ - */ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Constants RTCEx Private Constants - * @{ - */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (0x00080000U) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT (0x00100000U) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Macros RTCEx Private Macros - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h deleted file mode 100644 index d1bbdd0..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim.h +++ /dev/null @@ -1,1828 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32L1xx_HAL_TIM_H -#define STM32L1xx_HAL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - */ -typedef struct -{ - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode - @note When the Master/slave mode is enabled, the effect of - an event on the trigger input (TRGI) is delayed to allow a - perfect synchronization between the current timer and its - slaves (through TRGO). It is not mandatory in case of timer - synchronization mode. */ -} TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct -{ - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -} TIM_SlaveConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -} HAL_TIM_StateTypeDef; - -/** - * @brief TIM Channel States definition - */ -typedef enum -{ - HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ - HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ - HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ -} HAL_TIM_ChannelStateTypeDef; - -/** - * @brief DMA Burst States definition - */ -typedef enum -{ - HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ - HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ - HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ -} HAL_TIM_DMABurstStateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -} HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -typedef struct __TIM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ - __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ - void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ - void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ - void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ - void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ - void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ - void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ - void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ - void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ - void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ - void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ - void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ - void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ - void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ - void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ - void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ - void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ - void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ - void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ - void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ - void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ - void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} TIM_HandleTypeDef; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL TIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ -} HAL_TIM_CallbackIDTypeDef; - -/** - * @brief HAL TIM Callback pointer definition - */ -typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ - -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ -#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ -#define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 0x00000000U -#define TIM_DMABASE_CR2 0x00000001U -#define TIM_DMABASE_SMCR 0x00000002U -#define TIM_DMABASE_DIER 0x00000003U -#define TIM_DMABASE_SR 0x00000004U -#define TIM_DMABASE_EGR 0x00000005U -#define TIM_DMABASE_CCMR1 0x00000006U -#define TIM_DMABASE_CCMR2 0x00000007U -#define TIM_DMABASE_CCER 0x00000008U -#define TIM_DMABASE_CNT 0x00000009U -#define TIM_DMABASE_PSC 0x0000000AU -#define TIM_DMABASE_ARR 0x0000000BU -#define TIM_DMABASE_CCR1 0x0000000DU -#define TIM_DMABASE_CCR2 0x0000000EU -#define TIM_DMABASE_CCR3 0x0000000FU -#define TIM_DMABASE_CCR4 0x00000010U -#define TIM_DMABASE_DCR 0x00000012U -#define TIM_DMABASE_DMAR 0x00000013U -#define TIM_DMABASE_OR 0x00000014U -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ -#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ -#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ -#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ - -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ -#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ -#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ -#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity - * @{ - */ -#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ -#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ -#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ -#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ -#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ -#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ -#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ -#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ -#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ -#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ -#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ -#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ -#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ -#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ -#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ -#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ -#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ -#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ -#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ -#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ -#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ -#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ -#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ -#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ -#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ -#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ -#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ -#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ -#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ -#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ -#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ -#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ -#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ -#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ -#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ -#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ -#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ -#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ -#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ -#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ -#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ -#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ -#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ -#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ -#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ -#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ -#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - } while(0) -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } while(0) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ - == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR4 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__HANDLE__)->Instance->CCR4)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE)) - -/** - * @brief Enable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @note When fast mode is enabled an active edge on the trigger input acts - * like a compare match on CCx output. Delay to sample the trigger - * input and to activate CCx output is reduced to 3 clock cycles. - * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ - ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE)) - -/** - * @brief Disable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @note When fast mode is disabled CCx output behaves normally depending - * on counter and CCRx values even when the trigger is ON. The minimum - * delay to activate CCx output when an active edge occurs on the - * trigger input is 5 clock cycles. - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR)) - -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_OR)) - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) - -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_NONE)) - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ - (__HANDLE__)->ChannelState[3]) - -#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32l1xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); - -/* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -void TIM_ResetCallback(TIM_HandleTypeDef *htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32L1xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h deleted file mode 100644 index c6c8e2f..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_tim_ex.h +++ /dev/null @@ -1,182 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32L1xx_HAL_TIM_EX_H -#define STM32L1xx_HAL_TIM_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -/* @note STM32L1XX devices are organized in 6 categories: Cat.1, Cat.2, Cat.3, Cat.4, Cat.5, Cat.6. - Remap capabilities depend on the device category. As the DMA2 controller is available only in - Cat.3, Cat.4,Cat.5 and Cat.6 devices it is used to discriminate Cat.1 and Cat.2 devices v.s. - Cat.3, Cat.4, Cat.5 and Cat.6 devices. */ -#if defined(DMA2) -#define TIM_TIM2_ITR1_TIM10_OC (0x00000000) /*!< TIM2 ITR1 input is connected to TIM10 OC */ -#define TIM_TIM2_ITR1_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM2 ITR1 input is connected to TIM5 TGO */ -#endif /* DMA2 */ - -#if defined(DMA2) -#define TIM_TIM3_ITR2_TIM11_OC (0x00000000) /*!< TIM3 ITR2 input is connected to TIM11 OC */ -#define TIM_TIM3_ITR2_TIM5_TGO TIM2_OR_ITR1_RMP /*!< TIM3 ITR2 input is connected to TIM5 TGO */ -#endif /* DMA2 */ - -#if defined(DMA2) -#define TIM_TIM9_ITR1_TIM3_TGO (0x00000000) /*!< TIM9 ITR1 input is connected to TIM3 TGO */ -#define TIM_TIM9_ITR1_TS TIM9_OR_ITR1_RMP /*!< TIM9 ITR1 input is connected to touch sensing I/O */ -#endif /* DMA2 */ -#define TIM_TIM9_GPIO (0x00000000) /*!< TIM9 Channel1 is connected to GPIO */ -#define TIM_TIM9_LSE TIM_OR_TI1RMP_0 /*!< TIM9 Channel1 is connected to LSE internal clock */ -#define TIM_TIM9_GPIO1 TIM_OR_TI1RMP_1 /*!< TIM9 Channel1 is connected to GPIO */ -#define TIM_TIM9_GPIO2 TIM_OR_TI1RMP /*!< TIM9 Channel1 is connected to GPIO */ - -#if defined(DMA2) -#define TIM_TIM10_TI1RMP (0x00000000) /*!< TIM10 Channel 1 depends on TI1_RMP */ -#define TIM_TIM10_RI TIM_OR_TI1_RMP_RI /*!< TIM10 Channel 1 is connected to RI */ -#define TIM_TIM10_ETR_LSE (0x00000000) /*!< TIM10 ETR input is connected to LSE clock */ -#define TIM_TIM10_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM10 ETR input is connected to TIM9 TGO */ -#endif /* DMA2 */ -#define TIM_TIM10_GPIO (0x00000000) /*!< TIM10 Channel1 is connected to GPIO */ -#define TIM_TIM10_LSI TIM_OR_TI1RMP_0 /*!< TIM10 Channel1 is connected to LSI internal clock */ -#define TIM_TIM10_LSE TIM_OR_TI1RMP_1 /*!< TIM10 Channel1 is connected to LSE internal clock */ -#define TIM_TIM10_RTC TIM_OR_TI1RMP /*!< TIM10 Channel1 is connected to RTC wakeup interrupt */ - -#if defined(DMA2) -#define TIM_TIM11_TI1RMP (0x00000000) /*!< TIM11 Channel 1 depends on TI1_RMP */ -#define TIM_TIM11_RI TIM_OR_TI1_RMP_RI /*!< TIM11 Channel 1 is connected to RI */ -#define TIM_TIM11_ETR_LSE (0x00000000) /*!< TIM11 ETR input is connected to LSE clock */ -#define TIM_TIM11_ETR_TIM9_TGO TIM_OR_ETR_RMP /*!< TIM11 ETR input is connected to TIM9 TGO */ -#endif /* DMA2 */ -#define TIM_TIM11_GPIO (0x00000000) /*!< TIM11 Channel1 is connected to GPIO */ -#define TIM_TIM11_MSI TIM_OR_TI1RMP_0 /*!< TIM11 Channel1 is connected to MSI internal clock */ -#define TIM_TIM11_HSE_RTC TIM_OR_TI1RMP_1 /*!< TIM11 Channel1 is connected to HSE_RTC clock */ -#define TIM_TIM11_GPIO1 TIM_OR_TI1RMP /*!< TIM11 Channel1 is connected to GPIO */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ -#if defined(DMA2) -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ( (((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO))) || \ - (((INSTANCE) == TIM3) && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO))) || \ - (((INSTANCE) == TIM9) && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2))) || \ - (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC))) || \ - (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1))) \ - ) -#else -#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ - ( (((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2))) || \ - (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC))) || \ - (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1))) \ - ) -#endif /* DMA2 */ - -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32L1xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h b/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h deleted file mode 100644 index 1636cc8..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Inc/stm32l1xx_hal_uart.h +++ /dev/null @@ -1,846 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32L1xx_HAL_UART_H -#define __STM32L1xx_HAL_UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal_def.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) - - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UART_Word_Length */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). - This parameter can be a value of @ref UART_Over_Sampling */ -} UART_InitTypeDef; - -/** - * @brief HAL UART State structures definition - * @note HAL UART State value is a combination of 2 different substates: gState and RxState. - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral not initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef enum -{ - HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized - Value is allowed for gState and RxState */ - HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ - HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing - Value is allowed for gState only */ - HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing - Value is allowed for RxState only */ - HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ - HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state - Value is allowed for gState only */ - HAL_UART_STATE_ERROR = 0xE0U /*!< Error - Value is allowed for gState only */ -} HAL_UART_StateTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. - This parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ - void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ - void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ - void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ - void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ - void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ - void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ - void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ - void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ - - void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ - void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -} UART_HandleTypeDef; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief HAL UART Callback ID enumeration definition - */ -typedef enum -{ - HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ - HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ - HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ - HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ - HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ - HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ - HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ - HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ - - HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ - HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ - -} HAL_UART_CallbackIDTypeDef; - -/** - * @brief HAL UART Callback pointer definition - */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_Error_Code UART Error Code - * @{ - */ -#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ -#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ -#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ -#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ -#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup UART_Word_Length UART Word Length - * @{ - */ -#define UART_WORDLENGTH_8B 0x00000000U -#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) -/** - * @} - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_1 0x00000000U -#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U -#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) -#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U -#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) -#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) -#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX ((uint32_t)USART_CR1_RE) -#define UART_MODE_TX ((uint32_t)USART_CR1_TE) -#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U -#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U -#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U -#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) -/** - * @} - */ - -/** @defgroup UART_WakeUp_functions UART Wakeup Functions - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U -#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) -/** - * @} - */ - -/** @defgroup UART_Flags UART FLags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the SR register - * @{ - */ -#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) -#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) -#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) -#define UART_FLAG_TC ((uint32_t)USART_SR_TC) -#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) -#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) -#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) -#define UART_FLAG_NE ((uint32_t)USART_SR_NE) -#define UART_FLAG_FE ((uint32_t)USART_SR_FE) -#define UART_FLAG_PE ((uint32_t)USART_SR_PE) -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupt Definitions - * Elements values convention: 0xY000XXXX - * - XXXX : Interrupt mask (16 bits) in the Y register - * - Y : Interrupt source register (2bits) - * - 0001: CR1 register - * - 0010: CR2 register - * - 0011: CR3 register - * @{ - */ - -#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) -#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) -#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) -#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) -#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) - -#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) - -#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) -#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle gstate & RxState - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ - -/** @brief Flushes the UART DR register - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) - -/** @brief Checks whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg UART_FLAG_LBD: LIN Break detection flag - * @arg UART_FLAG_TXE: Transmit data register empty flag - * @arg UART_FLAG_TC: Transmission Complete flag - * @arg UART_FLAG_RXNE: Receive data register not empty flag - * @arg UART_FLAG_IDLE: Idle Line detection flag - * @arg UART_FLAG_ORE: Overrun Error flag - * @arg UART_FLAG_NE: Noise Error flag - * @arg UART_FLAG_FE: Framing Error flag - * @arg UART_FLAG_PE: Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg UART_FLAG_LBD: LIN Break detection flag. - * @arg UART_FLAG_TC: Transmission Complete flag. - * @arg UART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register followed by a read - * operation to USART_DR register. - * @note RXNE flag can be also cleared by a read to the USART_DR register. - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register followed by a write operation to USART_DR register. - * @note TXE flag is cleared only by a write to the USART_DR register. - * - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Clears the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg = 0x00U; \ - tmpreg = (__HANDLE__)->Instance->SR; \ - tmpreg = (__HANDLE__)->Instance->DR; \ - UNUSED(tmpreg); \ - } while(0U) - -/** @brief Clears the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clears the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clears the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Clears the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_PE: Parity Error interrupt - * @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) - -/** @brief Checks whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * UART Handle selects the USARTx or UARTy peripheral - * (USART,UART availability and x,y values depending on device). - * @param __IT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg UART_IT_LBD: LIN Break detection interrupt - * @arg UART_IT_TXE: Transmit Data Register empty interrupt - * @arg UART_IT_TC: Transmission complete interrupt - * @arg UART_IT_RXNE: Receive Data register not empty interrupt - * @arg UART_IT_IDLE: Idle line detection interrupt - * @arg UART_IT_ERR: Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) - -/** @brief Enable CTS flow control - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0U) - -/** @brief Disable CTS flow control - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0U) - -/** @brief Enable RTS flow control - * This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0U) - -/** @brief Disable RTS flow control - * This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) - * and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * The Handle Instance can be any USARTx (supporting the HW Flow control feature). - * It is used to select the USART peripheral (USART availability and x value depending on device). - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0U) - -/** @brief Macro to enable the UART's one bit sample method - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Macro to disable the UART's one bit sample method - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) - -/** @brief Enable UART - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -/** @brief UART interruptions flag mask - * - */ -#define UART_IT_MASK 0x0000FFFFU - -#define UART_CR1_REG_INDEX 1U -#define UART_CR2_REG_INDEX 2U -#define UART_CR3_REG_INDEX 3U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ - ((LENGTH) == UART_WORDLENGTH_9B)) -#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) -#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ - ((STOPBITS) == UART_STOPBITS_2)) -#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ - ((PARITY) == UART_PARITY_EVEN) || \ - ((PARITY) == UART_PARITY_ODD)) -#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == UART_HWCONTROL_NONE) || \ - ((CONTROL) == UART_HWCONTROL_RTS) || \ - ((CONTROL) == UART_HWCONTROL_CTS) || \ - ((CONTROL) == UART_HWCONTROL_RTS_CTS)) -#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) -#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ - ((STATE) == UART_STATE_ENABLE)) -#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ - ((SAMPLING) == UART_OVERSAMPLING_8)) -#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) -#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) -#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) -#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 4000000U) -#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) - -#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(4U*(_BAUD_))) -#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ -#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ - (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U)) + \ - (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) - -#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*25U)/(2U*(_BAUD_))) -#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ -#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) (((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ - ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ - (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32L1xx_HAL_UART_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c deleted file mode 100644 index 78e04d6..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal.c +++ /dev/null @@ -1,569 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup HAL_Private_Defines HAL Private Defines - * @{ - */ - -/** - * @brief STM32L1xx HAL Driver version number V1.4.3 - */ -#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L1xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\ - |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32L1xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK (0x00000FFFU) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/* Exported variables --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Variables - * @{ - */ -__IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */ -uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the Flash interface, the NVIC allocation and initial clock - configuration. It initializes the source of time base also when timeout - is needed and the backup domain when enabled. - (+) De-initialize common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. - -@endverbatim - * @{ - */ - -/** - * @brief This function configures the Flash prefetch, - * configures time base source, NVIC and Low level hardware - * @note This function is called at the beginning of program after reset and before - * the clock configuration - * @note The time base configuration is based on MSI clock when exiting from Reset. - * Once done, time base tick start incrementing. - * In the default implementation,Systick is used as source of time base. - * the tick variable is incremented each 1ms in its ISR. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - { - status = HAL_ERROR; - } - else - { - /* Init the low level hardware */ - HAL_MspInit(); - } - - /* Return function status */ - return status; -} - -/** - * @brief This function de-initializes common part of the HAL and stops the source - * of time base. - * @note This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB_FORCE_RESET(); - __HAL_RCC_AHB_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base: - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (uwTickFreq != 0U) - { - /*Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U) - { - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Get the unique device identifier - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick += uwTickFreq; -} - -/** - * @brief Provide a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function returns a tick priority. - * @retval tick priority - */ -uint32_t HAL_GetTickPrio(void) -{ - return uwTickPrio; -} - -/** - * @brief Set new tick Freq. - * @param Freq tick frequency - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t prevTickFreq; - - assert_param(IS_TICKFREQ(Freq)); - - if (uwTickFreq != Freq) - { - /* Back up uwTickFreq frequency */ - prevTickFreq = uwTickFreq; - - /* Update uwTickFreq global variable used by HAL_InitTick() */ - uwTickFreq = Freq; - - /* Apply the new tick Freq */ - status = HAL_InitTick(uwTickPrio); - - if (status != HAL_OK) - { - /* Restore previous tick frequency */ - uwTickFreq = prevTickFreq; - } - } - - return status; -} - -/** - * @brief Return tick frequency. - * @retval tick period in Hz - */ -uint32_t HAL_GetTickFreq(void) -{ - return uwTickFreq; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a period to guaranty minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += (uint32_t)(uwTickFreq); - } - - while((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend the Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Resume the Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Return the HAL revision - * @retval version: 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32L1xx_HAL_VERSION; -} - -/** - * @brief Return the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16U); -} - -/** - * @brief Return the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Return the first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier 31:0 bits - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Return the second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier 63:32 bits - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U)))); -} - -/** - * @brief Return the third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier 95:64 bits - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U)))); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions - * @brief DBGMCU Peripheral Control functions - * -@verbatim - =============================================================================== - ##### DBGMCU Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c deleted file mode 100644 index d88dcf4..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_cortex.c +++ /dev/null @@ -1,513 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using Cortex HAL driver *** - =========================================================== - [..] - This section provide functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M3 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function - - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() - - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() - - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest pre-emption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure Systick using Cortex HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for 1 msec interrupts. - - (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32l1xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* - Additional Tables: CORTEX_NVIC_Priority_Table - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - ========================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - ========================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority - | | | 4 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - | | | 3 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bits for subpriority - -------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bits for subpriority - ========================================================================================================================== -*/ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provide the Cortex HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Sets the priority grouping field (pre-emption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) - * @param PreemptPriority The pre-emption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** - * @brief Enable the MPU. - * @param MPU_Control Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk); - - /* Ensure MPU setting take effects */ - __DSB(); - __ISB(); -} - -/** - * @brief Disable the MPU. - * @retval None - */ -void HAL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - - /* Disable the MPU and clear the control register*/ - MPU->CTRL = 0; -} - -/** - * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - if ((MPU_Init->Enable) != RESET) - { - /* Check the parameters */ - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); - } - else - { - MPU->RBAR = 0x00; - MPU->RASR = 0x00; - } -} -#endif /* __MPU_PRESENT */ - -/** - * @brief Gets the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @param PriorityGroup the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c deleted file mode 100644 index bedf33b..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dma.c +++ /dev/null @@ -1,908 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Channel - (except for internal SRAM / FLASH memories: no initialization is - necessary). Please refer to the Reference manual for connection between peripherals - and DMA requests. - - (#) For a given Channel, program the required configuration through the following parameters: - Channel request, Transfer Direction, Source and Destination data formats, - Circular or Normal mode, Channel Priority level, Source and Destination Increment mode - using HAL_DMA_Init() function. - - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. - In this case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function to register callbacks with HAL_DMA_RegisterCallback(). - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @{ - */ - -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Channel source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Channel priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and initialize the associated handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp; - - /* Check the DMA handle allocation */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - -#if defined (DMA2) - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA2; - } -#else - /* calculation of the channel index */ - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; -#endif - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Get the CR register value */ - tmp = hdma->Instance->CCR; - - /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ - tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | - DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); - - /* Prepare the DMA Channel configuration */ - tmp |= hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* Write to DMA Channel CR register */ - hdma->Instance->CCR = tmp; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Allocate lock resource and initialize it */ - hdma->Lock = HAL_UNLOCKED; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA peripheral. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - - /* Check the DMA handle allocation */ - if (NULL == hdma ) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Channelx */ - __HAL_DMA_DISABLE(hdma); - -#if defined (DMA2) - /* Compute the channel index */ - if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) - { - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; - } - else - { - /* DMA2 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA2; - } -#else - /* calculation of the channel index */ - /* DMA1 */ - hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; - hdma->DmaBaseAddress = DMA1; -#endif - - /* Reset DMA Channel CR register */ - hdma->Instance->CCR = 0U; - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Clean callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Initialise the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions - * @brief Input and Output operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Configure the source, destination address and the data length & clear flags*/ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the transfer complete interrupt */ - /* Enable the transfer Error interrupt */ - if(NULL != hdma->XferHalfCpltCallback ) - { - /* Enable the Half transfer complete interrupt as well */ - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - } - else - { - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); - } - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Remain BUSY */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Abort the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DMA peripheral state */ - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return status; - } -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - status = HAL_ERROR; - } - else - { - /* Disable DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Disable the channel */ - __HAL_DMA_DISABLE(hdma); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Call User Abort callback */ - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - } - return status; -} - -/** - * @brief Polling for transfer complete. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CompleteLevel Specifies the DMA level complete. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) -{ - uint32_t temp; - uint32_t tickstart; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* no transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode */ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if (HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Transfer Complete flag */ - temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU); - } - else - { - /* Half Transfer Complete flag */ - temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU); - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - while((hdma->DmaBaseAddress->ISR & temp) == 0U) - { - if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - } - - if(HAL_DMA_FULL_TRANSFER == CompleteLevel) - { - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU)); - - /* The selected Channelx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - hdma->State = HAL_DMA_STATE_READY; - } - else - { - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)); - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @brief Handle DMA interrupt request. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t flag_it = hdma->DmaBaseAddress->ISR; - uint32_t source_it = hdma->Instance->CCR; - - /* Half Transfer Complete Interrupt management ******************************/ - if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the half transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); - } - /* Clear the half transfer complete flag */ - hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); - - /* DMA peripheral state is not updated in Half Transfer */ - /* but in Transfer Complete case */ - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - - /* Transfer Complete Interrupt management ***********************************/ - else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U)) - { - - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ - /* Disable the transfer complete and error interrupt */ - /* if the DMA mode is not CIRCULAR */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - } - /* Clear the transfer complete flag */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - - /* Transfer Error Interrupt management **************************************/ - else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) - { - /* When a DMA transfer error occurs */ - /* A hardware clear of its EN bits is performed */ - /* Disable ALL DMA IT */ - __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); - - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TE; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } - else - { - /* Nothing To Do */ - } - return; -} - -/** - * @brief Register callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback pointer to private callbacsk function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param CallbackID User Callback identifer - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - - - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the DMA handle state. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - /* Return DMA handle state */ - return hdma->State; -} - -/** - * @brief Return the DMA error code. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Channel. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear all flags */ - hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); - - /* Configure DMA Channel data length */ - hdma->Instance->CNDTR = DataLength; - - /* Memory to Peripheral */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Channel destination address */ - hdma->Instance->CPAR = DstAddress; - - /* Configure DMA Channel source address */ - hdma->Instance->CMAR = SrcAddress; - } - /* Peripheral to Memory */ - else - { - /* Configure DMA Channel source address */ - hdma->Instance->CPAR = SrcAddress; - - /* Configure DMA Channel destination address */ - hdma->Instance->CMAR = DstAddress; - } -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c deleted file mode 100644 index 8d07904..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_exti.c +++ /dev/null @@ -1,559 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_exti.c - * @author MCD Application Team - * @brief EXTI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### EXTI Peripheral features ##### - ============================================================================== - [..] - (+) Each Exti line can be configured within this driver. - - (+) Exti line can be configured in 3 different modes - (++) Interrupt - (++) Event - (++) Both of them - - (+) Configurable Exti lines can be configured with 3 different triggers - (++) Rising - (++) Falling - (++) Both of them - - (+) When set in interrupt mode, configurable Exti lines have two different - interrupts pending registers which allow to distinguish which transition - occurs: - (++) Rising edge pending interrupt - (++) Falling - - (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can - be selected through multiplexer. - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). - (++) Choose the interrupt line number by setting "Line" member from - EXTI_ConfigTypeDef structure. - (++) Configure the interrupt and/or event mode using "Mode" member from - EXTI_ConfigTypeDef structure. - (++) For configurable lines, configure rising and/or falling trigger - "Trigger" member from EXTI_ConfigTypeDef structure. - (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" - member from GPIO_InitTypeDef structure. - - (#) Get current Exti configuration of a dedicated line using - HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - - (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). - (++) Provide exiting handle as first parameter. - (++) Provide which callback will be registered using one value from - EXTI_CallbackIDTypeDef. - (++) Provide callback function pointer. - - (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ -/** MISRA C:2012 deviation rule has been granted for following rule: - * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out - * of bounds [0,3] in following API : - * HAL_EXTI_SetConfigLine - * HAL_EXTI_GetConfigLine - * HAL_EXTI_ClearConfigLine - */ - -#ifdef HAL_EXTI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup EXTI_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_Exported_Functions_Group1 - * @brief Configuration functions - * -@verbatim - =============================================================================== - ##### Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Set configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on EXTI configuration to be set. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_EXTI_LINE(pExtiConfig->Line)); - assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); - - /* Assign line number to handle */ - hexti->Line = pExtiConfig->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* Configure triggers for configurable lines */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); - - /* Configure rising trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) - { - EXTI->RTSR |= maskline; - } - else - { - EXTI->RTSR &= ~maskline; - } - - /* Configure falling trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) - { - EXTI->FTSR |= maskline; - } - else - { - EXTI->FTSR &= ~maskline; - } - - - /* Configure gpio port selection in case of gpio exti line */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - SYSCFG->EXTICR[linepos >> 2u] = regval; - } - } - - /* Configure interrupt mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) - { - EXTI->IMR |= maskline; - } - else - { - EXTI->IMR &= ~maskline; - } - - /* Configure event mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) - { - EXTI->EMR |= maskline; - } - else - { - EXTI->EMR &= ~maskline; - } - - return HAL_OK; -} - -/** - * @brief Get configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on structure to store Exti configuration. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* Store handle line number to configuration structure */ - pExtiConfig->Line = hexti->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Get core mode : interrupt */ - - /* Check if selected line is enable */ - if ((EXTI->IMR & maskline) != 0x00u) - { - pExtiConfig->Mode = EXTI_MODE_INTERRUPT; - } - else - { - pExtiConfig->Mode = EXTI_MODE_NONE; - } - - /* Get event mode */ - /* Check if selected line is enable */ - if ((EXTI->EMR & maskline) != 0x00u) - { - pExtiConfig->Mode |= EXTI_MODE_EVENT; - } - - /* 2] Get trigger for configurable lines : rising */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - /* Check if configuration of selected line is enable */ - if ((EXTI->RTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING; - } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } - - /* Get falling configuration */ - /* Check if configuration of selected line is enable */ - if ((EXTI->FTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; - } - - /* Get Gpio port selection for gpio lines */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); - } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - /* No Trigger selected */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; - } - - return HAL_OK; -} - -/** - * @brief Clear whole configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Clear interrupt mode */ - EXTI->IMR = (EXTI->IMR & ~maskline); - - /* 2] Clear event mode */ - EXTI->EMR = (EXTI->EMR & ~maskline); - - /* 3] Clear triggers in case of configurable lines */ - if ((hexti->Line & EXTI_CONFIG) != 0x00u) - { - EXTI->RTSR = (EXTI->RTSR & ~maskline); - EXTI->FTSR = (EXTI->FTSR & ~maskline); - - /* Get Gpio port selection for gpio lines */ - if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - SYSCFG->EXTICR[linepos >> 2u] = regval; - } - } - - return HAL_OK; -} - -/** - * @brief Register callback for a dedicated Exti line. - * @param hexti Exti handle. - * @param CallbackID User callback identifier. - * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. - * @param pPendingCbfn function pointer to be stored as callback. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) -{ - HAL_StatusTypeDef status = HAL_OK; - - switch (CallbackID) - { - case HAL_EXTI_COMMON_CB_ID: - hexti->PendingCallback = pPendingCbfn; - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Store line number as handle private field. - * @param hexti Exti handle. - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - else - { - /* Store line number as handle private field */ - hexti->Line = ExtiLine; - - return HAL_OK; - } -} - -/** - * @} - */ - -/** @addtogroup EXTI_Exported_Functions_Group2 - * @brief EXTI IO functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Handle EXTI interrupt request. - * @param hexti Exti handle. - * @retval none. - */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t maskline; - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Get pending bit */ - regval = (EXTI->PR & maskline); - if (regval != 0x00u) - { - /* Clear pending bit */ - EXTI->PR = maskline; - - /* Call callback */ - if (hexti->PendingCallback != NULL) - { - hexti->PendingCallback(); - } - } -} - -/** - * @brief Get interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be checked. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval 1 if interrupt is pending else 0. - */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* return 1 if bit is set else 0 */ - regval = ((EXTI->PR & maskline) >> linepos); - return regval; -} - -/** - * @brief Clear interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be clear. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval None. - */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Clear Pending bit */ - EXTI->PR = maskline; -} - -/** - * @brief Generate a software interrupt for a dedicated line. - * @param hexti Exti handle. - * @retval None. - */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Generate Software interrupt */ - EXTI->SWIER = maskline; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_EXTI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c deleted file mode 100644 index 30c7ad0..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash.c +++ /dev/null @@ -1,721 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) Option Bytes programming - - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32L1xx devices. - - (#) FLASH Memory I/O Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase page - (++) Program functions: Fast Word and Half Page(should be - executed from internal SRAM). - - (#) DATA EEPROM Programming functions: this group includes all - needed functions to erase and program the DATA EEPROM memory: - (++) Lock and Unlock the DATA EEPROM interface. - (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase - Double Word (should be executed from internal SRAM). - (++) Program functions: Fast Program Byte, Fast Program Half-Word, - FastProgramWord, Program Byte, Program Half-Word, - Program Word and Program Double-Word (should be executed - from internal SRAM). - - (#) FLASH Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Lock and Unlock the Option Bytes - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - (++) Set/Get the Read protection Level. - (++) Set/Get the BOR level. - (++) Get the Write protection. - (++) Get the user option bytes. - - (#) Interrupts and flags management functions : this group - includes all needed functions to: - (++) Handle FLASH interrupts - (++) Wait for last FLASH operation according to its status - (++) Get error flag status - - (#) FLASH Interface configuration functions: this group includes - the management of following features: - (++) Enable/Disable the RUN PowerDown mode. - (++) Enable/Disable the SLEEP PowerDown mode. - - (#) FLASH Peripheral State methods: this group includes - the management of following features: - (++) Wait for the FLASH operation - (++) Get the specific FLASH error flag - - [..] In addition to these function, this driver includes a set of macros allowing - to handle the following operations: - - (+) Set/Get the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the 64 bit Read Access. - (+) Enable/Disable the Flash power-down - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - - [..] The FLASH Memory Programming functions, includes the following functions: - (+) HAL_FLASH_Unlock(void); - (+) HAL_FLASH_Lock(void); - (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) - (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) - - [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page or program data. - (#) Call the HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - - ##### Option Bytes Programming functions ##### - ============================================================================== - - [..] The FLASH_Option Bytes Programming_functions, includes the following functions: - (+) HAL_FLASH_OB_Unlock(void); - (+) HAL_FLASH_OB_Lock(void); - (+) HAL_FLASH_OB_Launch(void); - (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); - (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); - - [..] Any operation of erase or program should follow these steps: - (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control - register access. - (#) Call the following functions to program the desired option bytes. - (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); - (#) Once all needed option bytes to be programmed are correctly written, call the - HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended - to protect the option Bytes against possible unwanted operations). - - [..] Proprietary code Read Out Protection (PcROP): - (#) The PcROP sector is selected by using the same option bytes as the Write - protection. As a result, these 2 options are exclusive each other. - (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below: - (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro ---------------------------- ---------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -static void FLASH_SetErrorCode(void); -extern void FLASH_PageErase(uint32_t PageAddress); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim -@endverbatim - * @{ - */ - -/** - * @brief Program word at a specified address - * @note To correctly run this function, the HAL_FLASH_Unlock() function - * must be called before. - * Call the HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation). - * - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address Specifie the address to be programmed. - * @param Data Specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /*Program word (32-bit) at a specified address.*/ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program word at a specified address with interrupt enabled. - * - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address Specifie the address to be programmed. - * @param Data Specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - pFlash.Address = Address; - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - if(TypeProgram == FLASH_TYPEPROGRAM_WORD) - { - /* Program word (32-bit) at a specified address. */ - *(__IO uint32_t *)Address = Data; - } - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t addresstmp = 0U; - - /* Check FLASH operation error flags */ - if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) || -#if defined(FLASH_SR_RDERR) - __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || -#endif /* FLASH_SR_RDERR */ -#if defined(FLASH_SR_OPTVERRUSR) - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || -#endif /* FLASH_SR_OPTVERRUSR */ - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Return the faulty sector */ - addresstmp = pFlash.Page; - pFlash.Page = 0xFFFFFFFFU; - } - else - { - /* Return the faulty address */ - addresstmp = pFlash.Address; - } - /* Save the Error code */ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(addresstmp); - - /* Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - /* Process can continue only if no error detected */ - if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /* Nb of pages to erased can be decreased */ - pFlash.NbPagesToErase--; - - /* Check if there are still pages to erase */ - if(pFlash.NbPagesToErase != 0U) - { - addresstmp = pFlash.Page; - /*Indicate user which sector has been erased */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - - /*Increment sector number*/ - addresstmp = pFlash.Page + FLASH_PAGE_SIZE; - pFlash.Page = addresstmp; - - /* If the erase operation is completed, disable the ERASE Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - FLASH_PageErase(addresstmp); - } - else - { - /* No more pages to Erase, user callback can be called. */ - /* Reset Sector and stop Erase pages procedure */ - pFlash.Page = addresstmp = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(addresstmp); - } - } - else - { - /* If the program operation is completed, disable the PROG Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Program ended. Return the selected address */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - - /* Reset Address and stop Program procedure */ - pFlash.Address = 0xFFFFFFFFU; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - } - } - - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Operation is completed, disable the PROG and ERASE */ - CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG)); - - /* Disable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Pages Erase: Address of the page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Pages Erase: Address of the page which returned an error - * - Program: Address which was selected for data program - * @retval none - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) - { - /* Unlocking FLASH_PECR register access*/ - if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) - { - WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); - WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); - - /* Verify that PELOCK is unlocked */ - if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) - { - return HAL_ERROR; - } - } - - /* Unlocking the program memory access */ - WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1); - WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2); - - /* Verify that PRGLOCK is unlocked */ - if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK)) - { - return HAL_ERROR; - } - } - - return HAL_OK; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the PRGLOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) - { - /* Unlocking FLASH_PECR register access*/ - if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) - { - /* Unlocking FLASH_PECR register access*/ - WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1); - WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2); - - /* Verify that PELOCK is unlocked */ - if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK)) - { - return HAL_ERROR; - } - } - - /* Unlocking the option bytes block access */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - - /* Verify that OPTLOCK is unlocked */ - if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK)) - { - return HAL_ERROR; - } - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the option bytes block access */ - SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @note This function will reset automatically the MCU. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OBL_Launch bit to launch the option byte loading */ - SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions - * @brief Peripheral errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode The returned value can be: - * @ref FLASH_Error_Codes - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operation timeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - uint32_t tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) - { - if (Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || -#if defined(FLASH_SR_RDERR) - __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || -#endif /* FLASH_SR_RDERR */ -#if defined(FLASH_SR_OPTVERRUSR) - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || -#endif /* FLASH_SR_OPTVERRUSR */ - __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - uint32_t flags = 0U; - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - flags |= FLASH_FLAG_WRPERR; - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - flags |= FLASH_FLAG_PGAERR; - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - flags |= FLASH_FLAG_OPTVERR; - } - -#if defined(FLASH_SR_RDERR) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - flags |= FLASH_FLAG_RDERR; - } -#endif /* FLASH_SR_RDERR */ -#if defined(FLASH_SR_OPTVERRUSR) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR; - flags |= FLASH_FLAG_OPTVERRUSR; - } -#endif /* FLASH_SR_OPTVERRUSR */ - - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(flags); -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c deleted file mode 100644 index d2284d3..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ex.c +++ /dev/null @@ -1,1873 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + FLASH Interface configuration - * + FLASH Memory Erasing - * + DATA EEPROM Programming/Erasing - * + Option Bytes Programming - * + Interrupts management - * - @verbatim - ============================================================================== - ##### Flash peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other products, the FLASH interface for STM32L1xx - devices contains the following additional features - (+) Erase functions - (+) DATA_EEPROM memory management - (+) BOOT option bit configuration - (+) PCROP protection for all sectors - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32L1xx. It includes: - (+) Full DATA_EEPROM erase and program management - (+) Boot activation - (+) PCROP protection configuration and control for all pages - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @addtogroup FLASH - * @{ - */ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variables used for Erase pages under interruption*/ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Constants FLASHEx Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -void FLASH_PageErase(uint32_t PageAddress); -static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState); -static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState); -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ - || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ - || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) -static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState); -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ - || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ - || defined(STM32L162xE) -static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState); -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ - || defined(STM32L152xDX) || defined(STM32L162xDX) -static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState); -#endif /* STM32L151xE || STM32L152xE || STM32L151xDX || ... */ -#if defined(FLASH_OBR_SPRMOD) -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState); -#endif /* FLASH_OBR_SPRMOD */ -#if defined(FLASH_OBR_nRST_BFB2) -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT); -#endif /* FLASH_OBR_nRST_BFB2 */ -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); -static uint8_t FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetUser(void); -static uint8_t FLASH_OB_GetBOR(void); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 FLASHEx Memory Erasing functions - * @brief FLASH Memory Erasing functions - * -@verbatim - ============================================================================== - ##### FLASH Erasing Programming functions ##### - ============================================================================== - - [..] The FLASH Memory Erasing functions, includes the following functions: - (+) @ref HAL_FLASHEx_Erase: return only when erase has been done - (+) @ref HAL_FLASHEx_Erase_IT: end of erase is done when @ref HAL_FLASH_EndOfOperationCallback - is called with parameter 0xFFFFFFFF - - [..] Any operation of erase should follow these steps: - (#) Call the @ref HAL_FLASH_Unlock() function to enable the flash control register and - program memory access. - (#) Call the desired function to erase page. - (#) Call the @ref HAL_FLASH_Lock() to disable the flash program memory access - (recommended to protect the FLASH memory against possible unwanted operation). - -@endverbatim - * @{ - */ - -/** - * @brief Erase the specified FLASH memory Pages - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between - * 2 banks, user should perform pages erase by bank only. - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError pointer to variable that - * contains the configuration information on faulty page in case of error - * (0xFFFFFFFF means that all the pages have been correctly erased) - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t address = 0U; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFU; - - /* Check the parameters */ - assert_param(IS_NBPAGES(pEraseInit->NbPages)); - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U)); - -#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX) - /* Check on which bank belongs the 1st address to erase */ - if (pEraseInit->PageAddress < FLASH_BANK2_BASE) - { - /* BANK1 */ - /* Check that last page to erase still belongs to BANK1 */ - if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END) - { - /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not - continuous */ - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return HAL_ERROR; - } - } - else - { - /* BANK2 */ - /* Check that last page to erase still belongs to BANK2 */ - if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END) - { - /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not - continuous */ - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return HAL_ERROR; - } - } -#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */ - - /* Erase page by page to be done*/ - for(address = pEraseInit->PageAddress; - address < ((pEraseInit->NbPages * FLASH_PAGE_SIZE) + pEraseInit->PageAddress); - address += FLASH_PAGE_SIZE) - { - FLASH_PageErase(address); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the ERASE Bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty address */ - *PageError = address; - break; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * End of erase is done when @ref HAL_FLASH_EndOfOperationCallback is called with parameter - * 0xFFFFFFFF - * @note For STM32L151xDX/STM32L152xDX/STM32L162xDX, as memory is not continuous between - * 2 banks, user should perform pages erase by bank only. - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* If procedure already ongoing, reject the next one */ - if (pFlash.ProcedureOnGoing != FLASH_PROC_NONE) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_NBPAGES(pEraseInit->NbPages)); - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); - assert_param(IS_FLASH_PROGRAM_ADDRESS((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - -#if defined(STM32L151xDX) || defined(STM32L152xDX) || defined(STM32L162xDX) - /* Check on which bank belongs the 1st address to erase */ - if (pEraseInit->PageAddress < FLASH_BANK2_BASE) - { - /* BANK1 */ - /* Check that last page to erase still belongs to BANK1 */ - if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK1_END) - { - /* Last page does not belong to BANK1, erase procedure cannot be performed because memory is not - continuous */ - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return HAL_ERROR; - } - } - else - { - /* BANK2 */ - /* Check that last page to erase still belongs to BANK2 */ - if (((pEraseInit->PageAddress & ~(FLASH_PAGE_SIZE - 1U)) + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1U) > FLASH_BANK2_END) - { - /* Last page does not belong to BANK2, erase procedure cannot be performed because memory is not - continuous */ - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return HAL_ERROR; - } - } -#endif /* STM32L151xDX || STM32L152xDX || STM32L162xDX */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Enable End of FLASH Operation and Error source interrupts */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR); - - pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - pFlash.NbPagesToErase = pEraseInit->NbPages; - pFlash.Page = pEraseInit->PageAddress; - - /*Erase 1st page and wait for IT*/ - FLASH_PageErase(pEraseInit->PageAddress); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } - - return status; -} - -/** - * @} - */ - -/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - ============================================================================== - ##### Option Bytes Programming functions ##### - ============================================================================== - - [..] Any operation of erase or program should follow these steps: - (#) Call the @ref HAL_FLASH_OB_Unlock() function to enable the Flash option control - register access. - (#) Call following function to program the desired option bytes. - (++) @ref HAL_FLASHEx_OBProgram: - - To Enable/Disable the desired sector write protection. - - To set the desired read Protection Level. - - To configure the user option Bytes: IWDG, STOP and the Standby. - - To Set the BOR level. - (#) Once all needed option bytes to be programmed are correctly written, call the - @ref HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. - (#) Call the @ref HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended - to protect the option Bytes against possible unwanted operations). - - [..] Proprietary code Read Out Protection (PcROP): - (#) The PcROP sector is selected by using the same option bytes as the Write - protection (nWRPi bits). As a result, these 2 options are exclusive each other. - (#) In order to activate the PcROP (change the function of the nWRPi option bits), - the SPRMOD option bit must be activated. - (#) The active value of nWRPi bits is inverted when PCROP mode is active, this - means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" - is read/write protected. - (#) To activate PCROP mode for Flash sector(s), you need to call the following function: - (++) @ref HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected - (++) @ref HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection - (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices. - -@endverbatim - * @{ - */ - -/** - * @brief Program option bytes - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /*Write protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /* Enable of Write protection on the selected Sector*/ - status = FLASH_OB_WRPConfig(pOBInit, ENABLE); - } - else - { - /* Disable of Write protection on the selected Sector*/ - status = FLASH_OB_WRPConfig(pOBInit, DISABLE); - } - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* Read protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* USER configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NORST, - pOBInit->USERConfig & OB_STDBY_NORST); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - - /* BOR Level configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) - { - status = FLASH_OB_BORConfig(pOBInit->BORLevel); - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; - } - } - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; - - /*Get WRP1*/ - pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1); - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ - || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ - || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) - - /*Get WRP2*/ - pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2); - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ - || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ - || defined(STM32L162xE) - - /*Get WRP3*/ - pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3); - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ - || defined(STM32L152xDX) || defined(STM32L162xDX) - - /*Get WRP4*/ - pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4); - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); - - /*Get BOR Level*/ - pOBInit->BORLevel = FLASH_OB_GetBOR(); -} - -#if defined(FLASH_OBR_SPRMOD) || defined(FLASH_OBR_nRST_BFB2) - -/** - * @brief Program option bytes - * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. - * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_OBEX(pAdvOBInit->OptionType)); - -#if defined(FLASH_OBR_SPRMOD) - - /* Program PCROP option byte*/ - if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) - { - /* Check the parameters */ - assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if (pAdvOBInit->PCROPState == OB_PCROP_STATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE); - if (status != HAL_OK) - { - return status; - } - } - else - { - /* Disable of Write protection on the selected Sector*/ - status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE); - if (status != HAL_OK) - { - return status; - } - } - } - -#endif /* FLASH_OBR_SPRMOD */ - -#if defined(FLASH_OBR_nRST_BFB2) - - /* Program BOOT config option byte */ - if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) - { - status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); - } - -#endif /* FLASH_OBR_nRST_BFB2 */ - - return status; -} - -/** - * @brief Get the OBEX byte configuration - * @note This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2. - * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) -{ - pAdvOBInit->OptionType = 0U; - -#if defined(FLASH_OBR_SPRMOD) - - pAdvOBInit->OptionType |= OPTIONBYTE_PCROP; - - /*Get PCROP state */ - pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD); - - /*Get PCROP protected sector from 0 to 31 */ - pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1; - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) - - /*Get PCROP protected sector from 32 to 63 */ - pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2; - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ -#endif /* FLASH_OBR_SPRMOD */ - -#if defined(FLASH_OBR_nRST_BFB2) - - pAdvOBInit->OptionType |= OPTIONBYTE_BOOTCONFIG; - - /* Get Boot config OB */ - pAdvOBInit->BootConfig = (FLASH->OBR & FLASH_OBR_nRST_BFB2) >> 16U; - -#endif /* FLASH_OBR_nRST_BFB2 */ -} - -#endif /* FLASH_OBR_SPRMOD || FLASH_OBR_nRST_BFB2 */ - -#if defined(FLASH_OBR_SPRMOD) - -/** - * @brief Select the Protection Mode (SPRMOD). - * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @retval HAL status - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0U; - uint32_t tmp2 = 0U; - uint8_t optiontmp = 0U; - uint16_t optiontmp2 = 0U; - - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* program PCRop */ - OB->RDP = tmp2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the Read protection operation Status */ - return status; -} - -/** - * @brief Deselect the Protection Mode (SPRMOD). - * @note This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @retval HAL status - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0U; - uint32_t tmp2 = 0U; - uint8_t optiontmp = 0U; - uint16_t optiontmp2 = 0U; - - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)optiontmp2)); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* program PCRop */ - OB->RDP = tmp2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the Read protection operation Status */ - return status; -} - -#endif /* FLASH_OBR_SPRMOD */ - -/** - * @} - */ - -/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions - * @brief DATA EEPROM Programming functions - * -@verbatim - =============================================================================== - ##### DATA EEPROM Programming functions ##### - =============================================================================== - - [..] Any operation of erase or program should follow these steps: - (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access - and Flash program erase control register access. - (#) Call the desired function to erase or program data. - (#) Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access - and Flash program erase control register access(recommended - to protect the DATA_EEPROM against possible unwanted operation). - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the data memory and FLASH_PECR register access. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) -{ - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) - { - /* Unlocking the Data memory and FLASH_PECR register access*/ - FLASH->PEKEYR = FLASH_PEKEY1; - FLASH->PEKEYR = FLASH_PEKEY2; - } - else - { - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Locks the Data memory and FLASH_PECR register access. - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) -{ - /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ - SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); - - return HAL_OK; -} - -/** - * @brief Erase a word in data memory. - * @param Address specifies the address to be erased. - * @param TypeErase Indicate the way to erase at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the @ref HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TYPEERASEDATA(TypeErase)); - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - if(TypeErase == FLASH_TYPEERASEDATA_WORD) - { - /* Write 00000000h to valid address in the data memory */ - *(__IO uint32_t *) Address = 0x00000000U; - } - - if(TypeErase == FLASH_TYPEERASEDATA_HALFWORD) - { - /* Write 0000h to valid address in the data memory */ - *(__IO uint16_t *) Address = (uint16_t)0x0000; - } - - if(TypeErase == FLASH_TYPEERASEDATA_BYTE) - { - /* Write 00h to valid address in the data memory */ - *(__IO uint8_t *) Address = (uint8_t)0x00; - } - - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Program word at a specified address - * @note To correctly run this function, the @ref HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the @ref HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @note The function @ref HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before - * this function to configure the Fixed Time Programming. - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASHEx_Type_Program_Data - * @param Address specifie the address to be programmed. - * @param Data specifie the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ - -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD) - { - /* Program word (32-bit) at a specified address.*/ - status = FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD) - { - /* Program halfword (16-bit) at a specified address.*/ - status = FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE) - { - /* Program byte (8-bit) at a specified address.*/ - status = FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTBYTE) - { - /*Program word (8-bit) at a specified address.*/ - status = FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTHALFWORD) - { - /* Program halfword (16-bit) at a specified address.*/ - status = FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); - } - else if(TypeProgram == FLASH_TYPEPROGRAMDATA_FASTWORD) - { - /* Program word (32-bit) at a specified address.*/ - status = FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); - } - else - { - status = HAL_ERROR; - } - - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Enable DATA EEPROM fixed Time programming (2*Tprog). - * @retval None - */ -void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void) -{ - SET_BIT(FLASH->PECR, FLASH_PECR_FTDW); -} - -/** - * @brief Disables DATA EEPROM fixed Time programming (2*Tprog). - * @retval None - */ -void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) -{ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ - -/* -============================================================================== - OPTIONS BYTES -============================================================================== -*/ -/** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the @ref HAL_FLASH_OB_Unlock() function - * must be called before. - * @param OB_RDP specifies the read protection level. - * This parameter can be: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @arg @ref OB_RDP_LEVEL_2 Chip protection - * - * !!!Warning!!! When enabling OB_RDP_LEVEL_2 it's no more possible to go back to level 1 or 0 - * - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - tmp1 = (uint32_t)(OB->RDP & FLASH_OBR_RDPRT); - - /* According to errata sheet, DocID022054 Rev 5, par2.1.5 - Before setting Level0 in the RDP register, check that the current level is not equal to Level0. - If the current level is not equal to Level0, Level0 can be activated. - If the current level is Level0 then the RDP register must not be written again with Level0. */ - - if ((tmp1 == OB_RDP_LEVEL_0) && (OB_RDP == OB_RDP_LEVEL_0)) - { - /*current level is Level0 then the RDP register must not be written again with Level0. */ - status = HAL_ERROR; - } - else - { -#if defined(FLASH_OBR_SPRMOD) - /* Mask SPRMOD bit */ - tmp3 = (uint32_t)(OB->RDP & FLASH_OBR_SPRMOD); -#endif - - /* calculate the option byte to write */ - tmp1 = (~((uint32_t)(OB_RDP | tmp3))); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16U)) | ((uint32_t)(OB_RDP | tmp3))); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* program read protection level */ - OB->RDP = tmp2; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - } - - /* Return the Read protection operation Status */ - return status; -} - -/** - * @brief Programs the FLASH brownout reset threshold level Option Byte. - * @param OB_BOR Selects the brownout reset threshold level. - * This parameter can be one of the following values: - * @arg @ref OB_BOR_OFF BOR is disabled at power down, the reset is asserted when the VDD - * power supply reaches the PDR(Power Down Reset) threshold (1.5V) - * @arg @ref OB_BOR_LEVEL1 BOR Reset threshold levels for 1.7V - 1.8V VDD power supply - * @arg @ref OB_BOR_LEVEL2 BOR Reset threshold levels for 1.9V - 2.0V VDD power supply - * @arg @ref OB_BOR_LEVEL3 BOR Reset threshold levels for 2.3V - 2.4V VDD power supply - * @arg @ref OB_BOR_LEVEL4 BOR Reset threshold levels for 2.55V - 2.65V VDD power supply - * @arg @ref OB_BOR_LEVEL5 BOR Reset threshold levels for 2.8V - 2.9V VDD power supply - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0U, tmp1 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_BOR_LEVEL(OB_BOR)); - - /* Get the User Option byte register */ - tmp1 = OB->USER & ((~FLASH_OBR_BOR_LEV) >> 16U); - - /* Calculate the option byte to write - [0xFFU | nUSER | 0x00U | USER]*/ - tmp = (uint32_t)~((OB_BOR | tmp1)) << 16U; - tmp |= (OB_BOR | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Write the BOR Option Byte */ - OB->USER = tmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the Option Byte BOR Programming Status */ - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @retval The FLASH User Option Bytes. - */ -static uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)((FLASH->OBR & (FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FLASH RDP level - * This parameter can be one of the following values: - * @arg @ref OB_RDP_LEVEL_0 No protection - * @arg @ref OB_RDP_LEVEL_1 Read protection of the memory - * @arg @ref OB_RDP_LEVEL_2 Full chip protection - */ -static uint8_t FLASH_OB_GetRDP(void) -{ - uint8_t rdp_level = (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT); - - if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_2)) - { - return (OB_RDP_LEVEL_1); - } - else - { - return (rdp_level); - } -} - -/** - * @brief Returns the FLASH BOR level. - * @retval The BOR level Option Bytes. - */ -static uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the BOR level */ - return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> 16U); -} - -/** - * @brief Write protects the desired pages of the first 64KB of the Flash. - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains WRP parameters. - * @param NewState new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval HAL_StatusTypeDef - */ -static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* WRP for sector between 0 to 31 */ - if (pOBInit->WRPSector0To31 != 0U) - { - FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState); - } - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ - || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ - || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) - - /* Pages for Cat3, Cat4 & Cat5 devices*/ - /* WRP for sector between 32 to 63 */ - if (pOBInit->WRPSector32To63 != 0U) - { - FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState); - } - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ - || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ - || defined(STM32L162xE) - - /* Pages for devices with FLASH >= 256KB*/ - /* WRP for sector between 64 to 95 */ - if (pOBInit->WRPSector64To95 != 0U) - { - FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState); - } - -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ - || defined(STM32L152xDX) || defined(STM32L162xDX) - - /* Pages for Cat5 devices*/ - /* WRP for sector between 96 to 127 */ - if (pOBInit->WRPSector96To127 != 0U) - { - FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState); - } - -#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the write protection operation Status */ - return status; -} - -#if defined(STM32L151xBA) || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC) \ - || defined(STM32L162xC) -/** - * @brief Enables the read/write protection (PCROP) of the desired - * sectors. - * @note This function can be used only for Cat2 & Cat3 devices - * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that - * contains PCROP parameters. - * @param NewState new state of the specified FLASH Pages read/Write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState) -{ - HAL_StatusTypeDef status = HAL_OK; - FunctionalState pcropstate = DISABLE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* Invert state to use same function of WRP */ - if (NewState == DISABLE) - { - pcropstate = ENABLE; - } - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Pages for Cat2 devices*/ - /* PCROP for sector between 0 to 31 */ - if (pAdvOBInit->PCROPSector0To31 != 0U) - { - FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate); - } - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) - - /* Pages for Cat3 devices*/ - /* WRP for sector between 32 to 63 */ - if (pAdvOBInit->PCROPSector32To63 != 0U) - { - FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate); - } - -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the write protection operation Status */ - return status; -} -#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */ - -/** - * @brief Write protects the desired pages of the first 128KB of the Flash. - * @param WRP1OrPCROP1 specifies the address of the pages to be write protected. - * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 - * @param NewState new state of the specified FLASH Pages Write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState) -{ - uint32_t wrp01data = 0U, wrp23data = 0U; - - uint32_t tmp1 = 0U, tmp2 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_WRP(WRP1OrPCROP1)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01)); - wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U | OB->WRP23))); - tmp1 = (uint32_t)(~(wrp01data) << 16U)|(wrp01data); - OB->WRP01 = tmp1; - - tmp2 = (uint32_t)(~(wrp23data) << 16U)|(wrp23data); - OB->WRP23 = tmp2; - } - else - { - wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01)); - wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16U & OB->WRP23))); - - tmp1 = (uint32_t)((~wrp01data) << 16U)|(wrp01data); - OB->WRP01 = tmp1; - - tmp2 = (uint32_t)((~wrp23data) << 16U)|(wrp23data); - OB->WRP23 = tmp2; - } -} - -#if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC) \ - || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xCA) \ - || defined(STM32L152xD) || defined(STM32L152xDX) || defined(STM32L162xCA) || defined(STM32L162xD) \ - || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) -/** - * @brief Enable Write protects the desired pages of the second 128KB of the Flash. - * @note This function can be used only for Cat3, Cat4 & Cat5 devices. - * @param WRP2OrPCROP2 specifies the address of the pages to be write protected. - * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 - * @param NewState new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState) -{ - uint32_t wrp45data = 0U, wrp67data = 0U; - - uint32_t tmp1 = 0U, tmp2 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_WRP(WRP2OrPCROP2)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45)); - wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U | OB->WRP67))); - tmp1 = (uint32_t)(~(wrp45data) << 16U)|(wrp45data); - OB->WRP45 = tmp1; - - tmp2 = (uint32_t)(~(wrp67data) << 16U)|(wrp67data); - OB->WRP67 = tmp2; - } - else - { - wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45)); - wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16U & OB->WRP67))); - - tmp1 = (uint32_t)((~wrp45data) << 16U)|(wrp45data); - OB->WRP45 = tmp1; - - tmp2 = (uint32_t)((~wrp67data) << 16U)|(wrp67data); - OB->WRP67 = tmp2; - } -} -#endif /* STM32L100xC || STM32L151xC || STM32L152xC || (...) || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xD) || defined(STM32L151xDX) || defined(STM32L152xD) || defined(STM32L152xDX) \ - || defined(STM32L162xD) || defined(STM32L162xDX) || defined(STM32L151xE) || defined(STM32L152xE) \ - || defined(STM32L162xE) -/** - * @brief Enable Write protects the desired pages of the third 128KB of the Flash. - * @note This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD & Cat5 devices. - * @param WRP3 specifies the address of the pages to be write protected. - * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 - * @param NewState new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState) -{ - uint32_t wrp89data = 0U, wrp1011data = 0U; - - uint32_t tmp1 = 0U, tmp2 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_WRP(WRP3)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89)); - wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16U | OB->WRP1011))); - tmp1 = (uint32_t)(~(wrp89data) << 16U)|(wrp89data); - OB->WRP89 = tmp1; - - tmp2 = (uint32_t)(~(wrp1011data) << 16U)|(wrp1011data); - OB->WRP1011 = tmp2; - } - else - { - wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89)); - wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16U & OB->WRP1011))); - - tmp1 = (uint32_t)((~wrp89data) << 16U)|(wrp89data); - OB->WRP89 = tmp1; - - tmp2 = (uint32_t)((~wrp1011data) << 16U)|(wrp1011data); - OB->WRP1011 = tmp2; - } -} -#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */ - -#if defined(STM32L151xE) || defined(STM32L152xE) || defined(STM32L162xE) || defined(STM32L151xDX) \ - || defined(STM32L152xDX) || defined(STM32L162xDX) -/** - * @brief Enable Write protects the desired pages of the Fourth 128KB of the Flash. - * @note This function can be used only for Cat5 & STM32L1xxDX devices. - * @param WRP4 specifies the address of the pages to be write protected. - * This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 - * @param NewState new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState) -{ - uint32_t wrp1213data = 0U, wrp1415data = 0U; - - uint32_t tmp1 = 0U, tmp2 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_WRP(WRP4)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213)); - wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16U | OB->WRP1415))); - tmp1 = (uint32_t)(~(wrp1213data) << 16U)|(wrp1213data); - OB->WRP1213 = tmp1; - - tmp2 = (uint32_t)(~(wrp1415data) << 16U)|(wrp1415data); - OB->WRP1415 = tmp2; - } - else - { - wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213)); - wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16U & OB->WRP1415))); - - tmp1 = (uint32_t)((~wrp1213data) << 16U)|(wrp1213data); - OB->WRP1213 = tmp1; - - tmp2 = (uint32_t)((~wrp1415data) << 16U)|(wrp1415data); - OB->WRP1415 = tmp2; - } -} -#endif /* STM32L151xE || STM32L152xE || STM32L162xE || STM32L151xDX || ... */ - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG Selects the WDG mode. - * This parameter can be one of the following values: - * @arg @ref OB_IWDG_SW Software WDG selected - * @arg @ref OB_IWDG_HW Hardware WDG selected - * @param OB_STOP Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg @ref OB_STOP_NORST No reset generated when entering in STOP - * @arg @ref OB_STOP_RST Reset generated when entering in STOP - * @param OB_STDBY Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg @ref OB_STDBY_NORST No reset generated when entering in STANDBY - * @arg @ref OB_STDBY_RST Reset generated when entering in STANDBY - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0U, tmp1 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Get the User Option byte register */ - tmp1 = OB->USER & ((~(FLASH_OBR_IWDG_SW | FLASH_OBR_nRST_STOP | FLASH_OBR_nRST_STDBY)) >> 16U); - - /* Calculate the user option byte to write */ - tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16U); - tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Write the User Option Byte */ - OB->USER = tmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the Option Byte program Status */ - return status; -} - -#if defined(FLASH_OBR_nRST_BFB2) -/** - * @brief Configures to boot from Bank1 or Bank2. - * @param OB_BOOT select the FLASH Bank to boot from. - * This parameter can be one of the following values: - * @arg @ref OB_BOOT_BANK2 At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank2 or Bank1, - * depending on the activation of the bank. The active banks are checked in - * the following order: Bank2, followed by Bank1. - * The active bank is recognized by the value programmed at the base address - * of the respective bank (corresponding to the initial stack pointer value - * in the interrupt vector table). - * @arg @ref OB_BOOT_BANK1 At startup, if boot pins are set in boot from user Flash - * position and this parameter is selected the device will boot from Bank1(Default). - * For more information, please refer to AN2606 from www.st.com. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0U, tmp1 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_BOOT_BANK(OB_BOOT)); - - /* Get the User Option byte register and BOR Level*/ - tmp1 = OB->USER & ((~FLASH_OBR_nRST_BFB2) >> 16U); - - /* Calculate the option byte to write */ - tmp = (uint32_t)~(OB_BOOT | tmp1) << 16U; - tmp |= (OB_BOOT | tmp1); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Write the BOOT Option Byte */ - OB->USER = tmp; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Return the Option Byte program Status */ - return status; -} - -#endif /* FLASH_OBR_nRST_BFB2 */ - -/* -============================================================================== - DATA -============================================================================== -*/ - -/** - * @brief Write a Byte at a specified address in data memory. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - uint32_t tmp = 0U, tmpaddr = 0U; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); - -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - /* Possible only on Cat1 devices */ - if(Data != (uint8_t)0x00U) - { - /* If the previous operation is completed, proceed to write the new Data */ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - else - { - tmpaddr = Address & 0xFFFFFFFCU; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); - /* Process Locked */ - __HAL_LOCK(&pFlash); - } -#else /*!Cat1*/ - /* If the previous operation is completed, proceed to write the new Data */ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Writes a half word at a specified address in data memory. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - uint32_t tmp = 0U, tmpaddr = 0U; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); - -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - /* Possible only on Cat1 devices */ - if(Data != (uint16_t)0x0000U) - { - /* If the previous operation is completed, proceed to write the new data */ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - if((Address & 0x3U) != 0x3U) - { - tmpaddr = Address & 0xFFFFFFFCU; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); - status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); - } - else - { - HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U); - HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U); - } - /* Process Locked */ - __HAL_LOCK(&pFlash); - } -#else /* !Cat1 */ - /* If the previous operation is completed, proceed to write the new data */ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW); - - /* If the previous operation is completed, proceed to program the new data */ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Write a Byte at a specified address in data memory without erase. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - uint32_t tmp = 0U, tmpaddr = 0U; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - if(Data != (uint8_t) 0x00U) - { - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - } - else - { - tmpaddr = Address & 0xFFFFFFFCU; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFU << ((uint32_t) (0x8U * (Address & 0x3U))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); - /* Process Locked */ - __HAL_LOCK(&pFlash); - } -#else /* Not Cat1*/ - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Writes a half word at a specified address in data memory without erase. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - uint32_t tmp = 0U, tmpaddr = 0U; -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { -#if defined(STM32L100xB) || defined(STM32L151xB) || defined(STM32L152xB) - if(Data != (uint16_t)0x0000U) - { - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - if((Address & 0x3U) != 0x3U) - { - tmpaddr = Address & 0xFFFFFFFCU; - tmp = * (__IO uint32_t *) tmpaddr; - tmpaddr = 0xFFFFU << ((uint32_t) (0x8U * (Address & 0x3U))); - tmp &= ~tmpaddr; - status = HAL_FLASHEx_DATAEEPROM_Erase(FLASH_TYPEERASEDATA_WORD, Address & 0xFFFFFFFCU); - status = HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFCU), tmp); - } - else - { - HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address, 0x00U); - HAL_FLASHEx_DATAEEPROM_Program(FLASH_TYPEPROGRAMDATA_FASTBYTE, Address + 1U, 0x00U); - } - /* Process Locked */ - __HAL_LOCK(&pFlash); - } -#else /* Not Cat1*/ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); -#endif /* STM32L100xB || STM32L151xB || STM32L152xB */ - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory without erase. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @retval HAL status - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH - * @{ - */ - - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Erases a specified page in program memory. - * @param PageAddress The page address in program memory to be erased. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). - * @retval None - */ -void FLASH_PageErase(uint32_t PageAddress) -{ - /* Clean the error context */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Set the ERASE bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - /* Set PROG bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Write 00000000h to the first word of the program page to erase */ - *(__IO uint32_t *)(uint32_t)(PageAddress & ~(FLASH_PAGE_SIZE - 1)) = 0x00000000; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c deleted file mode 100644 index 5b0bf98..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_flash_ramfunc.c +++ /dev/null @@ -1,644 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_flash_ramfunc.c - * @author MCD Application Team - * @brief FLASH RAMFUNC driver. - * This file provides a Flash firmware functions which should be - * executed from internal SRAM - * - * @verbatim - - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are be executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - -@endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/** @addtogroup FLASH - * @{ - */ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC - * @brief FLASH functions executed from RAM - * @{ - */ - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions - * @{ - */ - -static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout); -static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void); - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions - * -@verbatim - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM - transfers. - -@endverbatim - * @{ - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions - * @{ - */ - -/** - * @brief Enable the power down mode during RUN mode. - * @note This function can be used only when the user code is running from Internal SRAM. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void) -{ - /* Enable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_ENABLE(); - - return HAL_OK; -} - -/** - * @brief Disable the power down mode during RUN mode. - * @note This function can be used only when the user code is running from Internal SRAM. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void) -{ - /* Disable the Power Down in Run mode*/ - __HAL_FLASH_POWER_DOWN_DISABLE(); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions - * -@verbatim -@endverbatim - * @{ - */ - -#if defined(FLASH_PECR_PARALLBANK) -/** - * @brief Erases a specified 2 pages in program memory in parallel. - * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. - * To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation). - * @param Page_Address1: The page address in program memory to be erased in - * the first Bank (BANK1). This parameter should be between FLASH_BASE - * and FLASH_BANK1_END. - * @param Page_Address2: The page address in program memory to be erased in - * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE - * and FLASH_BANK2_END. - * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Proceed to erase the page */ - SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); - SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); - SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Write 00000000h to the first word of the first program page to erase */ - *(__IO uint32_t *)Page_Address1 = 0x00000000U; - /* Write 00000000h to the first word of the second program page to erase */ - *(__IO uint32_t *)Page_Address2 = 0x00000000U; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Program 2 half pages in program memory in parallel (half page size is 32 Words). - * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. - * @param Address1: specifies the first address to be written in the first bank - * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). - * @param pBuffer1: pointer to the buffer containing the data to be written - * to the first half page in the first bank. - * @param Address2: specifies the second address to be written in the second bank - * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). - * @param pBuffer2: pointer to the buffer containing the data to be written - * to the second half page in the second bank. - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation). - * @note Half page write is possible only from SRAM. - * @note If there are more than 32 words to write, after 32 words another - * Half Page programming operation starts and has to be finished. - * @note A half page is written to the program memory only if the first - * address to load is the start address of a half page (multiple of 128 - * bytes) and the 31 remaining words to load are in the same half page. - * @note During the Program memory half page write all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @note If a PGAERR is set during a Program memory half page write, the - * complete write operation is aborted. Software should then reset the - * FPRG and PROG/DATA bits and restart the write operation from the - * beginning. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) -{ - uint32_t primask_bit; - uint32_t count = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Disable all IRQs */ - primask_bit = __get_PRIMASK(); - __disable_irq(); - - /* Proceed to program the new half page */ - SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); - SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); - SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Write the first half page directly with 32 different words */ - while(count < 32U) - { - *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1; - pBuffer1++; - count ++; - } - - /* Write the second half page directly with 32 different words */ - count = 0U; - while(count < 32U) - { - *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2; - pBuffer2++; - count ++; - } - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); - - /* Enable IRQs */ - __set_PRIMASK(primask_bit); - } - - /* Return the Write Status */ - return status; -} -#endif /* FLASH_PECR_PARALLBANK */ - -/** - * @brief Program a half page in program memory. - * @param Address specifies the address to be written. - * @param pBuffer pointer to the buffer containing the data to be written to - * the half page. - * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function - * must be called before. - * Call the @ref HAL_FLASH_Lock() to disable the flash memory access - * (recommended to protect the FLASH memory against possible unwanted operation) - * @note Half page write is possible only from SRAM. - * @note If there are more than 32 words to write, after 32 words another - * Half Page programming operation starts and has to be finished. - * @note A half page is written to the program memory only if the first - * address to load is the start address of a half page (multiple of 128 - * bytes) and the 31 remaining words to load are in the same half page. - * @note During the Program memory half page write all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @note If a PGAERR is set during a Program memory half page write, the - * complete write operation is aborted. Software should then reset the - * FPRG and PROG/DATA bits and restart the write operation from the - * beginning. - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) -{ - uint32_t primask_bit; - uint32_t count = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Disable all IRQs */ - primask_bit = __get_PRIMASK(); - __disable_irq(); - - /* Proceed to program the new half page */ - SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); - SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - - /* Write one half page directly with 32 different words */ - while(count < 32U) - { - *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer; - pBuffer++; - count ++; - } - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the write operation is completed, disable the PROG and FPRG bits */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); - - /* Enable IRQs */ - __set_PRIMASK(primask_bit); - } - - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions - * @brief Peripheral errors functions - * -@verbatim - =============================================================================== - ##### Peripheral errors functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH errors flag. - * @param Error pointer is the error value. It can be a mixed of: -@if STM32L100xB -@elif STM32L100xBA - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) -@elif STM32L151xB -@elif STM32L151xBA - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) -@elif STM32L152xB -@elif STM32L152xBA - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) -@elif STM32L100xC - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) - * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error -@elif STM32L151xC - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) - * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error -@elif STM32L152xC - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) - * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error -@elif STM32L162xC - * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) - * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error -@else - * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error -@endif - * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag - * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag - * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag - * @retval HAL Status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error) -{ - *Error = pFlash.ErrorCode; - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions - * - * @{ - */ - -/** - * @brief Erase a double word in data memory. - * @param Address specifies the address to be erased. - * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @note Data memory double word erase is possible only from SRAM. - * @note A double word is erased to the data memory only if the first address - * to load is the start address of a double word (multiple of 8 bytes). - * @note During the Data memory double word erase, all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @retval HAL status - */ - -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) -{ - uint32_t primask_bit; - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Disable all IRQs */ - primask_bit = __get_PRIMASK(); - __disable_irq(); - - /* If the previous operation is completed, proceed to erase the next double word */ - /* Set the ERASE bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); - - /* Set DATA bit */ - SET_BIT(FLASH->PECR, FLASH_PECR_DATA); - - /* Write 00000000h to the 2 words to erase */ - *(__IO uint32_t *)Address = 0x00000000U; - Address += 4U; - *(__IO uint32_t *)Address = 0x00000000U; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the ERASE and DATA bits */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); - - /* Enable IRQs */ - __set_PRIMASK(primask_bit); - - } - - /* Return the erase status */ - return status; -} - -/** - * @brief Write a double word in data memory without erase. - * @param Address specifies the address to be written. - * @param Data specifies the data to be written. - * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @note Data memory double word write is possible only from SRAM. - * @note A data memory double word is written to the data memory only if the - * first address to load is the start address of a double word (multiple - * of double word). - * @note During the Data memory double word write, all read operations are - * forbidden (this includes DMA read operations and debugger read - * operations such as breakpoints, periodic updates, etc.). - * @retval HAL status - */ -__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - uint32_t primask_bit; - HAL_StatusTypeDef status = HAL_OK; - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Disable all IRQs */ - primask_bit = __get_PRIMASK(); - __disable_irq(); - - /* If the previous operation is completed, proceed to program the new data*/ - SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); - SET_BIT(FLASH->PECR, FLASH_PECR_DATA); - - /* Write the 2 words */ - *(__IO uint32_t *)Address = (uint32_t) Data; - Address += 4U; - *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); - - /* Wait for last operation to be completed */ - status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the write operation is completed, disable the FPRG and DATA bits */ - CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); - CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); - - /* Enable IRQs */ - __set_PRIMASK(primask_bit); - } - - /* Return the Write Status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup FLASH_RAMFUNC_Private_Functions - * @{ - */ - -/** - * @brief Set the specific FLASH error flag. - * @retval HAL Status - */ -static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void) -{ - uint32_t flags = 0U; - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - flags |= FLASH_FLAG_WRPERR; - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - flags |= FLASH_FLAG_PGAERR; - } - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; - flags |= FLASH_FLAG_OPTVERR; - } - -#if defined(FLASH_SR_RDERR) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - flags |= FLASH_FLAG_RDERR; - } -#endif /* FLASH_SR_RDERR */ -#if defined(FLASH_SR_OPTVERRUSR) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR)) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR; - flags |= FLASH_FLAG_OPTVERRUSR; - } -#endif /* FLASH_SR_OPTVERRUSR */ - - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(flags); - - return HAL_OK; -} - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operationtimeout - * @retval HAL status - */ -static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) - { - Timeout--; - } - - if(Timeout == 0x00U) - { - return HAL_TIMEOUT; - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || -#if defined(FLASH_SR_RDERR) - __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || -#endif /* FLASH_SR_RDERR */ -#if defined(FLASH_SR_OPTVERRUSR) - __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || -#endif /* FLASH_SR_OPTVERRUSR */ - __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) - { - /*Save the error code*/ - FLASHRAM_SetErrorCode(); - return HAL_ERROR; - } - - /* There is no error flag set */ - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c deleted file mode 100644 index 8342fa9..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_gpio.c +++ /dev/null @@ -1,550 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (+) Input mode - (+) Analog mode - (+) Output mode - (+) Alternate function mode - (+) External interrupt/event lines - - [..] - During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - [..] - In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - [..] - The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral s alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] - The external interrupt/event controller consists of up to 28 edge detectors - (depending on products 16 lines are connected to GPIO) for generating event/interrupt - requests (each input line can be independently configured to select the type - (interrupt or event) and the corresponding trigger event (rising or falling or both). - Each line can also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure, - the speed is configurable: Low, Medium and High. - (++) If alternate mode is selected, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also - recommended to use it to unconfigure pin which was used as an external interrupt - or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG - registers. - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Constants - * @{ - */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) - -#define GPIO_NUMBER (16U) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @addtogroup GPIO_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Configure the port pins */ - while (((GPIO_Init->Pin) >> position) != 0) - { - /* Get current io position */ - iocurrent = (GPIO_Init->Pin) & (1U << position); - - if (iocurrent) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Output or Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || - (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - SET_BIT(temp, GPIO_Init->Speed << (position * 2)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ; - SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); - GPIOx->OTYPER = temp; - } - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2)); - SET_BIT(temp, (GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; - - /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Alternate function parameters */ - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - /* Identify AFRL or AFRH register based on IO position*/ - temp = GPIOx->AFR[position >> 3]; - CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4)); - SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2)); - SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03))); - SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - SET_BIT(temp, iocurrent); - } - EXTI->IMR = temp; - - temp = EXTI->EMR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - SET_BIT(temp, iocurrent); - } - EXTI->EMR = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - CLEAR_BIT(temp, (uint32_t)iocurrent); - if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - SET_BIT(temp, iocurrent); - } - EXTI->FTSR = temp; - } - } - - position++; - } -} - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0) - { - /* Get current io position */ - iocurrent = (GPIO_Pin) & (1U << position); - - if (iocurrent) - { - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= ((0x0FU) << (4 * (position & 0x03))); - if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)))) - { - /* Clear EXTI line configuration */ - CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent); - CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent); - - tmp = (0x0FU) << (4 * (position & 0x03)); - CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp); - } - - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floting Mode */ - CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); - - /* Configure the default Alternate Function in current IO */ - CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ; - /* Deactivate the Pull-up oand Pull-down resistor for the current IO */ - CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2)); - - /* Configure the default value IO Output Type */ - CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ; - - /* Configure the default value for IO Speed */ - CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - } - - position++; - } -} - -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 - * @brief GPIO Read, Write, Toggle, Lock and EXTI management functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Sets or clears the selected data port bit. - * @note This function uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if (PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ; - } -} - -/** - * @brief Toggles the specified GPIO pin - * @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices - * @param GPIO_Pin specifies the pins to be toggled. - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t odr; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* get current Ouput Data Register value */ - odr = GPIOx->ODR; - - /* Set selected pins that were at low level, and reset ones that were high */ - GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); -} - -/** -* @brief Locks GPIO Pins configuration registers. -* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, -* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. -* @note The configuration of the locked GPIO pins can no longer be modified -* until the next reset. -* @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8 -* depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i]. -* GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8]. -* It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also -* GPIOx_OTYPER[i-8]. -* Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15, -* you must call also HAL_GPIO_LockPin with GPIO_Pin - 8. -* (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding -* GPIO_PIN_0 to GPIO_PIN_7). -* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices -* @param GPIO_Pin Specifies the port bit to be locked. -* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). -* @retval None -*/ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - SET_BIT(tmp, GPIO_Pin); - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKK register. This read is mandatory to complete key lock sequence */ - tmp = GPIOx->LCKR; - - /* Read again in order to confirm lock is active */ - if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callbacks. - * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c deleted file mode 100644 index a1fdcc3..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr.c +++ /dev/null @@ -1,650 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define PVD_MODE_IT (0x00010000U) -#define PVD_MODE_EVT (0x00020000U) -#define PVD_RISING_EDGE (0x00000001U) -#define PVD_FALLING_EDGE (0x00000002U) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @note Before calling this function, the VOS[1:0] bits should be configured - * to "10" and the system frequency has to be configured accordingly. - * To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig() - * function. - * @note ULP and FWU bits are not reset by this function. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers ). - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - /* Enable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers). - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - /* Disable access to RTC and backup registers */ - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) The PVD can use an external input analog voltage (PVD_IN) which is compared - internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode - when PWR_PVDLevel_7 is selected (PLS[2:0] = 111). - - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - *** WakeUp pin configuration *** - ================================ - [..] - (+) WakeUp pin is used to wake up the system from Standby mode. This pin is - forced in input pull-down configuration and is active on rising edges. - (+) There are two or three WakeUp pins: - WakeUp Pin 1 on PA.00. - WakeUp Pin 2 on PC.13. - WakeUp Pin 3 on PE.06. : Only on product with GPIOE available - - [..] - *** Main and Backup Regulators configuration *** - ================================================ - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() - macro which configure VOS bit in PWR_CR register: - (++) When this bit is set (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 32 MHz. - (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 16 MHz. - (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) - the System frequency can go up to 4.2 MHz. - - Refer to the datasheets for more details. - - *** Low Power modes configuration *** - ===================================== - [..] - The device features 5 low-power modes: - (+) Low power run mode: regulator in low power mode, limited clock frequency, - limited number of peripherals running. - (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running. - (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, - limited number of peripherals running, regulator in low power mode. - (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode. - (+) Standby mode: VCORE domain powered off - - *** Low power run mode *** - ========================= - [..] - To further reduce the consumption when the system is in Run mode, the regulator can be - configured in low power mode. In this mode, the system frequency should not exceed - MSI frequency range1. - In Low power run mode, all I/O pins keep the same state as in Run mode. - - (+) Entry: - (++) VCORE in range2 - (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. - (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() - function. - (+) Exit: - (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode() - function. - (++) Increase the system frequency if needed. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Low power sleep mode *** - ============================ - [..] - (+) Entry: - The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. - This reduces power consumption but increases the wake-up time. - - (+) Exit: - (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt - acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device - from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode, - the MCU exits Sleep mode as soon as an event occurs. - - *** Stop mode *** - ================= - [..] - The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral - clock gating. The voltage regulator can be configured either in normal or low-power mode. - In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and - the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. - To get the lowest consumption in Stop mode, the internal Flash memory also enters low - power mode. When the Flash memory is in power-down mode, an additional startup delay is - incurred when waking up from Stop mode. - To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature - sensor can be switched off before entering Stop mode. They can be switched on again by - software after exiting Stop mode using the ULP bit in the PWR_CR register. - In Stop mode, all I/O pins keep the same state as in Run mode. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - (+) Exit: - (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock. - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based on the - Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is - consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are - also switched off. SRAM and register contents are lost except for the RTC registers, RTC - backup registers and Standby circuitry. - - To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature - sensor can be switched off before entering the Standby mode. They can be switched - on again by software after exiting the Standby mode. - function. - - (+) Entry: - (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() - function - (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() - and HAL_RTC_SetTime() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and - Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() - or HAL_RTCEx_SetTimeStamp_IT() functions. - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and - Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() - function. - - (+) RTC auto-wakeup (AWU) from the Standby mode - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function. - (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() - and HAL_RTC_SetTime() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to - detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT() - or HAL_RTCEx_SetTamper_IT()functions. - (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event - using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions. - - (+) Comparator auto-wakeup (AWU) from the Stop mode - (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup - event, it is necessary to: - (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the - selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using - the COMP functions. - (+++) Configure the comparator to generate the event. - - - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - /* Enable the power voltage detector */ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - /* Disable the power voltage detector */ - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Enable the EWUPx pin */ - *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE; -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - /* Disable the EWUPx pin */ - *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE; -} - -/** - * @brief Enters Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @param Regulator: Specifies the regulator state in SLEEP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON - * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. - * When WFI entry is used, tick interrupt have to be disabled if not desired as - * the interrupt wake up source. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters Stop mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by using an interrupt or a wakeup event, - * MSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator: Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */ - MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enters Standby mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - WKUP pin 1 (PA0) if enabled. - * - WKUP pin 2 (PC13) if enabled. - * - WKUP pin 3 (PE6) if enabled. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - SET_BIT(PWR->CR, PWR_CR_PDDS); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - - -/** - * @brief Enables CORTEX M3 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - -/** - * @brief Disables CORTEX M3 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - - - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c deleted file mode 100644 index e3580ec..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_pwr_ex.c +++ /dev/null @@ -1,161 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Extended Initialization and de-initialization functions - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended features functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Return Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3) - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ - return (PWR->CR & PWR_CR_VOS); -} - - -/** - * @brief Enables the Fast WakeUp from Ultra Low Power mode. - * @note This bit works in conjunction with ULP bit. - * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when - * exiting from low power mode. - * @retval None - */ -void HAL_PWREx_EnableFastWakeUp(void) -{ - /* Enable the fast wake up */ - *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Fast WakeUp from Ultra Low Power mode. - * @retval None - */ -void HAL_PWREx_DisableFastWakeUp(void) -{ - /* Disable the fast wake up */ - *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enables the Ultra Low Power mode - * @retval None - */ -void HAL_PWREx_EnableUltraLowPower(void) -{ - /* Enable the Ultra Low Power mode */ - *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Ultra Low Power mode - * @retval None - */ -void HAL_PWREx_DisableUltraLowPower(void) -{ - /* Disable the Ultra Low Power mode */ - *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE; -} - -/** - * @brief Enters the Low Power Run mode. - * @note Low power run mode can only be entered when VCORE is in range 2. - * In addition, the dynamic voltage scaling must not be used when Low - * power run mode is selected. Only Stop and Sleep modes with regulator - * configured in Low power mode is allowed when Low power run mode is - * selected. - * @note In Low power run mode, all I/O pins keep the same state as in Run mode. - * @retval None - */ -void HAL_PWREx_EnableLowPowerRunMode(void) -{ - /* Enters the Low Power Run mode */ - *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE; - *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE; -} - -/** - * @brief Exits the Low Power Run mode. - * @retval None - */ -HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) -{ - /* Exits the Low Power Run mode */ - *(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE; - *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE; - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c deleted file mode 100644 index 7be986e..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc.c +++ /dev/null @@ -1,1394 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from multispeed internal oscillator clock - (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, - and all peripherals are off except internal SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; - all peripherals mapped on these buses are running at MSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB buses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals whose clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - (*) SDIO only for STM32L1xxxD devices - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC -* @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ -extern const uint8_t PLLMulTable[]; /* Defined in CMSIS (system_stm32l0xx.c)*/ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_Private_Functions RCC Private Functions - * @{ - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz, - 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. - - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring different output clocks: - (++) The first output is used to generate the high speed system clock (up to 32 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz) - - (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clocks automatically switched to MSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M3 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, - HSE or PLL clock (through a configurable prescaler) on PA8 pin. - - [..] System, AHB and APB buses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these buses. You can use - "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 16. You have to use @ref __HAL_RCC_RTC_CONFIG() and @ref __HAL_RCC_RTC_ENABLE() - macros to configure this clock. - (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 16. You have to use @ref __HAL_RCC_LCD_CONFIG() - macros to configure this clock. - (+@) USB OTG FS: USB OTG FS require a frequency equal to 48 MHz - to work correctly. This clock is derived of the main PLL through PLL Multiplier. - - (+@) IWDG clock which is always the LSI clock. - - (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz - and PCLK1 32 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly. - @endverbatim - * @{ - */ - -/* - Additional consideration on the HCLK based on Latency settings: - +----------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |------------------------------------------------------| - | | voltage range 1 | voltage range 2 | voltage range 3 | - | | 1.8 V | 1.5 V | 1.2 V | - |---------------|------------------|-----------------|-----------------| - |0WS(1CPU cycle)| 0 < HCLK <= 16 | 0 < HCLK <= 8 | 0 < HCLK <= 2 | - |---------------|------------------|-----------------|-----------------| - |1WS(2CPU cycle)| 16 < HCLK <= 32 | 8 < HCLK <= 16 | 2 < HCLK <= 4 | - +----------------------------------------------------------------------+ - - The following table gives the different clock source frequencies depending on the product - voltage range: - +------------------------------------------------------------------------------------------+ - | Product voltage | Clock frequency | - | |------------------|-----------------------------|-----------------------| - | range | MSI | HSI | HSE | PLL | - |-----------------|---------|--------|-----------------------------|-----------------------| - | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) | 32 MHz | - | | | | or 24 MHz (crystal) | (PLLVCO max = 96 MHz) | - |-----------------|---------|--------|-----------------------------|-----------------------| - | Range 2 (1.5 V) | 4.2 MHz | 16 MHz | 16 MHz | 16 MHz | - | | | | | (PLLVCO max = 48 MHz) | - |-----------------|---------|--------|-----------------------------|-----------------------| - | Range 3 (1.2 V) | 4.2 MHz | NA | 8 MHz | 4 MHz | - | | | | | (PLLVCO max = 24 MHz) | - +------------------------------------------------------------------------------------------+ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source - * - HSI, HSE and PLL OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS and MCO1 OFF - * - All interrupts disabled - * @note This function does not modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart; - HAL_StatusTypeDef status; - - /* Set MSIClockRange, HSITRIM and MSITRIM bits to the reset values */ - MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSITRIM | RCC_ICSCR_HSITRIM | RCC_ICSCR_MSIRANGE), \ - ((RCC_MSICALIBRATION_DEFAULT << RCC_ICSCR_MSITRIM_Pos) | (RCC_HSICALIBRATION_DEFAULT << RCC_ICSCR_HSITRIM_Pos) | RCC_ICSCR_MSIRANGE_5)); - - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSION); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Switch SYSCLK to MSI*/ - CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW); - - /* Wait till MSI as SYSCLK status is ready */ - while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != 0U) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = MSI_VALUE; - - /* Configure the source of time base considering new system clock settings */ - status = HAL_InitTick(uwTickPrio); - if(status != HAL_OK) - { - return status; - } - - /* Reset HSION, HSEON, CSSON & PLLON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is not ready */ - while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIR); - - /* Clear all flags */ -#if defined(RCC_LSECSS_SUPPORT) - WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC | RCC_CIR_LSECSSC | RCC_CIR_CSSC); -#else - WRITE_REG(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_MSIRDYC | RCC_CIR_CSSC); -#endif - - /* Clear all reset flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - return HAL_OK; -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart; - HAL_StatusTypeDef status; - uint32_t sysclk_source, pll_config; - - /* Check the parameters */ - if(RCC_OscInitStruct == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); - - /*------------------------------- HSE Configuration ------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) - { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) - { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- MSI Configuration --------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - { - /* When the MSI is used as system clock it will not be disabled */ - if(sysclk_source == RCC_CFGR_SWS_MSI) - { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration and MSI range change are allowed */ - else - { - /* Check MSICalibrationValue and MSIClockRange input parameters */ - assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - { - /* First increase number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - } - else - { - /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - - /* Decrease number of wait states update if necessary */ - if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U))) - >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; - - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - if(status != HAL_OK) - { - return status; - } - } - } - else - { - /* Check MSI State */ - assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); - - /* Check the MSI State */ - if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) - { - /* Enable the Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Check MSICalibrationValue and MSIClockRange input parameters */ - assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); - - /* Selects the Multiple Speed oscillator (MSI) clock range .*/ - __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); - - } - else - { - /* Disable the Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) - { - if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U) - { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL)); - assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV)); - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLMUL, - RCC_OscInitStruct->PLL.PLLDIV); - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - /* Check if there is a request to disable the PLL used as System clock source */ - if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - { - return HAL_ERROR; - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->CFGR; - if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) || - (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV)) - { - return HAL_ERROR; - } - } - } - } - - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * The value of this parameter depend on device used within the same series - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The MSI is used (enabled by hardware) as system clock source after - * start-up from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after start-up delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart; - HAL_StatusTypeDef status; - - /* Check the parameters */ - if(RCC_ClkInitStruct == NULL) - { - return HAL_ERROR; - } - - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if(FLatency > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - /* Check the HSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else - { - /* Check the MSI ready flag */ - if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U) - { - return HAL_ERROR; - } - } - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) - { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /* Decreasing the number of wait states because of lower CPU frequency */ - if(FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - - return status; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - - @endverbatim - * @{ - */ - -/** - * @brief Selects the clock source to output on MCO pin. - * @note MCO pin should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_MSI MSI oscillator clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO clock - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO clock - * @param RCC_MCODiv specifies the MCO DIV. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock - * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock - * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock - * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef gpio; - - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* Configure the MCO1 pin in alternate function mode */ - gpio.Mode = GPIO_MODE_AF_PP; - gpio.Speed = GPIO_SPEED_FREQ_HIGH; - gpio.Pull = GPIO_NOPULL; - gpio.Pin = MCO1_PIN; - gpio.Alternate = GPIO_AF0_MCO; - - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - - HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio); - - /* Configure the MCO clock source */ - __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv); -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; -} - -/** - * @brief Returns the SYSCLK frequency - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is MSI, function returns a value based on MSI - * Value as defined by the MSI range. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq; - - tmpreg = RCC->CFGR; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (tmpreg & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ - { - pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos]; - plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U; - if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - { - /* HSE used as PLL clock source */ - pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld); - } - sysclockfreq = pllvco; - break; - } - case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */ - default: /* MSI used as system clock */ - { - msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos; - sysclockfreq = (32768U * (1UL << (msiclkrange + 1U))); - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated within this function - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); -} - -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Check the parameters */ - assert_param(RCC_OscInitStruct != (void *)NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \ - | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI; - - - /* Get the HSE configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos); - - /* Get the MSI configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION) - { - RCC_OscInitStruct->MSIState = RCC_MSI_ON; - } - else - { - RCC_OscInitStruct->MSIState = RCC_MSI_OFF; - } - - RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos); - RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE)); - - /* Get the LSE configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - - /* Get the PLL configuration -----------------------------------------------*/ - if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL); - RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV); -} - -/** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * contains the current clock configuration. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(RCC_ClkInitStruct != (void *)NULL); - assert_param(pFLatency != (void *)NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = __HAL_FLASH_GET_LATENCY(); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup RCC_Private_Functions - * @{ - */ -/** - * @brief Update number of Flash wait states in line with MSI range and current - voltage range - * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6 - * @retval HAL status - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange) -{ - uint32_t vos; - uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ - - /* HCLK can reach 4 MHz only if AHB prescaler = 1 */ - if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1) - { - if(__HAL_RCC_PWR_IS_CLK_ENABLED()) - { - vos = READ_BIT(PWR->CR, PWR_CR_VOS); - } - else - { - __HAL_RCC_PWR_CLK_ENABLE(); - vos = READ_BIT(PWR->CR, PWR_CR_VOS); - __HAL_RCC_PWR_CLK_DISABLE(); - } - - /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */ - if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6)) - { - latency = FLASH_LATENCY_1; /* 1WS */ - } - } - - __HAL_FLASH_SET_LATENCY(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if(__HAL_FLASH_GET_LATENCY() != latency) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c deleted file mode 100644 index aa5e200..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rcc_ex.c +++ /dev/null @@ -1,440 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - *

© Copyright(c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/** @defgroup RCCEx RCCEx - * @brief RCC Extension HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). - * @retval HAL status - * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() - * to possibly update HSE divider. - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart; - uint32_t temp_reg; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*------------------------------- RTC/LCD Configuration ------------------------*/ - if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) -#if defined(LCD) - || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) -#endif /* LCD */ - ) - { - /* check for RTC Parameters used to output RTCCLK */ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - { - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - } - -#if defined(LCD) - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) - { - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); - } -#endif /* LCD */ - - FlagStatus pwrclkchanged = RESET; - - /* As soon as function is called to change RTC clock source, activation of the - power domain is done. */ - /* Requires to enable write access to Backup Domain of necessary */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->CR, PWR_CR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ - temp_reg = (RCC->CR & RCC_CR_RTCPRE); - if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) -#if defined (LCD) - || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) -#endif /* LCD */ - ) - { /* Check HSE State */ - if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - { - /* To update HSE divider, first switch-OFF HSE clock oscillator*/ - return HAL_ERROR; - } - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ - temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); - - if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ - && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#if defined(LCD) - || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ - && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) -#endif /* LCD */ - )) - { - /* Store the content of CSR register before the reset of Backup Domain */ - temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); - - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - /* Restore the Content of CSR register */ - RCC->CSR = temp_reg; - - /* Wait for LSERDY if LSE was enabled */ - if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) - { - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - - /* Require to disable power clock if necessary */ - if(pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - return HAL_OK; -} - -/** - * @brief Get the PeriphClkInit according to the internal RCC configuration registers. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t srcclk; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; -#if defined(LCD) - PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; -#endif /* LCD */ - - /* Get the RTC/LCD configuration -----------------------------------------------*/ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) - { - /* Source clock is LSE or LSI*/ - PeriphClkInit->RTCClockSelection = srcclk; - } - else - { - /* Source clock is HSE. Need to get the prescaler value*/ - PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); - } -#if defined(LCD) - PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; -#endif /* LCD */ -} - -/** - * @brief Return the peripheral clock frequency - * @note Return 0 if peripheral clock is unknown - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*) - * @note (*) means that this peripheral is not present on all the devices - * @retval Frequency in Hz (0: means that no available frequency for the peripheral) - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - uint32_t frequency = 0; - uint32_t srcclk; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - switch (PeriphClk) - { - case RCC_PERIPHCLK_RTC: -#if defined(LCD) - case RCC_PERIPHCLK_LCD: -#endif /* LCD */ - { - /* Get the current RTC source */ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - - /* Check if LSE is ready if RTC clock selection is LSE */ - if (srcclk == RCC_RTCCLKSOURCE_LSE) - { - if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)) - { - frequency = LSE_VALUE; - } - } - /* Check if LSI is ready if RTC clock selection is LSI */ - else if (srcclk == RCC_RTCCLKSOURCE_LSI) - { - if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) - { - frequency = LSI_VALUE; - } - } - /* Check if HSE is ready and if RTC clock selection is HSE */ - else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) - { - /* Get the current HSE clock divider */ - switch (__HAL_RCC_GET_RTC_HSE_PRESCALER()) - { - case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ - { - frequency = HSE_VALUE / 16U; - break; - } - case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ - { - frequency = HSE_VALUE / 8U; - break; - } - case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ - { - frequency = HSE_VALUE / 4U; - break; - } - default: /* HSE DIV2 has been selected */ - { - frequency = HSE_VALUE / 2U; - break; - } - } - } - } - else - { - /* No clock source, frequency default init at 0 */ - } - break; - } - - default: - break; - } - - return(frequency); -} - -#if defined(RCC_LSECSS_SUPPORT) -/** - * @brief Enables the LSE Clock Security System. - * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied - * to the RTC but no hardware action is made to the registers. - * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup - * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104). - * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator - * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with - * RTCSEL), or take any required action to secure the application. - * @note LSE CSS available only for high density and medium+ devices - * @retval None - */ -void HAL_RCCEx_EnableLSECSS(void) -{ - *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; -} - -/** - * @brief Disables the LSE Clock Security System. - * @note Once enabled this bit cannot be disabled, except after an LSE failure detection - * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. - * Reset by power on reset and RTC software reset (RTCRST bit). - * @note LSE CSS available only for high density and medium+ devices - * @retval None - */ -void HAL_RCCEx_DisableLSECSS(void) -{ - /* Disable LSE CSS */ - *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; - - /* Disable LSE CSS IT */ - __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); -} - -/** - * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. - * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 - * @retval None - */ -void HAL_RCCEx_EnableLSECSS_IT(void) -{ - /* Enable LSE CSS */ - *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; - - /* Enable LSE CSS IT */ - __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); - - /* Enable IT on EXTI Line 19 */ - __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); - __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); -} - -/** - * @brief Handle the RCC LSE Clock Security System interrupt request. - * @retval None - */ -void HAL_RCCEx_LSECSS_IRQHandler(void) -{ - /* Check RCC LSE CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) - { - /* RCC LSE Clock Security System interrupt user callback */ - HAL_RCCEx_LSECSS_Callback(); - - /* Clear RCC LSE CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); - } -} - -/** - * @brief RCCEx LSE Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_LSECSS_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file - */ -} -#endif /* RCC_LSECSS_SUPPORT */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c deleted file mode 100644 index 8040dd0..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc.c +++ /dev/null @@ -1,1865 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc.c - * @author MCD Application Team - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) peripheral: - * + Initialization and de-initialization functions - * + RTC Time and Date functions - * + RTC Alarm functions - * + Peripheral Control functions - * + Peripheral State functions - * - @verbatim - =============================================================================== - ##### RTC Operating Condition ##### - =============================================================================== - [..] The real-time clock (RTC) and the RTC backup registers can be powered - from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers and supply the RTC - when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC operating even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) PC13 to PC15 I/Os (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following pins are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following pins are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - - ##### Backup Domain Reset ##### - =============================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() function. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. - (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. - - - ##### How to use RTC Driver ##### - =================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the - HAL_RTC_SetAlarm_IT() function. - (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - ##### RTC and low power modes ##### - ================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and STANDBY modes is possible only when the RTC clock source - is LSE or LSI. - - *** Callback registration *** - ============================================= - - [..] - The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. - - [..] - Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: - (+) AlarmAEventCallback : RTC Alarm A Event callback. - (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC TimeStamp Event callback. - (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. - (+) Tamper3EventCallback : RTC Tamper 3 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) AlarmAEventCallback : RTC Alarm A Event callback. - (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC TimeStamp Event callback. - (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. - (+) Tamper3EventCallback : RTC Tamper 3 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. - - [..] - By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, - all callbacks are set to the corresponding weak functions : - examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). - Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null - (not registered beforehand). - If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - [..] - Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() - or @ref HAL_RTC_Init() function. - - [..] - When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - - -/** @addtogroup RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RTC_Exported_Functions - * @{ - */ - -/** @addtogroup RTC_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection, enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the RTC peripheral - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - /* Check the RTC peripheral state */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if (hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ - hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - if (hrtc->MspInitCallback == NULL) - { - hrtc->MspInitCallback = HAL_RTC_MspInit; - } - /* Init the low level hardware */ - hrtc->MspInitCallback(hrtc); - - if (hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - } -#else - if (hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; - hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; - } -} - -/** - * @brief DeInitialize the RTC peripheral. - * @param hrtc RTC handle - * @note This function does not reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - hrtc->Instance->TR = 0x00000000U; - hrtc->Instance->DR = 0x00002101U; - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= 0x00000007U; - - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while (((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= 0x00000000U; - hrtc->Instance->WUTR = 0x0000FFFFU; - hrtc->Instance->PRER = 0x007F00FFU; - hrtc->Instance->CALIBR = 0x00000000U; - hrtc->Instance->ALRMAR = 0x00000000U; - hrtc->Instance->ALRMBR = 0x00000000U; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - hrtc->Instance->SHIFTR = 0x00000000U; - hrtc->Instance->CALR = 0x00000000U; - hrtc->Instance->ALRMASSR = 0x00000000U; - hrtc->Instance->ALRMBSSR = 0x00000000U; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = 0x00000000U; - - /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAFCR = 0x00000000U; - - /* Wait for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if (hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hrtc->MspDeInitCallback(hrtc); - -#else - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ - - hrtc->State = HAL_RTC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User RTC Callback - * To be used instead of the weak predefined callback - * @param hrtc RTC handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID - * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hrtc); - - if (HAL_RTC_STATE_READY == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = pCallback; - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = pCallback; - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = pCallback; - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = pCallback; - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = pCallback; - break; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = pCallback; - break; - - case HAL_RTC_TAMPER3_EVENT_CB_ID : - hrtc->Tamper3EventCallback = pCallback; - break; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RTC_STATE_RESET == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Unregister an RTC Callback - * RTC callabck is redirected to the weak predefined callback - * @param hrtc RTC handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID - * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hrtc); - - if (HAL_RTC_STATE_READY == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - break; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ - break; - - case HAL_RTC_TAMPER3_EVENT_CB_ID : - hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ - break; -#endif - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RTC_STATE_RESET == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @brief Initialize the RTC MSP. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the RTC MSP. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group2 - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Set RTC current time. - * @param hrtc RTC handle - * @param sTime Pointer to Time structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (Format == RTC_FORMAT_BIN) - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16U)); - } - else - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - ((uint32_t)(sTime->Minutes) << 8U) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16U)); - } - UNUSED(tmpreg); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_TR register */ - hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Clear the bits to be configured */ - hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP); - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* Wait for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Get RTC current time. - * @param hrtc RTC handle - * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned - * with input format (BIN or BCD), also SubSeconds field (if availabale) returning the - * RTC_SSR register content and SecondFraction field the Synchronous pre-scaler - * factor to be used for second fraction ratio computation. - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note If available, you can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds - * value in second fraction ratio with time unit following generic formula: - * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read - * to ensure consistency between the time and date values. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Get subseconds structure field from the corresponding register*/ - sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS); - - /* Get SecondFraction structure field from the corresponding register field*/ - sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Get the TR register */ - tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); - - /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - { - /* Convert the time structure parameters to Binary format */ - sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - } - - return HAL_OK; -} - -/** - * @brief Set RTC current date. - * @param hrtc RTC handle - * @param sDate Pointer to date structure - * @param Format specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) - { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); - } - - assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - - if (Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13U)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); - assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - - datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - (((uint32_t)sDate->Month) << 8U) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13U)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Set the RTC_DR register */ - hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - - /* Wait for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY ; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; - } -} - -/** - * @brief Get RTC current date. - * @param hrtc RTC handle - * @param sDate Pointer to Date structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the DR register */ - datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); - - /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - { - /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group3 - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ -/** - * @brief Set the specified RTC Alarm. - * @param hrtc RTC handle - * @param sAlarm Pointer to Alarm structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart; - uint32_t tmpreg; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (Format == RTC_FORMAT_BIN) - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if (sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set the specified RTC Alarm with Interrupt. - * @param hrtc RTC handle - * @param sAlarm Pointer to Alarm structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0; - uint32_t tmpreg = 0; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - uint32_t subsecondtmpreg = 0; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (Format == RTC_FORMAT_BIN) - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if (sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the Alarm A Sub Second register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B interrupt */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear flag alarm B */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the Alarm B Sub Second register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); - } - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate the specified RTC Alarm. - * @param hrtc RTC handle - * @param Alarm Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - if (Alarm == RTC_ALARM_A) - { - /* AlarmA */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - else - { - /* AlarmB */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param hrtc RTC handle - * @param sAlarm Pointer to Date structure - * @param Alarm Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t tmpreg; -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - uint32_t subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(Alarm)); - - if (Alarm == RTC_ALARM_A) - { - /* AlarmA */ - sAlarm->Alarm = RTC_ALARM_A; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - } - else - { - sAlarm->Alarm = RTC_ALARM_B; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - } - - /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if (Format == RTC_FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - } - - return HAL_OK; -} - -/** - * @brief Handle Alarm interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get the AlarmA interrupt source enable status */ - if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) - { - /* Get the pending status of the AlarmA Interrupt */ - if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) - { - /* AlarmA callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->AlarmAEventCallback(hrtc); -#else - HAL_RTC_AlarmAEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the AlarmA interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - } - } - - /* Get the AlarmB interrupt source enable status */ - if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) - { - /* Get the pending status of the AlarmB Interrupt */ - if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) - { - /* AlarmB callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->AlarmBEventCallback(hrtc); -#else - HAL_RTCEx_AlarmBEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the AlarmB interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - } - } - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle AlarmA Polling request. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - - uint32_t tickstart = HAL_GetTick(); - - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group4 - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - -@endverbatim - * @{ - */ - -/** - * @brief Wait until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - { - /* Clear RSF flag */ - hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group5 - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Return the RTC handle state. - * @param hrtc RTC handle - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) -{ - /* Return RTC handle state */ - return hrtc->State; -} - -/** - * @} - */ -/** - * @} - */ - -/** @addtogroup RTC_Private_Functions - * @{ - */ -/** - * @brief Enter the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart; - - /* Check if the Initialization mode is set */ - if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) - { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - - -/** - * @brief Convert a 2 digit decimal to BCD format. - * @param Value Byte to be converted - * @retval Converted byte - */ -uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint32_t bcdhigh = 0U; - uint8_t Param = Value; - - while (Param >= 10U) - { - bcdhigh++; - Param -= 10U; - } - - return ((uint8_t)(bcdhigh << 4U) | Param); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value BCD value to be converted - * @retval Converted word - */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint32_t tmp; - tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U; - return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU)); -} - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c deleted file mode 100644 index 6d06b39..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_rtc_ex.c +++ /dev/null @@ -1,1806 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_rtc_ex.c - * @author MCD Application Team - * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extended peripheral: - * + RTC Time Stamp functions - * + RTC Tamper functions - * + RTC Wake-up functions - * + Extended Control functions - * + Extended RTC features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer with interrupt mode - using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() - function. - - *** TimeStamp configuration *** - =============================== - [..] - (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the - HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with - interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - (+) The TIMESTAMP alternate function can be mapped to RTC_AF1 (PC13). - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, precharge or discharge and Pull-UP using the - HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt - mode using HAL_RTCEx_SetTamper_IT() function. - (+) The TAMPER1 alternate function can be mapped to RTC_AF1 (PC13). - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RTCEx_Exported_Functions - * @{ - */ - - -/** @addtogroup RTCEx_Exported_Functions_Group1 - * @brief RTC TimeStamp and Tamper functions - * -@verbatim - =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure TimeStamp feature - -@endverbatim - * @{ - */ - -/** - * @brief Set TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc RTC handle - * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg |= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set TimeStamp with Interrupt. - * @param hrtc RTC handle - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - tmpreg |= TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS); - - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate TimeStamp. - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) -{ - uint32_t tmpreg; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Time Stamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get the RTC TimeStamp value. - * @param hrtc RTC handle - * @param sTimeStamp Pointer to Time structure - * @param sTimeStampDate Pointer to Date structure - * @param Format specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) -{ - uint32_t tmptime, tmpdate; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - sTimeStamp->SubSeconds = (uint32_t)((hrtc->Instance->TSSSR) & RTC_TSSSR_SS); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0U; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); - - /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); - sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); - sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); - - /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); - sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); - } - - /* Clear the TIMESTAMP Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - return HAL_OK; -} - -/** - * @brief Set Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc RTC handle - * @param sTamper Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - if ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) - { - /* Configure the RTC_TAFCR register */ - sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; - } - else - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \ - (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS | \ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \ - (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE); -#else - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Trigger)); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG); - -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - hrtc->Instance->TAFCR |= tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc RTC handle - * @param sTamper Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Configure the tamper trigger */ - if ((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE)) - { - sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE; - } - else - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter | \ - (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration | \ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS | \ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH | \ - (uint32_t)RTC_TAFCR_TAMPPUDIS); -#else - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger); - - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPIE); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - hrtc->Instance->TAFCR |= tmpreg; - - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate Tamper. - * @param hrtc RTC handle - * @param Tamper Selected tamper pin. - * This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - hrtc->Instance->TAFCR &= (uint32_t)~Tamper; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Handle TimeStamp interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get the TimeStamp interrupt source enable status */ - if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) - { - /* Get the pending status of the TIMESTAMP Interrupt */ - if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U) - { - /* TIMESTAMP callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->TimeStampEventCallback(hrtc); -#else - HAL_RTCEx_TimeStampEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - } - } - - /* Get the Tamper1 interrupts source enable status */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) - { - /* Get the pending status of the Tamper1 Interrupt */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) - { - /* Tamper1 callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper1EventCallback(hrtc); -#else - HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper1 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - } - } - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Get the Tamper2 interrupts source enable status */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) - { - /* Get the pending status of the Tamper2 Interrupt */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) - { - /* Tamper2 callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper2EventCallback(hrtc); -#else - HAL_RTCEx_Tamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper2 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - } - } - - /* Get the Tamper3 interrupts source enable status */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) - { - /* Get the pending status of the Tamper3 Interrupt */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) - { - /* Tamper3 callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper3EventCallback(hrtc); -#else - HAL_RTCEx_Tamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Tamper3 interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - } - } -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief TimeStamp callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 1 callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Tamper 2 callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 3 callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @brief Handle TimeStamp polling request. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) - { - if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Handle Tamper 1 Polling. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Handle Tamper 2 Polling. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Handle Tamper 3 Polling. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @} - */ - -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @brief RTC Wake-up functions - * -@verbatim - =============================================================================== - ##### RTC Wake-up functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Wake-up feature - -@endverbatim - * @{ - */ - -/** - * @brief Set wake up timer. - * @param hrtc RTC handle - * @param WakeUpCounter Wake up counter - * @param WakeUpClock Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Set wake up timer with interrupt. - * @param hrtc RTC handle - * @param WakeUpCounter Wake up counter - * @param WakeUpClock Wake up clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 1U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Disable the Wake-Up timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Clear flag Wake-Up */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate wake up timer counter. - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); - - tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Get wake up timer counter. - * @param hrtc RTC handle - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Handle Wake Up Timer interrupt request. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Get the pending status of the WAKEUPTIMER Interrupt */ - if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) - { - /* WAKEUPTIMER callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->WakeUpTimerEventCallback(hrtc); -#else - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - } - - - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Wake Up Timer callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle Wake Up Timer Polling. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - } - - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - - -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Write a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Set the Coarse calibration parameters. - (+) Deactivate the Coarse calibration parameters - (+) Set the Smooth calibration parameters. - (+) Configure the Synchronization Shift Control Settings. - (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enable the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enable the Bypass Shadow feature. - (+) Disable the Bypass Shadow feature. - -@endverbatim - * @{ - */ - -/** - * @brief Write a data in a specified RTC Backup data register. - * @param hrtc RTC handle - * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t) & (hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4U); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc RTC handle - * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t) & (hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4U); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @brief Sets the Coarse calibration parameters. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CalibSign Specifies the sign of the coarse calibration value. - * This parameter can be one of the following values : - * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive - * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative - * @param Value value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Enable the Coarse Calibration */ - __HAL_RTC_COARSE_CALIB_ENABLE(hrtc); - - /* Set the coarse calibration value */ - hrtc->Instance->CALIBR = (uint32_t)(CalibSign | Value); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates the Coarse calibration parameters. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - /* Enable the Coarse Calibration */ - __HAL_RTC_COARSE_CALIB_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Set the Smooth calibration parameters. - * @param hrtc RTC handle - * @param SmoothCalibPeriod Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmoothCalibMinusPulsesValue mut be equal to 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* check if a calibration is pending*/ - if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) - { - tickstart = HAL_GetTick(); - - /* check if a calibration is pending*/ - while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configure the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc RTC handle - * @param ShiftAdd1S Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed*/ - while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Check if the reference clock detection is disabled */ - if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - - /* Wait for synchro */ - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc RTC handle - * @param CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) -#else -/** - * @brief Configure the Calibration Pinout (RTC_CALIB). - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc) -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ -{ -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enable the RTC reference clock detection. - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the RTC reference clock detection. - * @param hrtc RTC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if (RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) -/** - * @brief Enable the Bypass Shadow feature. - * @param hrtc RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disable the Bypass Shadow feature. - * @param hrtc RTC handle - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} -#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ - -/** - * @} - */ - -/** @addtogroup RTCEx_Exported_Functions_Group4 - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alram B callback - (+) RTC Poll for Alarm B request - -@endverbatim - * @{ - */ - -/** - * @brief Alarm B callback. - * @param hrtc RTC handle - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handle Alarm B Polling request. - * @param hrtc RTC handle - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c deleted file mode 100644 index 64ad564..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim.c +++ /dev/null @@ -1,6966 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + TIM Time Base Initialization - * + TIM Time Base Start - * + TIM Time Base Start Interruption - * + TIM Time Base Start DMA - * + TIM Output Compare/PWM Initialization - * + TIM Output Compare/PWM Channel Configuration - * + TIM Output Compare/PWM Start - * + TIM Output Compare/PWM Start Interruption - * + TIM Output Compare/PWM Start DMA - * + TIM Input Capture Initialization - * + TIM Input Capture Channel Configuration - * + TIM Input Capture Start - * + TIM Input Capture Start Interruption - * + TIM Input Capture Start DMA - * + TIM One Pulse Initialization - * + TIM One Pulse Channel Configuration - * + TIM One Pulse Start - * + TIM Encoder Interface Initialization - * + TIM Encoder Interface Start - * + TIM Encoder Interface Start Interruption - * + TIM Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + TIM OCRef clear configuration - * + TIM External Clock configuration - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to interconnect - several timers together. - (#) Supports incremental encoder for positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - *** Callback registration *** - ============================================= - - [..] - The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, - the Callback ID and a pointer to the user callback function. - - [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - - [..] - These functions allow to register/unregister following callbacks: - (+) Base_MspInitCallback : TIM Base Msp Init Callback. - (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. - (+) IC_MspInitCallback : TIM IC Msp Init Callback. - (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. - (+) OC_MspInitCallback : TIM OC Msp Init Callback. - (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. - (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. - (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. - (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. - (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. - (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. - (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. - (+) PeriodElapsedCallback : TIM Period Elapsed Callback. - (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. - (+) TriggerCallback : TIM Trigger Callback. - (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. - (+) IC_CaptureCallback : TIM Input Capture Callback. - (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. - (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. - (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. - (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. - (+) ErrorCallback : TIM Error Callback. - - [..] -By default, after the Init and when the state is HAL_TIM_STATE_RESET -all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). - - [..] - Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init / DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit - keep and use the user MspInit / MspDeInit callbacks(registered beforehand) - - [..] - Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. - Exception done MspInit / MspDeInit that can be registered / unregistered - in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, - thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. - - [..] - When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); -static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Base_MspInitCallback == NULL) - { - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Base_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Base_MspDeInitCallback == NULL) - { - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Base_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - if (htim->State == HAL_TIM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) - { - return HAL_ERROR; - } - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * -@verbatim - ============================================================================== - ##### TIM Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the TIM Output Compare. - (+) Stop the TIM Output Compare. - (+) Start the TIM Output Compare and enable interrupt. - (+) Stop the TIM Output Compare and disable interrupt. - (+) Start the TIM Output Compare and enable DMA transfer. - (+) Stop the TIM Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OC_MspInitCallback == NULL) - { - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OC_MspDeInitCallback == NULL) - { - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) - { - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) - { - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - break; - } - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - break; - } - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * -@verbatim - ============================================================================== - ##### TIM PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM PWM. - (+) De-initialize the TIM PWM. - (+) Start the TIM PWM. - (+) Stop the TIM PWM. - (+) Start the TIM PWM and enable interrupt. - (+) Stop the TIM PWM and disable interrupt. - (+) Start the TIM PWM and enable DMA transfer. - (+) Stop the TIM PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->PWM_MspInitCallback == NULL) - { - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->PWM_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->PWM_MspDeInitCallback == NULL) - { - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - } - /* DeInit the low level hardware */ - htim->PWM_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) - { - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - break; - } - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - break; - } - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * -@verbatim - ============================================================================== - ##### TIM Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the TIM Input Capture. - (+) Stop the TIM Input Capture. - (+) Start the TIM Input Capture and enable interrupt. - (+) Stop the TIM Input Capture and disable interrupt. - (+) Start the TIM Input Capture and enable DMA transfer. - (+) Stop the TIM Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->IC_MspInitCallback == NULL) - { - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->IC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->IC_MspDeInitCallback == NULL) - { - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->IC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM Input Capture handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (channel_state != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (channel_state != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if (channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - if (channel_state == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - break; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - break; - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * -@verbatim - ============================================================================== - ##### TIM One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the TIM One Pulse. - (+) Stop the TIM One Pulse. - (+) Start the TIM One Pulse and enable interrupt. - (+) Stop the TIM One Pulse and disable interrupt. - (+) Start the TIM One Pulse and enable DMA transfer. - (+) Stop the TIM One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @note When the timer instance is initialized in One Pulse mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM One Pulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OnePulse_MspInitCallback == NULL) - { - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OnePulse_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OnePulse_MspDeInitCallback == NULL) - { - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OnePulse_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim TIM One Pulse handle - * @param OutputChannel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * -@verbatim - ============================================================================== - ##### TIM Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the TIM Encoder. - (+) Stop the TIM Encoder. - (+) Start the TIM Encoder and enable interrupt. - (+) Stop the TIM Encoder and disable interrupt. - (+) Start the TIM Encoder and enable DMA transfer. - (+) Stop the TIM Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together - * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource - * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa - * @note When the timer instance is initialized in Encoder mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Encoder_MspInitCallback == NULL) - { - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Encoder_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the SMS and ECE bits */ - htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Encoder_MspDeInitCallback == NULL) - { - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Encoder_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if (channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if (channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData1 == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else if (Channel == TIM_CHANNEL_2) - { - if (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData2 == NULL) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_ALL: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) - { - return HAL_ERROR; - } - - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) - { - return HAL_ERROR; - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - default: - break; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief TIM IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Trigger detection event */ - if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief TIM Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - break; - } - - default: - break; - } - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM output channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM input Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @note To output a waveform with a minimum delay user can enable the fast - * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx - * output is forced in response to the edge detection on TIx input, - * without taking in account the comparison. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel) -{ - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if (OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Output compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - break; - } - default: - break; - } - - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_OR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_OR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - default: - break; - } - - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - break; - } - - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Return function status */ - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_OR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_OR - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - return HAL_ERROR; - } - break; - } - default: - break; - } - - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - break; - } - - if (HAL_OK == status) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - } - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Return function status */ - return status; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @note Basic timers can only generate an update event. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Clear the OCREF clear selection bit and the the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - break; - } - case TIM_CLEARINPUTSOURCE_OCREFCLR: - { - /* Clear the OCREF clear selection bit */ - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - } - break; - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - break; - } - - default: - break; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - break; - } - default: - break; - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) -{ - uint32_t tmpsmcr; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - break; - } - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - break; - } - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - break; - } - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - break; - } - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - break; - } - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - break; - } - - case TIM_CLOCKSOURCE_ITR0: - case TIM_CLOCKSOURCE_ITR1: - case TIM_CLOCKSOURCE_ITR2: - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } - - default: - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) TIM Period elapsed callback - (+) TIM Output Compare callback - (+) TIM Input capture callback - (+) TIM Trigger callback - (+) TIM Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Period elapsed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture half complete callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User TIM callback to be used instead of the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @param pCallback pointer to the callback function - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(htim); - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = pCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Unregister a TIM callback - * TIM callback is redirected to the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(htim); - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ - break; - - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ - break; - - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return status; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief TIM Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Output Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder Interface handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM handle - * @retval Active channel - */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) -{ - return htim->Channel; -} - -/** - * @brief Return actual state of the TIM channel. - * @param htim TIM handle - * @param Channel TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval TIM Channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - return channel_state; -} - -/** - * @brief Return actual state of a DMA burst operation. - * @param htim TIM handle - * @retval DMA burst state - */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - - return htim->DMABurstState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedHalfCpltCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureHalfCpltCallback(htim); -#else - HAL_TIM_IC_CaptureHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Period Elapse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedHalfCpltCallback(htim); -#else - HAL_TIM_PeriodElapsedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerHalfCpltCallback(htim); -#else - HAL_TIM_TriggerHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = Structure->Prescaler; - - /* Generate an update event to reload the Prescaler - and the repetition counter (only for advanced timer) value immediately */ - TIMx->EGR = TIM_EGR_UG; -} - -/** - * @brief Timer Output Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Slave Timer configuration function - * @param htim TIM handle - * @param sSlaveConfig Slave timer configuration - * @retval None - */ -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) - { - return HAL_ERROR; - } - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - break; - } - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_ITR0: - case TIM_TS_ITR1: - case TIM_TS_ITR2: - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } - - default: - break; - } - return HAL_OK; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) -{ - uint32_t tmpsmcr; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -static void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. - * @retval None - */ -static void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param htim pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -void TIM_ResetCallback(TIM_HandleTypeDef *htim) -{ - /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c deleted file mode 100644 index 5fb13e7..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_tim_ex.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Master and Slave synchronization configuration - * + Time OCRef clear configuration - * + Timer remapping capabilities configuration - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Change the handler state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * - * For TIM2, the parameter can have the following values:(see note) - * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC - * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO - * - * For TIM3, the parameter can have the following values:(see note) - * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC - * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO - * - * For TIM9, the parameter is a combination of 2 fields (field1 | field2): - * - * field1 can have the following values:(see note) - * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO - * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O - * - * field2 can have the following values: - * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO - * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock - * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO - * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO - * - * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values:(see note) - * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP - * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI - * - * field2 can have the following values:(see note) - * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock - * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO - * - * field3 can have the following values: - * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO - * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock - * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock - * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt - * - * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): - * - * field1 can have the following values:(see note) - * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP - * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI - * - * field2 can have the following values:(see note) - * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock - * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO - * - * field3 can have the following values: - * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO - * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock - * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock - * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO - * - * @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - __HAL_LOCK(htim); - - /* Check parameters */ - assert_param(IS_TIM_REMAP(htim->Instance, Remap)); - - /* Set the Timer remapping configuration */ - WRITE_REG(htim->Instance->OR, Remap); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c b/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c deleted file mode 100644 index f2c14d2..0000000 --- a/RTC/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_uart.c +++ /dev/null @@ -1,3121 +0,0 @@ -/** - ****************************************************************************** - * @file stm32l1xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (##) Enable the USARTx interface clock. - (##) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input). - (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required - Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle - (used for last byte sending completion detection in DMA non circular mode) - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) in the huart Init structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API. - - (#) For the Multi-Processor mode, initialize the UART registers by calling - the HAL_MultiProcessor_Init() API. - - [..] - (@) The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit - and receive process. - - [..] - (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the - low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized - HAL_UART_MspInit() API. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - - [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. - - [..] - When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak (surcharged) callbacks are used. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_UART_Transmit() - (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback - (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback - (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxCpltCallback - (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_UART_ErrorCallback - (+) Pause the DMA Transfer using HAL_UART_DMAPause() - (+) Resume the DMA Transfer using HAL_UART_DMAResume() - (+) Stop the DMA Transfer using HAL_UART_DMAStop() - - *** UART HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in UART HAL driver. - - (+) __HAL_UART_ENABLE: Enable the UART peripheral - (+) __HAL_UART_DISABLE: Disable the UART peripheral - (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not - (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag - (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt - (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt - (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not - - [..] - (@) You can refer to the UART HAL driver header file for more useful macros - - @endverbatim - [..] - (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible UART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | UART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32l1xx_hal.h" - -/** @addtogroup STM32L1xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup UART_Private_Constants - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -static void UART_SetConfig(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - please refer to Reference manual for possible UART frame formats. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs - follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration - procedures (details for the procedures are available in reference manual (RM0038)). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the UART mode according to the specified parameters in - * the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* The hardware flow control is available only for USART1, USART2 and USART3 */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - } - else - { - assert_param(IS_UART_INSTANCE(huart->Instance)); - } - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state*/ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the LIN mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection - * @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In LIN mode, the following bits must be kept cleared: - - CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL); - SET_BIT(huart->Instance->CR2, BreakDetectLength); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state*/ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the Multi-Processor mode according to the specified - * parameters in the UART_InitTypeDef and create the associated handle. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param Address USART address - * @param WakeUpMethod specifies the USART wake-up method. - * This parameter can be one of the following values: - * @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection - * @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance)); - - /* Check the Address & wake up method parameters */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - assert_param(IS_UART_ADDRESS(Address)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the UART Communication parameters */ - UART_SetConfig(huart); - - /* In Multi-Processor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - /* Set the USART address node */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD); - SET_BIT(huart->Instance->CR2, Address); - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE); - SET_BIT(huart->Instance->CR1, WakeUpMethod); - - /* Enable the peripheral */ - __HAL_UART_ENABLE(huart); - - /* Initialize the UART state */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the UART peripheral. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - if (huart->MspDeInitCallback == NULL) - { - huart->MspDeInitCallback = HAL_UART_MspDeInit; - } - /* DeInit the low level hardware */ - huart->MspDeInitCallback(huart); -#else - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief UART MSP Init. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspInit could be implemented in the user file - */ -} - -/** - * @brief UART MSP DeInit. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User UART Callback - * To be used instead of the weak predefined callback - * @param huart uart handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_READY) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = pCallback; - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = pCallback; - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = pCallback; - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = pCallback; - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = pCallback; - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = pCallback; - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (huart->gState == HAL_UART_STATE_RESET) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @param huart uart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(huart); - - if (HAL_UART_STATE_READY == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_UART_STATE_RESET == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; - break; - - default : - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(huart); - - return status; -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit and Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two modes of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, these API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected. - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type, - and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Sends an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t *tmp; - uint32_t tickstart = 0U; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout managment */ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - while (huart->TxXferCount > 0U) - { - huart->TxXferCount--; - if (huart->Init.WordLength == UART_WORDLENGTH_9B) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t *) pData; - huart->Instance->DR = (*tmp & (uint16_t)0x01FF); - if (huart->Init.Parity == UART_PARITY_NONE) - { - pData += 2U; - } - else - { - pData += 1U; - } - } - else - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - huart->Instance->DR = (*pData++ & (uint8_t)0xFF); - } - } - - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint16_t *tmp; - uint32_t tickstart = 0U; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Init tickstart for timeout managment */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Check the remain data to be received */ - while (huart->RxXferCount > 0U) - { - huart->RxXferCount--; - if (huart->Init.WordLength == UART_WORDLENGTH_9B) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - tmp = (uint16_t *) pData; - if (huart->Init.Parity == UART_PARITY_NONE) - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - pData += 2U; - } - else - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - pData += 1U; - } - - } - else - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (huart->Init.Parity == UART_PARITY_NONE) - { - *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - - } - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Transmit data register empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in non blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); - - /* Enable the UART Data Register not empty Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sends an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); - - /* Clear the TC flag in the SR register by writing 0 to it */ - __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @note When the UART parity is enabled (PCE = 1) the received data contains the parity bit. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - uint32_t *tmp; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size); - - /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ - __HAL_UART_CLEAR_OREFLAG(huart); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pauses the DMA Transfer. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - uint32_t dmarequest = 0x00U; - - /* Process Locked */ - __HAL_LOCK(huart); - - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) - { - /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) - { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Resumes the DMA Transfer. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_UART_CLEAR_OREFLAG(huart); - - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Stops the DMA Transfer. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - uint32_t dmarequest = 0x00U; - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() - */ - - /* Stop UART DMA Tx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if (huart->hdmatx != NULL) - { - HAL_DMA_Abort(huart->hdmatx); - } - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - HAL_DMA_Abort(huart->hdmarx); - } - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel: use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel: use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->RxState and huart->gState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t AbortCplt = 0x01U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - AbortCplt = 0x00U; - } - } - } - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - AbortCplt = 0x01U; - } - else - { - AbortCplt = 0x00U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (AbortCplt == 0x01U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status -*/ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief This function handles UART interrupt request. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->SR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - uint32_t errorflags = 0x00U; - uint32_t dmarequest = 0x00U; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE)); - if (errorflags == RESET) - { - /* UART in mode Receiver -------------------------------------------------*/ - if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - UART_Receive_IT(huart); - return; - } - } - - /* If some errors occur */ - if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) - { - /* UART parity error interrupt occurred ----------------------------------*/ - if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART noise error interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART frame error interrupt occurred -----------------------------------*/ - if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET)) - { - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) - { - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* Call UART Error Call back function if need be --------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver -----------------------------------------------*/ - if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET)) - { - UART_Receive_IT(huart); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - } /* End if some error occurs */ - - /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET)) - { - UART_Transmit_IT(huart); - return; - } - - /* UART in mode Transmitter end --------------------------------------------*/ - if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET)) - { - UART_EndTransmit_IT(huart); - return; - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief UART error callbacks. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART: - (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character. - (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. - (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software. - (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode - (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode - -@endverbatim - * @{ - */ - -/** - * @brief Transmits break characters. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - SET_BIT(huart->Instance->CR1, USART_CR1_SBK); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enters the UART in mute mode. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RWU); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Exits the UART mute mode: wake up software. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00U; - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_TE; - - /* Write to USART CR1 */ - WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg = 0x00U; - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /*-------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = huart->Instance->CR1; - - /* Clear TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - tmpreg |= (uint32_t)USART_CR1_RE; - - /* Write to USART CR1 */ - WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief UART State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - UART communication process, return Peripheral Errors occurred during communication - process - (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral. - (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the UART state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) -{ - uint32_t temp1 = 0x00U, temp2 = 0x00U; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the UART error code - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code - */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Initialize the callbacks to their default values. - * @param huart UART handle. - * @retval none - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) -{ - /* Init the UART Callback settings */ - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @brief DMA UART transmit process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* DMA Normal mode*/ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - huart->TxXferCount = 0x00U; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - } - /* DMA Circular mode */ - else - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART transmit process half complete callback - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxHalfCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* DMA Normal mode*/ - if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) - { - huart->RxXferCount = 0U; - - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - } -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART receive process half complete callback - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); -#else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART communication error callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - uint32_t dmarequest = 0x00U; - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Stop UART DMA Tx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); - if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) - { - huart->TxXferCount = 0x00U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); - if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) - { - huart->RxXferCount = 0x00U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief This function handles UART Communication Timeout. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param Flag specifies the UART flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0x00U; - huart->TxXferCount = 0x00U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmarx != NULL) - { - if (huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmatx != NULL) - { - if (huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0x00U; - huart->RxXferCount = 0x00U; - - /* Reset ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->TxXferCount = 0x00U; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->RxXferCount = 0x00U; - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief Sends an amount of data in non blocking mode. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->Init.WordLength == UART_WORDLENGTH_9B) - { - tmp = (uint16_t *) huart->pTxBuffPtr; - huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); - if (huart->Init.Parity == UART_PARITY_NONE) - { - huart->pTxBuffPtr += 2U; - } - else - { - huart->pTxBuffPtr += 1U; - } - } - else - { - huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF); - } - - if (--huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - - /* Enable the UART Transmit Complete Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_TC); - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Wraps up transmission in non blocking mode. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_TC); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - return HAL_OK; -} - -/** - * @brief Receives an amount of data in non blocking mode - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - if (huart->Init.WordLength == UART_WORDLENGTH_9B) - { - tmp = (uint16_t *) huart->pRxBuffPtr; - if (huart->Init.Parity == UART_PARITY_NONE) - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF); - huart->pRxBuffPtr += 2U; - } - else - { - *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF); - huart->pRxBuffPtr += 1U; - } - } - else - { - if (huart->Init.Parity == UART_PARITY_NONE) - { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } - } - - if (--huart->RxXferCount == 0U) - { - /* Disable the UART Data Register not empty Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE); - - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - return HAL_OK; - } - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configures the UART peripheral. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits - according to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the UART Word Length, Parity and mode: - Set the M bits according to huart->Init.WordLength value - Set PCE and PS bits according to huart->Init.Parity value - Set TE and RE bits according to huart->Init.Mode value - Set OVER8 bit according to huart->Init.OverSampling value */ - - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; - MODIFY_REG(huart->Instance->CR1, - (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), - tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ - MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - - - if((huart->Instance == USART1)) - { - pclk = HAL_RCC_GetPCLK2Freq(); - } - else - { - pclk = HAL_RCC_GetPCLK1Freq(); - } - - /*-------------------------- USART BRR Configuration ---------------------*/ - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); - } - else - { - huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - } -} - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTC/RTC Debug.launch b/RTC/RTC Debug.launch index dfb9496..5ce9486 100644 --- a/RTC/RTC Debug.launch +++ b/RTC/RTC Debug.launch @@ -29,7 +29,7 @@ - + @@ -61,7 +61,7 @@ - + diff --git a/RTC/RTC.ioc b/RTC/RTC.ioc index fbb6306..ec5f3a4 100644 --- a/RTC/RTC.ioc +++ b/RTC/RTC.ioc @@ -1,44 +1,46 @@ #MicroXplorer Configuration settings - do not modify File.Version=6 KeepUserPlacement=false -Mcu.Family=STM32L1 +Mcu.Family=STM32F4 Mcu.IP0=NVIC Mcu.IP1=RCC Mcu.IP2=RTC Mcu.IP3=SYS Mcu.IP4=USART2 Mcu.IPNb=5 -Mcu.Name=STM32L152RETx +Mcu.Name=STM32F401R(D-E)Tx Mcu.Package=LQFP64 -Mcu.Pin0=PC13-WKUP2 +Mcu.Pin0=PC13-ANTI_TAMP Mcu.Pin1=PC14-OSC32_IN Mcu.Pin10=PB3 Mcu.Pin11=VP_RTC_VS_RTC_Activate Mcu.Pin12=VP_RTC_VS_RTC_Calendar -Mcu.Pin13=VP_SYS_VS_Systick +Mcu.Pin13=VP_RTC_VS_RTC_Alarm_A_Intern +Mcu.Pin14=VP_SYS_VS_Systick Mcu.Pin2=PC15-OSC32_OUT -Mcu.Pin3=PH0-OSC_IN -Mcu.Pin4=PH1-OSC_OUT +Mcu.Pin3=PH0 - OSC_IN +Mcu.Pin4=PH1 - OSC_OUT Mcu.Pin5=PA2 Mcu.Pin6=PA3 Mcu.Pin7=PA5 Mcu.Pin8=PA13 Mcu.Pin9=PA14 -Mcu.PinsNb=14 +Mcu.PinsNb=15 Mcu.ThirdPartyNb=0 Mcu.UserConstants= -Mcu.UserName=STM32L152RETx -MxCube.Version=6.0.0 -MxDb.Version=DB.6.0.0 +Mcu.UserName=STM32F401RETx +MxCube.Version=6.1.1 +MxDb.Version=DB.6.0.10 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.ForceEnableDMAVector=true NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:true\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:true\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_0 -NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:true\:false +NVIC.RTC_Alarm_IRQn=true\:0\:0\:false\:false\:true\:true\:true +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false PA13.GPIOParameters=GPIO_Label @@ -51,39 +53,51 @@ PA14.GPIO_Label=TCK PA14.Locked=true PA14.Mode=Serial_Wire PA14.Signal=SYS_JTCK-SWCLK -PA2.GPIOParameters=GPIO_Label +PA2.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA2.GPIO_Label=USART_TX +PA2.GPIO_Mode=GPIO_MODE_AF_PP +PA2.GPIO_PuPd=GPIO_NOPULL +PA2.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA2.Locked=true PA2.Mode=Asynchronous PA2.Signal=USART2_TX -PA3.GPIOParameters=GPIO_Label +PA3.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA3.GPIO_Label=USART_RX +PA3.GPIO_Mode=GPIO_MODE_AF_PP +PA3.GPIO_PuPd=GPIO_NOPULL +PA3.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA3.Locked=true PA3.Mode=Asynchronous PA3.Signal=USART2_RX -PA5.GPIOParameters=GPIO_Label +PA5.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label,GPIO_Mode PA5.GPIO_Label=LD2 [Green Led] +PA5.GPIO_Mode=GPIO_MODE_OUTPUT_PP +PA5.GPIO_PuPd=GPIO_NOPULL +PA5.GPIO_Speed=GPIO_SPEED_FREQ_LOW PA5.Locked=true PA5.Signal=GPIO_Output PB3.GPIOParameters=GPIO_Label PB3.GPIO_Label=SWO PB3.Locked=true -PB3.Signal=SYS_JTDO-TRACESWO -PC13-WKUP2.GPIOParameters=GPIO_Label -PC13-WKUP2.GPIO_Label=B1 [Blue PushButton] -PC13-WKUP2.Locked=true -PC13-WKUP2.Signal=GPXTI13 +PB3.Signal=SYS_JTDO-SWO +PC13-ANTI_TAMP.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI +PC13-ANTI_TAMP.GPIO_Label=B1 [Blue PushButton] +PC13-ANTI_TAMP.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING +PC13-ANTI_TAMP.GPIO_PuPd=GPIO_NOPULL +PC13-ANTI_TAMP.Locked=true +PC13-ANTI_TAMP.Signal=GPXTI13 PC14-OSC32_IN.Locked=true PC14-OSC32_IN.Mode=LSE-External-Oscillator PC14-OSC32_IN.Signal=RCC_OSC32_IN PC15-OSC32_OUT.Locked=true PC15-OSC32_OUT.Mode=LSE-External-Oscillator PC15-OSC32_OUT.Signal=RCC_OSC32_OUT -PH0-OSC_IN.Locked=true -PH0-OSC_IN.Mode=HSE-External-Clock-Source -PH0-OSC_IN.Signal=RCC_OSC_IN -PH1-OSC_OUT.Locked=true -PH1-OSC_OUT.Signal=RCC_OSC_OUT +PH0\ -\ OSC_IN.Locked=true +PH0\ -\ OSC_IN.Mode=HSE-External-Clock-Source +PH0\ -\ OSC_IN.Signal=RCC_OSC_IN +PH1\ -\ OSC_OUT.Locked=true +PH1\ -\ OSC_OUT.Mode=HSE-External-Clock-Source +PH1\ -\ OSC_OUT.Signal=RCC_OSC_OUT PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false @@ -93,8 +107,8 @@ ProjectManager.CoupleFile=false ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32L152RETx -ProjectManager.FirmwarePackage=STM32Cube FW_L1 V1.10.2 +ProjectManager.DeviceId=STM32F401RETx +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.2 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -112,55 +126,53 @@ ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=STM32CubeIDE ProjectManager.ToolChainLocation= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_RTC_Init-RTC-false-HAL-true RCC.48MHZClocksFreq_Value=48000000 -RCC.AHBFreq_Value=32000000 -RCC.APB1Freq_Value=32000000 -RCC.APB1TimFreq_Value=32000000 -RCC.APB2Freq_Value=32000000 -RCC.APB2TimFreq_Value=32000000 -RCC.FCLKCortexFreq_Value=32000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=32000000 +RCC.AHBFreq_Value=84000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV2 +RCC.APB1Freq_Value=42000000 +RCC.APB1TimFreq_Value=84000000 +RCC.APB2Freq_Value=84000000 +RCC.APB2TimFreq_Value=84000000 +RCC.CortexFreq_Value=84000000 +RCC.FCLKCortexFreq_Value=84000000 +RCC.HCLKFreq_Value=84000000 RCC.HSE_VALUE=8000000 RCC.HSI_VALUE=16000000 -RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,LCDFreq_Value,LSI_VALUE,MCOPinFreq_Value,MSI_VALUE,PLLCLKFreq_Value,PLLDIV,PLLMUL,PWRFreq_Value,RTCClockSelectionVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,TIMFreq_Value,TimerFreq_Value,USBOutput,VCOOutputFreq_Value -RCC.LCDFreq_Value=32768 -RCC.LSI_VALUE=37000 -RCC.MCOPinFreq_Value=32000000 -RCC.MSI_VALUE=2097000 -RCC.PLLCLKFreq_Value=32000000 -RCC.PLLDIV=RCC_PLL_DIV3 -RCC.PLLMUL=RCC_PLL_MUL6 -RCC.PWRFreq_Value=32000000 -RCC.RTCClockSelectionVirtual=RCC_RTCCLKSOURCE_LSE -RCC.RTCFreq_Value=32768 +RCC.I2SClocksFreq_Value=96000000 +RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,FCLKCortexFreq_Value,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLN,PLLP,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=84000000 +RCC.PLLCLKFreq_Value=84000000 +RCC.PLLN=336 +RCC.PLLP=RCC_PLLP_DIV4 +RCC.PLLQ=7 +RCC.PLLQCLKFreq_Value=48000000 +RCC.RTCFreq_Value=32000 RCC.RTCHSEDivFreq_Value=4000000 -RCC.SYSCLKFreq_VALUE=32000000 +RCC.SYSCLKFreq_VALUE=84000000 RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.TIMFreq_Value=32000000 -RCC.TimerFreq_Value=32000000 -RCC.USBOutput=48000000 -RCC.VCOOutputFreq_Value=96000000 -RTC.Date=31 -RTC.DayLightSaving=RTC_DAYLIGHTSAVING_NONE +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=336000000 +RCC.VcooutputI2S=96000000 +RTC.Alarm=RTC_ALARM_A +RTC.Date=8 RTC.Format=RTC_FORMAT_BIN -RTC.Hours=23 -RTC.IPParameters=Format,DayLightSaving,Hours,Minutes,Seconds,WeekDay,Month,Date -RTC.Minutes=59 -RTC.Month=RTC_MONTH_DECEMBER -RTC.Seconds=45 -RTC.WeekDay=RTC_WEEKDAY_SUNDAY +RTC.IPParameters=Format,Date,Year,Alarm +RTC.Year=21 SH.GPXTI13.0=GPIO_EXTI13 SH.GPXTI13.ConfNb=1 USART2.IPParameters=VirtualMode USART2.VirtualMode=VM_ASYNC VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate +VP_RTC_VS_RTC_Alarm_A_Intern.Mode=Alarm A +VP_RTC_VS_RTC_Alarm_A_Intern.Signal=RTC_VS_RTC_Alarm_A_Intern VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=NUCLEO-L152RE +board=NUCLEO-F401RE boardIOC=true isbadioc=false diff --git a/RTC/STM32L152RETX_FLASH.ld b/RTC/STM32L152RETX_FLASH.ld deleted file mode 100644 index 200fc56..0000000 --- a/RTC/STM32L152RETX_FLASH.ld +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file LinkerScript.ld - * @author Auto-generated by STM32CubeIDE - * Abstract : Linker script for NUCLEO-L152RE Board embedding STM32L152RETx Device from stm32l1 series - * 512Kbytes FLASH - * 80Kbytes RAM - * - * Set heap size, stack size and stack location according - * to application requirements. - * - * Set memory bank area and size if external memory is used - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200 ; /* required amount of heap */ -_Min_Stack_Size = 0x400 ; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "FLASH" Rom type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >FLASH - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/RTC/STM32L152RETX_RAM.ld b/RTC/STM32L152RETX_RAM.ld deleted file mode 100644 index db524fb..0000000 --- a/RTC/STM32L152RETX_RAM.ld +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file LinkerScript.ld - * @author Auto-generated by STM32CubeIDE - * Abstract : Linker script for NUCLEO-L152RE Board embedding STM32L152RETx Device from stm32l1 series - * 512Kbytes FLASH - * 80Kbytes RAM - * - * Set heap size, stack size and stack location according - * to application requirements. - * - * Set memory bank area and size if external memory is used - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2020 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Entry Point */ -ENTRY(Reset_Handler) - -/* Highest address of the user mode stack */ -_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ - -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - -/* Memories definition */ -MEMORY -{ - RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 80K - FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K -} - -/* Sections */ -SECTIONS -{ - /* The startup code into "RAM" Ram type memory */ - .isr_vector : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - } >RAM - - /* The program code and other data into "RAM" Ram type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >RAM - - /* Constant data into "RAM" Ram type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >RAM - - .ARM.extab : { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >RAM - - .ARM : { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >RAM - - .preinit_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >RAM - - .init_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >RAM - - .fini_array : - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >RAM - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -}