@@ -0,0 +1,486 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_conf_template.h | |||
* @author MCD Application Team | |||
* @brief HAL configuration template file. | |||
* This file should be copied to the application folder and renamed | |||
* to stm32f4xx_hal_conf.h. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_CONF_H | |||
#define __STM32F4xx_HAL_CONF_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Exported types ------------------------------------------------------------*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/* ########################## Module Selection ############################## */ | |||
/** | |||
* @brief This is the list of modules to be used in the HAL driver | |||
*/ | |||
#define HAL_MODULE_ENABLED | |||
/* #define HAL_ADC_MODULE_ENABLED */ | |||
/* #define HAL_CRYP_MODULE_ENABLED */ | |||
/* #define HAL_CAN_MODULE_ENABLED */ | |||
/* #define HAL_CRC_MODULE_ENABLED */ | |||
/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ | |||
/* #define HAL_CRYP_MODULE_ENABLED */ | |||
/* #define HAL_DAC_MODULE_ENABLED */ | |||
/* #define HAL_DCMI_MODULE_ENABLED */ | |||
/* #define HAL_DMA2D_MODULE_ENABLED */ | |||
/* #define HAL_ETH_MODULE_ENABLED */ | |||
/* #define HAL_NAND_MODULE_ENABLED */ | |||
/* #define HAL_NOR_MODULE_ENABLED */ | |||
/* #define HAL_PCCARD_MODULE_ENABLED */ | |||
/* #define HAL_SRAM_MODULE_ENABLED */ | |||
/* #define HAL_SDRAM_MODULE_ENABLED */ | |||
/* #define HAL_HASH_MODULE_ENABLED */ | |||
/* #define HAL_I2C_MODULE_ENABLED */ | |||
/* #define HAL_I2S_MODULE_ENABLED */ | |||
/* #define HAL_IWDG_MODULE_ENABLED */ | |||
/* #define HAL_LTDC_MODULE_ENABLED */ | |||
/* #define HAL_RNG_MODULE_ENABLED */ | |||
#define HAL_RTC_MODULE_ENABLED | |||
/* #define HAL_SAI_MODULE_ENABLED */ | |||
/* #define HAL_SD_MODULE_ENABLED */ | |||
/* #define HAL_MMC_MODULE_ENABLED */ | |||
/* #define HAL_SPI_MODULE_ENABLED */ | |||
/* #define HAL_TIM_MODULE_ENABLED */ | |||
#define HAL_UART_MODULE_ENABLED | |||
/* #define HAL_USART_MODULE_ENABLED */ | |||
/* #define HAL_IRDA_MODULE_ENABLED */ | |||
/* #define HAL_SMARTCARD_MODULE_ENABLED */ | |||
/* #define HAL_SMBUS_MODULE_ENABLED */ | |||
/* #define HAL_WWDG_MODULE_ENABLED */ | |||
/* #define HAL_PCD_MODULE_ENABLED */ | |||
/* #define HAL_HCD_MODULE_ENABLED */ | |||
/* #define HAL_DSI_MODULE_ENABLED */ | |||
/* #define HAL_QSPI_MODULE_ENABLED */ | |||
/* #define HAL_QSPI_MODULE_ENABLED */ | |||
/* #define HAL_CEC_MODULE_ENABLED */ | |||
/* #define HAL_FMPI2C_MODULE_ENABLED */ | |||
/* #define HAL_SPDIFRX_MODULE_ENABLED */ | |||
/* #define HAL_DFSDM_MODULE_ENABLED */ | |||
/* #define HAL_LPTIM_MODULE_ENABLED */ | |||
#define HAL_GPIO_MODULE_ENABLED | |||
#define HAL_EXTI_MODULE_ENABLED | |||
#define HAL_DMA_MODULE_ENABLED | |||
#define HAL_RCC_MODULE_ENABLED | |||
#define HAL_FLASH_MODULE_ENABLED | |||
#define HAL_PWR_MODULE_ENABLED | |||
#define HAL_CORTEX_MODULE_ENABLED | |||
/* ########################## HSE/HSI Values adaptation ##################### */ | |||
/** | |||
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application. | |||
* This value is used by the RCC HAL module to compute the system frequency | |||
* (when HSE is used as system clock source, directly or through the PLL). | |||
*/ | |||
#if !defined (HSE_VALUE) | |||
#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ | |||
#endif /* HSE_VALUE */ | |||
#if !defined (HSE_STARTUP_TIMEOUT) | |||
#define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ | |||
#endif /* HSE_STARTUP_TIMEOUT */ | |||
/** | |||
* @brief Internal High Speed oscillator (HSI) value. | |||
* This value is used by the RCC HAL module to compute the system frequency | |||
* (when HSI is used as system clock source, directly or through the PLL). | |||
*/ | |||
#if !defined (HSI_VALUE) | |||
#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ | |||
#endif /* HSI_VALUE */ | |||
/** | |||
* @brief Internal Low Speed oscillator (LSI) value. | |||
*/ | |||
#if !defined (LSI_VALUE) | |||
#define LSI_VALUE ((uint32_t)32000U) /*!< LSI Typical Value in Hz*/ | |||
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz | |||
The real value may vary depending on the variations | |||
in voltage and temperature.*/ | |||
/** | |||
* @brief External Low Speed oscillator (LSE) value. | |||
*/ | |||
#if !defined (LSE_VALUE) | |||
#define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External Low Speed oscillator in Hz */ | |||
#endif /* LSE_VALUE */ | |||
#if !defined (LSE_STARTUP_TIMEOUT) | |||
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ | |||
#endif /* LSE_STARTUP_TIMEOUT */ | |||
/** | |||
* @brief External clock source for I2S peripheral | |||
* This value is used by the I2S HAL module to compute the I2S clock source | |||
* frequency, this source is inserted directly through I2S_CKIN pad. | |||
*/ | |||
#if !defined (EXTERNAL_CLOCK_VALUE) | |||
#define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/ | |||
#endif /* EXTERNAL_CLOCK_VALUE */ | |||
/* Tip: To avoid modifying this file each time you need to use different HSE, | |||
=== you can define the HSE value in your toolchain compiler preprocessor. */ | |||
/* ########################### System Configuration ######################### */ | |||
/** | |||
* @brief This is the HAL system configuration section | |||
*/ | |||
#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ | |||
#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */ | |||
#define USE_RTOS 0U | |||
#define PREFETCH_ENABLE 1U | |||
#define INSTRUCTION_CACHE_ENABLE 1U | |||
#define DATA_CACHE_ENABLE 1U | |||
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ | |||
#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ | |||
#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ | |||
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ | |||
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ | |||
#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ | |||
#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ | |||
#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ | |||
#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ | |||
#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ | |||
#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ | |||
#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ | |||
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ | |||
#define USE_HAL_FMPI2C_REGISTER_CALLBACKS 0U /* FMPI2C register callback disabled */ | |||
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ | |||
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ | |||
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ | |||
#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ | |||
#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ | |||
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ | |||
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ | |||
#define USE_HAL_PCCARD_REGISTER_CALLBACKS 0U /* PCCARD register callback disabled */ | |||
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ | |||
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ | |||
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ | |||
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ | |||
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ | |||
#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ | |||
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ | |||
#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ | |||
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ | |||
#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ | |||
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ | |||
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ | |||
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ | |||
#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ | |||
#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ | |||
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ | |||
/* ########################## Assert Selection ############################## */ | |||
/** | |||
* @brief Uncomment the line below to expanse the "assert_param" macro in the | |||
* HAL drivers code | |||
*/ | |||
/* #define USE_FULL_ASSERT 1U */ | |||
/* ################## Ethernet peripheral configuration ##################### */ | |||
/* Section 1 : Ethernet peripheral configuration */ | |||
/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ | |||
#define MAC_ADDR0 2U | |||
#define MAC_ADDR1 0U | |||
#define MAC_ADDR2 0U | |||
#define MAC_ADDR3 0U | |||
#define MAC_ADDR4 0U | |||
#define MAC_ADDR5 0U | |||
/* Definition of the Ethernet driver buffers size and count */ | |||
#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ | |||
#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ | |||
#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ | |||
#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ | |||
/* Section 2: PHY configuration section */ | |||
/* DP83848_PHY_ADDRESS Address*/ | |||
#define DP83848_PHY_ADDRESS 0x01U | |||
/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ | |||
#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) | |||
/* PHY Configuration delay */ | |||
#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) | |||
#define PHY_READ_TO ((uint32_t)0x0000FFFFU) | |||
#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) | |||
/* Section 3: Common PHY Registers */ | |||
#define PHY_BCR ((uint16_t)0x0000U) /*!< Transceiver Basic Control Register */ | |||
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */ | |||
#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ | |||
#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ | |||
#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ | |||
#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ | |||
#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ | |||
#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ | |||
#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ | |||
#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ | |||
#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ | |||
#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ | |||
#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ | |||
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ | |||
#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ | |||
/* Section 4: Extended PHY Registers */ | |||
#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ | |||
#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ | |||
#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ | |||
/* ################## SPI peripheral configuration ########################## */ | |||
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver | |||
* Activated: CRC code is present inside driver | |||
* Deactivated: CRC code cleaned from driver | |||
*/ | |||
#define USE_SPI_CRC 0U | |||
/* Includes ------------------------------------------------------------------*/ | |||
/** | |||
* @brief Include module's header file | |||
*/ | |||
#ifdef HAL_RCC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_rcc.h" | |||
#endif /* HAL_RCC_MODULE_ENABLED */ | |||
#ifdef HAL_GPIO_MODULE_ENABLED | |||
#include "stm32f4xx_hal_gpio.h" | |||
#endif /* HAL_GPIO_MODULE_ENABLED */ | |||
#ifdef HAL_EXTI_MODULE_ENABLED | |||
#include "stm32f4xx_hal_exti.h" | |||
#endif /* HAL_EXTI_MODULE_ENABLED */ | |||
#ifdef HAL_DMA_MODULE_ENABLED | |||
#include "stm32f4xx_hal_dma.h" | |||
#endif /* HAL_DMA_MODULE_ENABLED */ | |||
#ifdef HAL_CORTEX_MODULE_ENABLED | |||
#include "stm32f4xx_hal_cortex.h" | |||
#endif /* HAL_CORTEX_MODULE_ENABLED */ | |||
#ifdef HAL_ADC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_adc.h" | |||
#endif /* HAL_ADC_MODULE_ENABLED */ | |||
#ifdef HAL_CAN_MODULE_ENABLED | |||
#include "stm32f4xx_hal_can.h" | |||
#endif /* HAL_CAN_MODULE_ENABLED */ | |||
#ifdef HAL_CAN_LEGACY_MODULE_ENABLED | |||
#include "stm32f4xx_hal_can_legacy.h" | |||
#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ | |||
#ifdef HAL_CRC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_crc.h" | |||
#endif /* HAL_CRC_MODULE_ENABLED */ | |||
#ifdef HAL_CRYP_MODULE_ENABLED | |||
#include "stm32f4xx_hal_cryp.h" | |||
#endif /* HAL_CRYP_MODULE_ENABLED */ | |||
#ifdef HAL_DMA2D_MODULE_ENABLED | |||
#include "stm32f4xx_hal_dma2d.h" | |||
#endif /* HAL_DMA2D_MODULE_ENABLED */ | |||
#ifdef HAL_DAC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_dac.h" | |||
#endif /* HAL_DAC_MODULE_ENABLED */ | |||
#ifdef HAL_DCMI_MODULE_ENABLED | |||
#include "stm32f4xx_hal_dcmi.h" | |||
#endif /* HAL_DCMI_MODULE_ENABLED */ | |||
#ifdef HAL_ETH_MODULE_ENABLED | |||
#include "stm32f4xx_hal_eth.h" | |||
#endif /* HAL_ETH_MODULE_ENABLED */ | |||
#ifdef HAL_FLASH_MODULE_ENABLED | |||
#include "stm32f4xx_hal_flash.h" | |||
#endif /* HAL_FLASH_MODULE_ENABLED */ | |||
#ifdef HAL_SRAM_MODULE_ENABLED | |||
#include "stm32f4xx_hal_sram.h" | |||
#endif /* HAL_SRAM_MODULE_ENABLED */ | |||
#ifdef HAL_NOR_MODULE_ENABLED | |||
#include "stm32f4xx_hal_nor.h" | |||
#endif /* HAL_NOR_MODULE_ENABLED */ | |||
#ifdef HAL_NAND_MODULE_ENABLED | |||
#include "stm32f4xx_hal_nand.h" | |||
#endif /* HAL_NAND_MODULE_ENABLED */ | |||
#ifdef HAL_PCCARD_MODULE_ENABLED | |||
#include "stm32f4xx_hal_pccard.h" | |||
#endif /* HAL_PCCARD_MODULE_ENABLED */ | |||
#ifdef HAL_SDRAM_MODULE_ENABLED | |||
#include "stm32f4xx_hal_sdram.h" | |||
#endif /* HAL_SDRAM_MODULE_ENABLED */ | |||
#ifdef HAL_HASH_MODULE_ENABLED | |||
#include "stm32f4xx_hal_hash.h" | |||
#endif /* HAL_HASH_MODULE_ENABLED */ | |||
#ifdef HAL_I2C_MODULE_ENABLED | |||
#include "stm32f4xx_hal_i2c.h" | |||
#endif /* HAL_I2C_MODULE_ENABLED */ | |||
#ifdef HAL_SMBUS_MODULE_ENABLED | |||
#include "stm32f4xx_hal_smbus.h" | |||
#endif /* HAL_SMBUS_MODULE_ENABLED */ | |||
#ifdef HAL_I2S_MODULE_ENABLED | |||
#include "stm32f4xx_hal_i2s.h" | |||
#endif /* HAL_I2S_MODULE_ENABLED */ | |||
#ifdef HAL_IWDG_MODULE_ENABLED | |||
#include "stm32f4xx_hal_iwdg.h" | |||
#endif /* HAL_IWDG_MODULE_ENABLED */ | |||
#ifdef HAL_LTDC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_ltdc.h" | |||
#endif /* HAL_LTDC_MODULE_ENABLED */ | |||
#ifdef HAL_PWR_MODULE_ENABLED | |||
#include "stm32f4xx_hal_pwr.h" | |||
#endif /* HAL_PWR_MODULE_ENABLED */ | |||
#ifdef HAL_RNG_MODULE_ENABLED | |||
#include "stm32f4xx_hal_rng.h" | |||
#endif /* HAL_RNG_MODULE_ENABLED */ | |||
#ifdef HAL_RTC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_rtc.h" | |||
#endif /* HAL_RTC_MODULE_ENABLED */ | |||
#ifdef HAL_SAI_MODULE_ENABLED | |||
#include "stm32f4xx_hal_sai.h" | |||
#endif /* HAL_SAI_MODULE_ENABLED */ | |||
#ifdef HAL_SD_MODULE_ENABLED | |||
#include "stm32f4xx_hal_sd.h" | |||
#endif /* HAL_SD_MODULE_ENABLED */ | |||
#ifdef HAL_SPI_MODULE_ENABLED | |||
#include "stm32f4xx_hal_spi.h" | |||
#endif /* HAL_SPI_MODULE_ENABLED */ | |||
#ifdef HAL_TIM_MODULE_ENABLED | |||
#include "stm32f4xx_hal_tim.h" | |||
#endif /* HAL_TIM_MODULE_ENABLED */ | |||
#ifdef HAL_UART_MODULE_ENABLED | |||
#include "stm32f4xx_hal_uart.h" | |||
#endif /* HAL_UART_MODULE_ENABLED */ | |||
#ifdef HAL_USART_MODULE_ENABLED | |||
#include "stm32f4xx_hal_usart.h" | |||
#endif /* HAL_USART_MODULE_ENABLED */ | |||
#ifdef HAL_IRDA_MODULE_ENABLED | |||
#include "stm32f4xx_hal_irda.h" | |||
#endif /* HAL_IRDA_MODULE_ENABLED */ | |||
#ifdef HAL_SMARTCARD_MODULE_ENABLED | |||
#include "stm32f4xx_hal_smartcard.h" | |||
#endif /* HAL_SMARTCARD_MODULE_ENABLED */ | |||
#ifdef HAL_WWDG_MODULE_ENABLED | |||
#include "stm32f4xx_hal_wwdg.h" | |||
#endif /* HAL_WWDG_MODULE_ENABLED */ | |||
#ifdef HAL_PCD_MODULE_ENABLED | |||
#include "stm32f4xx_hal_pcd.h" | |||
#endif /* HAL_PCD_MODULE_ENABLED */ | |||
#ifdef HAL_HCD_MODULE_ENABLED | |||
#include "stm32f4xx_hal_hcd.h" | |||
#endif /* HAL_HCD_MODULE_ENABLED */ | |||
#ifdef HAL_DSI_MODULE_ENABLED | |||
#include "stm32f4xx_hal_dsi.h" | |||
#endif /* HAL_DSI_MODULE_ENABLED */ | |||
#ifdef HAL_QSPI_MODULE_ENABLED | |||
#include "stm32f4xx_hal_qspi.h" | |||
#endif /* HAL_QSPI_MODULE_ENABLED */ | |||
#ifdef HAL_CEC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_cec.h" | |||
#endif /* HAL_CEC_MODULE_ENABLED */ | |||
#ifdef HAL_FMPI2C_MODULE_ENABLED | |||
#include "stm32f4xx_hal_fmpi2c.h" | |||
#endif /* HAL_FMPI2C_MODULE_ENABLED */ | |||
#ifdef HAL_SPDIFRX_MODULE_ENABLED | |||
#include "stm32f4xx_hal_spdifrx.h" | |||
#endif /* HAL_SPDIFRX_MODULE_ENABLED */ | |||
#ifdef HAL_DFSDM_MODULE_ENABLED | |||
#include "stm32f4xx_hal_dfsdm.h" | |||
#endif /* HAL_DFSDM_MODULE_ENABLED */ | |||
#ifdef HAL_LPTIM_MODULE_ENABLED | |||
#include "stm32f4xx_hal_lptim.h" | |||
#endif /* HAL_LPTIM_MODULE_ENABLED */ | |||
#ifdef HAL_MMC_MODULE_ENABLED | |||
#include "stm32f4xx_hal_mmc.h" | |||
#endif /* HAL_MMC_MODULE_ENABLED */ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
#ifdef USE_FULL_ASSERT | |||
/** | |||
* @brief The assert_param macro is used for function's parameters check. | |||
* @param expr If expr is false, it calls assert_failed function | |||
* which reports the name of the source file and the source | |||
* line number of the call that failed. | |||
* If expr is true, it returns no value. | |||
* @retval None | |||
*/ | |||
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) | |||
/* Exported functions ------------------------------------------------------- */ | |||
void assert_failed(uint8_t* file, uint32_t line); | |||
#else | |||
#define assert_param(expr) ((void)0U) | |||
#endif /* USE_FULL_ASSERT */ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_CONF_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,70 @@ | |||
/* USER CODE BEGIN Header */ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_it.h | |||
* @brief This file contains the headers of the interrupt handlers. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2021 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* USER CODE END Header */ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_IT_H | |||
#define __STM32F4xx_IT_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Private includes ----------------------------------------------------------*/ | |||
/* USER CODE BEGIN Includes */ | |||
/* USER CODE END Includes */ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/* USER CODE BEGIN ET */ | |||
/* USER CODE END ET */ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/* USER CODE BEGIN EC */ | |||
/* USER CODE END EC */ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/* USER CODE BEGIN EM */ | |||
/* USER CODE END EM */ | |||
/* Exported functions prototypes ---------------------------------------------*/ | |||
void NMI_Handler(void); | |||
void HardFault_Handler(void); | |||
void MemManage_Handler(void); | |||
void BusFault_Handler(void); | |||
void UsageFault_Handler(void); | |||
void SVC_Handler(void); | |||
void DebugMon_Handler(void); | |||
void PendSV_Handler(void); | |||
void SysTick_Handler(void); | |||
void RTC_Alarm_IRQHandler(void); | |||
/* USER CODE BEGIN EFP */ | |||
/* USER CODE END EFP */ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_IT_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,201 @@ | |||
/* USER CODE BEGIN Header */ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_msp.c | |||
* @brief This file provides code for the MSP Initialization | |||
* and de-Initialization codes. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2021 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* USER CODE END Header */ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "main.h" | |||
/* USER CODE BEGIN Includes */ | |||
/* USER CODE END Includes */ | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* USER CODE BEGIN TD */ | |||
/* USER CODE END TD */ | |||
/* Private define ------------------------------------------------------------*/ | |||
/* USER CODE BEGIN Define */ | |||
/* USER CODE END Define */ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* USER CODE BEGIN Macro */ | |||
/* USER CODE END Macro */ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* USER CODE BEGIN PV */ | |||
/* USER CODE END PV */ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* USER CODE BEGIN PFP */ | |||
/* USER CODE END PFP */ | |||
/* External functions --------------------------------------------------------*/ | |||
/* USER CODE BEGIN ExternalFunctions */ | |||
/* USER CODE END ExternalFunctions */ | |||
/* USER CODE BEGIN 0 */ | |||
/* USER CODE END 0 */ | |||
/** | |||
* Initializes the Global MSP. | |||
*/ | |||
void HAL_MspInit(void) | |||
{ | |||
/* USER CODE BEGIN MspInit 0 */ | |||
/* USER CODE END MspInit 0 */ | |||
__HAL_RCC_SYSCFG_CLK_ENABLE(); | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0); | |||
/* System interrupt init*/ | |||
/* USER CODE BEGIN MspInit 1 */ | |||
/* USER CODE END MspInit 1 */ | |||
} | |||
/** | |||
* @brief RTC MSP Initialization | |||
* This function configures the hardware resources used in this example | |||
* @param hrtc: RTC handle pointer | |||
* @retval None | |||
*/ | |||
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) | |||
{ | |||
if(hrtc->Instance==RTC) | |||
{ | |||
/* USER CODE BEGIN RTC_MspInit 0 */ | |||
/* USER CODE END RTC_MspInit 0 */ | |||
/* Peripheral clock enable */ | |||
__HAL_RCC_RTC_ENABLE(); | |||
/* RTC interrupt Init */ | |||
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, 0, 0); | |||
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); | |||
/* USER CODE BEGIN RTC_MspInit 1 */ | |||
/* USER CODE END RTC_MspInit 1 */ | |||
} | |||
} | |||
/** | |||
* @brief RTC MSP De-Initialization | |||
* This function freeze the hardware resources used in this example | |||
* @param hrtc: RTC handle pointer | |||
* @retval None | |||
*/ | |||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) | |||
{ | |||
if(hrtc->Instance==RTC) | |||
{ | |||
/* USER CODE BEGIN RTC_MspDeInit 0 */ | |||
/* USER CODE END RTC_MspDeInit 0 */ | |||
/* Peripheral clock disable */ | |||
__HAL_RCC_RTC_DISABLE(); | |||
/* RTC interrupt DeInit */ | |||
HAL_NVIC_DisableIRQ(RTC_Alarm_IRQn); | |||
/* USER CODE BEGIN RTC_MspDeInit 1 */ | |||
/* USER CODE END RTC_MspDeInit 1 */ | |||
} | |||
} | |||
/** | |||
* @brief UART MSP Initialization | |||
* This function configures the hardware resources used in this example | |||
* @param huart: UART handle pointer | |||
* @retval None | |||
*/ | |||
void HAL_UART_MspInit(UART_HandleTypeDef* huart) | |||
{ | |||
GPIO_InitTypeDef GPIO_InitStruct = {0}; | |||
if(huart->Instance==USART2) | |||
{ | |||
/* USER CODE BEGIN USART2_MspInit 0 */ | |||
/* USER CODE END USART2_MspInit 0 */ | |||
/* Peripheral clock enable */ | |||
__HAL_RCC_USART2_CLK_ENABLE(); | |||
__HAL_RCC_GPIOA_CLK_ENABLE(); | |||
/**USART2 GPIO Configuration | |||
PA2 ------> USART2_TX | |||
PA3 ------> USART2_RX | |||
*/ | |||
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; | |||
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; | |||
GPIO_InitStruct.Pull = GPIO_NOPULL; | |||
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; | |||
GPIO_InitStruct.Alternate = GPIO_AF7_USART2; | |||
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); | |||
/* USER CODE BEGIN USART2_MspInit 1 */ | |||
/* USER CODE END USART2_MspInit 1 */ | |||
} | |||
} | |||
/** | |||
* @brief UART MSP De-Initialization | |||
* This function freeze the hardware resources used in this example | |||
* @param huart: UART handle pointer | |||
* @retval None | |||
*/ | |||
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) | |||
{ | |||
if(huart->Instance==USART2) | |||
{ | |||
/* USER CODE BEGIN USART2_MspDeInit 0 */ | |||
/* USER CODE END USART2_MspDeInit 0 */ | |||
/* Peripheral clock disable */ | |||
__HAL_RCC_USART2_CLK_DISABLE(); | |||
/**USART2 GPIO Configuration | |||
PA2 ------> USART2_TX | |||
PA3 ------> USART2_RX | |||
*/ | |||
HAL_GPIO_DeInit(GPIOA, USART_TX_Pin|USART_RX_Pin); | |||
/* USER CODE BEGIN USART2_MspDeInit 1 */ | |||
/* USER CODE END USART2_MspDeInit 1 */ | |||
} | |||
} | |||
/* USER CODE BEGIN 1 */ | |||
/* USER CODE END 1 */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,219 @@ | |||
/* USER CODE BEGIN Header */ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_it.c | |||
* @brief Interrupt Service Routines. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2021 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* USER CODE END Header */ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "main.h" | |||
#include "stm32f4xx_it.h" | |||
/* Private includes ----------------------------------------------------------*/ | |||
/* USER CODE BEGIN Includes */ | |||
/* USER CODE END Includes */ | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* USER CODE BEGIN TD */ | |||
/* USER CODE END TD */ | |||
/* Private define ------------------------------------------------------------*/ | |||
/* USER CODE BEGIN PD */ | |||
/* USER CODE END PD */ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* USER CODE BEGIN PM */ | |||
/* USER CODE END PM */ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* USER CODE BEGIN PV */ | |||
/* USER CODE END PV */ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* USER CODE BEGIN PFP */ | |||
/* USER CODE END PFP */ | |||
/* Private user code ---------------------------------------------------------*/ | |||
/* USER CODE BEGIN 0 */ | |||
/* USER CODE END 0 */ | |||
/* External variables --------------------------------------------------------*/ | |||
extern RTC_HandleTypeDef hrtc; | |||
/* USER CODE BEGIN EV */ | |||
/* USER CODE END EV */ | |||
/******************************************************************************/ | |||
/* Cortex-M4 Processor Interruption and Exception Handlers */ | |||
/******************************************************************************/ | |||
/** | |||
* @brief This function handles Non maskable interrupt. | |||
*/ | |||
void NMI_Handler(void) | |||
{ | |||
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */ | |||
/* USER CODE END NonMaskableInt_IRQn 0 */ | |||
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */ | |||
while (1) | |||
{ | |||
} | |||
/* USER CODE END NonMaskableInt_IRQn 1 */ | |||
} | |||
/** | |||
* @brief This function handles Hard fault interrupt. | |||
*/ | |||
void HardFault_Handler(void) | |||
{ | |||
/* USER CODE BEGIN HardFault_IRQn 0 */ | |||
/* USER CODE END HardFault_IRQn 0 */ | |||
while (1) | |||
{ | |||
/* USER CODE BEGIN W1_HardFault_IRQn 0 */ | |||
/* USER CODE END W1_HardFault_IRQn 0 */ | |||
} | |||
} | |||
/** | |||
* @brief This function handles Memory management fault. | |||
*/ | |||
void MemManage_Handler(void) | |||
{ | |||
/* USER CODE BEGIN MemoryManagement_IRQn 0 */ | |||
/* USER CODE END MemoryManagement_IRQn 0 */ | |||
while (1) | |||
{ | |||
/* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ | |||
/* USER CODE END W1_MemoryManagement_IRQn 0 */ | |||
} | |||
} | |||
/** | |||
* @brief This function handles Pre-fetch fault, memory access fault. | |||
*/ | |||
void BusFault_Handler(void) | |||
{ | |||
/* USER CODE BEGIN BusFault_IRQn 0 */ | |||
/* USER CODE END BusFault_IRQn 0 */ | |||
while (1) | |||
{ | |||
/* USER CODE BEGIN W1_BusFault_IRQn 0 */ | |||
/* USER CODE END W1_BusFault_IRQn 0 */ | |||
} | |||
} | |||
/** | |||
* @brief This function handles Undefined instruction or illegal state. | |||
*/ | |||
void UsageFault_Handler(void) | |||
{ | |||
/* USER CODE BEGIN UsageFault_IRQn 0 */ | |||
/* USER CODE END UsageFault_IRQn 0 */ | |||
while (1) | |||
{ | |||
/* USER CODE BEGIN W1_UsageFault_IRQn 0 */ | |||
/* USER CODE END W1_UsageFault_IRQn 0 */ | |||
} | |||
} | |||
/** | |||
* @brief This function handles System service call via SWI instruction. | |||
*/ | |||
void SVC_Handler(void) | |||
{ | |||
/* USER CODE BEGIN SVCall_IRQn 0 */ | |||
/* USER CODE END SVCall_IRQn 0 */ | |||
/* USER CODE BEGIN SVCall_IRQn 1 */ | |||
/* USER CODE END SVCall_IRQn 1 */ | |||
} | |||
/** | |||
* @brief This function handles Debug monitor. | |||
*/ | |||
void DebugMon_Handler(void) | |||
{ | |||
/* USER CODE BEGIN DebugMonitor_IRQn 0 */ | |||
/* USER CODE END DebugMonitor_IRQn 0 */ | |||
/* USER CODE BEGIN DebugMonitor_IRQn 1 */ | |||
/* USER CODE END DebugMonitor_IRQn 1 */ | |||
} | |||
/** | |||
* @brief This function handles Pendable request for system service. | |||
*/ | |||
void PendSV_Handler(void) | |||
{ | |||
/* USER CODE BEGIN PendSV_IRQn 0 */ | |||
/* USER CODE END PendSV_IRQn 0 */ | |||
/* USER CODE BEGIN PendSV_IRQn 1 */ | |||
/* USER CODE END PendSV_IRQn 1 */ | |||
} | |||
/** | |||
* @brief This function handles System tick timer. | |||
*/ | |||
void SysTick_Handler(void) | |||
{ | |||
/* USER CODE BEGIN SysTick_IRQn 0 */ | |||
/* USER CODE END SysTick_IRQn 0 */ | |||
HAL_IncTick(); | |||
/* USER CODE BEGIN SysTick_IRQn 1 */ | |||
/* USER CODE END SysTick_IRQn 1 */ | |||
} | |||
/******************************************************************************/ | |||
/* STM32F4xx Peripheral Interrupt Handlers */ | |||
/* Add here the Interrupt Handlers for the used peripherals. */ | |||
/* For the available peripheral interrupt handler names, */ | |||
/* please refer to the startup file (startup_stm32f4xx.s). */ | |||
/******************************************************************************/ | |||
/** | |||
* @brief This function handles RTC alarms A and B interrupt through EXTI line 17. | |||
*/ | |||
void RTC_Alarm_IRQHandler(void) | |||
{ | |||
/* USER CODE BEGIN RTC_Alarm_IRQn 0 */ | |||
/* USER CODE END RTC_Alarm_IRQn 0 */ | |||
HAL_RTC_AlarmIRQHandler(&hrtc); | |||
/* USER CODE BEGIN RTC_Alarm_IRQn 1 */ | |||
/* USER CODE END RTC_Alarm_IRQn 1 */ | |||
} | |||
/* USER CODE BEGIN 1 */ | |||
/* USER CODE END 1 */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,727 @@ | |||
/** | |||
****************************************************************************** | |||
* @file system_stm32f4xx.c | |||
* @author MCD Application Team | |||
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. | |||
* | |||
* This file provides two functions and one global variable to be called from | |||
* user application: | |||
* - SystemInit(): This function is called at startup just after reset and | |||
* before branch to main program. This call is made inside | |||
* the "startup_stm32f4xx.s" file. | |||
* | |||
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used | |||
* by the user application to setup the SysTick | |||
* timer or configure other parameters. | |||
* | |||
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must | |||
* be called whenever the core clock is changed | |||
* during program execution. | |||
* | |||
* | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/** @addtogroup CMSIS | |||
* @{ | |||
*/ | |||
/** @addtogroup stm32f4xx_system | |||
* @{ | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_Includes | |||
* @{ | |||
*/ | |||
#include "stm32f4xx.h" | |||
#if !defined (HSE_VALUE) | |||
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ | |||
#endif /* HSE_VALUE */ | |||
#if !defined (HSI_VALUE) | |||
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ | |||
#endif /* HSI_VALUE */ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_TypesDefinitions | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_Defines | |||
* @{ | |||
*/ | |||
/************************* Miscellaneous Configuration ************************/ | |||
/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ | |||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ | |||
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ | |||
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) | |||
/* #define DATA_IN_ExtSRAM */ | |||
#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ | |||
STM32F412Zx || STM32F412Vx */ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ | |||
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |||
/* #define DATA_IN_ExtSDRAM */ | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ | |||
STM32F479xx */ | |||
/*!< Uncomment the following line if you need to relocate your vector Table in | |||
Internal SRAM. */ | |||
/* #define VECT_TAB_SRAM */ | |||
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. | |||
This value must be a multiple of 0x200. */ | |||
/******************************************************************************/ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_Macros | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_Variables | |||
* @{ | |||
*/ | |||
/* This variable is updated in three ways: | |||
1) by calling CMSIS function SystemCoreClockUpdate() | |||
2) by calling HAL API function HAL_RCC_GetHCLKFreq() | |||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency | |||
Note: If you use this function to configure the system clock; then there | |||
is no need to call the 2 first functions listed above, since SystemCoreClock | |||
variable is updated automatically. | |||
*/ | |||
uint32_t SystemCoreClock = 16000000; | |||
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; | |||
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes | |||
* @{ | |||
*/ | |||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) | |||
static void SystemInit_ExtMemCtl(void); | |||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup STM32F4xx_System_Private_Functions | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Setup the microcontroller system | |||
* Initialize the FPU setting, vector table location and External memory | |||
* configuration. | |||
* @param None | |||
* @retval None | |||
*/ | |||
void SystemInit(void) | |||
{ | |||
/* FPU settings ------------------------------------------------------------*/ | |||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) | |||
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ | |||
#endif | |||
#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) | |||
SystemInit_ExtMemCtl(); | |||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ | |||
/* Configure the Vector Table location add offset address ------------------*/ | |||
#ifdef VECT_TAB_SRAM | |||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ | |||
#else | |||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ | |||
#endif | |||
} | |||
/** | |||
* @brief Update SystemCoreClock variable according to Clock Register Values. | |||
* The SystemCoreClock variable contains the core clock (HCLK), it can | |||
* be used by the user application to setup the SysTick timer or configure | |||
* other parameters. | |||
* | |||
* @note Each time the core clock (HCLK) changes, this function must be called | |||
* to update SystemCoreClock variable value. Otherwise, any configuration | |||
* based on this variable will be incorrect. | |||
* | |||
* @note - The system frequency computed by this function is not the real | |||
* frequency in the chip. It is calculated based on the predefined | |||
* constant and the selected clock source: | |||
* | |||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) | |||
* | |||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) | |||
* | |||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) | |||
* or HSI_VALUE(*) multiplied/divided by the PLL factors. | |||
* | |||
* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value | |||
* 16 MHz) but the real value may vary depending on the variations | |||
* in voltage and temperature. | |||
* | |||
* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value | |||
* depends on the application requirements), user has to ensure that HSE_VALUE | |||
* is same as the real frequency of the crystal used. Otherwise, this function | |||
* may have wrong result. | |||
* | |||
* - The result of this function could be not correct when using fractional | |||
* value for HSE crystal. | |||
* | |||
* @param None | |||
* @retval None | |||
*/ | |||
void SystemCoreClockUpdate(void) | |||
{ | |||
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; | |||
/* Get SYSCLK source -------------------------------------------------------*/ | |||
tmp = RCC->CFGR & RCC_CFGR_SWS; | |||
switch (tmp) | |||
{ | |||
case 0x00: /* HSI used as system clock source */ | |||
SystemCoreClock = HSI_VALUE; | |||
break; | |||
case 0x04: /* HSE used as system clock source */ | |||
SystemCoreClock = HSE_VALUE; | |||
break; | |||
case 0x08: /* PLL used as system clock source */ | |||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N | |||
SYSCLK = PLL_VCO / PLL_P | |||
*/ | |||
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; | |||
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; | |||
if (pllsource != 0) | |||
{ | |||
/* HSE used as PLL clock source */ | |||
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); | |||
} | |||
else | |||
{ | |||
/* HSI used as PLL clock source */ | |||
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); | |||
} | |||
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; | |||
SystemCoreClock = pllvco/pllp; | |||
break; | |||
default: | |||
SystemCoreClock = HSI_VALUE; | |||
break; | |||
} | |||
/* Compute HCLK frequency --------------------------------------------------*/ | |||
/* Get HCLK prescaler */ | |||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; | |||
/* HCLK frequency */ | |||
SystemCoreClock >>= tmp; | |||
} | |||
#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ | |||
|| defined(STM32F469xx) || defined(STM32F479xx) | |||
/** | |||
* @brief Setup the external memory controller. | |||
* Called in startup_stm32f4xx.s before jump to main. | |||
* This function configures the external memories (SRAM/SDRAM) | |||
* This SRAM/SDRAM will be used as program data memory (including heap and stack). | |||
* @param None | |||
* @retval None | |||
*/ | |||
void SystemInit_ExtMemCtl(void) | |||
{ | |||
__IO uint32_t tmp = 0x00; | |||
register uint32_t tmpreg = 0, timeout = 0xFFFF; | |||
register __IO uint32_t index; | |||
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ | |||
RCC->AHB1ENR |= 0x000001F8; | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); | |||
/* Connect PDx pins to FMC Alternate function */ | |||
GPIOD->AFR[0] = 0x00CCC0CC; | |||
GPIOD->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PDx pins in Alternate function mode */ | |||
GPIOD->MODER = 0xAAAA0A8A; | |||
/* Configure PDx pins speed to 100 MHz */ | |||
GPIOD->OSPEEDR = 0xFFFF0FCF; | |||
/* Configure PDx pins Output type to push-pull */ | |||
GPIOD->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PDx pins */ | |||
GPIOD->PUPDR = 0x00000000; | |||
/* Connect PEx pins to FMC Alternate function */ | |||
GPIOE->AFR[0] = 0xC00CC0CC; | |||
GPIOE->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PEx pins in Alternate function mode */ | |||
GPIOE->MODER = 0xAAAA828A; | |||
/* Configure PEx pins speed to 100 MHz */ | |||
GPIOE->OSPEEDR = 0xFFFFC3CF; | |||
/* Configure PEx pins Output type to push-pull */ | |||
GPIOE->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PEx pins */ | |||
GPIOE->PUPDR = 0x00000000; | |||
/* Connect PFx pins to FMC Alternate function */ | |||
GPIOF->AFR[0] = 0xCCCCCCCC; | |||
GPIOF->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PFx pins in Alternate function mode */ | |||
GPIOF->MODER = 0xAA800AAA; | |||
/* Configure PFx pins speed to 50 MHz */ | |||
GPIOF->OSPEEDR = 0xAA800AAA; | |||
/* Configure PFx pins Output type to push-pull */ | |||
GPIOF->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PFx pins */ | |||
GPIOF->PUPDR = 0x00000000; | |||
/* Connect PGx pins to FMC Alternate function */ | |||
GPIOG->AFR[0] = 0xCCCCCCCC; | |||
GPIOG->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PGx pins in Alternate function mode */ | |||
GPIOG->MODER = 0xAAAAAAAA; | |||
/* Configure PGx pins speed to 50 MHz */ | |||
GPIOG->OSPEEDR = 0xAAAAAAAA; | |||
/* Configure PGx pins Output type to push-pull */ | |||
GPIOG->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PGx pins */ | |||
GPIOG->PUPDR = 0x00000000; | |||
/* Connect PHx pins to FMC Alternate function */ | |||
GPIOH->AFR[0] = 0x00C0CC00; | |||
GPIOH->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PHx pins in Alternate function mode */ | |||
GPIOH->MODER = 0xAAAA08A0; | |||
/* Configure PHx pins speed to 50 MHz */ | |||
GPIOH->OSPEEDR = 0xAAAA08A0; | |||
/* Configure PHx pins Output type to push-pull */ | |||
GPIOH->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PHx pins */ | |||
GPIOH->PUPDR = 0x00000000; | |||
/* Connect PIx pins to FMC Alternate function */ | |||
GPIOI->AFR[0] = 0xCCCCCCCC; | |||
GPIOI->AFR[1] = 0x00000CC0; | |||
/* Configure PIx pins in Alternate function mode */ | |||
GPIOI->MODER = 0x0028AAAA; | |||
/* Configure PIx pins speed to 50 MHz */ | |||
GPIOI->OSPEEDR = 0x0028AAAA; | |||
/* Configure PIx pins Output type to push-pull */ | |||
GPIOI->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PIx pins */ | |||
GPIOI->PUPDR = 0x00000000; | |||
/*-- FMC Configuration -------------------------------------------------------*/ | |||
/* Enable the FMC interface clock */ | |||
RCC->AHB3ENR |= 0x00000001; | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); | |||
FMC_Bank5_6->SDCR[0] = 0x000019E4; | |||
FMC_Bank5_6->SDTR[0] = 0x01115351; | |||
/* SDRAM initialization sequence */ | |||
/* Clock enable command */ | |||
FMC_Bank5_6->SDCMR = 0x00000011; | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* Delay */ | |||
for (index = 0; index<1000; index++); | |||
/* PALL command */ | |||
FMC_Bank5_6->SDCMR = 0x00000012; | |||
timeout = 0xFFFF; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* Auto refresh command */ | |||
FMC_Bank5_6->SDCMR = 0x00000073; | |||
timeout = 0xFFFF; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* MRD register program */ | |||
FMC_Bank5_6->SDCMR = 0x00046014; | |||
timeout = 0xFFFF; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* Set refresh count */ | |||
tmpreg = FMC_Bank5_6->SDRTR; | |||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); | |||
/* Disable write protection */ | |||
tmpreg = FMC_Bank5_6->SDCR[0]; | |||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) | |||
/* Configure and enable Bank1_SRAM2 */ | |||
FMC_Bank1->BTCR[2] = 0x00001011; | |||
FMC_Bank1->BTCR[3] = 0x00000201; | |||
FMC_Bank1E->BWTR[2] = 0x0fffffff; | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |||
#if defined(STM32F469xx) || defined(STM32F479xx) | |||
/* Configure and enable Bank1_SRAM2 */ | |||
FMC_Bank1->BTCR[2] = 0x00001091; | |||
FMC_Bank1->BTCR[3] = 0x00110212; | |||
FMC_Bank1E->BWTR[2] = 0x0fffffff; | |||
#endif /* STM32F469xx || STM32F479xx */ | |||
(void)(tmp); | |||
} | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |||
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) | |||
/** | |||
* @brief Setup the external memory controller. | |||
* Called in startup_stm32f4xx.s before jump to main. | |||
* This function configures the external memories (SRAM/SDRAM) | |||
* This SRAM/SDRAM will be used as program data memory (including heap and stack). | |||
* @param None | |||
* @retval None | |||
*/ | |||
void SystemInit_ExtMemCtl(void) | |||
{ | |||
__IO uint32_t tmp = 0x00; | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ | |||
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |||
#if defined (DATA_IN_ExtSDRAM) | |||
register uint32_t tmpreg = 0, timeout = 0xFFFF; | |||
register __IO uint32_t index; | |||
#if defined(STM32F446xx) | |||
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface | |||
clock */ | |||
RCC->AHB1ENR |= 0x0000007D; | |||
#else | |||
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface | |||
clock */ | |||
RCC->AHB1ENR |= 0x000001F8; | |||
#endif /* STM32F446xx */ | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); | |||
#if defined(STM32F446xx) | |||
/* Connect PAx pins to FMC Alternate function */ | |||
GPIOA->AFR[0] |= 0xC0000000; | |||
GPIOA->AFR[1] |= 0x00000000; | |||
/* Configure PDx pins in Alternate function mode */ | |||
GPIOA->MODER |= 0x00008000; | |||
/* Configure PDx pins speed to 50 MHz */ | |||
GPIOA->OSPEEDR |= 0x00008000; | |||
/* Configure PDx pins Output type to push-pull */ | |||
GPIOA->OTYPER |= 0x00000000; | |||
/* No pull-up, pull-down for PDx pins */ | |||
GPIOA->PUPDR |= 0x00000000; | |||
/* Connect PCx pins to FMC Alternate function */ | |||
GPIOC->AFR[0] |= 0x00CC0000; | |||
GPIOC->AFR[1] |= 0x00000000; | |||
/* Configure PDx pins in Alternate function mode */ | |||
GPIOC->MODER |= 0x00000A00; | |||
/* Configure PDx pins speed to 50 MHz */ | |||
GPIOC->OSPEEDR |= 0x00000A00; | |||
/* Configure PDx pins Output type to push-pull */ | |||
GPIOC->OTYPER |= 0x00000000; | |||
/* No pull-up, pull-down for PDx pins */ | |||
GPIOC->PUPDR |= 0x00000000; | |||
#endif /* STM32F446xx */ | |||
/* Connect PDx pins to FMC Alternate function */ | |||
GPIOD->AFR[0] = 0x000000CC; | |||
GPIOD->AFR[1] = 0xCC000CCC; | |||
/* Configure PDx pins in Alternate function mode */ | |||
GPIOD->MODER = 0xA02A000A; | |||
/* Configure PDx pins speed to 50 MHz */ | |||
GPIOD->OSPEEDR = 0xA02A000A; | |||
/* Configure PDx pins Output type to push-pull */ | |||
GPIOD->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PDx pins */ | |||
GPIOD->PUPDR = 0x00000000; | |||
/* Connect PEx pins to FMC Alternate function */ | |||
GPIOE->AFR[0] = 0xC00000CC; | |||
GPIOE->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PEx pins in Alternate function mode */ | |||
GPIOE->MODER = 0xAAAA800A; | |||
/* Configure PEx pins speed to 50 MHz */ | |||
GPIOE->OSPEEDR = 0xAAAA800A; | |||
/* Configure PEx pins Output type to push-pull */ | |||
GPIOE->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PEx pins */ | |||
GPIOE->PUPDR = 0x00000000; | |||
/* Connect PFx pins to FMC Alternate function */ | |||
GPIOF->AFR[0] = 0xCCCCCCCC; | |||
GPIOF->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PFx pins in Alternate function mode */ | |||
GPIOF->MODER = 0xAA800AAA; | |||
/* Configure PFx pins speed to 50 MHz */ | |||
GPIOF->OSPEEDR = 0xAA800AAA; | |||
/* Configure PFx pins Output type to push-pull */ | |||
GPIOF->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PFx pins */ | |||
GPIOF->PUPDR = 0x00000000; | |||
/* Connect PGx pins to FMC Alternate function */ | |||
GPIOG->AFR[0] = 0xCCCCCCCC; | |||
GPIOG->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PGx pins in Alternate function mode */ | |||
GPIOG->MODER = 0xAAAAAAAA; | |||
/* Configure PGx pins speed to 50 MHz */ | |||
GPIOG->OSPEEDR = 0xAAAAAAAA; | |||
/* Configure PGx pins Output type to push-pull */ | |||
GPIOG->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PGx pins */ | |||
GPIOG->PUPDR = 0x00000000; | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ | |||
|| defined(STM32F469xx) || defined(STM32F479xx) | |||
/* Connect PHx pins to FMC Alternate function */ | |||
GPIOH->AFR[0] = 0x00C0CC00; | |||
GPIOH->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PHx pins in Alternate function mode */ | |||
GPIOH->MODER = 0xAAAA08A0; | |||
/* Configure PHx pins speed to 50 MHz */ | |||
GPIOH->OSPEEDR = 0xAAAA08A0; | |||
/* Configure PHx pins Output type to push-pull */ | |||
GPIOH->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PHx pins */ | |||
GPIOH->PUPDR = 0x00000000; | |||
/* Connect PIx pins to FMC Alternate function */ | |||
GPIOI->AFR[0] = 0xCCCCCCCC; | |||
GPIOI->AFR[1] = 0x00000CC0; | |||
/* Configure PIx pins in Alternate function mode */ | |||
GPIOI->MODER = 0x0028AAAA; | |||
/* Configure PIx pins speed to 50 MHz */ | |||
GPIOI->OSPEEDR = 0x0028AAAA; | |||
/* Configure PIx pins Output type to push-pull */ | |||
GPIOI->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PIx pins */ | |||
GPIOI->PUPDR = 0x00000000; | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |||
/*-- FMC Configuration -------------------------------------------------------*/ | |||
/* Enable the FMC interface clock */ | |||
RCC->AHB3ENR |= 0x00000001; | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); | |||
/* Configure and enable SDRAM bank1 */ | |||
#if defined(STM32F446xx) | |||
FMC_Bank5_6->SDCR[0] = 0x00001954; | |||
#else | |||
FMC_Bank5_6->SDCR[0] = 0x000019E4; | |||
#endif /* STM32F446xx */ | |||
FMC_Bank5_6->SDTR[0] = 0x01115351; | |||
/* SDRAM initialization sequence */ | |||
/* Clock enable command */ | |||
FMC_Bank5_6->SDCMR = 0x00000011; | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* Delay */ | |||
for (index = 0; index<1000; index++); | |||
/* PALL command */ | |||
FMC_Bank5_6->SDCMR = 0x00000012; | |||
timeout = 0xFFFF; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* Auto refresh command */ | |||
#if defined(STM32F446xx) | |||
FMC_Bank5_6->SDCMR = 0x000000F3; | |||
#else | |||
FMC_Bank5_6->SDCMR = 0x00000073; | |||
#endif /* STM32F446xx */ | |||
timeout = 0xFFFF; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* MRD register program */ | |||
#if defined(STM32F446xx) | |||
FMC_Bank5_6->SDCMR = 0x00044014; | |||
#else | |||
FMC_Bank5_6->SDCMR = 0x00046014; | |||
#endif /* STM32F446xx */ | |||
timeout = 0xFFFF; | |||
while((tmpreg != 0) && (timeout-- > 0)) | |||
{ | |||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020; | |||
} | |||
/* Set refresh count */ | |||
tmpreg = FMC_Bank5_6->SDRTR; | |||
#if defined(STM32F446xx) | |||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); | |||
#else | |||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); | |||
#endif /* STM32F446xx */ | |||
/* Disable write protection */ | |||
tmpreg = FMC_Bank5_6->SDCR[0]; | |||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); | |||
#endif /* DATA_IN_ExtSDRAM */ | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ | |||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ | |||
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ | |||
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) | |||
#if defined(DATA_IN_ExtSRAM) | |||
/*-- GPIOs Configuration -----------------------------------------------------*/ | |||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ | |||
RCC->AHB1ENR |= 0x00000078; | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); | |||
/* Connect PDx pins to FMC Alternate function */ | |||
GPIOD->AFR[0] = 0x00CCC0CC; | |||
GPIOD->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PDx pins in Alternate function mode */ | |||
GPIOD->MODER = 0xAAAA0A8A; | |||
/* Configure PDx pins speed to 100 MHz */ | |||
GPIOD->OSPEEDR = 0xFFFF0FCF; | |||
/* Configure PDx pins Output type to push-pull */ | |||
GPIOD->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PDx pins */ | |||
GPIOD->PUPDR = 0x00000000; | |||
/* Connect PEx pins to FMC Alternate function */ | |||
GPIOE->AFR[0] = 0xC00CC0CC; | |||
GPIOE->AFR[1] = 0xCCCCCCCC; | |||
/* Configure PEx pins in Alternate function mode */ | |||
GPIOE->MODER = 0xAAAA828A; | |||
/* Configure PEx pins speed to 100 MHz */ | |||
GPIOE->OSPEEDR = 0xFFFFC3CF; | |||
/* Configure PEx pins Output type to push-pull */ | |||
GPIOE->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PEx pins */ | |||
GPIOE->PUPDR = 0x00000000; | |||
/* Connect PFx pins to FMC Alternate function */ | |||
GPIOF->AFR[0] = 0x00CCCCCC; | |||
GPIOF->AFR[1] = 0xCCCC0000; | |||
/* Configure PFx pins in Alternate function mode */ | |||
GPIOF->MODER = 0xAA000AAA; | |||
/* Configure PFx pins speed to 100 MHz */ | |||
GPIOF->OSPEEDR = 0xFF000FFF; | |||
/* Configure PFx pins Output type to push-pull */ | |||
GPIOF->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PFx pins */ | |||
GPIOF->PUPDR = 0x00000000; | |||
/* Connect PGx pins to FMC Alternate function */ | |||
GPIOG->AFR[0] = 0x00CCCCCC; | |||
GPIOG->AFR[1] = 0x000000C0; | |||
/* Configure PGx pins in Alternate function mode */ | |||
GPIOG->MODER = 0x00085AAA; | |||
/* Configure PGx pins speed to 100 MHz */ | |||
GPIOG->OSPEEDR = 0x000CAFFF; | |||
/* Configure PGx pins Output type to push-pull */ | |||
GPIOG->OTYPER = 0x00000000; | |||
/* No pull-up, pull-down for PGx pins */ | |||
GPIOG->PUPDR = 0x00000000; | |||
/*-- FMC/FSMC Configuration --------------------------------------------------*/ | |||
/* Enable the FMC/FSMC interface clock */ | |||
RCC->AHB3ENR |= 0x00000001; | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); | |||
/* Configure and enable Bank1_SRAM2 */ | |||
FMC_Bank1->BTCR[2] = 0x00001011; | |||
FMC_Bank1->BTCR[3] = 0x00000201; | |||
FMC_Bank1E->BWTR[2] = 0x0fffffff; | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |||
#if defined(STM32F469xx) || defined(STM32F479xx) | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); | |||
/* Configure and enable Bank1_SRAM2 */ | |||
FMC_Bank1->BTCR[2] = 0x00001091; | |||
FMC_Bank1->BTCR[3] = 0x00110212; | |||
FMC_Bank1E->BWTR[2] = 0x0fffffff; | |||
#endif /* STM32F469xx || STM32F479xx */ | |||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ | |||
|| defined(STM32F412Zx) || defined(STM32F412Vx) | |||
/* Delay after an RCC peripheral clock enabling */ | |||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); | |||
/* Configure and enable Bank1_SRAM2 */ | |||
FSMC_Bank1->BTCR[2] = 0x00001011; | |||
FSMC_Bank1->BTCR[3] = 0x00000201; | |||
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; | |||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ | |||
#endif /* DATA_IN_ExtSRAM */ | |||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ | |||
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ | |||
(void)(tmp); | |||
} | |||
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,298 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal.h | |||
* @author MCD Application Team | |||
* @brief This file contains all the functions prototypes for the HAL | |||
* module driver. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_H | |||
#define __STM32F4xx_HAL_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_conf.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup HAL | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup HAL_Exported_Constants HAL Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup HAL_TICK_FREQ Tick Frequency | |||
* @{ | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_TICK_FREQ_10HZ = 100U, | |||
HAL_TICK_FREQ_100HZ = 10U, | |||
HAL_TICK_FREQ_1KHZ = 1U, | |||
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ | |||
} HAL_TickFreqTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup HAL_Exported_Macros HAL Exported Macros | |||
* @{ | |||
*/ | |||
/** @brief Freeze/Unfreeze Peripherals in Debug mode | |||
*/ | |||
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) | |||
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) | |||
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) | |||
#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) | |||
#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) | |||
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) | |||
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) | |||
#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) | |||
#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) | |||
/** @brief Main Flash memory mapped at 0x00000000 | |||
*/ | |||
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE)) | |||
/** @brief System Flash memory mapped at 0x00000000 | |||
*/ | |||
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ | |||
SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\ | |||
}while(0); | |||
/** @brief Embedded SRAM mapped at 0x00000000 | |||
*/ | |||
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ | |||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\ | |||
}while(0); | |||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) | |||
/** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 | |||
*/ | |||
#define __HAL_SYSCFG_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ | |||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ | |||
}while(0); | |||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ | |||
defined(STM32F469xx) || defined(STM32F479xx) | |||
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 | |||
*/ | |||
#define __HAL_SYSCFG_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ | |||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\ | |||
}while(0); | |||
/** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000 | |||
*/ | |||
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\ | |||
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\ | |||
}while(0); | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |||
/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable | |||
* @{ | |||
*/ | |||
/** @brief SYSCFG Break Lockup lock | |||
* Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input | |||
* @note The selected configuration is locked and can be unlocked by system reset | |||
*/ | |||
#define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ | |||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ | |||
}while(0) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PVD_Lock_Enable PVD Lock | |||
* @{ | |||
*/ | |||
/** @brief SYSCFG Break PVD lock | |||
* Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register | |||
* @note The selected configuration is locked and can be unlocked by system reset | |||
*/ | |||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ | |||
SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ | |||
}while(0) | |||
/** | |||
* @} | |||
*/ | |||
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup HAL_Private_Macros HAL Private Macros | |||
* @{ | |||
*/ | |||
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ | |||
((FREQ) == HAL_TICK_FREQ_100HZ) || \ | |||
((FREQ) == HAL_TICK_FREQ_1KHZ)) | |||
/** | |||
* @} | |||
*/ | |||
/* Exported variables --------------------------------------------------------*/ | |||
/** @addtogroup HAL_Exported_Variables | |||
* @{ | |||
*/ | |||
extern __IO uint32_t uwTick; | |||
extern uint32_t uwTickPrio; | |||
extern HAL_TickFreqTypeDef uwTickFreq; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup HAL_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup HAL_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
/* Initialization and Configuration functions ******************************/ | |||
HAL_StatusTypeDef HAL_Init(void); | |||
HAL_StatusTypeDef HAL_DeInit(void); | |||
void HAL_MspInit(void); | |||
void HAL_MspDeInit(void); | |||
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup HAL_Exported_Functions_Group2 | |||
* @{ | |||
*/ | |||
/* Peripheral Control functions ************************************************/ | |||
void HAL_IncTick(void); | |||
void HAL_Delay(uint32_t Delay); | |||
uint32_t HAL_GetTick(void); | |||
uint32_t HAL_GetTickPrio(void); | |||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); | |||
HAL_TickFreqTypeDef HAL_GetTickFreq(void); | |||
void HAL_SuspendTick(void); | |||
void HAL_ResumeTick(void); | |||
uint32_t HAL_GetHalVersion(void); | |||
uint32_t HAL_GetREVID(void); | |||
uint32_t HAL_GetDEVID(void); | |||
void HAL_DBGMCU_EnableDBGSleepMode(void); | |||
void HAL_DBGMCU_DisableDBGSleepMode(void); | |||
void HAL_DBGMCU_EnableDBGStopMode(void); | |||
void HAL_DBGMCU_DisableDBGStopMode(void); | |||
void HAL_DBGMCU_EnableDBGStandbyMode(void); | |||
void HAL_DBGMCU_DisableDBGStandbyMode(void); | |||
void HAL_EnableCompensationCell(void); | |||
void HAL_DisableCompensationCell(void); | |||
uint32_t HAL_GetUIDw0(void); | |||
uint32_t HAL_GetUIDw1(void); | |||
uint32_t HAL_GetUIDw2(void); | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ | |||
defined(STM32F469xx) || defined(STM32F479xx) | |||
void HAL_EnableMemorySwappingBank(void); | |||
void HAL_DisableMemorySwappingBank(void); | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/** @defgroup HAL_Private_Variables HAL Private Variables | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup HAL_Private_Constants HAL Private Constants | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,410 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_cortex.h | |||
* @author MCD Application Team | |||
* @brief Header file of CORTEX HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_CORTEX_H | |||
#define __STM32F4xx_HAL_CORTEX_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup CORTEX | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup CORTEX_Exported_Types Cortex Exported Types | |||
* @{ | |||
*/ | |||
#if (__MPU_PRESENT == 1U) | |||
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition | |||
* @brief MPU Region initialization structure | |||
* @{ | |||
*/ | |||
typedef struct | |||
{ | |||
uint8_t Enable; /*!< Specifies the status of the region. | |||
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ | |||
uint8_t Number; /*!< Specifies the number of the region to protect. | |||
This parameter can be a value of @ref CORTEX_MPU_Region_Number */ | |||
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ | |||
uint8_t Size; /*!< Specifies the size of the region to protect. | |||
This parameter can be a value of @ref CORTEX_MPU_Region_Size */ | |||
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. | |||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ | |||
uint8_t TypeExtField; /*!< Specifies the TEX field level. | |||
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ | |||
uint8_t AccessPermission; /*!< Specifies the region access permission type. | |||
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ | |||
uint8_t DisableExec; /*!< Specifies the instruction access status. | |||
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ | |||
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. | |||
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ | |||
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. | |||
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ | |||
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. | |||
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ | |||
}MPU_Region_InitTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
#endif /* __MPU_PRESENT */ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group | |||
* @{ | |||
*/ | |||
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority | |||
4 bits for subpriority */ | |||
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority | |||
3 bits for subpriority */ | |||
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority | |||
2 bits for subpriority */ | |||
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority | |||
1 bits for subpriority */ | |||
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority | |||
0 bits for subpriority */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source | |||
* @{ | |||
*/ | |||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U | |||
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U | |||
/** | |||
* @} | |||
*/ | |||
#if (__MPU_PRESENT == 1) | |||
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control | |||
* @{ | |||
*/ | |||
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U | |||
#define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk | |||
#define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk | |||
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable | |||
* @{ | |||
*/ | |||
#define MPU_REGION_ENABLE ((uint8_t)0x01) | |||
#define MPU_REGION_DISABLE ((uint8_t)0x00) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access | |||
* @{ | |||
*/ | |||
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) | |||
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable | |||
* @{ | |||
*/ | |||
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) | |||
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable | |||
* @{ | |||
*/ | |||
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) | |||
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable | |||
* @{ | |||
*/ | |||
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) | |||
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels | |||
* @{ | |||
*/ | |||
#define MPU_TEX_LEVEL0 ((uint8_t)0x00) | |||
#define MPU_TEX_LEVEL1 ((uint8_t)0x01) | |||
#define MPU_TEX_LEVEL2 ((uint8_t)0x02) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size | |||
* @{ | |||
*/ | |||
#define MPU_REGION_SIZE_32B ((uint8_t)0x04) | |||
#define MPU_REGION_SIZE_64B ((uint8_t)0x05) | |||
#define MPU_REGION_SIZE_128B ((uint8_t)0x06) | |||
#define MPU_REGION_SIZE_256B ((uint8_t)0x07) | |||
#define MPU_REGION_SIZE_512B ((uint8_t)0x08) | |||
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09) | |||
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) | |||
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) | |||
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) | |||
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) | |||
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) | |||
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) | |||
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10) | |||
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11) | |||
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12) | |||
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13) | |||
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14) | |||
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15) | |||
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16) | |||
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17) | |||
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18) | |||
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19) | |||
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) | |||
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) | |||
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) | |||
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) | |||
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) | |||
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes | |||
* @{ | |||
*/ | |||
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00) | |||
#define MPU_REGION_PRIV_RW ((uint8_t)0x01) | |||
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) | |||
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) | |||
#define MPU_REGION_PRIV_RO ((uint8_t)0x05) | |||
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number | |||
* @{ | |||
*/ | |||
#define MPU_REGION_NUMBER0 ((uint8_t)0x00) | |||
#define MPU_REGION_NUMBER1 ((uint8_t)0x01) | |||
#define MPU_REGION_NUMBER2 ((uint8_t)0x02) | |||
#define MPU_REGION_NUMBER3 ((uint8_t)0x03) | |||
#define MPU_REGION_NUMBER4 ((uint8_t)0x04) | |||
#define MPU_REGION_NUMBER5 ((uint8_t)0x05) | |||
#define MPU_REGION_NUMBER6 ((uint8_t)0x06) | |||
#define MPU_REGION_NUMBER7 ((uint8_t)0x07) | |||
/** | |||
* @} | |||
*/ | |||
#endif /* __MPU_PRESENT */ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported Macros -----------------------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup CORTEX_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup CORTEX_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
/* Initialization and de-initialization functions *****************************/ | |||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); | |||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); | |||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); | |||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); | |||
void HAL_NVIC_SystemReset(void); | |||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup CORTEX_Exported_Functions_Group2 | |||
* @{ | |||
*/ | |||
/* Peripheral Control functions ***********************************************/ | |||
uint32_t HAL_NVIC_GetPriorityGrouping(void); | |||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); | |||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); | |||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); | |||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); | |||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); | |||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); | |||
void HAL_SYSTICK_IRQHandler(void); | |||
void HAL_SYSTICK_Callback(void); | |||
#if (__MPU_PRESENT == 1U) | |||
void HAL_MPU_Enable(uint32_t MPU_Control); | |||
void HAL_MPU_Disable(void); | |||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); | |||
#endif /* __MPU_PRESENT */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros | |||
* @{ | |||
*/ | |||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ | |||
((GROUP) == NVIC_PRIORITYGROUP_1) || \ | |||
((GROUP) == NVIC_PRIORITYGROUP_2) || \ | |||
((GROUP) == NVIC_PRIORITYGROUP_3) || \ | |||
((GROUP) == NVIC_PRIORITYGROUP_4)) | |||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) | |||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) | |||
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) | |||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ | |||
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) | |||
#if (__MPU_PRESENT == 1U) | |||
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ | |||
((STATE) == MPU_REGION_DISABLE)) | |||
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ | |||
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) | |||
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ | |||
((STATE) == MPU_ACCESS_NOT_SHAREABLE)) | |||
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ | |||
((STATE) == MPU_ACCESS_NOT_CACHEABLE)) | |||
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ | |||
((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) | |||
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ | |||
((TYPE) == MPU_TEX_LEVEL1) || \ | |||
((TYPE) == MPU_TEX_LEVEL2)) | |||
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ | |||
((TYPE) == MPU_REGION_PRIV_RW) || \ | |||
((TYPE) == MPU_REGION_PRIV_RW_URO) || \ | |||
((TYPE) == MPU_REGION_FULL_ACCESS) || \ | |||
((TYPE) == MPU_REGION_PRIV_RO) || \ | |||
((TYPE) == MPU_REGION_PRIV_RO_URO)) | |||
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ | |||
((NUMBER) == MPU_REGION_NUMBER1) || \ | |||
((NUMBER) == MPU_REGION_NUMBER2) || \ | |||
((NUMBER) == MPU_REGION_NUMBER3) || \ | |||
((NUMBER) == MPU_REGION_NUMBER4) || \ | |||
((NUMBER) == MPU_REGION_NUMBER5) || \ | |||
((NUMBER) == MPU_REGION_NUMBER6) || \ | |||
((NUMBER) == MPU_REGION_NUMBER7)) | |||
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ | |||
((SIZE) == MPU_REGION_SIZE_64B) || \ | |||
((SIZE) == MPU_REGION_SIZE_128B) || \ | |||
((SIZE) == MPU_REGION_SIZE_256B) || \ | |||
((SIZE) == MPU_REGION_SIZE_512B) || \ | |||
((SIZE) == MPU_REGION_SIZE_1KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_2KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_4KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_8KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_16KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_32KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_64KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_128KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_256KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_512KB) || \ | |||
((SIZE) == MPU_REGION_SIZE_1MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_2MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_4MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_8MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_16MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_32MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_64MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_128MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_256MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_512MB) || \ | |||
((SIZE) == MPU_REGION_SIZE_1GB) || \ | |||
((SIZE) == MPU_REGION_SIZE_2GB) || \ | |||
((SIZE) == MPU_REGION_SIZE_4GB)) | |||
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) | |||
#endif /* __MPU_PRESENT */ | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_CORTEX_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,197 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_def.h | |||
* @author MCD Application Team | |||
* @brief This file contains HAL common defines, enumeration, macros and | |||
* structures definitions. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_DEF | |||
#define __STM32F4xx_HAL_DEF | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx.h" | |||
#include "Legacy/stm32_hal_legacy.h" | |||
#include <stddef.h> | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** | |||
* @brief HAL Status structures definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_OK = 0x00U, | |||
HAL_ERROR = 0x01U, | |||
HAL_BUSY = 0x02U, | |||
HAL_TIMEOUT = 0x03U | |||
} HAL_StatusTypeDef; | |||
/** | |||
* @brief HAL Lock structures definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_UNLOCKED = 0x00U, | |||
HAL_LOCKED = 0x01U | |||
} HAL_LockTypeDef; | |||
/* Exported macro ------------------------------------------------------------*/ | |||
#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ | |||
#define HAL_MAX_DELAY 0xFFFFFFFFU | |||
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) | |||
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) | |||
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ | |||
do{ \ | |||
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ | |||
(__DMA_HANDLE__).Parent = (__HANDLE__); \ | |||
} while(0U) | |||
/** @brief Reset the Handle's State field. | |||
* @param __HANDLE__ specifies the Peripheral Handle. | |||
* @note This macro can be used for the following purpose: | |||
* - When the Handle is declared as local variable; before passing it as parameter | |||
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro | |||
* to set to 0 the Handle's "State" field. | |||
* Otherwise, "State" field may have any random value and the first time the function | |||
* HAL_PPP_Init() is called, the low level hardware initialization will be missed | |||
* (i.e. HAL_PPP_MspInit() will not be executed). | |||
* - When there is a need to reconfigure the low level hardware: instead of calling | |||
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). | |||
* In this later function, when the Handle's "State" field is set to 0, it will execute the function | |||
* HAL_PPP_MspInit() which will reconfigure the low level hardware. | |||
* @retval None | |||
*/ | |||
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) | |||
#if (USE_RTOS == 1U) | |||
/* Reserved for future use */ | |||
#error "USE_RTOS should be 0 in the current HAL release" | |||
#else | |||
#define __HAL_LOCK(__HANDLE__) \ | |||
do{ \ | |||
if((__HANDLE__)->Lock == HAL_LOCKED) \ | |||
{ \ | |||
return HAL_BUSY; \ | |||
} \ | |||
else \ | |||
{ \ | |||
(__HANDLE__)->Lock = HAL_LOCKED; \ | |||
} \ | |||
}while (0U) | |||
#define __HAL_UNLOCK(__HANDLE__) \ | |||
do{ \ | |||
(__HANDLE__)->Lock = HAL_UNLOCKED; \ | |||
}while (0U) | |||
#endif /* USE_RTOS */ | |||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ | |||
#ifndef __weak | |||
#define __weak __attribute__((weak)) | |||
#endif /* __weak */ | |||
#ifndef __packed | |||
#define __packed __attribute__((__packed__)) | |||
#endif /* __packed */ | |||
#endif /* __GNUC__ */ | |||
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ | |||
#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ | |||
#ifndef __ALIGN_END | |||
#define __ALIGN_END __attribute__ ((aligned (4))) | |||
#endif /* __ALIGN_END */ | |||
#ifndef __ALIGN_BEGIN | |||
#define __ALIGN_BEGIN | |||
#endif /* __ALIGN_BEGIN */ | |||
#else | |||
#ifndef __ALIGN_END | |||
#define __ALIGN_END | |||
#endif /* __ALIGN_END */ | |||
#ifndef __ALIGN_BEGIN | |||
#if defined (__CC_ARM) /* ARM Compiler */ | |||
#define __ALIGN_BEGIN __align(4) | |||
#elif defined (__ICCARM__) /* IAR Compiler */ | |||
#define __ALIGN_BEGIN | |||
#endif /* __CC_ARM */ | |||
#endif /* __ALIGN_BEGIN */ | |||
#endif /* __GNUC__ */ | |||
/** | |||
* @brief __RAM_FUNC definition | |||
*/ | |||
#if defined ( __CC_ARM ) | |||
/* ARM Compiler | |||
------------ | |||
RAM functions are defined using the toolchain options. | |||
Functions that are executed in RAM should reside in a separate source module. | |||
Using the 'Options for File' dialog you can simply change the 'Code / Const' | |||
area of a module to a memory space in physical RAM. | |||
Available memory areas are declared in the 'Target' tab of the 'Options for Target' | |||
dialog. | |||
*/ | |||
#define __RAM_FUNC | |||
#elif defined ( __ICCARM__ ) | |||
/* ICCARM Compiler | |||
--------------- | |||
RAM functions are defined using a specific toolchain keyword "__ramfunc". | |||
*/ | |||
#define __RAM_FUNC __ramfunc | |||
#elif defined ( __GNUC__ ) | |||
/* GNU Compiler | |||
------------ | |||
RAM functions are defined using a specific toolchain attribute | |||
"__attribute__((section(".RamFunc")))". | |||
*/ | |||
#define __RAM_FUNC __attribute__((section(".RamFunc"))) | |||
#endif | |||
/** | |||
* @brief __NOINLINE definition | |||
*/ | |||
#if defined ( __CC_ARM ) || defined ( __GNUC__ ) | |||
/* ARM & GNUCompiler | |||
---------------- | |||
*/ | |||
#define __NOINLINE __attribute__ ( (noinline) ) | |||
#elif defined ( __ICCARM__ ) | |||
/* ICCARM Compiler | |||
--------------- | |||
*/ | |||
#define __NOINLINE _Pragma("optimize = no_inline") | |||
#endif | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* ___STM32F4xx_HAL_DEF */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,804 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_dma.h | |||
* @author MCD Application Team | |||
* @brief Header file of DMA HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_DMA_H | |||
#define __STM32F4xx_HAL_DMA_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup DMA | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup DMA_Exported_Types DMA Exported Types | |||
* @brief DMA Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief DMA Configuration Structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t Channel; /*!< Specifies the channel used for the specified stream. | |||
This parameter can be a value of @ref DMA_Channel_selection */ | |||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, | |||
from memory to memory or from peripheral to memory. | |||
This parameter can be a value of @ref DMA_Data_transfer_direction */ | |||
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. | |||
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ | |||
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. | |||
This parameter can be a value of @ref DMA_Memory_incremented_mode */ | |||
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. | |||
This parameter can be a value of @ref DMA_Peripheral_data_size */ | |||
uint32_t MemDataAlignment; /*!< Specifies the Memory data width. | |||
This parameter can be a value of @ref DMA_Memory_data_size */ | |||
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. | |||
This parameter can be a value of @ref DMA_mode | |||
@note The circular buffer mode cannot be used if the memory-to-memory | |||
data transfer is configured on the selected Stream */ | |||
uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. | |||
This parameter can be a value of @ref DMA_Priority_level */ | |||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. | |||
This parameter can be a value of @ref DMA_FIFO_direct_mode | |||
@note The Direct mode (FIFO mode disabled) cannot be used if the | |||
memory-to-memory data transfer is configured on the selected stream */ | |||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. | |||
This parameter can be a value of @ref DMA_FIFO_threshold_level */ | |||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. | |||
It specifies the amount of data to be transferred in a single non interruptible | |||
transaction. | |||
This parameter can be a value of @ref DMA_Memory_burst | |||
@note The burst mode is possible only if the address Increment mode is enabled. */ | |||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. | |||
It specifies the amount of data to be transferred in a single non interruptible | |||
transaction. | |||
This parameter can be a value of @ref DMA_Peripheral_burst | |||
@note The burst mode is possible only if the address Increment mode is enabled. */ | |||
}DMA_InitTypeDef; | |||
/** | |||
* @brief HAL DMA State structures definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ | |||
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ | |||
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ | |||
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ | |||
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ | |||
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ | |||
}HAL_DMA_StateTypeDef; | |||
/** | |||
* @brief HAL DMA Error Code structure definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ | |||
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ | |||
}HAL_DMA_LevelCompleteTypeDef; | |||
/** | |||
* @brief HAL DMA Error Code structure definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ | |||
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ | |||
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ | |||
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ | |||
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ | |||
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ | |||
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ | |||
}HAL_DMA_CallbackIDTypeDef; | |||
/** | |||
* @brief DMA handle Structure definition | |||
*/ | |||
typedef struct __DMA_HandleTypeDef | |||
{ | |||
DMA_Stream_TypeDef *Instance; /*!< Register base address */ | |||
DMA_InitTypeDef Init; /*!< DMA communication parameters */ | |||
HAL_LockTypeDef Lock; /*!< DMA locking object */ | |||
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ | |||
void *Parent; /*!< Parent object state */ | |||
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ | |||
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ | |||
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ | |||
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ | |||
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ | |||
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ | |||
__IO uint32_t ErrorCode; /*!< DMA Error code */ | |||
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ | |||
uint32_t StreamIndex; /*!< DMA Stream Index */ | |||
}DMA_HandleTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup DMA_Exported_Constants DMA Exported Constants | |||
* @brief DMA Exported constants | |||
* @{ | |||
*/ | |||
/** @defgroup DMA_Error_Code DMA Error Code | |||
* @brief DMA Error Code | |||
* @{ | |||
*/ | |||
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ | |||
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ | |||
#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ | |||
#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ | |||
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ | |||
#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ | |||
#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ | |||
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Channel_selection DMA Channel selection | |||
* @brief DMA channel selection | |||
* @{ | |||
*/ | |||
#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ | |||
#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ | |||
#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ | |||
#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ | |||
#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ | |||
#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ | |||
#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ | |||
#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ | |||
#if defined (DMA_SxCR_CHSEL_3) | |||
#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ | |||
#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ | |||
#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ | |||
#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ | |||
#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ | |||
#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ | |||
#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ | |||
#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ | |||
#endif /* DMA_SxCR_CHSEL_3 */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction | |||
* @brief DMA data transfer direction | |||
* @{ | |||
*/ | |||
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ | |||
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ | |||
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode | |||
* @brief DMA peripheral incremented mode | |||
* @{ | |||
*/ | |||
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ | |||
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode | |||
* @brief DMA memory incremented mode | |||
* @{ | |||
*/ | |||
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ | |||
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size | |||
* @brief DMA peripheral data size | |||
* @{ | |||
*/ | |||
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ | |||
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ | |||
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Memory_data_size DMA Memory data size | |||
* @brief DMA memory data size | |||
* @{ | |||
*/ | |||
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ | |||
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ | |||
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_mode DMA mode | |||
* @brief DMA mode | |||
* @{ | |||
*/ | |||
#define DMA_NORMAL 0x00000000U /*!< Normal mode */ | |||
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ | |||
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Priority_level DMA Priority level | |||
* @brief DMA priority levels | |||
* @{ | |||
*/ | |||
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ | |||
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ | |||
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ | |||
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode | |||
* @brief DMA FIFO direct mode | |||
* @{ | |||
*/ | |||
#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ | |||
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level | |||
* @brief DMA FIFO level | |||
* @{ | |||
*/ | |||
#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ | |||
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ | |||
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ | |||
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Memory_burst DMA Memory burst | |||
* @brief DMA memory burst | |||
* @{ | |||
*/ | |||
#define DMA_MBURST_SINGLE 0x00000000U | |||
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) | |||
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) | |||
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Peripheral_burst DMA Peripheral burst | |||
* @brief DMA peripheral burst | |||
* @{ | |||
*/ | |||
#define DMA_PBURST_SINGLE 0x00000000U | |||
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) | |||
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) | |||
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions | |||
* @brief DMA interrupts definition | |||
* @{ | |||
*/ | |||
#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) | |||
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) | |||
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) | |||
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) | |||
#define DMA_IT_FE 0x00000080U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_flag_definitions DMA flag definitions | |||
* @brief DMA flag definitions | |||
* @{ | |||
*/ | |||
#define DMA_FLAG_FEIF0_4 0x00000001U | |||
#define DMA_FLAG_DMEIF0_4 0x00000004U | |||
#define DMA_FLAG_TEIF0_4 0x00000008U | |||
#define DMA_FLAG_HTIF0_4 0x00000010U | |||
#define DMA_FLAG_TCIF0_4 0x00000020U | |||
#define DMA_FLAG_FEIF1_5 0x00000040U | |||
#define DMA_FLAG_DMEIF1_5 0x00000100U | |||
#define DMA_FLAG_TEIF1_5 0x00000200U | |||
#define DMA_FLAG_HTIF1_5 0x00000400U | |||
#define DMA_FLAG_TCIF1_5 0x00000800U | |||
#define DMA_FLAG_FEIF2_6 0x00010000U | |||
#define DMA_FLAG_DMEIF2_6 0x00040000U | |||
#define DMA_FLAG_TEIF2_6 0x00080000U | |||
#define DMA_FLAG_HTIF2_6 0x00100000U | |||
#define DMA_FLAG_TCIF2_6 0x00200000U | |||
#define DMA_FLAG_FEIF3_7 0x00400000U | |||
#define DMA_FLAG_DMEIF3_7 0x01000000U | |||
#define DMA_FLAG_TEIF3_7 0x02000000U | |||
#define DMA_FLAG_HTIF3_7 0x04000000U | |||
#define DMA_FLAG_TCIF3_7 0x08000000U | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @brief Reset DMA handle state | |||
* @param __HANDLE__ specifies the DMA handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) | |||
/** | |||
* @brief Return the current DMA Stream FIFO filled level. | |||
* @param __HANDLE__ DMA handle | |||
* @retval The FIFO filling state. | |||
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full | |||
* and not empty. | |||
* - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. | |||
* - DMA_FIFOStatus_HalfFull: if more than 1 half-full. | |||
* - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. | |||
* - DMA_FIFOStatus_Empty: when FIFO is empty | |||
* - DMA_FIFOStatus_Full: when FIFO is full | |||
*/ | |||
#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) | |||
/** | |||
* @brief Enable the specified DMA Stream. | |||
* @param __HANDLE__ DMA handle | |||
* @retval None | |||
*/ | |||
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) | |||
/** | |||
* @brief Disable the specified DMA Stream. | |||
* @param __HANDLE__ DMA handle | |||
* @retval None | |||
*/ | |||
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) | |||
/* Interrupt & Flag management */ | |||
/** | |||
* @brief Return the current DMA Stream transfer complete flag. | |||
* @param __HANDLE__ DMA handle | |||
* @retval The specified transfer complete flag index. | |||
*/ | |||
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ | |||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ | |||
DMA_FLAG_TCIF3_7) | |||
/** | |||
* @brief Return the current DMA Stream half transfer complete flag. | |||
* @param __HANDLE__ DMA handle | |||
* @retval The specified half transfer complete flag index. | |||
*/ | |||
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ | |||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ | |||
DMA_FLAG_HTIF3_7) | |||
/** | |||
* @brief Return the current DMA Stream transfer error flag. | |||
* @param __HANDLE__ DMA handle | |||
* @retval The specified transfer error flag index. | |||
*/ | |||
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ | |||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ | |||
DMA_FLAG_TEIF3_7) | |||
/** | |||
* @brief Return the current DMA Stream FIFO error flag. | |||
* @param __HANDLE__ DMA handle | |||
* @retval The specified FIFO error flag index. | |||
*/ | |||
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ | |||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ | |||
DMA_FLAG_FEIF3_7) | |||
/** | |||
* @brief Return the current DMA Stream direct mode error flag. | |||
* @param __HANDLE__ DMA handle | |||
* @retval The specified direct mode error flag index. | |||
*/ | |||
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ | |||
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ | |||
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ | |||
DMA_FLAG_DMEIF3_7) | |||
/** | |||
* @brief Get the DMA Stream pending flags. | |||
* @param __HANDLE__ DMA handle | |||
* @param __FLAG__ Get the specified flag. | |||
* This parameter can be any combination of the following values: | |||
* @arg DMA_FLAG_TCIFx: Transfer complete flag. | |||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag. | |||
* @arg DMA_FLAG_TEIFx: Transfer error flag. | |||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag. | |||
* @arg DMA_FLAG_FEIFx: FIFO error flag. | |||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. | |||
* @retval The state of FLAG (SET or RESET). | |||
*/ | |||
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ | |||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ | |||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ | |||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) | |||
/** | |||
* @brief Clear the DMA Stream pending flags. | |||
* @param __HANDLE__ DMA handle | |||
* @param __FLAG__ specifies the flag to clear. | |||
* This parameter can be any combination of the following values: | |||
* @arg DMA_FLAG_TCIFx: Transfer complete flag. | |||
* @arg DMA_FLAG_HTIFx: Half transfer complete flag. | |||
* @arg DMA_FLAG_TEIFx: Transfer error flag. | |||
* @arg DMA_FLAG_DMEIFx: Direct mode error flag. | |||
* @arg DMA_FLAG_FEIFx: FIFO error flag. | |||
* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. | |||
* @retval None | |||
*/ | |||
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ | |||
(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ | |||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ | |||
((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) | |||
/** | |||
* @brief Enable the specified DMA Stream interrupts. | |||
* @param __HANDLE__ DMA handle | |||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. | |||
* This parameter can be any combination of the following values: | |||
* @arg DMA_IT_TC: Transfer complete interrupt mask. | |||
* @arg DMA_IT_HT: Half transfer complete interrupt mask. | |||
* @arg DMA_IT_TE: Transfer error interrupt mask. | |||
* @arg DMA_IT_FE: FIFO error interrupt mask. | |||
* @arg DMA_IT_DME: Direct mode error interrupt. | |||
* @retval None | |||
*/ | |||
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ | |||
((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) | |||
/** | |||
* @brief Disable the specified DMA Stream interrupts. | |||
* @param __HANDLE__ DMA handle | |||
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. | |||
* This parameter can be any combination of the following values: | |||
* @arg DMA_IT_TC: Transfer complete interrupt mask. | |||
* @arg DMA_IT_HT: Half transfer complete interrupt mask. | |||
* @arg DMA_IT_TE: Transfer error interrupt mask. | |||
* @arg DMA_IT_FE: FIFO error interrupt mask. | |||
* @arg DMA_IT_DME: Direct mode error interrupt. | |||
* @retval None | |||
*/ | |||
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ | |||
((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) | |||
/** | |||
* @brief Check whether the specified DMA Stream interrupt is enabled or disabled. | |||
* @param __HANDLE__ DMA handle | |||
* @param __INTERRUPT__ specifies the DMA interrupt source to check. | |||
* This parameter can be one of the following values: | |||
* @arg DMA_IT_TC: Transfer complete interrupt mask. | |||
* @arg DMA_IT_HT: Half transfer complete interrupt mask. | |||
* @arg DMA_IT_TE: Transfer error interrupt mask. | |||
* @arg DMA_IT_FE: FIFO error interrupt mask. | |||
* @arg DMA_IT_DME: Direct mode error interrupt. | |||
* @retval The state of DMA_IT. | |||
*/ | |||
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ | |||
((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ | |||
((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) | |||
/** | |||
* @brief Writes the number of data units to be transferred on the DMA Stream. | |||
* @param __HANDLE__ DMA handle | |||
* @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) | |||
* Number of data items depends only on the Peripheral data format. | |||
* | |||
* @note If Peripheral data format is Bytes: number of data units is equal | |||
* to total number of bytes to be transferred. | |||
* | |||
* @note If Peripheral data format is Half-Word: number of data units is | |||
* equal to total number of bytes to be transferred / 2. | |||
* | |||
* @note If Peripheral data format is Word: number of data units is equal | |||
* to total number of bytes to be transferred / 4. | |||
* | |||
* @retval The number of remaining data units in the current DMAy Streamx transfer. | |||
*/ | |||
#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) | |||
/** | |||
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer. | |||
* @param __HANDLE__ DMA handle | |||
* | |||
* @retval The number of remaining data units in the current DMA Stream transfer. | |||
*/ | |||
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) | |||
/* Include DMA HAL Extension module */ | |||
#include "stm32f4xx_hal_dma_ex.h" | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup DMA_Exported_Functions DMA Exported Functions | |||
* @brief DMA Exported functions | |||
* @{ | |||
*/ | |||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions | |||
* @brief Initialization and de-initialization functions | |||
* @{ | |||
*/ | |||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); | |||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions | |||
* @brief I/O operation functions | |||
* @{ | |||
*/ | |||
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); | |||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); | |||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); | |||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); | |||
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); | |||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); | |||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions | |||
* @brief Peripheral State functions | |||
* @{ | |||
*/ | |||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); | |||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private Constants -------------------------------------------------------------*/ | |||
/** @defgroup DMA_Private_Constants DMA Private Constants | |||
* @brief DMA private defines and constants | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup DMA_Private_Macros DMA Private Macros | |||
* @brief DMA private macros | |||
* @{ | |||
*/ | |||
#if defined (DMA_SxCR_CHSEL_3) | |||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ | |||
((CHANNEL) == DMA_CHANNEL_1) || \ | |||
((CHANNEL) == DMA_CHANNEL_2) || \ | |||
((CHANNEL) == DMA_CHANNEL_3) || \ | |||
((CHANNEL) == DMA_CHANNEL_4) || \ | |||
((CHANNEL) == DMA_CHANNEL_5) || \ | |||
((CHANNEL) == DMA_CHANNEL_6) || \ | |||
((CHANNEL) == DMA_CHANNEL_7) || \ | |||
((CHANNEL) == DMA_CHANNEL_8) || \ | |||
((CHANNEL) == DMA_CHANNEL_9) || \ | |||
((CHANNEL) == DMA_CHANNEL_10)|| \ | |||
((CHANNEL) == DMA_CHANNEL_11)|| \ | |||
((CHANNEL) == DMA_CHANNEL_12)|| \ | |||
((CHANNEL) == DMA_CHANNEL_13)|| \ | |||
((CHANNEL) == DMA_CHANNEL_14)|| \ | |||
((CHANNEL) == DMA_CHANNEL_15)) | |||
#else | |||
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ | |||
((CHANNEL) == DMA_CHANNEL_1) || \ | |||
((CHANNEL) == DMA_CHANNEL_2) || \ | |||
((CHANNEL) == DMA_CHANNEL_3) || \ | |||
((CHANNEL) == DMA_CHANNEL_4) || \ | |||
((CHANNEL) == DMA_CHANNEL_5) || \ | |||
((CHANNEL) == DMA_CHANNEL_6) || \ | |||
((CHANNEL) == DMA_CHANNEL_7)) | |||
#endif /* DMA_SxCR_CHSEL_3 */ | |||
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ | |||
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ | |||
((DIRECTION) == DMA_MEMORY_TO_MEMORY)) | |||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) | |||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ | |||
((STATE) == DMA_PINC_DISABLE)) | |||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ | |||
((STATE) == DMA_MINC_DISABLE)) | |||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ | |||
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ | |||
((SIZE) == DMA_PDATAALIGN_WORD)) | |||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ | |||
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ | |||
((SIZE) == DMA_MDATAALIGN_WORD )) | |||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ | |||
((MODE) == DMA_CIRCULAR) || \ | |||
((MODE) == DMA_PFCTRL)) | |||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ | |||
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ | |||
((PRIORITY) == DMA_PRIORITY_HIGH) || \ | |||
((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) | |||
#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ | |||
((STATE) == DMA_FIFOMODE_ENABLE)) | |||
#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ | |||
((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ | |||
((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ | |||
((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) | |||
#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ | |||
((BURST) == DMA_MBURST_INC4) || \ | |||
((BURST) == DMA_MBURST_INC8) || \ | |||
((BURST) == DMA_MBURST_INC16)) | |||
#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ | |||
((BURST) == DMA_PBURST_INC4) || \ | |||
((BURST) == DMA_PBURST_INC8) || \ | |||
((BURST) == DMA_PBURST_INC16)) | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup DMA_Private_Functions DMA Private Functions | |||
* @brief DMA private functions | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_DMA_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,104 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_dma_ex.h | |||
* @author MCD Application Team | |||
* @brief Header file of DMA HAL extension module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_DMA_EX_H | |||
#define __STM32F4xx_HAL_DMA_EX_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup DMAEx | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types | |||
* @brief DMAEx Exported types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief HAL DMA Memory definition | |||
*/ | |||
typedef enum | |||
{ | |||
MEMORY0 = 0x00U, /*!< Memory 0 */ | |||
MEMORY1 = 0x01U /*!< Memory 1 */ | |||
}HAL_DMA_MemoryTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions | |||
* @brief DMAEx Exported functions | |||
* @{ | |||
*/ | |||
/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions | |||
* @brief Extended features functions | |||
* @{ | |||
*/ | |||
/* IO operation functions *******************************************************/ | |||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); | |||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); | |||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions | |||
* @brief DMAEx Private functions | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /*__STM32F4xx_HAL_DMA_EX_H*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,368 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_exti.h | |||
* @author MCD Application Team | |||
* @brief Header file of EXTI HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2018 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef STM32f4xx_HAL_EXTI_H | |||
#define STM32f4xx_HAL_EXTI_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup EXTI EXTI | |||
* @brief EXTI HAL module driver | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup EXTI_Exported_Types EXTI Exported Types | |||
* @{ | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_EXTI_COMMON_CB_ID = 0x00U | |||
} EXTI_CallbackIDTypeDef; | |||
/** | |||
* @brief EXTI Handle structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t Line; /*!< Exti line number */ | |||
void (* PendingCallback)(void); /*!< Exti pending callback */ | |||
} EXTI_HandleTypeDef; | |||
/** | |||
* @brief EXTI Configuration structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t Line; /*!< The Exti line to be configured. This parameter | |||
can be a value of @ref EXTI_Line */ | |||
uint32_t Mode; /*!< The Exit Mode to be configured for a core. | |||
This parameter can be a combination of @ref EXTI_Mode */ | |||
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter | |||
can be a value of @ref EXTI_Trigger */ | |||
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. | |||
This parameter is only possible for line 0 to 15. It | |||
can be a value of @ref EXTI_GPIOSel */ | |||
} EXTI_ConfigTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup EXTI_Line EXTI Line | |||
* @{ | |||
*/ | |||
#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ | |||
#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ | |||
#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ | |||
#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ | |||
#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ | |||
#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ | |||
#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ | |||
#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ | |||
#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ | |||
#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ | |||
#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ | |||
#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ | |||
#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ | |||
#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ | |||
#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ | |||
#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ | |||
#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ | |||
#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ | |||
#if defined(EXTI_IMR_IM18) | |||
#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ | |||
#else | |||
#define EXTI_LINE_18 (EXTI_RESERVED | 0x12u) /*!< No interrupt supported in this line */ | |||
#endif /* EXTI_IMR_IM18 */ | |||
#if defined(EXTI_IMR_IM19) | |||
#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ | |||
#else | |||
#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ | |||
#endif /* EXTI_IMR_IM19 */ | |||
#if defined(EXTI_IMR_IM20) | |||
#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ | |||
#else | |||
#define EXTI_LINE_20 (EXTI_RESERVED | 0x14u) /*!< No interrupt supported in this line */ | |||
#endif /* EXTI_IMR_IM20 */ | |||
#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ | |||
#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ | |||
#if defined(EXTI_IMR_IM23) | |||
#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */ | |||
#endif /* EXTI_IMR_IM23 */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup EXTI_Mode EXTI Mode | |||
* @{ | |||
*/ | |||
#define EXTI_MODE_NONE 0x00000000u | |||
#define EXTI_MODE_INTERRUPT 0x00000001u | |||
#define EXTI_MODE_EVENT 0x00000002u | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup EXTI_Trigger EXTI Trigger | |||
* @{ | |||
*/ | |||
#define EXTI_TRIGGER_NONE 0x00000000u | |||
#define EXTI_TRIGGER_RISING 0x00000001u | |||
#define EXTI_TRIGGER_FALLING 0x00000002u | |||
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup EXTI_GPIOSel EXTI GPIOSel | |||
* @brief | |||
* @{ | |||
*/ | |||
#define EXTI_GPIOA 0x00000000u | |||
#define EXTI_GPIOB 0x00000001u | |||
#define EXTI_GPIOC 0x00000002u | |||
#if defined (GPIOD) | |||
#define EXTI_GPIOD 0x00000003u | |||
#endif /* GPIOD */ | |||
#if defined (GPIOE) | |||
#define EXTI_GPIOE 0x00000004u | |||
#endif /* GPIOE */ | |||
#if defined (GPIOF) | |||
#define EXTI_GPIOF 0x00000005u | |||
#endif /* GPIOF */ | |||
#if defined (GPIOG) | |||
#define EXTI_GPIOG 0x00000006u | |||
#endif /* GPIOG */ | |||
#if defined (GPIOH) | |||
#define EXTI_GPIOH 0x00000007u | |||
#endif /* GPIOH */ | |||
#if defined (GPIOI) | |||
#define EXTI_GPIOI 0x00000008u | |||
#endif /* GPIOI */ | |||
#if defined (GPIOJ) | |||
#define EXTI_GPIOJ 0x00000009u | |||
#endif /* GPIOJ */ | |||
#if defined (GPIOK) | |||
#define EXTI_GPIOK 0x0000000Au | |||
#endif /* GPIOK */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private constants --------------------------------------------------------*/ | |||
/** @defgroup EXTI_Private_Constants EXTI Private Constants | |||
* @{ | |||
*/ | |||
/** | |||
* @brief EXTI Line property definition | |||
*/ | |||
#define EXTI_PROPERTY_SHIFT 24u | |||
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) | |||
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) | |||
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) | |||
#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) | |||
/** | |||
* @brief EXTI bit usage | |||
*/ | |||
#define EXTI_PIN_MASK 0x0000001Fu | |||
/** | |||
* @brief EXTI Mask for interrupt & event mode | |||
*/ | |||
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) | |||
/** | |||
* @brief EXTI Mask for trigger possibilities | |||
*/ | |||
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) | |||
/** | |||
* @brief EXTI Line number | |||
*/ | |||
#if defined(EXTI_IMR_IM23) | |||
#define EXTI_LINE_NB 24UL | |||
#else | |||
#define EXTI_LINE_NB 23UL | |||
#endif /* EXTI_IMR_IM23 */ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup EXTI_Private_Macros EXTI Private Macros | |||
* @{ | |||
*/ | |||
#define IS_EXTI_LINE(__LINE__) ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ | |||
((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ | |||
(((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ | |||
(((__LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) | |||
#define IS_EXTI_MODE(__LINE__) ((((__LINE__) & EXTI_MODE_MASK) != 0x00u) && \ | |||
(((__LINE__) & ~EXTI_MODE_MASK) == 0x00u)) | |||
#define IS_EXTI_TRIGGER(__LINE__) (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) | |||
#define IS_EXTI_PENDING_EDGE(__LINE__) ((__LINE__) == EXTI_TRIGGER_RISING_FALLING) | |||
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) | |||
#if !defined (GPIOD) | |||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ | |||
((__PORT__) == EXTI_GPIOB) || \ | |||
((__PORT__) == EXTI_GPIOC) || \ | |||
((__PORT__) == EXTI_GPIOH)) | |||
#elif !defined (GPIOE) | |||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ | |||
((__PORT__) == EXTI_GPIOB) || \ | |||
((__PORT__) == EXTI_GPIOC) || \ | |||
((__PORT__) == EXTI_GPIOD) || \ | |||
((__PORT__) == EXTI_GPIOH)) | |||
#elif !defined (GPIOF) | |||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ | |||
((__PORT__) == EXTI_GPIOB) || \ | |||
((__PORT__) == EXTI_GPIOC) || \ | |||
((__PORT__) == EXTI_GPIOD) || \ | |||
((__PORT__) == EXTI_GPIOE) || \ | |||
((__PORT__) == EXTI_GPIOH)) | |||
#elif !defined (GPIOI) | |||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ | |||
((__PORT__) == EXTI_GPIOB) || \ | |||
((__PORT__) == EXTI_GPIOC) || \ | |||
((__PORT__) == EXTI_GPIOD) || \ | |||
((__PORT__) == EXTI_GPIOE) || \ | |||
((__PORT__) == EXTI_GPIOF) || \ | |||
((__PORT__) == EXTI_GPIOG) || \ | |||
((__PORT__) == EXTI_GPIOH)) | |||
#elif !defined (GPIOJ) | |||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ | |||
((__PORT__) == EXTI_GPIOB) || \ | |||
((__PORT__) == EXTI_GPIOC) || \ | |||
((__PORT__) == EXTI_GPIOD) || \ | |||
((__PORT__) == EXTI_GPIOE) || \ | |||
((__PORT__) == EXTI_GPIOF) || \ | |||
((__PORT__) == EXTI_GPIOG) || \ | |||
((__PORT__) == EXTI_GPIOH) || \ | |||
((__PORT__) == EXTI_GPIOI)) | |||
#else | |||
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ | |||
((__PORT__) == EXTI_GPIOB) || \ | |||
((__PORT__) == EXTI_GPIOC) || \ | |||
((__PORT__) == EXTI_GPIOD) || \ | |||
((__PORT__) == EXTI_GPIOE) || \ | |||
((__PORT__) == EXTI_GPIOF) || \ | |||
((__PORT__) == EXTI_GPIOG) || \ | |||
((__PORT__) == EXTI_GPIOH) || \ | |||
((__PORT__) == EXTI_GPIOI) || \ | |||
((__PORT__) == EXTI_GPIOJ) || \ | |||
((__PORT__) == EXTI_GPIOK)) | |||
#endif /* GPIOD */ | |||
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions | |||
* @brief EXTI Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions | |||
* @brief Configuration functions | |||
* @{ | |||
*/ | |||
/* Configuration functions ****************************************************/ | |||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); | |||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); | |||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); | |||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); | |||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions | |||
* @brief IO operation functions | |||
* @{ | |||
*/ | |||
/* IO operation functions *****************************************************/ | |||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); | |||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); | |||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); | |||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* STM32f4xx_HAL_EXTI_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,428 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_flash.h | |||
* @author MCD Application Team | |||
* @brief Header file of FLASH HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_FLASH_H | |||
#define __STM32F4xx_HAL_FLASH_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup FLASH | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup FLASH_Exported_Types FLASH Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief FLASH Procedure structure definition | |||
*/ | |||
typedef enum | |||
{ | |||
FLASH_PROC_NONE = 0U, | |||
FLASH_PROC_SECTERASE, | |||
FLASH_PROC_MASSERASE, | |||
FLASH_PROC_PROGRAM | |||
} FLASH_ProcedureTypeDef; | |||
/** | |||
* @brief FLASH handle Structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ | |||
__IO uint32_t NbSectorsToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ | |||
__IO uint8_t VoltageForErase; /*Internal variable to provide voltage range selected by user in IT context*/ | |||
__IO uint32_t Sector; /*Internal variable to define the current sector which is erasing*/ | |||
__IO uint32_t Bank; /*Internal variable to save current bank selected during mass erase*/ | |||
__IO uint32_t Address; /*Internal variable to save address selected for program*/ | |||
HAL_LockTypeDef Lock; /* FLASH locking object */ | |||
__IO uint32_t ErrorCode; /* FLASH error code */ | |||
}FLASH_ProcessTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup FLASH_Error_Code FLASH Error Code | |||
* @brief FLASH Error Code | |||
* @{ | |||
*/ | |||
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */ | |||
#define HAL_FLASH_ERROR_RD 0x00000001U /*!< Read Protection error */ | |||
#define HAL_FLASH_ERROR_PGS 0x00000002U /*!< Programming Sequence error */ | |||
#define HAL_FLASH_ERROR_PGP 0x00000004U /*!< Programming Parallelism error */ | |||
#define HAL_FLASH_ERROR_PGA 0x00000008U /*!< Programming Alignment error */ | |||
#define HAL_FLASH_ERROR_WRP 0x00000010U /*!< Write protection error */ | |||
#define HAL_FLASH_ERROR_OPERATION 0x00000020U /*!< Operation Error */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Type_Program FLASH Type Program | |||
* @{ | |||
*/ | |||
#define FLASH_TYPEPROGRAM_BYTE 0x00000000U /*!< Program byte (8-bit) at a specified address */ | |||
#define FLASH_TYPEPROGRAM_HALFWORD 0x00000001U /*!< Program a half-word (16-bit) at a specified address */ | |||
#define FLASH_TYPEPROGRAM_WORD 0x00000002U /*!< Program a word (32-bit) at a specified address */ | |||
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00000003U /*!< Program a double word (64-bit) at a specified address */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Flag_definition FLASH Flag definition | |||
* @brief Flag definition | |||
* @{ | |||
*/ | |||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ | |||
#define FLASH_FLAG_OPERR FLASH_SR_SOP /*!< FLASH operation Error flag */ | |||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ | |||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ | |||
#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ | |||
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming Sequence error flag */ | |||
#if defined(FLASH_SR_RDERR) | |||
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< Read Protection error flag (PCROP) */ | |||
#endif /* FLASH_SR_RDERR */ | |||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition | |||
* @brief FLASH Interrupt definition | |||
* @{ | |||
*/ | |||
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ | |||
#define FLASH_IT_ERR 0x02000000U /*!< Error Interrupt source */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism | |||
* @{ | |||
*/ | |||
#define FLASH_PSIZE_BYTE 0x00000000U | |||
#define FLASH_PSIZE_HALF_WORD 0x00000100U | |||
#define FLASH_PSIZE_WORD 0x00000200U | |||
#define FLASH_PSIZE_DOUBLE_WORD 0x00000300U | |||
#define CR_PSIZE_MASK 0xFFFFFCFFU | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Keys FLASH Keys | |||
* @{ | |||
*/ | |||
#define RDP_KEY ((uint16_t)0x00A5) | |||
#define FLASH_KEY1 0x45670123U | |||
#define FLASH_KEY2 0xCDEF89ABU | |||
#define FLASH_OPT_KEY1 0x08192A3BU | |||
#define FLASH_OPT_KEY2 0x4C5D6E7FU | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Set the FLASH Latency. | |||
* @param __LATENCY__ FLASH Latency | |||
* The value of this parameter depend on device used within the same series | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__)) | |||
/** | |||
* @brief Get the FLASH Latency. | |||
* @retval FLASH Latency | |||
* The value of this parameter depend on device used within the same series | |||
*/ | |||
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) | |||
/** | |||
* @brief Enable the FLASH prefetch buffer. | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) | |||
/** | |||
* @brief Disable the FLASH prefetch buffer. | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) | |||
/** | |||
* @brief Enable the FLASH instruction cache. | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_ICEN) | |||
/** | |||
* @brief Disable the FLASH instruction cache. | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_ICEN)) | |||
/** | |||
* @brief Enable the FLASH data cache. | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_DATA_CACHE_ENABLE() (FLASH->ACR |= FLASH_ACR_DCEN) | |||
/** | |||
* @brief Disable the FLASH data cache. | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_DATA_CACHE_DISABLE() (FLASH->ACR &= (~FLASH_ACR_DCEN)) | |||
/** | |||
* @brief Resets the FLASH instruction Cache. | |||
* @note This function must be used only when the Instruction Cache is disabled. | |||
* @retval None | |||
*/ | |||
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST; \ | |||
FLASH->ACR &= ~FLASH_ACR_ICRST; \ | |||
}while(0U) | |||
/** | |||
* @brief Resets the FLASH data Cache. | |||
* @note This function must be used only when the data Cache is disabled. | |||
* @retval None | |||
*/ | |||
#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST; \ | |||
FLASH->ACR &= ~FLASH_ACR_DCRST; \ | |||
}while(0U) | |||
/** | |||
* @brief Enable the specified FLASH interrupt. | |||
* @param __INTERRUPT__ FLASH interrupt | |||
* This parameter can be any combination of the following values: | |||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt | |||
* @arg FLASH_IT_ERR: Error Interrupt | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) | |||
/** | |||
* @brief Disable the specified FLASH interrupt. | |||
* @param __INTERRUPT__ FLASH interrupt | |||
* This parameter can be any combination of the following values: | |||
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt | |||
* @arg FLASH_IT_ERR: Error Interrupt | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) | |||
/** | |||
* @brief Get the specified FLASH flag status. | |||
* @param __FLAG__ specifies the FLASH flags to check. | |||
* This parameter can be any combination of the following values: | |||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag | |||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag | |||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag | |||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag | |||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag | |||
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag | |||
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) | |||
* @arg FLASH_FLAG_BSY : FLASH Busy flag | |||
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices | |||
* @retval The new state of __FLAG__ (SET or RESET). | |||
*/ | |||
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) | |||
/** | |||
* @brief Clear the specified FLASH flags. | |||
* @param __FLAG__ specifies the FLASH flags to clear. | |||
* This parameter can be any combination of the following values: | |||
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag | |||
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag | |||
* @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag | |||
* @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag | |||
* @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag | |||
* @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag | |||
* @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*) | |||
* (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices | |||
* @retval none | |||
*/ | |||
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) | |||
/** | |||
* @} | |||
*/ | |||
/* Include FLASH HAL Extension module */ | |||
#include "stm32f4xx_hal_flash_ex.h" | |||
#include "stm32f4xx_hal_flash_ramfunc.h" | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup FLASH_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup FLASH_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
/* Program operation functions ***********************************************/ | |||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); | |||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); | |||
/* FLASH IRQ handler method */ | |||
void HAL_FLASH_IRQHandler(void); | |||
/* Callbacks in non blocking modes */ | |||
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); | |||
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup FLASH_Exported_Functions_Group2 | |||
* @{ | |||
*/ | |||
/* Peripheral Control functions **********************************************/ | |||
HAL_StatusTypeDef HAL_FLASH_Unlock(void); | |||
HAL_StatusTypeDef HAL_FLASH_Lock(void); | |||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); | |||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); | |||
/* Option bytes control */ | |||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup FLASH_Exported_Functions_Group3 | |||
* @{ | |||
*/ | |||
/* Peripheral State functions ************************************************/ | |||
uint32_t HAL_FLASH_GetError(void); | |||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/** @defgroup FLASH_Private_Variables FLASH Private Variables | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup FLASH_Private_Constants FLASH Private Constants | |||
* @{ | |||
*/ | |||
/** | |||
* @brief ACR register byte 0 (Bits[7:0]) base address | |||
*/ | |||
#define ACR_BYTE0_ADDRESS 0x40023C00U | |||
/** | |||
* @brief OPTCR register byte 0 (Bits[7:0]) base address | |||
*/ | |||
#define OPTCR_BYTE0_ADDRESS 0x40023C14U | |||
/** | |||
* @brief OPTCR register byte 1 (Bits[15:8]) base address | |||
*/ | |||
#define OPTCR_BYTE1_ADDRESS 0x40023C15U | |||
/** | |||
* @brief OPTCR register byte 2 (Bits[23:16]) base address | |||
*/ | |||
#define OPTCR_BYTE2_ADDRESS 0x40023C16U | |||
/** | |||
* @brief OPTCR register byte 3 (Bits[31:24]) base address | |||
*/ | |||
#define OPTCR_BYTE3_ADDRESS 0x40023C17U | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup FLASH_Private_Macros FLASH Private Macros | |||
* @{ | |||
*/ | |||
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters | |||
* @{ | |||
*/ | |||
#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ | |||
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ | |||
((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ | |||
((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup FLASH_Private_Functions FLASH Private Functions | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_FLASH_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,79 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_flash_ramfunc.h | |||
* @author MCD Application Team | |||
* @brief Header file of FLASH RAMFUNC driver. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_FLASH_RAMFUNC_H | |||
#define __STM32F4xx_FLASH_RAMFUNC_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\ | |||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup FLASH_RAMFUNC | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void); | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void); | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void); | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,309 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_gpio.h | |||
* @author MCD Application Team | |||
* @brief Header file of GPIO HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_GPIO_H | |||
#define __STM32F4xx_HAL_GPIO_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup GPIO | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup GPIO_Exported_Types GPIO Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief GPIO Init structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t Pin; /*!< Specifies the GPIO pins to be configured. | |||
This parameter can be any value of @ref GPIO_pins_define */ | |||
uint32_t Mode; /*!< Specifies the operating mode for the selected pins. | |||
This parameter can be a value of @ref GPIO_mode_define */ | |||
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. | |||
This parameter can be a value of @ref GPIO_pull_define */ | |||
uint32_t Speed; /*!< Specifies the speed for the selected pins. | |||
This parameter can be a value of @ref GPIO_speed_define */ | |||
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. | |||
This parameter can be a value of @ref GPIO_Alternate_function_selection */ | |||
}GPIO_InitTypeDef; | |||
/** | |||
* @brief GPIO Bit SET and Bit RESET enumeration | |||
*/ | |||
typedef enum | |||
{ | |||
GPIO_PIN_RESET = 0, | |||
GPIO_PIN_SET | |||
}GPIO_PinState; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup GPIO_pins_define GPIO pins define | |||
* @{ | |||
*/ | |||
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ | |||
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */ | |||
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */ | |||
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */ | |||
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */ | |||
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */ | |||
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */ | |||
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */ | |||
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */ | |||
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */ | |||
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */ | |||
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */ | |||
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */ | |||
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */ | |||
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ | |||
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ | |||
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ | |||
#define GPIO_PIN_MASK 0x0000FFFFU /* PIN mask for assert test */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup GPIO_mode_define GPIO mode define | |||
* @brief GPIO Configuration Mode | |||
* Elements values convention: 0xX0yz00YZ | |||
* - X : GPIO mode or EXTI Mode | |||
* - y : External IT or Event trigger detection | |||
* - z : IO configuration on External IT or Event | |||
* - Y : Output type (Push Pull or Open Drain) | |||
* - Z : IO Direction mode (Input, Output, Alternate or Analog) | |||
* @{ | |||
*/ | |||
#define GPIO_MODE_INPUT 0x00000000U /*!< Input Floating Mode */ | |||
#define GPIO_MODE_OUTPUT_PP 0x00000001U /*!< Output Push Pull Mode */ | |||
#define GPIO_MODE_OUTPUT_OD 0x00000011U /*!< Output Open Drain Mode */ | |||
#define GPIO_MODE_AF_PP 0x00000002U /*!< Alternate Function Push Pull Mode */ | |||
#define GPIO_MODE_AF_OD 0x00000012U /*!< Alternate Function Open Drain Mode */ | |||
#define GPIO_MODE_ANALOG 0x00000003U /*!< Analog Mode */ | |||
#define GPIO_MODE_IT_RISING 0x10110000U /*!< External Interrupt Mode with Rising edge trigger detection */ | |||
#define GPIO_MODE_IT_FALLING 0x10210000U /*!< External Interrupt Mode with Falling edge trigger detection */ | |||
#define GPIO_MODE_IT_RISING_FALLING 0x10310000U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ | |||
#define GPIO_MODE_EVT_RISING 0x10120000U /*!< External Event Mode with Rising edge trigger detection */ | |||
#define GPIO_MODE_EVT_FALLING 0x10220000U /*!< External Event Mode with Falling edge trigger detection */ | |||
#define GPIO_MODE_EVT_RISING_FALLING 0x10320000U /*!< External Event Mode with Rising/Falling edge trigger detection */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup GPIO_speed_define GPIO speed define | |||
* @brief GPIO Output Maximum frequency | |||
* @{ | |||
*/ | |||
#define GPIO_SPEED_FREQ_LOW 0x00000000U /*!< IO works at 2 MHz, please refer to the product datasheet */ | |||
#define GPIO_SPEED_FREQ_MEDIUM 0x00000001U /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */ | |||
#define GPIO_SPEED_FREQ_HIGH 0x00000002U /*!< range 25 MHz to 100 MHz, please refer to the product datasheet */ | |||
#define GPIO_SPEED_FREQ_VERY_HIGH 0x00000003U /*!< range 50 MHz to 200 MHz, please refer to the product datasheet */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup GPIO_pull_define GPIO pull define | |||
* @brief GPIO Pull-Up or Pull-Down Activation | |||
* @{ | |||
*/ | |||
#define GPIO_NOPULL 0x00000000U /*!< No Pull-up or Pull-down activation */ | |||
#define GPIO_PULLUP 0x00000001U /*!< Pull-up activation */ | |||
#define GPIO_PULLDOWN 0x00000002U /*!< Pull-down activation */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Checks whether the specified EXTI line flag is set or not. | |||
* @param __EXTI_LINE__ specifies the EXTI line flag to check. | |||
* This parameter can be GPIO_PIN_x where x can be(0..15) | |||
* @retval The new state of __EXTI_LINE__ (SET or RESET). | |||
*/ | |||
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) | |||
/** | |||
* @brief Clears the EXTI's line pending flags. | |||
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear. | |||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) | |||
* @retval None | |||
*/ | |||
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) | |||
/** | |||
* @brief Checks whether the specified EXTI line is asserted or not. | |||
* @param __EXTI_LINE__ specifies the EXTI line to check. | |||
* This parameter can be GPIO_PIN_x where x can be(0..15) | |||
* @retval The new state of __EXTI_LINE__ (SET or RESET). | |||
*/ | |||
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) | |||
/** | |||
* @brief Clears the EXTI's line pending bits. | |||
* @param __EXTI_LINE__ specifies the EXTI lines to clear. | |||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15) | |||
* @retval None | |||
*/ | |||
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) | |||
/** | |||
* @brief Generates a Software interrupt on selected EXTI line. | |||
* @param __EXTI_LINE__ specifies the EXTI line to check. | |||
* This parameter can be GPIO_PIN_x where x can be(0..15) | |||
* @retval None | |||
*/ | |||
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) | |||
/** | |||
* @} | |||
*/ | |||
/* Include GPIO HAL Extension module */ | |||
#include "stm32f4xx_hal_gpio_ex.h" | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup GPIO_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup GPIO_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
/* Initialization and de-initialization functions *****************************/ | |||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); | |||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup GPIO_Exported_Functions_Group2 | |||
* @{ | |||
*/ | |||
/* IO operation functions *****************************************************/ | |||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); | |||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); | |||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); | |||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); | |||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); | |||
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup GPIO_Private_Constants GPIO Private Constants | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup GPIO_Private_Macros GPIO Private Macros | |||
* @{ | |||
*/ | |||
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) | |||
#define IS_GPIO_PIN(PIN) (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U)) | |||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ | |||
((MODE) == GPIO_MODE_OUTPUT_PP) ||\ | |||
((MODE) == GPIO_MODE_OUTPUT_OD) ||\ | |||
((MODE) == GPIO_MODE_AF_PP) ||\ | |||
((MODE) == GPIO_MODE_AF_OD) ||\ | |||
((MODE) == GPIO_MODE_IT_RISING) ||\ | |||
((MODE) == GPIO_MODE_IT_FALLING) ||\ | |||
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ | |||
((MODE) == GPIO_MODE_EVT_RISING) ||\ | |||
((MODE) == GPIO_MODE_EVT_FALLING) ||\ | |||
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ | |||
((MODE) == GPIO_MODE_ANALOG)) | |||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \ | |||
((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH)) | |||
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ | |||
((PULL) == GPIO_PULLDOWN)) | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup GPIO_Private_Functions GPIO Private Functions | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_GPIO_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,431 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_pwr.h | |||
* @author MCD Application Team | |||
* @brief Header file of PWR HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_PWR_H | |||
#define __STM32F4xx_HAL_PWR_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup PWR | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup PWR_Exported_Types PWR Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief PWR PVD configuration structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. | |||
This parameter can be a value of @ref PWR_PVD_detection_level */ | |||
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. | |||
This parameter can be a value of @ref PWR_PVD_Mode */ | |||
}PWR_PVDTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup PWR_Exported_Constants PWR Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins | |||
* @{ | |||
*/ | |||
#define PWR_WAKEUP_PIN1 0x00000100U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_PVD_detection_level PWR PVD detection level | |||
* @{ | |||
*/ | |||
#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 | |||
#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 | |||
#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 | |||
#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 | |||
#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 | |||
#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 | |||
#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 | |||
#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage | |||
(Compare internally to VREFINT) */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_PVD_Mode PWR PVD Mode | |||
* @{ | |||
*/ | |||
#define PWR_PVD_MODE_NORMAL 0x00000000U /*!< basic mode is used */ | |||
#define PWR_PVD_MODE_IT_RISING 0x00010001U /*!< External Interrupt Mode with Rising edge trigger detection */ | |||
#define PWR_PVD_MODE_IT_FALLING 0x00010002U /*!< External Interrupt Mode with Falling edge trigger detection */ | |||
#define PWR_PVD_MODE_IT_RISING_FALLING 0x00010003U /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ | |||
#define PWR_PVD_MODE_EVENT_RISING 0x00020001U /*!< Event Mode with Rising edge trigger detection */ | |||
#define PWR_PVD_MODE_EVENT_FALLING 0x00020002U /*!< Event Mode with Falling edge trigger detection */ | |||
#define PWR_PVD_MODE_EVENT_RISING_FALLING 0x00020003U /*!< Event Mode with Rising/Falling edge trigger detection */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode | |||
* @{ | |||
*/ | |||
#define PWR_MAINREGULATOR_ON 0x00000000U | |||
#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry | |||
* @{ | |||
*/ | |||
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) | |||
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry | |||
* @{ | |||
*/ | |||
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) | |||
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_Flag PWR Flag | |||
* @{ | |||
*/ | |||
#define PWR_FLAG_WU PWR_CSR_WUF | |||
#define PWR_FLAG_SB PWR_CSR_SBF | |||
#define PWR_FLAG_PVDO PWR_CSR_PVDO | |||
#define PWR_FLAG_BRR PWR_CSR_BRR | |||
#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup PWR_Exported_Macro PWR Exported Macro | |||
* @{ | |||
*/ | |||
/** @brief Check PWR flag is set or not. | |||
* @param __FLAG__ specifies the flag to check. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event | |||
* was received from the WKUP pin or from the RTC alarm (Alarm A | |||
* or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. | |||
* An additional wakeup event is detected if the WKUP pin is enabled | |||
* (by setting the EWUP bit) when the WKUP pin level is already high. | |||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was | |||
* resumed from StandBy mode. | |||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled | |||
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode | |||
* For this reason, this bit is equal to 0 after Standby or reset | |||
* until the PVDE bit is set. | |||
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset | |||
* when the device wakes up from Standby mode or by a system reset | |||
* or power reset. | |||
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage | |||
* scaling output selection is ready. | |||
* @retval The new state of __FLAG__ (TRUE or FALSE). | |||
*/ | |||
#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) | |||
/** @brief Clear the PWR's pending flags. | |||
* @param __FLAG__ specifies the flag to clear. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_FLAG_WU: Wake Up flag | |||
* @arg PWR_FLAG_SB: StandBy flag | |||
*/ | |||
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) | |||
/** | |||
* @brief Enable the PVD Exti Line 16. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @brief Disable the PVD EXTI Line 16. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @brief Enable event on PVD Exti Line 16. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @brief Disable event on PVD Exti Line 16. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @brief Enable the PVD Extended Interrupt Rising Trigger. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) | |||
/** | |||
* @brief Disable the PVD Extended Interrupt Rising Trigger. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) | |||
/** | |||
* @brief Enable the PVD Extended Interrupt Falling Trigger. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) | |||
/** | |||
* @brief Disable the PVD Extended Interrupt Falling Trigger. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) | |||
/** | |||
* @brief PVD EXTI line configuration: set rising & falling edge trigger. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\ | |||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\ | |||
}while(0U) | |||
/** | |||
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. | |||
* This parameter can be: | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\ | |||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\ | |||
}while(0U) | |||
/** | |||
* @brief checks whether the specified PVD Exti interrupt flag is set or not. | |||
* @retval EXTI PVD Line Status. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @brief Clear the PVD Exti flag. | |||
* @retval None. | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @brief Generates a Software interrupt on PVD EXTI line. | |||
* @retval None | |||
*/ | |||
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) | |||
/** | |||
* @} | |||
*/ | |||
/* Include PWR HAL Extension module */ | |||
#include "stm32f4xx_hal_pwr_ex.h" | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup PWR_Exported_Functions PWR Exported Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions | |||
* @{ | |||
*/ | |||
/* Initialization and de-initialization functions *****************************/ | |||
void HAL_PWR_DeInit(void); | |||
void HAL_PWR_EnableBkUpAccess(void); | |||
void HAL_PWR_DisableBkUpAccess(void); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions | |||
* @{ | |||
*/ | |||
/* Peripheral Control functions **********************************************/ | |||
/* PVD configuration */ | |||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); | |||
void HAL_PWR_EnablePVD(void); | |||
void HAL_PWR_DisablePVD(void); | |||
/* WakeUp pins configuration */ | |||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); | |||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); | |||
/* Low Power modes entry */ | |||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); | |||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); | |||
void HAL_PWR_EnterSTANDBYMode(void); | |||
/* Power PVD IRQ Handler */ | |||
void HAL_PWR_PVD_IRQHandler(void); | |||
void HAL_PWR_PVDCallback(void); | |||
/* Cortex System Control functions *******************************************/ | |||
void HAL_PWR_EnableSleepOnExit(void); | |||
void HAL_PWR_DisableSleepOnExit(void); | |||
void HAL_PWR_EnableSEVOnPend(void); | |||
void HAL_PWR_DisableSEVOnPend(void); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup PWR_Private_Constants PWR Private Constants | |||
* @{ | |||
*/ | |||
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line | |||
* @{ | |||
*/ | |||
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_register_alias_address PWR Register alias address | |||
* @{ | |||
*/ | |||
/* ------------- PWR registers bit address in the alias region ---------------*/ | |||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) | |||
#define PWR_CR_OFFSET 0x00U | |||
#define PWR_CSR_OFFSET 0x04U | |||
#define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET) | |||
#define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_CR_register_alias PWR CR Register alias address | |||
* @{ | |||
*/ | |||
/* --- CR Register ---*/ | |||
/* Alias word address of DBP bit */ | |||
#define DBP_BIT_NUMBER PWR_CR_DBP_Pos | |||
#define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) | |||
/* Alias word address of PVDE bit */ | |||
#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos | |||
#define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) | |||
/* Alias word address of VOS bit */ | |||
#define VOS_BIT_NUMBER PWR_CR_VOS_Pos | |||
#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address | |||
* @{ | |||
*/ | |||
/* --- CSR Register ---*/ | |||
/* Alias word address of EWUP bit */ | |||
#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos | |||
#define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup PWR_Private_Macros PWR Private Macros | |||
* @{ | |||
*/ | |||
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters | |||
* @{ | |||
*/ | |||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ | |||
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ | |||
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ | |||
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) | |||
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ | |||
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ | |||
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ | |||
((MODE) == PWR_PVD_MODE_NORMAL)) | |||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ | |||
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) | |||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) | |||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_PWR_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,344 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_pwr_ex.h | |||
* @author MCD Application Team | |||
* @brief Header file of PWR HAL Extension module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_PWR_EX_H | |||
#define __STM32F4xx_HAL_PWR_EX_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup PWREx | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants | |||
* @{ | |||
*/ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |||
/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode | |||
* @{ | |||
*/ | |||
#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS | |||
#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag | |||
* @{ | |||
*/ | |||
#define PWR_FLAG_ODRDY PWR_CSR_ODRDY | |||
#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY | |||
#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY | |||
/** | |||
* @} | |||
*/ | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ | |||
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale | |||
* @{ | |||
*/ | |||
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) | |||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */ | |||
#define PWR_REGULATOR_VOLTAGE_SCALE2 0x00000000U /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */ | |||
#else | |||
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to | |||
180 MHz by activating the over-drive mode. */ | |||
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to | |||
168 MHz by activating the over-drive mode. */ | |||
#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS_0 /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */ | |||
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ | |||
/** | |||
* @} | |||
*/ | |||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ | |||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) | |||
/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins | |||
* @{ | |||
*/ | |||
#define PWR_WAKEUP_PIN2 0x00000080U | |||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ | |||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) | |||
#define PWR_WAKEUP_PIN3 0x00000040U | |||
#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \ | |||
STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || | |||
STM32F413xx || STM32F423xx */ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants | |||
* @{ | |||
*/ | |||
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) | |||
/** @brief macros configure the main internal regulator output voltage. | |||
* @param __REGULATOR__ specifies the regulator output voltage to achieve | |||
* a tradeoff between performance and power consumption when the device does | |||
* not operate at the maximum frequency (refer to the datasheets for more details). | |||
* This parameter can be one of the following values: | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode | |||
* @retval None | |||
*/ | |||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ | |||
__IO uint32_t tmpreg = 0x00U; \ | |||
MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ | |||
/* Delay after an RCC peripheral clock enabling */ \ | |||
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ | |||
UNUSED(tmpreg); \ | |||
} while(0U) | |||
#else | |||
/** @brief macros configure the main internal regulator output voltage. | |||
* @param __REGULATOR__ specifies the regulator output voltage to achieve | |||
* a tradeoff between performance and power consumption when the device does | |||
* not operate at the maximum frequency (refer to the datasheets for more details). | |||
* This parameter can be one of the following values: | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode | |||
* @retval None | |||
*/ | |||
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ | |||
__IO uint32_t tmpreg = 0x00U; \ | |||
MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)); \ | |||
/* Delay after an RCC peripheral clock enabling */ \ | |||
tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS); \ | |||
UNUSED(tmpreg); \ | |||
} while(0U) | |||
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |||
/** @brief Macros to enable or disable the Over drive mode. | |||
* @note These macros can be used only for STM32F42xx/STM3243xx devices. | |||
*/ | |||
#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE) | |||
#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE) | |||
/** @brief Macros to enable or disable the Over drive switching. | |||
* @note These macros can be used only for STM32F42xx/STM3243xx devices. | |||
*/ | |||
#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE) | |||
#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE) | |||
/** @brief Macros to enable or disable the Under drive mode. | |||
* @note This mode is enabled only with STOP low power mode. | |||
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This | |||
* mode is only available when the main regulator or the low power regulator | |||
* is in low voltage mode. | |||
* @note If the Under-drive mode was enabled, it is automatically disabled after | |||
* exiting Stop mode. | |||
* When the voltage regulator operates in Under-drive mode, an additional | |||
* startup delay is induced when waking up from Stop mode. | |||
*/ | |||
#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN) | |||
#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN)) | |||
/** @brief Check PWR flag is set or not. | |||
* @note These macros can be used only for STM32F42xx/STM3243xx devices. | |||
* @param __FLAG__ specifies the flag to check. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode | |||
* is ready | |||
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode | |||
* switching is ready | |||
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode | |||
* is enabled in Stop mode | |||
* @retval The new state of __FLAG__ (TRUE or FALSE). | |||
*/ | |||
#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) | |||
/** @brief Clear the Under-Drive Ready flag. | |||
* @note These macros can be used only for STM32F42xx/STM3243xx devices. | |||
*/ | |||
#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY) | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup PWREx_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
void HAL_PWREx_EnableFlashPowerDown(void); | |||
void HAL_PWREx_DisableFlashPowerDown(void); | |||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); | |||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); | |||
uint32_t HAL_PWREx_GetVoltageRange(void); | |||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); | |||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\ | |||
defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\ | |||
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) | |||
void HAL_PWREx_EnableMainRegulatorLowVoltage(void); | |||
void HAL_PWREx_DisableMainRegulatorLowVoltage(void); | |||
void HAL_PWREx_EnableLowRegulatorLowVoltage(void); | |||
void HAL_PWREx_DisableLowRegulatorLowVoltage(void); | |||
#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\ | |||
STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\ | |||
defined(STM32F469xx) || defined(STM32F479xx) | |||
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); | |||
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); | |||
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup PWREx_Private_Constants PWREx Private Constants | |||
* @{ | |||
*/ | |||
/** @defgroup PWREx_register_alias_address PWREx Register alias address | |||
* @{ | |||
*/ | |||
/* ------------- PWR registers bit address in the alias region ---------------*/ | |||
/* --- CR Register ---*/ | |||
/* Alias word address of FPDS bit */ | |||
#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos | |||
#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U)) | |||
/* Alias word address of ODEN bit */ | |||
#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos | |||
#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U)) | |||
/* Alias word address of ODSWEN bit */ | |||
#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos | |||
#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U)) | |||
/* Alias word address of MRLVDS bit */ | |||
#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos | |||
#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U)) | |||
/* Alias word address of LPLVDS bit */ | |||
#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos | |||
#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U)) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address | |||
* @{ | |||
*/ | |||
/* --- CSR Register ---*/ | |||
/* Alias word address of BRE bit */ | |||
#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos | |||
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U)) | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup PWREx_Private_Macros PWREx Private Macros | |||
* @{ | |||
*/ | |||
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters | |||
* @{ | |||
*/ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |||
#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ | |||
((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ | |||
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) | |||
#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ | |||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) | |||
#else | |||
#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ | |||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ | |||
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) | |||
#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ | |||
#if defined(STM32F446xx) | |||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2)) | |||
#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\ | |||
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\ | |||
defined(STM32F423xx) | |||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \ | |||
((PIN) == PWR_WAKEUP_PIN3)) | |||
#else | |||
#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1) | |||
#endif /* STM32F446xx */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_PWR_EX_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,874 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_rtc.h | |||
* @author MCD Application Team | |||
* @brief Header file of RTC HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_RTC_H | |||
#define __STM32F4xx_HAL_RTC_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup RTC | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup RTC_Exported_Types RTC Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief HAL State structures definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ | |||
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ | |||
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ | |||
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ | |||
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ | |||
}HAL_RTCStateTypeDef; | |||
/** | |||
* @brief RTC Configuration Structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t HourFormat; /*!< Specifies the RTC Hour Format. | |||
This parameter can be a value of @ref RTC_Hour_Formats */ | |||
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. | |||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ | |||
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. | |||
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */ | |||
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. | |||
This parameter can be a value of @ref RTC_Output_selection_Definitions */ | |||
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. | |||
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ | |||
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. | |||
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ | |||
}RTC_InitTypeDef; | |||
/** | |||
* @brief RTC Time structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint8_t Hours; /*!< Specifies the RTC Time Hour. | |||
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. | |||
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ | |||
uint8_t Minutes; /*!< Specifies the RTC Time Minutes. | |||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ | |||
uint8_t Seconds; /*!< Specifies the RTC Time Seconds. | |||
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ | |||
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. | |||
This parameter can be a value of @ref RTC_AM_PM_Definitions */ | |||
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. | |||
This parameter corresponds to a time unit range between [0-1] Second | |||
with [1 Sec / SecondFraction +1] granularity */ | |||
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content | |||
corresponding to Synchronous pre-scaler factor value (PREDIV_S) | |||
This parameter corresponds to a time unit range between [0-1] Second | |||
with [1 Sec / SecondFraction +1] granularity. | |||
This field will be used only by HAL_RTC_GetTime function */ | |||
uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation. | |||
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ | |||
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit | |||
in CR register to store the operation. | |||
This parameter can be a value of @ref RTC_StoreOperation_Definitions */ | |||
}RTC_TimeTypeDef; | |||
/** | |||
* @brief RTC Date structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. | |||
This parameter can be a value of @ref RTC_WeekDay_Definitions */ | |||
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). | |||
This parameter can be a value of @ref RTC_Month_Date_Definitions */ | |||
uint8_t Date; /*!< Specifies the RTC Date. | |||
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ | |||
uint8_t Year; /*!< Specifies the RTC Date Year. | |||
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ | |||
}RTC_DateTypeDef; | |||
/** | |||
* @brief RTC Alarm structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ | |||
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. | |||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */ | |||
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. | |||
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ | |||
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. | |||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ | |||
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. | |||
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. | |||
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ | |||
uint32_t Alarm; /*!< Specifies the alarm . | |||
This parameter can be a value of @ref RTC_Alarms_Definitions */ | |||
}RTC_AlarmTypeDef; | |||
/** | |||
* @brief RTC Handle Structure definition | |||
*/ | |||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) | |||
typedef struct __RTC_HandleTypeDef | |||
#else | |||
typedef struct | |||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ | |||
{ | |||
RTC_TypeDef *Instance; /*!< Register base address */ | |||
RTC_InitTypeDef Init; /*!< RTC required parameters */ | |||
HAL_LockTypeDef Lock; /*!< RTC locking object */ | |||
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */ | |||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) | |||
void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ | |||
void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ | |||
void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ | |||
void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ | |||
void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ | |||
void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ | |||
void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ | |||
void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ | |||
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ | |||
}RTC_HandleTypeDef; | |||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) | |||
/** | |||
* @brief HAL RTC Callback ID enumeration definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ | |||
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */ | |||
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */ | |||
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */ | |||
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ | |||
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */ | |||
HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ | |||
HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ | |||
}HAL_RTC_CallbackIDTypeDef; | |||
/** | |||
* @brief HAL RTC Callback pointer definition | |||
*/ | |||
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */ | |||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup RTC_Exported_Constants RTC Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup RTC_Hour_Formats RTC Hour Formats | |||
* @{ | |||
*/ | |||
#define RTC_HOURFORMAT_24 0x00000000U | |||
#define RTC_HOURFORMAT_12 0x00000040U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions | |||
* @{ | |||
*/ | |||
#define RTC_OUTPUT_DISABLE 0x00000000U | |||
#define RTC_OUTPUT_ALARMA 0x00200000U | |||
#define RTC_OUTPUT_ALARMB 0x00400000U | |||
#define RTC_OUTPUT_WAKEUP 0x00600000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions | |||
* @{ | |||
*/ | |||
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U | |||
#define RTC_OUTPUT_POLARITY_LOW 0x00100000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT | |||
* @{ | |||
*/ | |||
#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U | |||
#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions | |||
* @{ | |||
*/ | |||
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) | |||
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions | |||
* @{ | |||
*/ | |||
#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U | |||
#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U | |||
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions | |||
* @{ | |||
*/ | |||
#define RTC_STOREOPERATION_RESET 0x00000000U | |||
#define RTC_STOREOPERATION_SET 0x00040000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions | |||
* @{ | |||
*/ | |||
#define RTC_FORMAT_BIN 0x00000000U | |||
#define RTC_FORMAT_BCD 0x00000001U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions | |||
* @{ | |||
*/ | |||
/* Coded in BCD format */ | |||
#define RTC_MONTH_JANUARY ((uint8_t)0x01) | |||
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) | |||
#define RTC_MONTH_MARCH ((uint8_t)0x03) | |||
#define RTC_MONTH_APRIL ((uint8_t)0x04) | |||
#define RTC_MONTH_MAY ((uint8_t)0x05) | |||
#define RTC_MONTH_JUNE ((uint8_t)0x06) | |||
#define RTC_MONTH_JULY ((uint8_t)0x07) | |||
#define RTC_MONTH_AUGUST ((uint8_t)0x08) | |||
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) | |||
#define RTC_MONTH_OCTOBER ((uint8_t)0x10) | |||
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) | |||
#define RTC_MONTH_DECEMBER ((uint8_t)0x12) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions | |||
* @{ | |||
*/ | |||
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) | |||
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) | |||
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) | |||
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) | |||
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) | |||
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) | |||
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions | |||
* @{ | |||
*/ | |||
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U | |||
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions | |||
* @{ | |||
*/ | |||
#define RTC_ALARMMASK_NONE 0x00000000U | |||
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 | |||
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 | |||
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 | |||
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 | |||
#define RTC_ALARMMASK_ALL 0x80808080U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions | |||
* @{ | |||
*/ | |||
#define RTC_ALARM_A RTC_CR_ALRAE | |||
#define RTC_ALARM_B RTC_CR_ALRBE | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions | |||
* @{ | |||
*/ | |||
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. | |||
There is no comparison on sub seconds | |||
for Alarm */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm | |||
comparison. Only SS[0] is compared. */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm | |||
comparison. Only SS[1:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm | |||
comparison. Only SS[2:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm | |||
comparison. Only SS[3:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm | |||
comparison. Only SS[4:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm | |||
comparison. Only SS[5:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm | |||
comparison. Only SS[6:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm | |||
comparison. Only SS[7:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm | |||
comparison. Only SS[8:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm | |||
comparison. Only SS[9:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm | |||
comparison. Only SS[10:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm | |||
comparison.Only SS[11:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm | |||
comparison. Only SS[12:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm | |||
comparison.Only SS[13:0] are compared */ | |||
#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match | |||
to activate alarm. */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions | |||
* @{ | |||
*/ | |||
#define RTC_IT_TS 0x00008000U | |||
#define RTC_IT_WUT 0x00004000U | |||
#define RTC_IT_ALRB 0x00002000U | |||
#define RTC_IT_ALRA 0x00001000U | |||
#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */ | |||
#define RTC_IT_TAMP1 0x00020000U | |||
#define RTC_IT_TAMP2 0x00040000U | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions | |||
* @{ | |||
*/ | |||
#define RTC_FLAG_RECALPF 0x00010000U | |||
#define RTC_FLAG_TAMP2F 0x00004000U | |||
#define RTC_FLAG_TAMP1F 0x00002000U | |||
#define RTC_FLAG_TSOVF 0x00001000U | |||
#define RTC_FLAG_TSF 0x00000800U | |||
#define RTC_FLAG_WUTF 0x00000400U | |||
#define RTC_FLAG_ALRBF 0x00000200U | |||
#define RTC_FLAG_ALRAF 0x00000100U | |||
#define RTC_FLAG_INITF 0x00000040U | |||
#define RTC_FLAG_RSF 0x00000020U | |||
#define RTC_FLAG_INITS 0x00000010U | |||
#define RTC_FLAG_SHPF 0x00000008U | |||
#define RTC_FLAG_WUTWF 0x00000004U | |||
#define RTC_FLAG_ALRBWF 0x00000002U | |||
#define RTC_FLAG_ALRAWF 0x00000001U | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup RTC_Exported_Macros RTC Exported Macros | |||
* @{ | |||
*/ | |||
/** @brief Reset RTC handle state | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) | |||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ | |||
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\ | |||
(__HANDLE__)->MspInitCallback = NULL;\ | |||
(__HANDLE__)->MspDeInitCallback = NULL;\ | |||
}while(0u) | |||
#else | |||
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) | |||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ | |||
/** | |||
* @brief Disable the write protection for RTC registers. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ | |||
do{ \ | |||
(__HANDLE__)->Instance->WPR = 0xCAU; \ | |||
(__HANDLE__)->Instance->WPR = 0x53U; \ | |||
} while(0U) | |||
/** | |||
* @brief Enable the write protection for RTC registers. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ | |||
do{ \ | |||
(__HANDLE__)->Instance->WPR = 0xFFU; \ | |||
} while(0U) | |||
/** | |||
* @brief Enable the RTC ALARMA peripheral. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) | |||
/** | |||
* @brief Disable the RTC ALARMA peripheral. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) | |||
/** | |||
* @brief Enable the RTC ALARMB peripheral. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) | |||
/** | |||
* @brief Disable the RTC ALARMB peripheral. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) | |||
/** | |||
* @brief Enable the RTC Alarm interrupt. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. | |||
* This parameter can be any combination of the following values: | |||
* @arg RTC_IT_ALRA: Alarm A interrupt | |||
* @arg RTC_IT_ALRB: Alarm B interrupt | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) | |||
/** | |||
* @brief Disable the RTC Alarm interrupt. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. | |||
* This parameter can be any combination of the following values: | |||
* @arg RTC_IT_ALRA: Alarm A interrupt | |||
* @arg RTC_IT_ALRB: Alarm B interrupt | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) | |||
/** | |||
* @brief Check whether the specified RTC Alarm interrupt has occurred or not. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. | |||
* This parameter can be: | |||
* @arg RTC_IT_ALRA: Alarm A interrupt | |||
* @arg RTC_IT_ALRB: Alarm B interrupt | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) | |||
/** | |||
* @brief Get the selected RTC Alarm's flag status. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @param __FLAG__ specifies the RTC Alarm Flag to check. | |||
* This parameter can be: | |||
* @arg RTC_FLAG_ALRAF | |||
* @arg RTC_FLAG_ALRBF | |||
* @arg RTC_FLAG_ALRAWF | |||
* @arg RTC_FLAG_ALRBWF | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) | |||
/** | |||
* @brief Clear the RTC Alarm's pending flags. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. | |||
* This parameter can be: | |||
* @arg RTC_FLAG_ALRAF | |||
* @arg RTC_FLAG_ALRBF | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) | |||
/** | |||
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not. | |||
* @param __HANDLE__ specifies the RTC handle. | |||
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. | |||
* This parameter can be: | |||
* @arg RTC_IT_ALRA: Alarm A interrupt | |||
* @arg RTC_IT_ALRB: Alarm B interrupt | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) | |||
/** | |||
* @brief Enable interrupt on the RTC Alarm associated Exti line. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @brief Disable interrupt on the RTC Alarm associated Exti line. | |||
* @retval None | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) | |||
/** | |||
* @brief Enable event on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @brief Disable event on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) | |||
/** | |||
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) | |||
/** | |||
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) | |||
/** | |||
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ | |||
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\ | |||
} while(0U) | |||
/** | |||
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\ | |||
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\ | |||
} while(0U) | |||
/** | |||
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. | |||
* @retval Line Status. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @brief Clear the RTC Alarm associated Exti line flag. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @brief Generate a Software interrupt on RTC Alarm associated Exti line. | |||
* @retval None. | |||
*/ | |||
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) | |||
/** | |||
* @} | |||
*/ | |||
/* Include RTC HAL Extension module */ | |||
#include "stm32f4xx_hal_rtc_ex.h" | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup RTC_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup RTC_Exported_Functions_Group1 | |||
* @{ | |||
*/ | |||
/* Initialization and de-initialization functions ****************************/ | |||
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); | |||
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); | |||
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); | |||
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); | |||
/* Callbacks Register/UnRegister functions ***********************************/ | |||
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) | |||
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); | |||
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); | |||
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup RTC_Exported_Functions_Group2 | |||
* @{ | |||
*/ | |||
/* RTC Time and Date functions ************************************************/ | |||
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); | |||
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); | |||
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); | |||
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup RTC_Exported_Functions_Group3 | |||
* @{ | |||
*/ | |||
/* RTC Alarm functions ********************************************************/ | |||
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); | |||
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); | |||
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); | |||
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); | |||
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); | |||
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); | |||
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup RTC_Exported_Functions_Group4 | |||
* @{ | |||
*/ | |||
/* Peripheral Control functions ***********************************************/ | |||
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup RTC_Exported_Functions_Group5 | |||
* @{ | |||
*/ | |||
/* Peripheral State functions *************************************************/ | |||
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup RTC_Private_Constants RTC Private Constants | |||
* @{ | |||
*/ | |||
/* Masks Definition */ | |||
#define RTC_TR_RESERVED_MASK 0x007F7F7FU | |||
#define RTC_DR_RESERVED_MASK 0x00FFFF3FU | |||
#define RTC_INIT_MASK 0xFFFFFFFFU | |||
#define RTC_RSF_MASK 0xFFFFFF5FU | |||
#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ | |||
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ | |||
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ | |||
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ | |||
RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) | |||
#define RTC_TIMEOUT_VALUE 1000 | |||
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup RTC_Private_Macros RTC Private Macros | |||
* @{ | |||
*/ | |||
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters | |||
* @{ | |||
*/ | |||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ | |||
((FORMAT) == RTC_HOURFORMAT_24)) | |||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ | |||
((OUTPUT) == RTC_OUTPUT_ALARMA) || \ | |||
((OUTPUT) == RTC_OUTPUT_ALARMB) || \ | |||
((OUTPUT) == RTC_OUTPUT_WAKEUP)) | |||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ | |||
((POL) == RTC_OUTPUT_POLARITY_LOW)) | |||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ | |||
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) | |||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) | |||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) | |||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) | |||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) | |||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) | |||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) | |||
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) | |||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ | |||
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ | |||
((SAVE) == RTC_DAYLIGHTSAVING_NONE)) | |||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ | |||
((OPERATION) == RTC_STOREOPERATION_SET)) | |||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) | |||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) | |||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) | |||
#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) | |||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) | |||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) | |||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ | |||
((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) | |||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ | |||
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) | |||
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET) | |||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) | |||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU) | |||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ | |||
((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup RTC_Private_Functions RTC Private Functions | |||
* @{ | |||
*/ | |||
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); | |||
uint8_t RTC_ByteToBcd2(uint8_t Value); | |||
uint8_t RTC_Bcd2ToByte(uint8_t Value); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_RTC_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,356 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_tim_ex.h | |||
* @author MCD Application Team | |||
* @brief Header file of TIM HAL Extended module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef STM32F4xx_HAL_TIM_EX_H | |||
#define STM32F4xx_HAL_TIM_EX_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup TIMEx | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief TIM Hall sensor Configuration Structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. | |||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ | |||
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. | |||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ | |||
uint32_t IC1Filter; /*!< Specifies the input capture filter. | |||
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ | |||
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. | |||
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ | |||
} TIM_HallSensor_InitTypeDef; | |||
/** | |||
* @} | |||
*/ | |||
/* End of exported types -----------------------------------------------------*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup TIMEx_Remap TIM Extended Remapping | |||
* @{ | |||
*/ | |||
#if defined (TIM2) | |||
#if defined(TIM8) | |||
#define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ | |||
#else | |||
#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ | |||
#endif /* TIM8 */ | |||
#define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ | |||
#define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ | |||
#endif /* TIM2 */ | |||
#define TIM_TIM5_GPIO 0x00000000U /*!< TIM5 TI4 is connected to GPIO */ | |||
#define TIM_TIM5_LSI TIM_OR_TI4_RMP_0 /*!< TIM5 TI4 is connected to LSI */ | |||
#define TIM_TIM5_LSE TIM_OR_TI4_RMP_1 /*!< TIM5 TI4 is connected to LSE */ | |||
#define TIM_TIM5_RTC (TIM_OR_TI4_RMP_1 | TIM_OR_TI4_RMP_0) /*!< TIM5 TI4 is connected to the RTC wakeup interrupt */ | |||
#define TIM_TIM11_GPIO 0x00000000U /*!< TIM11 TI1 is connected to GPIO */ | |||
#define TIM_TIM11_HSE TIM_OR_TI1_RMP_1 /*!< TIM11 TI1 is connected to HSE_RTC clock */ | |||
#if defined(SPDIFRX) | |||
#define TIM_TIM11_SPDIFRX TIM_OR_TI1_RMP_0 /*!< TIM11 TI1 is connected to SPDIFRX_FRAME_SYNC */ | |||
#endif /* SPDIFRX*/ | |||
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) | |||
#define LPTIM_REMAP_MASK 0x10000000U | |||
#define TIM_TIM9_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM9 ITR1 is connected to TIM3 TRGO */ | |||
#define TIM_TIM9_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM9_ITR1_RMP) /*!< TIM9 ITR1 is connected to LPTIM1 output */ | |||
#define TIM_TIM5_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM5 ITR1 is connected to TIM3 TRGO */ | |||
#define TIM_TIM5_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM5_ITR1_RMP) /*!< TIM5 ITR1 is connected to LPTIM1 output */ | |||
#define TIM_TIM1_TIM3_TRGO LPTIM_REMAP_MASK /*!< TIM1 ITR2 is connected to TIM3 TRGO */ | |||
#define TIM_TIM1_LPTIM (LPTIM_REMAP_MASK | LPTIM_OR_TIM1_ITR2_RMP) /*!< TIM1 ITR2 is connected to LPTIM1 output */ | |||
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* End of exported constants -------------------------------------------------*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* End of exported macro -----------------------------------------------------*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros | |||
* @{ | |||
*/ | |||
#if defined(SPDIFRX) | |||
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ | |||
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ | |||
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSI) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSE) || \ | |||
((TIM_REMAP) == TIM_TIM5_RTC))) || \ | |||
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM11_SPDIFRX) || \ | |||
((TIM_REMAP) == TIM_TIM11_HSE)))) | |||
#elif defined(TIM2) | |||
#if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) | |||
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ | |||
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ | |||
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSI) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSE) || \ | |||
((TIM_REMAP) == TIM_TIM5_RTC))) || \ | |||
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM11_HSE))) || \ | |||
(((INSTANCE) == TIM1) && (((TIM_REMAP) == TIM_TIM1_TIM3_TRGO) || \ | |||
((TIM_REMAP) == TIM_TIM1_LPTIM))) || \ | |||
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_TIM3_TRGO) || \ | |||
((TIM_REMAP) == TIM_TIM5_LPTIM))) || \ | |||
(((INSTANCE) == TIM9) && (((TIM_REMAP) == TIM_TIM9_TIM3_TRGO) || \ | |||
((TIM_REMAP) == TIM_TIM9_LPTIM)))) | |||
#elif defined(TIM8) | |||
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ | |||
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_TIM8_TRGO) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ | |||
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSI) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSE) || \ | |||
((TIM_REMAP) == TIM_TIM5_RTC))) || \ | |||
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM11_HSE)))) | |||
#else | |||
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ | |||
((((INSTANCE) == TIM2) && (((TIM_REMAP) == TIM_TIM2_ETH_PTP) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBFS_SOF) || \ | |||
((TIM_REMAP) == TIM_TIM2_USBHS_SOF))) || \ | |||
(((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSI) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSE) || \ | |||
((TIM_REMAP) == TIM_TIM5_RTC))) || \ | |||
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM11_HSE)))) | |||
#endif /* LPTIM_OR_TIM1_ITR2_RMP && LPTIM_OR_TIM5_ITR1_RMP && LPTIM_OR_TIM5_ITR1_RMP */ | |||
#else | |||
#define IS_TIM_REMAP(INSTANCE, TIM_REMAP) \ | |||
((((INSTANCE) == TIM5) && (((TIM_REMAP) == TIM_TIM5_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSI) || \ | |||
((TIM_REMAP) == TIM_TIM5_LSE) || \ | |||
((TIM_REMAP) == TIM_TIM5_RTC))) || \ | |||
(((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || \ | |||
((TIM_REMAP) == TIM_TIM11_HSE)))) | |||
#endif /* SPDIFRX */ | |||
/** | |||
* @} | |||
*/ | |||
/* End of private macro ------------------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions | |||
* @brief Timer Hall Sensor functions | |||
* @{ | |||
*/ | |||
/* Timer Hall Sensor functions **********************************************/ | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); | |||
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); | |||
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); | |||
/* Blocking mode: Polling */ | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); | |||
/* Non-Blocking mode: Interrupt */ | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); | |||
/* Non-Blocking mode: DMA */ | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); | |||
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions | |||
* @brief Timer Complementary Output Compare functions | |||
* @{ | |||
*/ | |||
/* Timer Complementary Output Compare functions *****************************/ | |||
/* Blocking mode: Polling */ | |||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
/* Non-Blocking mode: Interrupt */ | |||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
/* Non-Blocking mode: DMA */ | |||
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); | |||
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions | |||
* @brief Timer Complementary PWM functions | |||
* @{ | |||
*/ | |||
/* Timer Complementary PWM functions ****************************************/ | |||
/* Blocking mode: Polling */ | |||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
/* Non-Blocking mode: Interrupt */ | |||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
/* Non-Blocking mode: DMA */ | |||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); | |||
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions | |||
* @brief Timer Complementary One Pulse functions | |||
* @{ | |||
*/ | |||
/* Timer Complementary One Pulse functions **********************************/ | |||
/* Blocking mode: Polling */ | |||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |||
/* Non-Blocking mode: Interrupt */ | |||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |||
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions | |||
* @brief Peripheral Control functions | |||
* @{ | |||
*/ | |||
/* Extended Control functions ************************************************/ | |||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, | |||
uint32_t CommutationSource); | |||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, | |||
uint32_t CommutationSource); | |||
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, | |||
uint32_t CommutationSource); | |||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, | |||
TIM_MasterConfigTypeDef *sMasterConfig); | |||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, | |||
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); | |||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions | |||
* @brief Extended Callbacks functions | |||
* @{ | |||
*/ | |||
/* Extended Callback **********************************************************/ | |||
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); | |||
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); | |||
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions | |||
* @brief Extended Peripheral State functions | |||
* @{ | |||
*/ | |||
/* Extended Peripheral State functions ***************************************/ | |||
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* End of exported functions -------------------------------------------------*/ | |||
/* Private functions----------------------------------------------------------*/ | |||
/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions | |||
* @{ | |||
*/ | |||
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); | |||
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); | |||
/** | |||
* @} | |||
*/ | |||
/* End of private functions --------------------------------------------------*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* STM32F4xx_HAL_TIM_EX_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,846 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_uart.h | |||
* @author MCD Application Team | |||
* @brief Header file of UART HAL module. | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2016 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Define to prevent recursive inclusion -------------------------------------*/ | |||
#ifndef __STM32F4xx_HAL_UART_H | |||
#define __STM32F4xx_HAL_UART_H | |||
#ifdef __cplusplus | |||
extern "C" { | |||
#endif | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal_def.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup UART | |||
* @{ | |||
*/ | |||
/* Exported types ------------------------------------------------------------*/ | |||
/** @defgroup UART_Exported_Types UART Exported Types | |||
* @{ | |||
*/ | |||
/** | |||
* @brief UART Init Structure definition | |||
*/ | |||
typedef struct | |||
{ | |||
uint32_t BaudRate; /*!< This member configures the UART communication baud rate. | |||
The baud rate is computed using the following formula: | |||
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate))) | |||
- FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 | |||
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ | |||
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. | |||
This parameter can be a value of @ref UART_Word_Length */ | |||
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. | |||
This parameter can be a value of @ref UART_Stop_Bits */ | |||
uint32_t Parity; /*!< Specifies the parity mode. | |||
This parameter can be a value of @ref UART_Parity | |||
@note When parity is enabled, the computed parity is inserted | |||
at the MSB position of the transmitted data (9th bit when | |||
the word length is set to 9 data bits; 8th bit when the | |||
word length is set to 8 data bits). */ | |||
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. | |||
This parameter can be a value of @ref UART_Mode */ | |||
uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. | |||
This parameter can be a value of @ref UART_Hardware_Flow_Control */ | |||
uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8). | |||
This parameter can be a value of @ref UART_Over_Sampling */ | |||
} UART_InitTypeDef; | |||
/** | |||
* @brief HAL UART State structures definition | |||
* @note HAL UART State value is a combination of 2 different substates: gState and RxState. | |||
* - gState contains UART state information related to global Handle management | |||
* and also information related to Tx operations. | |||
* gState value coding follow below described bitmap : | |||
* b7-b6 Error information | |||
* 00 : No Error | |||
* 01 : (Not Used) | |||
* 10 : Timeout | |||
* 11 : Error | |||
* b5 Peripheral initialization status | |||
* 0 : Reset (Peripheral not initialized) | |||
* 1 : Init done (Peripheral not initialized. HAL UART Init function already called) | |||
* b4-b3 (not used) | |||
* xx : Should be set to 00 | |||
* b2 Intrinsic process state | |||
* 0 : Ready | |||
* 1 : Busy (Peripheral busy with some configuration or internal operations) | |||
* b1 (not used) | |||
* x : Should be set to 0 | |||
* b0 Tx state | |||
* 0 : Ready (no Tx operation ongoing) | |||
* 1 : Busy (Tx operation ongoing) | |||
* - RxState contains information related to Rx operations. | |||
* RxState value coding follow below described bitmap : | |||
* b7-b6 (not used) | |||
* xx : Should be set to 00 | |||
* b5 Peripheral initialization status | |||
* 0 : Reset (Peripheral not initialized) | |||
* 1 : Init done (Peripheral not initialized) | |||
* b4-b2 (not used) | |||
* xxx : Should be set to 000 | |||
* b1 Rx state | |||
* 0 : Ready (no Rx operation ongoing) | |||
* 1 : Busy (Rx operation ongoing) | |||
* b0 (not used) | |||
* x : Should be set to 0. | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized | |||
Value is allowed for gState and RxState */ | |||
HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use | |||
Value is allowed for gState and RxState */ | |||
HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing | |||
Value is allowed for gState only */ | |||
HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing | |||
Value is allowed for gState only */ | |||
HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing | |||
Value is allowed for RxState only */ | |||
HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing | |||
Not to be used for neither gState nor RxState. | |||
Value is result of combination (Or) between gState and RxState values */ | |||
HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state | |||
Value is allowed for gState only */ | |||
HAL_UART_STATE_ERROR = 0xE0U /*!< Error | |||
Value is allowed for gState only */ | |||
} HAL_UART_StateTypeDef; | |||
/** | |||
* @brief UART handle Structure definition | |||
*/ | |||
typedef struct __UART_HandleTypeDef | |||
{ | |||
USART_TypeDef *Instance; /*!< UART registers base address */ | |||
UART_InitTypeDef Init; /*!< UART communication parameters */ | |||
uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ | |||
uint16_t TxXferSize; /*!< UART Tx Transfer size */ | |||
__IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ | |||
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ | |||
uint16_t RxXferSize; /*!< UART Rx Transfer size */ | |||
__IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ | |||
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ | |||
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ | |||
HAL_LockTypeDef Lock; /*!< Locking object */ | |||
__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management | |||
and also related to Tx operations. | |||
This parameter can be a value of @ref HAL_UART_StateTypeDef */ | |||
__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. | |||
This parameter can be a value of @ref HAL_UART_StateTypeDef */ | |||
__IO uint32_t ErrorCode; /*!< UART Error code */ | |||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) | |||
void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ | |||
void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ | |||
void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ | |||
void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ | |||
void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ | |||
void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ | |||
void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ | |||
void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ | |||
void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ | |||
void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ | |||
void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ | |||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ | |||
} UART_HandleTypeDef; | |||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) | |||
/** | |||
* @brief HAL UART Callback ID enumeration definition | |||
*/ | |||
typedef enum | |||
{ | |||
HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ | |||
HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ | |||
HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ | |||
HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ | |||
HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ | |||
HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ | |||
HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ | |||
HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ | |||
HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ | |||
HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ | |||
HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ | |||
} HAL_UART_CallbackIDTypeDef; | |||
/** | |||
* @brief HAL UART Callback pointer definition | |||
*/ | |||
typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ | |||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported constants --------------------------------------------------------*/ | |||
/** @defgroup UART_Exported_Constants UART Exported Constants | |||
* @{ | |||
*/ | |||
/** @defgroup UART_Error_Code UART Error Code | |||
* @{ | |||
*/ | |||
#define HAL_UART_ERROR_NONE 0x00000000U /*!< No error */ | |||
#define HAL_UART_ERROR_PE 0x00000001U /*!< Parity error */ | |||
#define HAL_UART_ERROR_NE 0x00000002U /*!< Noise error */ | |||
#define HAL_UART_ERROR_FE 0x00000004U /*!< Frame error */ | |||
#define HAL_UART_ERROR_ORE 0x00000008U /*!< Overrun error */ | |||
#define HAL_UART_ERROR_DMA 0x00000010U /*!< DMA transfer error */ | |||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) | |||
#define HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid Callback error */ | |||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Word_Length UART Word Length | |||
* @{ | |||
*/ | |||
#define UART_WORDLENGTH_8B 0x00000000U | |||
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Stop_Bits UART Number of Stop Bits | |||
* @{ | |||
*/ | |||
#define UART_STOPBITS_1 0x00000000U | |||
#define UART_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Parity UART Parity | |||
* @{ | |||
*/ | |||
#define UART_PARITY_NONE 0x00000000U | |||
#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) | |||
#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control | |||
* @{ | |||
*/ | |||
#define UART_HWCONTROL_NONE 0x00000000U | |||
#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) | |||
#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) | |||
#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Mode UART Transfer Mode | |||
* @{ | |||
*/ | |||
#define UART_MODE_RX ((uint32_t)USART_CR1_RE) | |||
#define UART_MODE_TX ((uint32_t)USART_CR1_TE) | |||
#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE | USART_CR1_RE)) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_State UART State | |||
* @{ | |||
*/ | |||
#define UART_STATE_DISABLE 0x00000000U | |||
#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Over_Sampling UART Over Sampling | |||
* @{ | |||
*/ | |||
#define UART_OVERSAMPLING_16 0x00000000U | |||
#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_LIN_Break_Detection_Length UART LIN Break Detection Length | |||
* @{ | |||
*/ | |||
#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U | |||
#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_WakeUp_functions UART Wakeup Functions | |||
* @{ | |||
*/ | |||
#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U | |||
#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Flags UART FLags | |||
* Elements values convention: 0xXXXX | |||
* - 0xXXXX : Flag mask in the SR register | |||
* @{ | |||
*/ | |||
#define UART_FLAG_CTS ((uint32_t)USART_SR_CTS) | |||
#define UART_FLAG_LBD ((uint32_t)USART_SR_LBD) | |||
#define UART_FLAG_TXE ((uint32_t)USART_SR_TXE) | |||
#define UART_FLAG_TC ((uint32_t)USART_SR_TC) | |||
#define UART_FLAG_RXNE ((uint32_t)USART_SR_RXNE) | |||
#define UART_FLAG_IDLE ((uint32_t)USART_SR_IDLE) | |||
#define UART_FLAG_ORE ((uint32_t)USART_SR_ORE) | |||
#define UART_FLAG_NE ((uint32_t)USART_SR_NE) | |||
#define UART_FLAG_FE ((uint32_t)USART_SR_FE) | |||
#define UART_FLAG_PE ((uint32_t)USART_SR_PE) | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup UART_Interrupt_definition UART Interrupt Definitions | |||
* Elements values convention: 0xY000XXXX | |||
* - XXXX : Interrupt mask (16 bits) in the Y register | |||
* - Y : Interrupt source register (2bits) | |||
* - 0001: CR1 register | |||
* - 0010: CR2 register | |||
* - 0011: CR3 register | |||
* @{ | |||
*/ | |||
#define UART_IT_PE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE)) | |||
#define UART_IT_TXE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE)) | |||
#define UART_IT_TC ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE)) | |||
#define UART_IT_RXNE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE)) | |||
#define UART_IT_IDLE ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE)) | |||
#define UART_IT_LBD ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE)) | |||
#define UART_IT_CTS ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE)) | |||
#define UART_IT_ERR ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE)) | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Exported macro ------------------------------------------------------------*/ | |||
/** @defgroup UART_Exported_Macros UART Exported Macros | |||
* @{ | |||
*/ | |||
/** @brief Reset UART handle gstate & RxState | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @retval None | |||
*/ | |||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) | |||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ | |||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \ | |||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ | |||
(__HANDLE__)->MspInitCallback = NULL; \ | |||
(__HANDLE__)->MspDeInitCallback = NULL; \ | |||
} while(0U) | |||
#else | |||
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ | |||
(__HANDLE__)->gState = HAL_UART_STATE_RESET; \ | |||
(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ | |||
} while(0U) | |||
#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ | |||
/** @brief Flushes the UART DR register | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
*/ | |||
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR) | |||
/** @brief Checks whether the specified UART flag is set or not. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @param __FLAG__ specifies the flag to check. | |||
* This parameter can be one of the following values: | |||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) | |||
* @arg UART_FLAG_LBD: LIN Break detection flag | |||
* @arg UART_FLAG_TXE: Transmit data register empty flag | |||
* @arg UART_FLAG_TC: Transmission Complete flag | |||
* @arg UART_FLAG_RXNE: Receive data register not empty flag | |||
* @arg UART_FLAG_IDLE: Idle Line detection flag | |||
* @arg UART_FLAG_ORE: Overrun Error flag | |||
* @arg UART_FLAG_NE: Noise Error flag | |||
* @arg UART_FLAG_FE: Framing Error flag | |||
* @arg UART_FLAG_PE: Parity Error flag | |||
* @retval The new state of __FLAG__ (TRUE or FALSE). | |||
*/ | |||
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) | |||
/** @brief Clears the specified UART pending flag. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @param __FLAG__ specifies the flag to check. | |||
* This parameter can be any combination of the following values: | |||
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). | |||
* @arg UART_FLAG_LBD: LIN Break detection flag. | |||
* @arg UART_FLAG_TC: Transmission Complete flag. | |||
* @arg UART_FLAG_RXNE: Receive data register not empty flag. | |||
* | |||
* @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun | |||
* error) and IDLE (Idle line detected) flags are cleared by software | |||
* sequence: a read operation to USART_SR register followed by a read | |||
* operation to USART_DR register. | |||
* @note RXNE flag can be also cleared by a read to the USART_DR register. | |||
* @note TC flag can be also cleared by software sequence: a read operation to | |||
* USART_SR register followed by a write operation to USART_DR register. | |||
* @note TXE flag is cleared only by a write to the USART_DR register. | |||
* | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) | |||
/** @brief Clears the UART PE pending flag. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) \ | |||
do{ \ | |||
__IO uint32_t tmpreg = 0x00U; \ | |||
tmpreg = (__HANDLE__)->Instance->SR; \ | |||
tmpreg = (__HANDLE__)->Instance->DR; \ | |||
UNUSED(tmpreg); \ | |||
} while(0U) | |||
/** @brief Clears the UART FE pending flag. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) | |||
/** @brief Clears the UART NE pending flag. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) | |||
/** @brief Clears the UART ORE pending flag. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) | |||
/** @brief Clears the UART IDLE pending flag. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__) | |||
/** @brief Enable the specified UART interrupt. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @param __INTERRUPT__ specifies the UART interrupt source to enable. | |||
* This parameter can be one of the following values: | |||
* @arg UART_IT_CTS: CTS change interrupt | |||
* @arg UART_IT_LBD: LIN Break detection interrupt | |||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt | |||
* @arg UART_IT_TC: Transmission complete interrupt | |||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt | |||
* @arg UART_IT_IDLE: Idle line detection interrupt | |||
* @arg UART_IT_PE: Parity Error interrupt | |||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \ | |||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \ | |||
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK))) | |||
/** @brief Disable the specified UART interrupt. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @param __INTERRUPT__ specifies the UART interrupt source to disable. | |||
* This parameter can be one of the following values: | |||
* @arg UART_IT_CTS: CTS change interrupt | |||
* @arg UART_IT_LBD: LIN Break detection interrupt | |||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt | |||
* @arg UART_IT_TC: Transmission complete interrupt | |||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt | |||
* @arg UART_IT_IDLE: Idle line detection interrupt | |||
* @arg UART_IT_PE: Parity Error interrupt | |||
* @arg UART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ | |||
(((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \ | |||
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK))) | |||
/** @brief Checks whether the specified UART interrupt source is enabled or not. | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* UART Handle selects the USARTx or UARTy peripheral | |||
* (USART,UART availability and x,y values depending on device). | |||
* @param __IT__ specifies the UART interrupt source to check. | |||
* This parameter can be one of the following values: | |||
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) | |||
* @arg UART_IT_LBD: LIN Break detection interrupt | |||
* @arg UART_IT_TXE: Transmit Data Register empty interrupt | |||
* @arg UART_IT_TC: Transmission complete interrupt | |||
* @arg UART_IT_RXNE: Receive Data register not empty interrupt | |||
* @arg UART_IT_IDLE: Idle line detection interrupt | |||
* @arg UART_IT_ERR: Error interrupt | |||
* @retval The new state of __IT__ (TRUE or FALSE). | |||
*/ | |||
#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ | |||
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) | |||
/** @brief Enable CTS flow control | |||
* @note This macro allows to enable CTS hardware flow control for a given UART instance, | |||
* without need to call HAL_UART_Init() function. | |||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. | |||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need | |||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : | |||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) | |||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) | |||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). | |||
* It is used to select the USART peripheral (USART availability and x value depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ | |||
do{ \ | |||
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ | |||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ | |||
} while(0U) | |||
/** @brief Disable CTS flow control | |||
* @note This macro allows to disable CTS hardware flow control for a given UART instance, | |||
* without need to call HAL_UART_Init() function. | |||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. | |||
* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need | |||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : | |||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) | |||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) | |||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). | |||
* It is used to select the USART peripheral (USART availability and x value depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ | |||
do{ \ | |||
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ | |||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ | |||
} while(0U) | |||
/** @brief Enable RTS flow control | |||
* This macro allows to enable RTS hardware flow control for a given UART instance, | |||
* without need to call HAL_UART_Init() function. | |||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. | |||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need | |||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : | |||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) | |||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) | |||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). | |||
* It is used to select the USART peripheral (USART availability and x value depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ | |||
do{ \ | |||
SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ | |||
(__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ | |||
} while(0U) | |||
/** @brief Disable RTS flow control | |||
* This macro allows to disable RTS hardware flow control for a given UART instance, | |||
* without need to call HAL_UART_Init() function. | |||
* As involving direct access to UART registers, usage of this macro should be fully endorsed by user. | |||
* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need | |||
* for USART instance Deinit/Init, following conditions for macro call should be fulfilled : | |||
* - UART instance should have already been initialised (through call of HAL_UART_Init() ) | |||
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__)) | |||
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)). | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* The Handle Instance can be any USARTx (supporting the HW Flow control feature). | |||
* It is used to select the USART peripheral (USART availability and x value depending on device). | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ | |||
do{ \ | |||
CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ | |||
(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ | |||
} while(0U) | |||
/** @brief Macro to enable the UART's one bit sample method | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) | |||
/** @brief Macro to disable the UART's one bit sample method | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) | |||
/** @brief Enable UART | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) | |||
/** @brief Disable UART | |||
* @param __HANDLE__ specifies the UART Handle. | |||
* @retval None | |||
*/ | |||
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup UART_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions | |||
* @{ | |||
*/ | |||
/* Initialization/de-initialization functions **********************************/ | |||
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); | |||
HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); | |||
HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); | |||
void HAL_UART_MspInit(UART_HandleTypeDef *huart); | |||
void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); | |||
/* Callbacks Register/UnRegister functions ***********************************/ | |||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) | |||
HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); | |||
HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); | |||
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup UART_Exported_Functions_Group2 IO operation functions | |||
* @{ | |||
*/ | |||
/* IO operation functions *******************************************************/ | |||
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); | |||
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); | |||
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); | |||
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); | |||
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); | |||
HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); | |||
HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); | |||
/* Transfer Abort functions */ | |||
HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); | |||
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); | |||
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); | |||
void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup UART_Exported_Functions_Group3 | |||
* @{ | |||
*/ | |||
/* Peripheral Control functions ************************************************/ | |||
HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); | |||
HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup UART_Exported_Functions_Group4 | |||
* @{ | |||
*/ | |||
/* Peripheral State functions **************************************************/ | |||
HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); | |||
uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/** @defgroup UART_Private_Constants UART Private Constants | |||
* @{ | |||
*/ | |||
/** @brief UART interruptions flag mask | |||
* | |||
*/ | |||
#define UART_IT_MASK 0x0000FFFFU | |||
#define UART_CR1_REG_INDEX 1U | |||
#define UART_CR2_REG_INDEX 2U | |||
#define UART_CR3_REG_INDEX 3U | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/** @defgroup UART_Private_Macros UART Private Macros | |||
* @{ | |||
*/ | |||
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \ | |||
((LENGTH) == UART_WORDLENGTH_9B)) | |||
#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B)) | |||
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \ | |||
((STOPBITS) == UART_STOPBITS_2)) | |||
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \ | |||
((PARITY) == UART_PARITY_EVEN) || \ | |||
((PARITY) == UART_PARITY_ODD)) | |||
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\ | |||
(((CONTROL) == UART_HWCONTROL_NONE) || \ | |||
((CONTROL) == UART_HWCONTROL_RTS) || \ | |||
((CONTROL) == UART_HWCONTROL_CTS) || \ | |||
((CONTROL) == UART_HWCONTROL_RTS_CTS)) | |||
#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U)) | |||
#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \ | |||
((STATE) == UART_STATE_ENABLE)) | |||
#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \ | |||
((SAMPLING) == UART_OVERSAMPLING_8)) | |||
#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16)) | |||
#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \ | |||
((LENGTH) == UART_LINBREAKDETECTLENGTH_11B)) | |||
#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \ | |||
((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK)) | |||
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U) | |||
#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU) | |||
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) | |||
#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) | |||
#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) | |||
/* UART BRR = mantissa + overflow + fraction | |||
= (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ | |||
#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ | |||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \ | |||
(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU)) | |||
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) | |||
#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) | |||
#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) | |||
/* UART BRR = mantissa + overflow + fraction | |||
= (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ | |||
#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ | |||
((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \ | |||
(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U)) | |||
/** | |||
* @} | |||
*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup UART_Private_Functions UART Private Functions | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#ifdef __cplusplus | |||
} | |||
#endif | |||
#endif /* __STM32F4xx_HAL_UART_H */ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,615 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal.c | |||
* @author MCD Application Team | |||
* @brief HAL module driver. | |||
* This is the common part of the HAL initialization | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### How to use this driver ##### | |||
============================================================================== | |||
[..] | |||
The common HAL driver contains a set of generic and common APIs that can be | |||
used by the PPP peripheral drivers and the user to start using the HAL. | |||
[..] | |||
The HAL contains two APIs' categories: | |||
(+) Common HAL APIs | |||
(+) Services HAL APIs | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup HAL HAL | |||
* @brief HAL module driver. | |||
* @{ | |||
*/ | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private define ------------------------------------------------------------*/ | |||
/** @addtogroup HAL_Private_Constants | |||
* @{ | |||
*/ | |||
/** | |||
* @brief STM32F4xx HAL Driver version number V1.7.10 | |||
*/ | |||
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ | |||
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ | |||
#define __STM32F4xx_HAL_VERSION_SUB2 (0x0AU) /*!< [15:8] sub2 version */ | |||
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ | |||
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ | |||
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ | |||
|(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\ | |||
|(__STM32F4xx_HAL_VERSION_RC)) | |||
#define IDCODE_DEVID_MASK 0x00000FFFU | |||
/* ------------ RCC registers bit address in the alias region ----------- */ | |||
#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) | |||
/* --- MEMRMP Register ---*/ | |||
/* Alias word address of UFB_MODE bit */ | |||
#define MEMRMP_OFFSET SYSCFG_OFFSET | |||
#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos | |||
#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) | |||
/* --- CMPCR Register ---*/ | |||
/* Alias word address of CMP_PD bit */ | |||
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U) | |||
#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos | |||
#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U)) | |||
/* --- MCHDLYCR Register ---*/ | |||
/* Alias word address of BSCKSEL bit */ | |||
#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U) | |||
#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos | |||
#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U)) | |||
/** | |||
* @} | |||
*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/** @addtogroup HAL_Private_Variables | |||
* @{ | |||
*/ | |||
__IO uint32_t uwTick; | |||
uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ | |||
HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ | |||
/** | |||
* @} | |||
*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup HAL_Exported_Functions HAL Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions | |||
* @brief Initialization and de-initialization functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Initialization and Configuration functions ##### | |||
=============================================================================== | |||
[..] This section provides functions allowing to: | |||
(+) Initializes the Flash interface the NVIC allocation and initial clock | |||
configuration. It initializes the systick also when timeout is needed | |||
and the backup domain when enabled. | |||
(+) De-Initializes common part of the HAL. | |||
(+) Configure the time base source to have 1ms time base with a dedicated | |||
Tick interrupt priority. | |||
(++) SysTick timer is used by default as source of time base, but user | |||
can eventually implement his proper time base source (a general purpose | |||
timer for example or other time source), keeping in mind that Time base | |||
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and | |||
handled in milliseconds basis. | |||
(++) Time base configuration function (HAL_InitTick ()) is called automatically | |||
at the beginning of the program after reset by HAL_Init() or at any time | |||
when clock is configured, by HAL_RCC_ClockConfig(). | |||
(++) Source of time base is configured to generate interrupts at regular | |||
time intervals. Care must be taken if HAL_Delay() is called from a | |||
peripheral ISR process, the Tick interrupt line must have higher priority | |||
(numerically lower) than the peripheral interrupt. Otherwise the caller | |||
ISR process will be blocked. | |||
(++) functions affecting time base configurations are declared as __weak | |||
to make override possible in case of other implementations in user file. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief This function is used to initialize the HAL Library; it must be the first | |||
* instruction to be executed in the main program (before to call any other | |||
* HAL function), it performs the following: | |||
* Configure the Flash prefetch, instruction and Data caches. | |||
* Configures the SysTick to generate an interrupt each 1 millisecond, | |||
* which is clocked by the HSI (at this stage, the clock is not yet | |||
* configured and thus the system is running from the internal HSI at 16 MHz). | |||
* Set NVIC Group Priority to 4. | |||
* Calls the HAL_MspInit() callback function defined in user file | |||
* "stm32f4xx_hal_msp.c" to do the global low level hardware initialization | |||
* | |||
* @note SysTick is used as time base for the HAL_Delay() function, the application | |||
* need to ensure that the SysTick time base is always set to 1 millisecond | |||
* to have correct HAL operation. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_Init(void) | |||
{ | |||
/* Configure Flash prefetch, Instruction cache, Data cache */ | |||
#if (INSTRUCTION_CACHE_ENABLE != 0U) | |||
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); | |||
#endif /* INSTRUCTION_CACHE_ENABLE */ | |||
#if (DATA_CACHE_ENABLE != 0U) | |||
__HAL_FLASH_DATA_CACHE_ENABLE(); | |||
#endif /* DATA_CACHE_ENABLE */ | |||
#if (PREFETCH_ENABLE != 0U) | |||
__HAL_FLASH_PREFETCH_BUFFER_ENABLE(); | |||
#endif /* PREFETCH_ENABLE */ | |||
/* Set Interrupt Group Priority */ | |||
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); | |||
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ | |||
HAL_InitTick(TICK_INT_PRIORITY); | |||
/* Init the low level hardware */ | |||
HAL_MspInit(); | |||
/* Return function status */ | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief This function de-Initializes common part of the HAL and stops the systick. | |||
* This function is optional. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_DeInit(void) | |||
{ | |||
/* Reset of all peripherals */ | |||
__HAL_RCC_APB1_FORCE_RESET(); | |||
__HAL_RCC_APB1_RELEASE_RESET(); | |||
__HAL_RCC_APB2_FORCE_RESET(); | |||
__HAL_RCC_APB2_RELEASE_RESET(); | |||
__HAL_RCC_AHB1_FORCE_RESET(); | |||
__HAL_RCC_AHB1_RELEASE_RESET(); | |||
__HAL_RCC_AHB2_FORCE_RESET(); | |||
__HAL_RCC_AHB2_RELEASE_RESET(); | |||
__HAL_RCC_AHB3_FORCE_RESET(); | |||
__HAL_RCC_AHB3_RELEASE_RESET(); | |||
/* De-Init the low level hardware */ | |||
HAL_MspDeInit(); | |||
/* Return function status */ | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Initialize the MSP. | |||
* @retval None | |||
*/ | |||
__weak void HAL_MspInit(void) | |||
{ | |||
/* NOTE : This function should not be modified, when the callback is needed, | |||
the HAL_MspInit could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @brief DeInitializes the MSP. | |||
* @retval None | |||
*/ | |||
__weak void HAL_MspDeInit(void) | |||
{ | |||
/* NOTE : This function should not be modified, when the callback is needed, | |||
the HAL_MspDeInit could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @brief This function configures the source of the time base. | |||
* The time source is configured to have 1ms time base with a dedicated | |||
* Tick interrupt priority. | |||
* @note This function is called automatically at the beginning of program after | |||
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). | |||
* @note In the default implementation, SysTick timer is the source of time base. | |||
* It is used to generate interrupts at regular time intervals. | |||
* Care must be taken if HAL_Delay() is called from a peripheral ISR process, | |||
* The SysTick interrupt must have higher priority (numerically lower) | |||
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked. | |||
* The function is declared as __weak to be overwritten in case of other | |||
* implementation in user file. | |||
* @param TickPriority Tick interrupt priority. | |||
* @retval HAL status | |||
*/ | |||
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) | |||
{ | |||
/* Configure the SysTick to have interrupt in 1ms time basis*/ | |||
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) | |||
{ | |||
return HAL_ERROR; | |||
} | |||
/* Configure the SysTick IRQ priority */ | |||
if (TickPriority < (1UL << __NVIC_PRIO_BITS)) | |||
{ | |||
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); | |||
uwTickPrio = TickPriority; | |||
} | |||
else | |||
{ | |||
return HAL_ERROR; | |||
} | |||
/* Return function status */ | |||
return HAL_OK; | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions | |||
* @brief HAL Control functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### HAL Control functions ##### | |||
=============================================================================== | |||
[..] This section provides functions allowing to: | |||
(+) Provide a tick value in millisecond | |||
(+) Provide a blocking delay in millisecond | |||
(+) Suspend the time base source interrupt | |||
(+) Resume the time base source interrupt | |||
(+) Get the HAL API driver version | |||
(+) Get the device identifier | |||
(+) Get the device revision identifier | |||
(+) Enable/Disable Debug module during SLEEP mode | |||
(+) Enable/Disable Debug module during STOP mode | |||
(+) Enable/Disable Debug module during STANDBY mode | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief This function is called to increment a global variable "uwTick" | |||
* used as application time base. | |||
* @note In the default implementation, this variable is incremented each 1ms | |||
* in SysTick ISR. | |||
* @note This function is declared as __weak to be overwritten in case of other | |||
* implementations in user file. | |||
* @retval None | |||
*/ | |||
__weak void HAL_IncTick(void) | |||
{ | |||
uwTick += uwTickFreq; | |||
} | |||
/** | |||
* @brief Provides a tick value in millisecond. | |||
* @note This function is declared as __weak to be overwritten in case of other | |||
* implementations in user file. | |||
* @retval tick value | |||
*/ | |||
__weak uint32_t HAL_GetTick(void) | |||
{ | |||
return uwTick; | |||
} | |||
/** | |||
* @brief This function returns a tick priority. | |||
* @retval tick priority | |||
*/ | |||
uint32_t HAL_GetTickPrio(void) | |||
{ | |||
return uwTickPrio; | |||
} | |||
/** | |||
* @brief Set new tick Freq. | |||
* @retval Status | |||
*/ | |||
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) | |||
{ | |||
HAL_StatusTypeDef status = HAL_OK; | |||
HAL_TickFreqTypeDef prevTickFreq; | |||
assert_param(IS_TICKFREQ(Freq)); | |||
if (uwTickFreq != Freq) | |||
{ | |||
/* Back up uwTickFreq frequency */ | |||
prevTickFreq = uwTickFreq; | |||
/* Update uwTickFreq global variable used by HAL_InitTick() */ | |||
uwTickFreq = Freq; | |||
/* Apply the new tick Freq */ | |||
status = HAL_InitTick(uwTickPrio); | |||
if (status != HAL_OK) | |||
{ | |||
/* Restore previous tick frequency */ | |||
uwTickFreq = prevTickFreq; | |||
} | |||
} | |||
return status; | |||
} | |||
/** | |||
* @brief Return tick frequency. | |||
* @retval tick period in Hz | |||
*/ | |||
HAL_TickFreqTypeDef HAL_GetTickFreq(void) | |||
{ | |||
return uwTickFreq; | |||
} | |||
/** | |||
* @brief This function provides minimum delay (in milliseconds) based | |||
* on variable incremented. | |||
* @note In the default implementation , SysTick timer is the source of time base. | |||
* It is used to generate interrupts at regular time intervals where uwTick | |||
* is incremented. | |||
* @note This function is declared as __weak to be overwritten in case of other | |||
* implementations in user file. | |||
* @param Delay specifies the delay time length, in milliseconds. | |||
* @retval None | |||
*/ | |||
__weak void HAL_Delay(uint32_t Delay) | |||
{ | |||
uint32_t tickstart = HAL_GetTick(); | |||
uint32_t wait = Delay; | |||
/* Add a freq to guarantee minimum wait */ | |||
if (wait < HAL_MAX_DELAY) | |||
{ | |||
wait += (uint32_t)(uwTickFreq); | |||
} | |||
while((HAL_GetTick() - tickstart) < wait) | |||
{ | |||
} | |||
} | |||
/** | |||
* @brief Suspend Tick increment. | |||
* @note In the default implementation , SysTick timer is the source of time base. It is | |||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick() | |||
* is called, the SysTick interrupt will be disabled and so Tick increment | |||
* is suspended. | |||
* @note This function is declared as __weak to be overwritten in case of other | |||
* implementations in user file. | |||
* @retval None | |||
*/ | |||
__weak void HAL_SuspendTick(void) | |||
{ | |||
/* Disable SysTick Interrupt */ | |||
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; | |||
} | |||
/** | |||
* @brief Resume Tick increment. | |||
* @note In the default implementation , SysTick timer is the source of time base. It is | |||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick() | |||
* is called, the SysTick interrupt will be enabled and so Tick increment | |||
* is resumed. | |||
* @note This function is declared as __weak to be overwritten in case of other | |||
* implementations in user file. | |||
* @retval None | |||
*/ | |||
__weak void HAL_ResumeTick(void) | |||
{ | |||
/* Enable SysTick Interrupt */ | |||
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; | |||
} | |||
/** | |||
* @brief Returns the HAL revision | |||
* @retval version : 0xXYZR (8bits for each decimal, R for RC) | |||
*/ | |||
uint32_t HAL_GetHalVersion(void) | |||
{ | |||
return __STM32F4xx_HAL_VERSION; | |||
} | |||
/** | |||
* @brief Returns the device revision identifier. | |||
* @retval Device revision identifier | |||
*/ | |||
uint32_t HAL_GetREVID(void) | |||
{ | |||
return((DBGMCU->IDCODE) >> 16U); | |||
} | |||
/** | |||
* @brief Returns the device identifier. | |||
* @retval Device identifier | |||
*/ | |||
uint32_t HAL_GetDEVID(void) | |||
{ | |||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); | |||
} | |||
/** | |||
* @brief Enable the Debug Module during SLEEP mode | |||
* @retval None | |||
*/ | |||
void HAL_DBGMCU_EnableDBGSleepMode(void) | |||
{ | |||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); | |||
} | |||
/** | |||
* @brief Disable the Debug Module during SLEEP mode | |||
* @retval None | |||
*/ | |||
void HAL_DBGMCU_DisableDBGSleepMode(void) | |||
{ | |||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); | |||
} | |||
/** | |||
* @brief Enable the Debug Module during STOP mode | |||
* @retval None | |||
*/ | |||
void HAL_DBGMCU_EnableDBGStopMode(void) | |||
{ | |||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); | |||
} | |||
/** | |||
* @brief Disable the Debug Module during STOP mode | |||
* @retval None | |||
*/ | |||
void HAL_DBGMCU_DisableDBGStopMode(void) | |||
{ | |||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); | |||
} | |||
/** | |||
* @brief Enable the Debug Module during STANDBY mode | |||
* @retval None | |||
*/ | |||
void HAL_DBGMCU_EnableDBGStandbyMode(void) | |||
{ | |||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); | |||
} | |||
/** | |||
* @brief Disable the Debug Module during STANDBY mode | |||
* @retval None | |||
*/ | |||
void HAL_DBGMCU_DisableDBGStandbyMode(void) | |||
{ | |||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); | |||
} | |||
/** | |||
* @brief Enables the I/O Compensation Cell. | |||
* @note The I/O compensation cell can be used only when the device supply | |||
* voltage ranges from 2.4 to 3.6 V. | |||
* @retval None | |||
*/ | |||
void HAL_EnableCompensationCell(void) | |||
{ | |||
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Power-down the I/O Compensation Cell. | |||
* @note The I/O compensation cell can be used only when the device supply | |||
* voltage ranges from 2.4 to 3.6 V. | |||
* @retval None | |||
*/ | |||
void HAL_DisableCompensationCell(void) | |||
{ | |||
*(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE; | |||
} | |||
/** | |||
* @brief Returns first word of the unique device identifier (UID based on 96 bits) | |||
* @retval Device identifier | |||
*/ | |||
uint32_t HAL_GetUIDw0(void) | |||
{ | |||
return (READ_REG(*((uint32_t *)UID_BASE))); | |||
} | |||
/** | |||
* @brief Returns second word of the unique device identifier (UID based on 96 bits) | |||
* @retval Device identifier | |||
*/ | |||
uint32_t HAL_GetUIDw1(void) | |||
{ | |||
return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); | |||
} | |||
/** | |||
* @brief Returns third word of the unique device identifier (UID based on 96 bits) | |||
* @retval Device identifier | |||
*/ | |||
uint32_t HAL_GetUIDw2(void) | |||
{ | |||
return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); | |||
} | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ | |||
defined(STM32F469xx) || defined(STM32F479xx) | |||
/** | |||
* @brief Enables the Internal FLASH Bank Swapping. | |||
* | |||
* @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. | |||
* | |||
* @note Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) | |||
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) | |||
* | |||
* @retval None | |||
*/ | |||
void HAL_EnableMemorySwappingBank(void) | |||
{ | |||
*(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Disables the Internal FLASH Bank Swapping. | |||
* | |||
* @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. | |||
* | |||
* @note The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) | |||
* and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) | |||
* | |||
* @retval None | |||
*/ | |||
void HAL_DisableMemorySwappingBank(void) | |||
{ | |||
*(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE; | |||
} | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,505 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_cortex.c | |||
* @author MCD Application Team | |||
* @brief CORTEX HAL module driver. | |||
* This file provides firmware functions to manage the following | |||
* functionalities of the CORTEX: | |||
* + Initialization and de-initialization functions | |||
* + Peripheral Control functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### How to use this driver ##### | |||
============================================================================== | |||
[..] | |||
*** How to configure Interrupts using CORTEX HAL driver *** | |||
=========================================================== | |||
[..] | |||
This section provides functions allowing to configure the NVIC interrupts (IRQ). | |||
The Cortex-M4 exceptions are managed by CMSIS functions. | |||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() | |||
function according to the following table. | |||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). | |||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). | |||
(#) please refer to programming manual for details in how to configure priority. | |||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. | |||
The pending IRQ priority will be managed only by the sub priority. | |||
-@- IRQ priority order (sorted by highest to lowest priority): | |||
(+@) Lowest preemption priority | |||
(+@) Lowest sub priority | |||
(+@) Lowest hardware priority (IRQ number) | |||
[..] | |||
*** How to configure Systick using CORTEX HAL driver *** | |||
======================================================== | |||
[..] | |||
Setup SysTick Timer for time base. | |||
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which | |||
is a CMSIS function that: | |||
(++) Configures the SysTick Reload register with value passed as function parameter. | |||
(++) Configures the SysTick IRQ priority to the lowest value 0x0F. | |||
(++) Resets the SysTick Counter register. | |||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). | |||
(++) Enables the SysTick Interrupt. | |||
(++) Starts the SysTick Counter. | |||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro | |||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the | |||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined | |||
inside the stm32f4xx_hal_cortex.h file. | |||
(+) You can change the SysTick IRQ priority by calling the | |||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function | |||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. | |||
(+) To adjust the SysTick time base, use the following formula: | |||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) | |||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function | |||
(++) Reload Value should not exceed 0xFFFFFF | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup CORTEX CORTEX | |||
* @brief CORTEX HAL module driver | |||
* @{ | |||
*/ | |||
#ifdef HAL_CORTEX_MODULE_ENABLED | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private constants ---------------------------------------------------------*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions | |||
* @brief Initialization and Configuration functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### Initialization and de-initialization functions ##### | |||
============================================================================== | |||
[..] | |||
This section provides the CORTEX HAL driver functions allowing to configure Interrupts | |||
Systick functionalities | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Sets the priority grouping field (preemption priority and subpriority) | |||
* using the required unlock sequence. | |||
* @param PriorityGroup The priority grouping bits length. | |||
* This parameter can be one of the following values: | |||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority | |||
* 4 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority | |||
* 3 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority | |||
* 2 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority | |||
* 1 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority | |||
* 0 bits for subpriority | |||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. | |||
* The pending IRQ priority will be managed only by the subpriority. | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); | |||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ | |||
NVIC_SetPriorityGrouping(PriorityGroup); | |||
} | |||
/** | |||
* @brief Sets the priority of an interrupt. | |||
* @param IRQn External interrupt number. | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @param PreemptPriority The preemption priority for the IRQn channel. | |||
* This parameter can be a value between 0 and 15 | |||
* A lower priority value indicates a higher priority | |||
* @param SubPriority the subpriority level for the IRQ channel. | |||
* This parameter can be a value between 0 and 15 | |||
* A lower priority value indicates a higher priority. | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) | |||
{ | |||
uint32_t prioritygroup = 0x00U; | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); | |||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); | |||
prioritygroup = NVIC_GetPriorityGrouping(); | |||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); | |||
} | |||
/** | |||
* @brief Enables a device specific interrupt in the NVIC interrupt controller. | |||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() | |||
* function should be called before. | |||
* @param IRQn External interrupt number. | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); | |||
/* Enable interrupt */ | |||
NVIC_EnableIRQ(IRQn); | |||
} | |||
/** | |||
* @brief Disables a device specific interrupt in the NVIC interrupt controller. | |||
* @param IRQn External interrupt number. | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); | |||
/* Disable interrupt */ | |||
NVIC_DisableIRQ(IRQn); | |||
} | |||
/** | |||
* @brief Initiates a system reset request to reset the MCU. | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_SystemReset(void) | |||
{ | |||
/* System Reset */ | |||
NVIC_SystemReset(); | |||
} | |||
/** | |||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. | |||
* Counter is in free running mode to generate periodic interrupts. | |||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts. | |||
* @retval status: - 0 Function succeeded. | |||
* - 1 Function failed. | |||
*/ | |||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) | |||
{ | |||
return SysTick_Config(TicksNumb); | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions | |||
* @brief Cortex control functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### Peripheral Control functions ##### | |||
============================================================================== | |||
[..] | |||
This subsection provides a set of functions allowing to control the CORTEX | |||
(NVIC, SYSTICK, MPU) functionalities. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
#if (__MPU_PRESENT == 1U) | |||
/** | |||
* @brief Disables the MPU | |||
* @retval None | |||
*/ | |||
void HAL_MPU_Disable(void) | |||
{ | |||
/* Make sure outstanding transfers are done */ | |||
__DMB(); | |||
/* Disable fault exceptions */ | |||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; | |||
/* Disable the MPU and clear the control register*/ | |||
MPU->CTRL = 0U; | |||
} | |||
/** | |||
* @brief Enable the MPU. | |||
* @param MPU_Control Specifies the control mode of the MPU during hard fault, | |||
* NMI, FAULTMASK and privileged access to the default memory | |||
* This parameter can be one of the following values: | |||
* @arg MPU_HFNMI_PRIVDEF_NONE | |||
* @arg MPU_HARDFAULT_NMI | |||
* @arg MPU_PRIVILEGED_DEFAULT | |||
* @arg MPU_HFNMI_PRIVDEF | |||
* @retval None | |||
*/ | |||
void HAL_MPU_Enable(uint32_t MPU_Control) | |||
{ | |||
/* Enable the MPU */ | |||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; | |||
/* Enable fault exceptions */ | |||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; | |||
/* Ensure MPU setting take effects */ | |||
__DSB(); | |||
__ISB(); | |||
} | |||
/** | |||
* @brief Initializes and configures the Region and the memory to be protected. | |||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains | |||
* the initialization and configuration information. | |||
* @retval None | |||
*/ | |||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); | |||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); | |||
/* Set the Region number */ | |||
MPU->RNR = MPU_Init->Number; | |||
if ((MPU_Init->Enable) != RESET) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); | |||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); | |||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); | |||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); | |||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); | |||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); | |||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); | |||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); | |||
MPU->RBAR = MPU_Init->BaseAddress; | |||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | | |||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | | |||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | | |||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | | |||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | | |||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | | |||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | | |||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | | |||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); | |||
} | |||
else | |||
{ | |||
MPU->RBAR = 0x00U; | |||
MPU->RASR = 0x00U; | |||
} | |||
} | |||
#endif /* __MPU_PRESENT */ | |||
/** | |||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller. | |||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) | |||
*/ | |||
uint32_t HAL_NVIC_GetPriorityGrouping(void) | |||
{ | |||
/* Get the PRIGROUP[10:8] field value */ | |||
return NVIC_GetPriorityGrouping(); | |||
} | |||
/** | |||
* @brief Gets the priority of an interrupt. | |||
* @param IRQn External interrupt number. | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @param PriorityGroup the priority grouping bits length. | |||
* This parameter can be one of the following values: | |||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority | |||
* 4 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority | |||
* 3 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority | |||
* 2 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority | |||
* 1 bits for subpriority | |||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority | |||
* 0 bits for subpriority | |||
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). | |||
* @param pSubPriority Pointer on the Subpriority value (starting from 0). | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); | |||
/* Get priority for Cortex-M system or device specific interrupts */ | |||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); | |||
} | |||
/** | |||
* @brief Sets Pending bit of an external interrupt. | |||
* @param IRQn External interrupt number | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); | |||
/* Set interrupt pending */ | |||
NVIC_SetPendingIRQ(IRQn); | |||
} | |||
/** | |||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC | |||
* and returns the pending bit for the specified interrupt). | |||
* @param IRQn External interrupt number. | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @retval status: - 0 Interrupt status is not pending. | |||
* - 1 Interrupt status is pending. | |||
*/ | |||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); | |||
/* Return 1 if pending else 0 */ | |||
return NVIC_GetPendingIRQ(IRQn); | |||
} | |||
/** | |||
* @brief Clears the pending bit of an external interrupt. | |||
* @param IRQn External interrupt number. | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @retval None | |||
*/ | |||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); | |||
/* Clear pending interrupt */ | |||
NVIC_ClearPendingIRQ(IRQn); | |||
} | |||
/** | |||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). | |||
* @param IRQn External interrupt number | |||
* This parameter can be an enumerator of IRQn_Type enumeration | |||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) | |||
* @retval status: - 0 Interrupt status is not pending. | |||
* - 1 Interrupt status is pending. | |||
*/ | |||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); | |||
/* Return 1 if active else 0 */ | |||
return NVIC_GetActive(IRQn); | |||
} | |||
/** | |||
* @brief Configures the SysTick clock source. | |||
* @param CLKSource specifies the SysTick clock source. | |||
* This parameter can be one of the following values: | |||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. | |||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. | |||
* @retval None | |||
*/ | |||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); | |||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK) | |||
{ | |||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; | |||
} | |||
else | |||
{ | |||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; | |||
} | |||
} | |||
/** | |||
* @brief This function handles SYSTICK interrupt request. | |||
* @retval None | |||
*/ | |||
void HAL_SYSTICK_IRQHandler(void) | |||
{ | |||
HAL_SYSTICK_Callback(); | |||
} | |||
/** | |||
* @brief SYSTICK callback. | |||
* @retval None | |||
*/ | |||
__weak void HAL_SYSTICK_Callback(void) | |||
{ | |||
/* NOTE : This function Should not be modified, when the callback is needed, | |||
the HAL_SYSTICK_Callback could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_CORTEX_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,315 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_dma_ex.c | |||
* @author MCD Application Team | |||
* @brief DMA Extension HAL module driver | |||
* This file provides firmware functions to manage the following | |||
* functionalities of the DMA Extension peripheral: | |||
* + Extended features functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### How to use this driver ##### | |||
============================================================================== | |||
[..] | |||
The DMA Extension HAL driver can be used as follows: | |||
(#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function | |||
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. | |||
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. | |||
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default. | |||
-@- In Multi (Double) buffer mode, it is possible to update the base address for | |||
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup DMAEx DMAEx | |||
* @brief DMA Extended HAL module driver | |||
* @{ | |||
*/ | |||
#ifdef HAL_DMA_MODULE_ENABLED | |||
/* Private types -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private Constants ---------------------------------------------------------*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @addtogroup DMAEx_Private_Functions | |||
* @{ | |||
*/ | |||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions ---------------------------------------------------------*/ | |||
/** @addtogroup DMAEx_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup DMAEx_Exported_Functions_Group1 | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Extended features functions ##### | |||
=============================================================================== | |||
[..] This section provides functions allowing to: | |||
(+) Configure the source, destination address and data length and | |||
Start MultiBuffer DMA transfer | |||
(+) Configure the source, destination address and data length and | |||
Start MultiBuffer DMA transfer with interrupt | |||
(+) Change on the fly the memory0 or memory1 address. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Starts the multi_buffer DMA Transfer. | |||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains | |||
* the configuration information for the specified DMA Stream. | |||
* @param SrcAddress The source memory Buffer address | |||
* @param DstAddress The destination memory Buffer address | |||
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer | |||
* @param DataLength The length of data to be transferred from source to destination | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) | |||
{ | |||
HAL_StatusTypeDef status = HAL_OK; | |||
/* Check the parameters */ | |||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); | |||
/* Memory-to-memory transfer not supported in double buffering mode */ | |||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) | |||
{ | |||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; | |||
status = HAL_ERROR; | |||
} | |||
else | |||
{ | |||
/* Process Locked */ | |||
__HAL_LOCK(hdma); | |||
if(HAL_DMA_STATE_READY == hdma->State) | |||
{ | |||
/* Change DMA peripheral state */ | |||
hdma->State = HAL_DMA_STATE_BUSY; | |||
/* Enable the double buffer mode */ | |||
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; | |||
/* Configure DMA Stream destination address */ | |||
hdma->Instance->M1AR = SecondMemAddress; | |||
/* Configure the source, destination address and the data length */ | |||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); | |||
/* Enable the peripheral */ | |||
__HAL_DMA_ENABLE(hdma); | |||
} | |||
else | |||
{ | |||
/* Return error status */ | |||
status = HAL_BUSY; | |||
} | |||
} | |||
return status; | |||
} | |||
/** | |||
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled. | |||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains | |||
* the configuration information for the specified DMA Stream. | |||
* @param SrcAddress The source memory Buffer address | |||
* @param DstAddress The destination memory Buffer address | |||
* @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer | |||
* @param DataLength The length of data to be transferred from source to destination | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) | |||
{ | |||
HAL_StatusTypeDef status = HAL_OK; | |||
/* Check the parameters */ | |||
assert_param(IS_DMA_BUFFER_SIZE(DataLength)); | |||
/* Memory-to-memory transfer not supported in double buffering mode */ | |||
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) | |||
{ | |||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; | |||
return HAL_ERROR; | |||
} | |||
/* Check callback functions */ | |||
if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback)) | |||
{ | |||
hdma->ErrorCode = HAL_DMA_ERROR_PARAM; | |||
return HAL_ERROR; | |||
} | |||
/* Process locked */ | |||
__HAL_LOCK(hdma); | |||
if(HAL_DMA_STATE_READY == hdma->State) | |||
{ | |||
/* Change DMA peripheral state */ | |||
hdma->State = HAL_DMA_STATE_BUSY; | |||
/* Initialize the error code */ | |||
hdma->ErrorCode = HAL_DMA_ERROR_NONE; | |||
/* Enable the Double buffer mode */ | |||
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; | |||
/* Configure DMA Stream destination address */ | |||
hdma->Instance->M1AR = SecondMemAddress; | |||
/* Configure the source, destination address and the data length */ | |||
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); | |||
/* Clear all flags */ | |||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); | |||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); | |||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); | |||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); | |||
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); | |||
/* Enable Common interrupts*/ | |||
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; | |||
hdma->Instance->FCR |= DMA_IT_FE; | |||
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) | |||
{ | |||
hdma->Instance->CR |= DMA_IT_HT; | |||
} | |||
/* Enable the peripheral */ | |||
__HAL_DMA_ENABLE(hdma); | |||
} | |||
else | |||
{ | |||
/* Process unlocked */ | |||
__HAL_UNLOCK(hdma); | |||
/* Return error status */ | |||
status = HAL_BUSY; | |||
} | |||
return status; | |||
} | |||
/** | |||
* @brief Change the memory0 or memory1 address on the fly. | |||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains | |||
* the configuration information for the specified DMA Stream. | |||
* @param Address The new address | |||
* @param memory the memory to be changed, This parameter can be one of | |||
* the following values: | |||
* MEMORY0 / | |||
* MEMORY1 | |||
* @note The MEMORY0 address can be changed only when the current transfer use | |||
* MEMORY1 and the MEMORY1 address can be changed only when the current | |||
* transfer use MEMORY0. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) | |||
{ | |||
if(memory == MEMORY0) | |||
{ | |||
/* change the memory0 address */ | |||
hdma->Instance->M0AR = Address; | |||
} | |||
else | |||
{ | |||
/* change the memory1 address */ | |||
hdma->Instance->M1AR = Address; | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup DMAEx_Private_Functions | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Set the DMA Transfer parameter. | |||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains | |||
* the configuration information for the specified DMA Stream. | |||
* @param SrcAddress The source memory Buffer address | |||
* @param DstAddress The destination memory Buffer address | |||
* @param DataLength The length of data to be transferred from source to destination | |||
* @retval HAL status | |||
*/ | |||
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) | |||
{ | |||
/* Configure DMA Stream data length */ | |||
hdma->Instance->NDTR = DataLength; | |||
/* Peripheral to Memory */ | |||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) | |||
{ | |||
/* Configure DMA Stream destination address */ | |||
hdma->Instance->PAR = DstAddress; | |||
/* Configure DMA Stream source address */ | |||
hdma->Instance->M0AR = SrcAddress; | |||
} | |||
/* Memory to Peripheral */ | |||
else | |||
{ | |||
/* Configure DMA Stream source address */ | |||
hdma->Instance->PAR = SrcAddress; | |||
/* Configure DMA Stream destination address */ | |||
hdma->Instance->M0AR = DstAddress; | |||
} | |||
} | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_DMA_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,559 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_exti.c | |||
* @author MCD Application Team | |||
* @brief EXTI HAL module driver. | |||
* This file provides firmware functions to manage the following | |||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral: | |||
* + Initialization and de-initialization functions | |||
* + IO operation functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### EXTI Peripheral features ##### | |||
============================================================================== | |||
[..] | |||
(+) Each Exti line can be configured within this driver. | |||
(+) Exti line can be configured in 3 different modes | |||
(++) Interrupt | |||
(++) Event | |||
(++) Both of them | |||
(+) Configurable Exti lines can be configured with 3 different triggers | |||
(++) Rising | |||
(++) Falling | |||
(++) Both of them | |||
(+) When set in interrupt mode, configurable Exti lines have two different | |||
interrupts pending registers which allow to distinguish which transition | |||
occurs: | |||
(++) Rising edge pending interrupt | |||
(++) Falling | |||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can | |||
be selected through multiplexer. | |||
##### How to use this driver ##### | |||
============================================================================== | |||
[..] | |||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). | |||
(++) Choose the interrupt line number by setting "Line" member from | |||
EXTI_ConfigTypeDef structure. | |||
(++) Configure the interrupt and/or event mode using "Mode" member from | |||
EXTI_ConfigTypeDef structure. | |||
(++) For configurable lines, configure rising and/or falling trigger | |||
"Trigger" member from EXTI_ConfigTypeDef structure. | |||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" | |||
member from GPIO_InitTypeDef structure. | |||
(#) Get current Exti configuration of a dedicated line using | |||
HAL_EXTI_GetConfigLine(). | |||
(++) Provide exiting handle as parameter. | |||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. | |||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). | |||
(++) Provide exiting handle as parameter. | |||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). | |||
(++) Provide exiting handle as first parameter. | |||
(++) Provide which callback will be registered using one value from | |||
EXTI_CallbackIDTypeDef. | |||
(++) Provide callback function pointer. | |||
(#) Get interrupt pending bit using HAL_EXTI_GetPending(). | |||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending(). | |||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI(). | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2018 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @addtogroup EXTI | |||
* @{ | |||
*/ | |||
/** MISRA C:2012 deviation rule has been granted for following rule: | |||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out | |||
* of bounds [0,3] in following API : | |||
* HAL_EXTI_SetConfigLine | |||
* HAL_EXTI_GetConfigLine | |||
* HAL_EXTI_ClearConfigLine | |||
*/ | |||
#ifdef HAL_EXTI_MODULE_ENABLED | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private defines -----------------------------------------------------------*/ | |||
/** @defgroup EXTI_Private_Constants EXTI Private Constants | |||
* @{ | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macros ------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @addtogroup EXTI_Exported_Functions | |||
* @{ | |||
*/ | |||
/** @addtogroup EXTI_Exported_Functions_Group1 | |||
* @brief Configuration functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Configuration functions ##### | |||
=============================================================================== | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Set configuration of a dedicated Exti line. | |||
* @param hexti Exti handle. | |||
* @param pExtiConfig Pointer on EXTI configuration to be set. | |||
* @retval HAL Status. | |||
*/ | |||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) | |||
{ | |||
uint32_t regval; | |||
uint32_t linepos; | |||
uint32_t maskline; | |||
/* Check null pointer */ | |||
if ((hexti == NULL) || (pExtiConfig == NULL)) | |||
{ | |||
return HAL_ERROR; | |||
} | |||
/* Check parameters */ | |||
assert_param(IS_EXTI_LINE(pExtiConfig->Line)); | |||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); | |||
/* Assign line number to handle */ | |||
hexti->Line = pExtiConfig->Line; | |||
/* Compute line mask */ | |||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); | |||
maskline = (1uL << linepos); | |||
/* Configure triggers for configurable lines */ | |||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) | |||
{ | |||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); | |||
/* Configure rising trigger */ | |||
/* Mask or set line */ | |||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) | |||
{ | |||
EXTI->RTSR |= maskline; | |||
} | |||
else | |||
{ | |||
EXTI->RTSR &= ~maskline; | |||
} | |||
/* Configure falling trigger */ | |||
/* Mask or set line */ | |||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) | |||
{ | |||
EXTI->FTSR |= maskline; | |||
} | |||
else | |||
{ | |||
EXTI->FTSR &= ~maskline; | |||
} | |||
/* Configure gpio port selection in case of gpio exti line */ | |||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) | |||
{ | |||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); | |||
assert_param(IS_EXTI_GPIO_PIN(linepos)); | |||
regval = SYSCFG->EXTICR[linepos >> 2u]; | |||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); | |||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); | |||
SYSCFG->EXTICR[linepos >> 2u] = regval; | |||
} | |||
} | |||
/* Configure interrupt mode : read current mode */ | |||
/* Mask or set line */ | |||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) | |||
{ | |||
EXTI->IMR |= maskline; | |||
} | |||
else | |||
{ | |||
EXTI->IMR &= ~maskline; | |||
} | |||
/* Configure event mode : read current mode */ | |||
/* Mask or set line */ | |||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) | |||
{ | |||
EXTI->EMR |= maskline; | |||
} | |||
else | |||
{ | |||
EXTI->EMR &= ~maskline; | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Get configuration of a dedicated Exti line. | |||
* @param hexti Exti handle. | |||
* @param pExtiConfig Pointer on structure to store Exti configuration. | |||
* @retval HAL Status. | |||
*/ | |||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) | |||
{ | |||
uint32_t regval; | |||
uint32_t linepos; | |||
uint32_t maskline; | |||
/* Check null pointer */ | |||
if ((hexti == NULL) || (pExtiConfig == NULL)) | |||
{ | |||
return HAL_ERROR; | |||
} | |||
/* Check the parameter */ | |||
assert_param(IS_EXTI_LINE(hexti->Line)); | |||
/* Store handle line number to configuration structure */ | |||
pExtiConfig->Line = hexti->Line; | |||
/* Compute line mask */ | |||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK); | |||
maskline = (1uL << linepos); | |||
/* 1] Get core mode : interrupt */ | |||
/* Check if selected line is enable */ | |||
if ((EXTI->IMR & maskline) != 0x00u) | |||
{ | |||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT; | |||
} | |||
else | |||
{ | |||
pExtiConfig->Mode = EXTI_MODE_NONE; | |||
} | |||
/* Get event mode */ | |||
/* Check if selected line is enable */ | |||
if ((EXTI->EMR & maskline) != 0x00u) | |||
{ | |||
pExtiConfig->Mode |= EXTI_MODE_EVENT; | |||
} | |||
/* 2] Get trigger for configurable lines : rising */ | |||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) | |||
{ | |||
/* Check if configuration of selected line is enable */ | |||
if ((EXTI->RTSR & maskline) != 0x00u) | |||
{ | |||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING; | |||
} | |||
else | |||
{ | |||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE; | |||
} | |||
/* Get falling configuration */ | |||
/* Check if configuration of selected line is enable */ | |||
if ((EXTI->FTSR & maskline) != 0x00u) | |||
{ | |||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; | |||
} | |||
/* Get Gpio port selection for gpio lines */ | |||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) | |||
{ | |||
assert_param(IS_EXTI_GPIO_PIN(linepos)); | |||
regval = SYSCFG->EXTICR[linepos >> 2u]; | |||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); | |||
} | |||
else | |||
{ | |||
pExtiConfig->GPIOSel = 0x00u; | |||
} | |||
} | |||
else | |||
{ | |||
/* No Trigger selected */ | |||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE; | |||
pExtiConfig->GPIOSel = 0x00u; | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Clear whole configuration of a dedicated Exti line. | |||
* @param hexti Exti handle. | |||
* @retval HAL Status. | |||
*/ | |||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) | |||
{ | |||
uint32_t regval; | |||
uint32_t linepos; | |||
uint32_t maskline; | |||
/* Check null pointer */ | |||
if (hexti == NULL) | |||
{ | |||
return HAL_ERROR; | |||
} | |||
/* Check the parameter */ | |||
assert_param(IS_EXTI_LINE(hexti->Line)); | |||
/* compute line mask */ | |||
linepos = (hexti->Line & EXTI_PIN_MASK); | |||
maskline = (1uL << linepos); | |||
/* 1] Clear interrupt mode */ | |||
EXTI->IMR = (EXTI->IMR & ~maskline); | |||
/* 2] Clear event mode */ | |||
EXTI->EMR = (EXTI->EMR & ~maskline); | |||
/* 3] Clear triggers in case of configurable lines */ | |||
if ((hexti->Line & EXTI_CONFIG) != 0x00u) | |||
{ | |||
EXTI->RTSR = (EXTI->RTSR & ~maskline); | |||
EXTI->FTSR = (EXTI->FTSR & ~maskline); | |||
/* Get Gpio port selection for gpio lines */ | |||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) | |||
{ | |||
assert_param(IS_EXTI_GPIO_PIN(linepos)); | |||
regval = SYSCFG->EXTICR[linepos >> 2u]; | |||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); | |||
SYSCFG->EXTICR[linepos >> 2u] = regval; | |||
} | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Register callback for a dedicated Exti line. | |||
* @param hexti Exti handle. | |||
* @param CallbackID User callback identifier. | |||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. | |||
* @param pPendingCbfn function pointer to be stored as callback. | |||
* @retval HAL Status. | |||
*/ | |||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) | |||
{ | |||
HAL_StatusTypeDef status = HAL_OK; | |||
switch (CallbackID) | |||
{ | |||
case HAL_EXTI_COMMON_CB_ID: | |||
hexti->PendingCallback = pPendingCbfn; | |||
break; | |||
default: | |||
status = HAL_ERROR; | |||
break; | |||
} | |||
return status; | |||
} | |||
/** | |||
* @brief Store line number as handle private field. | |||
* @param hexti Exti handle. | |||
* @param ExtiLine Exti line number. | |||
* This parameter can be from 0 to @ref EXTI_LINE_NB. | |||
* @retval HAL Status. | |||
*/ | |||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_EXTI_LINE(ExtiLine)); | |||
/* Check null pointer */ | |||
if (hexti == NULL) | |||
{ | |||
return HAL_ERROR; | |||
} | |||
else | |||
{ | |||
/* Store line number as handle private field */ | |||
hexti->Line = ExtiLine; | |||
return HAL_OK; | |||
} | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @addtogroup EXTI_Exported_Functions_Group2 | |||
* @brief EXTI IO functions. | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### IO operation functions ##### | |||
=============================================================================== | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Handle EXTI interrupt request. | |||
* @param hexti Exti handle. | |||
* @retval none. | |||
*/ | |||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) | |||
{ | |||
uint32_t regval; | |||
uint32_t maskline; | |||
/* Compute line mask */ | |||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); | |||
/* Get pending bit */ | |||
regval = (EXTI->PR & maskline); | |||
if (regval != 0x00u) | |||
{ | |||
/* Clear pending bit */ | |||
EXTI->PR = maskline; | |||
/* Call callback */ | |||
if (hexti->PendingCallback != NULL) | |||
{ | |||
hexti->PendingCallback(); | |||
} | |||
} | |||
} | |||
/** | |||
* @brief Get interrupt pending bit of a dedicated line. | |||
* @param hexti Exti handle. | |||
* @param Edge Specify which pending edge as to be checked. | |||
* This parameter can be one of the following values: | |||
* @arg @ref EXTI_TRIGGER_RISING_FALLING | |||
* This parameter is kept for compatibility with other series. | |||
* @retval 1 if interrupt is pending else 0. | |||
*/ | |||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) | |||
{ | |||
uint32_t regval; | |||
uint32_t linepos; | |||
uint32_t maskline; | |||
/* Check parameters */ | |||
assert_param(IS_EXTI_LINE(hexti->Line)); | |||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); | |||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); | |||
/* Compute line mask */ | |||
linepos = (hexti->Line & EXTI_PIN_MASK); | |||
maskline = (1uL << linepos); | |||
/* return 1 if bit is set else 0 */ | |||
regval = ((EXTI->PR & maskline) >> linepos); | |||
return regval; | |||
} | |||
/** | |||
* @brief Clear interrupt pending bit of a dedicated line. | |||
* @param hexti Exti handle. | |||
* @param Edge Specify which pending edge as to be clear. | |||
* This parameter can be one of the following values: | |||
* @arg @ref EXTI_TRIGGER_RISING_FALLING | |||
* This parameter is kept for compatibility with other series. | |||
* @retval None. | |||
*/ | |||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) | |||
{ | |||
uint32_t maskline; | |||
/* Check parameters */ | |||
assert_param(IS_EXTI_LINE(hexti->Line)); | |||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); | |||
assert_param(IS_EXTI_PENDING_EDGE(Edge)); | |||
/* Compute line mask */ | |||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); | |||
/* Clear Pending bit */ | |||
EXTI->PR = maskline; | |||
} | |||
/** | |||
* @brief Generate a software interrupt for a dedicated line. | |||
* @param hexti Exti handle. | |||
* @retval None. | |||
*/ | |||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) | |||
{ | |||
uint32_t maskline; | |||
/* Check parameters */ | |||
assert_param(IS_EXTI_LINE(hexti->Line)); | |||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); | |||
/* Compute line mask */ | |||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); | |||
/* Generate Software interrupt */ | |||
EXTI->SWIER = maskline; | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_EXTI_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,778 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_flash.c | |||
* @author MCD Application Team | |||
* @brief FLASH HAL module driver. | |||
* This file provides firmware functions to manage the following | |||
* functionalities of the internal FLASH memory: | |||
* + Program operations functions | |||
* + Memory Control functions | |||
* + Peripheral Errors functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### FLASH peripheral features ##### | |||
============================================================================== | |||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses | |||
to the Flash memory. It implements the erase and program Flash memory operations | |||
and the read and write protection mechanisms. | |||
[..] The Flash memory interface accelerates code execution with a system of instruction | |||
prefetch and cache lines. | |||
[..] The FLASH main features are: | |||
(+) Flash memory read operations | |||
(+) Flash memory program/erase operations | |||
(+) Read / write protections | |||
(+) Prefetch on I-Code | |||
(+) 64 cache lines of 128 bits on I-Code | |||
(+) 8 cache lines of 128 bits on D-Code | |||
##### How to use this driver ##### | |||
============================================================================== | |||
[..] | |||
This driver provides functions and macros to configure and program the FLASH | |||
memory of all STM32F4xx devices. | |||
(#) FLASH Memory IO Programming functions: | |||
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and | |||
HAL_FLASH_Lock() functions | |||
(++) Program functions: byte, half word, word and double word | |||
(++) There Two modes of programming : | |||
(+++) Polling mode using HAL_FLASH_Program() function | |||
(+++) Interrupt mode using HAL_FLASH_Program_IT() function | |||
(#) Interrupts and flags management functions : | |||
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() | |||
(++) Wait for last FLASH operation according to its status | |||
(++) Get error flag status by calling HAL_SetErrorCode() | |||
[..] | |||
In addition to these functions, this driver includes a set of macros allowing | |||
to handle the following operations: | |||
(+) Set the latency | |||
(+) Enable/Disable the prefetch buffer | |||
(+) Enable/Disable the Instruction cache and the Data cache | |||
(+) Reset the Instruction cache and the Data cache | |||
(+) Enable/Disable the FLASH interrupts | |||
(+) Monitor the FLASH flags status | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup FLASH FLASH | |||
* @brief FLASH HAL module driver | |||
* @{ | |||
*/ | |||
#ifdef HAL_FLASH_MODULE_ENABLED | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private define ------------------------------------------------------------*/ | |||
/** @addtogroup FLASH_Private_Constants | |||
* @{ | |||
*/ | |||
#define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/** @addtogroup FLASH_Private_Variables | |||
* @{ | |||
*/ | |||
/* Variable used for Erase sectors under interruption */ | |||
FLASH_ProcessTypeDef pFlash; | |||
/** | |||
* @} | |||
*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/** @addtogroup FLASH_Private_Functions | |||
* @{ | |||
*/ | |||
/* Program operations */ | |||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); | |||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data); | |||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); | |||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); | |||
static void FLASH_SetErrorCode(void); | |||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); | |||
/** | |||
* @} | |||
*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions | |||
* @brief Programming operation functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Programming operation functions ##### | |||
=============================================================================== | |||
[..] | |||
This subsection provides a set of functions allowing to manage the FLASH | |||
program operations. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Program byte, halfword, word or double word at a specified address | |||
* @param TypeProgram Indicate the way to program at a specified address. | |||
* This parameter can be a value of @ref FLASH_Type_Program | |||
* @param Address specifies the address to be programmed. | |||
* @param Data specifies the data to be programmed | |||
* | |||
* @retval HAL_StatusTypeDef HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) | |||
{ | |||
HAL_StatusTypeDef status = HAL_ERROR; | |||
/* Process Locked */ | |||
__HAL_LOCK(&pFlash); | |||
/* Check the parameters */ | |||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); | |||
/* Wait for last operation to be completed */ | |||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); | |||
if(status == HAL_OK) | |||
{ | |||
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) | |||
{ | |||
/*Program byte (8-bit) at a specified address.*/ | |||
FLASH_Program_Byte(Address, (uint8_t) Data); | |||
} | |||
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) | |||
{ | |||
/*Program halfword (16-bit) at a specified address.*/ | |||
FLASH_Program_HalfWord(Address, (uint16_t) Data); | |||
} | |||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) | |||
{ | |||
/*Program word (32-bit) at a specified address.*/ | |||
FLASH_Program_Word(Address, (uint32_t) Data); | |||
} | |||
else | |||
{ | |||
/*Program double word (64-bit) at a specified address.*/ | |||
FLASH_Program_DoubleWord(Address, Data); | |||
} | |||
/* Wait for last operation to be completed */ | |||
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); | |||
/* If the program operation is completed, disable the PG Bit */ | |||
FLASH->CR &= (~FLASH_CR_PG); | |||
} | |||
/* Process Unlocked */ | |||
__HAL_UNLOCK(&pFlash); | |||
return status; | |||
} | |||
/** | |||
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. | |||
* @param TypeProgram Indicate the way to program at a specified address. | |||
* This parameter can be a value of @ref FLASH_Type_Program | |||
* @param Address specifies the address to be programmed. | |||
* @param Data specifies the data to be programmed | |||
* | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) | |||
{ | |||
HAL_StatusTypeDef status = HAL_OK; | |||
/* Process Locked */ | |||
__HAL_LOCK(&pFlash); | |||
/* Check the parameters */ | |||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); | |||
/* Enable End of FLASH Operation interrupt */ | |||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); | |||
/* Enable Error source interrupt */ | |||
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); | |||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; | |||
pFlash.Address = Address; | |||
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE) | |||
{ | |||
/*Program byte (8-bit) at a specified address.*/ | |||
FLASH_Program_Byte(Address, (uint8_t) Data); | |||
} | |||
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD) | |||
{ | |||
/*Program halfword (16-bit) at a specified address.*/ | |||
FLASH_Program_HalfWord(Address, (uint16_t) Data); | |||
} | |||
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD) | |||
{ | |||
/*Program word (32-bit) at a specified address.*/ | |||
FLASH_Program_Word(Address, (uint32_t) Data); | |||
} | |||
else | |||
{ | |||
/*Program double word (64-bit) at a specified address.*/ | |||
FLASH_Program_DoubleWord(Address, Data); | |||
} | |||
return status; | |||
} | |||
/** | |||
* @brief This function handles FLASH interrupt request. | |||
* @retval None | |||
*/ | |||
void HAL_FLASH_IRQHandler(void) | |||
{ | |||
uint32_t addresstmp = 0U; | |||
/* Check FLASH operation error flags */ | |||
#if defined(FLASH_SR_RDERR) | |||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ | |||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) | |||
#else | |||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ | |||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) | |||
#endif /* FLASH_SR_RDERR */ | |||
{ | |||
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) | |||
{ | |||
/*return the faulty sector*/ | |||
addresstmp = pFlash.Sector; | |||
pFlash.Sector = 0xFFFFFFFFU; | |||
} | |||
else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) | |||
{ | |||
/*return the faulty bank*/ | |||
addresstmp = pFlash.Bank; | |||
} | |||
else | |||
{ | |||
/*return the faulty address*/ | |||
addresstmp = pFlash.Address; | |||
} | |||
/*Save the Error code*/ | |||
FLASH_SetErrorCode(); | |||
/* FLASH error interrupt user callback */ | |||
HAL_FLASH_OperationErrorCallback(addresstmp); | |||
/*Stop the procedure ongoing*/ | |||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; | |||
} | |||
/* Check FLASH End of Operation flag */ | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) | |||
{ | |||
/* Clear FLASH End of Operation pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); | |||
if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE) | |||
{ | |||
/*Nb of sector to erased can be decreased*/ | |||
pFlash.NbSectorsToErase--; | |||
/* Check if there are still sectors to erase*/ | |||
if(pFlash.NbSectorsToErase != 0U) | |||
{ | |||
addresstmp = pFlash.Sector; | |||
/*Indicate user which sector has been erased*/ | |||
HAL_FLASH_EndOfOperationCallback(addresstmp); | |||
/*Increment sector number*/ | |||
pFlash.Sector++; | |||
addresstmp = pFlash.Sector; | |||
FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase); | |||
} | |||
else | |||
{ | |||
/*No more sectors to Erase, user callback can be called.*/ | |||
/*Reset Sector and stop Erase sectors procedure*/ | |||
pFlash.Sector = addresstmp = 0xFFFFFFFFU; | |||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; | |||
/* Flush the caches to be sure of the data consistency */ | |||
FLASH_FlushCaches() ; | |||
/* FLASH EOP interrupt user callback */ | |||
HAL_FLASH_EndOfOperationCallback(addresstmp); | |||
} | |||
} | |||
else | |||
{ | |||
if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) | |||
{ | |||
/* MassErase ended. Return the selected bank */ | |||
/* Flush the caches to be sure of the data consistency */ | |||
FLASH_FlushCaches() ; | |||
/* FLASH EOP interrupt user callback */ | |||
HAL_FLASH_EndOfOperationCallback(pFlash.Bank); | |||
} | |||
else | |||
{ | |||
/*Program ended. Return the selected address*/ | |||
/* FLASH EOP interrupt user callback */ | |||
HAL_FLASH_EndOfOperationCallback(pFlash.Address); | |||
} | |||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE; | |||
} | |||
} | |||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) | |||
{ | |||
/* Operation is completed, disable the PG, SER, SNB and MER Bits */ | |||
CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT)); | |||
/* Disable End of FLASH Operation interrupt */ | |||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); | |||
/* Disable Error source interrupt */ | |||
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); | |||
/* Process Unlocked */ | |||
__HAL_UNLOCK(&pFlash); | |||
} | |||
} | |||
/** | |||
* @brief FLASH end of operation interrupt callback | |||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure | |||
* Mass Erase: Bank number which has been requested to erase | |||
* Sectors Erase: Sector which has been erased | |||
* (if 0xFFFFFFFFU, it means that all the selected sectors have been erased) | |||
* Program: Address which was selected for data program | |||
* @retval None | |||
*/ | |||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) | |||
{ | |||
/* Prevent unused argument(s) compilation warning */ | |||
UNUSED(ReturnValue); | |||
/* NOTE : This function Should not be modified, when the callback is needed, | |||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @brief FLASH operation error interrupt callback | |||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure | |||
* Mass Erase: Bank number which has been requested to erase | |||
* Sectors Erase: Sector number which returned an error | |||
* Program: Address which was selected for data program | |||
* @retval None | |||
*/ | |||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) | |||
{ | |||
/* Prevent unused argument(s) compilation warning */ | |||
UNUSED(ReturnValue); | |||
/* NOTE : This function Should not be modified, when the callback is needed, | |||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions | |||
* @brief management functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Peripheral Control functions ##### | |||
=============================================================================== | |||
[..] | |||
This subsection provides a set of functions allowing to control the FLASH | |||
memory operations. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Unlock the FLASH control register access | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_Unlock(void) | |||
{ | |||
HAL_StatusTypeDef status = HAL_OK; | |||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) | |||
{ | |||
/* Authorize the FLASH Registers access */ | |||
WRITE_REG(FLASH->KEYR, FLASH_KEY1); | |||
WRITE_REG(FLASH->KEYR, FLASH_KEY2); | |||
/* Verify Flash is unlocked */ | |||
if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) | |||
{ | |||
status = HAL_ERROR; | |||
} | |||
} | |||
return status; | |||
} | |||
/** | |||
* @brief Locks the FLASH control register access | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_Lock(void) | |||
{ | |||
/* Set the LOCK Bit to lock the FLASH Registers access */ | |||
FLASH->CR |= FLASH_CR_LOCK; | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Unlock the FLASH Option Control Registers access. | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) | |||
{ | |||
if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) | |||
{ | |||
/* Authorizes the Option Byte register programming */ | |||
FLASH->OPTKEYR = FLASH_OPT_KEY1; | |||
FLASH->OPTKEYR = FLASH_OPT_KEY2; | |||
} | |||
else | |||
{ | |||
return HAL_ERROR; | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Lock the FLASH Option Control Registers access. | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) | |||
{ | |||
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ | |||
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Launch the option byte loading. | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) | |||
{ | |||
/* Set the OPTSTRT bit in OPTCR register */ | |||
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; | |||
/* Wait for last operation to be completed */ | |||
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions | |||
* @brief Peripheral Errors functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Peripheral Errors functions ##### | |||
=============================================================================== | |||
[..] | |||
This subsection permits to get in run-time Errors of the FLASH peripheral. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Get the specific FLASH error flag. | |||
* @retval FLASH_ErrorCode: The returned value can be a combination of: | |||
* @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) | |||
* @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag | |||
* @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag | |||
* @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag | |||
* @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag | |||
* @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag | |||
*/ | |||
uint32_t HAL_FLASH_GetError(void) | |||
{ | |||
return pFlash.ErrorCode; | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @brief Wait for a FLASH operation to complete. | |||
* @param Timeout maximum flash operationtimeout | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) | |||
{ | |||
uint32_t tickstart = 0U; | |||
/* Clear Error Code */ | |||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; | |||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. | |||
Even if the FLASH operation fails, the BUSY flag will be reset and an error | |||
flag will be set */ | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) | |||
{ | |||
if(Timeout != HAL_MAX_DELAY) | |||
{ | |||
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
} | |||
/* Check FLASH End of Operation flag */ | |||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) | |||
{ | |||
/* Clear FLASH End of Operation pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); | |||
} | |||
#if defined(FLASH_SR_RDERR) | |||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ | |||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET) | |||
#else | |||
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ | |||
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET) | |||
#endif /* FLASH_SR_RDERR */ | |||
{ | |||
/*Save the error code*/ | |||
FLASH_SetErrorCode(); | |||
return HAL_ERROR; | |||
} | |||
/* If there is no error flag set */ | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Program a double word (64-bit) at a specified address. | |||
* @note This function must be used when the device voltage range is from | |||
* 2.7V to 3.6V and Vpp in the range 7V to 9V. | |||
* | |||
* @note If an erase and a program operations are requested simultaneously, | |||
* the erase operation is performed before the program one. | |||
* | |||
* @param Address specifies the address to be programmed. | |||
* @param Data specifies the data to be programmed. | |||
* @retval None | |||
*/ | |||
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_FLASH_ADDRESS(Address)); | |||
/* If the previous operation is completed, proceed to program the new data */ | |||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); | |||
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; | |||
FLASH->CR |= FLASH_CR_PG; | |||
/* Program first word */ | |||
*(__IO uint32_t*)Address = (uint32_t)Data; | |||
/* Barrier to ensure programming is performed in 2 steps, in right order | |||
(independently of compiler optimization behavior) */ | |||
__ISB(); | |||
/* Program second word */ | |||
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); | |||
} | |||
/** | |||
* @brief Program word (32-bit) at a specified address. | |||
* @note This function must be used when the device voltage range is from | |||
* 2.7V to 3.6V. | |||
* | |||
* @note If an erase and a program operations are requested simultaneously, | |||
* the erase operation is performed before the program one. | |||
* | |||
* @param Address specifies the address to be programmed. | |||
* @param Data specifies the data to be programmed. | |||
* @retval None | |||
*/ | |||
static void FLASH_Program_Word(uint32_t Address, uint32_t Data) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_FLASH_ADDRESS(Address)); | |||
/* If the previous operation is completed, proceed to program the new data */ | |||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); | |||
FLASH->CR |= FLASH_PSIZE_WORD; | |||
FLASH->CR |= FLASH_CR_PG; | |||
*(__IO uint32_t*)Address = Data; | |||
} | |||
/** | |||
* @brief Program a half-word (16-bit) at a specified address. | |||
* @note This function must be used when the device voltage range is from | |||
* 2.1V to 3.6V. | |||
* | |||
* @note If an erase and a program operations are requested simultaneously, | |||
* the erase operation is performed before the program one. | |||
* | |||
* @param Address specifies the address to be programmed. | |||
* @param Data specifies the data to be programmed. | |||
* @retval None | |||
*/ | |||
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_FLASH_ADDRESS(Address)); | |||
/* If the previous operation is completed, proceed to program the new data */ | |||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); | |||
FLASH->CR |= FLASH_PSIZE_HALF_WORD; | |||
FLASH->CR |= FLASH_CR_PG; | |||
*(__IO uint16_t*)Address = Data; | |||
} | |||
/** | |||
* @brief Program byte (8-bit) at a specified address. | |||
* @note This function must be used when the device voltage range is from | |||
* 1.8V to 3.6V. | |||
* | |||
* @note If an erase and a program operations are requested simultaneously, | |||
* the erase operation is performed before the program one. | |||
* | |||
* @param Address specifies the address to be programmed. | |||
* @param Data specifies the data to be programmed. | |||
* @retval None | |||
*/ | |||
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_FLASH_ADDRESS(Address)); | |||
/* If the previous operation is completed, proceed to program the new data */ | |||
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); | |||
FLASH->CR |= FLASH_PSIZE_BYTE; | |||
FLASH->CR |= FLASH_CR_PG; | |||
*(__IO uint8_t*)Address = Data; | |||
} | |||
/** | |||
* @brief Set the specific FLASH error flag. | |||
* @retval None | |||
*/ | |||
static void FLASH_SetErrorCode(void) | |||
{ | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) | |||
{ | |||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; | |||
/* Clear FLASH write protection error pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR); | |||
} | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) | |||
{ | |||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; | |||
/* Clear FLASH Programming alignment error pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR); | |||
} | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) | |||
{ | |||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; | |||
/* Clear FLASH Programming parallelism error pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR); | |||
} | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET) | |||
{ | |||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS; | |||
/* Clear FLASH Programming sequence error pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR); | |||
} | |||
#if defined(FLASH_SR_RDERR) | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) | |||
{ | |||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; | |||
/* Clear FLASH Proprietary readout protection error pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR); | |||
} | |||
#endif /* FLASH_SR_RDERR */ | |||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) | |||
{ | |||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; | |||
/* Clear FLASH Operation error pending bit */ | |||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR); | |||
} | |||
} | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_FLASH_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,175 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_flash_ramfunc.c | |||
* @author MCD Application Team | |||
* @brief FLASH RAMFUNC module driver. | |||
* This file provides a FLASH firmware functions which should be | |||
* executed from internal SRAM | |||
* + Stop/Start the flash interface while System Run | |||
* + Enable/Disable the flash sleep while System Run | |||
@verbatim | |||
============================================================================== | |||
##### APIs executed from Internal RAM ##### | |||
============================================================================== | |||
[..] | |||
*** ARM Compiler *** | |||
-------------------- | |||
[..] RAM functions are defined using the toolchain options. | |||
Functions that are be executed in RAM should reside in a separate | |||
source module. Using the 'Options for File' dialog you can simply change | |||
the 'Code / Const' area of a module to a memory space in physical RAM. | |||
Available memory areas are declared in the 'Target' tab of the | |||
Options for Target' dialog. | |||
*** ICCARM Compiler *** | |||
----------------------- | |||
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc". | |||
*** GNU Compiler *** | |||
-------------------- | |||
[..] RAM functions are defined using a specific toolchain attribute | |||
"__attribute__((section(".RamFunc")))". | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC | |||
* @brief FLASH functions executed from RAM | |||
* @{ | |||
*/ | |||
#ifdef HAL_FLASH_MODULE_ENABLED | |||
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \ | |||
defined(STM32F412Rx) || defined(STM32F412Cx) | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private define ------------------------------------------------------------*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM | |||
* @brief Peripheral Extended features functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### ramfunc functions ##### | |||
=============================================================================== | |||
[..] | |||
This subsection provides a set of functions that should be executed from RAM | |||
transfers. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Stop the flash interface while System Run | |||
* @note This mode is only available for STM32F41xxx/STM32F446xx devices. | |||
* @note This mode couldn't be set while executing with the flash itself. | |||
* It should be done with specific routine executed from RAM. | |||
* @retval HAL status | |||
*/ | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void) | |||
{ | |||
/* Enable Power ctrl clock */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Stop the flash interface while System Run */ | |||
SET_BIT(PWR->CR, PWR_CR_FISSR); | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Start the flash interface while System Run | |||
* @note This mode is only available for STM32F411xx/STM32F446xx devices. | |||
* @note This mode couldn't be set while executing with the flash itself. | |||
* It should be done with specific routine executed from RAM. | |||
* @retval HAL status | |||
*/ | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void) | |||
{ | |||
/* Enable Power ctrl clock */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Start the flash interface while System Run */ | |||
CLEAR_BIT(PWR->CR, PWR_CR_FISSR); | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Enable the flash sleep while System Run | |||
* @note This mode is only available for STM32F41xxx/STM32F446xx devices. | |||
* @note This mode could n't be set while executing with the flash itself. | |||
* It should be done with specific routine executed from RAM. | |||
* @retval HAL status | |||
*/ | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void) | |||
{ | |||
/* Enable Power ctrl clock */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Enable the flash sleep while System Run */ | |||
SET_BIT(PWR->CR, PWR_CR_FMSSR); | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Disable the flash sleep while System Run | |||
* @note This mode is only available for STM32F41xxx/STM32F446xx devices. | |||
* @note This mode couldn't be set while executing with the flash itself. | |||
* It should be done with specific routine executed from RAM. | |||
* @retval HAL status | |||
*/ | |||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) | |||
{ | |||
/* Enable Power ctrl clock */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Disable the flash sleep while System Run */ | |||
CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); | |||
return HAL_OK; | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ | |||
#endif /* HAL_FLASH_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,537 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_gpio.c | |||
* @author MCD Application Team | |||
* @brief GPIO HAL module driver. | |||
* This file provides firmware functions to manage the following | |||
* functionalities of the General Purpose Input/Output (GPIO) peripheral: | |||
* + Initialization and de-initialization functions | |||
* + IO operation functions | |||
* | |||
@verbatim | |||
============================================================================== | |||
##### GPIO Peripheral features ##### | |||
============================================================================== | |||
[..] | |||
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each | |||
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software | |||
in several modes: | |||
(+) Input mode | |||
(+) Analog mode | |||
(+) Output mode | |||
(+) Alternate function mode | |||
(+) External interrupt/event lines | |||
[..] | |||
During and just after reset, the alternate functions and external interrupt | |||
lines are not active and the I/O ports are configured in input floating mode. | |||
[..] | |||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be | |||
activated or not. | |||
[..] | |||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull | |||
type and the IO speed can be selected depending on the VDD value. | |||
[..] | |||
All ports have external interrupt/event capability. To use external interrupt | |||
lines, the port must be configured in input mode. All available GPIO pins are | |||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. | |||
[..] | |||
The external interrupt/event controller consists of up to 23 edge detectors | |||
(16 lines are connected to GPIO) for generating event/interrupt requests (each | |||
input line can be independently configured to select the type (interrupt or event) | |||
and the corresponding trigger event (rising or falling or both). Each line can | |||
also be masked independently. | |||
##### How to use this driver ##### | |||
============================================================================== | |||
[..] | |||
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). | |||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init(). | |||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure | |||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef | |||
structure. | |||
(++) In case of Output or alternate function mode selection: the speed is | |||
configured through "Speed" member from GPIO_InitTypeDef structure. | |||
(++) In alternate mode is selection, the alternate function connected to the IO | |||
is configured through "Alternate" member from GPIO_InitTypeDef structure. | |||
(++) Analog mode is required when a pin is to be used as ADC channel | |||
or DAC output. | |||
(++) In case of external interrupt/event selection the "Mode" member from | |||
GPIO_InitTypeDef structure select the type (interrupt or event) and | |||
the corresponding trigger event (rising or falling or both). | |||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority | |||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using | |||
HAL_NVIC_EnableIRQ(). | |||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). | |||
(#) To set/reset the level of a pin configured in output mode use | |||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). | |||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). | |||
(#) During and just after reset, the alternate functions are not | |||
active and the GPIO pins are configured in input floating mode (except JTAG | |||
pins). | |||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose | |||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has | |||
priority over the GPIO function. | |||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as | |||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off. | |||
The HSE has priority over the GPIO function. | |||
@endverbatim | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup GPIO GPIO | |||
* @brief GPIO HAL module driver | |||
* @{ | |||
*/ | |||
#ifdef HAL_GPIO_MODULE_ENABLED | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private define ------------------------------------------------------------*/ | |||
/** @addtogroup GPIO_Private_Constants GPIO Private Constants | |||
* @{ | |||
*/ | |||
#define GPIO_MODE 0x00000003U | |||
#define EXTI_MODE 0x10000000U | |||
#define GPIO_MODE_IT 0x00010000U | |||
#define GPIO_MODE_EVT 0x00020000U | |||
#define RISING_EDGE 0x00100000U | |||
#define FALLING_EDGE 0x00200000U | |||
#define GPIO_OUTPUT_TYPE 0x00000010U | |||
#define GPIO_NUMBER 16U | |||
/** | |||
* @} | |||
*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/* Exported functions --------------------------------------------------------*/ | |||
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions | |||
* @brief Initialization and Configuration functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Initialization and de-initialization functions ##### | |||
=============================================================================== | |||
[..] | |||
This section provides functions allowing to initialize and de-initialize the GPIOs | |||
to be ready for use. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. | |||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or | |||
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. | |||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains | |||
* the configuration information for the specified GPIO peripheral. | |||
* @retval None | |||
*/ | |||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) | |||
{ | |||
uint32_t position; | |||
uint32_t ioposition = 0x00U; | |||
uint32_t iocurrent = 0x00U; | |||
uint32_t temp = 0x00U; | |||
/* Check the parameters */ | |||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); | |||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); | |||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); | |||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); | |||
/* Configure the port pins */ | |||
for(position = 0U; position < GPIO_NUMBER; position++) | |||
{ | |||
/* Get the IO position */ | |||
ioposition = 0x01U << position; | |||
/* Get the current IO position */ | |||
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; | |||
if(iocurrent == ioposition) | |||
{ | |||
/*--------------------- GPIO Mode Configuration ------------------------*/ | |||
/* In case of Output or Alternate function mode selection */ | |||
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || | |||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) | |||
{ | |||
/* Check the Speed parameter */ | |||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); | |||
/* Configure the IO Speed */ | |||
temp = GPIOx->OSPEEDR; | |||
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); | |||
temp |= (GPIO_Init->Speed << (position * 2U)); | |||
GPIOx->OSPEEDR = temp; | |||
/* Configure the IO Output Type */ | |||
temp = GPIOx->OTYPER; | |||
temp &= ~(GPIO_OTYPER_OT_0 << position) ; | |||
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); | |||
GPIOx->OTYPER = temp; | |||
} | |||
/* Activate the Pull-up or Pull down resistor for the current IO */ | |||
temp = GPIOx->PUPDR; | |||
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); | |||
temp |= ((GPIO_Init->Pull) << (position * 2U)); | |||
GPIOx->PUPDR = temp; | |||
/* In case of Alternate function mode selection */ | |||
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) | |||
{ | |||
/* Check the Alternate function parameter */ | |||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); | |||
/* Configure Alternate function mapped with the current IO */ | |||
temp = GPIOx->AFR[position >> 3U]; | |||
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; | |||
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); | |||
GPIOx->AFR[position >> 3U] = temp; | |||
} | |||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */ | |||
temp = GPIOx->MODER; | |||
temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); | |||
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); | |||
GPIOx->MODER = temp; | |||
/*--------------------- EXTI Mode Configuration ------------------------*/ | |||
/* Configure the External Interrupt or event for the current IO */ | |||
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) | |||
{ | |||
/* Enable SYSCFG Clock */ | |||
__HAL_RCC_SYSCFG_CLK_ENABLE(); | |||
temp = SYSCFG->EXTICR[position >> 2U]; | |||
temp &= ~(0x0FU << (4U * (position & 0x03U))); | |||
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); | |||
SYSCFG->EXTICR[position >> 2U] = temp; | |||
/* Clear EXTI line configuration */ | |||
temp = EXTI->IMR; | |||
temp &= ~((uint32_t)iocurrent); | |||
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) | |||
{ | |||
temp |= iocurrent; | |||
} | |||
EXTI->IMR = temp; | |||
temp = EXTI->EMR; | |||
temp &= ~((uint32_t)iocurrent); | |||
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) | |||
{ | |||
temp |= iocurrent; | |||
} | |||
EXTI->EMR = temp; | |||
/* Clear Rising Falling edge configuration */ | |||
temp = EXTI->RTSR; | |||
temp &= ~((uint32_t)iocurrent); | |||
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) | |||
{ | |||
temp |= iocurrent; | |||
} | |||
EXTI->RTSR = temp; | |||
temp = EXTI->FTSR; | |||
temp &= ~((uint32_t)iocurrent); | |||
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) | |||
{ | |||
temp |= iocurrent; | |||
} | |||
EXTI->FTSR = temp; | |||
} | |||
} | |||
} | |||
} | |||
/** | |||
* @brief De-initializes the GPIOx peripheral registers to their default reset values. | |||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or | |||
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. | |||
* @param GPIO_Pin specifies the port bit to be written. | |||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). | |||
* @retval None | |||
*/ | |||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) | |||
{ | |||
uint32_t position; | |||
uint32_t ioposition = 0x00U; | |||
uint32_t iocurrent = 0x00U; | |||
uint32_t tmp = 0x00U; | |||
/* Check the parameters */ | |||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); | |||
/* Configure the port pins */ | |||
for(position = 0U; position < GPIO_NUMBER; position++) | |||
{ | |||
/* Get the IO position */ | |||
ioposition = 0x01U << position; | |||
/* Get the current IO position */ | |||
iocurrent = (GPIO_Pin) & ioposition; | |||
if(iocurrent == ioposition) | |||
{ | |||
/*------------------------- EXTI Mode Configuration --------------------*/ | |||
tmp = SYSCFG->EXTICR[position >> 2U]; | |||
tmp &= (0x0FU << (4U * (position & 0x03U))); | |||
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)))) | |||
{ | |||
/* Clear EXTI line configuration */ | |||
EXTI->IMR &= ~((uint32_t)iocurrent); | |||
EXTI->EMR &= ~((uint32_t)iocurrent); | |||
/* Clear Rising Falling edge configuration */ | |||
EXTI->RTSR &= ~((uint32_t)iocurrent); | |||
EXTI->FTSR &= ~((uint32_t)iocurrent); | |||
/* Configure the External Interrupt or event for the current IO */ | |||
tmp = 0x0FU << (4U * (position & 0x03U)); | |||
SYSCFG->EXTICR[position >> 2U] &= ~tmp; | |||
} | |||
/*------------------------- GPIO Mode Configuration --------------------*/ | |||
/* Configure IO Direction in Input Floating Mode */ | |||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U)); | |||
/* Configure the default Alternate Function in current IO */ | |||
GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; | |||
/* Deactivate the Pull-up and Pull-down resistor for the current IO */ | |||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); | |||
/* Configure the default value IO Output Type */ | |||
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; | |||
/* Configure the default value for IO Speed */ | |||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); | |||
} | |||
} | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions | |||
* @brief GPIO Read and Write | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### IO operation functions ##### | |||
=============================================================================== | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Reads the specified input port pin. | |||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or | |||
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. | |||
* @param GPIO_Pin specifies the port bit to read. | |||
* This parameter can be GPIO_PIN_x where x can be (0..15). | |||
* @retval The input port pin value. | |||
*/ | |||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) | |||
{ | |||
GPIO_PinState bitstatus; | |||
/* Check the parameters */ | |||
assert_param(IS_GPIO_PIN(GPIO_Pin)); | |||
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) | |||
{ | |||
bitstatus = GPIO_PIN_SET; | |||
} | |||
else | |||
{ | |||
bitstatus = GPIO_PIN_RESET; | |||
} | |||
return bitstatus; | |||
} | |||
/** | |||
* @brief Sets or clears the selected data port bit. | |||
* | |||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify | |||
* accesses. In this way, there is no risk of an IRQ occurring between | |||
* the read and the modify access. | |||
* | |||
* @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or | |||
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. | |||
* @param GPIO_Pin specifies the port bit to be written. | |||
* This parameter can be one of GPIO_PIN_x where x can be (0..15). | |||
* @param PinState specifies the value to be written to the selected bit. | |||
* This parameter can be one of the GPIO_PinState enum values: | |||
* @arg GPIO_PIN_RESET: to clear the port pin | |||
* @arg GPIO_PIN_SET: to set the port pin | |||
* @retval None | |||
*/ | |||
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_GPIO_PIN(GPIO_Pin)); | |||
assert_param(IS_GPIO_PIN_ACTION(PinState)); | |||
if(PinState != GPIO_PIN_RESET) | |||
{ | |||
GPIOx->BSRR = GPIO_Pin; | |||
} | |||
else | |||
{ | |||
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; | |||
} | |||
} | |||
/** | |||
* @brief Toggles the specified GPIO pins. | |||
* @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or | |||
* x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. | |||
* @param GPIO_Pin Specifies the pins to be toggled. | |||
* @retval None | |||
*/ | |||
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_GPIO_PIN(GPIO_Pin)); | |||
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) | |||
{ | |||
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; | |||
} | |||
else | |||
{ | |||
GPIOx->BSRR = GPIO_Pin; | |||
} | |||
} | |||
/** | |||
* @brief Locks GPIO Pins configuration registers. | |||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, | |||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. | |||
* @note The configuration of the locked GPIO pins can no longer be modified | |||
* until the next reset. | |||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family | |||
* @param GPIO_Pin specifies the port bit to be locked. | |||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15). | |||
* @retval None | |||
*/ | |||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) | |||
{ | |||
__IO uint32_t tmp = GPIO_LCKR_LCKK; | |||
/* Check the parameters */ | |||
assert_param(IS_GPIO_PIN(GPIO_Pin)); | |||
/* Apply lock key write sequence */ | |||
tmp |= GPIO_Pin; | |||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ | |||
GPIOx->LCKR = tmp; | |||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ | |||
GPIOx->LCKR = GPIO_Pin; | |||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ | |||
GPIOx->LCKR = tmp; | |||
/* Read LCKR register. This read is mandatory to complete key lock sequence */ | |||
tmp = GPIOx->LCKR; | |||
/* Read again in order to confirm lock is active */ | |||
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) | |||
{ | |||
return HAL_OK; | |||
} | |||
else | |||
{ | |||
return HAL_ERROR; | |||
} | |||
} | |||
/** | |||
* @brief This function handles EXTI interrupt request. | |||
* @param GPIO_Pin Specifies the pins connected EXTI line | |||
* @retval None | |||
*/ | |||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) | |||
{ | |||
/* EXTI line interrupt detected */ | |||
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) | |||
{ | |||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); | |||
HAL_GPIO_EXTI_Callback(GPIO_Pin); | |||
} | |||
} | |||
/** | |||
* @brief EXTI line detection callbacks. | |||
* @param GPIO_Pin Specifies the pins connected EXTI line | |||
* @retval None | |||
*/ | |||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) | |||
{ | |||
/* Prevent unused argument(s) compilation warning */ | |||
UNUSED(GPIO_Pin); | |||
/* NOTE: This function Should not be modified, when the callback is needed, | |||
the HAL_GPIO_EXTI_Callback could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_GPIO_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,559 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_pwr.c | |||
* @author MCD Application Team | |||
* @brief PWR HAL module driver. | |||
* This file provides firmware functions to manage the following | |||
* functionalities of the Power Controller (PWR) peripheral: | |||
* + Initialization and de-initialization functions | |||
* + Peripheral Control functions | |||
* | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup PWR PWR | |||
* @brief PWR HAL module driver | |||
* @{ | |||
*/ | |||
#ifdef HAL_PWR_MODULE_ENABLED | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private define ------------------------------------------------------------*/ | |||
/** @addtogroup PWR_Private_Constants | |||
* @{ | |||
*/ | |||
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask | |||
* @{ | |||
*/ | |||
#define PVD_MODE_IT 0x00010000U | |||
#define PVD_MODE_EVT 0x00020000U | |||
#define PVD_RISING_EDGE 0x00000001U | |||
#define PVD_FALLING_EDGE 0x00000002U | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup PWR_Exported_Functions PWR Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions | |||
* @brief Initialization and de-initialization functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Initialization and de-initialization functions ##### | |||
=============================================================================== | |||
[..] | |||
After reset, the backup domain (RTC registers, RTC backup data | |||
registers and backup SRAM) is protected against possible unwanted | |||
write accesses. | |||
To enable access to the RTC Domain and RTC registers, proceed as follows: | |||
(+) Enable the Power Controller (PWR) APB1 interface clock using the | |||
__HAL_RCC_PWR_CLK_ENABLE() macro. | |||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_DeInit(void) | |||
{ | |||
__HAL_RCC_PWR_FORCE_RESET(); | |||
__HAL_RCC_PWR_RELEASE_RESET(); | |||
} | |||
/** | |||
* @brief Enables access to the backup domain (RTC registers, RTC | |||
* backup data registers and backup SRAM). | |||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the | |||
* Backup Domain Access should be kept enabled. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnableBkUpAccess(void) | |||
{ | |||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Disables access to the backup domain (RTC registers, RTC | |||
* backup data registers and backup SRAM). | |||
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the | |||
* Backup Domain Access should be kept enabled. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_DisableBkUpAccess(void) | |||
{ | |||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions | |||
* @brief Low Power modes configuration functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Peripheral Control functions ##### | |||
=============================================================================== | |||
*** PVD configuration *** | |||
========================= | |||
[..] | |||
(+) The PVD is used to monitor the VDD power supply by comparing it to a | |||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). | |||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower | |||
than the PVD threshold. This event is internally connected to the EXTI | |||
line16 and can generate an interrupt if enabled. This is done through | |||
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro. | |||
(+) The PVD is stopped in Standby mode. | |||
*** Wake-up pin configuration *** | |||
================================ | |||
[..] | |||
(+) Wake-up pin is used to wake up the system from Standby mode. This pin is | |||
forced in input pull-down configuration and is active on rising edges. | |||
(+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. | |||
(++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 | |||
(++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 | |||
*** Low Power modes configuration *** | |||
===================================== | |||
[..] | |||
The devices feature 3 low-power modes: | |||
(+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. | |||
(+) Stop mode: all clocks are stopped, regulator running, regulator | |||
in low power mode | |||
(+) Standby mode: 1.2V domain powered off. | |||
*** Sleep mode *** | |||
================== | |||
[..] | |||
(+) Entry: | |||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) | |||
functions with | |||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction | |||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction | |||
-@@- The Regulator parameter is not used for the STM32F4 family | |||
and is kept as parameter just to maintain compatibility with the | |||
lower power families (STM32L). | |||
(+) Exit: | |||
Any peripheral interrupt acknowledged by the nested vectored interrupt | |||
controller (NVIC) can wake up the device from Sleep mode. | |||
*** Stop mode *** | |||
================= | |||
[..] | |||
In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, | |||
and the HSE RC oscillators are disabled. Internal SRAM and register contents | |||
are preserved. | |||
The voltage regulator can be configured either in normal or low-power mode. | |||
To minimize the consumption In Stop mode, FLASH can be powered off before | |||
entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. | |||
It can be switched on again by software after exiting the Stop mode using | |||
the HAL_PWREx_DisableFlashPowerDown() function. | |||
(+) Entry: | |||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) | |||
function with: | |||
(++) Main regulator ON. | |||
(++) Low Power regulator ON. | |||
(+) Exit: | |||
Any EXTI Line (Internal or External) configured in Interrupt/Event mode. | |||
*** Standby mode *** | |||
==================== | |||
[..] | |||
(+) | |||
The Standby mode allows to achieve the lowest power consumption. It is based | |||
on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. | |||
The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and | |||
the HSE oscillator are also switched off. SRAM and register contents are lost | |||
except for the RTC registers, RTC backup registers, backup SRAM and Standby | |||
circuitry. | |||
The voltage regulator is OFF. | |||
(++) Entry: | |||
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. | |||
(++) Exit: | |||
(+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, | |||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset. | |||
*** Auto-wake-up (AWU) from low-power mode *** | |||
============================================= | |||
[..] | |||
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC | |||
Wake-up event, a tamper event or a time-stamp event, without depending on | |||
an external interrupt (Auto-wake-up mode). | |||
(+) RTC auto-wake-up (AWU) from the Stop and Standby modes | |||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to | |||
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. | |||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it | |||
is necessary to configure the RTC to detect the tamper or time stamp event using the | |||
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. | |||
(++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to | |||
configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). | |||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration | |||
* information for the PVD. | |||
* @note Refer to the electrical characteristics of your device datasheet for | |||
* more details about the voltage threshold corresponding to each | |||
* detection level. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); | |||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); | |||
/* Set PLS[7:5] bits according to PVDLevel value */ | |||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); | |||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ | |||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT(); | |||
__HAL_PWR_PVD_EXTI_DISABLE_IT(); | |||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); | |||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); | |||
/* Configure interrupt mode */ | |||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) | |||
{ | |||
__HAL_PWR_PVD_EXTI_ENABLE_IT(); | |||
} | |||
/* Configure event mode */ | |||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) | |||
{ | |||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT(); | |||
} | |||
/* Configure the edge */ | |||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) | |||
{ | |||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); | |||
} | |||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) | |||
{ | |||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); | |||
} | |||
} | |||
/** | |||
* @brief Enables the Power Voltage Detector(PVD). | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnablePVD(void) | |||
{ | |||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Disables the Power Voltage Detector(PVD). | |||
* @retval None | |||
*/ | |||
void HAL_PWR_DisablePVD(void) | |||
{ | |||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; | |||
} | |||
/** | |||
* @brief Enables the Wake-up PINx functionality. | |||
* @param WakeUpPinx Specifies the Power Wake-Up pin to enable. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_WAKEUP_PIN1 | |||
* @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices | |||
* @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) | |||
{ | |||
/* Check the parameter */ | |||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); | |||
/* Enable the wake up pin */ | |||
SET_BIT(PWR->CSR, WakeUpPinx); | |||
} | |||
/** | |||
* @brief Disables the Wake-up PINx functionality. | |||
* @param WakeUpPinx Specifies the Power Wake-Up pin to disable. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_WAKEUP_PIN1 | |||
* @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices | |||
* @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices | |||
* @retval None | |||
*/ | |||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) | |||
{ | |||
/* Check the parameter */ | |||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); | |||
/* Disable the wake up pin */ | |||
CLEAR_BIT(PWR->CSR, WakeUpPinx); | |||
} | |||
/** | |||
* @brief Enters Sleep mode. | |||
* | |||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode. | |||
* | |||
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with | |||
* systick interrupt when used as time base for Timeout | |||
* | |||
* @param Regulator Specifies the regulator state in SLEEP mode. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON | |||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON | |||
* @note This parameter is not used for the STM32F4 family and is kept as parameter | |||
* just to maintain compatibility with the lower power families. | |||
* @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction | |||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_PWR_REGULATOR(Regulator)); | |||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); | |||
/* Clear SLEEPDEEP bit of Cortex System Control Register */ | |||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |||
/* Select SLEEP mode entry -------------------------------------------------*/ | |||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI) | |||
{ | |||
/* Request Wait For Interrupt */ | |||
__WFI(); | |||
} | |||
else | |||
{ | |||
/* Request Wait For Event */ | |||
__SEV(); | |||
__WFE(); | |||
__WFE(); | |||
} | |||
} | |||
/** | |||
* @brief Enters Stop mode. | |||
* @note In Stop mode, all I/O pins keep the same state as in Run mode. | |||
* @note When exiting Stop mode by issuing an interrupt or a wake-up event, | |||
* the HSI RC oscillator is selected as system clock. | |||
* @note When the voltage regulator operates in low power mode, an additional | |||
* startup delay is incurred when waking up from Stop mode. | |||
* By keeping the internal regulator ON during Stop mode, the consumption | |||
* is higher although the startup time is reduced. | |||
* @param Regulator Specifies the regulator state in Stop mode. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON | |||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON | |||
* @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction | |||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) | |||
{ | |||
/* Check the parameters */ | |||
assert_param(IS_PWR_REGULATOR(Regulator)); | |||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); | |||
/* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ | |||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); | |||
/* Set SLEEPDEEP bit of Cortex System Control Register */ | |||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |||
/* Select Stop mode entry --------------------------------------------------*/ | |||
if(STOPEntry == PWR_STOPENTRY_WFI) | |||
{ | |||
/* Request Wait For Interrupt */ | |||
__WFI(); | |||
} | |||
else | |||
{ | |||
/* Request Wait For Event */ | |||
__SEV(); | |||
__WFE(); | |||
__WFE(); | |||
} | |||
/* Reset SLEEPDEEP bit of Cortex System Control Register */ | |||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |||
} | |||
/** | |||
* @brief Enters Standby mode. | |||
* @note In Standby mode, all I/O pins are high impedance except for: | |||
* - Reset pad (still available) | |||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC | |||
* Alarm out, or RTC clock calibration out. | |||
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. | |||
* - WKUP pin 1 (PA0) if enabled. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnterSTANDBYMode(void) | |||
{ | |||
/* Select Standby mode */ | |||
SET_BIT(PWR->CR, PWR_CR_PDDS); | |||
/* Set SLEEPDEEP bit of Cortex System Control Register */ | |||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); | |||
/* This option is used to ensure that store operations are completed */ | |||
#if defined ( __CC_ARM) | |||
__force_stores(); | |||
#endif | |||
/* Request Wait For Interrupt */ | |||
__WFI(); | |||
} | |||
/** | |||
* @brief This function handles the PWR PVD interrupt request. | |||
* @note This API should be called under the PVD_IRQHandler(). | |||
* @retval None | |||
*/ | |||
void HAL_PWR_PVD_IRQHandler(void) | |||
{ | |||
/* Check PWR Exti flag */ | |||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) | |||
{ | |||
/* PWR PVD interrupt user callback */ | |||
HAL_PWR_PVDCallback(); | |||
/* Clear PWR Exti pending bit */ | |||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG(); | |||
} | |||
} | |||
/** | |||
* @brief PWR PVD interrupt callback | |||
* @retval None | |||
*/ | |||
__weak void HAL_PWR_PVDCallback(void) | |||
{ | |||
/* NOTE : This function Should not be modified, when the callback is needed, | |||
the HAL_PWR_PVDCallback could be implemented in the user file | |||
*/ | |||
} | |||
/** | |||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. | |||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor | |||
* re-enters SLEEP mode when an interruption handling is over. | |||
* Setting this bit is useful when the processor is expected to run only on | |||
* interruptions handling. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnableSleepOnExit(void) | |||
{ | |||
/* Set SLEEPONEXIT bit of Cortex System Control Register */ | |||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); | |||
} | |||
/** | |||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. | |||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor | |||
* re-enters SLEEP mode when an interruption handling is over. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_DisableSleepOnExit(void) | |||
{ | |||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */ | |||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); | |||
} | |||
/** | |||
* @brief Enables CORTEX M4 SEVONPEND bit. | |||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes | |||
* WFE to wake up when an interrupt moves from inactive to pended. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_EnableSEVOnPend(void) | |||
{ | |||
/* Set SEVONPEND bit of Cortex System Control Register */ | |||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); | |||
} | |||
/** | |||
* @brief Disables CORTEX M4 SEVONPEND bit. | |||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes | |||
* WFE to wake up when an interrupt moves from inactive to pended. | |||
* @retval None | |||
*/ | |||
void HAL_PWR_DisableSEVOnPend(void) | |||
{ | |||
/* Clear SEVONPEND bit of Cortex System Control Register */ | |||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); | |||
} | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_PWR_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
@@ -0,0 +1,604 @@ | |||
/** | |||
****************************************************************************** | |||
* @file stm32f4xx_hal_pwr_ex.c | |||
* @author MCD Application Team | |||
* @brief Extended PWR HAL module driver. | |||
* This file provides firmware functions to manage the following | |||
* functionalities of PWR extension peripheral: | |||
* + Peripheral Extended features functions | |||
* | |||
****************************************************************************** | |||
* @attention | |||
* | |||
* <h2><center>© Copyright (c) 2017 STMicroelectronics. | |||
* All rights reserved.</center></h2> | |||
* | |||
* This software component is licensed by ST under BSD 3-Clause license, | |||
* the "License"; You may not use this file except in compliance with the | |||
* License. You may obtain a copy of the License at: | |||
* opensource.org/licenses/BSD-3-Clause | |||
* | |||
****************************************************************************** | |||
*/ | |||
/* Includes ------------------------------------------------------------------*/ | |||
#include "stm32f4xx_hal.h" | |||
/** @addtogroup STM32F4xx_HAL_Driver | |||
* @{ | |||
*/ | |||
/** @defgroup PWREx PWREx | |||
* @brief PWR HAL module driver | |||
* @{ | |||
*/ | |||
#ifdef HAL_PWR_MODULE_ENABLED | |||
/* Private typedef -----------------------------------------------------------*/ | |||
/* Private define ------------------------------------------------------------*/ | |||
/** @addtogroup PWREx_Private_Constants | |||
* @{ | |||
*/ | |||
#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U | |||
#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U | |||
#define PWR_BKPREG_TIMEOUT_VALUE 1000U | |||
#define PWR_VOSRDY_TIMEOUT_VALUE 1000U | |||
/** | |||
* @} | |||
*/ | |||
/* Private macro -------------------------------------------------------------*/ | |||
/* Private variables ---------------------------------------------------------*/ | |||
/* Private function prototypes -----------------------------------------------*/ | |||
/* Private functions ---------------------------------------------------------*/ | |||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions | |||
* @{ | |||
*/ | |||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions | |||
* @brief Peripheral Extended features functions | |||
* | |||
@verbatim | |||
=============================================================================== | |||
##### Peripheral extended features functions ##### | |||
=============================================================================== | |||
*** Main and Backup Regulators configuration *** | |||
================================================ | |||
[..] | |||
(+) The backup domain includes 4 Kbytes of backup SRAM accessible only from | |||
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is | |||
retained even in Standby or VBAT mode when the low power backup regulator | |||
is enabled. It can be considered as an internal EEPROM when VBAT is | |||
always present. You can use the HAL_PWREx_EnableBkUpReg() function to | |||
enable the low power backup regulator. | |||
(+) When the backup domain is supplied by VDD (analog switch connected to VDD) | |||
the backup SRAM is powered from VDD which replaces the VBAT power supply to | |||
save battery life. | |||
(+) The backup SRAM is not mass erased by a tamper event. It is read | |||
protected to prevent confidential data, such as cryptographic private | |||
key, from being accessed. The backup SRAM can be erased only through | |||
the Flash interface when a protection level change from level 1 to | |||
level 0 is requested. | |||
-@- Refer to the description of Read protection (RDP) in the Flash | |||
programming manual. | |||
(+) The main internal regulator can be configured to have a tradeoff between | |||
performance and power consumption when the device does not operate at | |||
the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() | |||
macro which configure VOS bit in PWR_CR register | |||
Refer to the product datasheets for more details. | |||
*** FLASH Power Down configuration **** | |||
======================================= | |||
[..] | |||
(+) By setting the FPDS bit in the PWR_CR register by using the | |||
HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power | |||
down mode when the device enters Stop mode. When the Flash memory | |||
is in power down mode, an additional startup delay is incurred when | |||
waking up from Stop mode. | |||
(+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL | |||
is OFF and the HSI or HSE clock source is selected as system clock. | |||
The new value programmed is active only when the PLL is ON. | |||
When the PLL is OFF, the voltage scale 3 is automatically selected. | |||
Refer to the datasheets for more details. | |||
*** Over-Drive and Under-Drive configuration **** | |||
================================================= | |||
[..] | |||
(+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has | |||
2 operating modes available: | |||
(++) Normal mode: The CPU and core logic operate at maximum frequency at a given | |||
voltage scaling (scale 1, scale 2 or scale 3) | |||
(++) Over-drive mode: This mode allows the CPU and the core logic to operate at a | |||
higher frequency than the normal mode for a given voltage scaling (scale 1, | |||
scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and | |||
disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow | |||
the sequence described in Reference manual. | |||
(+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator | |||
supplies a low power voltage to the 1.2V domain, thus preserving the content of registers | |||
and internal SRAM. 2 operating modes are available: | |||
(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only | |||
available when the main regulator or the low power regulator is used in Scale 3 or | |||
low voltage mode. | |||
(++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only | |||
available when the main regulator or the low power regulator is in low voltage mode. | |||
@endverbatim | |||
* @{ | |||
*/ | |||
/** | |||
* @brief Enables the Backup Regulator. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) | |||
{ | |||
uint32_t tickstart = 0U; | |||
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
/* Wait till Backup regulator ready flag is set */ | |||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Disables the Backup Regulator. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) | |||
{ | |||
uint32_t tickstart = 0U; | |||
*(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
/* Wait till Backup regulator ready flag is set */ | |||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Enables the Flash Power Down in Stop mode. | |||
* @retval None | |||
*/ | |||
void HAL_PWREx_EnableFlashPowerDown(void) | |||
{ | |||
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Disables the Flash Power Down in Stop mode. | |||
* @retval None | |||
*/ | |||
void HAL_PWREx_DisableFlashPowerDown(void) | |||
{ | |||
*(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; | |||
} | |||
/** | |||
* @brief Return Voltage Scaling Range. | |||
* @retval The configured scale for the regulator voltage(VOS bit field). | |||
* The returned value can be one of the following: | |||
* - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode | |||
* - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode | |||
* - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode | |||
*/ | |||
uint32_t HAL_PWREx_GetVoltageRange(void) | |||
{ | |||
return (PWR->CR & PWR_CR_VOS); | |||
} | |||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |||
/** | |||
* @brief Configures the main internal regulator output voltage. | |||
* @param VoltageScaling specifies the regulator output voltage to achieve | |||
* a tradeoff between performance and power consumption. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, | |||
* the maximum value of fHCLK = 168 MHz. | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, | |||
* the maximum value of fHCLK = 144 MHz. | |||
* @note When moving from Range 1 to Range 2, the system frequency must be decreased to | |||
* a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. | |||
* When moving from Range 2 to Range 1, the system frequency can be increased to | |||
* a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) | |||
{ | |||
uint32_t tickstart = 0U; | |||
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); | |||
/* Enable PWR RCC Clock Peripheral */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Set Range */ | |||
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); | |||
/* Get Start Tick*/ | |||
tickstart = HAL_GetTick(); | |||
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
return HAL_OK; | |||
} | |||
#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ | |||
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ | |||
defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ | |||
defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ | |||
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) | |||
/** | |||
* @brief Configures the main internal regulator output voltage. | |||
* @param VoltageScaling specifies the regulator output voltage to achieve | |||
* a tradeoff between performance and power consumption. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, | |||
* the maximum value of fHCLK is 168 MHz. It can be extended to | |||
* 180 MHz by activating the over-drive mode. | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, | |||
* the maximum value of fHCLK is 144 MHz. It can be extended to, | |||
* 168 MHz by activating the over-drive mode. | |||
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, | |||
* the maximum value of fHCLK is 120 MHz. | |||
* @note To update the system clock frequency(SYSCLK): | |||
* - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). | |||
* - Call the HAL_RCC_OscConfig() to configure the PLL. | |||
* - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. | |||
* - Set the new system clock frequency using the HAL_RCC_ClockConfig(). | |||
* @note The scale can be modified only when the HSI or HSE clock source is selected | |||
* as system clock source, otherwise the API returns HAL_ERROR. | |||
* @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits | |||
* value in the PWR_CR1 register are not taken in account. | |||
* @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. | |||
* @note The new voltage scale is active only when the PLL is ON. | |||
* @retval HAL Status | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) | |||
{ | |||
uint32_t tickstart = 0U; | |||
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); | |||
/* Enable PWR RCC Clock Peripheral */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Check if the PLL is used as system clock or not */ | |||
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) | |||
{ | |||
/* Disable the main PLL */ | |||
__HAL_RCC_PLL_DISABLE(); | |||
/* Get Start Tick */ | |||
tickstart = HAL_GetTick(); | |||
/* Wait till PLL is disabled */ | |||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
/* Set Range */ | |||
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); | |||
/* Enable the main PLL */ | |||
__HAL_RCC_PLL_ENABLE(); | |||
/* Get Start Tick */ | |||
tickstart = HAL_GetTick(); | |||
/* Wait till PLL is ready */ | |||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
/* Get Start Tick */ | |||
tickstart = HAL_GetTick(); | |||
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
} | |||
else | |||
{ | |||
return HAL_ERROR; | |||
} | |||
return HAL_OK; | |||
} | |||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |||
#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ | |||
defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ | |||
defined(STM32F413xx) || defined(STM32F423xx) | |||
/** | |||
* @brief Enables Main Regulator low voltage mode. | |||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ | |||
* STM32F413xx/STM32F423xx devices. | |||
* @retval None | |||
*/ | |||
void HAL_PWREx_EnableMainRegulatorLowVoltage(void) | |||
{ | |||
*(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Disables Main Regulator low voltage mode. | |||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ | |||
* STM32F413xx/STM32F423xxdevices. | |||
* @retval None | |||
*/ | |||
void HAL_PWREx_DisableMainRegulatorLowVoltage(void) | |||
{ | |||
*(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; | |||
} | |||
/** | |||
* @brief Enables Low Power Regulator low voltage mode. | |||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ | |||
* STM32F413xx/STM32F423xx devices. | |||
* @retval None | |||
*/ | |||
void HAL_PWREx_EnableLowRegulatorLowVoltage(void) | |||
{ | |||
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; | |||
} | |||
/** | |||
* @brief Disables Low Power Regulator low voltage mode. | |||
* @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ | |||
* STM32F413xx/STM32F423xx devices. | |||
* @retval None | |||
*/ | |||
void HAL_PWREx_DisableLowRegulatorLowVoltage(void) | |||
{ | |||
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; | |||
} | |||
#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || | |||
STM32F413xx || STM32F423xx */ | |||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |||
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |||
/** | |||
* @brief Activates the Over-Drive mode. | |||
* @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. | |||
* This mode allows the CPU and the core logic to operate at a higher frequency | |||
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). | |||
* @note It is recommended to enter or exit Over-drive mode when the application is not running | |||
* critical tasks and when the system clock source is either HSI or HSE. | |||
* During the Over-drive switch activation, no peripheral clocks should be enabled. | |||
* The peripheral clocks must be enabled once the Over-drive mode is activated. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) | |||
{ | |||
uint32_t tickstart = 0U; | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */ | |||
__HAL_PWR_OVERDRIVE_ENABLE(); | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) | |||
{ | |||
if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
/* Enable the Over-drive switch */ | |||
__HAL_PWR_OVERDRIVESWITCHING_ENABLE(); | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) | |||
{ | |||
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Deactivates the Over-Drive mode. | |||
* @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. | |||
* This mode allows the CPU and the core logic to operate at a higher frequency | |||
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). | |||
* @note It is recommended to enter or exit Over-drive mode when the application is not running | |||
* critical tasks and when the system clock source is either HSI or HSE. | |||
* During the Over-drive switch activation, no peripheral clocks should be enabled. | |||
* The peripheral clocks must be enabled once the Over-drive mode is activated. | |||
* @retval HAL status | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) | |||
{ | |||
uint32_t tickstart = 0U; | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Disable the Over-drive switch */ | |||
__HAL_PWR_OVERDRIVESWITCHING_DISABLE(); | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) | |||
{ | |||
if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
/* Disable the Over-drive */ | |||
__HAL_PWR_OVERDRIVE_DISABLE(); | |||
/* Get tick */ | |||
tickstart = HAL_GetTick(); | |||
while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) | |||
{ | |||
if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) | |||
{ | |||
return HAL_TIMEOUT; | |||
} | |||
} | |||
return HAL_OK; | |||
} | |||
/** | |||
* @brief Enters in Under-Drive STOP mode. | |||
* | |||
* @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. | |||
* | |||
* @note This mode can be selected only when the Under-Drive is already active | |||
* | |||
* @note This mode is enabled only with STOP low power mode. | |||
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This | |||
* mode is only available when the main regulator or the low power regulator | |||
* is in low voltage mode | |||
* | |||
* @note If the Under-drive mode was enabled, it is automatically disabled after | |||
* exiting Stop mode. | |||
* When the voltage regulator operates in Under-drive mode, an additional | |||
* startup delay is induced when waking up from Stop mode. | |||
* | |||
* @note In Stop mode, all I/O pins keep the same state as in Run mode. | |||
* | |||
* @note When exiting Stop mode by issuing an interrupt or a wake-up event, | |||
* the HSI RC oscillator is selected as system clock. | |||
* | |||
* @note When the voltage regulator operates in low power mode, an additional | |||
* startup delay is incurred when waking up from Stop mode. | |||
* By keeping the internal regulator ON during Stop mode, the consumption | |||
* is higher although the startup time is reduced. | |||
* | |||
* @param Regulator specifies the regulator state in STOP mode. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode | |||
* and Flash memory in power-down when the device is in Stop under-drive mode | |||
* @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode | |||
* and Flash memory in power-down when the device is in Stop under-drive mode | |||
* @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. | |||
* This parameter can be one of the following values: | |||
* @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction | |||
* @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction | |||
* @retval None | |||
*/ | |||
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) | |||
{ | |||
uint32_t tmpreg1 = 0U; | |||
/* Check the parameters */ | |||
assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); | |||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); | |||
/* Enable Power ctrl clock */ | |||
__HAL_RCC_PWR_CLK_ENABLE(); | |||
/* Enable the Under-drive Mode ---------------------------------------------*/ | |||
/* Clear Under-drive flag */ | |||
__HAL_PWR_CLEAR_ODRUDR_FLAG(); | |||
/* Enable the Under-drive */ | |||
__HAL_PWR_UNDERDRIVE_ENABLE(); | |||
/* Select the regulator state in STOP mode ---------------------------------*/ | |||
tmpreg1 = PWR->CR; | |||
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ | |||
tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); | |||
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ | |||
tmpreg1 |= Regulator; | |||
/* Store the new value */ | |||
PWR->CR = tmpreg1; | |||
/* Set SLEEPDEEP bit of Cortex System Control Register */ | |||
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; | |||
/* Select STOP mode entry --------------------------------------------------*/ | |||
if(STOPEntry == PWR_SLEEPENTRY_WFI) | |||
{ | |||
/* Request Wait For Interrupt */ | |||
__WFI(); | |||
} | |||
else | |||
{ | |||
/* Request Wait For Event */ | |||
__WFE(); | |||
} | |||
/* Reset SLEEPDEEP bit of Cortex System Control Register */ | |||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); | |||
return HAL_OK; | |||
} | |||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
#endif /* HAL_PWR_MODULE_ENABLED */ | |||
/** | |||
* @} | |||
*/ | |||
/** | |||
* @} | |||
*/ | |||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |