init branch test
This commit is contained in:
@@ -0,0 +1,569 @@
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/**
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******************************************************************************
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* @file stm32l1xx_hal.c
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* @author MCD Application Team
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* @brief HAL module driver.
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* This is the common part of the HAL initialization
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*
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@verbatim
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==============================================================================
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##### How to use this driver #####
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==============================================================================
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[..]
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The common HAL driver contains a set of generic and common APIs that can be
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used by the PPP peripheral drivers and the user to start using the HAL.
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[..]
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The HAL contains two APIs categories:
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(+) Common HAL APIs
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(+) Services HAL APIs
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32l1xx_hal.h"
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/** @addtogroup STM32L1xx_HAL_Driver
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* @{
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*/
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/** @defgroup HAL HAL
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* @brief HAL module driver.
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* @{
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*/
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#ifdef HAL_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup HAL_Private_Defines HAL Private Defines
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* @{
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*/
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/**
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* @brief STM32L1xx HAL Driver version number V1.4.3
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*/
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#define __STM32L1xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
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#define __STM32L1xx_HAL_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
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#define __STM32L1xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
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#define __STM32L1xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32L1xx_HAL_VERSION ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
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|(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
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|(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\
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|(__STM32L1xx_HAL_VERSION_RC))
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#define IDCODE_DEVID_MASK (0x00000FFFU)
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/* Exported variables --------------------------------------------------------*/
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/** @addtogroup HAL_Exported_Variables
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* @{
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*/
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__IO uint32_t uwTick;
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uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
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uint32_t uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup HAL_Exported_Functions HAL Exported Functions
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* @{
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*/
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/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Initialize the Flash interface, the NVIC allocation and initial clock
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configuration. It initializes the source of time base also when timeout
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is needed and the backup domain when enabled.
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(+) De-initialize common part of the HAL.
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(+) Configure the time base source to have 1ms time base with a dedicated
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Tick interrupt priority.
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(++) SysTick timer is used by default as source of time base, but user
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can eventually implement his proper time base source (a general purpose
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timer for example or other time source), keeping in mind that Time base
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duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
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handled in milliseconds basis.
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(++) Time base configuration function (HAL_InitTick ()) is called automatically
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at the beginning of the program after reset by HAL_Init() or at any time
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when clock is configured, by HAL_RCC_ClockConfig().
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(++) Source of time base is configured to generate interrupts at regular
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time intervals. Care must be taken if HAL_Delay() is called from a
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peripheral ISR process, the Tick interrupt line must have higher priority
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(numerically lower) than the peripheral interrupt. Otherwise the caller
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ISR process will be blocked.
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(++) functions affecting time base configurations are declared as __weak
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to make override possible in case of other implementations in user file.
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@endverbatim
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* @{
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*/
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/**
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* @brief This function configures the Flash prefetch,
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* configures time base source, NVIC and Low level hardware
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* @note This function is called at the beginning of program after reset and before
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* the clock configuration
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* @note The time base configuration is based on MSI clock when exiting from Reset.
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* Once done, time base tick start incrementing.
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* In the default implementation,Systick is used as source of time base.
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* the tick variable is incremented each 1ms in its ISR.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_Init(void)
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{
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HAL_StatusTypeDef status = HAL_OK;
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/* Configure Flash prefetch */
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#if (PREFETCH_ENABLE != 0)
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__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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#endif /* PREFETCH_ENABLE */
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/* Set Interrupt Group Priority */
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HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
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/* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
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if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
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{
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status = HAL_ERROR;
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}
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else
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{
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/* Init the low level hardware */
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HAL_MspInit();
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}
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/* Return function status */
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return status;
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}
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/**
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* @brief This function de-initializes common part of the HAL and stops the source
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* of time base.
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* @note This function is optional.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_DeInit(void)
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{
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/* Reset of all peripherals */
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__HAL_RCC_APB1_FORCE_RESET();
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__HAL_RCC_APB1_RELEASE_RESET();
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__HAL_RCC_APB2_FORCE_RESET();
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__HAL_RCC_APB2_RELEASE_RESET();
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__HAL_RCC_AHB_FORCE_RESET();
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__HAL_RCC_AHB_RELEASE_RESET();
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/* De-Init the low level hardware */
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HAL_MspDeInit();
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/* Return function status */
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return HAL_OK;
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}
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/**
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* @brief Initialize the MSP.
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* @retval None
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*/
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__weak void HAL_MspInit(void)
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{
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/* NOTE : This function should not be modified, when the callback is needed,
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the HAL_MspInit could be implemented in the user file
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*/
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}
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/**
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* @brief DeInitialize the MSP.
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* @retval None
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*/
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__weak void HAL_MspDeInit(void)
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{
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/* NOTE : This function should not be modified, when the callback is needed,
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the HAL_MspDeInit could be implemented in the user file
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*/
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}
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/**
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* @brief This function configures the source of the time base:
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* The time source is configured to have 1ms time base with a dedicated
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* Tick interrupt priority.
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* @note This function is called automatically at the beginning of program after
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* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
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* @note In the default implementation, SysTick timer is the source of time base.
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* It is used to generate interrupts at regular time intervals.
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* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
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* The SysTick interrupt must have higher priority (numerically lower)
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* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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* The function is declared as __weak to be overwritten in case of other
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* implementation in user file.
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* @param TickPriority Tick interrupt priority.
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* @retval HAL status
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*/
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__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
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{
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HAL_StatusTypeDef status = HAL_OK;
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if (uwTickFreq != 0U)
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{
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/*Configure the SysTick to have interrupt in 1ms time basis*/
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if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
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{
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/* Configure the SysTick IRQ priority */
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if (TickPriority < (1UL << __NVIC_PRIO_BITS))
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{
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HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
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uwTickPrio = TickPriority;
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}
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else
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{
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status = HAL_ERROR;
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}
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}
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else
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{
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status = HAL_ERROR;
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}
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}
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else
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{
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status = HAL_ERROR;
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}
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/* Return function status */
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return status;
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}
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/**
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* @}
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*/
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/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
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* @brief HAL Control functions
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*
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@verbatim
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===============================================================================
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##### HAL Control functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Provide a tick value in millisecond
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(+) Provide a blocking delay in millisecond
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(+) Suspend the time base source interrupt
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(+) Resume the time base source interrupt
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||||
(+) Get the HAL API driver version
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(+) Get the device identifier
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(+) Get the device revision identifier
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||||
(+) Get the unique device identifier
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||||
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||||
@endverbatim
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||||
* @{
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||||
*/
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/**
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* @brief This function is called to increment a global variable "uwTick"
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* used as application time base.
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||||
* @note In the default implementation, this variable is incremented each 1ms
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||||
* in SysTick ISR.
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||||
* @note This function is declared as __weak to be overwritten in case of other
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||||
* implementations in user file.
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* @retval None
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||||
*/
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__weak void HAL_IncTick(void)
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{
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uwTick += uwTickFreq;
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}
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/**
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* @brief Provide a tick value in millisecond.
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||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
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* @retval tick value
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*/
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__weak uint32_t HAL_GetTick(void)
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{
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return uwTick;
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}
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/**
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* @brief This function returns a tick priority.
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* @retval tick priority
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||||
*/
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uint32_t HAL_GetTickPrio(void)
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||||
{
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return uwTickPrio;
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}
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/**
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||||
* @brief Set new tick Freq.
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||||
* @param Freq tick frequency
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||||
* @retval HAL status
|
||||
*/
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||||
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq)
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||||
{
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||||
HAL_StatusTypeDef status = HAL_OK;
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||||
uint32_t prevTickFreq;
|
||||
|
||||
assert_param(IS_TICKFREQ(Freq));
|
||||
|
||||
if (uwTickFreq != Freq)
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{
|
||||
/* Back up uwTickFreq frequency */
|
||||
prevTickFreq = uwTickFreq;
|
||||
|
||||
/* Update uwTickFreq global variable used by HAL_InitTick() */
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uwTickFreq = Freq;
|
||||
|
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/* Apply the new tick Freq */
|
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status = HAL_InitTick(uwTickPrio);
|
||||
|
||||
if (status != HAL_OK)
|
||||
{
|
||||
/* Restore previous tick frequency */
|
||||
uwTickFreq = prevTickFreq;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
*/
|
||||
uint32_t HAL_GetTickFreq(void)
|
||||
{
|
||||
return uwTickFreq;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function provides minimum delay (in milliseconds) based
|
||||
* on variable incremented.
|
||||
* @note In the default implementation , SysTick timer is the source of time base.
|
||||
* It is used to generate interrupts at regular time intervals where uwTick
|
||||
* is incremented.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @param Delay specifies the delay time length, in milliseconds.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_Delay(uint32_t Delay)
|
||||
{
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
uint32_t wait = Delay;
|
||||
|
||||
/* Add a period to guaranty minimum wait */
|
||||
if (wait < HAL_MAX_DELAY)
|
||||
{
|
||||
wait += (uint32_t)(uwTickFreq);
|
||||
}
|
||||
|
||||
while((HAL_GetTick() - tickstart) < wait)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Suspend the Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
|
||||
* is called, the SysTick interrupt will be disabled and so Tick increment
|
||||
* is suspended.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SuspendTick(void)
|
||||
{
|
||||
/* Disable SysTick Interrupt */
|
||||
CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Resume the Tick increment.
|
||||
* @note In the default implementation , SysTick timer is the source of time base. It is
|
||||
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
|
||||
* is called, the SysTick interrupt will be enabled and so Tick increment
|
||||
* is resumed.
|
||||
* @note This function is declared as __weak to be overwritten in case of other
|
||||
* implementations in user file.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_ResumeTick(void)
|
||||
{
|
||||
/* Enable SysTick Interrupt */
|
||||
SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the HAL revision
|
||||
* @retval version: 0xXYZR (8bits for each decimal, R for RC)
|
||||
*/
|
||||
uint32_t HAL_GetHalVersion(void)
|
||||
{
|
||||
return __STM32L1xx_HAL_VERSION;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the device revision identifier.
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t HAL_GetREVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) >> 16U);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the device identifier.
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t HAL_GetDEVID(void)
|
||||
{
|
||||
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the first word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier 31:0 bits
|
||||
*/
|
||||
uint32_t HAL_GetUIDw0(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)UID_BASE)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the second word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier 63:32 bits
|
||||
*/
|
||||
uint32_t HAL_GetUIDw1(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 0x4U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the third word of the unique device identifier (UID based on 96 bits)
|
||||
* @retval Device identifier 95:64 bits
|
||||
*/
|
||||
uint32_t HAL_GetUIDw2(void)
|
||||
{
|
||||
return(READ_REG(*((uint32_t *)(UID_BASE + 0x14U))));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_Exported_Functions_Group3 DBGMCU Peripheral Control functions
|
||||
* @brief DBGMCU Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DBGMCU Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Enable/Disable Debug module during SLEEP mode
|
||||
(+) Enable/Disable Debug module during STOP mode
|
||||
(+) Enable/Disable Debug module during STANDBY mode
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGSleepMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during SLEEP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGSleepMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStopMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STOP mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStopMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_EnableDBGStandbyMode(void)
|
||||
{
|
||||
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the Debug Module during STANDBY mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DBGMCU_DisableDBGStandbyMode(void)
|
||||
{
|
||||
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,513 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_cortex.c
|
||||
* @author MCD Application Team
|
||||
* @brief CORTEX HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the CORTEX:
|
||||
* + Initialization and de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
|
||||
[..]
|
||||
*** How to configure Interrupts using Cortex HAL driver ***
|
||||
===========================================================
|
||||
[..]
|
||||
This section provide functions allowing to configure the NVIC interrupts (IRQ).
|
||||
The Cortex-M3 exceptions are managed by CMSIS functions.
|
||||
|
||||
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
|
||||
|
||||
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
|
||||
|
||||
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
|
||||
|
||||
|
||||
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
|
||||
The pending IRQ priority will be managed only by the sub priority.
|
||||
|
||||
-@- IRQ priority order (sorted by highest to lowest priority):
|
||||
(+@) Lowest pre-emption priority
|
||||
(+@) Lowest sub priority
|
||||
(+@) Lowest hardware priority (IRQ number)
|
||||
|
||||
[..]
|
||||
*** How to configure Systick using Cortex HAL driver ***
|
||||
========================================================
|
||||
[..]
|
||||
Setup SysTick Timer for 1 msec interrupts.
|
||||
|
||||
(+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
|
||||
is a CMSIS function that:
|
||||
(++) Configures the SysTick Reload register with value passed as function parameter.
|
||||
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
|
||||
(++) Resets the SysTick Counter register.
|
||||
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
|
||||
(++) Enables the SysTick Interrupt.
|
||||
(++) Starts the SysTick Counter.
|
||||
|
||||
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
|
||||
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
|
||||
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
|
||||
inside the stm32l1xx_hal_cortex.h file.
|
||||
|
||||
(+) You can change the SysTick IRQ priority by calling the
|
||||
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
|
||||
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
|
||||
|
||||
(+) To adjust the SysTick time base, use the following formula:
|
||||
|
||||
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
|
||||
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
|
||||
(++) Reload Value should not exceed 0xFFFFFF
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*
|
||||
Additional Tables: CORTEX_NVIC_Priority_Table
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
|
||||
==========================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
==========================================================================================================================
|
||||
NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
--------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
==========================================================================================================================
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX CORTEX
|
||||
* @brief CORTEX HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_CORTEX_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provide the Cortex HAL driver functions allowing to configure Interrupts
|
||||
Systick functionalities
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Sets the priority grouping field (pre-emption priority and subpriority)
|
||||
* using the required unlock sequence.
|
||||
* @param PriorityGroup The priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
||||
* The pending IRQ priority will be managed only by the subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
||||
NVIC_SetPriorityGrouping(PriorityGroup);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
|
||||
* @param PreemptPriority The pre-emption priority for the IRQn channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority
|
||||
* @param SubPriority the subpriority level for the IRQ channel.
|
||||
* This parameter can be a value between 0 and 15
|
||||
* A lower priority value indicates a higher priority.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t prioritygroup = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
|
||||
prioritygroup = NVIC_GetPriorityGrouping();
|
||||
|
||||
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Enable interrupt */
|
||||
NVIC_EnableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
||||
|
||||
/* Disable interrupt */
|
||||
NVIC_DisableIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initiates a system reset request to reset the MCU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SystemReset(void)
|
||||
{
|
||||
/* System Reset */
|
||||
NVIC_SystemReset();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
* Counter is in free running mode to generate periodic interrupts.
|
||||
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
|
||||
* @retval status: - 0 Function succeeded.
|
||||
* - 1 Function failed.
|
||||
*/
|
||||
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
||||
{
|
||||
return SysTick_Config(TicksNumb);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Cortex control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the CORTEX
|
||||
(NVIC, SYSTICK, MPU) functionalities.
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/**
|
||||
* @brief Enable the MPU.
|
||||
* @param MPU_Control Specifies the control mode of the MPU during hard fault,
|
||||
* NMI, FAULTMASK and privileged accessto the default memory
|
||||
* This parameter can be one of the following values:
|
||||
* @arg MPU_HFNMI_PRIVDEF_NONE
|
||||
* @arg MPU_HARDFAULT_NMI
|
||||
* @arg MPU_PRIVILEGED_DEFAULT
|
||||
* @arg MPU_HFNMI_PRIVDEF
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
/* Enable the MPU */
|
||||
MPU->CTRL = (MPU_Control | MPU_CTRL_ENABLE_Msk);
|
||||
|
||||
/* Ensure MPU setting take effects */
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the MPU.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_Disable(void)
|
||||
{
|
||||
/* Make sure outstanding transfers are done */
|
||||
__DMB();
|
||||
|
||||
/* Disable the MPU and clear the control register*/
|
||||
MPU->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != RESET)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00;
|
||||
MPU->RASR = 0x00;
|
||||
}
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
/**
|
||||
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
|
||||
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void)
|
||||
{
|
||||
/* Get the PRIGROUP[10:8] field value */
|
||||
return NVIC_GetPriorityGrouping();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the priority of an interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
|
||||
* @param PriorityGroup the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
* @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
|
||||
* @param pSubPriority Pointer on the Subpriority value (starting from 0).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
||||
/* Get priority for Cortex-M system or device specific interrupts */
|
||||
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets Pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Set interrupt pending */
|
||||
NVIC_SetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
|
||||
* and returns the pending bit for the specified interrupt).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if pending else 0 */
|
||||
return NVIC_GetPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the pending bit of an external interrupt.
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
/* Clear pending interrupt */
|
||||
NVIC_ClearPendingIRQ(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
|
||||
* @param IRQn External interrupt number
|
||||
* This parameter can be an enumerator of IRQn_Type enumeration
|
||||
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
|
||||
* @retval status: - 0 Interrupt status is not pending.
|
||||
* - 1 Interrupt status is pending.
|
||||
*/
|
||||
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
/* Return 1 if active else 0 */
|
||||
return NVIC_GetActive(IRQn);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param CLKSource specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
|
||||
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles SYSTICK interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_SYSTICK_IRQHandler(void)
|
||||
{
|
||||
HAL_SYSTICK_Callback();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief SYSTICK callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_SYSTICK_Callback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_SYSTICK_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_CORTEX_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,908 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_dma.c
|
||||
* @author MCD Application Team
|
||||
* @brief DMA HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access (DMA) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
* + Peripheral State and errors functions
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable and configure the peripheral to be connected to the DMA Channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary). Please refer to the Reference manual for connection between peripherals
|
||||
and DMA requests.
|
||||
|
||||
(#) For a given Channel, program the required configuration through the following parameters:
|
||||
Channel request, Transfer Direction, Source and Destination data formats,
|
||||
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
|
||||
using HAL_DMA_Init() function.
|
||||
|
||||
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
|
||||
detection.
|
||||
|
||||
(#) Use HAL_DMA_Abort() function to abort the current transfer
|
||||
|
||||
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
|
||||
*** Polling mode IO operation ***
|
||||
=================================
|
||||
[..]
|
||||
(+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
|
||||
address and destination address and the Length of data to be transferred
|
||||
(+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
|
||||
case a fixed Timeout can be configured by User depending from his application.
|
||||
|
||||
*** Interrupt mode IO operation ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
|
||||
(+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
|
||||
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
|
||||
Source address and destination address and the Length of data to be transferred.
|
||||
In this case the DMA interrupt is configured
|
||||
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
|
||||
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
|
||||
add his own function to register callbacks with HAL_DMA_RegisterCallback().
|
||||
|
||||
*** DMA HAL driver macros list ***
|
||||
=============================================
|
||||
[..]
|
||||
Below the list of macros in DMA HAL driver.
|
||||
|
||||
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
|
||||
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
|
||||
(+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
|
||||
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
|
||||
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
|
||||
|
||||
[..]
|
||||
(@) You can refer to the DMA HAL driver header file for more useful macros
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA DMA
|
||||
* @brief DMA HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_DMA_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup DMA_Private_Functions DMA Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions DMA Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to initialize the DMA Channel source
|
||||
and destination addresses, incrementation and data sizes, transfer direction,
|
||||
circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
|
||||
[..]
|
||||
The HAL_DMA_Init() function follows the DMA configuration procedures as described in
|
||||
reference manual.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initialize the DMA according to the specified
|
||||
* parameters in the DMA_InitTypeDef and initialize the associated handle.
|
||||
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if(hdma == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
|
||||
assert_param(IS_DMA_MODE(hdma->Init.Mode));
|
||||
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
|
||||
|
||||
#if defined (DMA2)
|
||||
/* Compute the channel index */
|
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
||||
{
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA2 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA2;
|
||||
}
|
||||
#else
|
||||
/* calculation of the channel index */
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
#endif
|
||||
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
|
||||
/* Get the CR register value */
|
||||
tmp = hdma->Instance->CCR;
|
||||
|
||||
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
|
||||
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
|
||||
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
|
||||
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
|
||||
|
||||
/* Prepare the DMA Channel configuration */
|
||||
tmp |= hdma->Init.Direction |
|
||||
hdma->Init.PeriphInc | hdma->Init.MemInc |
|
||||
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
|
||||
hdma->Init.Mode | hdma->Init.Priority;
|
||||
|
||||
/* Write to DMA Channel CR register */
|
||||
hdma->Instance->CCR = tmp;
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state*/
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Allocate lock resource and initialize it */
|
||||
hdma->Lock = HAL_UNLOCKED;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief DeInitialize the DMA peripheral.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
|
||||
/* Check the DMA handle allocation */
|
||||
if (NULL == hdma )
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
|
||||
|
||||
/* Disable the selected DMA Channelx */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
#if defined (DMA2)
|
||||
/* Compute the channel index */
|
||||
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
|
||||
{
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMA2 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA2;
|
||||
}
|
||||
#else
|
||||
/* calculation of the channel index */
|
||||
/* DMA1 */
|
||||
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
|
||||
hdma->DmaBaseAddress = DMA1;
|
||||
#endif
|
||||
|
||||
/* Reset DMA Channel CR register */
|
||||
hdma->Instance->CCR = 0U;
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Clean callbacks */
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
|
||||
/* Initialise the error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Initialize the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_RESET;
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
|
||||
* @brief Input and Output operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
[..] This section provides functions allowing to:
|
||||
(+) Configure the source, destination address and data length and Start DMA transfer
|
||||
(+) Configure the source, destination address and data length and
|
||||
Start DMA transfer with interrupt
|
||||
(+) Abort DMA transfer
|
||||
(+) Poll for transfer complete
|
||||
(+) Handle DMA interrupt request
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length & clear flags*/
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Start the DMA Transfer with interrupt enabled.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
/* Change DMA peripheral state */
|
||||
hdma->State = HAL_DMA_STATE_BUSY;
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
||||
|
||||
/* Disable the peripheral */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Configure the source, destination address and the data length & clear flags*/
|
||||
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
||||
|
||||
/* Enable the transfer complete interrupt */
|
||||
/* Enable the transfer Error interrupt */
|
||||
if(NULL != hdma->XferHalfCpltCallback )
|
||||
{
|
||||
/* Enable the Half transfer complete interrupt as well */
|
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
}
|
||||
else
|
||||
{
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
||||
}
|
||||
|
||||
/* Enable the Peripheral */
|
||||
__HAL_DMA_ENABLE(hdma);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Remain BUSY */
|
||||
status = HAL_BUSY;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort the DMA Transfer.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the DMA peripheral state */
|
||||
if(hdma->State != HAL_DMA_STATE_BUSY)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
|
||||
/* Disable the channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Aborts the DMA Transfer in Interrupt mode.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable DMA IT */
|
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
|
||||
/* Disable the channel */
|
||||
__HAL_DMA_DISABLE(hdma);
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
/* Call User Abort callback */
|
||||
if(hdma->XferAbortCallback != NULL)
|
||||
{
|
||||
hdma->XferAbortCallback(hdma);
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Polling for transfer complete.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CompleteLevel Specifies the DMA level complete.
|
||||
* @param Timeout Timeout duration.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
|
||||
{
|
||||
uint32_t temp;
|
||||
uint32_t tickstart;
|
||||
|
||||
if(HAL_DMA_STATE_BUSY != hdma->State)
|
||||
{
|
||||
/* no transfer ongoing */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
||||
__HAL_UNLOCK(hdma);
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Polling mode not supported in circular mode */
|
||||
if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
|
||||
{
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Get the level transfer complete flag */
|
||||
if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Transfer Complete flag */
|
||||
temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Half Transfer Complete flag */
|
||||
temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
|
||||
}
|
||||
|
||||
/* Get tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while((hdma->DmaBaseAddress->ISR & temp) == 0U)
|
||||
{
|
||||
if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State= HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
/* Check for the Timeout */
|
||||
if(Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
||||
{
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
|
||||
{
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
|
||||
|
||||
/* The selected Channelx EN bit is cleared (DMA is disabled and
|
||||
all transfers are complete) */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
|
||||
}
|
||||
|
||||
/* Process unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle DMA interrupt request.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
uint32_t flag_it = hdma->DmaBaseAddress->ISR;
|
||||
uint32_t source_it = hdma->Instance->CCR;
|
||||
|
||||
/* Half Transfer Complete Interrupt management ******************************/
|
||||
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
||||
{
|
||||
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the half transfer interrupt */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
||||
}
|
||||
/* Clear the half transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
|
||||
|
||||
/* DMA peripheral state is not updated in Half Transfer */
|
||||
/* but in Transfer Complete case */
|
||||
|
||||
if(hdma->XferHalfCpltCallback != NULL)
|
||||
{
|
||||
/* Half transfer callback */
|
||||
hdma->XferHalfCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Complete Interrupt management ***********************************/
|
||||
else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
|
||||
{
|
||||
|
||||
if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
||||
{
|
||||
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
|
||||
/* Disable the transfer complete and error interrupt */
|
||||
/* if the DMA mode is not CIRCULAR */
|
||||
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
}
|
||||
/* Clear the transfer complete flag */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if(hdma->XferCpltCallback != NULL)
|
||||
{
|
||||
/* Transfer complete callback */
|
||||
hdma->XferCpltCallback(hdma);
|
||||
}
|
||||
}
|
||||
|
||||
/* Transfer Error Interrupt management **************************************/
|
||||
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
|
||||
{
|
||||
/* When a DMA transfer error occurs */
|
||||
/* A hardware clear of its EN bits is performed */
|
||||
/* Disable ALL DMA IT */
|
||||
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
||||
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Update error code */
|
||||
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
||||
|
||||
/* Change the DMA state */
|
||||
hdma->State = HAL_DMA_STATE_READY;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
if (hdma->XferErrorCallback != NULL)
|
||||
{
|
||||
/* Transfer error callback */
|
||||
hdma->XferErrorCallback(hdma);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Nothing To Do */
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CallbackID User Callback identifer
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @param pCallback pointer to private callbacsk function which has pointer to
|
||||
* a DMA_HandleTypeDef structure as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = pCallback;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = pCallback;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief UnRegister callbacks
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param CallbackID User Callback identifer
|
||||
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hdma);
|
||||
|
||||
if(HAL_DMA_STATE_READY == hdma->State)
|
||||
{
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_DMA_XFER_CPLT_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_HALFCPLT_CB_ID:
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ERROR_CB_ID:
|
||||
hdma->XferErrorCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ABORT_CB_ID:
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
case HAL_DMA_XFER_ALL_CB_ID:
|
||||
hdma->XferCpltCallback = NULL;
|
||||
hdma->XferHalfCpltCallback = NULL;
|
||||
hdma->XferErrorCallback = NULL;
|
||||
hdma->XferAbortCallback = NULL;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hdma);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral State and Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral State and Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides functions allowing to
|
||||
(+) Check the DMA state
|
||||
(+) Get error code
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return the DMA handle state.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
/* Return DMA handle state */
|
||||
return hdma->State;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the DMA error code.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @retval DMA Error Code
|
||||
*/
|
||||
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
|
||||
{
|
||||
return hdma->ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the DMA Transfer parameter.
|
||||
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified DMA Channel.
|
||||
* @param SrcAddress The source memory Buffer address
|
||||
* @param DstAddress The destination memory Buffer address
|
||||
* @param DataLength The length of data to be transferred from source to destination
|
||||
* @retval HAL status
|
||||
*/
|
||||
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
||||
{
|
||||
/* Clear all flags */
|
||||
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
||||
|
||||
/* Configure DMA Channel data length */
|
||||
hdma->Instance->CNDTR = DataLength;
|
||||
|
||||
/* Memory to Peripheral */
|
||||
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
||||
{
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CPAR = DstAddress;
|
||||
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CMAR = SrcAddress;
|
||||
}
|
||||
/* Peripheral to Memory */
|
||||
else
|
||||
{
|
||||
/* Configure DMA Channel source address */
|
||||
hdma->Instance->CPAR = SrcAddress;
|
||||
|
||||
/* Configure DMA Channel destination address */
|
||||
hdma->Instance->CMAR = DstAddress;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_DMA_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,559 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_exti.c
|
||||
* @author MCD Application Team
|
||||
* @brief EXTI HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### EXTI Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) Each Exti line can be configured within this driver.
|
||||
|
||||
(+) Exti line can be configured in 3 different modes
|
||||
(++) Interrupt
|
||||
(++) Event
|
||||
(++) Both of them
|
||||
|
||||
(+) Configurable Exti lines can be configured with 3 different triggers
|
||||
(++) Rising
|
||||
(++) Falling
|
||||
(++) Both of them
|
||||
|
||||
(+) When set in interrupt mode, configurable Exti lines have two different
|
||||
interrupts pending registers which allow to distinguish which transition
|
||||
occurs:
|
||||
(++) Rising edge pending interrupt
|
||||
(++) Falling
|
||||
|
||||
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
|
||||
be selected through multiplexer.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
|
||||
(#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
|
||||
(++) Choose the interrupt line number by setting "Line" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) Configure the interrupt and/or event mode using "Mode" member from
|
||||
EXTI_ConfigTypeDef structure.
|
||||
(++) For configurable lines, configure rising and/or falling trigger
|
||||
"Trigger" member from EXTI_ConfigTypeDef structure.
|
||||
(++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
|
||||
member from GPIO_InitTypeDef structure.
|
||||
|
||||
(#) Get current Exti configuration of a dedicated line using
|
||||
HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
(++) Provide exiting handle as first parameter.
|
||||
(++) Provide which callback will be registered using one value from
|
||||
EXTI_CallbackIDTypeDef.
|
||||
(++) Provide callback function pointer.
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2018 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
/** MISRA C:2012 deviation rule has been granted for following rule:
|
||||
* Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
|
||||
* of bounds [0,3] in following API :
|
||||
* HAL_EXTI_SetConfigLine
|
||||
* HAL_EXTI_GetConfigLine
|
||||
* HAL_EXTI_ClearConfigLine
|
||||
*/
|
||||
|
||||
#ifdef HAL_EXTI_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/** @defgroup EXTI_Private_Constants EXTI Private Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group1
|
||||
* @brief Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on EXTI configuration to be set.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(pExtiConfig->Line));
|
||||
assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
|
||||
|
||||
/* Assign line number to handle */
|
||||
hexti->Line = pExtiConfig->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* Configure triggers for configurable lines */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
|
||||
|
||||
/* Configure rising trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->RTSR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure falling trigger */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
|
||||
{
|
||||
EXTI->FTSR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->FTSR &= ~maskline;
|
||||
}
|
||||
|
||||
|
||||
/* Configure gpio port selection in case of gpio exti line */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure interrupt mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
|
||||
{
|
||||
EXTI->IMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->IMR &= ~maskline;
|
||||
}
|
||||
|
||||
/* Configure event mode : read current mode */
|
||||
/* Mask or set line */
|
||||
if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
|
||||
{
|
||||
EXTI->EMR |= maskline;
|
||||
}
|
||||
else
|
||||
{
|
||||
EXTI->EMR &= ~maskline;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param pExtiConfig Pointer on structure to store Exti configuration.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if ((hexti == NULL) || (pExtiConfig == NULL))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* Store handle line number to configuration structure */
|
||||
pExtiConfig->Line = hexti->Line;
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Get core mode : interrupt */
|
||||
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->IMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Mode = EXTI_MODE_NONE;
|
||||
}
|
||||
|
||||
/* Get event mode */
|
||||
/* Check if selected line is enable */
|
||||
if ((EXTI->EMR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Mode |= EXTI_MODE_EVENT;
|
||||
}
|
||||
|
||||
/* 2] Get trigger for configurable lines : rising */
|
||||
if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->RTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
}
|
||||
|
||||
/* Get falling configuration */
|
||||
/* Check if configuration of selected line is enable */
|
||||
if ((EXTI->FTSR & maskline) != 0x00u)
|
||||
{
|
||||
pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
|
||||
}
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24);
|
||||
}
|
||||
else
|
||||
{
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No Trigger selected */
|
||||
pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
|
||||
pExtiConfig->GPIOSel = 0x00u;
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear whole configuration of a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
|
||||
/* compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* 1] Clear interrupt mode */
|
||||
EXTI->IMR = (EXTI->IMR & ~maskline);
|
||||
|
||||
/* 2] Clear event mode */
|
||||
EXTI->EMR = (EXTI->EMR & ~maskline);
|
||||
|
||||
/* 3] Clear triggers in case of configurable lines */
|
||||
if ((hexti->Line & EXTI_CONFIG) != 0x00u)
|
||||
{
|
||||
EXTI->RTSR = (EXTI->RTSR & ~maskline);
|
||||
EXTI->FTSR = (EXTI->FTSR & ~maskline);
|
||||
|
||||
/* Get Gpio port selection for gpio lines */
|
||||
if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
|
||||
{
|
||||
assert_param(IS_EXTI_GPIO_PIN(linepos));
|
||||
|
||||
regval = SYSCFG->EXTICR[linepos >> 2u];
|
||||
regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
|
||||
SYSCFG->EXTICR[linepos >> 2u] = regval;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register callback for a dedicated Exti line.
|
||||
* @param hexti Exti handle.
|
||||
* @param CallbackID User callback identifier.
|
||||
* This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
|
||||
* @param pPendingCbfn function pointer to be stored as callback.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
switch (CallbackID)
|
||||
{
|
||||
case HAL_EXTI_COMMON_CB_ID:
|
||||
hexti->PendingCallback = pPendingCbfn;
|
||||
break;
|
||||
|
||||
default:
|
||||
status = HAL_ERROR;
|
||||
break;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Store line number as handle private field.
|
||||
* @param hexti Exti handle.
|
||||
* @param ExtiLine Exti line number.
|
||||
* This parameter can be from 0 to @ref EXTI_LINE_NB.
|
||||
* @retval HAL Status.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(ExtiLine));
|
||||
|
||||
/* Check null pointer */
|
||||
if (hexti == NULL)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Store line number as handle private field */
|
||||
hexti->Line = ExtiLine;
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI_Exported_Functions_Group2
|
||||
* @brief EXTI IO functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Handle EXTI interrupt request.
|
||||
* @param hexti Exti handle.
|
||||
* @retval none.
|
||||
*/
|
||||
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Get pending bit */
|
||||
regval = (EXTI->PR & maskline);
|
||||
if (regval != 0x00u)
|
||||
{
|
||||
/* Clear pending bit */
|
||||
EXTI->PR = maskline;
|
||||
|
||||
/* Call callback */
|
||||
if (hexti->PendingCallback != NULL)
|
||||
{
|
||||
hexti->PendingCallback();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be checked.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval 1 if interrupt is pending else 0.
|
||||
*/
|
||||
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t linepos;
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
linepos = (hexti->Line & EXTI_PIN_MASK);
|
||||
maskline = (1uL << linepos);
|
||||
|
||||
/* return 1 if bit is set else 0 */
|
||||
regval = ((EXTI->PR & maskline) >> linepos);
|
||||
return regval;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear interrupt pending bit of a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @param Edge Specify which pending edge as to be clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref EXTI_TRIGGER_RISING_FALLING
|
||||
* This parameter is kept for compatibility with other series.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_PENDING_EDGE(Edge));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Clear Pending bit */
|
||||
EXTI->PR = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generate a software interrupt for a dedicated line.
|
||||
* @param hexti Exti handle.
|
||||
* @retval None.
|
||||
*/
|
||||
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
|
||||
{
|
||||
uint32_t maskline;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
/* Compute line mask */
|
||||
maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
|
||||
|
||||
/* Generate Software interrupt */
|
||||
EXTI->SWIER = maskline;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_EXTI_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,721 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the internal FLASH memory:
|
||||
* + Program operations functions
|
||||
* + Memory Control functions
|
||||
* + Peripheral State functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### FLASH peripheral features #####
|
||||
==============================================================================
|
||||
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
|
||||
to the Flash memory. It implements the erase and program Flash memory operations
|
||||
and the read and write protection mechanisms.
|
||||
|
||||
[..] The Flash memory interface accelerates code execution with a system of instruction
|
||||
prefetch.
|
||||
|
||||
[..] The FLASH main features are:
|
||||
(+) Flash memory read operations
|
||||
(+) Flash memory program/erase operations
|
||||
(+) Read / write protections
|
||||
(+) Prefetch on I-Code
|
||||
(+) Option Bytes programming
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This driver provides functions and macros to configure and program the FLASH
|
||||
memory of all STM32L1xx devices.
|
||||
|
||||
(#) FLASH Memory I/O Programming functions: this group includes all needed
|
||||
functions to erase and program the main memory:
|
||||
(++) Lock and Unlock the FLASH interface
|
||||
(++) Erase function: Erase page
|
||||
(++) Program functions: Fast Word and Half Page(should be
|
||||
executed from internal SRAM).
|
||||
|
||||
(#) DATA EEPROM Programming functions: this group includes all
|
||||
needed functions to erase and program the DATA EEPROM memory:
|
||||
(++) Lock and Unlock the DATA EEPROM interface.
|
||||
(++) Erase function: Erase Byte, erase HalfWord, erase Word, erase
|
||||
Double Word (should be executed from internal SRAM).
|
||||
(++) Program functions: Fast Program Byte, Fast Program Half-Word,
|
||||
FastProgramWord, Program Byte, Program Half-Word,
|
||||
Program Word and Program Double-Word (should be executed
|
||||
from internal SRAM).
|
||||
|
||||
(#) FLASH Option Bytes Programming functions: this group includes all needed
|
||||
functions to manage the Option Bytes:
|
||||
(++) Lock and Unlock the Option Bytes
|
||||
(++) Set/Reset the write protection
|
||||
(++) Set the Read protection Level
|
||||
(++) Program the user Option Bytes
|
||||
(++) Launch the Option Bytes loader
|
||||
(++) Set/Get the Read protection Level.
|
||||
(++) Set/Get the BOR level.
|
||||
(++) Get the Write protection.
|
||||
(++) Get the user option bytes.
|
||||
|
||||
(#) Interrupts and flags management functions : this group
|
||||
includes all needed functions to:
|
||||
(++) Handle FLASH interrupts
|
||||
(++) Wait for last FLASH operation according to its status
|
||||
(++) Get error flag status
|
||||
|
||||
(#) FLASH Interface configuration functions: this group includes
|
||||
the management of following features:
|
||||
(++) Enable/Disable the RUN PowerDown mode.
|
||||
(++) Enable/Disable the SLEEP PowerDown mode.
|
||||
|
||||
(#) FLASH Peripheral State methods: this group includes
|
||||
the management of following features:
|
||||
(++) Wait for the FLASH operation
|
||||
(++) Get the specific FLASH error flag
|
||||
|
||||
[..] In addition to these function, this driver includes a set of macros allowing
|
||||
to handle the following operations:
|
||||
|
||||
(+) Set/Get the latency
|
||||
(+) Enable/Disable the prefetch buffer
|
||||
(+) Enable/Disable the 64 bit Read Access.
|
||||
(+) Enable/Disable the Flash power-down
|
||||
(+) Enable/Disable the FLASH interrupts
|
||||
(+) Monitor the FLASH flags status
|
||||
|
||||
##### Programming operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the FLASH
|
||||
program operations.
|
||||
|
||||
[..] The FLASH Memory Programming functions, includes the following functions:
|
||||
(+) HAL_FLASH_Unlock(void);
|
||||
(+) HAL_FLASH_Lock(void);
|
||||
(+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
(+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
|
||||
[..] Any operation of erase or program should follow these steps:
|
||||
(#) Call the HAL_FLASH_Unlock() function to enable the flash control register and
|
||||
program memory access.
|
||||
(#) Call the desired function to erase page or program data.
|
||||
(#) Call the HAL_FLASH_Lock() to disable the flash program memory access
|
||||
(recommended to protect the FLASH memory against possible unwanted operation).
|
||||
|
||||
##### Option Bytes Programming functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The FLASH_Option Bytes Programming_functions, includes the following functions:
|
||||
(+) HAL_FLASH_OB_Unlock(void);
|
||||
(+) HAL_FLASH_OB_Lock(void);
|
||||
(+) HAL_FLASH_OB_Launch(void);
|
||||
(+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
(+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
|
||||
[..] Any operation of erase or program should follow these steps:
|
||||
(#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control
|
||||
register access.
|
||||
(#) Call the following functions to program the desired option bytes.
|
||||
(++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
|
||||
(#) Once all needed option bytes to be programmed are correctly written, call the
|
||||
HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
|
||||
(#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
|
||||
to protect the option Bytes against possible unwanted operations).
|
||||
|
||||
[..] Proprietary code Read Out Protection (PcROP):
|
||||
(#) The PcROP sector is selected by using the same option bytes as the Write
|
||||
protection. As a result, these 2 options are exclusive each other.
|
||||
(#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below:
|
||||
(++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @defgroup FLASH FLASH
|
||||
* @brief FLASH HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Constants FLASH Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro ---------------------------- ---------------------------------*/
|
||||
/** @defgroup FLASH_Private_Macros FLASH Private Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Variables FLASH Private Variables
|
||||
* @{
|
||||
*/
|
||||
/* Variables used for Erase pages under interruption*/
|
||||
FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_Private_Functions FLASH Private Functions
|
||||
* @{
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void);
|
||||
extern void FLASH_PageErase(uint32_t PageAddress);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Program word at a specified address
|
||||
* @note To correctly run this function, the HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_ERROR;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
/*Program word (32-bit) at a specified address.*/
|
||||
*(__IO uint32_t *)Address = Data;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program word at a specified address with interrupt enabled.
|
||||
*
|
||||
* @param TypeProgram Indicate the way to program at a specified address.
|
||||
* This parameter can be a value of @ref FLASH_Type_Program
|
||||
* @param Address Specifie the address to be programmed.
|
||||
* @param Data Specifie the data to be programmed
|
||||
*
|
||||
* @retval HAL_StatusTypeDef HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(&pFlash);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
|
||||
assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
|
||||
|
||||
/* Enable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
pFlash.Address = Address;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
|
||||
/* Clean the error context */
|
||||
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
|
||||
|
||||
if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
|
||||
{
|
||||
/* Program word (32-bit) at a specified address. */
|
||||
*(__IO uint32_t *)Address = Data;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles FLASH interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASH_IRQHandler(void)
|
||||
{
|
||||
uint32_t addresstmp = 0U;
|
||||
|
||||
/* Check FLASH operation error flags */
|
||||
if( __HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) ||
|
||||
#if defined(FLASH_SR_RDERR)
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
#endif /* FLASH_SR_RDERR */
|
||||
#if defined(FLASH_SR_OPTVERRUSR)
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
|
||||
#endif /* FLASH_SR_OPTVERRUSR */
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) )
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Return the faulty sector */
|
||||
addresstmp = pFlash.Page;
|
||||
pFlash.Page = 0xFFFFFFFFU;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Return the faulty address */
|
||||
addresstmp = pFlash.Address;
|
||||
}
|
||||
/* Save the Error code */
|
||||
FLASH_SetErrorCode();
|
||||
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(addresstmp);
|
||||
|
||||
/* Stop the procedure ongoing */
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
|
||||
/* Process can continue only if no error detected */
|
||||
if(pFlash.ProcedureOnGoing != FLASH_PROC_NONE)
|
||||
{
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
|
||||
{
|
||||
/* Nb of pages to erased can be decreased */
|
||||
pFlash.NbPagesToErase--;
|
||||
|
||||
/* Check if there are still pages to erase */
|
||||
if(pFlash.NbPagesToErase != 0U)
|
||||
{
|
||||
addresstmp = pFlash.Page;
|
||||
/*Indicate user which sector has been erased */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
|
||||
/*Increment sector number*/
|
||||
addresstmp = pFlash.Page + FLASH_PAGE_SIZE;
|
||||
pFlash.Page = addresstmp;
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE Bit */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
|
||||
FLASH_PageErase(addresstmp);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No more pages to Erase, user callback can be called. */
|
||||
/* Reset Sector and stop Erase pages procedure */
|
||||
pFlash.Page = addresstmp = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(addresstmp);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If the program operation is completed, disable the PROG Bit */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Program ended. Return the selected address */
|
||||
/* FLASH EOP interrupt user callback */
|
||||
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
|
||||
|
||||
/* Reset Address and stop Program procedure */
|
||||
pFlash.Address = 0xFFFFFFFFU;
|
||||
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
{
|
||||
/* Operation is completed, disable the PROG and ERASE */
|
||||
CLEAR_BIT(FLASH->PECR, (FLASH_PECR_ERASE | FLASH_PECR_PROG));
|
||||
|
||||
/* Disable End of FLASH Operation and Error source interrupts */
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_ERR);
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(&pFlash);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH end of operation interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Pages Erase: Address of the page which has been erased
|
||||
* (if 0xFFFFFFFF, it means that all the selected pages have been erased)
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH operation error interrupt callback
|
||||
* @param ReturnValue The value saved in this parameter depends on the ongoing procedure
|
||||
* - Pages Erase: Address of the page which returned an error
|
||||
* - Program: Address which was selected for data program
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(ReturnValue);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the FLASH
|
||||
memory operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
|
||||
{
|
||||
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
|
||||
{
|
||||
/* Unlocking FLASH_PECR register access*/
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
|
||||
|
||||
/* Verify that PELOCK is unlocked */
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Unlocking the program memory access */
|
||||
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY1);
|
||||
WRITE_REG(FLASH->PRGKEYR, FLASH_PRGKEY2);
|
||||
|
||||
/* Verify that PRGLOCK is unlocked */
|
||||
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PRGLOCK))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks the FLASH control register access
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_Lock(void)
|
||||
{
|
||||
/* Set the PRGLOCK Bit to lock the FLASH Registers access */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unlock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
|
||||
{
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
|
||||
{
|
||||
/* Unlocking FLASH_PECR register access*/
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
/* Unlocking FLASH_PECR register access*/
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY1);
|
||||
WRITE_REG(FLASH->PEKEYR, FLASH_PEKEY2);
|
||||
|
||||
/* Verify that PELOCK is unlocked */
|
||||
if(HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_PELOCK))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Unlocking the option bytes block access */
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
|
||||
WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
|
||||
|
||||
/* Verify that OPTLOCK is unlocked */
|
||||
if (HAL_IS_BIT_SET(FLASH->PECR, FLASH_PECR_OPTLOCK))
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Lock the FLASH Option Control Registers access.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
|
||||
{
|
||||
/* Set the OPTLOCK Bit to lock the option bytes block access */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Launch the option byte loading.
|
||||
* @note This function will reset automatically the MCU.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
{
|
||||
/* Set the OBL_Launch bit to launch the option byte loading */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH error flag.
|
||||
* @retval FLASH_ErrorCode The returned value can be:
|
||||
* @ref FLASH_Error_Codes
|
||||
*/
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
return pFlash.ErrorCode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operation timeout
|
||||
* @retval HAL Status
|
||||
*/
|
||||
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
uint32_t tickstart = HAL_GetTick();
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
|
||||
{
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
#if defined(FLASH_SR_RDERR)
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
#endif /* FLASH_SR_RDERR */
|
||||
#if defined(FLASH_SR_OPTVERRUSR)
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
|
||||
#endif /* FLASH_SR_OPTVERRUSR */
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASH_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval None
|
||||
*/
|
||||
static void FLASH_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
||||
flags |= FLASH_FLAG_PGAERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
|
||||
flags |= FLASH_FLAG_OPTVERR;
|
||||
}
|
||||
|
||||
#if defined(FLASH_SR_RDERR)
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
|
||||
flags |= FLASH_FLAG_RDERR;
|
||||
}
|
||||
#endif /* FLASH_SR_RDERR */
|
||||
#if defined(FLASH_SR_OPTVERRUSR)
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
|
||||
flags |= FLASH_FLAG_OPTVERRUSR;
|
||||
}
|
||||
#endif /* FLASH_SR_OPTVERRUSR */
|
||||
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,644 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_flash_ramfunc.c
|
||||
* @author MCD Application Team
|
||||
* @brief FLASH RAMFUNC driver.
|
||||
* This file provides a Flash firmware functions which should be
|
||||
* executed from internal SRAM
|
||||
*
|
||||
* @verbatim
|
||||
|
||||
*** ARM Compiler ***
|
||||
--------------------
|
||||
[..] RAM functions are defined using the toolchain options.
|
||||
Functions that are be executed in RAM should reside in a separate
|
||||
source module. Using the 'Options for File' dialog you can simply change
|
||||
the 'Code / Const' area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the
|
||||
Options for Target' dialog.
|
||||
|
||||
*** ICCARM Compiler ***
|
||||
-----------------------
|
||||
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
|
||||
*** GNU Compiler ***
|
||||
--------------------
|
||||
[..] RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".RamFunc")))".
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_FLASH_MODULE_ENABLED
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
/** @addtogroup FLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
extern FLASH_ProcessTypeDef pFlash;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
|
||||
* @brief FLASH functions executed from RAM
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout);
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### ramfunc functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions that should be executed from RAM
|
||||
transfers.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable the power down mode during RUN mode.
|
||||
* @note This function can be used only when the user code is running from Internal SRAM.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void)
|
||||
{
|
||||
/* Enable the Power Down in Run mode*/
|
||||
__HAL_FLASH_POWER_DOWN_ENABLE();
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the power down mode during RUN mode.
|
||||
* @note This function can be used only when the user code is running from Internal SRAM.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void)
|
||||
{
|
||||
/* Disable the Power Down in Run mode*/
|
||||
__HAL_FLASH_POWER_DOWN_DISABLE();
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined(FLASH_PECR_PARALLBANK)
|
||||
/**
|
||||
* @brief Erases a specified 2 pages in program memory in parallel.
|
||||
* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
|
||||
* To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
* @param Page_Address1: The page address in program memory to be erased in
|
||||
* the first Bank (BANK1). This parameter should be between FLASH_BASE
|
||||
* and FLASH_BANK1_END.
|
||||
* @param Page_Address2: The page address in program memory to be erased in
|
||||
* the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
|
||||
* and FLASH_BANK2_END.
|
||||
* @note A Page is erased in the Program memory only if the address to load
|
||||
* is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Proceed to erase the page */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Write 00000000h to the first word of the first program page to erase */
|
||||
*(__IO uint32_t *)Page_Address1 = 0x00000000U;
|
||||
/* Write 00000000h to the first word of the second program page to erase */
|
||||
*(__IO uint32_t *)Page_Address2 = 0x00000000U;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
}
|
||||
/* Return the Erase Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Program 2 half pages in program memory in parallel (half page size is 32 Words).
|
||||
* @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
|
||||
* @param Address1: specifies the first address to be written in the first bank
|
||||
* (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
|
||||
* @param pBuffer1: pointer to the buffer containing the data to be written
|
||||
* to the first half page in the first bank.
|
||||
* @param Address2: specifies the second address to be written in the second bank
|
||||
* (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
|
||||
* @param pBuffer2: pointer to the buffer containing the data to be written
|
||||
* to the second half page in the second bank.
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
* @note Half page write is possible only from SRAM.
|
||||
* @note If there are more than 32 words to write, after 32 words another
|
||||
* Half Page programming operation starts and has to be finished.
|
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 128
|
||||
* bytes) and the 31 remaining words to load are in the same half page.
|
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Disable all IRQs */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* Proceed to program the new half page */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Write the first half page directly with 32 different words */
|
||||
while(count < 32U)
|
||||
{
|
||||
*(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
|
||||
pBuffer1++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Write the second half page directly with 32 different words */
|
||||
count = 0U;
|
||||
while(count < 32U)
|
||||
{
|
||||
*(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
|
||||
pBuffer2++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
|
||||
|
||||
/* Enable IRQs */
|
||||
__set_PRIMASK(primask_bit);
|
||||
}
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
#endif /* FLASH_PECR_PARALLBANK */
|
||||
|
||||
/**
|
||||
* @brief Program a half page in program memory.
|
||||
* @param Address specifies the address to be written.
|
||||
* @param pBuffer pointer to the buffer containing the data to be written to
|
||||
* the half page.
|
||||
* @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the @ref HAL_FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @note Half page write is possible only from SRAM.
|
||||
* @note If there are more than 32 words to write, after 32 words another
|
||||
* Half Page programming operation starts and has to be finished.
|
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 128
|
||||
* bytes) and the 31 remaining words to load are in the same half page.
|
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning.
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
uint32_t count = 0U;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Disable all IRQs */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* Proceed to program the new half page */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
|
||||
/* Write one half page directly with 32 different words */
|
||||
while(count < 32U)
|
||||
{
|
||||
*(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
|
||||
pBuffer++;
|
||||
count ++;
|
||||
}
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the write operation is completed, disable the PROG and FPRG bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
|
||||
/* Enable IRQs */
|
||||
__set_PRIMASK(primask_bit);
|
||||
}
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
|
||||
* @brief Peripheral errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral errors functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection permit to get in run-time errors of the FLASH peripheral.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get the specific FLASH errors flag.
|
||||
* @param Error pointer is the error value. It can be a mixed of:
|
||||
@if STM32L100xB
|
||||
@elif STM32L100xBA
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
@elif STM32L151xB
|
||||
@elif STM32L151xBA
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
@elif STM32L152xB
|
||||
@elif STM32L152xBA
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
@elif STM32L100xC
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
|
||||
@elif STM32L151xC
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
|
||||
@elif STM32L152xC
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
|
||||
@elif STM32L162xC
|
||||
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
|
||||
@else
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
|
||||
@endif
|
||||
* @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag
|
||||
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
|
||||
* @retval HAL Status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_GetError(uint32_t * Error)
|
||||
{
|
||||
*Error = pFlash.ErrorCode;
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions
|
||||
*
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erase a double word in data memory.
|
||||
* @param Address specifies the address to be erased.
|
||||
* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
|
||||
* must be called before.
|
||||
* Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
|
||||
* and Flash program erase control register access(recommended to protect
|
||||
* the DATA_EEPROM against possible unwanted operation).
|
||||
* @note Data memory double word erase is possible only from SRAM.
|
||||
* @note A double word is erased to the data memory only if the first address
|
||||
* to load is the start address of a double word (multiple of 8 bytes).
|
||||
* @note During the Data memory double word erase, all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @retval HAL status
|
||||
*/
|
||||
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Disable all IRQs */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* If the previous operation is completed, proceed to erase the next double word */
|
||||
/* Set the ERASE bit */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
|
||||
/* Set DATA bit */
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
|
||||
|
||||
/* Write 00000000h to the 2 words to erase */
|
||||
*(__IO uint32_t *)Address = 0x00000000U;
|
||||
Address += 4U;
|
||||
*(__IO uint32_t *)Address = 0x00000000U;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE and DATA bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
|
||||
|
||||
/* Enable IRQs */
|
||||
__set_PRIMASK(primask_bit);
|
||||
|
||||
}
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a double word in data memory without erase.
|
||||
* @param Address specifies the address to be written.
|
||||
* @param Data specifies the data to be written.
|
||||
* @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
|
||||
* must be called before.
|
||||
* Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
|
||||
* and Flash program erase control register access(recommended to protect
|
||||
* the DATA_EEPROM against possible unwanted operation).
|
||||
* @note Data memory double word write is possible only from SRAM.
|
||||
* @note A data memory double word is written to the data memory only if the
|
||||
* first address to load is the start address of a double word (multiple
|
||||
* of double word).
|
||||
* @note During the Data memory double word write, all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @retval HAL status
|
||||
*/
|
||||
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
|
||||
{
|
||||
uint32_t primask_bit;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
if(status == HAL_OK)
|
||||
{
|
||||
/* Disable all IRQs */
|
||||
primask_bit = __get_PRIMASK();
|
||||
__disable_irq();
|
||||
|
||||
/* If the previous operation is completed, proceed to program the new data*/
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
|
||||
|
||||
/* Write the 2 words */
|
||||
*(__IO uint32_t *)Address = (uint32_t) Data;
|
||||
Address += 4U;
|
||||
*(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
|
||||
|
||||
/* If the write operation is completed, disable the FPRG and DATA bits */
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
|
||||
CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
|
||||
|
||||
/* Enable IRQs */
|
||||
__set_PRIMASK(primask_bit);
|
||||
}
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_RAMFUNC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set the specific FLASH error flag.
|
||||
* @retval HAL Status
|
||||
*/
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_SetErrorCode(void)
|
||||
{
|
||||
uint32_t flags = 0U;
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
|
||||
flags |= FLASH_FLAG_WRPERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
|
||||
flags |= FLASH_FLAG_PGAERR;
|
||||
}
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
|
||||
flags |= FLASH_FLAG_OPTVERR;
|
||||
}
|
||||
|
||||
#if defined(FLASH_SR_RDERR)
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
|
||||
flags |= FLASH_FLAG_RDERR;
|
||||
}
|
||||
#endif /* FLASH_SR_RDERR */
|
||||
#if defined(FLASH_SR_OPTVERRUSR)
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
|
||||
{
|
||||
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
|
||||
flags |= FLASH_FLAG_OPTVERRUSR;
|
||||
}
|
||||
#endif /* FLASH_SR_OPTVERRUSR */
|
||||
|
||||
/* Clear FLASH error pending bits */
|
||||
__HAL_FLASH_CLEAR_FLAG(flags);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Wait for a FLASH operation to complete.
|
||||
* @param Timeout maximum flash operationtimeout
|
||||
* @retval HAL status
|
||||
*/
|
||||
static __RAM_FUNC HAL_StatusTypeDef FLASHRAM_WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
|
||||
Even if the FLASH operation fails, the BUSY flag will be reset and an error
|
||||
flag will be set */
|
||||
|
||||
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U))
|
||||
{
|
||||
Timeout--;
|
||||
}
|
||||
|
||||
if(Timeout == 0x00U)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
/* Check FLASH End of Operation flag */
|
||||
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
|
||||
{
|
||||
/* Clear FLASH End of Operation pending bit */
|
||||
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
|
||||
}
|
||||
|
||||
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
|
||||
#if defined(FLASH_SR_RDERR)
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
|
||||
#endif /* FLASH_SR_RDERR */
|
||||
#if defined(FLASH_SR_OPTVERRUSR)
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
|
||||
#endif /* FLASH_SR_OPTVERRUSR */
|
||||
__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
|
||||
{
|
||||
/*Save the error code*/
|
||||
FLASHRAM_SetErrorCode();
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* There is no error flag set */
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_FLASH_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,550 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @brief GPIO HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
|
||||
* + Initialization and de-initialization functions
|
||||
* + IO operation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### GPIO Peripheral features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
configured by software in several modes:
|
||||
(+) Input mode
|
||||
(+) Analog mode
|
||||
(+) Output mode
|
||||
(+) Alternate function mode
|
||||
(+) External interrupt/event lines
|
||||
|
||||
[..]
|
||||
During and just after reset, the alternate functions and external interrupt
|
||||
lines are not active and the I/O ports are configured in input floating mode.
|
||||
|
||||
[..]
|
||||
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
|
||||
activated or not.
|
||||
|
||||
[..]
|
||||
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
|
||||
type and the IO speed can be selected depending on the VDD value.
|
||||
|
||||
[..]
|
||||
The microcontroller IO pins are connected to onboard peripherals/modules through a
|
||||
multiplexer that allows only one peripheral s alternate function (AF) connected
|
||||
to an IO pin at a time. In this way, there can be no conflict between peripherals
|
||||
sharing the same IO pin.
|
||||
|
||||
[..]
|
||||
All ports have external interrupt/event capability. To use external interrupt
|
||||
lines, the port must be configured in input mode. All available GPIO pins are
|
||||
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
|
||||
|
||||
[..]
|
||||
The external interrupt/event controller consists of up to 28 edge detectors
|
||||
(depending on products 16 lines are connected to GPIO) for generating event/interrupt
|
||||
requests (each input line can be independently configured to select the type
|
||||
(interrupt or event) and the corresponding trigger event (rising or falling or both).
|
||||
Each line can also be masked independently.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE().
|
||||
|
||||
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
|
||||
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
|
||||
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
|
||||
structure.
|
||||
(++) In case of Output or alternate function mode selection: the speed is
|
||||
configured through "Speed" member from GPIO_InitTypeDef structure,
|
||||
the speed is configurable: Low, Medium and High.
|
||||
(++) If alternate mode is selected, the alternate function connected to the IO
|
||||
is configured through "Alternate" member from GPIO_InitTypeDef structure
|
||||
(++) Analog mode is required when a pin is to be used as ADC channel
|
||||
or DAC output.
|
||||
(++) In case of external interrupt/event selection the "Mode" member from
|
||||
GPIO_InitTypeDef structure select the type (interrupt or event) and
|
||||
the corresponding trigger event (rising or falling or both).
|
||||
|
||||
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
|
||||
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
|
||||
HAL_NVIC_EnableIRQ().
|
||||
|
||||
(#) HAL_GPIO_DeInit allows to set register values to their reset value. It's also
|
||||
recommended to use it to unconfigure pin which was used as an external interrupt
|
||||
or in event mode. That's the only way to reset corresponding bit in EXTI & SYSCFG
|
||||
registers.
|
||||
|
||||
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
|
||||
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
|
||||
|
||||
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
|
||||
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode (except JTAG
|
||||
pins).
|
||||
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
|
||||
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
|
||||
priority over the GPIO function.
|
||||
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
|
||||
The HSE has priority over the GPIO function.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @brief GPIO HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_GPIO_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @addtogroup GPIO_Private_Constants
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_MODE (0x00000003U)
|
||||
#define EXTI_MODE (0x10000000U)
|
||||
#define GPIO_MODE_IT (0x00010000U)
|
||||
#define GPIO_MODE_EVT (0x00020000U)
|
||||
#define RISING_EDGE (0x00100000U)
|
||||
#define FALLING_EDGE (0x00200000U)
|
||||
#define GPIO_OUTPUT_TYPE (0x00000010U)
|
||||
|
||||
#define GPIO_NUMBER (16U)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Exported functions ---------------------------------------------------------*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group1
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
|
||||
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
|
||||
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
||||
* the configuration information for the specified GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
||||
{
|
||||
uint32_t position = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t temp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
||||
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
||||
|
||||
/* Configure the port pins */
|
||||
while (((GPIO_Init->Pin) >> position) != 0)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Init->Pin) & (1U << position);
|
||||
|
||||
if (iocurrent)
|
||||
{
|
||||
/*--------------------- GPIO Mode Configuration ------------------------*/
|
||||
/* In case of Output or Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
||||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Speed parameter */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
||||
/* Configure the IO Speed */
|
||||
temp = GPIOx->OSPEEDR;
|
||||
CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
SET_BIT(temp, GPIO_Init->Speed << (position * 2));
|
||||
GPIOx->OSPEEDR = temp;
|
||||
|
||||
/* Configure the IO Output Type */
|
||||
temp = GPIOx->OTYPER;
|
||||
CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
|
||||
SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
|
||||
GPIOx->OTYPER = temp;
|
||||
}
|
||||
|
||||
/* Activate the Pull-up or Pull down resistor for the current IO */
|
||||
temp = GPIOx->PUPDR;
|
||||
CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
|
||||
GPIOx->PUPDR = temp;
|
||||
|
||||
/* In case of Alternate function mode selection */
|
||||
if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
|
||||
{
|
||||
/* Check the Alternate function parameters */
|
||||
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
||||
|
||||
/* Configure Alternate function mapped with the current IO */
|
||||
/* Identify AFRL or AFRH register based on IO position*/
|
||||
temp = GPIOx->AFR[position >> 3];
|
||||
CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
|
||||
SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
|
||||
GPIOx->AFR[position >> 3] = temp;
|
||||
}
|
||||
|
||||
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
||||
temp = GPIOx->MODER;
|
||||
CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
|
||||
SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
|
||||
GPIOx->MODER = temp;
|
||||
|
||||
/*--------------------- EXTI Mode Configuration ------------------------*/
|
||||
/* Configure the External Interrupt or event for the current IO */
|
||||
if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
||||
{
|
||||
/* Enable SYSCFG Clock */
|
||||
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
||||
|
||||
temp = SYSCFG->EXTICR[position >> 2];
|
||||
CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
|
||||
SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
|
||||
SYSCFG->EXTICR[position >> 2] = temp;
|
||||
|
||||
/* Clear EXTI line configuration */
|
||||
temp = EXTI->IMR;
|
||||
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
||||
{
|
||||
SET_BIT(temp, iocurrent);
|
||||
}
|
||||
EXTI->IMR = temp;
|
||||
|
||||
temp = EXTI->EMR;
|
||||
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
||||
{
|
||||
SET_BIT(temp, iocurrent);
|
||||
}
|
||||
EXTI->EMR = temp;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
temp = EXTI->RTSR;
|
||||
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
||||
{
|
||||
SET_BIT(temp, iocurrent);
|
||||
}
|
||||
EXTI->RTSR = temp;
|
||||
|
||||
temp = EXTI->FTSR;
|
||||
CLEAR_BIT(temp, (uint32_t)iocurrent);
|
||||
if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
||||
{
|
||||
SET_BIT(temp, iocurrent);
|
||||
}
|
||||
EXTI->FTSR = temp;
|
||||
}
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
|
||||
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t position = 0x00;
|
||||
uint32_t iocurrent = 0x00;
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Configure the port pins */
|
||||
while ((GPIO_Pin >> position) != 0)
|
||||
{
|
||||
/* Get current io position */
|
||||
iocurrent = (GPIO_Pin) & (1U << position);
|
||||
|
||||
if (iocurrent)
|
||||
{
|
||||
/*------------------------- EXTI Mode Configuration --------------------*/
|
||||
/* Clear the External Interrupt or Event for the current IO */
|
||||
|
||||
tmp = SYSCFG->EXTICR[position >> 2];
|
||||
tmp &= ((0x0FU) << (4 * (position & 0x03)));
|
||||
if (tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
|
||||
CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
|
||||
CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
|
||||
|
||||
tmp = (0x0FU) << (4 * (position & 0x03));
|
||||
CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
|
||||
}
|
||||
|
||||
/*------------------------- GPIO Mode Configuration --------------------*/
|
||||
/* Configure IO Direction in Input Floting Mode */
|
||||
CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2));
|
||||
|
||||
/* Configure the default Alternate Function in current IO */
|
||||
CLEAR_BIT(GPIOx->AFR[position >> 3], 0xFU << ((uint32_t)(position & 0x07U) * 4)) ;
|
||||
/* Deactivate the Pull-up oand Pull-down resistor for the current IO */
|
||||
CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));
|
||||
|
||||
/* Configure the default value IO Output Type */
|
||||
CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
|
||||
|
||||
/* Configure the default value for IO Speed */
|
||||
CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
|
||||
}
|
||||
|
||||
position++;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO_Exported_Functions_Group2
|
||||
* @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### IO operation functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
|
||||
* @param GPIO_Pin specifies the port bit to read.
|
||||
* This parameter can be GPIO_PIN_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIO_PinState bitstatus;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
|
||||
{
|
||||
bitstatus = GPIO_PIN_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = GPIO_PIN_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
|
||||
* @param GPIO_Pin specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
|
||||
* @param PinState specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the GPIO_PinState enum values:
|
||||
* @arg GPIO_PIN_RESET: to clear the port pin
|
||||
* @arg GPIO_PIN_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
||||
|
||||
if (PinState != GPIO_PIN_RESET)
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pin
|
||||
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
|
||||
* @param GPIO_Pin specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t odr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* get current Ouput Data Register value */
|
||||
odr = GPIOx->ODR;
|
||||
|
||||
/* Set selected pins that were at low level, and reset ones that were high */
|
||||
GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* @note The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @note Limitation concerning GPIOx_OTYPER: Locking of GPIOx_OTYPER[i] with i = 15..8
|
||||
* depends from setting of GPIOx_LCKR[i-8] and not from GPIOx_LCKR[i].
|
||||
* GPIOx_LCKR[i-8] is locking GPIOx_OTYPER[i] together with GPIOx_OTYPER[i-8].
|
||||
* It is not possible to lock GPIOx_OTYPER[i] with i = 15..8, without locking also
|
||||
* GPIOx_OTYPER[i-8].
|
||||
* Workaround: When calling HAL_GPIO_LockPin with GPIO_Pin from GPIO_PIN_8 to GPIO_PIN_15,
|
||||
* you must call also HAL_GPIO_LockPin with GPIO_Pin - 8.
|
||||
* (When locking a pin from GPIO_PIN_8 to GPIO_PIN_15, you must lock also the corresponding
|
||||
* GPIO_PIN_0 to GPIO_PIN_7).
|
||||
* @param GPIOx where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
|
||||
* @param GPIO_Pin Specifies the port bit to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = GPIO_LCKR_LCKK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
/* Apply lock key write sequence */
|
||||
SET_BIT(tmp, GPIO_Pin);
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK register. This read is mandatory to complete key lock sequence */
|
||||
tmp = GPIOx->LCKR;
|
||||
|
||||
/* Read again in order to confirm lock is active */
|
||||
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
|
||||
{
|
||||
return HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function handles EXTI interrupt request.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* EXTI line interrupt detected */
|
||||
if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
|
||||
{
|
||||
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
|
||||
HAL_GPIO_EXTI_Callback(GPIO_Pin);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief EXTI line detection callbacks.
|
||||
* @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(GPIO_Pin);
|
||||
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_GPIO_EXTI_Callback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_GPIO_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,650 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @brief PWR HAL module driver.
|
||||
*
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Initialization/de-initialization functions
|
||||
* + Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR PWR
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define PVD_MODE_IT (0x00010000U)
|
||||
#define PVD_MODE_EVT (0x00020000U)
|
||||
#define PVD_RISING_EDGE (0x00000001U)
|
||||
#define PVD_FALLING_EDGE (0x00000002U)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions PWR Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
|
||||
* @brief Initialization and de-initialization functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and de-initialization functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
After reset, the backup domain (RTC registers, RTC backup data
|
||||
registers) is protected against possible unwanted
|
||||
write accesses.
|
||||
To enable access to the RTC Domain and RTC registers, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
__HAL_RCC_PWR_CLK_ENABLE() macro.
|
||||
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @note Before calling this function, the VOS[1:0] bits should be configured
|
||||
* to "10" and the system frequency has to be configured accordingly.
|
||||
* To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
|
||||
* function.
|
||||
* @note ULP and FWU bits are not reset by this function.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DeInit(void)
|
||||
{
|
||||
__HAL_RCC_PWR_FORCE_RESET();
|
||||
__HAL_RCC_PWR_RELEASE_RESET();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers ).
|
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableBkUpAccess(void)
|
||||
{
|
||||
/* Enable access to RTC and backup registers */
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables access to the backup domain (RTC registers, RTC
|
||||
* backup data registers).
|
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
|
||||
* Backup Domain Access should be kept enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableBkUpAccess(void)
|
||||
{
|
||||
/* Disable access to RTC and backup registers */
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
===============================================================================
|
||||
|
||||
*** PVD configuration ***
|
||||
=========================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a
|
||||
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) The PVD can use an external input analog voltage (PVD_IN) which is compared
|
||||
internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
|
||||
when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
|
||||
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
|
||||
than the PVD threshold. This event is internally connected to the EXTI
|
||||
line16 and can generate an interrupt if enabled. This is done through
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
*** WakeUp pin configuration ***
|
||||
================================
|
||||
[..]
|
||||
(+) WakeUp pin is used to wake up the system from Standby mode. This pin is
|
||||
forced in input pull-down configuration and is active on rising edges.
|
||||
(+) There are two or three WakeUp pins:
|
||||
WakeUp Pin 1 on PA.00.
|
||||
WakeUp Pin 2 on PC.13.
|
||||
WakeUp Pin 3 on PE.06. : Only on product with GPIOE available
|
||||
|
||||
[..]
|
||||
*** Main and Backup Regulators configuration ***
|
||||
================================================
|
||||
|
||||
(+) The main internal regulator can be configured to have a tradeoff between
|
||||
performance and power consumption when the device does not operate at
|
||||
the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
|
||||
macro which configure VOS bit in PWR_CR register:
|
||||
(++) When this bit is set (Regulator voltage output Scale 1 mode selected)
|
||||
the System frequency can go up to 32 MHz.
|
||||
(++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
|
||||
the System frequency can go up to 16 MHz.
|
||||
(++) When this bit is reset (Regulator voltage output Scale 3 mode selected)
|
||||
the System frequency can go up to 4.2 MHz.
|
||||
|
||||
Refer to the datasheets for more details.
|
||||
|
||||
*** Low Power modes configuration ***
|
||||
=====================================
|
||||
[..]
|
||||
The device features 5 low-power modes:
|
||||
(+) Low power run mode: regulator in low power mode, limited clock frequency,
|
||||
limited number of peripherals running.
|
||||
(+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
|
||||
(+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
|
||||
limited number of peripherals running, regulator in low power mode.
|
||||
(+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
|
||||
(+) Standby mode: VCORE domain powered off
|
||||
|
||||
*** Low power run mode ***
|
||||
=========================
|
||||
[..]
|
||||
To further reduce the consumption when the system is in Run mode, the regulator can be
|
||||
configured in low power mode. In this mode, the system frequency should not exceed
|
||||
MSI frequency range1.
|
||||
In Low power run mode, all I/O pins keep the same state as in Run mode.
|
||||
|
||||
(+) Entry:
|
||||
(++) VCORE in range2
|
||||
(++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1.
|
||||
(++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
|
||||
function.
|
||||
(+) Exit:
|
||||
(++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
|
||||
function.
|
||||
(++) Increase the system frequency if needed.
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Low power sleep mode ***
|
||||
============================
|
||||
[..]
|
||||
(+) Entry:
|
||||
The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
|
||||
functions with
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
(+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register.
|
||||
This reduces power consumption but increases the wake-up time.
|
||||
|
||||
(+) Exit:
|
||||
(++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
|
||||
acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
|
||||
from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
|
||||
the MCU exits Sleep mode as soon as an event occurs.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..]
|
||||
The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
|
||||
clock gating. The voltage regulator can be configured either in normal or low-power mode.
|
||||
In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
|
||||
the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
|
||||
To get the lowest consumption in Stop mode, the internal Flash memory also enters low
|
||||
power mode. When the Flash memory is in power-down mode, an additional startup delay is
|
||||
incurred when waking up from Stop mode.
|
||||
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
|
||||
sensor can be switched off before entering Stop mode. They can be switched on again by
|
||||
software after exiting Stop mode using the ULP bit in the PWR_CR register.
|
||||
In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
|
||||
(+) Entry:
|
||||
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI )
|
||||
function with:
|
||||
(++) Main regulator ON.
|
||||
(++) Low Power regulator ON.
|
||||
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
(+) Exit:
|
||||
(++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..]
|
||||
The Standby mode allows to achieve the lowest power consumption. It is based on the
|
||||
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is
|
||||
consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
|
||||
also switched off. SRAM and register contents are lost except for the RTC registers, RTC
|
||||
backup registers and Standby circuitry.
|
||||
|
||||
To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
|
||||
sensor can be switched off before entering the Standby mode. They can be switched
|
||||
on again by software after exiting the Standby mode.
|
||||
function.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]
|
||||
The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT()
|
||||
function
|
||||
(+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
|
||||
and HAL_RTC_SetTime() functions.
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and
|
||||
Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT()
|
||||
or HAL_RTCEx_SetTimeStamp_IT() functions.
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and
|
||||
Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function.
|
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer()
|
||||
function.
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Standby mode
|
||||
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function.
|
||||
(+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init()
|
||||
and HAL_RTC_SetTime() functions.
|
||||
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to
|
||||
detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT()
|
||||
or HAL_RTCEx_SetTamper_IT()functions.
|
||||
(++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
|
||||
(+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event
|
||||
using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
|
||||
event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the
|
||||
selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using
|
||||
the COMP functions.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
|
||||
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
|
||||
* information for the PVD.
|
||||
* @note Refer to the electrical characteristics of your device datasheet for
|
||||
* more details about the voltage threshold corresponding to each
|
||||
* detection level.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
|
||||
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
|
||||
|
||||
/* Set PLS[7:5] bits according to PVDLevel value */
|
||||
MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
|
||||
|
||||
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_IT();
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE();
|
||||
|
||||
/* Configure interrupt mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_IT();
|
||||
}
|
||||
|
||||
/* Configure event mode */
|
||||
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
|
||||
}
|
||||
|
||||
/* Configure the edge */
|
||||
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
|
||||
{
|
||||
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnablePVD(void)
|
||||
{
|
||||
/* Enable the power voltage detector */
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Power Voltage Detector(PVD).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisablePVD(void)
|
||||
{
|
||||
/* Disable the power voltage detector */
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Enable the EWUPx pin */
|
||||
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the WakeUp PINx functionality.
|
||||
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_WAKEUP_PIN1
|
||||
* @arg PWR_WAKEUP_PIN2
|
||||
* @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
|
||||
/* Disable the EWUPx pin */
|
||||
*(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param Regulator: Specifies the regulator state in SLEEP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
|
||||
* @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
|
||||
* When WFI entry is used, tick interrupt have to be disabled if not desired as
|
||||
* the interrupt wake up source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
|
||||
|
||||
/* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Stop mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by using an interrupt or a wakeup event,
|
||||
* MSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param Regulator: Specifies the regulator state in Stop mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
|
||||
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
|
||||
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
|
||||
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
|
||||
|
||||
/* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
|
||||
MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* Select Stop mode entry --------------------------------------------------*/
|
||||
if(STOPEntry == PWR_STOPENTRY_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__SEV();
|
||||
__WFE();
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Standby mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* - Reset pad (still available)
|
||||
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
|
||||
* Alarm out, or RTC clock calibration out.
|
||||
* - WKUP pin 1 (PA0) if enabled.
|
||||
* - WKUP pin 2 (PC13) if enabled.
|
||||
* - WKUP pin 3 (PE6) if enabled.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Select Standby mode */
|
||||
SET_BIT(PWR->CR, PWR_CR_PDDS);
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM)
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
|
||||
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* Setting this bit is useful when the processor is expected to run only on
|
||||
* interruptions handling.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSleepOnExit(void)
|
||||
{
|
||||
/* Set SLEEPONEXIT bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
|
||||
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
|
||||
* re-enters SLEEP mode when an interruption handling is over.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSleepOnExit(void)
|
||||
{
|
||||
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables CORTEX M3 SEVONPEND bit.
|
||||
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_EnableSEVOnPend(void)
|
||||
{
|
||||
/* Set SEVONPEND bit of Cortex System Control Register */
|
||||
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disables CORTEX M3 SEVONPEND bit.
|
||||
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
|
||||
* WFE to wake up when an interrupt moves from inactive to pended.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_DisableSEVOnPend(void)
|
||||
{
|
||||
/* Clear SEVONPEND bit of Cortex System Control Register */
|
||||
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function handles the PWR PVD interrupt request.
|
||||
* @note This API should be called under the PVD_IRQHandler().
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWR_PVD_IRQHandler(void)
|
||||
{
|
||||
/* Check PWR exti flag */
|
||||
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
|
||||
{
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback();
|
||||
|
||||
/* Clear PWR Exti pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PWR PVD interrupt callback
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_PWR_PVDCallback(void)
|
||||
{
|
||||
/* NOTE : This function Should not be modified, when the callback is needed,
|
||||
the HAL_PWR_PVDCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
@@ -0,0 +1,161 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_pwr_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended PWR HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + Extended Initialization and de-initialization functions
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx PWREx
|
||||
* @brief PWR HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_PWR_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Peripheral extended features functions #####
|
||||
===============================================================================
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Return Voltage Scaling Range.
|
||||
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or PWR_REGULATOR_VOLTAGE_SCALE3)
|
||||
*/
|
||||
uint32_t HAL_PWREx_GetVoltageRange(void)
|
||||
{
|
||||
return (PWR->CR & PWR_CR_VOS);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enables the Fast WakeUp from Ultra Low Power mode.
|
||||
* @note This bit works in conjunction with ULP bit.
|
||||
* Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when
|
||||
* exiting from low power mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableFastWakeUp(void)
|
||||
{
|
||||
/* Enable the fast wake up */
|
||||
*(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Fast WakeUp from Ultra Low Power mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableFastWakeUp(void)
|
||||
{
|
||||
/* Disable the fast wake up */
|
||||
*(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Ultra Low Power mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableUltraLowPower(void)
|
||||
{
|
||||
/* Enable the Ultra Low Power mode */
|
||||
*(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the Ultra Low Power mode
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_DisableUltraLowPower(void)
|
||||
{
|
||||
/* Disable the Ultra Low Power mode */
|
||||
*(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters the Low Power Run mode.
|
||||
* @note Low power run mode can only be entered when VCORE is in range 2.
|
||||
* In addition, the dynamic voltage scaling must not be used when Low
|
||||
* power run mode is selected. Only Stop and Sleep modes with regulator
|
||||
* configured in Low power mode is allowed when Low power run mode is
|
||||
* selected.
|
||||
* @note In Low power run mode, all I/O pins keep the same state as in Run mode.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_PWREx_EnableLowPowerRunMode(void)
|
||||
{
|
||||
/* Enters the Low Power Run mode */
|
||||
*(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE;
|
||||
*(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Exits the Low Power Run mode.
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
|
||||
{
|
||||
/* Exits the Low Power Run mode */
|
||||
*(__IO uint32_t *) CR_LPRUN_BB = (uint32_t)DISABLE;
|
||||
*(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE;
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_PWR_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,440 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_rcc_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief Extended RCC HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities RCC extension peripheral:
|
||||
* + Extended Peripheral Control functions
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright(c) 2017 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_RCC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup RCCEx RCCEx
|
||||
* @brief RCC Extension HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
|
||||
* @brief Extended Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended Peripheral Control functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to control the RCC Clocks
|
||||
frequencies.
|
||||
[..]
|
||||
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
|
||||
select the RTC clock source; in this case the Backup domain will be reset in
|
||||
order to modify the RTC Clock source, as consequence RTC registers (including
|
||||
the backup registers) are set to their reset values.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the RCC extended peripherals clocks according to the specified
|
||||
* parameters in the RCC_PeriphCLKInitTypeDef.
|
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
|
||||
* @retval HAL status
|
||||
* @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
|
||||
* to possibly update HSE divider.
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t temp_reg;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
||||
|
||||
/*------------------------------- RTC/LCD Configuration ------------------------*/
|
||||
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
||||
#if defined(LCD)
|
||||
|| (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
|
||||
#endif /* LCD */
|
||||
)
|
||||
{
|
||||
/* check for RTC Parameters used to output RTCCLK */
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
||||
{
|
||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
||||
}
|
||||
|
||||
#if defined(LCD)
|
||||
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
|
||||
{
|
||||
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
|
||||
}
|
||||
#endif /* LCD */
|
||||
|
||||
FlagStatus pwrclkchanged = RESET;
|
||||
|
||||
/* As soon as function is called to change RTC clock source, activation of the
|
||||
power domain is done. */
|
||||
/* Requires to enable write access to Backup Domain of necessary */
|
||||
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_ENABLE();
|
||||
pwrclkchanged = SET;
|
||||
}
|
||||
|
||||
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||
{
|
||||
/* Enable write access to Backup domain */
|
||||
SET_BIT(PWR->CR, PWR_CR_DBP);
|
||||
|
||||
/* Wait for Backup domain Write protection disable */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
|
||||
{
|
||||
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
|
||||
temp_reg = (RCC->CR & RCC_CR_RTCPRE);
|
||||
if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
|
||||
#if defined (LCD)
|
||||
|| (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
|
||||
#endif /* LCD */
|
||||
)
|
||||
{ /* Check HSE State */
|
||||
if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
|
||||
{
|
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
|
||||
{
|
||||
/* To update HSE divider, first switch-OFF HSE clock oscillator*/
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
|
||||
temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
|
||||
|
||||
if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
|
||||
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
|
||||
#if defined(LCD)
|
||||
|| ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
|
||||
&& (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
|
||||
#endif /* LCD */
|
||||
))
|
||||
{
|
||||
/* Store the content of CSR register before the reset of Backup Domain */
|
||||
temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
|
||||
|
||||
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
||||
__HAL_RCC_BACKUPRESET_FORCE();
|
||||
__HAL_RCC_BACKUPRESET_RELEASE();
|
||||
|
||||
/* Restore the Content of CSR register */
|
||||
RCC->CSR = temp_reg;
|
||||
|
||||
/* Wait for LSERDY if LSE was enabled */
|
||||
if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
|
||||
{
|
||||
/* Get Start Tick */
|
||||
tickstart = HAL_GetTick();
|
||||
|
||||
/* Wait till LSE is ready */
|
||||
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
|
||||
{
|
||||
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
|
||||
{
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
||||
|
||||
/* Require to disable power clock if necessary */
|
||||
if(pwrclkchanged == SET)
|
||||
{
|
||||
__HAL_RCC_PWR_CLK_DISABLE();
|
||||
}
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the PeriphClkInit according to the internal RCC configuration registers.
|
||||
* @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
|
||||
* returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
||||
{
|
||||
uint32_t srcclk;
|
||||
|
||||
/* Set all possible values for the extended clock type parameter------------*/
|
||||
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
|
||||
#if defined(LCD)
|
||||
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
|
||||
#endif /* LCD */
|
||||
|
||||
/* Get the RTC/LCD configuration -----------------------------------------------*/
|
||||
srcclk = __HAL_RCC_GET_RTC_SOURCE();
|
||||
if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
|
||||
{
|
||||
/* Source clock is LSE or LSI*/
|
||||
PeriphClkInit->RTCClockSelection = srcclk;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Source clock is HSE. Need to get the prescaler value*/
|
||||
PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
|
||||
}
|
||||
#if defined(LCD)
|
||||
PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
|
||||
#endif /* LCD */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the peripheral clock frequency
|
||||
* @note Return 0 if peripheral clock is unknown
|
||||
* @param PeriphClk Peripheral clock identifier
|
||||
* This parameter can be one of the following values:
|
||||
* @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock
|
||||
* @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*)
|
||||
* @note (*) means that this peripheral is not present on all the devices
|
||||
* @retval Frequency in Hz (0: means that no available frequency for the peripheral)
|
||||
*/
|
||||
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
|
||||
{
|
||||
uint32_t frequency = 0;
|
||||
uint32_t srcclk;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
|
||||
|
||||
switch (PeriphClk)
|
||||
{
|
||||
case RCC_PERIPHCLK_RTC:
|
||||
#if defined(LCD)
|
||||
case RCC_PERIPHCLK_LCD:
|
||||
#endif /* LCD */
|
||||
{
|
||||
/* Get the current RTC source */
|
||||
srcclk = __HAL_RCC_GET_RTC_SOURCE();
|
||||
|
||||
/* Check if LSE is ready if RTC clock selection is LSE */
|
||||
if (srcclk == RCC_RTCCLKSOURCE_LSE)
|
||||
{
|
||||
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY))
|
||||
{
|
||||
frequency = LSE_VALUE;
|
||||
}
|
||||
}
|
||||
/* Check if LSI is ready if RTC clock selection is LSI */
|
||||
else if (srcclk == RCC_RTCCLKSOURCE_LSI)
|
||||
{
|
||||
if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY))
|
||||
{
|
||||
frequency = LSI_VALUE;
|
||||
}
|
||||
}
|
||||
/* Check if HSE is ready and if RTC clock selection is HSE */
|
||||
else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX)
|
||||
{
|
||||
if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
|
||||
{
|
||||
/* Get the current HSE clock divider */
|
||||
switch (__HAL_RCC_GET_RTC_HSE_PRESCALER())
|
||||
{
|
||||
case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */
|
||||
{
|
||||
frequency = HSE_VALUE / 16U;
|
||||
break;
|
||||
}
|
||||
case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */
|
||||
{
|
||||
frequency = HSE_VALUE / 8U;
|
||||
break;
|
||||
}
|
||||
case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */
|
||||
{
|
||||
frequency = HSE_VALUE / 4U;
|
||||
break;
|
||||
}
|
||||
default: /* HSE DIV2 has been selected */
|
||||
{
|
||||
frequency = HSE_VALUE / 2U;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* No clock source, frequency default init at 0 */
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return(frequency);
|
||||
}
|
||||
|
||||
#if defined(RCC_LSECSS_SUPPORT)
|
||||
/**
|
||||
* @brief Enables the LSE Clock Security System.
|
||||
* @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
|
||||
* to the RTC but no hardware action is made to the registers.
|
||||
* In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
|
||||
* the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
|
||||
* The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
|
||||
* (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
|
||||
* RTCSEL), or take any required action to secure the application.
|
||||
* @note LSE CSS available only for high density and medium+ devices
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_EnableLSECSS(void)
|
||||
{
|
||||
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the LSE Clock Security System.
|
||||
* @note Once enabled this bit cannot be disabled, except after an LSE failure detection
|
||||
* (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
|
||||
* Reset by power on reset and RTC software reset (RTCRST bit).
|
||||
* @note LSE CSS available only for high density and medium+ devices
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_DisableLSECSS(void)
|
||||
{
|
||||
/* Disable LSE CSS */
|
||||
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
|
||||
|
||||
/* Disable LSE CSS IT */
|
||||
__HAL_RCC_DISABLE_IT(RCC_IT_LSECSS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the LSE Clock Security System IT & corresponding EXTI line.
|
||||
* @note LSE Clock Security System IT is mapped on RTC EXTI line 19
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_EnableLSECSS_IT(void)
|
||||
{
|
||||
/* Enable LSE CSS */
|
||||
*(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
|
||||
|
||||
/* Enable LSE CSS IT */
|
||||
__HAL_RCC_ENABLE_IT(RCC_IT_LSECSS);
|
||||
|
||||
/* Enable IT on EXTI Line 19 */
|
||||
__HAL_RCC_LSECSS_EXTI_ENABLE_IT();
|
||||
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle the RCC LSE Clock Security System interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_RCCEx_LSECSS_IRQHandler(void)
|
||||
{
|
||||
/* Check RCC LSE CSSF flag */
|
||||
if(__HAL_RCC_GET_IT(RCC_IT_LSECSS))
|
||||
{
|
||||
/* RCC LSE Clock Security System interrupt user callback */
|
||||
HAL_RCCEx_LSECSS_Callback();
|
||||
|
||||
/* Clear RCC LSE CSS pending bit */
|
||||
__HAL_RCC_CLEAR_IT(RCC_IT_LSECSS);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief RCCEx LSE Clock Security System interrupt callback.
|
||||
* @retval none
|
||||
*/
|
||||
__weak void HAL_RCCEx_LSECSS_Callback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file
|
||||
*/
|
||||
}
|
||||
#endif /* RCC_LSECSS_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif /* HAL_RCC_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,227 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_hal_tim_ex.c
|
||||
* @author MCD Application Team
|
||||
* @brief TIM HAL module driver.
|
||||
* This file provides firmware functions to manage the following
|
||||
* functionalities of the Timer Extended peripheral:
|
||||
* + Time Master and Slave synchronization configuration
|
||||
* + Time OCRef clear configuration
|
||||
* + Timer remapping capabilities configuration
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### TIMER Extended features #####
|
||||
==============================================================================
|
||||
[..]
|
||||
The Timer Extended features include:
|
||||
(#) Synchronization circuit to control the timer with external signals and to
|
||||
interconnect several timers together.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.</center></h2>
|
||||
*
|
||||
* This software component is licensed by ST under BSD 3-Clause license,
|
||||
* the "License"; You may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at:
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_hal.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TIMEx TIMEx
|
||||
* @brief TIM Extended HAL module driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef HAL_TIM_MODULE_ENABLED
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
|
||||
* @{
|
||||
*/
|
||||
/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
|
||||
* @brief Peripheral Control functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
This section provides functions allowing to:
|
||||
(+) Configure Master synchronization.
|
||||
(+) Configure timer remapping capabilities.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the TIM in master mode.
|
||||
* @param htim TIM handle.
|
||||
* @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
|
||||
* contains the selected trigger output (TRGO) and the Master/Slave
|
||||
* mode.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
||||
TIM_MasterConfigTypeDef *sMasterConfig)
|
||||
{
|
||||
uint32_t tmpcr2;
|
||||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
||||
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
||||
|
||||
/* Check input state */
|
||||
__HAL_LOCK(htim);
|
||||
|
||||
/* Change the handler state */
|
||||
htim->State = HAL_TIM_STATE_BUSY;
|
||||
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = htim->Instance->CR2;
|
||||
|
||||
/* Get the TIMx SMCR register value */
|
||||
tmpsmcr = htim->Instance->SMCR;
|
||||
|
||||
/* Reset the MMS Bits */
|
||||
tmpcr2 &= ~TIM_CR2_MMS;
|
||||
/* Select the TRGO source */
|
||||
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
||||
|
||||
/* Update TIMx CR2 */
|
||||
htim->Instance->CR2 = tmpcr2;
|
||||
|
||||
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Reset the MSM Bit */
|
||||
tmpsmcr &= ~TIM_SMCR_MSM;
|
||||
/* Set master mode */
|
||||
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
||||
|
||||
/* Update TIMx SMCR */
|
||||
htim->Instance->SMCR = tmpsmcr;
|
||||
}
|
||||
|
||||
/* Change the htim state */
|
||||
htim->State = HAL_TIM_STATE_READY;
|
||||
|
||||
__HAL_UNLOCK(htim);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the TIMx Remapping input capabilities.
|
||||
* @param htim TIM handle.
|
||||
* @param Remap specifies the TIM remapping source.
|
||||
*
|
||||
* For TIM2, the parameter can have the following values:(see note)
|
||||
* @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC
|
||||
* @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO
|
||||
*
|
||||
* For TIM3, the parameter can have the following values:(see note)
|
||||
* @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC
|
||||
* @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO
|
||||
*
|
||||
* For TIM9, the parameter is a combination of 2 fields (field1 | field2):
|
||||
*
|
||||
* field1 can have the following values:(see note)
|
||||
* @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO
|
||||
* @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O
|
||||
*
|
||||
* field2 can have the following values:
|
||||
* @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO
|
||||
* @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock
|
||||
* @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO
|
||||
* @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO
|
||||
*
|
||||
* For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
||||
*
|
||||
* field1 can have the following values:(see note)
|
||||
* @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP
|
||||
* @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI
|
||||
*
|
||||
* field2 can have the following values:(see note)
|
||||
* @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock
|
||||
* @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO
|
||||
* @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock
|
||||
* @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock
|
||||
* @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt
|
||||
*
|
||||
* For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3):
|
||||
*
|
||||
* field1 can have the following values:(see note)
|
||||
* @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP
|
||||
* @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI
|
||||
*
|
||||
* field2 can have the following values:(see note)
|
||||
* @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock
|
||||
* @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO
|
||||
*
|
||||
* field3 can have the following values:
|
||||
* @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO
|
||||
* @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock
|
||||
* @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock
|
||||
* @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO
|
||||
*
|
||||
* @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices.
|
||||
*
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
||||
{
|
||||
__HAL_LOCK(htim);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_TIM_REMAP(htim->Instance, Remap));
|
||||
|
||||
/* Set the Timer remapping configuration */
|
||||
WRITE_REG(htim->Instance->OR, Remap);
|
||||
|
||||
__HAL_UNLOCK(htim);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
#endif /* HAL_TIM_MODULE_ENABLED */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user