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stm32l1xx_hal_i2s.c 58KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32l1xx_hal_i2s.c
  4. * @author MCD Application Team
  5. * @brief I2S HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Integrated Interchip Sound (I2S) peripheral:
  8. * + Initialization and de-initialization functions
  9. * + IO operation functions
  10. * + Peripheral State and Errors functions
  11. @verbatim
  12. ===============================================================================
  13. ##### How to use this driver #####
  14. ===============================================================================
  15. [..]
  16. The I2S HAL driver can be used as follow:
  17. (#) Declare a I2S_HandleTypeDef handle structure.
  18. (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
  19. (##) Enable the SPIx interface clock.
  20. (##) I2S pins configuration:
  21. (+++) Enable the clock for the I2S GPIOs.
  22. (+++) Configure these I2S pins as alternate function pull-up.
  23. (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
  24. and HAL_I2S_Receive_IT() APIs).
  25. (+++) Configure the I2Sx interrupt priority.
  26. (+++) Enable the NVIC I2S IRQ handle.
  27. (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
  28. and HAL_I2S_Receive_DMA() APIs:
  29. (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel.
  30. (+++) Enable the DMAx interface clock.
  31. (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
  32. (+++) Configure the DMA Tx/Rx Stream/Channel.
  33. (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle.
  34. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the
  35. DMA Tx/Rx Stream/Channel.
  36. (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
  37. using HAL_I2S_Init() function.
  38. -@- The specific I2S interrupts (Transmission complete interrupt,
  39. RXNE interrupt and Error Interrupts) will be managed using the macros
  40. __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
  41. -@- Make sure that either:
  42. (+@) External clock source is configured after setting correctly
  43. the define constant HSE_VALUE in the stm32l1xx_hal_conf.h file.
  44. (#) Three mode of operations are available within this driver :
  45. *** Polling mode IO operation ***
  46. =================================
  47. [..]
  48. (+) Send an amount of data in blocking mode using HAL_I2S_Transmit()
  49. (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
  50. *** Interrupt mode IO operation ***
  51. ===================================
  52. [..]
  53. (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT()
  54. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  55. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  56. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  57. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  58. (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT()
  59. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  60. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  61. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  62. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  63. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  64. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  65. *** DMA mode IO operation ***
  66. ==============================
  67. [..]
  68. (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA()
  69. (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
  70. add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
  71. (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
  72. add his own code by customization of function pointer HAL_I2S_TxCpltCallback
  73. (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA()
  74. (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
  75. add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
  76. (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
  77. add his own code by customization of function pointer HAL_I2S_RxCpltCallback
  78. (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
  79. add his own code by customization of function pointer HAL_I2S_ErrorCallback
  80. (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
  81. (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
  82. (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
  83. *** I2S HAL driver macros list ***
  84. ===================================
  85. [..]
  86. Below the list of most used macros in I2S HAL driver.
  87. (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode)
  88. (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
  89. (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
  90. (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
  91. (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
  92. [..]
  93. (@) You can refer to the I2S HAL driver header file for more useful macros
  94. *** I2S HAL driver macros list ***
  95. ===================================
  96. [..]
  97. Callback registration:
  98. (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U
  99. allows the user to configure dynamically the driver callbacks.
  100. Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback.
  101. Function HAL_I2S_RegisterCallback() allows to register following callbacks:
  102. (+) TxCpltCallback : I2S Tx Completed callback
  103. (+) RxCpltCallback : I2S Rx Completed callback
  104. (+) TxHalfCpltCallback : I2S Tx Half Completed callback
  105. (+) RxHalfCpltCallback : I2S Rx Half Completed callback
  106. (+) ErrorCallback : I2S Error callback
  107. (+) MspInitCallback : I2S Msp Init callback
  108. (+) MspDeInitCallback : I2S Msp DeInit callback
  109. This function takes as parameters the HAL peripheral handle, the Callback ID
  110. and a pointer to the user callback function.
  111. (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default
  112. weak function.
  113. HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle,
  114. and the Callback ID.
  115. This function allows to reset following callbacks:
  116. (+) TxCpltCallback : I2S Tx Completed callback
  117. (+) RxCpltCallback : I2S Rx Completed callback
  118. (+) TxHalfCpltCallback : I2S Tx Half Completed callback
  119. (+) RxHalfCpltCallback : I2S Rx Half Completed callback
  120. (+) ErrorCallback : I2S Error callback
  121. (+) MspInitCallback : I2S Msp Init callback
  122. (+) MspDeInitCallback : I2S Msp DeInit callback
  123. By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET
  124. all callbacks are set to the corresponding weak functions:
  125. examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback().
  126. Exception done for MspInit and MspDeInit functions that are
  127. reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when
  128. these callbacks are null (not registered beforehand).
  129. If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit()
  130. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
  131. Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only.
  132. Exception done MspInit/MspDeInit functions that can be registered/unregistered
  133. in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state,
  134. thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
  135. Then, the user first registers the MspInit/MspDeInit user callbacks
  136. using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit()
  137. or HAL_I2S_Init() function.
  138. When The compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or
  139. not defined, the callback registering feature is not available
  140. and weak (surcharged) callbacks are used.
  141. @endverbatim
  142. ******************************************************************************
  143. * @attention
  144. *
  145. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  146. * All rights reserved.</center></h2>
  147. *
  148. * This software component is licensed by ST under BSD 3-Clause license,
  149. * the "License"; You may not use this file except in compliance with the
  150. * License. You may obtain a copy of the License at:
  151. * opensource.org/licenses/BSD-3-Clause
  152. *
  153. ******************************************************************************
  154. */
  155. /* Includes ------------------------------------------------------------------*/
  156. #include "stm32l1xx_hal.h"
  157. #ifdef HAL_I2S_MODULE_ENABLED
  158. #if defined(SPI_I2S_SUPPORT)
  159. /** @addtogroup STM32L1xx_HAL_Driver
  160. * @{
  161. */
  162. /** @defgroup I2S I2S
  163. * @brief I2S HAL module driver
  164. * @{
  165. */
  166. /* Private typedef -----------------------------------------------------------*/
  167. /* Private define ------------------------------------------------------------*/
  168. /* Private macro -------------------------------------------------------------*/
  169. /* Private variables ---------------------------------------------------------*/
  170. /* Private function prototypes -----------------------------------------------*/
  171. /** @defgroup I2S_Private_Functions I2S Private Functions
  172. * @{
  173. */
  174. static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
  175. static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
  176. static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
  177. static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
  178. static void I2S_DMAError(DMA_HandleTypeDef *hdma);
  179. static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
  180. static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
  181. static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
  182. uint32_t Timeout);
  183. /**
  184. * @}
  185. */
  186. /* Exported functions ---------------------------------------------------------*/
  187. /** @defgroup I2S_Exported_Functions I2S Exported Functions
  188. * @{
  189. */
  190. /** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
  191. * @brief Initialization and Configuration functions
  192. *
  193. @verbatim
  194. ===============================================================================
  195. ##### Initialization and de-initialization functions #####
  196. ===============================================================================
  197. [..] This subsection provides a set of functions allowing to initialize and
  198. de-initialize the I2Sx peripheral in simplex mode:
  199. (+) User must Implement HAL_I2S_MspInit() function in which he configures
  200. all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
  201. (+) Call the function HAL_I2S_Init() to configure the selected device with
  202. the selected configuration:
  203. (++) Mode
  204. (++) Standard
  205. (++) Data Format
  206. (++) MCLK Output
  207. (++) Audio frequency
  208. (++) Polarity
  209. (+) Call the function HAL_I2S_DeInit() to restore the default configuration
  210. of the selected I2Sx peripheral.
  211. @endverbatim
  212. * @{
  213. */
  214. /**
  215. * @brief Initializes the I2S according to the specified parameters
  216. * in the I2S_InitTypeDef and create the associated handle.
  217. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  218. * the configuration information for I2S module
  219. * @retval HAL status
  220. */
  221. HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
  222. {
  223. uint32_t i2sdiv;
  224. uint32_t i2sodd;
  225. uint32_t packetlength;
  226. uint32_t tmp;
  227. uint32_t i2sclk;
  228. /* Check the I2S handle allocation */
  229. if (hi2s == NULL)
  230. {
  231. return HAL_ERROR;
  232. }
  233. /* Check the I2S parameters */
  234. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  235. assert_param(IS_I2S_MODE(hi2s->Init.Mode));
  236. assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
  237. assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
  238. assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
  239. assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
  240. assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));
  241. if (hi2s->State == HAL_I2S_STATE_RESET)
  242. {
  243. /* Allocate lock resource and initialize it */
  244. hi2s->Lock = HAL_UNLOCKED;
  245. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  246. /* Init the I2S Callback settings */
  247. hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
  248. hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
  249. hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
  250. hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
  251. hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
  252. if (hi2s->MspInitCallback == NULL)
  253. {
  254. hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
  255. }
  256. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  257. hi2s->MspInitCallback(hi2s);
  258. #else
  259. /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
  260. HAL_I2S_MspInit(hi2s);
  261. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  262. }
  263. hi2s->State = HAL_I2S_STATE_BUSY;
  264. /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
  265. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  266. CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \
  267. SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  268. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD));
  269. hi2s->Instance->I2SPR = 0x0002U;
  270. /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/
  271. /* If the requested audio frequency is not the default, compute the prescaler */
  272. if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT)
  273. {
  274. /* Check the frame length (For the Prescaler computing) ********************/
  275. if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
  276. {
  277. /* Packet length is 16 bits */
  278. packetlength = 16U;
  279. }
  280. else
  281. {
  282. /* Packet length is 32 bits */
  283. packetlength = 32U;
  284. }
  285. /* I2S standard */
  286. if (hi2s->Init.Standard <= I2S_STANDARD_LSB)
  287. {
  288. /* In I2S standard packet lenght is multiplied by 2 */
  289. packetlength = packetlength * 2U;
  290. }
  291. /* Get the source clock value: based on System Clock value */
  292. i2sclk = HAL_RCC_GetSysClockFreq();
  293. /* Compute the Real divider depending on the MCLK output state, with a floating point */
  294. if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
  295. {
  296. /* MCLK output is enabled */
  297. if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B)
  298. {
  299. tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  300. }
  301. else
  302. {
  303. tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  304. }
  305. }
  306. else
  307. {
  308. /* MCLK output is disabled */
  309. tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U);
  310. }
  311. /* Remove the flatting point */
  312. tmp = tmp / 10U;
  313. /* Check the parity of the divider */
  314. i2sodd = (uint32_t)(tmp & (uint32_t)1U);
  315. /* Compute the i2sdiv prescaler */
  316. i2sdiv = (uint32_t)((tmp - i2sodd) / 2U);
  317. /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
  318. i2sodd = (uint32_t)(i2sodd << 8U);
  319. }
  320. else
  321. {
  322. /* Set the default values */
  323. i2sdiv = 2U;
  324. i2sodd = 0U;
  325. }
  326. /* Test if the divider is 1 or 0 or greater than 0xFF */
  327. if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
  328. {
  329. /* Set the error code and execute error callback*/
  330. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER);
  331. return HAL_ERROR;
  332. }
  333. /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
  334. /* Write to SPIx I2SPR register the computed value */
  335. hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
  336. /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
  337. /* And configure the I2S with the I2S_InitStruct values */
  338. MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
  339. SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
  340. SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \
  341. SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \
  342. (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \
  343. hi2s->Init.Standard | hi2s->Init.DataFormat | \
  344. hi2s->Init.CPOL));
  345. #if defined(SPI_I2SCFGR_ASTRTEN)
  346. if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)))
  347. {
  348. /* Write to SPIx I2SCFGR */
  349. SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
  350. }
  351. #endif /* SPI_I2SCFGR_ASTRTEN */
  352. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  353. hi2s->State = HAL_I2S_STATE_READY;
  354. return HAL_OK;
  355. }
  356. /**
  357. * @brief DeInitializes the I2S peripheral
  358. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  359. * the configuration information for I2S module
  360. * @retval HAL status
  361. */
  362. HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
  363. {
  364. /* Check the I2S handle allocation */
  365. if (hi2s == NULL)
  366. {
  367. return HAL_ERROR;
  368. }
  369. /* Check the parameters */
  370. assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
  371. hi2s->State = HAL_I2S_STATE_BUSY;
  372. /* Disable the I2S Peripheral Clock */
  373. __HAL_I2S_DISABLE(hi2s);
  374. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  375. if (hi2s->MspDeInitCallback == NULL)
  376. {
  377. hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
  378. }
  379. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  380. hi2s->MspDeInitCallback(hi2s);
  381. #else
  382. /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
  383. HAL_I2S_MspDeInit(hi2s);
  384. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  385. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  386. hi2s->State = HAL_I2S_STATE_RESET;
  387. /* Release Lock */
  388. __HAL_UNLOCK(hi2s);
  389. return HAL_OK;
  390. }
  391. /**
  392. * @brief I2S MSP Init
  393. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  394. * the configuration information for I2S module
  395. * @retval None
  396. */
  397. __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
  398. {
  399. /* Prevent unused argument(s) compilation warning */
  400. UNUSED(hi2s);
  401. /* NOTE : This function Should not be modified, when the callback is needed,
  402. the HAL_I2S_MspInit could be implemented in the user file
  403. */
  404. }
  405. /**
  406. * @brief I2S MSP DeInit
  407. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  408. * the configuration information for I2S module
  409. * @retval None
  410. */
  411. __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
  412. {
  413. /* Prevent unused argument(s) compilation warning */
  414. UNUSED(hi2s);
  415. /* NOTE : This function Should not be modified, when the callback is needed,
  416. the HAL_I2S_MspDeInit could be implemented in the user file
  417. */
  418. }
  419. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  420. /**
  421. * @brief Register a User I2S Callback
  422. * To be used instead of the weak predefined callback
  423. * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
  424. * the configuration information for the specified I2S.
  425. * @param CallbackID ID of the callback to be registered
  426. * @param pCallback pointer to the Callback function
  427. * @retval HAL status
  428. */
  429. HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
  430. pI2S_CallbackTypeDef pCallback)
  431. {
  432. HAL_StatusTypeDef status = HAL_OK;
  433. if (pCallback == NULL)
  434. {
  435. /* Update the error code */
  436. hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK;
  437. return HAL_ERROR;
  438. }
  439. /* Process locked */
  440. __HAL_LOCK(hi2s);
  441. if (HAL_I2S_STATE_READY == hi2s->State)
  442. {
  443. switch (CallbackID)
  444. {
  445. case HAL_I2S_TX_COMPLETE_CB_ID :
  446. hi2s->TxCpltCallback = pCallback;
  447. break;
  448. case HAL_I2S_RX_COMPLETE_CB_ID :
  449. hi2s->RxCpltCallback = pCallback;
  450. break;
  451. case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
  452. hi2s->TxHalfCpltCallback = pCallback;
  453. break;
  454. case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
  455. hi2s->RxHalfCpltCallback = pCallback;
  456. break;
  457. case HAL_I2S_ERROR_CB_ID :
  458. hi2s->ErrorCallback = pCallback;
  459. break;
  460. case HAL_I2S_MSPINIT_CB_ID :
  461. hi2s->MspInitCallback = pCallback;
  462. break;
  463. case HAL_I2S_MSPDEINIT_CB_ID :
  464. hi2s->MspDeInitCallback = pCallback;
  465. break;
  466. default :
  467. /* Update the error code */
  468. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  469. /* Return error status */
  470. status = HAL_ERROR;
  471. break;
  472. }
  473. }
  474. else if (HAL_I2S_STATE_RESET == hi2s->State)
  475. {
  476. switch (CallbackID)
  477. {
  478. case HAL_I2S_MSPINIT_CB_ID :
  479. hi2s->MspInitCallback = pCallback;
  480. break;
  481. case HAL_I2S_MSPDEINIT_CB_ID :
  482. hi2s->MspDeInitCallback = pCallback;
  483. break;
  484. default :
  485. /* Update the error code */
  486. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  487. /* Return error status */
  488. status = HAL_ERROR;
  489. break;
  490. }
  491. }
  492. else
  493. {
  494. /* Update the error code */
  495. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  496. /* Return error status */
  497. status = HAL_ERROR;
  498. }
  499. /* Release Lock */
  500. __HAL_UNLOCK(hi2s);
  501. return status;
  502. }
  503. /**
  504. * @brief Unregister an I2S Callback
  505. * I2S callback is redirected to the weak predefined callback
  506. * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains
  507. * the configuration information for the specified I2S.
  508. * @param CallbackID ID of the callback to be unregistered
  509. * @retval HAL status
  510. */
  511. HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID)
  512. {
  513. HAL_StatusTypeDef status = HAL_OK;
  514. /* Process locked */
  515. __HAL_LOCK(hi2s);
  516. if (HAL_I2S_STATE_READY == hi2s->State)
  517. {
  518. switch (CallbackID)
  519. {
  520. case HAL_I2S_TX_COMPLETE_CB_ID :
  521. hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */
  522. break;
  523. case HAL_I2S_RX_COMPLETE_CB_ID :
  524. hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */
  525. break;
  526. case HAL_I2S_TX_HALF_COMPLETE_CB_ID :
  527. hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */
  528. break;
  529. case HAL_I2S_RX_HALF_COMPLETE_CB_ID :
  530. hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */
  531. break;
  532. case HAL_I2S_ERROR_CB_ID :
  533. hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */
  534. break;
  535. case HAL_I2S_MSPINIT_CB_ID :
  536. hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
  537. break;
  538. case HAL_I2S_MSPDEINIT_CB_ID :
  539. hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
  540. break;
  541. default :
  542. /* Update the error code */
  543. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  544. /* Return error status */
  545. status = HAL_ERROR;
  546. break;
  547. }
  548. }
  549. else if (HAL_I2S_STATE_RESET == hi2s->State)
  550. {
  551. switch (CallbackID)
  552. {
  553. case HAL_I2S_MSPINIT_CB_ID :
  554. hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */
  555. break;
  556. case HAL_I2S_MSPDEINIT_CB_ID :
  557. hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */
  558. break;
  559. default :
  560. /* Update the error code */
  561. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  562. /* Return error status */
  563. status = HAL_ERROR;
  564. break;
  565. }
  566. }
  567. else
  568. {
  569. /* Update the error code */
  570. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK);
  571. /* Return error status */
  572. status = HAL_ERROR;
  573. }
  574. /* Release Lock */
  575. __HAL_UNLOCK(hi2s);
  576. return status;
  577. }
  578. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  579. /**
  580. * @}
  581. */
  582. /** @defgroup I2S_Exported_Functions_Group2 IO operation functions
  583. * @brief Data transfers functions
  584. *
  585. @verbatim
  586. ===============================================================================
  587. ##### IO operation functions #####
  588. ===============================================================================
  589. [..]
  590. This subsection provides a set of functions allowing to manage the I2S data
  591. transfers.
  592. (#) There are two modes of transfer:
  593. (++) Blocking mode : The communication is performed in the polling mode.
  594. The status of all data processing is returned by the same function
  595. after finishing transfer.
  596. (++) No-Blocking mode : The communication is performed using Interrupts
  597. or DMA. These functions return the status of the transfer startup.
  598. The end of the data processing will be indicated through the
  599. dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
  600. using DMA mode.
  601. (#) Blocking mode functions are :
  602. (++) HAL_I2S_Transmit()
  603. (++) HAL_I2S_Receive()
  604. (#) No-Blocking mode functions with Interrupt are :
  605. (++) HAL_I2S_Transmit_IT()
  606. (++) HAL_I2S_Receive_IT()
  607. (#) No-Blocking mode functions with DMA are :
  608. (++) HAL_I2S_Transmit_DMA()
  609. (++) HAL_I2S_Receive_DMA()
  610. (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
  611. (++) HAL_I2S_TxCpltCallback()
  612. (++) HAL_I2S_RxCpltCallback()
  613. (++) HAL_I2S_ErrorCallback()
  614. @endverbatim
  615. * @{
  616. */
  617. /**
  618. * @brief Transmit an amount of data in blocking mode
  619. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  620. * the configuration information for I2S module
  621. * @param pData a 16-bit pointer to data buffer.
  622. * @param Size number of data sample to be sent:
  623. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  624. * configuration phase, the Size parameter means the number of 16-bit data length
  625. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  626. * the Size parameter means the number of 16-bit data length.
  627. * @param Timeout Timeout duration
  628. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  629. * between Master and Slave(example: audio streaming).
  630. * @retval HAL status
  631. */
  632. HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  633. {
  634. uint32_t tmpreg_cfgr;
  635. if ((pData == NULL) || (Size == 0U))
  636. {
  637. return HAL_ERROR;
  638. }
  639. /* Process Locked */
  640. __HAL_LOCK(hi2s);
  641. if (hi2s->State != HAL_I2S_STATE_READY)
  642. {
  643. __HAL_UNLOCK(hi2s);
  644. return HAL_BUSY;
  645. }
  646. /* Set state and reset error code */
  647. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  648. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  649. hi2s->pTxBuffPtr = pData;
  650. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  651. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  652. {
  653. hi2s->TxXferSize = (Size << 1U);
  654. hi2s->TxXferCount = (Size << 1U);
  655. }
  656. else
  657. {
  658. hi2s->TxXferSize = Size;
  659. hi2s->TxXferCount = Size;
  660. }
  661. tmpreg_cfgr = hi2s->Instance->I2SCFGR;
  662. /* Check if the I2S is already enabled */
  663. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  664. {
  665. /* Enable I2S peripheral */
  666. __HAL_I2S_ENABLE(hi2s);
  667. }
  668. /* Wait until TXE flag is set */
  669. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
  670. {
  671. /* Set the error code */
  672. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  673. hi2s->State = HAL_I2S_STATE_READY;
  674. __HAL_UNLOCK(hi2s);
  675. return HAL_ERROR;
  676. }
  677. while (hi2s->TxXferCount > 0U)
  678. {
  679. hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
  680. hi2s->pTxBuffPtr++;
  681. hi2s->TxXferCount--;
  682. /* Wait until TXE flag is set */
  683. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK)
  684. {
  685. /* Set the error code */
  686. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  687. hi2s->State = HAL_I2S_STATE_READY;
  688. __HAL_UNLOCK(hi2s);
  689. return HAL_ERROR;
  690. }
  691. /* Check if an underrun occurs */
  692. if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET)
  693. {
  694. /* Clear underrun flag */
  695. __HAL_I2S_CLEAR_UDRFLAG(hi2s);
  696. /* Set the error code */
  697. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  698. }
  699. }
  700. /* Check if Slave mode is selected */
  701. if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX)
  702. || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX))
  703. {
  704. /* Wait until Busy flag is reset */
  705. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK)
  706. {
  707. /* Set the error code */
  708. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  709. hi2s->State = HAL_I2S_STATE_READY;
  710. __HAL_UNLOCK(hi2s);
  711. return HAL_ERROR;
  712. }
  713. }
  714. hi2s->State = HAL_I2S_STATE_READY;
  715. __HAL_UNLOCK(hi2s);
  716. return HAL_OK;
  717. }
  718. /**
  719. * @brief Receive an amount of data in blocking mode
  720. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  721. * the configuration information for I2S module
  722. * @param pData a 16-bit pointer to data buffer.
  723. * @param Size number of data sample to be sent:
  724. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  725. * configuration phase, the Size parameter means the number of 16-bit data length
  726. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  727. * the Size parameter means the number of 16-bit data length.
  728. * @param Timeout Timeout duration
  729. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  730. * between Master and Slave(example: audio streaming).
  731. * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
  732. * in continuous way and as the I2S is not disabled at the end of the I2S transaction.
  733. * @retval HAL status
  734. */
  735. HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
  736. {
  737. uint32_t tmpreg_cfgr;
  738. if ((pData == NULL) || (Size == 0U))
  739. {
  740. return HAL_ERROR;
  741. }
  742. /* Process Locked */
  743. __HAL_LOCK(hi2s);
  744. if (hi2s->State != HAL_I2S_STATE_READY)
  745. {
  746. __HAL_UNLOCK(hi2s);
  747. return HAL_BUSY;
  748. }
  749. /* Set state and reset error code */
  750. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  751. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  752. hi2s->pRxBuffPtr = pData;
  753. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  754. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  755. {
  756. hi2s->RxXferSize = (Size << 1U);
  757. hi2s->RxXferCount = (Size << 1U);
  758. }
  759. else
  760. {
  761. hi2s->RxXferSize = Size;
  762. hi2s->RxXferCount = Size;
  763. }
  764. /* Check if the I2S is already enabled */
  765. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  766. {
  767. /* Enable I2S peripheral */
  768. __HAL_I2S_ENABLE(hi2s);
  769. }
  770. /* Check if Master Receiver mode is selected */
  771. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  772. {
  773. /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
  774. access to the SPI_SR register. */
  775. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  776. }
  777. /* Receive data */
  778. while (hi2s->RxXferCount > 0U)
  779. {
  780. /* Wait until RXNE flag is set */
  781. if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK)
  782. {
  783. /* Set the error code */
  784. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT);
  785. hi2s->State = HAL_I2S_STATE_READY;
  786. __HAL_UNLOCK(hi2s);
  787. return HAL_ERROR;
  788. }
  789. (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
  790. hi2s->pRxBuffPtr++;
  791. hi2s->RxXferCount--;
  792. /* Check if an overrun occurs */
  793. if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET)
  794. {
  795. /* Clear overrun flag */
  796. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  797. /* Set the error code */
  798. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  799. }
  800. }
  801. hi2s->State = HAL_I2S_STATE_READY;
  802. __HAL_UNLOCK(hi2s);
  803. return HAL_OK;
  804. }
  805. /**
  806. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  807. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  808. * the configuration information for I2S module
  809. * @param pData a 16-bit pointer to data buffer.
  810. * @param Size number of data sample to be sent:
  811. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  812. * configuration phase, the Size parameter means the number of 16-bit data length
  813. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  814. * the Size parameter means the number of 16-bit data length.
  815. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  816. * between Master and Slave(example: audio streaming).
  817. * @retval HAL status
  818. */
  819. HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  820. {
  821. uint32_t tmpreg_cfgr;
  822. if ((pData == NULL) || (Size == 0U))
  823. {
  824. return HAL_ERROR;
  825. }
  826. /* Process Locked */
  827. __HAL_LOCK(hi2s);
  828. if (hi2s->State != HAL_I2S_STATE_READY)
  829. {
  830. __HAL_UNLOCK(hi2s);
  831. return HAL_BUSY;
  832. }
  833. /* Set state and reset error code */
  834. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  835. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  836. hi2s->pTxBuffPtr = pData;
  837. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  838. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  839. {
  840. hi2s->TxXferSize = (Size << 1U);
  841. hi2s->TxXferCount = (Size << 1U);
  842. }
  843. else
  844. {
  845. hi2s->TxXferSize = Size;
  846. hi2s->TxXferCount = Size;
  847. }
  848. /* Enable TXE and ERR interrupt */
  849. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  850. /* Check if the I2S is already enabled */
  851. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  852. {
  853. /* Enable I2S peripheral */
  854. __HAL_I2S_ENABLE(hi2s);
  855. }
  856. __HAL_UNLOCK(hi2s);
  857. return HAL_OK;
  858. }
  859. /**
  860. * @brief Receive an amount of data in non-blocking mode with Interrupt
  861. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  862. * the configuration information for I2S module
  863. * @param pData a 16-bit pointer to the Receive data buffer.
  864. * @param Size number of data sample to be sent:
  865. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  866. * configuration phase, the Size parameter means the number of 16-bit data length
  867. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  868. * the Size parameter means the number of 16-bit data length.
  869. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  870. * between Master and Slave(example: audio streaming).
  871. * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization
  872. * between Master and Slave otherwise the I2S interrupt should be optimized.
  873. * @retval HAL status
  874. */
  875. HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  876. {
  877. uint32_t tmpreg_cfgr;
  878. if ((pData == NULL) || (Size == 0U))
  879. {
  880. return HAL_ERROR;
  881. }
  882. /* Process Locked */
  883. __HAL_LOCK(hi2s);
  884. if (hi2s->State != HAL_I2S_STATE_READY)
  885. {
  886. __HAL_UNLOCK(hi2s);
  887. return HAL_BUSY;
  888. }
  889. /* Set state and reset error code */
  890. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  891. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  892. hi2s->pRxBuffPtr = pData;
  893. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  894. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  895. {
  896. hi2s->RxXferSize = (Size << 1U);
  897. hi2s->RxXferCount = (Size << 1U);
  898. }
  899. else
  900. {
  901. hi2s->RxXferSize = Size;
  902. hi2s->RxXferCount = Size;
  903. }
  904. /* Enable RXNE and ERR interrupt */
  905. __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  906. /* Check if the I2S is already enabled */
  907. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
  908. {
  909. /* Enable I2S peripheral */
  910. __HAL_I2S_ENABLE(hi2s);
  911. }
  912. __HAL_UNLOCK(hi2s);
  913. return HAL_OK;
  914. }
  915. /**
  916. * @brief Transmit an amount of data in non-blocking mode with DMA
  917. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  918. * the configuration information for I2S module
  919. * @param pData a 16-bit pointer to the Transmit data buffer.
  920. * @param Size number of data sample to be sent:
  921. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  922. * configuration phase, the Size parameter means the number of 16-bit data length
  923. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  924. * the Size parameter means the number of 16-bit data length.
  925. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  926. * between Master and Slave(example: audio streaming).
  927. * @retval HAL status
  928. */
  929. HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  930. {
  931. uint32_t tmpreg_cfgr;
  932. if ((pData == NULL) || (Size == 0U))
  933. {
  934. return HAL_ERROR;
  935. }
  936. /* Process Locked */
  937. __HAL_LOCK(hi2s);
  938. if (hi2s->State != HAL_I2S_STATE_READY)
  939. {
  940. __HAL_UNLOCK(hi2s);
  941. return HAL_BUSY;
  942. }
  943. /* Set state and reset error code */
  944. hi2s->State = HAL_I2S_STATE_BUSY_TX;
  945. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  946. hi2s->pTxBuffPtr = pData;
  947. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  948. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  949. {
  950. hi2s->TxXferSize = (Size << 1U);
  951. hi2s->TxXferCount = (Size << 1U);
  952. }
  953. else
  954. {
  955. hi2s->TxXferSize = Size;
  956. hi2s->TxXferCount = Size;
  957. }
  958. /* Set the I2S Tx DMA Half transfer complete callback */
  959. hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
  960. /* Set the I2S Tx DMA transfer complete callback */
  961. hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
  962. /* Set the DMA error callback */
  963. hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
  964. /* Enable the Tx DMA Stream/Channel */
  965. if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx,
  966. (uint32_t)hi2s->pTxBuffPtr,
  967. (uint32_t)&hi2s->Instance->DR,
  968. hi2s->TxXferSize))
  969. {
  970. /* Update SPI error code */
  971. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  972. hi2s->State = HAL_I2S_STATE_READY;
  973. __HAL_UNLOCK(hi2s);
  974. return HAL_ERROR;
  975. }
  976. /* Check if the I2S is already enabled */
  977. if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
  978. {
  979. /* Enable I2S peripheral */
  980. __HAL_I2S_ENABLE(hi2s);
  981. }
  982. /* Check if the I2S Tx request is already enabled */
  983. if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN))
  984. {
  985. /* Enable Tx DMA Request */
  986. SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  987. }
  988. __HAL_UNLOCK(hi2s);
  989. return HAL_OK;
  990. }
  991. /**
  992. * @brief Receive an amount of data in non-blocking mode with DMA
  993. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  994. * the configuration information for I2S module
  995. * @param pData a 16-bit pointer to the Receive data buffer.
  996. * @param Size number of data sample to be sent:
  997. * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
  998. * configuration phase, the Size parameter means the number of 16-bit data length
  999. * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
  1000. * the Size parameter means the number of 16-bit data length.
  1001. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
  1002. * between Master and Slave(example: audio streaming).
  1003. * @retval HAL status
  1004. */
  1005. HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
  1006. {
  1007. uint32_t tmpreg_cfgr;
  1008. if ((pData == NULL) || (Size == 0U))
  1009. {
  1010. return HAL_ERROR;
  1011. }
  1012. /* Process Locked */
  1013. __HAL_LOCK(hi2s);
  1014. if (hi2s->State != HAL_I2S_STATE_READY)
  1015. {
  1016. __HAL_UNLOCK(hi2s);
  1017. return HAL_BUSY;
  1018. }
  1019. /* Set state and reset error code */
  1020. hi2s->State = HAL_I2S_STATE_BUSY_RX;
  1021. hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
  1022. hi2s->pRxBuffPtr = pData;
  1023. tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
  1024. if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B))
  1025. {
  1026. hi2s->RxXferSize = (Size << 1U);
  1027. hi2s->RxXferCount = (Size << 1U);
  1028. }
  1029. else
  1030. {
  1031. hi2s->RxXferSize = Size;
  1032. hi2s->RxXferCount = Size;
  1033. }
  1034. /* Set the I2S Rx DMA Half transfer complete callback */
  1035. hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
  1036. /* Set the I2S Rx DMA transfer complete callback */
  1037. hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
  1038. /* Set the DMA error callback */
  1039. hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
  1040. /* Check if Master Receiver mode is selected */
  1041. if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
  1042. {
  1043. /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
  1044. access to the SPI_SR register. */
  1045. __HAL_I2S_CLEAR_OVRFLAG(hi2s);
  1046. }
  1047. /* Enable the Rx DMA Stream/Channel */
  1048. if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr,
  1049. hi2s->RxXferSize))
  1050. {
  1051. /* Update SPI error code */
  1052. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1053. hi2s->State = HAL_I2S_STATE_READY;
  1054. __HAL_UNLOCK(hi2s);
  1055. return HAL_ERROR;
  1056. }
  1057. /* Check if the I2S is already enabled */
  1058. if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
  1059. {
  1060. /* Enable I2S peripheral */
  1061. __HAL_I2S_ENABLE(hi2s);
  1062. }
  1063. /* Check if the I2S Rx request is already enabled */
  1064. if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN))
  1065. {
  1066. /* Enable Rx DMA Request */
  1067. SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1068. }
  1069. __HAL_UNLOCK(hi2s);
  1070. return HAL_OK;
  1071. }
  1072. /**
  1073. * @brief Pauses the audio DMA Stream/Channel playing from the Media.
  1074. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1075. * the configuration information for I2S module
  1076. * @retval HAL status
  1077. */
  1078. HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
  1079. {
  1080. /* Process Locked */
  1081. __HAL_LOCK(hi2s);
  1082. if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
  1083. {
  1084. /* Disable the I2S DMA Tx request */
  1085. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1086. }
  1087. else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
  1088. {
  1089. /* Disable the I2S DMA Rx request */
  1090. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1091. }
  1092. else
  1093. {
  1094. /* nothing to do */
  1095. }
  1096. /* Process Unlocked */
  1097. __HAL_UNLOCK(hi2s);
  1098. return HAL_OK;
  1099. }
  1100. /**
  1101. * @brief Resumes the audio DMA Stream/Channel playing from the Media.
  1102. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1103. * the configuration information for I2S module
  1104. * @retval HAL status
  1105. */
  1106. HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
  1107. {
  1108. /* Process Locked */
  1109. __HAL_LOCK(hi2s);
  1110. if (hi2s->State == HAL_I2S_STATE_BUSY_TX)
  1111. {
  1112. /* Enable the I2S DMA Tx request */
  1113. SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1114. }
  1115. else if (hi2s->State == HAL_I2S_STATE_BUSY_RX)
  1116. {
  1117. /* Enable the I2S DMA Rx request */
  1118. SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1119. }
  1120. else
  1121. {
  1122. /* nothing to do */
  1123. }
  1124. /* If the I2S peripheral is still not enabled, enable it */
  1125. if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
  1126. {
  1127. /* Enable I2S peripheral */
  1128. __HAL_I2S_ENABLE(hi2s);
  1129. }
  1130. /* Process Unlocked */
  1131. __HAL_UNLOCK(hi2s);
  1132. return HAL_OK;
  1133. }
  1134. /**
  1135. * @brief Stops the audio DMA Stream/Channel playing from the Media.
  1136. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1137. * the configuration information for I2S module
  1138. * @retval HAL status
  1139. */
  1140. HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
  1141. {
  1142. HAL_StatusTypeDef errorcode = HAL_OK;
  1143. /* The Lock is not implemented on this API to allow the user application
  1144. to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
  1145. when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated
  1146. and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback()
  1147. */
  1148. /* Disable the I2S Tx/Rx DMA requests */
  1149. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1150. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1151. /* Abort the I2S DMA tx Stream/Channel */
  1152. if (hi2s->hdmatx != NULL)
  1153. {
  1154. /* Disable the I2S DMA tx Stream/Channel */
  1155. if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx))
  1156. {
  1157. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1158. errorcode = HAL_ERROR;
  1159. }
  1160. }
  1161. /* Abort the I2S DMA rx Stream/Channel */
  1162. if (hi2s->hdmarx != NULL)
  1163. {
  1164. /* Disable the I2S DMA rx Stream/Channel */
  1165. if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx))
  1166. {
  1167. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1168. errorcode = HAL_ERROR;
  1169. }
  1170. }
  1171. /* Disable I2S peripheral */
  1172. __HAL_I2S_DISABLE(hi2s);
  1173. hi2s->State = HAL_I2S_STATE_READY;
  1174. return errorcode;
  1175. }
  1176. /**
  1177. * @brief This function handles I2S interrupt request.
  1178. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1179. * the configuration information for I2S module
  1180. * @retval None
  1181. */
  1182. void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
  1183. {
  1184. uint32_t itsource = hi2s->Instance->CR2;
  1185. uint32_t itflag = hi2s->Instance->SR;
  1186. /* I2S in mode Receiver ------------------------------------------------*/
  1187. if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) &&
  1188. (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET))
  1189. {
  1190. I2S_Receive_IT(hi2s);
  1191. return;
  1192. }
  1193. /* I2S in mode Tramitter -----------------------------------------------*/
  1194. if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET))
  1195. {
  1196. I2S_Transmit_IT(hi2s);
  1197. return;
  1198. }
  1199. /* I2S interrupt error -------------------------------------------------*/
  1200. if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET)
  1201. {
  1202. /* I2S Overrun error interrupt occurred ---------------------------------*/
  1203. if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET)
  1204. {
  1205. /* Disable RXNE and ERR interrupt */
  1206. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  1207. /* Set the error code and execute error callback*/
  1208. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
  1209. }
  1210. /* I2S Underrun error interrupt occurred --------------------------------*/
  1211. if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET)
  1212. {
  1213. /* Disable TXE and ERR interrupt */
  1214. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  1215. /* Set the error code and execute error callback*/
  1216. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
  1217. }
  1218. /* Set the I2S State ready */
  1219. hi2s->State = HAL_I2S_STATE_READY;
  1220. /* Call user error callback */
  1221. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1222. hi2s->ErrorCallback(hi2s);
  1223. #else
  1224. HAL_I2S_ErrorCallback(hi2s);
  1225. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1226. }
  1227. }
  1228. /**
  1229. * @brief Tx Transfer Half completed callbacks
  1230. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1231. * the configuration information for I2S module
  1232. * @retval None
  1233. */
  1234. __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  1235. {
  1236. /* Prevent unused argument(s) compilation warning */
  1237. UNUSED(hi2s);
  1238. /* NOTE : This function Should not be modified, when the callback is needed,
  1239. the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
  1240. */
  1241. }
  1242. /**
  1243. * @brief Tx Transfer completed callbacks
  1244. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1245. * the configuration information for I2S module
  1246. * @retval None
  1247. */
  1248. __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
  1249. {
  1250. /* Prevent unused argument(s) compilation warning */
  1251. UNUSED(hi2s);
  1252. /* NOTE : This function Should not be modified, when the callback is needed,
  1253. the HAL_I2S_TxCpltCallback could be implemented in the user file
  1254. */
  1255. }
  1256. /**
  1257. * @brief Rx Transfer half completed callbacks
  1258. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1259. * the configuration information for I2S module
  1260. * @retval None
  1261. */
  1262. __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
  1263. {
  1264. /* Prevent unused argument(s) compilation warning */
  1265. UNUSED(hi2s);
  1266. /* NOTE : This function Should not be modified, when the callback is needed,
  1267. the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
  1268. */
  1269. }
  1270. /**
  1271. * @brief Rx Transfer completed callbacks
  1272. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1273. * the configuration information for I2S module
  1274. * @retval None
  1275. */
  1276. __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
  1277. {
  1278. /* Prevent unused argument(s) compilation warning */
  1279. UNUSED(hi2s);
  1280. /* NOTE : This function Should not be modified, when the callback is needed,
  1281. the HAL_I2S_RxCpltCallback could be implemented in the user file
  1282. */
  1283. }
  1284. /**
  1285. * @brief I2S error callbacks
  1286. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1287. * the configuration information for I2S module
  1288. * @retval None
  1289. */
  1290. __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
  1291. {
  1292. /* Prevent unused argument(s) compilation warning */
  1293. UNUSED(hi2s);
  1294. /* NOTE : This function Should not be modified, when the callback is needed,
  1295. the HAL_I2S_ErrorCallback could be implemented in the user file
  1296. */
  1297. }
  1298. /**
  1299. * @}
  1300. */
  1301. /** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
  1302. * @brief Peripheral State functions
  1303. *
  1304. @verbatim
  1305. ===============================================================================
  1306. ##### Peripheral State and Errors functions #####
  1307. ===============================================================================
  1308. [..]
  1309. This subsection permits to get in run-time the status of the peripheral
  1310. and the data flow.
  1311. @endverbatim
  1312. * @{
  1313. */
  1314. /**
  1315. * @brief Return the I2S state
  1316. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1317. * the configuration information for I2S module
  1318. * @retval HAL state
  1319. */
  1320. HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
  1321. {
  1322. return hi2s->State;
  1323. }
  1324. /**
  1325. * @brief Return the I2S error code
  1326. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1327. * the configuration information for I2S module
  1328. * @retval I2S Error Code
  1329. */
  1330. uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
  1331. {
  1332. return hi2s->ErrorCode;
  1333. }
  1334. /**
  1335. * @}
  1336. */
  1337. /**
  1338. * @}
  1339. */
  1340. /** @addtogroup I2S_Private_Functions I2S Private Functions
  1341. * @{
  1342. */
  1343. /**
  1344. * @brief DMA I2S transmit process complete callback
  1345. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1346. * the configuration information for the specified DMA module.
  1347. * @retval None
  1348. */
  1349. static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
  1350. {
  1351. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1352. /* if DMA is configured in DMA_NORMAL Mode */
  1353. if (hdma->Init.Mode == DMA_NORMAL)
  1354. {
  1355. /* Disable Tx DMA Request */
  1356. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
  1357. hi2s->TxXferCount = 0U;
  1358. hi2s->State = HAL_I2S_STATE_READY;
  1359. }
  1360. /* Call user Tx complete callback */
  1361. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1362. hi2s->TxCpltCallback(hi2s);
  1363. #else
  1364. HAL_I2S_TxCpltCallback(hi2s);
  1365. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1366. }
  1367. /**
  1368. * @brief DMA I2S transmit process half complete callback
  1369. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1370. * the configuration information for the specified DMA module.
  1371. * @retval None
  1372. */
  1373. static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
  1374. {
  1375. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1376. /* Call user Tx half complete callback */
  1377. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1378. hi2s->TxHalfCpltCallback(hi2s);
  1379. #else
  1380. HAL_I2S_TxHalfCpltCallback(hi2s);
  1381. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1382. }
  1383. /**
  1384. * @brief DMA I2S receive process complete callback
  1385. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1386. * the configuration information for the specified DMA module.
  1387. * @retval None
  1388. */
  1389. static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
  1390. {
  1391. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1392. /* if DMA is configured in DMA_NORMAL Mode */
  1393. if (hdma->Init.Mode == DMA_NORMAL)
  1394. {
  1395. /* Disable Rx DMA Request */
  1396. CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
  1397. hi2s->RxXferCount = 0U;
  1398. hi2s->State = HAL_I2S_STATE_READY;
  1399. }
  1400. /* Call user Rx complete callback */
  1401. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1402. hi2s->RxCpltCallback(hi2s);
  1403. #else
  1404. HAL_I2S_RxCpltCallback(hi2s);
  1405. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1406. }
  1407. /**
  1408. * @brief DMA I2S receive process half complete callback
  1409. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1410. * the configuration information for the specified DMA module.
  1411. * @retval None
  1412. */
  1413. static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
  1414. {
  1415. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1416. /* Call user Rx half complete callback */
  1417. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1418. hi2s->RxHalfCpltCallback(hi2s);
  1419. #else
  1420. HAL_I2S_RxHalfCpltCallback(hi2s);
  1421. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1422. }
  1423. /**
  1424. * @brief DMA I2S communication error callback
  1425. * @param hdma pointer to a DMA_HandleTypeDef structure that contains
  1426. * the configuration information for the specified DMA module.
  1427. * @retval None
  1428. */
  1429. static void I2S_DMAError(DMA_HandleTypeDef *hdma)
  1430. {
  1431. I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */
  1432. /* Disable Rx and Tx DMA Request */
  1433. CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
  1434. hi2s->TxXferCount = 0U;
  1435. hi2s->RxXferCount = 0U;
  1436. hi2s->State = HAL_I2S_STATE_READY;
  1437. /* Set the error code and execute error callback*/
  1438. SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
  1439. /* Call user error callback */
  1440. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1441. hi2s->ErrorCallback(hi2s);
  1442. #else
  1443. HAL_I2S_ErrorCallback(hi2s);
  1444. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1445. }
  1446. /**
  1447. * @brief Transmit an amount of data in non-blocking mode with Interrupt
  1448. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1449. * the configuration information for I2S module
  1450. * @retval None
  1451. */
  1452. static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
  1453. {
  1454. /* Transmit data */
  1455. hi2s->Instance->DR = (*hi2s->pTxBuffPtr);
  1456. hi2s->pTxBuffPtr++;
  1457. hi2s->TxXferCount--;
  1458. if (hi2s->TxXferCount == 0U)
  1459. {
  1460. /* Disable TXE and ERR interrupt */
  1461. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
  1462. hi2s->State = HAL_I2S_STATE_READY;
  1463. /* Call user Tx complete callback */
  1464. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1465. hi2s->TxCpltCallback(hi2s);
  1466. #else
  1467. HAL_I2S_TxCpltCallback(hi2s);
  1468. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1469. }
  1470. }
  1471. /**
  1472. * @brief Receive an amount of data in non-blocking mode with Interrupt
  1473. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1474. * the configuration information for I2S module
  1475. * @retval None
  1476. */
  1477. static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
  1478. {
  1479. /* Receive data */
  1480. (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR;
  1481. hi2s->pRxBuffPtr++;
  1482. hi2s->RxXferCount--;
  1483. if (hi2s->RxXferCount == 0U)
  1484. {
  1485. /* Disable RXNE and ERR interrupt */
  1486. __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
  1487. hi2s->State = HAL_I2S_STATE_READY;
  1488. /* Call user Rx complete callback */
  1489. #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
  1490. hi2s->RxCpltCallback(hi2s);
  1491. #else
  1492. HAL_I2S_RxCpltCallback(hi2s);
  1493. #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
  1494. }
  1495. }
  1496. /**
  1497. * @brief This function handles I2S Communication Timeout.
  1498. * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
  1499. * the configuration information for I2S module
  1500. * @param Flag Flag checked
  1501. * @param State Value of the flag expected
  1502. * @param Timeout Duration of the timeout
  1503. * @retval HAL status
  1504. */
  1505. static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State,
  1506. uint32_t Timeout)
  1507. {
  1508. uint32_t tickstart;
  1509. /* Get tick */
  1510. tickstart = HAL_GetTick();
  1511. /* Wait until flag is set to status*/
  1512. while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State)
  1513. {
  1514. if (Timeout != HAL_MAX_DELAY)
  1515. {
  1516. if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U))
  1517. {
  1518. /* Set the I2S State ready */
  1519. hi2s->State = HAL_I2S_STATE_READY;
  1520. /* Process Unlocked */
  1521. __HAL_UNLOCK(hi2s);
  1522. return HAL_TIMEOUT;
  1523. }
  1524. }
  1525. }
  1526. return HAL_OK;
  1527. }
  1528. /**
  1529. * @}
  1530. */
  1531. /**
  1532. * @}
  1533. */
  1534. /**
  1535. * @}
  1536. */
  1537. #endif /* SPI_I2S_SUPPORT */
  1538. #endif /* HAL_I2S_MODULE_ENABLED */
  1539. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/