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cmsis_armclang.h 53KB

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  1. /**************************************************************************//**
  2. * @file cmsis_armclang.h
  3. * @brief CMSIS compiler armclang (Arm Compiler 6) header file
  4. * @version V5.0.4
  5. * @date 10. January 2018
  6. ******************************************************************************/
  7. /*
  8. * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
  9. *
  10. * SPDX-License-Identifier: Apache-2.0
  11. *
  12. * Licensed under the Apache License, Version 2.0 (the License); you may
  13. * not use this file except in compliance with the License.
  14. * You may obtain a copy of the License at
  15. *
  16. * www.apache.org/licenses/LICENSE-2.0
  17. *
  18. * Unless required by applicable law or agreed to in writing, software
  19. * distributed under the License is distributed on an AS IS BASIS, WITHOUT
  20. * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  21. * See the License for the specific language governing permissions and
  22. * limitations under the License.
  23. */
  24. /*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
  25. #ifndef __CMSIS_ARMCLANG_H
  26. #define __CMSIS_ARMCLANG_H
  27. #pragma clang system_header /* treat file as system include file */
  28. #ifndef __ARM_COMPAT_H
  29. #include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
  30. #endif
  31. /* CMSIS compiler specific defines */
  32. #ifndef __ASM
  33. #define __ASM __asm
  34. #endif
  35. #ifndef __INLINE
  36. #define __INLINE __inline
  37. #endif
  38. #ifndef __STATIC_INLINE
  39. #define __STATIC_INLINE static __inline
  40. #endif
  41. #ifndef __STATIC_FORCEINLINE
  42. #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
  43. #endif
  44. #ifndef __NO_RETURN
  45. #define __NO_RETURN __attribute__((__noreturn__))
  46. #endif
  47. #ifndef __USED
  48. #define __USED __attribute__((used))
  49. #endif
  50. #ifndef __WEAK
  51. #define __WEAK __attribute__((weak))
  52. #endif
  53. #ifndef __PACKED
  54. #define __PACKED __attribute__((packed, aligned(1)))
  55. #endif
  56. #ifndef __PACKED_STRUCT
  57. #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
  58. #endif
  59. #ifndef __PACKED_UNION
  60. #define __PACKED_UNION union __attribute__((packed, aligned(1)))
  61. #endif
  62. #ifndef __UNALIGNED_UINT32 /* deprecated */
  63. #pragma clang diagnostic push
  64. #pragma clang diagnostic ignored "-Wpacked"
  65. /*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
  66. struct __attribute__((packed)) T_UINT32 { uint32_t v; };
  67. #pragma clang diagnostic pop
  68. #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
  69. #endif
  70. #ifndef __UNALIGNED_UINT16_WRITE
  71. #pragma clang diagnostic push
  72. #pragma clang diagnostic ignored "-Wpacked"
  73. /*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
  74. __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
  75. #pragma clang diagnostic pop
  76. #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
  77. #endif
  78. #ifndef __UNALIGNED_UINT16_READ
  79. #pragma clang diagnostic push
  80. #pragma clang diagnostic ignored "-Wpacked"
  81. /*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
  82. __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
  83. #pragma clang diagnostic pop
  84. #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
  85. #endif
  86. #ifndef __UNALIGNED_UINT32_WRITE
  87. #pragma clang diagnostic push
  88. #pragma clang diagnostic ignored "-Wpacked"
  89. /*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
  90. __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
  91. #pragma clang diagnostic pop
  92. #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
  93. #endif
  94. #ifndef __UNALIGNED_UINT32_READ
  95. #pragma clang diagnostic push
  96. #pragma clang diagnostic ignored "-Wpacked"
  97. /*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
  98. __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
  99. #pragma clang diagnostic pop
  100. #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
  101. #endif
  102. #ifndef __ALIGNED
  103. #define __ALIGNED(x) __attribute__((aligned(x)))
  104. #endif
  105. #ifndef __RESTRICT
  106. #define __RESTRICT __restrict
  107. #endif
  108. /* ########################### Core Function Access ########################### */
  109. /** \ingroup CMSIS_Core_FunctionInterface
  110. \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
  111. @{
  112. */
  113. /**
  114. \brief Enable IRQ Interrupts
  115. \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
  116. Can only be executed in Privileged modes.
  117. */
  118. /* intrinsic void __enable_irq(); see arm_compat.h */
  119. /**
  120. \brief Disable IRQ Interrupts
  121. \details Disables IRQ interrupts by setting the I-bit in the CPSR.
  122. Can only be executed in Privileged modes.
  123. */
  124. /* intrinsic void __disable_irq(); see arm_compat.h */
  125. /**
  126. \brief Get Control Register
  127. \details Returns the content of the Control Register.
  128. \return Control Register value
  129. */
  130. __STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
  131. {
  132. uint32_t result;
  133. __ASM volatile ("MRS %0, control" : "=r" (result) );
  134. return(result);
  135. }
  136. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  137. /**
  138. \brief Get Control Register (non-secure)
  139. \details Returns the content of the non-secure Control Register when in secure mode.
  140. \return non-secure Control Register value
  141. */
  142. __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
  143. {
  144. uint32_t result;
  145. __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
  146. return(result);
  147. }
  148. #endif
  149. /**
  150. \brief Set Control Register
  151. \details Writes the given value to the Control Register.
  152. \param [in] control Control Register value to set
  153. */
  154. __STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
  155. {
  156. __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
  157. }
  158. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  159. /**
  160. \brief Set Control Register (non-secure)
  161. \details Writes the given value to the non-secure Control Register when in secure state.
  162. \param [in] control Control Register value to set
  163. */
  164. __STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
  165. {
  166. __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
  167. }
  168. #endif
  169. /**
  170. \brief Get IPSR Register
  171. \details Returns the content of the IPSR Register.
  172. \return IPSR Register value
  173. */
  174. __STATIC_FORCEINLINE uint32_t __get_IPSR(void)
  175. {
  176. uint32_t result;
  177. __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
  178. return(result);
  179. }
  180. /**
  181. \brief Get APSR Register
  182. \details Returns the content of the APSR Register.
  183. \return APSR Register value
  184. */
  185. __STATIC_FORCEINLINE uint32_t __get_APSR(void)
  186. {
  187. uint32_t result;
  188. __ASM volatile ("MRS %0, apsr" : "=r" (result) );
  189. return(result);
  190. }
  191. /**
  192. \brief Get xPSR Register
  193. \details Returns the content of the xPSR Register.
  194. \return xPSR Register value
  195. */
  196. __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
  197. {
  198. uint32_t result;
  199. __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
  200. return(result);
  201. }
  202. /**
  203. \brief Get Process Stack Pointer
  204. \details Returns the current value of the Process Stack Pointer (PSP).
  205. \return PSP Register value
  206. */
  207. __STATIC_FORCEINLINE uint32_t __get_PSP(void)
  208. {
  209. uint32_t result;
  210. __ASM volatile ("MRS %0, psp" : "=r" (result) );
  211. return(result);
  212. }
  213. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  214. /**
  215. \brief Get Process Stack Pointer (non-secure)
  216. \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
  217. \return PSP Register value
  218. */
  219. __STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
  220. {
  221. uint32_t result;
  222. __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
  223. return(result);
  224. }
  225. #endif
  226. /**
  227. \brief Set Process Stack Pointer
  228. \details Assigns the given value to the Process Stack Pointer (PSP).
  229. \param [in] topOfProcStack Process Stack Pointer value to set
  230. */
  231. __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
  232. {
  233. __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
  234. }
  235. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  236. /**
  237. \brief Set Process Stack Pointer (non-secure)
  238. \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
  239. \param [in] topOfProcStack Process Stack Pointer value to set
  240. */
  241. __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
  242. {
  243. __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
  244. }
  245. #endif
  246. /**
  247. \brief Get Main Stack Pointer
  248. \details Returns the current value of the Main Stack Pointer (MSP).
  249. \return MSP Register value
  250. */
  251. __STATIC_FORCEINLINE uint32_t __get_MSP(void)
  252. {
  253. uint32_t result;
  254. __ASM volatile ("MRS %0, msp" : "=r" (result) );
  255. return(result);
  256. }
  257. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  258. /**
  259. \brief Get Main Stack Pointer (non-secure)
  260. \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
  261. \return MSP Register value
  262. */
  263. __STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
  264. {
  265. uint32_t result;
  266. __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
  267. return(result);
  268. }
  269. #endif
  270. /**
  271. \brief Set Main Stack Pointer
  272. \details Assigns the given value to the Main Stack Pointer (MSP).
  273. \param [in] topOfMainStack Main Stack Pointer value to set
  274. */
  275. __STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
  276. {
  277. __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
  278. }
  279. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  280. /**
  281. \brief Set Main Stack Pointer (non-secure)
  282. \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
  283. \param [in] topOfMainStack Main Stack Pointer value to set
  284. */
  285. __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
  286. {
  287. __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
  288. }
  289. #endif
  290. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  291. /**
  292. \brief Get Stack Pointer (non-secure)
  293. \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
  294. \return SP Register value
  295. */
  296. __STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
  297. {
  298. uint32_t result;
  299. __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
  300. return(result);
  301. }
  302. /**
  303. \brief Set Stack Pointer (non-secure)
  304. \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
  305. \param [in] topOfStack Stack Pointer value to set
  306. */
  307. __STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
  308. {
  309. __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
  310. }
  311. #endif
  312. /**
  313. \brief Get Priority Mask
  314. \details Returns the current state of the priority mask bit from the Priority Mask Register.
  315. \return Priority Mask value
  316. */
  317. __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
  318. {
  319. uint32_t result;
  320. __ASM volatile ("MRS %0, primask" : "=r" (result) );
  321. return(result);
  322. }
  323. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  324. /**
  325. \brief Get Priority Mask (non-secure)
  326. \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
  327. \return Priority Mask value
  328. */
  329. __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
  330. {
  331. uint32_t result;
  332. __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
  333. return(result);
  334. }
  335. #endif
  336. /**
  337. \brief Set Priority Mask
  338. \details Assigns the given value to the Priority Mask Register.
  339. \param [in] priMask Priority Mask
  340. */
  341. __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
  342. {
  343. __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
  344. }
  345. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  346. /**
  347. \brief Set Priority Mask (non-secure)
  348. \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
  349. \param [in] priMask Priority Mask
  350. */
  351. __STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
  352. {
  353. __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
  354. }
  355. #endif
  356. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  357. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  358. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  359. /**
  360. \brief Enable FIQ
  361. \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
  362. Can only be executed in Privileged modes.
  363. */
  364. #define __enable_fault_irq __enable_fiq /* see arm_compat.h */
  365. /**
  366. \brief Disable FIQ
  367. \details Disables FIQ interrupts by setting the F-bit in the CPSR.
  368. Can only be executed in Privileged modes.
  369. */
  370. #define __disable_fault_irq __disable_fiq /* see arm_compat.h */
  371. /**
  372. \brief Get Base Priority
  373. \details Returns the current value of the Base Priority register.
  374. \return Base Priority register value
  375. */
  376. __STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
  377. {
  378. uint32_t result;
  379. __ASM volatile ("MRS %0, basepri" : "=r" (result) );
  380. return(result);
  381. }
  382. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  383. /**
  384. \brief Get Base Priority (non-secure)
  385. \details Returns the current value of the non-secure Base Priority register when in secure state.
  386. \return Base Priority register value
  387. */
  388. __STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
  389. {
  390. uint32_t result;
  391. __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
  392. return(result);
  393. }
  394. #endif
  395. /**
  396. \brief Set Base Priority
  397. \details Assigns the given value to the Base Priority register.
  398. \param [in] basePri Base Priority value to set
  399. */
  400. __STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
  401. {
  402. __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
  403. }
  404. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  405. /**
  406. \brief Set Base Priority (non-secure)
  407. \details Assigns the given value to the non-secure Base Priority register when in secure state.
  408. \param [in] basePri Base Priority value to set
  409. */
  410. __STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
  411. {
  412. __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
  413. }
  414. #endif
  415. /**
  416. \brief Set Base Priority with condition
  417. \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
  418. or the new value increases the BASEPRI priority level.
  419. \param [in] basePri Base Priority value to set
  420. */
  421. __STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
  422. {
  423. __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
  424. }
  425. /**
  426. \brief Get Fault Mask
  427. \details Returns the current value of the Fault Mask register.
  428. \return Fault Mask register value
  429. */
  430. __STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
  431. {
  432. uint32_t result;
  433. __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
  434. return(result);
  435. }
  436. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  437. /**
  438. \brief Get Fault Mask (non-secure)
  439. \details Returns the current value of the non-secure Fault Mask register when in secure state.
  440. \return Fault Mask register value
  441. */
  442. __STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
  443. {
  444. uint32_t result;
  445. __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
  446. return(result);
  447. }
  448. #endif
  449. /**
  450. \brief Set Fault Mask
  451. \details Assigns the given value to the Fault Mask register.
  452. \param [in] faultMask Fault Mask value to set
  453. */
  454. __STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
  455. {
  456. __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
  457. }
  458. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  459. /**
  460. \brief Set Fault Mask (non-secure)
  461. \details Assigns the given value to the non-secure Fault Mask register when in secure state.
  462. \param [in] faultMask Fault Mask value to set
  463. */
  464. __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
  465. {
  466. __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
  467. }
  468. #endif
  469. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  470. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  471. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  472. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  473. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  474. /**
  475. \brief Get Process Stack Pointer Limit
  476. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  477. Stack Pointer Limit register hence zero is returned always in non-secure
  478. mode.
  479. \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
  480. \return PSPLIM Register value
  481. */
  482. __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
  483. {
  484. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  485. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  486. // without main extensions, the non-secure PSPLIM is RAZ/WI
  487. return 0U;
  488. #else
  489. uint32_t result;
  490. __ASM volatile ("MRS %0, psplim" : "=r" (result) );
  491. return result;
  492. #endif
  493. }
  494. #if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
  495. /**
  496. \brief Get Process Stack Pointer Limit (non-secure)
  497. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  498. Stack Pointer Limit register hence zero is returned always in non-secure
  499. mode.
  500. \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  501. \return PSPLIM Register value
  502. */
  503. __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
  504. {
  505. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  506. // without main extensions, the non-secure PSPLIM is RAZ/WI
  507. return 0U;
  508. #else
  509. uint32_t result;
  510. __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
  511. return result;
  512. #endif
  513. }
  514. #endif
  515. /**
  516. \brief Set Process Stack Pointer Limit
  517. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  518. Stack Pointer Limit register hence the write is silently ignored in non-secure
  519. mode.
  520. \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
  521. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
  522. */
  523. __STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
  524. {
  525. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  526. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  527. // without main extensions, the non-secure PSPLIM is RAZ/WI
  528. (void)ProcStackPtrLimit;
  529. #else
  530. __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
  531. #endif
  532. }
  533. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  534. /**
  535. \brief Set Process Stack Pointer (non-secure)
  536. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  537. Stack Pointer Limit register hence the write is silently ignored in non-secure
  538. mode.
  539. \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
  540. \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
  541. */
  542. __STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
  543. {
  544. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  545. // without main extensions, the non-secure PSPLIM is RAZ/WI
  546. (void)ProcStackPtrLimit;
  547. #else
  548. __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
  549. #endif
  550. }
  551. #endif
  552. /**
  553. \brief Get Main Stack Pointer Limit
  554. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  555. Stack Pointer Limit register hence zero is returned always.
  556. \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
  557. \return MSPLIM Register value
  558. */
  559. __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
  560. {
  561. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  562. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  563. // without main extensions, the non-secure MSPLIM is RAZ/WI
  564. return 0U;
  565. #else
  566. uint32_t result;
  567. __ASM volatile ("MRS %0, msplim" : "=r" (result) );
  568. return result;
  569. #endif
  570. }
  571. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  572. /**
  573. \brief Get Main Stack Pointer Limit (non-secure)
  574. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  575. Stack Pointer Limit register hence zero is returned always.
  576. \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
  577. \return MSPLIM Register value
  578. */
  579. __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
  580. {
  581. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  582. // without main extensions, the non-secure MSPLIM is RAZ/WI
  583. return 0U;
  584. #else
  585. uint32_t result;
  586. __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
  587. return result;
  588. #endif
  589. }
  590. #endif
  591. /**
  592. \brief Set Main Stack Pointer Limit
  593. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  594. Stack Pointer Limit register hence the write is silently ignored.
  595. \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
  596. \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
  597. */
  598. __STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
  599. {
  600. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
  601. (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
  602. // without main extensions, the non-secure MSPLIM is RAZ/WI
  603. (void)MainStackPtrLimit;
  604. #else
  605. __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
  606. #endif
  607. }
  608. #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
  609. /**
  610. \brief Set Main Stack Pointer Limit (non-secure)
  611. Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
  612. Stack Pointer Limit register hence the write is silently ignored.
  613. \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
  614. \param [in] MainStackPtrLimit Main Stack Pointer value to set
  615. */
  616. __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
  617. {
  618. #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
  619. // without main extensions, the non-secure MSPLIM is RAZ/WI
  620. (void)MainStackPtrLimit;
  621. #else
  622. __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
  623. #endif
  624. }
  625. #endif
  626. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  627. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  628. /**
  629. \brief Get FPSCR
  630. \details Returns the current value of the Floating Point Status/Control register.
  631. \return Floating Point Status/Control register value
  632. */
  633. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  634. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  635. #define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr
  636. #else
  637. #define __get_FPSCR() ((uint32_t)0U)
  638. #endif
  639. /**
  640. \brief Set FPSCR
  641. \details Assigns the given value to the Floating Point Status/Control register.
  642. \param [in] fpscr Floating Point Status/Control value to set
  643. */
  644. #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
  645. (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
  646. #define __set_FPSCR __builtin_arm_set_fpscr
  647. #else
  648. #define __set_FPSCR(x) ((void)(x))
  649. #endif
  650. /*@} end of CMSIS_Core_RegAccFunctions */
  651. /* ########################## Core Instruction Access ######################### */
  652. /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
  653. Access to dedicated instructions
  654. @{
  655. */
  656. /* Define macros for porting to both thumb1 and thumb2.
  657. * For thumb1, use low register (r0-r7), specified by constraint "l"
  658. * Otherwise, use general registers, specified by constraint "r" */
  659. #if defined (__thumb__) && !defined (__thumb2__)
  660. #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
  661. #define __CMSIS_GCC_USE_REG(r) "l" (r)
  662. #else
  663. #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
  664. #define __CMSIS_GCC_USE_REG(r) "r" (r)
  665. #endif
  666. /**
  667. \brief No Operation
  668. \details No Operation does nothing. This instruction can be used for code alignment purposes.
  669. */
  670. #define __NOP __builtin_arm_nop
  671. /**
  672. \brief Wait For Interrupt
  673. \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
  674. */
  675. #define __WFI __builtin_arm_wfi
  676. /**
  677. \brief Wait For Event
  678. \details Wait For Event is a hint instruction that permits the processor to enter
  679. a low-power state until one of a number of events occurs.
  680. */
  681. #define __WFE __builtin_arm_wfe
  682. /**
  683. \brief Send Event
  684. \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
  685. */
  686. #define __SEV __builtin_arm_sev
  687. /**
  688. \brief Instruction Synchronization Barrier
  689. \details Instruction Synchronization Barrier flushes the pipeline in the processor,
  690. so that all instructions following the ISB are fetched from cache or memory,
  691. after the instruction has been completed.
  692. */
  693. #define __ISB() __builtin_arm_isb(0xF);
  694. /**
  695. \brief Data Synchronization Barrier
  696. \details Acts as a special kind of Data Memory Barrier.
  697. It completes when all explicit memory accesses before this instruction complete.
  698. */
  699. #define __DSB() __builtin_arm_dsb(0xF);
  700. /**
  701. \brief Data Memory Barrier
  702. \details Ensures the apparent order of the explicit memory operations before
  703. and after the instruction, without ensuring their completion.
  704. */
  705. #define __DMB() __builtin_arm_dmb(0xF);
  706. /**
  707. \brief Reverse byte order (32 bit)
  708. \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
  709. \param [in] value Value to reverse
  710. \return Reversed value
  711. */
  712. #define __REV(value) __builtin_bswap32(value)
  713. /**
  714. \brief Reverse byte order (16 bit)
  715. \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
  716. \param [in] value Value to reverse
  717. \return Reversed value
  718. */
  719. #define __REV16(value) __ROR(__REV(value), 16)
  720. /**
  721. \brief Reverse byte order (16 bit)
  722. \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
  723. \param [in] value Value to reverse
  724. \return Reversed value
  725. */
  726. #define __REVSH(value) (int16_t)__builtin_bswap16(value)
  727. /**
  728. \brief Rotate Right in unsigned value (32 bit)
  729. \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
  730. \param [in] op1 Value to rotate
  731. \param [in] op2 Number of Bits to rotate
  732. \return Rotated value
  733. */
  734. __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
  735. {
  736. op2 %= 32U;
  737. if (op2 == 0U)
  738. {
  739. return op1;
  740. }
  741. return (op1 >> op2) | (op1 << (32U - op2));
  742. }
  743. /**
  744. \brief Breakpoint
  745. \details Causes the processor to enter Debug state.
  746. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
  747. \param [in] value is ignored by the processor.
  748. If required, a debugger can use it to store additional information about the breakpoint.
  749. */
  750. #define __BKPT(value) __ASM volatile ("bkpt "#value)
  751. /**
  752. \brief Reverse bit order of value
  753. \details Reverses the bit order of the given value.
  754. \param [in] value Value to reverse
  755. \return Reversed value
  756. */
  757. #define __RBIT __builtin_arm_rbit
  758. /**
  759. \brief Count leading zeros
  760. \details Counts the number of leading zeros of a data value.
  761. \param [in] value Value to count the leading zeros
  762. \return number of leading zeros in value
  763. */
  764. #define __CLZ (uint8_t)__builtin_clz
  765. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  766. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  767. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  768. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  769. /**
  770. \brief LDR Exclusive (8 bit)
  771. \details Executes a exclusive LDR instruction for 8 bit value.
  772. \param [in] ptr Pointer to data
  773. \return value of type uint8_t at (*ptr)
  774. */
  775. #define __LDREXB (uint8_t)__builtin_arm_ldrex
  776. /**
  777. \brief LDR Exclusive (16 bit)
  778. \details Executes a exclusive LDR instruction for 16 bit values.
  779. \param [in] ptr Pointer to data
  780. \return value of type uint16_t at (*ptr)
  781. */
  782. #define __LDREXH (uint16_t)__builtin_arm_ldrex
  783. /**
  784. \brief LDR Exclusive (32 bit)
  785. \details Executes a exclusive LDR instruction for 32 bit values.
  786. \param [in] ptr Pointer to data
  787. \return value of type uint32_t at (*ptr)
  788. */
  789. #define __LDREXW (uint32_t)__builtin_arm_ldrex
  790. /**
  791. \brief STR Exclusive (8 bit)
  792. \details Executes a exclusive STR instruction for 8 bit values.
  793. \param [in] value Value to store
  794. \param [in] ptr Pointer to location
  795. \return 0 Function succeeded
  796. \return 1 Function failed
  797. */
  798. #define __STREXB (uint32_t)__builtin_arm_strex
  799. /**
  800. \brief STR Exclusive (16 bit)
  801. \details Executes a exclusive STR instruction for 16 bit values.
  802. \param [in] value Value to store
  803. \param [in] ptr Pointer to location
  804. \return 0 Function succeeded
  805. \return 1 Function failed
  806. */
  807. #define __STREXH (uint32_t)__builtin_arm_strex
  808. /**
  809. \brief STR Exclusive (32 bit)
  810. \details Executes a exclusive STR instruction for 32 bit values.
  811. \param [in] value Value to store
  812. \param [in] ptr Pointer to location
  813. \return 0 Function succeeded
  814. \return 1 Function failed
  815. */
  816. #define __STREXW (uint32_t)__builtin_arm_strex
  817. /**
  818. \brief Remove the exclusive lock
  819. \details Removes the exclusive lock which is created by LDREX.
  820. */
  821. #define __CLREX __builtin_arm_clrex
  822. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  823. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  824. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  825. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  826. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  827. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  828. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  829. /**
  830. \brief Signed Saturate
  831. \details Saturates a signed value.
  832. \param [in] value Value to be saturated
  833. \param [in] sat Bit position to saturate to (1..32)
  834. \return Saturated value
  835. */
  836. #define __SSAT __builtin_arm_ssat
  837. /**
  838. \brief Unsigned Saturate
  839. \details Saturates an unsigned value.
  840. \param [in] value Value to be saturated
  841. \param [in] sat Bit position to saturate to (0..31)
  842. \return Saturated value
  843. */
  844. #define __USAT __builtin_arm_usat
  845. /**
  846. \brief Rotate Right with Extend (32 bit)
  847. \details Moves each bit of a bitstring right by one bit.
  848. The carry input is shifted in at the left end of the bitstring.
  849. \param [in] value Value to rotate
  850. \return Rotated value
  851. */
  852. __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
  853. {
  854. uint32_t result;
  855. __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
  856. return(result);
  857. }
  858. /**
  859. \brief LDRT Unprivileged (8 bit)
  860. \details Executes a Unprivileged LDRT instruction for 8 bit value.
  861. \param [in] ptr Pointer to data
  862. \return value of type uint8_t at (*ptr)
  863. */
  864. __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
  865. {
  866. uint32_t result;
  867. __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
  868. return ((uint8_t) result); /* Add explicit type cast here */
  869. }
  870. /**
  871. \brief LDRT Unprivileged (16 bit)
  872. \details Executes a Unprivileged LDRT instruction for 16 bit values.
  873. \param [in] ptr Pointer to data
  874. \return value of type uint16_t at (*ptr)
  875. */
  876. __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
  877. {
  878. uint32_t result;
  879. __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
  880. return ((uint16_t) result); /* Add explicit type cast here */
  881. }
  882. /**
  883. \brief LDRT Unprivileged (32 bit)
  884. \details Executes a Unprivileged LDRT instruction for 32 bit values.
  885. \param [in] ptr Pointer to data
  886. \return value of type uint32_t at (*ptr)
  887. */
  888. __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
  889. {
  890. uint32_t result;
  891. __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
  892. return(result);
  893. }
  894. /**
  895. \brief STRT Unprivileged (8 bit)
  896. \details Executes a Unprivileged STRT instruction for 8 bit values.
  897. \param [in] value Value to store
  898. \param [in] ptr Pointer to location
  899. */
  900. __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
  901. {
  902. __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  903. }
  904. /**
  905. \brief STRT Unprivileged (16 bit)
  906. \details Executes a Unprivileged STRT instruction for 16 bit values.
  907. \param [in] value Value to store
  908. \param [in] ptr Pointer to location
  909. */
  910. __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
  911. {
  912. __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  913. }
  914. /**
  915. \brief STRT Unprivileged (32 bit)
  916. \details Executes a Unprivileged STRT instruction for 32 bit values.
  917. \param [in] value Value to store
  918. \param [in] ptr Pointer to location
  919. */
  920. __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
  921. {
  922. __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
  923. }
  924. #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  925. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  926. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  927. /**
  928. \brief Signed Saturate
  929. \details Saturates a signed value.
  930. \param [in] value Value to be saturated
  931. \param [in] sat Bit position to saturate to (1..32)
  932. \return Saturated value
  933. */
  934. __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
  935. {
  936. if ((sat >= 1U) && (sat <= 32U))
  937. {
  938. const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
  939. const int32_t min = -1 - max ;
  940. if (val > max)
  941. {
  942. return max;
  943. }
  944. else if (val < min)
  945. {
  946. return min;
  947. }
  948. }
  949. return val;
  950. }
  951. /**
  952. \brief Unsigned Saturate
  953. \details Saturates an unsigned value.
  954. \param [in] value Value to be saturated
  955. \param [in] sat Bit position to saturate to (0..31)
  956. \return Saturated value
  957. */
  958. __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
  959. {
  960. if (sat <= 31U)
  961. {
  962. const uint32_t max = ((1U << sat) - 1U);
  963. if (val > (int32_t)max)
  964. {
  965. return max;
  966. }
  967. else if (val < 0)
  968. {
  969. return 0U;
  970. }
  971. }
  972. return (uint32_t)val;
  973. }
  974. #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  975. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  976. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
  977. #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  978. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
  979. /**
  980. \brief Load-Acquire (8 bit)
  981. \details Executes a LDAB instruction for 8 bit value.
  982. \param [in] ptr Pointer to data
  983. \return value of type uint8_t at (*ptr)
  984. */
  985. __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
  986. {
  987. uint32_t result;
  988. __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
  989. return ((uint8_t) result);
  990. }
  991. /**
  992. \brief Load-Acquire (16 bit)
  993. \details Executes a LDAH instruction for 16 bit values.
  994. \param [in] ptr Pointer to data
  995. \return value of type uint16_t at (*ptr)
  996. */
  997. __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
  998. {
  999. uint32_t result;
  1000. __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
  1001. return ((uint16_t) result);
  1002. }
  1003. /**
  1004. \brief Load-Acquire (32 bit)
  1005. \details Executes a LDA instruction for 32 bit values.
  1006. \param [in] ptr Pointer to data
  1007. \return value of type uint32_t at (*ptr)
  1008. */
  1009. __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
  1010. {
  1011. uint32_t result;
  1012. __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
  1013. return(result);
  1014. }
  1015. /**
  1016. \brief Store-Release (8 bit)
  1017. \details Executes a STLB instruction for 8 bit values.
  1018. \param [in] value Value to store
  1019. \param [in] ptr Pointer to location
  1020. */
  1021. __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
  1022. {
  1023. __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1024. }
  1025. /**
  1026. \brief Store-Release (16 bit)
  1027. \details Executes a STLH instruction for 16 bit values.
  1028. \param [in] value Value to store
  1029. \param [in] ptr Pointer to location
  1030. */
  1031. __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
  1032. {
  1033. __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1034. }
  1035. /**
  1036. \brief Store-Release (32 bit)
  1037. \details Executes a STL instruction for 32 bit values.
  1038. \param [in] value Value to store
  1039. \param [in] ptr Pointer to location
  1040. */
  1041. __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
  1042. {
  1043. __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
  1044. }
  1045. /**
  1046. \brief Load-Acquire Exclusive (8 bit)
  1047. \details Executes a LDAB exclusive instruction for 8 bit value.
  1048. \param [in] ptr Pointer to data
  1049. \return value of type uint8_t at (*ptr)
  1050. */
  1051. #define __LDAEXB (uint8_t)__builtin_arm_ldaex
  1052. /**
  1053. \brief Load-Acquire Exclusive (16 bit)
  1054. \details Executes a LDAH exclusive instruction for 16 bit values.
  1055. \param [in] ptr Pointer to data
  1056. \return value of type uint16_t at (*ptr)
  1057. */
  1058. #define __LDAEXH (uint16_t)__builtin_arm_ldaex
  1059. /**
  1060. \brief Load-Acquire Exclusive (32 bit)
  1061. \details Executes a LDA exclusive instruction for 32 bit values.
  1062. \param [in] ptr Pointer to data
  1063. \return value of type uint32_t at (*ptr)
  1064. */
  1065. #define __LDAEX (uint32_t)__builtin_arm_ldaex
  1066. /**
  1067. \brief Store-Release Exclusive (8 bit)
  1068. \details Executes a STLB exclusive instruction for 8 bit values.
  1069. \param [in] value Value to store
  1070. \param [in] ptr Pointer to location
  1071. \return 0 Function succeeded
  1072. \return 1 Function failed
  1073. */
  1074. #define __STLEXB (uint32_t)__builtin_arm_stlex
  1075. /**
  1076. \brief Store-Release Exclusive (16 bit)
  1077. \details Executes a STLH exclusive instruction for 16 bit values.
  1078. \param [in] value Value to store
  1079. \param [in] ptr Pointer to location
  1080. \return 0 Function succeeded
  1081. \return 1 Function failed
  1082. */
  1083. #define __STLEXH (uint32_t)__builtin_arm_stlex
  1084. /**
  1085. \brief Store-Release Exclusive (32 bit)
  1086. \details Executes a STL exclusive instruction for 32 bit values.
  1087. \param [in] value Value to store
  1088. \param [in] ptr Pointer to location
  1089. \return 0 Function succeeded
  1090. \return 1 Function failed
  1091. */
  1092. #define __STLEX (uint32_t)__builtin_arm_stlex
  1093. #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
  1094. (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
  1095. /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
  1096. /* ################### Compiler specific Intrinsics ########################### */
  1097. /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
  1098. Access to dedicated SIMD instructions
  1099. @{
  1100. */
  1101. #if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
  1102. __STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
  1103. {
  1104. uint32_t result;
  1105. __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1106. return(result);
  1107. }
  1108. __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
  1109. {
  1110. uint32_t result;
  1111. __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1112. return(result);
  1113. }
  1114. __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
  1115. {
  1116. uint32_t result;
  1117. __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1118. return(result);
  1119. }
  1120. __STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
  1121. {
  1122. uint32_t result;
  1123. __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1124. return(result);
  1125. }
  1126. __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
  1127. {
  1128. uint32_t result;
  1129. __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1130. return(result);
  1131. }
  1132. __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
  1133. {
  1134. uint32_t result;
  1135. __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1136. return(result);
  1137. }
  1138. __STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
  1139. {
  1140. uint32_t result;
  1141. __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1142. return(result);
  1143. }
  1144. __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
  1145. {
  1146. uint32_t result;
  1147. __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1148. return(result);
  1149. }
  1150. __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
  1151. {
  1152. uint32_t result;
  1153. __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1154. return(result);
  1155. }
  1156. __STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
  1157. {
  1158. uint32_t result;
  1159. __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1160. return(result);
  1161. }
  1162. __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
  1163. {
  1164. uint32_t result;
  1165. __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1166. return(result);
  1167. }
  1168. __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
  1169. {
  1170. uint32_t result;
  1171. __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1172. return(result);
  1173. }
  1174. __STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
  1175. {
  1176. uint32_t result;
  1177. __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1178. return(result);
  1179. }
  1180. __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
  1181. {
  1182. uint32_t result;
  1183. __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1184. return(result);
  1185. }
  1186. __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
  1187. {
  1188. uint32_t result;
  1189. __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1190. return(result);
  1191. }
  1192. __STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
  1193. {
  1194. uint32_t result;
  1195. __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1196. return(result);
  1197. }
  1198. __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
  1199. {
  1200. uint32_t result;
  1201. __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1202. return(result);
  1203. }
  1204. __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
  1205. {
  1206. uint32_t result;
  1207. __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1208. return(result);
  1209. }
  1210. __STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
  1211. {
  1212. uint32_t result;
  1213. __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1214. return(result);
  1215. }
  1216. __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
  1217. {
  1218. uint32_t result;
  1219. __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1220. return(result);
  1221. }
  1222. __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
  1223. {
  1224. uint32_t result;
  1225. __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1226. return(result);
  1227. }
  1228. __STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
  1229. {
  1230. uint32_t result;
  1231. __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1232. return(result);
  1233. }
  1234. __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
  1235. {
  1236. uint32_t result;
  1237. __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1238. return(result);
  1239. }
  1240. __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
  1241. {
  1242. uint32_t result;
  1243. __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1244. return(result);
  1245. }
  1246. __STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
  1247. {
  1248. uint32_t result;
  1249. __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1250. return(result);
  1251. }
  1252. __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
  1253. {
  1254. uint32_t result;
  1255. __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1256. return(result);
  1257. }
  1258. __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
  1259. {
  1260. uint32_t result;
  1261. __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1262. return(result);
  1263. }
  1264. __STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
  1265. {
  1266. uint32_t result;
  1267. __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1268. return(result);
  1269. }
  1270. __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
  1271. {
  1272. uint32_t result;
  1273. __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1274. return(result);
  1275. }
  1276. __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
  1277. {
  1278. uint32_t result;
  1279. __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1280. return(result);
  1281. }
  1282. __STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
  1283. {
  1284. uint32_t result;
  1285. __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1286. return(result);
  1287. }
  1288. __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
  1289. {
  1290. uint32_t result;
  1291. __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1292. return(result);
  1293. }
  1294. __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
  1295. {
  1296. uint32_t result;
  1297. __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1298. return(result);
  1299. }
  1300. __STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
  1301. {
  1302. uint32_t result;
  1303. __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1304. return(result);
  1305. }
  1306. __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
  1307. {
  1308. uint32_t result;
  1309. __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1310. return(result);
  1311. }
  1312. __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
  1313. {
  1314. uint32_t result;
  1315. __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1316. return(result);
  1317. }
  1318. __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
  1319. {
  1320. uint32_t result;
  1321. __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1322. return(result);
  1323. }
  1324. __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
  1325. {
  1326. uint32_t result;
  1327. __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1328. return(result);
  1329. }
  1330. #define __SSAT16(ARG1,ARG2) \
  1331. ({ \
  1332. int32_t __RES, __ARG1 = (ARG1); \
  1333. __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1334. __RES; \
  1335. })
  1336. #define __USAT16(ARG1,ARG2) \
  1337. ({ \
  1338. uint32_t __RES, __ARG1 = (ARG1); \
  1339. __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
  1340. __RES; \
  1341. })
  1342. __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
  1343. {
  1344. uint32_t result;
  1345. __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
  1346. return(result);
  1347. }
  1348. __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
  1349. {
  1350. uint32_t result;
  1351. __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1352. return(result);
  1353. }
  1354. __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
  1355. {
  1356. uint32_t result;
  1357. __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
  1358. return(result);
  1359. }
  1360. __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
  1361. {
  1362. uint32_t result;
  1363. __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1364. return(result);
  1365. }
  1366. __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
  1367. {
  1368. uint32_t result;
  1369. __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1370. return(result);
  1371. }
  1372. __STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
  1373. {
  1374. uint32_t result;
  1375. __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1376. return(result);
  1377. }
  1378. __STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
  1379. {
  1380. uint32_t result;
  1381. __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1382. return(result);
  1383. }
  1384. __STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
  1385. {
  1386. uint32_t result;
  1387. __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1388. return(result);
  1389. }
  1390. __STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
  1391. {
  1392. union llreg_u{
  1393. uint32_t w32[2];
  1394. uint64_t w64;
  1395. } llr;
  1396. llr.w64 = acc;
  1397. #ifndef __ARMEB__ /* Little endian */
  1398. __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1399. #else /* Big endian */
  1400. __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1401. #endif
  1402. return(llr.w64);
  1403. }
  1404. __STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
  1405. {
  1406. union llreg_u{
  1407. uint32_t w32[2];
  1408. uint64_t w64;
  1409. } llr;
  1410. llr.w64 = acc;
  1411. #ifndef __ARMEB__ /* Little endian */
  1412. __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1413. #else /* Big endian */
  1414. __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1415. #endif
  1416. return(llr.w64);
  1417. }
  1418. __STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
  1419. {
  1420. uint32_t result;
  1421. __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1422. return(result);
  1423. }
  1424. __STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
  1425. {
  1426. uint32_t result;
  1427. __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1428. return(result);
  1429. }
  1430. __STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
  1431. {
  1432. uint32_t result;
  1433. __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1434. return(result);
  1435. }
  1436. __STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
  1437. {
  1438. uint32_t result;
  1439. __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
  1440. return(result);
  1441. }
  1442. __STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
  1443. {
  1444. union llreg_u{
  1445. uint32_t w32[2];
  1446. uint64_t w64;
  1447. } llr;
  1448. llr.w64 = acc;
  1449. #ifndef __ARMEB__ /* Little endian */
  1450. __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1451. #else /* Big endian */
  1452. __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1453. #endif
  1454. return(llr.w64);
  1455. }
  1456. __STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
  1457. {
  1458. union llreg_u{
  1459. uint32_t w32[2];
  1460. uint64_t w64;
  1461. } llr;
  1462. llr.w64 = acc;
  1463. #ifndef __ARMEB__ /* Little endian */
  1464. __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
  1465. #else /* Big endian */
  1466. __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
  1467. #endif
  1468. return(llr.w64);
  1469. }
  1470. __STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
  1471. {
  1472. uint32_t result;
  1473. __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1474. return(result);
  1475. }
  1476. __STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2)
  1477. {
  1478. int32_t result;
  1479. __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1480. return(result);
  1481. }
  1482. __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2)
  1483. {
  1484. int32_t result;
  1485. __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
  1486. return(result);
  1487. }
  1488. #if 0
  1489. #define __PKHBT(ARG1,ARG2,ARG3) \
  1490. ({ \
  1491. uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
  1492. __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
  1493. __RES; \
  1494. })
  1495. #define __PKHTB(ARG1,ARG2,ARG3) \
  1496. ({ \
  1497. uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
  1498. if (ARG3 == 0) \
  1499. __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
  1500. else \
  1501. __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
  1502. __RES; \
  1503. })
  1504. #endif
  1505. #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
  1506. ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
  1507. #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
  1508. ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
  1509. __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
  1510. {
  1511. int32_t result;
  1512. __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
  1513. return(result);
  1514. }
  1515. #endif /* (__ARM_FEATURE_DSP == 1) */
  1516. /*@} end of group CMSIS_SIMD_intrinsics */
  1517. #endif /* __CMSIS_ARMCLANG_H */