projekt_wuest_steiner/RTC/Debug/RTC.list

RTC.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   0000013c  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000024a8  0800013c  0800013c  0001013c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000024  080025e4  080025e4  000125e4  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08002608  08002608  0002000c  2**0
                  CONTENTS
  4 .ARM          00000008  08002608  08002608  00012608  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08002610  08002610  0002000c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08002610  08002610  00012610  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  08002614  08002614  00012614  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000000c  20000000  08002618  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000098  2000000c  08002624  0002000c  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  200000a4  08002624  000200a4  2**0
                  ALLOC
 11 .ARM.attributes 00000029  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
 12 .debug_info   00006999  00000000  00000000  00020035  2**0
                  CONTENTS, READONLY, DEBUGGING
 13 .debug_abbrev 00001431  00000000  00000000  000269ce  2**0
                  CONTENTS, READONLY, DEBUGGING
 14 .debug_aranges 000006f8  00000000  00000000  00027e00  2**3
                  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges 00000640  00000000  00000000  000284f8  2**3
                  CONTENTS, READONLY, DEBUGGING
 16 .debug_macro  00015151  00000000  00000000  00028b38  2**0
                  CONTENTS, READONLY, DEBUGGING
 17 .debug_line   000062c4  00000000  00000000  0003dc89  2**0
                  CONTENTS, READONLY, DEBUGGING
 18 .debug_str    000859c4  00000000  00000000  00043f4d  2**0
                  CONTENTS, READONLY, DEBUGGING
 19 .comment      0000007b  00000000  00000000  000c9911  2**0
                  CONTENTS, READONLY
 20 .debug_frame  00001b48  00000000  00000000  000c998c  2**2
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

0800013c <__do_global_dtors_aux>:
 800013c:	b510      	push	{r4, lr}
 800013e:	4c05      	ldr	r4, [pc, #20]	; (8000154 <__do_global_dtors_aux+0x18>)
 8000140:	7823      	ldrb	r3, [r4, #0]
 8000142:	b933      	cbnz	r3, 8000152 <__do_global_dtors_aux+0x16>
 8000144:	4b04      	ldr	r3, [pc, #16]	; (8000158 <__do_global_dtors_aux+0x1c>)
 8000146:	b113      	cbz	r3, 800014e <__do_global_dtors_aux+0x12>
 8000148:	4804      	ldr	r0, [pc, #16]	; (800015c <__do_global_dtors_aux+0x20>)
 800014a:	f3af 8000 	nop.w
 800014e:	2301      	movs	r3, #1
 8000150:	7023      	strb	r3, [r4, #0]
 8000152:	bd10      	pop	{r4, pc}
 8000154:	2000000c 	.word	0x2000000c
 8000158:	00000000 	.word	0x00000000
 800015c:	080025cc 	.word	0x080025cc

08000160 <frame_dummy>:
 8000160:	b508      	push	{r3, lr}
 8000162:	4b03      	ldr	r3, [pc, #12]	; (8000170 <frame_dummy+0x10>)
 8000164:	b11b      	cbz	r3, 800016e <frame_dummy+0xe>
 8000166:	4903      	ldr	r1, [pc, #12]	; (8000174 <frame_dummy+0x14>)
 8000168:	4803      	ldr	r0, [pc, #12]	; (8000178 <frame_dummy+0x18>)
 800016a:	f3af 8000 	nop.w
 800016e:	bd08      	pop	{r3, pc}
 8000170:	00000000 	.word	0x00000000
 8000174:	20000010 	.word	0x20000010
 8000178:	080025cc 	.word	0x080025cc

0800017c <__aeabi_uldivmod>:
 800017c:	b953      	cbnz	r3, 8000194 <__aeabi_uldivmod+0x18>
 800017e:	b94a      	cbnz	r2, 8000194 <__aeabi_uldivmod+0x18>
 8000180:	2900      	cmp	r1, #0
 8000182:	bf08      	it	eq
 8000184:	2800      	cmpeq	r0, #0
 8000186:	bf1c      	itt	ne
 8000188:	f04f 31ff 	movne.w	r1, #4294967295
 800018c:	f04f 30ff 	movne.w	r0, #4294967295
 8000190:	f000 b974 	b.w	800047c <__aeabi_idiv0>
 8000194:	f1ad 0c08 	sub.w	ip, sp, #8
 8000198:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 800019c:	f000 f806 	bl	80001ac <__udivmoddi4>
 80001a0:	f8dd e004 	ldr.w	lr, [sp, #4]
 80001a4:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 80001a8:	b004      	add	sp, #16
 80001aa:	4770      	bx	lr

080001ac <__udivmoddi4>:
 80001ac:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 80001b0:	468c      	mov	ip, r1
 80001b2:	4604      	mov	r4, r0
 80001b4:	9e08      	ldr	r6, [sp, #32]
 80001b6:	2b00      	cmp	r3, #0
 80001b8:	d14b      	bne.n	8000252 <__udivmoddi4+0xa6>
 80001ba:	428a      	cmp	r2, r1
 80001bc:	4615      	mov	r5, r2
 80001be:	d967      	bls.n	8000290 <__udivmoddi4+0xe4>
 80001c0:	fab2 f282 	clz	r2, r2
 80001c4:	b14a      	cbz	r2, 80001da <__udivmoddi4+0x2e>
 80001c6:	f1c2 0720 	rsb	r7, r2, #32
 80001ca:	fa01 f302 	lsl.w	r3, r1, r2
 80001ce:	fa20 f707 	lsr.w	r7, r0, r7
 80001d2:	4095      	lsls	r5, r2
 80001d4:	ea47 0c03 	orr.w	ip, r7, r3
 80001d8:	4094      	lsls	r4, r2
 80001da:	ea4f 4e15 	mov.w	lr, r5, lsr #16
 80001de:	fbbc f7fe 	udiv	r7, ip, lr
 80001e2:	fa1f f885 	uxth.w	r8, r5
 80001e6:	fb0e c317 	mls	r3, lr, r7, ip
 80001ea:	fb07 f908 	mul.w	r9, r7, r8
 80001ee:	0c21      	lsrs	r1, r4, #16
 80001f0:	ea41 4303 	orr.w	r3, r1, r3, lsl #16
 80001f4:	4599      	cmp	r9, r3
 80001f6:	d909      	bls.n	800020c <__udivmoddi4+0x60>
 80001f8:	18eb      	adds	r3, r5, r3
 80001fa:	f107 31ff 	add.w	r1, r7, #4294967295
 80001fe:	f080 811c 	bcs.w	800043a <__udivmoddi4+0x28e>
 8000202:	4599      	cmp	r9, r3
 8000204:	f240 8119 	bls.w	800043a <__udivmoddi4+0x28e>
 8000208:	3f02      	subs	r7, #2
 800020a:	442b      	add	r3, r5
 800020c:	eba3 0309 	sub.w	r3, r3, r9
 8000210:	fbb3 f0fe 	udiv	r0, r3, lr
 8000214:	fb0e 3310 	mls	r3, lr, r0, r3
 8000218:	fb00 f108 	mul.w	r1, r0, r8
 800021c:	b2a4      	uxth	r4, r4
 800021e:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 8000222:	42a1      	cmp	r1, r4
 8000224:	d909      	bls.n	800023a <__udivmoddi4+0x8e>
 8000226:	192c      	adds	r4, r5, r4
 8000228:	f100 33ff 	add.w	r3, r0, #4294967295
 800022c:	f080 8107 	bcs.w	800043e <__udivmoddi4+0x292>
 8000230:	42a1      	cmp	r1, r4
 8000232:	f240 8104 	bls.w	800043e <__udivmoddi4+0x292>
 8000236:	3802      	subs	r0, #2
 8000238:	442c      	add	r4, r5
 800023a:	ea40 4007 	orr.w	r0, r0, r7, lsl #16
 800023e:	2700      	movs	r7, #0
 8000240:	1a64      	subs	r4, r4, r1
 8000242:	b11e      	cbz	r6, 800024c <__udivmoddi4+0xa0>
 8000244:	2300      	movs	r3, #0
 8000246:	40d4      	lsrs	r4, r2
 8000248:	e9c6 4300 	strd	r4, r3, [r6]
 800024c:	4639      	mov	r1, r7
 800024e:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000252:	428b      	cmp	r3, r1
 8000254:	d909      	bls.n	800026a <__udivmoddi4+0xbe>
 8000256:	2e00      	cmp	r6, #0
 8000258:	f000 80ec 	beq.w	8000434 <__udivmoddi4+0x288>
 800025c:	2700      	movs	r7, #0
 800025e:	e9c6 0100 	strd	r0, r1, [r6]
 8000262:	4638      	mov	r0, r7
 8000264:	4639      	mov	r1, r7
 8000266:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 800026a:	fab3 f783 	clz	r7, r3
 800026e:	2f00      	cmp	r7, #0
 8000270:	d148      	bne.n	8000304 <__udivmoddi4+0x158>
 8000272:	428b      	cmp	r3, r1
 8000274:	d302      	bcc.n	800027c <__udivmoddi4+0xd0>
 8000276:	4282      	cmp	r2, r0
 8000278:	f200 80fb 	bhi.w	8000472 <__udivmoddi4+0x2c6>
 800027c:	1a84      	subs	r4, r0, r2
 800027e:	eb61 0303 	sbc.w	r3, r1, r3
 8000282:	2001      	movs	r0, #1
 8000284:	469c      	mov	ip, r3
 8000286:	2e00      	cmp	r6, #0
 8000288:	d0e0      	beq.n	800024c <__udivmoddi4+0xa0>
 800028a:	e9c6 4c00 	strd	r4, ip, [r6]
 800028e:	e7dd      	b.n	800024c <__udivmoddi4+0xa0>
 8000290:	b902      	cbnz	r2, 8000294 <__udivmoddi4+0xe8>
 8000292:	deff      	udf	#255	; 0xff
 8000294:	fab2 f282 	clz	r2, r2
 8000298:	2a00      	cmp	r2, #0
 800029a:	f040 808f 	bne.w	80003bc <__udivmoddi4+0x210>
 800029e:	2701      	movs	r7, #1
 80002a0:	1b49      	subs	r1, r1, r5
 80002a2:	ea4f 4815 	mov.w	r8, r5, lsr #16
 80002a6:	fa1f f985 	uxth.w	r9, r5
 80002aa:	fbb1 fef8 	udiv	lr, r1, r8
 80002ae:	fb08 111e 	mls	r1, r8, lr, r1
 80002b2:	fb09 f00e 	mul.w	r0, r9, lr
 80002b6:	ea4f 4c14 	mov.w	ip, r4, lsr #16
 80002ba:	ea4c 4301 	orr.w	r3, ip, r1, lsl #16
 80002be:	4298      	cmp	r0, r3
 80002c0:	d907      	bls.n	80002d2 <__udivmoddi4+0x126>
 80002c2:	18eb      	adds	r3, r5, r3
 80002c4:	f10e 31ff 	add.w	r1, lr, #4294967295
 80002c8:	d202      	bcs.n	80002d0 <__udivmoddi4+0x124>
 80002ca:	4298      	cmp	r0, r3
 80002cc:	f200 80cd 	bhi.w	800046a <__udivmoddi4+0x2be>
 80002d0:	468e      	mov	lr, r1
 80002d2:	1a1b      	subs	r3, r3, r0
 80002d4:	fbb3 f0f8 	udiv	r0, r3, r8
 80002d8:	fb08 3310 	mls	r3, r8, r0, r3
 80002dc:	fb09 f900 	mul.w	r9, r9, r0
 80002e0:	b2a4      	uxth	r4, r4
 80002e2:	ea44 4403 	orr.w	r4, r4, r3, lsl #16
 80002e6:	45a1      	cmp	r9, r4
 80002e8:	d907      	bls.n	80002fa <__udivmoddi4+0x14e>
 80002ea:	192c      	adds	r4, r5, r4
 80002ec:	f100 33ff 	add.w	r3, r0, #4294967295
 80002f0:	d202      	bcs.n	80002f8 <__udivmoddi4+0x14c>
 80002f2:	45a1      	cmp	r9, r4
 80002f4:	f200 80b6 	bhi.w	8000464 <__udivmoddi4+0x2b8>
 80002f8:	4618      	mov	r0, r3
 80002fa:	eba4 0409 	sub.w	r4, r4, r9
 80002fe:	ea40 400e 	orr.w	r0, r0, lr, lsl #16
 8000302:	e79e      	b.n	8000242 <__udivmoddi4+0x96>
 8000304:	f1c7 0520 	rsb	r5, r7, #32
 8000308:	40bb      	lsls	r3, r7
 800030a:	fa22 fc05 	lsr.w	ip, r2, r5
 800030e:	ea4c 0c03 	orr.w	ip, ip, r3
 8000312:	fa21 f405 	lsr.w	r4, r1, r5
 8000316:	ea4f 4e1c 	mov.w	lr, ip, lsr #16
 800031a:	fbb4 f9fe 	udiv	r9, r4, lr
 800031e:	fa1f f88c 	uxth.w	r8, ip
 8000322:	fb0e 4419 	mls	r4, lr, r9, r4
 8000326:	fa20 f305 	lsr.w	r3, r0, r5
 800032a:	40b9      	lsls	r1, r7
 800032c:	fb09 fa08 	mul.w	sl, r9, r8
 8000330:	4319      	orrs	r1, r3
 8000332:	0c0b      	lsrs	r3, r1, #16
 8000334:	ea43 4404 	orr.w	r4, r3, r4, lsl #16
 8000338:	45a2      	cmp	sl, r4
 800033a:	fa02 f207 	lsl.w	r2, r2, r7
 800033e:	fa00 f307 	lsl.w	r3, r0, r7
 8000342:	d90b      	bls.n	800035c <__udivmoddi4+0x1b0>
 8000344:	eb1c 0404 	adds.w	r4, ip, r4
 8000348:	f109 30ff 	add.w	r0, r9, #4294967295
 800034c:	f080 8088 	bcs.w	8000460 <__udivmoddi4+0x2b4>
 8000350:	45a2      	cmp	sl, r4
 8000352:	f240 8085 	bls.w	8000460 <__udivmoddi4+0x2b4>
 8000356:	f1a9 0902 	sub.w	r9, r9, #2
 800035a:	4464      	add	r4, ip
 800035c:	eba4 040a 	sub.w	r4, r4, sl
 8000360:	fbb4 f0fe 	udiv	r0, r4, lr
 8000364:	fb0e 4410 	mls	r4, lr, r0, r4
 8000368:	fb00 fa08 	mul.w	sl, r0, r8
 800036c:	b289      	uxth	r1, r1
 800036e:	ea41 4404 	orr.w	r4, r1, r4, lsl #16
 8000372:	45a2      	cmp	sl, r4
 8000374:	d908      	bls.n	8000388 <__udivmoddi4+0x1dc>
 8000376:	eb1c 0404 	adds.w	r4, ip, r4
 800037a:	f100 31ff 	add.w	r1, r0, #4294967295
 800037e:	d26b      	bcs.n	8000458 <__udivmoddi4+0x2ac>
 8000380:	45a2      	cmp	sl, r4
 8000382:	d969      	bls.n	8000458 <__udivmoddi4+0x2ac>
 8000384:	3802      	subs	r0, #2
 8000386:	4464      	add	r4, ip
 8000388:	ea40 4009 	orr.w	r0, r0, r9, lsl #16
 800038c:	fba0 8902 	umull	r8, r9, r0, r2
 8000390:	eba4 040a 	sub.w	r4, r4, sl
 8000394:	454c      	cmp	r4, r9
 8000396:	4641      	mov	r1, r8
 8000398:	46ce      	mov	lr, r9
 800039a:	d354      	bcc.n	8000446 <__udivmoddi4+0x29a>
 800039c:	d051      	beq.n	8000442 <__udivmoddi4+0x296>
 800039e:	2e00      	cmp	r6, #0
 80003a0:	d069      	beq.n	8000476 <__udivmoddi4+0x2ca>
 80003a2:	1a5a      	subs	r2, r3, r1
 80003a4:	eb64 040e 	sbc.w	r4, r4, lr
 80003a8:	fa04 f505 	lsl.w	r5, r4, r5
 80003ac:	fa22 f307 	lsr.w	r3, r2, r7
 80003b0:	40fc      	lsrs	r4, r7
 80003b2:	431d      	orrs	r5, r3
 80003b4:	e9c6 5400 	strd	r5, r4, [r6]
 80003b8:	2700      	movs	r7, #0
 80003ba:	e747      	b.n	800024c <__udivmoddi4+0xa0>
 80003bc:	4095      	lsls	r5, r2
 80003be:	f1c2 0320 	rsb	r3, r2, #32
 80003c2:	fa21 f003 	lsr.w	r0, r1, r3
 80003c6:	ea4f 4815 	mov.w	r8, r5, lsr #16
 80003ca:	fbb0 f7f8 	udiv	r7, r0, r8
 80003ce:	fa1f f985 	uxth.w	r9, r5
 80003d2:	fb08 0017 	mls	r0, r8, r7, r0
 80003d6:	fa24 f303 	lsr.w	r3, r4, r3
 80003da:	4091      	lsls	r1, r2
 80003dc:	fb07 fc09 	mul.w	ip, r7, r9
 80003e0:	430b      	orrs	r3, r1
 80003e2:	0c19      	lsrs	r1, r3, #16
 80003e4:	ea41 4100 	orr.w	r1, r1, r0, lsl #16
 80003e8:	458c      	cmp	ip, r1
 80003ea:	fa04 f402 	lsl.w	r4, r4, r2
 80003ee:	d907      	bls.n	8000400 <__udivmoddi4+0x254>
 80003f0:	1869      	adds	r1, r5, r1
 80003f2:	f107 30ff 	add.w	r0, r7, #4294967295
 80003f6:	d231      	bcs.n	800045c <__udivmoddi4+0x2b0>
 80003f8:	458c      	cmp	ip, r1
 80003fa:	d92f      	bls.n	800045c <__udivmoddi4+0x2b0>
 80003fc:	3f02      	subs	r7, #2
 80003fe:	4429      	add	r1, r5
 8000400:	eba1 010c 	sub.w	r1, r1, ip
 8000404:	fbb1 f0f8 	udiv	r0, r1, r8
 8000408:	fb08 1c10 	mls	ip, r8, r0, r1
 800040c:	fb00 fe09 	mul.w	lr, r0, r9
 8000410:	b299      	uxth	r1, r3
 8000412:	ea41 410c 	orr.w	r1, r1, ip, lsl #16
 8000416:	458e      	cmp	lr, r1
 8000418:	d907      	bls.n	800042a <__udivmoddi4+0x27e>
 800041a:	1869      	adds	r1, r5, r1
 800041c:	f100 33ff 	add.w	r3, r0, #4294967295
 8000420:	d218      	bcs.n	8000454 <__udivmoddi4+0x2a8>
 8000422:	458e      	cmp	lr, r1
 8000424:	d916      	bls.n	8000454 <__udivmoddi4+0x2a8>
 8000426:	3802      	subs	r0, #2
 8000428:	4429      	add	r1, r5
 800042a:	eba1 010e 	sub.w	r1, r1, lr
 800042e:	ea40 4707 	orr.w	r7, r0, r7, lsl #16
 8000432:	e73a      	b.n	80002aa <__udivmoddi4+0xfe>
 8000434:	4637      	mov	r7, r6
 8000436:	4630      	mov	r0, r6
 8000438:	e708      	b.n	800024c <__udivmoddi4+0xa0>
 800043a:	460f      	mov	r7, r1
 800043c:	e6e6      	b.n	800020c <__udivmoddi4+0x60>
 800043e:	4618      	mov	r0, r3
 8000440:	e6fb      	b.n	800023a <__udivmoddi4+0x8e>
 8000442:	4543      	cmp	r3, r8
 8000444:	d2ab      	bcs.n	800039e <__udivmoddi4+0x1f2>
 8000446:	ebb8 0102 	subs.w	r1, r8, r2
 800044a:	eb69 020c 	sbc.w	r2, r9, ip
 800044e:	3801      	subs	r0, #1
 8000450:	4696      	mov	lr, r2
 8000452:	e7a4      	b.n	800039e <__udivmoddi4+0x1f2>
 8000454:	4618      	mov	r0, r3
 8000456:	e7e8      	b.n	800042a <__udivmoddi4+0x27e>
 8000458:	4608      	mov	r0, r1
 800045a:	e795      	b.n	8000388 <__udivmoddi4+0x1dc>
 800045c:	4607      	mov	r7, r0
 800045e:	e7cf      	b.n	8000400 <__udivmoddi4+0x254>
 8000460:	4681      	mov	r9, r0
 8000462:	e77b      	b.n	800035c <__udivmoddi4+0x1b0>
 8000464:	3802      	subs	r0, #2
 8000466:	442c      	add	r4, r5
 8000468:	e747      	b.n	80002fa <__udivmoddi4+0x14e>
 800046a:	f1ae 0e02 	sub.w	lr, lr, #2
 800046e:	442b      	add	r3, r5
 8000470:	e72f      	b.n	80002d2 <__udivmoddi4+0x126>
 8000472:	4638      	mov	r0, r7
 8000474:	e707      	b.n	8000286 <__udivmoddi4+0xda>
 8000476:	4637      	mov	r7, r6
 8000478:	e6e8      	b.n	800024c <__udivmoddi4+0xa0>
 800047a:	bf00      	nop

0800047c <__aeabi_idiv0>:
 800047c:	4770      	bx	lr
 800047e:	bf00      	nop

08000480 <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 8000480:	b580      	push	{r7, lr}
 8000482:	b082      	sub	sp, #8
 8000484:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000486:	f000 fa7e 	bl	8000986 <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 800048a:	f000 f843 	bl	8000514 <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 800048e:	f000 f927 	bl	80006e0 <MX_GPIO_Init>
  MX_USART2_UART_Init();
 8000492:	f000 f8fb 	bl	800068c <MX_USART2_UART_Init>
  MX_RTC_Init();
 8000496:	f000 f8a1 	bl	80005dc <MX_RTC_Init>
  /* USER CODE BEGIN 2 */
  uint8_t hours = 0;
 800049a:	2300      	movs	r3, #0
 800049c:	71fb      	strb	r3, [r7, #7]
  uint8_t minutes = 0;
 800049e:	2300      	movs	r3, #0
 80004a0:	71bb      	strb	r3, [r7, #6]
  uint8_t seconds = 0;
 80004a2:	2300      	movs	r3, #0
 80004a4:	717b      	strb	r3, [r7, #5]
  uint8_t weekDay = 0;
 80004a6:	2300      	movs	r3, #0
 80004a8:	713b      	strb	r3, [r7, #4]
  uint8_t month = 0;
 80004aa:	2300      	movs	r3, #0
 80004ac:	70fb      	strb	r3, [r7, #3]
  uint8_t date = 0;
 80004ae:	2300      	movs	r3, #0
 80004b0:	70bb      	strb	r3, [r7, #2]
  uint8_t year = 0;
 80004b2:	2300      	movs	r3, #0
 80004b4:	707b      	strb	r3, [r7, #1]
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
  while (1)
  {
    /* USER CODE END WHILE */
	  if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK)
 80004b6:	2200      	movs	r2, #0
 80004b8:	4913      	ldr	r1, [pc, #76]	; (8000508 <main+0x88>)
 80004ba:	4814      	ldr	r0, [pc, #80]	; (800050c <main+0x8c>)
 80004bc:	f001 fd4f 	bl	8001f5e <HAL_RTC_GetTime>
 80004c0:	4603      	mov	r3, r0
 80004c2:	2b00      	cmp	r3, #0
 80004c4:	d108      	bne.n	80004d8 <main+0x58>
	    {
	      hours = sTime.Hours;
 80004c6:	4b10      	ldr	r3, [pc, #64]	; (8000508 <main+0x88>)
 80004c8:	781b      	ldrb	r3, [r3, #0]
 80004ca:	71fb      	strb	r3, [r7, #7]
	      minutes = sTime.Minutes;
 80004cc:	4b0e      	ldr	r3, [pc, #56]	; (8000508 <main+0x88>)
 80004ce:	785b      	ldrb	r3, [r3, #1]
 80004d0:	71bb      	strb	r3, [r7, #6]
	      seconds = sTime.Seconds;
 80004d2:	4b0d      	ldr	r3, [pc, #52]	; (8000508 <main+0x88>)
 80004d4:	789b      	ldrb	r3, [r3, #2]
 80004d6:	717b      	strb	r3, [r7, #5]
	    }
	  if (HAL_RTC_GetDate(&hrtc, &sDate, RTC_FORMAT_BIN) == HAL_OK)
 80004d8:	2200      	movs	r2, #0
 80004da:	490d      	ldr	r1, [pc, #52]	; (8000510 <main+0x90>)
 80004dc:	480b      	ldr	r0, [pc, #44]	; (800050c <main+0x8c>)
 80004de:	f001 fe39 	bl	8002154 <HAL_RTC_GetDate>
 80004e2:	4603      	mov	r3, r0
 80004e4:	2b00      	cmp	r3, #0
 80004e6:	d10b      	bne.n	8000500 <main+0x80>
	    {
		  weekDay = sDate.WeekDay;
 80004e8:	4b09      	ldr	r3, [pc, #36]	; (8000510 <main+0x90>)
 80004ea:	781b      	ldrb	r3, [r3, #0]
 80004ec:	713b      	strb	r3, [r7, #4]
		  month = sDate.Month;
 80004ee:	4b08      	ldr	r3, [pc, #32]	; (8000510 <main+0x90>)
 80004f0:	785b      	ldrb	r3, [r3, #1]
 80004f2:	70fb      	strb	r3, [r7, #3]
		  date = sDate.Date;
 80004f4:	4b06      	ldr	r3, [pc, #24]	; (8000510 <main+0x90>)
 80004f6:	789b      	ldrb	r3, [r3, #2]
 80004f8:	70bb      	strb	r3, [r7, #2]
		  year = sDate.Year;
 80004fa:	4b05      	ldr	r3, [pc, #20]	; (8000510 <main+0x90>)
 80004fc:	78db      	ldrb	r3, [r3, #3]
 80004fe:	707b      	strb	r3, [r7, #1]
	    }
	  HAL_Delay(200);
 8000500:	20c8      	movs	r0, #200	; 0xc8
 8000502:	f000 faaf 	bl	8000a64 <HAL_Delay>
	  if (HAL_RTC_GetTime(&hrtc, &sTime, RTC_FORMAT_BIN) == HAL_OK)
 8000506:	e7d6      	b.n	80004b6 <main+0x36>
 8000508:	20000028 	.word	0x20000028
 800050c:	20000040 	.word	0x20000040
 8000510:	2000003c 	.word	0x2000003c

08000514 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8000514:	b580      	push	{r7, lr}
 8000516:	b096      	sub	sp, #88	; 0x58
 8000518:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 800051a:	f107 0324 	add.w	r3, r7, #36	; 0x24
 800051e:	2234      	movs	r2, #52	; 0x34
 8000520:	2100      	movs	r1, #0
 8000522:	4618      	mov	r0, r3
 8000524:	f002 f84a 	bl	80025bc <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8000528:	f107 0310 	add.w	r3, r7, #16
 800052c:	2200      	movs	r2, #0
 800052e:	601a      	str	r2, [r3, #0]
 8000530:	605a      	str	r2, [r3, #4]
 8000532:	609a      	str	r2, [r3, #8]
 8000534:	60da      	str	r2, [r3, #12]
 8000536:	611a      	str	r2, [r3, #16]
  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
 8000538:	1d3b      	adds	r3, r7, #4
 800053a:	2200      	movs	r2, #0
 800053c:	601a      	str	r2, [r3, #0]
 800053e:	605a      	str	r2, [r3, #4]
 8000540:	609a      	str	r2, [r3, #8]

  /** Configure the main internal regulator output voltage
  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 8000542:	4b25      	ldr	r3, [pc, #148]	; (80005d8 <SystemClock_Config+0xc4>)
 8000544:	681b      	ldr	r3, [r3, #0]
 8000546:	f423 53c0 	bic.w	r3, r3, #6144	; 0x1800
 800054a:	4a23      	ldr	r2, [pc, #140]	; (80005d8 <SystemClock_Config+0xc4>)
 800054c:	f443 6300 	orr.w	r3, r3, #2048	; 0x800
 8000550:	6013      	str	r3, [r2, #0]
  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSE;
 8000552:	2306      	movs	r3, #6
 8000554:	627b      	str	r3, [r7, #36]	; 0x24
  RCC_OscInitStruct.LSEState = RCC_LSE_ON;
 8000556:	2301      	movs	r3, #1
 8000558:	62fb      	str	r3, [r7, #44]	; 0x2c
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 800055a:	2301      	movs	r3, #1
 800055c:	633b      	str	r3, [r7, #48]	; 0x30
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 800055e:	2310      	movs	r3, #16
 8000560:	637b      	str	r3, [r7, #52]	; 0x34
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8000562:	2302      	movs	r3, #2
 8000564:	64bb      	str	r3, [r7, #72]	; 0x48
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 8000566:	2300      	movs	r3, #0
 8000568:	64fb      	str	r3, [r7, #76]	; 0x4c
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
 800056a:	f44f 2300 	mov.w	r3, #524288	; 0x80000
 800056e:	653b      	str	r3, [r7, #80]	; 0x50
  RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
 8000570:	f44f 0300 	mov.w	r3, #8388608	; 0x800000
 8000574:	657b      	str	r3, [r7, #84]	; 0x54
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8000576:	f107 0324 	add.w	r3, r7, #36	; 0x24
 800057a:	4618      	mov	r0, r3
 800057c:	f000 fd1e 	bl	8000fbc <HAL_RCC_OscConfig>
 8000580:	4603      	mov	r3, r0
 8000582:	2b00      	cmp	r3, #0
 8000584:	d001      	beq.n	800058a <SystemClock_Config+0x76>
  {
    Error_Handler();
 8000586:	f000 f913 	bl	80007b0 <Error_Handler>
  }
  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800058a:	230f      	movs	r3, #15
 800058c:	613b      	str	r3, [r7, #16]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 800058e:	2303      	movs	r3, #3
 8000590:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8000592:	2300      	movs	r3, #0
 8000594:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 8000596:	2300      	movs	r3, #0
 8000598:	61fb      	str	r3, [r7, #28]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 800059a:	2300      	movs	r3, #0
 800059c:	623b      	str	r3, [r7, #32]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 800059e:	f107 0310 	add.w	r3, r7, #16
 80005a2:	2101      	movs	r1, #1
 80005a4:	4618      	mov	r0, r3
 80005a6:	f001 f839 	bl	800161c <HAL_RCC_ClockConfig>
 80005aa:	4603      	mov	r3, r0
 80005ac:	2b00      	cmp	r3, #0
 80005ae:	d001      	beq.n	80005b4 <SystemClock_Config+0xa0>
  {
    Error_Handler();
 80005b0:	f000 f8fe 	bl	80007b0 <Error_Handler>
  }
  PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC;
 80005b4:	2301      	movs	r3, #1
 80005b6:	607b      	str	r3, [r7, #4]
  PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
 80005b8:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 80005bc:	60bb      	str	r3, [r7, #8]
  if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
 80005be:	1d3b      	adds	r3, r7, #4
 80005c0:	4618      	mov	r0, r3
 80005c2:	f001 fabb 	bl	8001b3c <HAL_RCCEx_PeriphCLKConfig>
 80005c6:	4603      	mov	r3, r0
 80005c8:	2b00      	cmp	r3, #0
 80005ca:	d001      	beq.n	80005d0 <SystemClock_Config+0xbc>
  {
    Error_Handler();
 80005cc:	f000 f8f0 	bl	80007b0 <Error_Handler>
  }
}
 80005d0:	bf00      	nop
 80005d2:	3758      	adds	r7, #88	; 0x58
 80005d4:	46bd      	mov	sp, r7
 80005d6:	bd80      	pop	{r7, pc}
 80005d8:	40007000 	.word	0x40007000

080005dc <MX_RTC_Init>:
  * @brief RTC Initialization Function
  * @param None
  * @retval None
  */
static void MX_RTC_Init(void)
{
 80005dc:	b580      	push	{r7, lr}
 80005de:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN RTC_Init 1 */

  /* USER CODE END RTC_Init 1 */
  /** Initialize RTC Only
  */
  hrtc.Instance = RTC;
 80005e0:	4b26      	ldr	r3, [pc, #152]	; (800067c <MX_RTC_Init+0xa0>)
 80005e2:	4a27      	ldr	r2, [pc, #156]	; (8000680 <MX_RTC_Init+0xa4>)
 80005e4:	601a      	str	r2, [r3, #0]
  hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
 80005e6:	4b25      	ldr	r3, [pc, #148]	; (800067c <MX_RTC_Init+0xa0>)
 80005e8:	2200      	movs	r2, #0
 80005ea:	605a      	str	r2, [r3, #4]
  hrtc.Init.AsynchPrediv = 127;
 80005ec:	4b23      	ldr	r3, [pc, #140]	; (800067c <MX_RTC_Init+0xa0>)
 80005ee:	227f      	movs	r2, #127	; 0x7f
 80005f0:	609a      	str	r2, [r3, #8]
  hrtc.Init.SynchPrediv = 255;
 80005f2:	4b22      	ldr	r3, [pc, #136]	; (800067c <MX_RTC_Init+0xa0>)
 80005f4:	22ff      	movs	r2, #255	; 0xff
 80005f6:	60da      	str	r2, [r3, #12]
  hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
 80005f8:	4b20      	ldr	r3, [pc, #128]	; (800067c <MX_RTC_Init+0xa0>)
 80005fa:	2200      	movs	r2, #0
 80005fc:	611a      	str	r2, [r3, #16]
  hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
 80005fe:	4b1f      	ldr	r3, [pc, #124]	; (800067c <MX_RTC_Init+0xa0>)
 8000600:	2200      	movs	r2, #0
 8000602:	615a      	str	r2, [r3, #20]
  hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
 8000604:	4b1d      	ldr	r3, [pc, #116]	; (800067c <MX_RTC_Init+0xa0>)
 8000606:	2200      	movs	r2, #0
 8000608:	619a      	str	r2, [r3, #24]
  if (HAL_RTC_Init(&hrtc) != HAL_OK)
 800060a:	481c      	ldr	r0, [pc, #112]	; (800067c <MX_RTC_Init+0xa0>)
 800060c:	f001 fb78 	bl	8001d00 <HAL_RTC_Init>
 8000610:	4603      	mov	r3, r0
 8000612:	2b00      	cmp	r3, #0
 8000614:	d001      	beq.n	800061a <MX_RTC_Init+0x3e>
  {
    Error_Handler();
 8000616:	f000 f8cb 	bl	80007b0 <Error_Handler>

  /* USER CODE END Check_RTC_BKUP */

  /** Initialize RTC and set the Time and Date
  */
  sTime.Hours = 23;
 800061a:	4b1a      	ldr	r3, [pc, #104]	; (8000684 <MX_RTC_Init+0xa8>)
 800061c:	2217      	movs	r2, #23
 800061e:	701a      	strb	r2, [r3, #0]
  sTime.Minutes = 59;
 8000620:	4b18      	ldr	r3, [pc, #96]	; (8000684 <MX_RTC_Init+0xa8>)
 8000622:	223b      	movs	r2, #59	; 0x3b
 8000624:	705a      	strb	r2, [r3, #1]
  sTime.Seconds = 45;
 8000626:	4b17      	ldr	r3, [pc, #92]	; (8000684 <MX_RTC_Init+0xa8>)
 8000628:	222d      	movs	r2, #45	; 0x2d
 800062a:	709a      	strb	r2, [r3, #2]
  sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
 800062c:	4b15      	ldr	r3, [pc, #84]	; (8000684 <MX_RTC_Init+0xa8>)
 800062e:	2200      	movs	r2, #0
 8000630:	60da      	str	r2, [r3, #12]
  sTime.StoreOperation = RTC_STOREOPERATION_RESET;
 8000632:	4b14      	ldr	r3, [pc, #80]	; (8000684 <MX_RTC_Init+0xa8>)
 8000634:	2200      	movs	r2, #0
 8000636:	611a      	str	r2, [r3, #16]
  if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BIN) != HAL_OK)
 8000638:	2200      	movs	r2, #0
 800063a:	4912      	ldr	r1, [pc, #72]	; (8000684 <MX_RTC_Init+0xa8>)
 800063c:	480f      	ldr	r0, [pc, #60]	; (800067c <MX_RTC_Init+0xa0>)
 800063e:	f001 fbda 	bl	8001df6 <HAL_RTC_SetTime>
 8000642:	4603      	mov	r3, r0
 8000644:	2b00      	cmp	r3, #0
 8000646:	d001      	beq.n	800064c <MX_RTC_Init+0x70>
  {
    Error_Handler();
 8000648:	f000 f8b2 	bl	80007b0 <Error_Handler>
  }
  sDate.WeekDay = RTC_WEEKDAY_SUNDAY;
 800064c:	4b0e      	ldr	r3, [pc, #56]	; (8000688 <MX_RTC_Init+0xac>)
 800064e:	2207      	movs	r2, #7
 8000650:	701a      	strb	r2, [r3, #0]
  sDate.Month = RTC_MONTH_DECEMBER;
 8000652:	4b0d      	ldr	r3, [pc, #52]	; (8000688 <MX_RTC_Init+0xac>)
 8000654:	2212      	movs	r2, #18
 8000656:	705a      	strb	r2, [r3, #1]
  sDate.Date = 31;
 8000658:	4b0b      	ldr	r3, [pc, #44]	; (8000688 <MX_RTC_Init+0xac>)
 800065a:	221f      	movs	r2, #31
 800065c:	709a      	strb	r2, [r3, #2]
  sDate.Year = 17;
 800065e:	4b0a      	ldr	r3, [pc, #40]	; (8000688 <MX_RTC_Init+0xac>)
 8000660:	2211      	movs	r2, #17
 8000662:	70da      	strb	r2, [r3, #3]

  if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BIN) != HAL_OK)
 8000664:	2200      	movs	r2, #0
 8000666:	4908      	ldr	r1, [pc, #32]	; (8000688 <MX_RTC_Init+0xac>)
 8000668:	4804      	ldr	r0, [pc, #16]	; (800067c <MX_RTC_Init+0xa0>)
 800066a:	f001 fcd5 	bl	8002018 <HAL_RTC_SetDate>
 800066e:	4603      	mov	r3, r0
 8000670:	2b00      	cmp	r3, #0
 8000672:	d001      	beq.n	8000678 <MX_RTC_Init+0x9c>
  {
    Error_Handler();
 8000674:	f000 f89c 	bl	80007b0 <Error_Handler>
  }
  /* USER CODE BEGIN RTC_Init 2 */

  /* USER CODE END RTC_Init 2 */

}
 8000678:	bf00      	nop
 800067a:	bd80      	pop	{r7, pc}
 800067c:	20000040 	.word	0x20000040
 8000680:	40002800 	.word	0x40002800
 8000684:	20000028 	.word	0x20000028
 8000688:	2000003c 	.word	0x2000003c

0800068c <MX_USART2_UART_Init>:
  * @brief USART2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART2_UART_Init(void)
{
 800068c:	b580      	push	{r7, lr}
 800068e:	af00      	add	r7, sp, #0
  /* USER CODE END USART2_Init 0 */

  /* USER CODE BEGIN USART2_Init 1 */

  /* USER CODE END USART2_Init 1 */
  huart2.Instance = USART2;
 8000690:	4b11      	ldr	r3, [pc, #68]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 8000692:	4a12      	ldr	r2, [pc, #72]	; (80006dc <MX_USART2_UART_Init+0x50>)
 8000694:	601a      	str	r2, [r3, #0]
  huart2.Init.BaudRate = 115200;
 8000696:	4b10      	ldr	r3, [pc, #64]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 8000698:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 800069c:	605a      	str	r2, [r3, #4]
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 800069e:	4b0e      	ldr	r3, [pc, #56]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006a0:	2200      	movs	r2, #0
 80006a2:	609a      	str	r2, [r3, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 80006a4:	4b0c      	ldr	r3, [pc, #48]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006a6:	2200      	movs	r2, #0
 80006a8:	60da      	str	r2, [r3, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 80006aa:	4b0b      	ldr	r3, [pc, #44]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006ac:	2200      	movs	r2, #0
 80006ae:	611a      	str	r2, [r3, #16]
  huart2.Init.Mode = UART_MODE_TX_RX;
 80006b0:	4b09      	ldr	r3, [pc, #36]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006b2:	220c      	movs	r2, #12
 80006b4:	615a      	str	r2, [r3, #20]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 80006b6:	4b08      	ldr	r3, [pc, #32]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006b8:	2200      	movs	r2, #0
 80006ba:	619a      	str	r2, [r3, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 80006bc:	4b06      	ldr	r3, [pc, #24]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006be:	2200      	movs	r2, #0
 80006c0:	61da      	str	r2, [r3, #28]
  if (HAL_UART_Init(&huart2) != HAL_OK)
 80006c2:	4805      	ldr	r0, [pc, #20]	; (80006d8 <MX_USART2_UART_Init+0x4c>)
 80006c4:	f001 fe24 	bl	8002310 <HAL_UART_Init>
 80006c8:	4603      	mov	r3, r0
 80006ca:	2b00      	cmp	r3, #0
 80006cc:	d001      	beq.n	80006d2 <MX_USART2_UART_Init+0x46>
  {
    Error_Handler();
 80006ce:	f000 f86f 	bl	80007b0 <Error_Handler>
  }
  /* USER CODE BEGIN USART2_Init 2 */

  /* USER CODE END USART2_Init 2 */

}
 80006d2:	bf00      	nop
 80006d4:	bd80      	pop	{r7, pc}
 80006d6:	bf00      	nop
 80006d8:	20000060 	.word	0x20000060
 80006dc:	40004400 	.word	0x40004400

080006e0 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 80006e0:	b580      	push	{r7, lr}
 80006e2:	b08a      	sub	sp, #40	; 0x28
 80006e4:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80006e6:	f107 0314 	add.w	r3, r7, #20
 80006ea:	2200      	movs	r2, #0
 80006ec:	601a      	str	r2, [r3, #0]
 80006ee:	605a      	str	r2, [r3, #4]
 80006f0:	609a      	str	r2, [r3, #8]
 80006f2:	60da      	str	r2, [r3, #12]
 80006f4:	611a      	str	r2, [r3, #16]

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 80006f6:	4b2a      	ldr	r3, [pc, #168]	; (80007a0 <MX_GPIO_Init+0xc0>)
 80006f8:	69db      	ldr	r3, [r3, #28]
 80006fa:	4a29      	ldr	r2, [pc, #164]	; (80007a0 <MX_GPIO_Init+0xc0>)
 80006fc:	f043 0304 	orr.w	r3, r3, #4
 8000700:	61d3      	str	r3, [r2, #28]
 8000702:	4b27      	ldr	r3, [pc, #156]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000704:	69db      	ldr	r3, [r3, #28]
 8000706:	f003 0304 	and.w	r3, r3, #4
 800070a:	613b      	str	r3, [r7, #16]
 800070c:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOH_CLK_ENABLE();
 800070e:	4b24      	ldr	r3, [pc, #144]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000710:	69db      	ldr	r3, [r3, #28]
 8000712:	4a23      	ldr	r2, [pc, #140]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000714:	f043 0320 	orr.w	r3, r3, #32
 8000718:	61d3      	str	r3, [r2, #28]
 800071a:	4b21      	ldr	r3, [pc, #132]	; (80007a0 <MX_GPIO_Init+0xc0>)
 800071c:	69db      	ldr	r3, [r3, #28]
 800071e:	f003 0320 	and.w	r3, r3, #32
 8000722:	60fb      	str	r3, [r7, #12]
 8000724:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 8000726:	4b1e      	ldr	r3, [pc, #120]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000728:	69db      	ldr	r3, [r3, #28]
 800072a:	4a1d      	ldr	r2, [pc, #116]	; (80007a0 <MX_GPIO_Init+0xc0>)
 800072c:	f043 0301 	orr.w	r3, r3, #1
 8000730:	61d3      	str	r3, [r2, #28]
 8000732:	4b1b      	ldr	r3, [pc, #108]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000734:	69db      	ldr	r3, [r3, #28]
 8000736:	f003 0301 	and.w	r3, r3, #1
 800073a:	60bb      	str	r3, [r7, #8]
 800073c:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 800073e:	4b18      	ldr	r3, [pc, #96]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000740:	69db      	ldr	r3, [r3, #28]
 8000742:	4a17      	ldr	r2, [pc, #92]	; (80007a0 <MX_GPIO_Init+0xc0>)
 8000744:	f043 0302 	orr.w	r3, r3, #2
 8000748:	61d3      	str	r3, [r2, #28]
 800074a:	4b15      	ldr	r3, [pc, #84]	; (80007a0 <MX_GPIO_Init+0xc0>)
 800074c:	69db      	ldr	r3, [r3, #28]
 800074e:	f003 0302 	and.w	r3, r3, #2
 8000752:	607b      	str	r3, [r7, #4]
 8000754:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
 8000756:	2200      	movs	r2, #0
 8000758:	2120      	movs	r1, #32
 800075a:	4812      	ldr	r0, [pc, #72]	; (80007a4 <MX_GPIO_Init+0xc4>)
 800075c:	f000 fc16 	bl	8000f8c <HAL_GPIO_WritePin>

  /*Configure GPIO pin : B1_Pin */
  GPIO_InitStruct.Pin = B1_Pin;
 8000760:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8000764:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 8000766:	4b10      	ldr	r3, [pc, #64]	; (80007a8 <MX_GPIO_Init+0xc8>)
 8000768:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 800076a:	2300      	movs	r3, #0
 800076c:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
 800076e:	f107 0314 	add.w	r3, r7, #20
 8000772:	4619      	mov	r1, r3
 8000774:	480d      	ldr	r0, [pc, #52]	; (80007ac <MX_GPIO_Init+0xcc>)
 8000776:	f000 fa7b 	bl	8000c70 <HAL_GPIO_Init>

  /*Configure GPIO pin : LD2_Pin */
  GPIO_InitStruct.Pin = LD2_Pin;
 800077a:	2320      	movs	r3, #32
 800077c:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 800077e:	2301      	movs	r3, #1
 8000780:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000782:	2300      	movs	r3, #0
 8000784:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000786:	2300      	movs	r3, #0
 8000788:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
 800078a:	f107 0314 	add.w	r3, r7, #20
 800078e:	4619      	mov	r1, r3
 8000790:	4804      	ldr	r0, [pc, #16]	; (80007a4 <MX_GPIO_Init+0xc4>)
 8000792:	f000 fa6d 	bl	8000c70 <HAL_GPIO_Init>

}
 8000796:	bf00      	nop
 8000798:	3728      	adds	r7, #40	; 0x28
 800079a:	46bd      	mov	sp, r7
 800079c:	bd80      	pop	{r7, pc}
 800079e:	bf00      	nop
 80007a0:	40023800 	.word	0x40023800
 80007a4:	40020000 	.word	0x40020000
 80007a8:	10110000 	.word	0x10110000
 80007ac:	40020800 	.word	0x40020800

080007b0 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 80007b0:	b480      	push	{r7}
 80007b2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */

  /* USER CODE END Error_Handler_Debug */
}
 80007b4:	bf00      	nop
 80007b6:	46bd      	mov	sp, r7
 80007b8:	bc80      	pop	{r7}
 80007ba:	4770      	bx	lr

080007bc <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 80007bc:	b580      	push	{r7, lr}
 80007be:	b084      	sub	sp, #16
 80007c0:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_COMP_CLK_ENABLE();
 80007c2:	4b15      	ldr	r3, [pc, #84]	; (8000818 <HAL_MspInit+0x5c>)
 80007c4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80007c6:	4a14      	ldr	r2, [pc, #80]	; (8000818 <HAL_MspInit+0x5c>)
 80007c8:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 80007cc:	6253      	str	r3, [r2, #36]	; 0x24
 80007ce:	4b12      	ldr	r3, [pc, #72]	; (8000818 <HAL_MspInit+0x5c>)
 80007d0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80007d2:	f003 4300 	and.w	r3, r3, #2147483648	; 0x80000000
 80007d6:	60fb      	str	r3, [r7, #12]
 80007d8:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_SYSCFG_CLK_ENABLE();
 80007da:	4b0f      	ldr	r3, [pc, #60]	; (8000818 <HAL_MspInit+0x5c>)
 80007dc:	6a1b      	ldr	r3, [r3, #32]
 80007de:	4a0e      	ldr	r2, [pc, #56]	; (8000818 <HAL_MspInit+0x5c>)
 80007e0:	f043 0301 	orr.w	r3, r3, #1
 80007e4:	6213      	str	r3, [r2, #32]
 80007e6:	4b0c      	ldr	r3, [pc, #48]	; (8000818 <HAL_MspInit+0x5c>)
 80007e8:	6a1b      	ldr	r3, [r3, #32]
 80007ea:	f003 0301 	and.w	r3, r3, #1
 80007ee:	60bb      	str	r3, [r7, #8]
 80007f0:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_PWR_CLK_ENABLE();
 80007f2:	4b09      	ldr	r3, [pc, #36]	; (8000818 <HAL_MspInit+0x5c>)
 80007f4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80007f6:	4a08      	ldr	r2, [pc, #32]	; (8000818 <HAL_MspInit+0x5c>)
 80007f8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80007fc:	6253      	str	r3, [r2, #36]	; 0x24
 80007fe:	4b06      	ldr	r3, [pc, #24]	; (8000818 <HAL_MspInit+0x5c>)
 8000800:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000802:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000806:	607b      	str	r3, [r7, #4]
 8000808:	687b      	ldr	r3, [r7, #4]

  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
 800080a:	2007      	movs	r0, #7
 800080c:	f000 f9fc 	bl	8000c08 <HAL_NVIC_SetPriorityGrouping>
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000810:	bf00      	nop
 8000812:	3710      	adds	r7, #16
 8000814:	46bd      	mov	sp, r7
 8000816:	bd80      	pop	{r7, pc}
 8000818:	40023800 	.word	0x40023800

0800081c <HAL_RTC_MspInit>:
* This function configures the hardware resources used in this example
* @param hrtc: RTC handle pointer
* @retval None
*/
void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
{
 800081c:	b480      	push	{r7}
 800081e:	b083      	sub	sp, #12
 8000820:	af00      	add	r7, sp, #0
 8000822:	6078      	str	r0, [r7, #4]
  if(hrtc->Instance==RTC)
 8000824:	687b      	ldr	r3, [r7, #4]
 8000826:	681b      	ldr	r3, [r3, #0]
 8000828:	4a05      	ldr	r2, [pc, #20]	; (8000840 <HAL_RTC_MspInit+0x24>)
 800082a:	4293      	cmp	r3, r2
 800082c:	d102      	bne.n	8000834 <HAL_RTC_MspInit+0x18>
  {
  /* USER CODE BEGIN RTC_MspInit 0 */

  /* USER CODE END RTC_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_RTC_ENABLE();
 800082e:	4b05      	ldr	r3, [pc, #20]	; (8000844 <HAL_RTC_MspInit+0x28>)
 8000830:	2201      	movs	r2, #1
 8000832:	601a      	str	r2, [r3, #0]
  /* USER CODE BEGIN RTC_MspInit 1 */

  /* USER CODE END RTC_MspInit 1 */
  }

}
 8000834:	bf00      	nop
 8000836:	370c      	adds	r7, #12
 8000838:	46bd      	mov	sp, r7
 800083a:	bc80      	pop	{r7}
 800083c:	4770      	bx	lr
 800083e:	bf00      	nop
 8000840:	40002800 	.word	0x40002800
 8000844:	424706d8 	.word	0x424706d8

08000848 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8000848:	b580      	push	{r7, lr}
 800084a:	b08a      	sub	sp, #40	; 0x28
 800084c:	af00      	add	r7, sp, #0
 800084e:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000850:	f107 0314 	add.w	r3, r7, #20
 8000854:	2200      	movs	r2, #0
 8000856:	601a      	str	r2, [r3, #0]
 8000858:	605a      	str	r2, [r3, #4]
 800085a:	609a      	str	r2, [r3, #8]
 800085c:	60da      	str	r2, [r3, #12]
 800085e:	611a      	str	r2, [r3, #16]
  if(huart->Instance==USART2)
 8000860:	687b      	ldr	r3, [r7, #4]
 8000862:	681b      	ldr	r3, [r3, #0]
 8000864:	4a17      	ldr	r2, [pc, #92]	; (80008c4 <HAL_UART_MspInit+0x7c>)
 8000866:	4293      	cmp	r3, r2
 8000868:	d127      	bne.n	80008ba <HAL_UART_MspInit+0x72>
  {
  /* USER CODE BEGIN USART2_MspInit 0 */

  /* USER CODE END USART2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART2_CLK_ENABLE();
 800086a:	4b17      	ldr	r3, [pc, #92]	; (80008c8 <HAL_UART_MspInit+0x80>)
 800086c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800086e:	4a16      	ldr	r2, [pc, #88]	; (80008c8 <HAL_UART_MspInit+0x80>)
 8000870:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8000874:	6253      	str	r3, [r2, #36]	; 0x24
 8000876:	4b14      	ldr	r3, [pc, #80]	; (80008c8 <HAL_UART_MspInit+0x80>)
 8000878:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800087a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800087e:	613b      	str	r3, [r7, #16]
 8000880:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000882:	4b11      	ldr	r3, [pc, #68]	; (80008c8 <HAL_UART_MspInit+0x80>)
 8000884:	69db      	ldr	r3, [r3, #28]
 8000886:	4a10      	ldr	r2, [pc, #64]	; (80008c8 <HAL_UART_MspInit+0x80>)
 8000888:	f043 0301 	orr.w	r3, r3, #1
 800088c:	61d3      	str	r3, [r2, #28]
 800088e:	4b0e      	ldr	r3, [pc, #56]	; (80008c8 <HAL_UART_MspInit+0x80>)
 8000890:	69db      	ldr	r3, [r3, #28]
 8000892:	f003 0301 	and.w	r3, r3, #1
 8000896:	60fb      	str	r3, [r7, #12]
 8000898:	68fb      	ldr	r3, [r7, #12]
    /**USART2 GPIO Configuration
    PA2     ------> USART2_TX
    PA3     ------> USART2_RX
    */
    GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
 800089a:	230c      	movs	r3, #12
 800089c:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 800089e:	2302      	movs	r3, #2
 80008a0:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80008a2:	2300      	movs	r3, #0
 80008a4:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80008a6:	2303      	movs	r3, #3
 80008a8:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 80008aa:	2307      	movs	r3, #7
 80008ac:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80008ae:	f107 0314 	add.w	r3, r7, #20
 80008b2:	4619      	mov	r1, r3
 80008b4:	4805      	ldr	r0, [pc, #20]	; (80008cc <HAL_UART_MspInit+0x84>)
 80008b6:	f000 f9db 	bl	8000c70 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 80008ba:	bf00      	nop
 80008bc:	3728      	adds	r7, #40	; 0x28
 80008be:	46bd      	mov	sp, r7
 80008c0:	bd80      	pop	{r7, pc}
 80008c2:	bf00      	nop
 80008c4:	40004400 	.word	0x40004400
 80008c8:	40023800 	.word	0x40023800
 80008cc:	40020000 	.word	0x40020000

080008d0 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 80008d0:	b480      	push	{r7}
 80008d2:	af00      	add	r7, sp, #0

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */

  /* USER CODE END NonMaskableInt_IRQn 1 */
}
 80008d4:	bf00      	nop
 80008d6:	46bd      	mov	sp, r7
 80008d8:	bc80      	pop	{r7}
 80008da:	4770      	bx	lr

080008dc <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 80008dc:	b480      	push	{r7}
 80008de:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80008e0:	e7fe      	b.n	80008e0 <HardFault_Handler+0x4>

080008e2 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 80008e2:	b480      	push	{r7}
 80008e4:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 80008e6:	e7fe      	b.n	80008e6 <MemManage_Handler+0x4>

080008e8 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 80008e8:	b480      	push	{r7}
 80008ea:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 80008ec:	e7fe      	b.n	80008ec <BusFault_Handler+0x4>

080008ee <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 80008ee:	b480      	push	{r7}
 80008f0:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 80008f2:	e7fe      	b.n	80008f2 <UsageFault_Handler+0x4>

080008f4 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 80008f4:	b480      	push	{r7}
 80008f6:	af00      	add	r7, sp, #0

  /* USER CODE END SVC_IRQn 0 */
  /* USER CODE BEGIN SVC_IRQn 1 */

  /* USER CODE END SVC_IRQn 1 */
}
 80008f8:	bf00      	nop
 80008fa:	46bd      	mov	sp, r7
 80008fc:	bc80      	pop	{r7}
 80008fe:	4770      	bx	lr

08000900 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8000900:	b480      	push	{r7}
 8000902:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8000904:	bf00      	nop
 8000906:	46bd      	mov	sp, r7
 8000908:	bc80      	pop	{r7}
 800090a:	4770      	bx	lr

0800090c <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 800090c:	b480      	push	{r7}
 800090e:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8000910:	bf00      	nop
 8000912:	46bd      	mov	sp, r7
 8000914:	bc80      	pop	{r7}
 8000916:	4770      	bx	lr

08000918 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8000918:	b580      	push	{r7, lr}
 800091a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 800091c:	f000 f886 	bl	8000a2c <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8000920:	bf00      	nop
 8000922:	bd80      	pop	{r7, pc}

08000924 <SystemInit>:
  *         SystemCoreClock variable.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 8000924:	b480      	push	{r7}
 8000926:	af00      	add	r7, sp, #0
#endif /* DATA_IN_ExtSRAM */
    
#ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 8000928:	4b03      	ldr	r3, [pc, #12]	; (8000938 <SystemInit+0x14>)
 800092a:	f04f 6200 	mov.w	r2, #134217728	; 0x8000000
 800092e:	609a      	str	r2, [r3, #8]
#endif
}
 8000930:	bf00      	nop
 8000932:	46bd      	mov	sp, r7
 8000934:	bc80      	pop	{r7}
 8000936:	4770      	bx	lr
 8000938:	e000ed00 	.word	0xe000ed00

0800093c <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */
  movs r1, #0
 800093c:	2100      	movs	r1, #0
  b LoopCopyDataInit
 800093e:	e003      	b.n	8000948 <LoopCopyDataInit>

08000940 <CopyDataInit>:

CopyDataInit:
  ldr r3, =_sidata
 8000940:	4b0b      	ldr	r3, [pc, #44]	; (8000970 <LoopFillZerobss+0x14>)
  ldr r3, [r3, r1]
 8000942:	585b      	ldr	r3, [r3, r1]
  str r3, [r0, r1]
 8000944:	5043      	str	r3, [r0, r1]
  adds r1, r1, #4
 8000946:	3104      	adds	r1, #4

08000948 <LoopCopyDataInit>:

LoopCopyDataInit:
  ldr r0, =_sdata
 8000948:	480a      	ldr	r0, [pc, #40]	; (8000974 <LoopFillZerobss+0x18>)
  ldr r3, =_edata
 800094a:	4b0b      	ldr	r3, [pc, #44]	; (8000978 <LoopFillZerobss+0x1c>)
  adds r2, r0, r1
 800094c:	1842      	adds	r2, r0, r1
  cmp r2, r3
 800094e:	429a      	cmp	r2, r3
  bcc CopyDataInit
 8000950:	d3f6      	bcc.n	8000940 <CopyDataInit>
  ldr r2, =_sbss
 8000952:	4a0a      	ldr	r2, [pc, #40]	; (800097c <LoopFillZerobss+0x20>)
  b LoopFillZerobss
 8000954:	e002      	b.n	800095c <LoopFillZerobss>

08000956 <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
  movs r3, #0
 8000956:	2300      	movs	r3, #0
  str r3, [r2], #4
 8000958:	f842 3b04 	str.w	r3, [r2], #4

0800095c <LoopFillZerobss>:

LoopFillZerobss:
  ldr r3, = _ebss
 800095c:	4b08      	ldr	r3, [pc, #32]	; (8000980 <LoopFillZerobss+0x24>)
  cmp r2, r3
 800095e:	429a      	cmp	r2, r3
  bcc FillZerobss
 8000960:	d3f9      	bcc.n	8000956 <FillZerobss>

/* Call the clock system intitialization function.*/
    bl  SystemInit
 8000962:	f7ff ffdf 	bl	8000924 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8000966:	f001 fe05 	bl	8002574 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 800096a:	f7ff fd89 	bl	8000480 <main>
  bx lr
 800096e:	4770      	bx	lr
  ldr r3, =_sidata
 8000970:	08002618 	.word	0x08002618
  ldr r0, =_sdata
 8000974:	20000000 	.word	0x20000000
  ldr r3, =_edata
 8000978:	2000000c 	.word	0x2000000c
  ldr r2, =_sbss
 800097c:	2000000c 	.word	0x2000000c
  ldr r3, = _ebss
 8000980:	200000a4 	.word	0x200000a4

08000984 <ADC1_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8000984:	e7fe      	b.n	8000984 <ADC1_IRQHandler>

08000986 <HAL_Init>:
  *        In the default implementation,Systick is used as source of time base.
  *        the tick variable is incremented each 1ms in its ISR.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8000986:	b580      	push	{r7, lr}
 8000988:	b082      	sub	sp, #8
 800098a:	af00      	add	r7, sp, #0
  HAL_StatusTypeDef  status = HAL_OK;
 800098c:	2300      	movs	r3, #0
 800098e:	71fb      	strb	r3, [r7, #7]
#if (PREFETCH_ENABLE != 0)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000990:	2003      	movs	r0, #3
 8000992:	f000 f939 	bl	8000c08 <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
 8000996:	2000      	movs	r0, #0
 8000998:	f000 f80e 	bl	80009b8 <HAL_InitTick>
 800099c:	4603      	mov	r3, r0
 800099e:	2b00      	cmp	r3, #0
 80009a0:	d002      	beq.n	80009a8 <HAL_Init+0x22>
  {
    status = HAL_ERROR;
 80009a2:	2301      	movs	r3, #1
 80009a4:	71fb      	strb	r3, [r7, #7]
 80009a6:	e001      	b.n	80009ac <HAL_Init+0x26>
  }
  else
  {
    /* Init the low level hardware */
    HAL_MspInit();
 80009a8:	f7ff ff08 	bl	80007bc <HAL_MspInit>
  }

  /* Return function status */
  return status;
 80009ac:	79fb      	ldrb	r3, [r7, #7]
}
 80009ae:	4618      	mov	r0, r3
 80009b0:	3708      	adds	r7, #8
 80009b2:	46bd      	mov	sp, r7
 80009b4:	bd80      	pop	{r7, pc}
	...

080009b8 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 80009b8:	b580      	push	{r7, lr}
 80009ba:	b084      	sub	sp, #16
 80009bc:	af00      	add	r7, sp, #0
 80009be:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef  status = HAL_OK;
 80009c0:	2300      	movs	r3, #0
 80009c2:	73fb      	strb	r3, [r7, #15]

  if (uwTickFreq != 0U)
 80009c4:	4b16      	ldr	r3, [pc, #88]	; (8000a20 <HAL_InitTick+0x68>)
 80009c6:	681b      	ldr	r3, [r3, #0]
 80009c8:	2b00      	cmp	r3, #0
 80009ca:	d022      	beq.n	8000a12 <HAL_InitTick+0x5a>
  {
    /*Configure the SysTick to have interrupt in 1ms time basis*/
    if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
 80009cc:	4b15      	ldr	r3, [pc, #84]	; (8000a24 <HAL_InitTick+0x6c>)
 80009ce:	681a      	ldr	r2, [r3, #0]
 80009d0:	4b13      	ldr	r3, [pc, #76]	; (8000a20 <HAL_InitTick+0x68>)
 80009d2:	681b      	ldr	r3, [r3, #0]
 80009d4:	f44f 717a 	mov.w	r1, #1000	; 0x3e8
 80009d8:	fbb1 f3f3 	udiv	r3, r1, r3
 80009dc:	fbb2 f3f3 	udiv	r3, r2, r3
 80009e0:	4618      	mov	r0, r3
 80009e2:	f000 f938 	bl	8000c56 <HAL_SYSTICK_Config>
 80009e6:	4603      	mov	r3, r0
 80009e8:	2b00      	cmp	r3, #0
 80009ea:	d10f      	bne.n	8000a0c <HAL_InitTick+0x54>
    {
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 80009ec:	687b      	ldr	r3, [r7, #4]
 80009ee:	2b0f      	cmp	r3, #15
 80009f0:	d809      	bhi.n	8000a06 <HAL_InitTick+0x4e>
      {
        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80009f2:	2200      	movs	r2, #0
 80009f4:	6879      	ldr	r1, [r7, #4]
 80009f6:	f04f 30ff 	mov.w	r0, #4294967295
 80009fa:	f000 f910 	bl	8000c1e <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 80009fe:	4a0a      	ldr	r2, [pc, #40]	; (8000a28 <HAL_InitTick+0x70>)
 8000a00:	687b      	ldr	r3, [r7, #4]
 8000a02:	6013      	str	r3, [r2, #0]
 8000a04:	e007      	b.n	8000a16 <HAL_InitTick+0x5e>
      }
      else
      {
        status = HAL_ERROR;
 8000a06:	2301      	movs	r3, #1
 8000a08:	73fb      	strb	r3, [r7, #15]
 8000a0a:	e004      	b.n	8000a16 <HAL_InitTick+0x5e>
      }
    }
    else
    {
      status = HAL_ERROR;
 8000a0c:	2301      	movs	r3, #1
 8000a0e:	73fb      	strb	r3, [r7, #15]
 8000a10:	e001      	b.n	8000a16 <HAL_InitTick+0x5e>
    }
  }
  else
  {
    status = HAL_ERROR;
 8000a12:	2301      	movs	r3, #1
 8000a14:	73fb      	strb	r3, [r7, #15]
  }

  /* Return function status */
  return status;
 8000a16:	7bfb      	ldrb	r3, [r7, #15]
}
 8000a18:	4618      	mov	r0, r3
 8000a1a:	3710      	adds	r7, #16
 8000a1c:	46bd      	mov	sp, r7
 8000a1e:	bd80      	pop	{r7, pc}
 8000a20:	20000008 	.word	0x20000008
 8000a24:	20000000 	.word	0x20000000
 8000a28:	20000004 	.word	0x20000004

08000a2c <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000a2c:	b480      	push	{r7}
 8000a2e:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8000a30:	4b05      	ldr	r3, [pc, #20]	; (8000a48 <HAL_IncTick+0x1c>)
 8000a32:	681a      	ldr	r2, [r3, #0]
 8000a34:	4b05      	ldr	r3, [pc, #20]	; (8000a4c <HAL_IncTick+0x20>)
 8000a36:	681b      	ldr	r3, [r3, #0]
 8000a38:	4413      	add	r3, r2
 8000a3a:	4a03      	ldr	r2, [pc, #12]	; (8000a48 <HAL_IncTick+0x1c>)
 8000a3c:	6013      	str	r3, [r2, #0]
}
 8000a3e:	bf00      	nop
 8000a40:	46bd      	mov	sp, r7
 8000a42:	bc80      	pop	{r7}
 8000a44:	4770      	bx	lr
 8000a46:	bf00      	nop
 8000a48:	200000a0 	.word	0x200000a0
 8000a4c:	20000008 	.word	0x20000008

08000a50 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000a50:	b480      	push	{r7}
 8000a52:	af00      	add	r7, sp, #0
  return uwTick;
 8000a54:	4b02      	ldr	r3, [pc, #8]	; (8000a60 <HAL_GetTick+0x10>)
 8000a56:	681b      	ldr	r3, [r3, #0]
}
 8000a58:	4618      	mov	r0, r3
 8000a5a:	46bd      	mov	sp, r7
 8000a5c:	bc80      	pop	{r7}
 8000a5e:	4770      	bx	lr
 8000a60:	200000a0 	.word	0x200000a0

08000a64 <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 8000a64:	b580      	push	{r7, lr}
 8000a66:	b084      	sub	sp, #16
 8000a68:	af00      	add	r7, sp, #0
 8000a6a:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8000a6c:	f7ff fff0 	bl	8000a50 <HAL_GetTick>
 8000a70:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 8000a72:	687b      	ldr	r3, [r7, #4]
 8000a74:	60fb      	str	r3, [r7, #12]

  /* Add a period to guaranty minimum wait */
  if (wait < HAL_MAX_DELAY)
 8000a76:	68fb      	ldr	r3, [r7, #12]
 8000a78:	f1b3 3fff 	cmp.w	r3, #4294967295
 8000a7c:	d004      	beq.n	8000a88 <HAL_Delay+0x24>
  {
    wait += (uint32_t)(uwTickFreq);
 8000a7e:	4b09      	ldr	r3, [pc, #36]	; (8000aa4 <HAL_Delay+0x40>)
 8000a80:	681b      	ldr	r3, [r3, #0]
 8000a82:	68fa      	ldr	r2, [r7, #12]
 8000a84:	4413      	add	r3, r2
 8000a86:	60fb      	str	r3, [r7, #12]
  }

  while((HAL_GetTick() - tickstart) < wait)
 8000a88:	bf00      	nop
 8000a8a:	f7ff ffe1 	bl	8000a50 <HAL_GetTick>
 8000a8e:	4602      	mov	r2, r0
 8000a90:	68bb      	ldr	r3, [r7, #8]
 8000a92:	1ad3      	subs	r3, r2, r3
 8000a94:	68fa      	ldr	r2, [r7, #12]
 8000a96:	429a      	cmp	r2, r3
 8000a98:	d8f7      	bhi.n	8000a8a <HAL_Delay+0x26>
  {
  }
}
 8000a9a:	bf00      	nop
 8000a9c:	3710      	adds	r7, #16
 8000a9e:	46bd      	mov	sp, r7
 8000aa0:	bd80      	pop	{r7, pc}
 8000aa2:	bf00      	nop
 8000aa4:	20000008 	.word	0x20000008

08000aa8 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8000aa8:	b480      	push	{r7}
 8000aaa:	b085      	sub	sp, #20
 8000aac:	af00      	add	r7, sp, #0
 8000aae:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8000ab0:	687b      	ldr	r3, [r7, #4]
 8000ab2:	f003 0307 	and.w	r3, r3, #7
 8000ab6:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8000ab8:	4b0c      	ldr	r3, [pc, #48]	; (8000aec <__NVIC_SetPriorityGrouping+0x44>)
 8000aba:	68db      	ldr	r3, [r3, #12]
 8000abc:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8000abe:	68ba      	ldr	r2, [r7, #8]
 8000ac0:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 8000ac4:	4013      	ands	r3, r2
 8000ac6:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 8000ac8:	68fb      	ldr	r3, [r7, #12]
 8000aca:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8000acc:	68bb      	ldr	r3, [r7, #8]
 8000ace:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8000ad0:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8000ad4:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8000ad8:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8000ada:	4a04      	ldr	r2, [pc, #16]	; (8000aec <__NVIC_SetPriorityGrouping+0x44>)
 8000adc:	68bb      	ldr	r3, [r7, #8]
 8000ade:	60d3      	str	r3, [r2, #12]
}
 8000ae0:	bf00      	nop
 8000ae2:	3714      	adds	r7, #20
 8000ae4:	46bd      	mov	sp, r7
 8000ae6:	bc80      	pop	{r7}
 8000ae8:	4770      	bx	lr
 8000aea:	bf00      	nop
 8000aec:	e000ed00 	.word	0xe000ed00

08000af0 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 8000af0:	b480      	push	{r7}
 8000af2:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8000af4:	4b04      	ldr	r3, [pc, #16]	; (8000b08 <__NVIC_GetPriorityGrouping+0x18>)
 8000af6:	68db      	ldr	r3, [r3, #12]
 8000af8:	0a1b      	lsrs	r3, r3, #8
 8000afa:	f003 0307 	and.w	r3, r3, #7
}
 8000afe:	4618      	mov	r0, r3
 8000b00:	46bd      	mov	sp, r7
 8000b02:	bc80      	pop	{r7}
 8000b04:	4770      	bx	lr
 8000b06:	bf00      	nop
 8000b08:	e000ed00 	.word	0xe000ed00

08000b0c <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000b0c:	b480      	push	{r7}
 8000b0e:	b083      	sub	sp, #12
 8000b10:	af00      	add	r7, sp, #0
 8000b12:	4603      	mov	r3, r0
 8000b14:	6039      	str	r1, [r7, #0]
 8000b16:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000b18:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000b1c:	2b00      	cmp	r3, #0
 8000b1e:	db0a      	blt.n	8000b36 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000b20:	683b      	ldr	r3, [r7, #0]
 8000b22:	b2da      	uxtb	r2, r3
 8000b24:	490c      	ldr	r1, [pc, #48]	; (8000b58 <__NVIC_SetPriority+0x4c>)
 8000b26:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000b2a:	0112      	lsls	r2, r2, #4
 8000b2c:	b2d2      	uxtb	r2, r2
 8000b2e:	440b      	add	r3, r1
 8000b30:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8000b34:	e00a      	b.n	8000b4c <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000b36:	683b      	ldr	r3, [r7, #0]
 8000b38:	b2da      	uxtb	r2, r3
 8000b3a:	4908      	ldr	r1, [pc, #32]	; (8000b5c <__NVIC_SetPriority+0x50>)
 8000b3c:	79fb      	ldrb	r3, [r7, #7]
 8000b3e:	f003 030f 	and.w	r3, r3, #15
 8000b42:	3b04      	subs	r3, #4
 8000b44:	0112      	lsls	r2, r2, #4
 8000b46:	b2d2      	uxtb	r2, r2
 8000b48:	440b      	add	r3, r1
 8000b4a:	761a      	strb	r2, [r3, #24]
}
 8000b4c:	bf00      	nop
 8000b4e:	370c      	adds	r7, #12
 8000b50:	46bd      	mov	sp, r7
 8000b52:	bc80      	pop	{r7}
 8000b54:	4770      	bx	lr
 8000b56:	bf00      	nop
 8000b58:	e000e100 	.word	0xe000e100
 8000b5c:	e000ed00 	.word	0xe000ed00

08000b60 <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000b60:	b480      	push	{r7}
 8000b62:	b089      	sub	sp, #36	; 0x24
 8000b64:	af00      	add	r7, sp, #0
 8000b66:	60f8      	str	r0, [r7, #12]
 8000b68:	60b9      	str	r1, [r7, #8]
 8000b6a:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8000b6c:	68fb      	ldr	r3, [r7, #12]
 8000b6e:	f003 0307 	and.w	r3, r3, #7
 8000b72:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000b74:	69fb      	ldr	r3, [r7, #28]
 8000b76:	f1c3 0307 	rsb	r3, r3, #7
 8000b7a:	2b04      	cmp	r3, #4
 8000b7c:	bf28      	it	cs
 8000b7e:	2304      	movcs	r3, #4
 8000b80:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000b82:	69fb      	ldr	r3, [r7, #28]
 8000b84:	3304      	adds	r3, #4
 8000b86:	2b06      	cmp	r3, #6
 8000b88:	d902      	bls.n	8000b90 <NVIC_EncodePriority+0x30>
 8000b8a:	69fb      	ldr	r3, [r7, #28]
 8000b8c:	3b03      	subs	r3, #3
 8000b8e:	e000      	b.n	8000b92 <NVIC_EncodePriority+0x32>
 8000b90:	2300      	movs	r3, #0
 8000b92:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000b94:	f04f 32ff 	mov.w	r2, #4294967295
 8000b98:	69bb      	ldr	r3, [r7, #24]
 8000b9a:	fa02 f303 	lsl.w	r3, r2, r3
 8000b9e:	43da      	mvns	r2, r3
 8000ba0:	68bb      	ldr	r3, [r7, #8]
 8000ba2:	401a      	ands	r2, r3
 8000ba4:	697b      	ldr	r3, [r7, #20]
 8000ba6:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000ba8:	f04f 31ff 	mov.w	r1, #4294967295
 8000bac:	697b      	ldr	r3, [r7, #20]
 8000bae:	fa01 f303 	lsl.w	r3, r1, r3
 8000bb2:	43d9      	mvns	r1, r3
 8000bb4:	687b      	ldr	r3, [r7, #4]
 8000bb6:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000bb8:	4313      	orrs	r3, r2
         );
}
 8000bba:	4618      	mov	r0, r3
 8000bbc:	3724      	adds	r7, #36	; 0x24
 8000bbe:	46bd      	mov	sp, r7
 8000bc0:	bc80      	pop	{r7}
 8000bc2:	4770      	bx	lr

08000bc4 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8000bc4:	b580      	push	{r7, lr}
 8000bc6:	b082      	sub	sp, #8
 8000bc8:	af00      	add	r7, sp, #0
 8000bca:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000bcc:	687b      	ldr	r3, [r7, #4]
 8000bce:	3b01      	subs	r3, #1
 8000bd0:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 8000bd4:	d301      	bcc.n	8000bda <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 8000bd6:	2301      	movs	r3, #1
 8000bd8:	e00f      	b.n	8000bfa <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000bda:	4a0a      	ldr	r2, [pc, #40]	; (8000c04 <SysTick_Config+0x40>)
 8000bdc:	687b      	ldr	r3, [r7, #4]
 8000bde:	3b01      	subs	r3, #1
 8000be0:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 8000be2:	210f      	movs	r1, #15
 8000be4:	f04f 30ff 	mov.w	r0, #4294967295
 8000be8:	f7ff ff90 	bl	8000b0c <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8000bec:	4b05      	ldr	r3, [pc, #20]	; (8000c04 <SysTick_Config+0x40>)
 8000bee:	2200      	movs	r2, #0
 8000bf0:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000bf2:	4b04      	ldr	r3, [pc, #16]	; (8000c04 <SysTick_Config+0x40>)
 8000bf4:	2207      	movs	r2, #7
 8000bf6:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8000bf8:	2300      	movs	r3, #0
}
 8000bfa:	4618      	mov	r0, r3
 8000bfc:	3708      	adds	r7, #8
 8000bfe:	46bd      	mov	sp, r7
 8000c00:	bd80      	pop	{r7, pc}
 8000c02:	bf00      	nop
 8000c04:	e000e010 	.word	0xe000e010

08000c08 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8000c08:	b580      	push	{r7, lr}
 8000c0a:	b082      	sub	sp, #8
 8000c0c:	af00      	add	r7, sp, #0
 8000c0e:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8000c10:	6878      	ldr	r0, [r7, #4]
 8000c12:	f7ff ff49 	bl	8000aa8 <__NVIC_SetPriorityGrouping>
}
 8000c16:	bf00      	nop
 8000c18:	3708      	adds	r7, #8
 8000c1a:	46bd      	mov	sp, r7
 8000c1c:	bd80      	pop	{r7, pc}

08000c1e <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000c1e:	b580      	push	{r7, lr}
 8000c20:	b086      	sub	sp, #24
 8000c22:	af00      	add	r7, sp, #0
 8000c24:	4603      	mov	r3, r0
 8000c26:	60b9      	str	r1, [r7, #8]
 8000c28:	607a      	str	r2, [r7, #4]
 8000c2a:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00;
 8000c2c:	2300      	movs	r3, #0
 8000c2e:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 8000c30:	f7ff ff5e 	bl	8000af0 <__NVIC_GetPriorityGrouping>
 8000c34:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 8000c36:	687a      	ldr	r2, [r7, #4]
 8000c38:	68b9      	ldr	r1, [r7, #8]
 8000c3a:	6978      	ldr	r0, [r7, #20]
 8000c3c:	f7ff ff90 	bl	8000b60 <NVIC_EncodePriority>
 8000c40:	4602      	mov	r2, r0
 8000c42:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8000c46:	4611      	mov	r1, r2
 8000c48:	4618      	mov	r0, r3
 8000c4a:	f7ff ff5f 	bl	8000b0c <__NVIC_SetPriority>
}
 8000c4e:	bf00      	nop
 8000c50:	3718      	adds	r7, #24
 8000c52:	46bd      	mov	sp, r7
 8000c54:	bd80      	pop	{r7, pc}

08000c56 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8000c56:	b580      	push	{r7, lr}
 8000c58:	b082      	sub	sp, #8
 8000c5a:	af00      	add	r7, sp, #0
 8000c5c:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 8000c5e:	6878      	ldr	r0, [r7, #4]
 8000c60:	f7ff ffb0 	bl	8000bc4 <SysTick_Config>
 8000c64:	4603      	mov	r3, r0
}
 8000c66:	4618      	mov	r0, r3
 8000c68:	3708      	adds	r7, #8
 8000c6a:	46bd      	mov	sp, r7
 8000c6c:	bd80      	pop	{r7, pc}
	...

08000c70 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8000c70:	b480      	push	{r7}
 8000c72:	b087      	sub	sp, #28
 8000c74:	af00      	add	r7, sp, #0
 8000c76:	6078      	str	r0, [r7, #4]
 8000c78:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00;
 8000c7a:	2300      	movs	r3, #0
 8000c7c:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00;
 8000c7e:	2300      	movs	r3, #0
 8000c80:	60fb      	str	r3, [r7, #12]
  uint32_t temp = 0x00;
 8000c82:	2300      	movs	r3, #0
 8000c84:	613b      	str	r3, [r7, #16]
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0)
 8000c86:	e160      	b.n	8000f4a <HAL_GPIO_Init+0x2da>
  {
    /* Get current io position */
    iocurrent = (GPIO_Init->Pin) & (1U << position);
 8000c88:	683b      	ldr	r3, [r7, #0]
 8000c8a:	681a      	ldr	r2, [r3, #0]
 8000c8c:	2101      	movs	r1, #1
 8000c8e:	697b      	ldr	r3, [r7, #20]
 8000c90:	fa01 f303 	lsl.w	r3, r1, r3
 8000c94:	4013      	ands	r3, r2
 8000c96:	60fb      	str	r3, [r7, #12]

    if (iocurrent)
 8000c98:	68fb      	ldr	r3, [r7, #12]
 8000c9a:	2b00      	cmp	r3, #0
 8000c9c:	f000 8152 	beq.w	8000f44 <HAL_GPIO_Init+0x2d4>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
 8000ca0:	683b      	ldr	r3, [r7, #0]
 8000ca2:	685b      	ldr	r3, [r3, #4]
 8000ca4:	2b01      	cmp	r3, #1
 8000ca6:	d00b      	beq.n	8000cc0 <HAL_GPIO_Init+0x50>
 8000ca8:	683b      	ldr	r3, [r7, #0]
 8000caa:	685b      	ldr	r3, [r3, #4]
 8000cac:	2b02      	cmp	r3, #2
 8000cae:	d007      	beq.n	8000cc0 <HAL_GPIO_Init+0x50>
          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
 8000cb0:	683b      	ldr	r3, [r7, #0]
 8000cb2:	685b      	ldr	r3, [r3, #4]
      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
 8000cb4:	2b11      	cmp	r3, #17
 8000cb6:	d003      	beq.n	8000cc0 <HAL_GPIO_Init+0x50>
          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
 8000cb8:	683b      	ldr	r3, [r7, #0]
 8000cba:	685b      	ldr	r3, [r3, #4]
 8000cbc:	2b12      	cmp	r3, #18
 8000cbe:	d130      	bne.n	8000d22 <HAL_GPIO_Init+0xb2>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 8000cc0:	687b      	ldr	r3, [r7, #4]
 8000cc2:	689b      	ldr	r3, [r3, #8]
 8000cc4:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
 8000cc6:	697b      	ldr	r3, [r7, #20]
 8000cc8:	005b      	lsls	r3, r3, #1
 8000cca:	2203      	movs	r2, #3
 8000ccc:	fa02 f303 	lsl.w	r3, r2, r3
 8000cd0:	43db      	mvns	r3, r3
 8000cd2:	693a      	ldr	r2, [r7, #16]
 8000cd4:	4013      	ands	r3, r2
 8000cd6:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, GPIO_Init->Speed << (position * 2));
 8000cd8:	683b      	ldr	r3, [r7, #0]
 8000cda:	68da      	ldr	r2, [r3, #12]
 8000cdc:	697b      	ldr	r3, [r7, #20]
 8000cde:	005b      	lsls	r3, r3, #1
 8000ce0:	fa02 f303 	lsl.w	r3, r2, r3
 8000ce4:	693a      	ldr	r2, [r7, #16]
 8000ce6:	4313      	orrs	r3, r2
 8000ce8:	613b      	str	r3, [r7, #16]
        GPIOx->OSPEEDR = temp;
 8000cea:	687b      	ldr	r3, [r7, #4]
 8000cec:	693a      	ldr	r2, [r7, #16]
 8000cee:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8000cf0:	687b      	ldr	r3, [r7, #4]
 8000cf2:	685b      	ldr	r3, [r3, #4]
 8000cf4:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
 8000cf6:	2201      	movs	r2, #1
 8000cf8:	697b      	ldr	r3, [r7, #20]
 8000cfa:	fa02 f303 	lsl.w	r3, r2, r3
 8000cfe:	43db      	mvns	r3, r3
 8000d00:	693a      	ldr	r2, [r7, #16]
 8000d02:	4013      	ands	r3, r2
 8000d04:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
 8000d06:	683b      	ldr	r3, [r7, #0]
 8000d08:	685b      	ldr	r3, [r3, #4]
 8000d0a:	091b      	lsrs	r3, r3, #4
 8000d0c:	f003 0201 	and.w	r2, r3, #1
 8000d10:	697b      	ldr	r3, [r7, #20]
 8000d12:	fa02 f303 	lsl.w	r3, r2, r3
 8000d16:	693a      	ldr	r2, [r7, #16]
 8000d18:	4313      	orrs	r3, r2
 8000d1a:	613b      	str	r3, [r7, #16]
        GPIOx->OTYPER = temp;
 8000d1c:	687b      	ldr	r3, [r7, #4]
 8000d1e:	693a      	ldr	r2, [r7, #16]
 8000d20:	605a      	str	r2, [r3, #4]
      }

      /* Activate the Pull-up or Pull down resistor for the current IO */
      temp = GPIOx->PUPDR;
 8000d22:	687b      	ldr	r3, [r7, #4]
 8000d24:	68db      	ldr	r3, [r3, #12]
 8000d26:	613b      	str	r3, [r7, #16]
      CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
 8000d28:	697b      	ldr	r3, [r7, #20]
 8000d2a:	005b      	lsls	r3, r3, #1
 8000d2c:	2203      	movs	r2, #3
 8000d2e:	fa02 f303 	lsl.w	r3, r2, r3
 8000d32:	43db      	mvns	r3, r3
 8000d34:	693a      	ldr	r2, [r7, #16]
 8000d36:	4013      	ands	r3, r2
 8000d38:	613b      	str	r3, [r7, #16]
      SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
 8000d3a:	683b      	ldr	r3, [r7, #0]
 8000d3c:	689a      	ldr	r2, [r3, #8]
 8000d3e:	697b      	ldr	r3, [r7, #20]
 8000d40:	005b      	lsls	r3, r3, #1
 8000d42:	fa02 f303 	lsl.w	r3, r2, r3
 8000d46:	693a      	ldr	r2, [r7, #16]
 8000d48:	4313      	orrs	r3, r2
 8000d4a:	613b      	str	r3, [r7, #16]
      GPIOx->PUPDR = temp;
 8000d4c:	687b      	ldr	r3, [r7, #4]
 8000d4e:	693a      	ldr	r2, [r7, #16]
 8000d50:	60da      	str	r2, [r3, #12]

      /* In case of Alternate function mode selection */
      if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
 8000d52:	683b      	ldr	r3, [r7, #0]
 8000d54:	685b      	ldr	r3, [r3, #4]
 8000d56:	2b02      	cmp	r3, #2
 8000d58:	d003      	beq.n	8000d62 <HAL_GPIO_Init+0xf2>
 8000d5a:	683b      	ldr	r3, [r7, #0]
 8000d5c:	685b      	ldr	r3, [r3, #4]
 8000d5e:	2b12      	cmp	r3, #18
 8000d60:	d123      	bne.n	8000daa <HAL_GPIO_Init+0x13a>
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        /* Identify AFRL or AFRH register based on IO position*/
        temp = GPIOx->AFR[position >> 3];
 8000d62:	697b      	ldr	r3, [r7, #20]
 8000d64:	08da      	lsrs	r2, r3, #3
 8000d66:	687b      	ldr	r3, [r7, #4]
 8000d68:	3208      	adds	r2, #8
 8000d6a:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8000d6e:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
 8000d70:	697b      	ldr	r3, [r7, #20]
 8000d72:	f003 0307 	and.w	r3, r3, #7
 8000d76:	009b      	lsls	r3, r3, #2
 8000d78:	220f      	movs	r2, #15
 8000d7a:	fa02 f303 	lsl.w	r3, r2, r3
 8000d7e:	43db      	mvns	r3, r3
 8000d80:	693a      	ldr	r2, [r7, #16]
 8000d82:	4013      	ands	r3, r2
 8000d84:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
 8000d86:	683b      	ldr	r3, [r7, #0]
 8000d88:	691a      	ldr	r2, [r3, #16]
 8000d8a:	697b      	ldr	r3, [r7, #20]
 8000d8c:	f003 0307 	and.w	r3, r3, #7
 8000d90:	009b      	lsls	r3, r3, #2
 8000d92:	fa02 f303 	lsl.w	r3, r2, r3
 8000d96:	693a      	ldr	r2, [r7, #16]
 8000d98:	4313      	orrs	r3, r2
 8000d9a:	613b      	str	r3, [r7, #16]
        GPIOx->AFR[position >> 3] = temp;
 8000d9c:	697b      	ldr	r3, [r7, #20]
 8000d9e:	08da      	lsrs	r2, r3, #3
 8000da0:	687b      	ldr	r3, [r7, #4]
 8000da2:	3208      	adds	r2, #8
 8000da4:	6939      	ldr	r1, [r7, #16]
 8000da6:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8000daa:	687b      	ldr	r3, [r7, #4]
 8000dac:	681b      	ldr	r3, [r3, #0]
 8000dae:	613b      	str	r3, [r7, #16]
      CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
 8000db0:	697b      	ldr	r3, [r7, #20]
 8000db2:	005b      	lsls	r3, r3, #1
 8000db4:	2203      	movs	r2, #3
 8000db6:	fa02 f303 	lsl.w	r3, r2, r3
 8000dba:	43db      	mvns	r3, r3
 8000dbc:	693a      	ldr	r2, [r7, #16]
 8000dbe:	4013      	ands	r3, r2
 8000dc0:	613b      	str	r3, [r7, #16]
      SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
 8000dc2:	683b      	ldr	r3, [r7, #0]
 8000dc4:	685b      	ldr	r3, [r3, #4]
 8000dc6:	f003 0203 	and.w	r2, r3, #3
 8000dca:	697b      	ldr	r3, [r7, #20]
 8000dcc:	005b      	lsls	r3, r3, #1
 8000dce:	fa02 f303 	lsl.w	r3, r2, r3
 8000dd2:	693a      	ldr	r2, [r7, #16]
 8000dd4:	4313      	orrs	r3, r2
 8000dd6:	613b      	str	r3, [r7, #16]
      GPIOx->MODER = temp;
 8000dd8:	687b      	ldr	r3, [r7, #4]
 8000dda:	693a      	ldr	r2, [r7, #16]
 8000ddc:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 8000dde:	683b      	ldr	r3, [r7, #0]
 8000de0:	685b      	ldr	r3, [r3, #4]
 8000de2:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000de6:	2b00      	cmp	r3, #0
 8000de8:	f000 80ac 	beq.w	8000f44 <HAL_GPIO_Init+0x2d4>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000dec:	4b5d      	ldr	r3, [pc, #372]	; (8000f64 <HAL_GPIO_Init+0x2f4>)
 8000dee:	6a1b      	ldr	r3, [r3, #32]
 8000df0:	4a5c      	ldr	r2, [pc, #368]	; (8000f64 <HAL_GPIO_Init+0x2f4>)
 8000df2:	f043 0301 	orr.w	r3, r3, #1
 8000df6:	6213      	str	r3, [r2, #32]
 8000df8:	4b5a      	ldr	r3, [pc, #360]	; (8000f64 <HAL_GPIO_Init+0x2f4>)
 8000dfa:	6a1b      	ldr	r3, [r3, #32]
 8000dfc:	f003 0301 	and.w	r3, r3, #1
 8000e00:	60bb      	str	r3, [r7, #8]
 8000e02:	68bb      	ldr	r3, [r7, #8]

        temp = SYSCFG->EXTICR[position >> 2];
 8000e04:	4a58      	ldr	r2, [pc, #352]	; (8000f68 <HAL_GPIO_Init+0x2f8>)
 8000e06:	697b      	ldr	r3, [r7, #20]
 8000e08:	089b      	lsrs	r3, r3, #2
 8000e0a:	3302      	adds	r3, #2
 8000e0c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8000e10:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
 8000e12:	697b      	ldr	r3, [r7, #20]
 8000e14:	f003 0303 	and.w	r3, r3, #3
 8000e18:	009b      	lsls	r3, r3, #2
 8000e1a:	220f      	movs	r2, #15
 8000e1c:	fa02 f303 	lsl.w	r3, r2, r3
 8000e20:	43db      	mvns	r3, r3
 8000e22:	693a      	ldr	r2, [r7, #16]
 8000e24:	4013      	ands	r3, r2
 8000e26:	613b      	str	r3, [r7, #16]
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
 8000e28:	687b      	ldr	r3, [r7, #4]
 8000e2a:	4a50      	ldr	r2, [pc, #320]	; (8000f6c <HAL_GPIO_Init+0x2fc>)
 8000e2c:	4293      	cmp	r3, r2
 8000e2e:	d025      	beq.n	8000e7c <HAL_GPIO_Init+0x20c>
 8000e30:	687b      	ldr	r3, [r7, #4]
 8000e32:	4a4f      	ldr	r2, [pc, #316]	; (8000f70 <HAL_GPIO_Init+0x300>)
 8000e34:	4293      	cmp	r3, r2
 8000e36:	d01f      	beq.n	8000e78 <HAL_GPIO_Init+0x208>
 8000e38:	687b      	ldr	r3, [r7, #4]
 8000e3a:	4a4e      	ldr	r2, [pc, #312]	; (8000f74 <HAL_GPIO_Init+0x304>)
 8000e3c:	4293      	cmp	r3, r2
 8000e3e:	d019      	beq.n	8000e74 <HAL_GPIO_Init+0x204>
 8000e40:	687b      	ldr	r3, [r7, #4]
 8000e42:	4a4d      	ldr	r2, [pc, #308]	; (8000f78 <HAL_GPIO_Init+0x308>)
 8000e44:	4293      	cmp	r3, r2
 8000e46:	d013      	beq.n	8000e70 <HAL_GPIO_Init+0x200>
 8000e48:	687b      	ldr	r3, [r7, #4]
 8000e4a:	4a4c      	ldr	r2, [pc, #304]	; (8000f7c <HAL_GPIO_Init+0x30c>)
 8000e4c:	4293      	cmp	r3, r2
 8000e4e:	d00d      	beq.n	8000e6c <HAL_GPIO_Init+0x1fc>
 8000e50:	687b      	ldr	r3, [r7, #4]
 8000e52:	4a4b      	ldr	r2, [pc, #300]	; (8000f80 <HAL_GPIO_Init+0x310>)
 8000e54:	4293      	cmp	r3, r2
 8000e56:	d007      	beq.n	8000e68 <HAL_GPIO_Init+0x1f8>
 8000e58:	687b      	ldr	r3, [r7, #4]
 8000e5a:	4a4a      	ldr	r2, [pc, #296]	; (8000f84 <HAL_GPIO_Init+0x314>)
 8000e5c:	4293      	cmp	r3, r2
 8000e5e:	d101      	bne.n	8000e64 <HAL_GPIO_Init+0x1f4>
 8000e60:	2306      	movs	r3, #6
 8000e62:	e00c      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e64:	2307      	movs	r3, #7
 8000e66:	e00a      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e68:	2305      	movs	r3, #5
 8000e6a:	e008      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e6c:	2304      	movs	r3, #4
 8000e6e:	e006      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e70:	2303      	movs	r3, #3
 8000e72:	e004      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e74:	2302      	movs	r3, #2
 8000e76:	e002      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e78:	2301      	movs	r3, #1
 8000e7a:	e000      	b.n	8000e7e <HAL_GPIO_Init+0x20e>
 8000e7c:	2300      	movs	r3, #0
 8000e7e:	697a      	ldr	r2, [r7, #20]
 8000e80:	f002 0203 	and.w	r2, r2, #3
 8000e84:	0092      	lsls	r2, r2, #2
 8000e86:	4093      	lsls	r3, r2
 8000e88:	693a      	ldr	r2, [r7, #16]
 8000e8a:	4313      	orrs	r3, r2
 8000e8c:	613b      	str	r3, [r7, #16]
        SYSCFG->EXTICR[position >> 2] = temp;
 8000e8e:	4936      	ldr	r1, [pc, #216]	; (8000f68 <HAL_GPIO_Init+0x2f8>)
 8000e90:	697b      	ldr	r3, [r7, #20]
 8000e92:	089b      	lsrs	r3, r3, #2
 8000e94:	3302      	adds	r3, #2
 8000e96:	693a      	ldr	r2, [r7, #16]
 8000e98:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 8000e9c:	4b3a      	ldr	r3, [pc, #232]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000e9e:	681b      	ldr	r3, [r3, #0]
 8000ea0:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8000ea2:	68fb      	ldr	r3, [r7, #12]
 8000ea4:	43db      	mvns	r3, r3
 8000ea6:	693a      	ldr	r2, [r7, #16]
 8000ea8:	4013      	ands	r3, r2
 8000eaa:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8000eac:	683b      	ldr	r3, [r7, #0]
 8000eae:	685b      	ldr	r3, [r3, #4]
 8000eb0:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8000eb4:	2b00      	cmp	r3, #0
 8000eb6:	d003      	beq.n	8000ec0 <HAL_GPIO_Init+0x250>
        {
          SET_BIT(temp, iocurrent);
 8000eb8:	693a      	ldr	r2, [r7, #16]
 8000eba:	68fb      	ldr	r3, [r7, #12]
 8000ebc:	4313      	orrs	r3, r2
 8000ebe:	613b      	str	r3, [r7, #16]
        }
        EXTI->IMR = temp;
 8000ec0:	4a31      	ldr	r2, [pc, #196]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000ec2:	693b      	ldr	r3, [r7, #16]
 8000ec4:	6013      	str	r3, [r2, #0]

        temp = EXTI->EMR;
 8000ec6:	4b30      	ldr	r3, [pc, #192]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000ec8:	685b      	ldr	r3, [r3, #4]
 8000eca:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8000ecc:	68fb      	ldr	r3, [r7, #12]
 8000ece:	43db      	mvns	r3, r3
 8000ed0:	693a      	ldr	r2, [r7, #16]
 8000ed2:	4013      	ands	r3, r2
 8000ed4:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 8000ed6:	683b      	ldr	r3, [r7, #0]
 8000ed8:	685b      	ldr	r3, [r3, #4]
 8000eda:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000ede:	2b00      	cmp	r3, #0
 8000ee0:	d003      	beq.n	8000eea <HAL_GPIO_Init+0x27a>
        {
          SET_BIT(temp, iocurrent);
 8000ee2:	693a      	ldr	r2, [r7, #16]
 8000ee4:	68fb      	ldr	r3, [r7, #12]
 8000ee6:	4313      	orrs	r3, r2
 8000ee8:	613b      	str	r3, [r7, #16]
        }
        EXTI->EMR = temp;
 8000eea:	4a27      	ldr	r2, [pc, #156]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000eec:	693b      	ldr	r3, [r7, #16]
 8000eee:	6053      	str	r3, [r2, #4]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 8000ef0:	4b25      	ldr	r3, [pc, #148]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000ef2:	689b      	ldr	r3, [r3, #8]
 8000ef4:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8000ef6:	68fb      	ldr	r3, [r7, #12]
 8000ef8:	43db      	mvns	r3, r3
 8000efa:	693a      	ldr	r2, [r7, #16]
 8000efc:	4013      	ands	r3, r2
 8000efe:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 8000f00:	683b      	ldr	r3, [r7, #0]
 8000f02:	685b      	ldr	r3, [r3, #4]
 8000f04:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 8000f08:	2b00      	cmp	r3, #0
 8000f0a:	d003      	beq.n	8000f14 <HAL_GPIO_Init+0x2a4>
        {
          SET_BIT(temp, iocurrent);
 8000f0c:	693a      	ldr	r2, [r7, #16]
 8000f0e:	68fb      	ldr	r3, [r7, #12]
 8000f10:	4313      	orrs	r3, r2
 8000f12:	613b      	str	r3, [r7, #16]
        }
        EXTI->RTSR = temp;
 8000f14:	4a1c      	ldr	r2, [pc, #112]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000f16:	693b      	ldr	r3, [r7, #16]
 8000f18:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR;
 8000f1a:	4b1b      	ldr	r3, [pc, #108]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000f1c:	68db      	ldr	r3, [r3, #12]
 8000f1e:	613b      	str	r3, [r7, #16]
        CLEAR_BIT(temp, (uint32_t)iocurrent);
 8000f20:	68fb      	ldr	r3, [r7, #12]
 8000f22:	43db      	mvns	r3, r3
 8000f24:	693a      	ldr	r2, [r7, #16]
 8000f26:	4013      	ands	r3, r2
 8000f28:	613b      	str	r3, [r7, #16]
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 8000f2a:	683b      	ldr	r3, [r7, #0]
 8000f2c:	685b      	ldr	r3, [r3, #4]
 8000f2e:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8000f32:	2b00      	cmp	r3, #0
 8000f34:	d003      	beq.n	8000f3e <HAL_GPIO_Init+0x2ce>
        {
          SET_BIT(temp, iocurrent);
 8000f36:	693a      	ldr	r2, [r7, #16]
 8000f38:	68fb      	ldr	r3, [r7, #12]
 8000f3a:	4313      	orrs	r3, r2
 8000f3c:	613b      	str	r3, [r7, #16]
        }
        EXTI->FTSR = temp;
 8000f3e:	4a12      	ldr	r2, [pc, #72]	; (8000f88 <HAL_GPIO_Init+0x318>)
 8000f40:	693b      	ldr	r3, [r7, #16]
 8000f42:	60d3      	str	r3, [r2, #12]
      }
    }

    position++;
 8000f44:	697b      	ldr	r3, [r7, #20]
 8000f46:	3301      	adds	r3, #1
 8000f48:	617b      	str	r3, [r7, #20]
  while (((GPIO_Init->Pin) >> position) != 0)
 8000f4a:	683b      	ldr	r3, [r7, #0]
 8000f4c:	681a      	ldr	r2, [r3, #0]
 8000f4e:	697b      	ldr	r3, [r7, #20]
 8000f50:	fa22 f303 	lsr.w	r3, r2, r3
 8000f54:	2b00      	cmp	r3, #0
 8000f56:	f47f ae97 	bne.w	8000c88 <HAL_GPIO_Init+0x18>
  }
}
 8000f5a:	bf00      	nop
 8000f5c:	371c      	adds	r7, #28
 8000f5e:	46bd      	mov	sp, r7
 8000f60:	bc80      	pop	{r7}
 8000f62:	4770      	bx	lr
 8000f64:	40023800 	.word	0x40023800
 8000f68:	40010000 	.word	0x40010000
 8000f6c:	40020000 	.word	0x40020000
 8000f70:	40020400 	.word	0x40020400
 8000f74:	40020800 	.word	0x40020800
 8000f78:	40020c00 	.word	0x40020c00
 8000f7c:	40021000 	.word	0x40021000
 8000f80:	40021400 	.word	0x40021400
 8000f84:	40021800 	.word	0x40021800
 8000f88:	40010400 	.word	0x40010400

08000f8c <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8000f8c:	b480      	push	{r7}
 8000f8e:	b083      	sub	sp, #12
 8000f90:	af00      	add	r7, sp, #0
 8000f92:	6078      	str	r0, [r7, #4]
 8000f94:	460b      	mov	r3, r1
 8000f96:	807b      	strh	r3, [r7, #2]
 8000f98:	4613      	mov	r3, r2
 8000f9a:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8000f9c:	787b      	ldrb	r3, [r7, #1]
 8000f9e:	2b00      	cmp	r3, #0
 8000fa0:	d003      	beq.n	8000faa <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8000fa2:	887a      	ldrh	r2, [r7, #2]
 8000fa4:	687b      	ldr	r3, [r7, #4]
 8000fa6:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
  }
}
 8000fa8:	e003      	b.n	8000fb2 <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
 8000faa:	887b      	ldrh	r3, [r7, #2]
 8000fac:	041a      	lsls	r2, r3, #16
 8000fae:	687b      	ldr	r3, [r7, #4]
 8000fb0:	619a      	str	r2, [r3, #24]
}
 8000fb2:	bf00      	nop
 8000fb4:	370c      	adds	r7, #12
 8000fb6:	46bd      	mov	sp, r7
 8000fb8:	bc80      	pop	{r7}
 8000fba:	4770      	bx	lr

08000fbc <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8000fbc:	b580      	push	{r7, lr}
 8000fbe:	b088      	sub	sp, #32
 8000fc0:	af00      	add	r7, sp, #0
 8000fc2:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  HAL_StatusTypeDef status;
  uint32_t sysclk_source, pll_config;

  /* Check the parameters */
  if(RCC_OscInitStruct == NULL)
 8000fc4:	687b      	ldr	r3, [r7, #4]
 8000fc6:	2b00      	cmp	r3, #0
 8000fc8:	d101      	bne.n	8000fce <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8000fca:	2301      	movs	r3, #1
 8000fcc:	e31d      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
  }

  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
 8000fce:	4b94      	ldr	r3, [pc, #592]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8000fd0:	689b      	ldr	r3, [r3, #8]
 8000fd2:	f003 030c 	and.w	r3, r3, #12
 8000fd6:	61bb      	str	r3, [r7, #24]
  pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
 8000fd8:	4b91      	ldr	r3, [pc, #580]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8000fda:	689b      	ldr	r3, [r3, #8]
 8000fdc:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8000fe0:	617b      	str	r3, [r7, #20]

  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000fe2:	687b      	ldr	r3, [r7, #4]
 8000fe4:	681b      	ldr	r3, [r3, #0]
 8000fe6:	f003 0301 	and.w	r3, r3, #1
 8000fea:	2b00      	cmp	r3, #0
 8000fec:	d07b      	beq.n	80010e6 <HAL_RCC_OscConfig+0x12a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
 8000fee:	69bb      	ldr	r3, [r7, #24]
 8000ff0:	2b08      	cmp	r3, #8
 8000ff2:	d006      	beq.n	8001002 <HAL_RCC_OscConfig+0x46>
       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
 8000ff4:	69bb      	ldr	r3, [r7, #24]
 8000ff6:	2b0c      	cmp	r3, #12
 8000ff8:	d10f      	bne.n	800101a <HAL_RCC_OscConfig+0x5e>
 8000ffa:	697b      	ldr	r3, [r7, #20]
 8000ffc:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8001000:	d10b      	bne.n	800101a <HAL_RCC_OscConfig+0x5e>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8001002:	4b87      	ldr	r3, [pc, #540]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001004:	681b      	ldr	r3, [r3, #0]
 8001006:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800100a:	2b00      	cmp	r3, #0
 800100c:	d06a      	beq.n	80010e4 <HAL_RCC_OscConfig+0x128>
 800100e:	687b      	ldr	r3, [r7, #4]
 8001010:	685b      	ldr	r3, [r3, #4]
 8001012:	2b00      	cmp	r3, #0
 8001014:	d166      	bne.n	80010e4 <HAL_RCC_OscConfig+0x128>
      {
        return HAL_ERROR;
 8001016:	2301      	movs	r3, #1
 8001018:	e2f7      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 800101a:	687b      	ldr	r3, [r7, #4]
 800101c:	685b      	ldr	r3, [r3, #4]
 800101e:	2b01      	cmp	r3, #1
 8001020:	d106      	bne.n	8001030 <HAL_RCC_OscConfig+0x74>
 8001022:	4b7f      	ldr	r3, [pc, #508]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001024:	681b      	ldr	r3, [r3, #0]
 8001026:	4a7e      	ldr	r2, [pc, #504]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001028:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 800102c:	6013      	str	r3, [r2, #0]
 800102e:	e02d      	b.n	800108c <HAL_RCC_OscConfig+0xd0>
 8001030:	687b      	ldr	r3, [r7, #4]
 8001032:	685b      	ldr	r3, [r3, #4]
 8001034:	2b00      	cmp	r3, #0
 8001036:	d10c      	bne.n	8001052 <HAL_RCC_OscConfig+0x96>
 8001038:	4b79      	ldr	r3, [pc, #484]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800103a:	681b      	ldr	r3, [r3, #0]
 800103c:	4a78      	ldr	r2, [pc, #480]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800103e:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8001042:	6013      	str	r3, [r2, #0]
 8001044:	4b76      	ldr	r3, [pc, #472]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001046:	681b      	ldr	r3, [r3, #0]
 8001048:	4a75      	ldr	r2, [pc, #468]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800104a:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 800104e:	6013      	str	r3, [r2, #0]
 8001050:	e01c      	b.n	800108c <HAL_RCC_OscConfig+0xd0>
 8001052:	687b      	ldr	r3, [r7, #4]
 8001054:	685b      	ldr	r3, [r3, #4]
 8001056:	2b05      	cmp	r3, #5
 8001058:	d10c      	bne.n	8001074 <HAL_RCC_OscConfig+0xb8>
 800105a:	4b71      	ldr	r3, [pc, #452]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800105c:	681b      	ldr	r3, [r3, #0]
 800105e:	4a70      	ldr	r2, [pc, #448]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001060:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8001064:	6013      	str	r3, [r2, #0]
 8001066:	4b6e      	ldr	r3, [pc, #440]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001068:	681b      	ldr	r3, [r3, #0]
 800106a:	4a6d      	ldr	r2, [pc, #436]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800106c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001070:	6013      	str	r3, [r2, #0]
 8001072:	e00b      	b.n	800108c <HAL_RCC_OscConfig+0xd0>
 8001074:	4b6a      	ldr	r3, [pc, #424]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001076:	681b      	ldr	r3, [r3, #0]
 8001078:	4a69      	ldr	r2, [pc, #420]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800107a:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 800107e:	6013      	str	r3, [r2, #0]
 8001080:	4b67      	ldr	r3, [pc, #412]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001082:	681b      	ldr	r3, [r3, #0]
 8001084:	4a66      	ldr	r2, [pc, #408]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001086:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 800108a:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800108c:	687b      	ldr	r3, [r7, #4]
 800108e:	685b      	ldr	r3, [r3, #4]
 8001090:	2b00      	cmp	r3, #0
 8001092:	d013      	beq.n	80010bc <HAL_RCC_OscConfig+0x100>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001094:	f7ff fcdc 	bl	8000a50 <HAL_GetTick>
 8001098:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 800109a:	e008      	b.n	80010ae <HAL_RCC_OscConfig+0xf2>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 800109c:	f7ff fcd8 	bl	8000a50 <HAL_GetTick>
 80010a0:	4602      	mov	r2, r0
 80010a2:	693b      	ldr	r3, [r7, #16]
 80010a4:	1ad3      	subs	r3, r2, r3
 80010a6:	2b64      	cmp	r3, #100	; 0x64
 80010a8:	d901      	bls.n	80010ae <HAL_RCC_OscConfig+0xf2>
          {
            return HAL_TIMEOUT;
 80010aa:	2303      	movs	r3, #3
 80010ac:	e2ad      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 80010ae:	4b5c      	ldr	r3, [pc, #368]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 80010b0:	681b      	ldr	r3, [r3, #0]
 80010b2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80010b6:	2b00      	cmp	r3, #0
 80010b8:	d0f0      	beq.n	800109c <HAL_RCC_OscConfig+0xe0>
 80010ba:	e014      	b.n	80010e6 <HAL_RCC_OscConfig+0x12a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80010bc:	f7ff fcc8 	bl	8000a50 <HAL_GetTick>
 80010c0:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 80010c2:	e008      	b.n	80010d6 <HAL_RCC_OscConfig+0x11a>
        {
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 80010c4:	f7ff fcc4 	bl	8000a50 <HAL_GetTick>
 80010c8:	4602      	mov	r2, r0
 80010ca:	693b      	ldr	r3, [r7, #16]
 80010cc:	1ad3      	subs	r3, r2, r3
 80010ce:	2b64      	cmp	r3, #100	; 0x64
 80010d0:	d901      	bls.n	80010d6 <HAL_RCC_OscConfig+0x11a>
          {
            return HAL_TIMEOUT;
 80010d2:	2303      	movs	r3, #3
 80010d4:	e299      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
 80010d6:	4b52      	ldr	r3, [pc, #328]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 80010d8:	681b      	ldr	r3, [r3, #0]
 80010da:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80010de:	2b00      	cmp	r3, #0
 80010e0:	d1f0      	bne.n	80010c4 <HAL_RCC_OscConfig+0x108>
 80010e2:	e000      	b.n	80010e6 <HAL_RCC_OscConfig+0x12a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 80010e4:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 80010e6:	687b      	ldr	r3, [r7, #4]
 80010e8:	681b      	ldr	r3, [r3, #0]
 80010ea:	f003 0302 	and.w	r3, r3, #2
 80010ee:	2b00      	cmp	r3, #0
 80010f0:	d05a      	beq.n	80011a8 <HAL_RCC_OscConfig+0x1ec>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
 80010f2:	69bb      	ldr	r3, [r7, #24]
 80010f4:	2b04      	cmp	r3, #4
 80010f6:	d005      	beq.n	8001104 <HAL_RCC_OscConfig+0x148>
       || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
 80010f8:	69bb      	ldr	r3, [r7, #24]
 80010fa:	2b0c      	cmp	r3, #12
 80010fc:	d119      	bne.n	8001132 <HAL_RCC_OscConfig+0x176>
 80010fe:	697b      	ldr	r3, [r7, #20]
 8001100:	2b00      	cmp	r3, #0
 8001102:	d116      	bne.n	8001132 <HAL_RCC_OscConfig+0x176>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8001104:	4b46      	ldr	r3, [pc, #280]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001106:	681b      	ldr	r3, [r3, #0]
 8001108:	f003 0302 	and.w	r3, r3, #2
 800110c:	2b00      	cmp	r3, #0
 800110e:	d005      	beq.n	800111c <HAL_RCC_OscConfig+0x160>
 8001110:	687b      	ldr	r3, [r7, #4]
 8001112:	68db      	ldr	r3, [r3, #12]
 8001114:	2b01      	cmp	r3, #1
 8001116:	d001      	beq.n	800111c <HAL_RCC_OscConfig+0x160>
      {
        return HAL_ERROR;
 8001118:	2301      	movs	r3, #1
 800111a:	e276      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800111c:	4b40      	ldr	r3, [pc, #256]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800111e:	685b      	ldr	r3, [r3, #4]
 8001120:	f423 52f8 	bic.w	r2, r3, #7936	; 0x1f00
 8001124:	687b      	ldr	r3, [r7, #4]
 8001126:	691b      	ldr	r3, [r3, #16]
 8001128:	021b      	lsls	r3, r3, #8
 800112a:	493d      	ldr	r1, [pc, #244]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800112c:	4313      	orrs	r3, r2
 800112e:	604b      	str	r3, [r1, #4]
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8001130:	e03a      	b.n	80011a8 <HAL_RCC_OscConfig+0x1ec>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8001132:	687b      	ldr	r3, [r7, #4]
 8001134:	68db      	ldr	r3, [r3, #12]
 8001136:	2b00      	cmp	r3, #0
 8001138:	d020      	beq.n	800117c <HAL_RCC_OscConfig+0x1c0>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 800113a:	4b3a      	ldr	r3, [pc, #232]	; (8001224 <HAL_RCC_OscConfig+0x268>)
 800113c:	2201      	movs	r2, #1
 800113e:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001140:	f7ff fc86 	bl	8000a50 <HAL_GetTick>
 8001144:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 8001146:	e008      	b.n	800115a <HAL_RCC_OscConfig+0x19e>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8001148:	f7ff fc82 	bl	8000a50 <HAL_GetTick>
 800114c:	4602      	mov	r2, r0
 800114e:	693b      	ldr	r3, [r7, #16]
 8001150:	1ad3      	subs	r3, r2, r3
 8001152:	2b02      	cmp	r3, #2
 8001154:	d901      	bls.n	800115a <HAL_RCC_OscConfig+0x19e>
          {
            return HAL_TIMEOUT;
 8001156:	2303      	movs	r3, #3
 8001158:	e257      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 800115a:	4b31      	ldr	r3, [pc, #196]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800115c:	681b      	ldr	r3, [r3, #0]
 800115e:	f003 0302 	and.w	r3, r3, #2
 8001162:	2b00      	cmp	r3, #0
 8001164:	d0f0      	beq.n	8001148 <HAL_RCC_OscConfig+0x18c>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8001166:	4b2e      	ldr	r3, [pc, #184]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001168:	685b      	ldr	r3, [r3, #4]
 800116a:	f423 52f8 	bic.w	r2, r3, #7936	; 0x1f00
 800116e:	687b      	ldr	r3, [r7, #4]
 8001170:	691b      	ldr	r3, [r3, #16]
 8001172:	021b      	lsls	r3, r3, #8
 8001174:	492a      	ldr	r1, [pc, #168]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001176:	4313      	orrs	r3, r2
 8001178:	604b      	str	r3, [r1, #4]
 800117a:	e015      	b.n	80011a8 <HAL_RCC_OscConfig+0x1ec>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 800117c:	4b29      	ldr	r3, [pc, #164]	; (8001224 <HAL_RCC_OscConfig+0x268>)
 800117e:	2200      	movs	r2, #0
 8001180:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001182:	f7ff fc65 	bl	8000a50 <HAL_GetTick>
 8001186:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 8001188:	e008      	b.n	800119c <HAL_RCC_OscConfig+0x1e0>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 800118a:	f7ff fc61 	bl	8000a50 <HAL_GetTick>
 800118e:	4602      	mov	r2, r0
 8001190:	693b      	ldr	r3, [r7, #16]
 8001192:	1ad3      	subs	r3, r2, r3
 8001194:	2b02      	cmp	r3, #2
 8001196:	d901      	bls.n	800119c <HAL_RCC_OscConfig+0x1e0>
          {
            return HAL_TIMEOUT;
 8001198:	2303      	movs	r3, #3
 800119a:	e236      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
 800119c:	4b20      	ldr	r3, [pc, #128]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800119e:	681b      	ldr	r3, [r3, #0]
 80011a0:	f003 0302 	and.w	r3, r3, #2
 80011a4:	2b00      	cmp	r3, #0
 80011a6:	d1f0      	bne.n	800118a <HAL_RCC_OscConfig+0x1ce>
        }
      }
    }
  }
  /*----------------------------- MSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
 80011a8:	687b      	ldr	r3, [r7, #4]
 80011aa:	681b      	ldr	r3, [r3, #0]
 80011ac:	f003 0310 	and.w	r3, r3, #16
 80011b0:	2b00      	cmp	r3, #0
 80011b2:	f000 80b8 	beq.w	8001326 <HAL_RCC_OscConfig+0x36a>
  {
    /* When the MSI is used as system clock it will not be disabled */
    if(sysclk_source == RCC_CFGR_SWS_MSI)
 80011b6:	69bb      	ldr	r3, [r7, #24]
 80011b8:	2b00      	cmp	r3, #0
 80011ba:	d170      	bne.n	800129e <HAL_RCC_OscConfig+0x2e2>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
 80011bc:	4b18      	ldr	r3, [pc, #96]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 80011be:	681b      	ldr	r3, [r3, #0]
 80011c0:	f403 7300 	and.w	r3, r3, #512	; 0x200
 80011c4:	2b00      	cmp	r3, #0
 80011c6:	d005      	beq.n	80011d4 <HAL_RCC_OscConfig+0x218>
 80011c8:	687b      	ldr	r3, [r7, #4]
 80011ca:	699b      	ldr	r3, [r3, #24]
 80011cc:	2b00      	cmp	r3, #0
 80011ce:	d101      	bne.n	80011d4 <HAL_RCC_OscConfig+0x218>
      {
        return HAL_ERROR;
 80011d0:	2301      	movs	r3, #1
 80011d2:	e21a      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
           must be correctly programmed according to the frequency of the CPU clock
           (HCLK) and the supply voltage of the device. */
        if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
 80011d4:	687b      	ldr	r3, [r7, #4]
 80011d6:	6a1a      	ldr	r2, [r3, #32]
 80011d8:	4b11      	ldr	r3, [pc, #68]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 80011da:	685b      	ldr	r3, [r3, #4]
 80011dc:	f403 4360 	and.w	r3, r3, #57344	; 0xe000
 80011e0:	429a      	cmp	r2, r3
 80011e2:	d921      	bls.n	8001228 <HAL_RCC_OscConfig+0x26c>
        {
          /* First increase number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 80011e4:	687b      	ldr	r3, [r7, #4]
 80011e6:	6a1b      	ldr	r3, [r3, #32]
 80011e8:	4618      	mov	r0, r3
 80011ea:	f000 fc47 	bl	8001a7c <RCC_SetFlashLatencyFromMSIRange>
 80011ee:	4603      	mov	r3, r0
 80011f0:	2b00      	cmp	r3, #0
 80011f2:	d001      	beq.n	80011f8 <HAL_RCC_OscConfig+0x23c>
          {
            return HAL_ERROR;
 80011f4:	2301      	movs	r3, #1
 80011f6:	e208      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
          }

          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 80011f8:	4b09      	ldr	r3, [pc, #36]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 80011fa:	685b      	ldr	r3, [r3, #4]
 80011fc:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8001200:	687b      	ldr	r3, [r7, #4]
 8001202:	6a1b      	ldr	r3, [r3, #32]
 8001204:	4906      	ldr	r1, [pc, #24]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 8001206:	4313      	orrs	r3, r2
 8001208:	604b      	str	r3, [r1, #4]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 800120a:	4b05      	ldr	r3, [pc, #20]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800120c:	685b      	ldr	r3, [r3, #4]
 800120e:	f023 427f 	bic.w	r2, r3, #4278190080	; 0xff000000
 8001212:	687b      	ldr	r3, [r7, #4]
 8001214:	69db      	ldr	r3, [r3, #28]
 8001216:	061b      	lsls	r3, r3, #24
 8001218:	4901      	ldr	r1, [pc, #4]	; (8001220 <HAL_RCC_OscConfig+0x264>)
 800121a:	4313      	orrs	r3, r2
 800121c:	604b      	str	r3, [r1, #4]
 800121e:	e020      	b.n	8001262 <HAL_RCC_OscConfig+0x2a6>
 8001220:	40023800 	.word	0x40023800
 8001224:	42470000 	.word	0x42470000
        }
        else
        {
          /* Else, keep current flash latency while decreasing applies */
          /* Selects the Multiple Speed oscillator (MSI) clock range .*/
          __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 8001228:	4ba4      	ldr	r3, [pc, #656]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800122a:	685b      	ldr	r3, [r3, #4]
 800122c:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8001230:	687b      	ldr	r3, [r7, #4]
 8001232:	6a1b      	ldr	r3, [r3, #32]
 8001234:	49a1      	ldr	r1, [pc, #644]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001236:	4313      	orrs	r3, r2
 8001238:	604b      	str	r3, [r1, #4]
          /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
          __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 800123a:	4ba0      	ldr	r3, [pc, #640]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800123c:	685b      	ldr	r3, [r3, #4]
 800123e:	f023 427f 	bic.w	r2, r3, #4278190080	; 0xff000000
 8001242:	687b      	ldr	r3, [r7, #4]
 8001244:	69db      	ldr	r3, [r3, #28]
 8001246:	061b      	lsls	r3, r3, #24
 8001248:	499c      	ldr	r1, [pc, #624]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800124a:	4313      	orrs	r3, r2
 800124c:	604b      	str	r3, [r1, #4]

          /* Decrease number of wait states update if necessary */
          if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
 800124e:	687b      	ldr	r3, [r7, #4]
 8001250:	6a1b      	ldr	r3, [r3, #32]
 8001252:	4618      	mov	r0, r3
 8001254:	f000 fc12 	bl	8001a7c <RCC_SetFlashLatencyFromMSIRange>
 8001258:	4603      	mov	r3, r0
 800125a:	2b00      	cmp	r3, #0
 800125c:	d001      	beq.n	8001262 <HAL_RCC_OscConfig+0x2a6>
          {
            return HAL_ERROR;
 800125e:	2301      	movs	r3, #1
 8001260:	e1d3      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
          }
        }

        /* Update the SystemCoreClock global variable */
        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
 8001262:	687b      	ldr	r3, [r7, #4]
 8001264:	6a1b      	ldr	r3, [r3, #32]
 8001266:	0b5b      	lsrs	r3, r3, #13
 8001268:	3301      	adds	r3, #1
 800126a:	f44f 4200 	mov.w	r2, #32768	; 0x8000
 800126e:	fa02 f303 	lsl.w	r3, r2, r3
                           >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
 8001272:	4a92      	ldr	r2, [pc, #584]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001274:	6892      	ldr	r2, [r2, #8]
 8001276:	0912      	lsrs	r2, r2, #4
 8001278:	f002 020f 	and.w	r2, r2, #15
 800127c:	4990      	ldr	r1, [pc, #576]	; (80014c0 <HAL_RCC_OscConfig+0x504>)
 800127e:	5c8a      	ldrb	r2, [r1, r2]
 8001280:	40d3      	lsrs	r3, r2
        SystemCoreClock =  (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
 8001282:	4a90      	ldr	r2, [pc, #576]	; (80014c4 <HAL_RCC_OscConfig+0x508>)
 8001284:	6013      	str	r3, [r2, #0]

        /* Configure the source of time base considering new system clocks settings*/
        status = HAL_InitTick(uwTickPrio);
 8001286:	4b90      	ldr	r3, [pc, #576]	; (80014c8 <HAL_RCC_OscConfig+0x50c>)
 8001288:	681b      	ldr	r3, [r3, #0]
 800128a:	4618      	mov	r0, r3
 800128c:	f7ff fb94 	bl	80009b8 <HAL_InitTick>
 8001290:	4603      	mov	r3, r0
 8001292:	73fb      	strb	r3, [r7, #15]
        if(status != HAL_OK)
 8001294:	7bfb      	ldrb	r3, [r7, #15]
 8001296:	2b00      	cmp	r3, #0
 8001298:	d045      	beq.n	8001326 <HAL_RCC_OscConfig+0x36a>
        {
          return status;
 800129a:	7bfb      	ldrb	r3, [r7, #15]
 800129c:	e1b5      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
    {
      /* Check MSI State */
      assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));

      /* Check the MSI State */
      if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
 800129e:	687b      	ldr	r3, [r7, #4]
 80012a0:	699b      	ldr	r3, [r3, #24]
 80012a2:	2b00      	cmp	r3, #0
 80012a4:	d029      	beq.n	80012fa <HAL_RCC_OscConfig+0x33e>
      {
        /* Enable the Multi Speed oscillator (MSI). */
        __HAL_RCC_MSI_ENABLE();
 80012a6:	4b89      	ldr	r3, [pc, #548]	; (80014cc <HAL_RCC_OscConfig+0x510>)
 80012a8:	2201      	movs	r2, #1
 80012aa:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80012ac:	f7ff fbd0 	bl	8000a50 <HAL_GetTick>
 80012b0:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 80012b2:	e008      	b.n	80012c6 <HAL_RCC_OscConfig+0x30a>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 80012b4:	f7ff fbcc 	bl	8000a50 <HAL_GetTick>
 80012b8:	4602      	mov	r2, r0
 80012ba:	693b      	ldr	r3, [r7, #16]
 80012bc:	1ad3      	subs	r3, r2, r3
 80012be:	2b02      	cmp	r3, #2
 80012c0:	d901      	bls.n	80012c6 <HAL_RCC_OscConfig+0x30a>
          {
            return HAL_TIMEOUT;
 80012c2:	2303      	movs	r3, #3
 80012c4:	e1a1      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 80012c6:	4b7d      	ldr	r3, [pc, #500]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80012c8:	681b      	ldr	r3, [r3, #0]
 80012ca:	f403 7300 	and.w	r3, r3, #512	; 0x200
 80012ce:	2b00      	cmp	r3, #0
 80012d0:	d0f0      	beq.n	80012b4 <HAL_RCC_OscConfig+0x2f8>
        /* Check MSICalibrationValue and MSIClockRange input parameters */
        assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
        assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));

        /* Selects the Multiple Speed oscillator (MSI) clock range .*/
        __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
 80012d2:	4b7a      	ldr	r3, [pc, #488]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80012d4:	685b      	ldr	r3, [r3, #4]
 80012d6:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 80012da:	687b      	ldr	r3, [r7, #4]
 80012dc:	6a1b      	ldr	r3, [r3, #32]
 80012de:	4977      	ldr	r1, [pc, #476]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80012e0:	4313      	orrs	r3, r2
 80012e2:	604b      	str	r3, [r1, #4]
         /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
 80012e4:	4b75      	ldr	r3, [pc, #468]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80012e6:	685b      	ldr	r3, [r3, #4]
 80012e8:	f023 427f 	bic.w	r2, r3, #4278190080	; 0xff000000
 80012ec:	687b      	ldr	r3, [r7, #4]
 80012ee:	69db      	ldr	r3, [r3, #28]
 80012f0:	061b      	lsls	r3, r3, #24
 80012f2:	4972      	ldr	r1, [pc, #456]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80012f4:	4313      	orrs	r3, r2
 80012f6:	604b      	str	r3, [r1, #4]
 80012f8:	e015      	b.n	8001326 <HAL_RCC_OscConfig+0x36a>

      }
      else
      {
        /* Disable the Multi Speed oscillator (MSI). */
        __HAL_RCC_MSI_DISABLE();
 80012fa:	4b74      	ldr	r3, [pc, #464]	; (80014cc <HAL_RCC_OscConfig+0x510>)
 80012fc:	2200      	movs	r2, #0
 80012fe:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001300:	f7ff fba6 	bl	8000a50 <HAL_GetTick>
 8001304:	6138      	str	r0, [r7, #16]

        /* Wait till MSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
 8001306:	e008      	b.n	800131a <HAL_RCC_OscConfig+0x35e>
        {
          if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
 8001308:	f7ff fba2 	bl	8000a50 <HAL_GetTick>
 800130c:	4602      	mov	r2, r0
 800130e:	693b      	ldr	r3, [r7, #16]
 8001310:	1ad3      	subs	r3, r2, r3
 8001312:	2b02      	cmp	r3, #2
 8001314:	d901      	bls.n	800131a <HAL_RCC_OscConfig+0x35e>
          {
            return HAL_TIMEOUT;
 8001316:	2303      	movs	r3, #3
 8001318:	e177      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
 800131a:	4b68      	ldr	r3, [pc, #416]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800131c:	681b      	ldr	r3, [r3, #0]
 800131e:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8001322:	2b00      	cmp	r3, #0
 8001324:	d1f0      	bne.n	8001308 <HAL_RCC_OscConfig+0x34c>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8001326:	687b      	ldr	r3, [r7, #4]
 8001328:	681b      	ldr	r3, [r3, #0]
 800132a:	f003 0308 	and.w	r3, r3, #8
 800132e:	2b00      	cmp	r3, #0
 8001330:	d030      	beq.n	8001394 <HAL_RCC_OscConfig+0x3d8>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8001332:	687b      	ldr	r3, [r7, #4]
 8001334:	695b      	ldr	r3, [r3, #20]
 8001336:	2b00      	cmp	r3, #0
 8001338:	d016      	beq.n	8001368 <HAL_RCC_OscConfig+0x3ac>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 800133a:	4b65      	ldr	r3, [pc, #404]	; (80014d0 <HAL_RCC_OscConfig+0x514>)
 800133c:	2201      	movs	r2, #1
 800133e:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8001340:	f7ff fb86 	bl	8000a50 <HAL_GetTick>
 8001344:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 8001346:	e008      	b.n	800135a <HAL_RCC_OscConfig+0x39e>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8001348:	f7ff fb82 	bl	8000a50 <HAL_GetTick>
 800134c:	4602      	mov	r2, r0
 800134e:	693b      	ldr	r3, [r7, #16]
 8001350:	1ad3      	subs	r3, r2, r3
 8001352:	2b02      	cmp	r3, #2
 8001354:	d901      	bls.n	800135a <HAL_RCC_OscConfig+0x39e>
        {
          return HAL_TIMEOUT;
 8001356:	2303      	movs	r3, #3
 8001358:	e157      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
 800135a:	4b58      	ldr	r3, [pc, #352]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800135c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800135e:	f003 0302 	and.w	r3, r3, #2
 8001362:	2b00      	cmp	r3, #0
 8001364:	d0f0      	beq.n	8001348 <HAL_RCC_OscConfig+0x38c>
 8001366:	e015      	b.n	8001394 <HAL_RCC_OscConfig+0x3d8>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8001368:	4b59      	ldr	r3, [pc, #356]	; (80014d0 <HAL_RCC_OscConfig+0x514>)
 800136a:	2200      	movs	r2, #0
 800136c:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 800136e:	f7ff fb6f 	bl	8000a50 <HAL_GetTick>
 8001372:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8001374:	e008      	b.n	8001388 <HAL_RCC_OscConfig+0x3cc>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8001376:	f7ff fb6b 	bl	8000a50 <HAL_GetTick>
 800137a:	4602      	mov	r2, r0
 800137c:	693b      	ldr	r3, [r7, #16]
 800137e:	1ad3      	subs	r3, r2, r3
 8001380:	2b02      	cmp	r3, #2
 8001382:	d901      	bls.n	8001388 <HAL_RCC_OscConfig+0x3cc>
        {
          return HAL_TIMEOUT;
 8001384:	2303      	movs	r3, #3
 8001386:	e140      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
 8001388:	4b4c      	ldr	r3, [pc, #304]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800138a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800138c:	f003 0302 	and.w	r3, r3, #2
 8001390:	2b00      	cmp	r3, #0
 8001392:	d1f0      	bne.n	8001376 <HAL_RCC_OscConfig+0x3ba>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8001394:	687b      	ldr	r3, [r7, #4]
 8001396:	681b      	ldr	r3, [r3, #0]
 8001398:	f003 0304 	and.w	r3, r3, #4
 800139c:	2b00      	cmp	r3, #0
 800139e:	f000 80b5 	beq.w	800150c <HAL_RCC_OscConfig+0x550>
  {
    FlagStatus       pwrclkchanged = RESET;
 80013a2:	2300      	movs	r3, #0
 80013a4:	77fb      	strb	r3, [r7, #31]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 80013a6:	4b45      	ldr	r3, [pc, #276]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80013a8:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80013aa:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80013ae:	2b00      	cmp	r3, #0
 80013b0:	d10d      	bne.n	80013ce <HAL_RCC_OscConfig+0x412>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 80013b2:	4b42      	ldr	r3, [pc, #264]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80013b4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80013b6:	4a41      	ldr	r2, [pc, #260]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80013b8:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80013bc:	6253      	str	r3, [r2, #36]	; 0x24
 80013be:	4b3f      	ldr	r3, [pc, #252]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80013c0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80013c2:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80013c6:	60bb      	str	r3, [r7, #8]
 80013c8:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 80013ca:	2301      	movs	r3, #1
 80013cc:	77fb      	strb	r3, [r7, #31]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80013ce:	4b41      	ldr	r3, [pc, #260]	; (80014d4 <HAL_RCC_OscConfig+0x518>)
 80013d0:	681b      	ldr	r3, [r3, #0]
 80013d2:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80013d6:	2b00      	cmp	r3, #0
 80013d8:	d118      	bne.n	800140c <HAL_RCC_OscConfig+0x450>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 80013da:	4b3e      	ldr	r3, [pc, #248]	; (80014d4 <HAL_RCC_OscConfig+0x518>)
 80013dc:	681b      	ldr	r3, [r3, #0]
 80013de:	4a3d      	ldr	r2, [pc, #244]	; (80014d4 <HAL_RCC_OscConfig+0x518>)
 80013e0:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 80013e4:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 80013e6:	f7ff fb33 	bl	8000a50 <HAL_GetTick>
 80013ea:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80013ec:	e008      	b.n	8001400 <HAL_RCC_OscConfig+0x444>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 80013ee:	f7ff fb2f 	bl	8000a50 <HAL_GetTick>
 80013f2:	4602      	mov	r2, r0
 80013f4:	693b      	ldr	r3, [r7, #16]
 80013f6:	1ad3      	subs	r3, r2, r3
 80013f8:	2b64      	cmp	r3, #100	; 0x64
 80013fa:	d901      	bls.n	8001400 <HAL_RCC_OscConfig+0x444>
        {
          return HAL_TIMEOUT;
 80013fc:	2303      	movs	r3, #3
 80013fe:	e104      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001400:	4b34      	ldr	r3, [pc, #208]	; (80014d4 <HAL_RCC_OscConfig+0x518>)
 8001402:	681b      	ldr	r3, [r3, #0]
 8001404:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001408:	2b00      	cmp	r3, #0
 800140a:	d0f0      	beq.n	80013ee <HAL_RCC_OscConfig+0x432>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 800140c:	687b      	ldr	r3, [r7, #4]
 800140e:	689b      	ldr	r3, [r3, #8]
 8001410:	2b01      	cmp	r3, #1
 8001412:	d106      	bne.n	8001422 <HAL_RCC_OscConfig+0x466>
 8001414:	4b29      	ldr	r3, [pc, #164]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001416:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001418:	4a28      	ldr	r2, [pc, #160]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800141a:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 800141e:	6353      	str	r3, [r2, #52]	; 0x34
 8001420:	e02d      	b.n	800147e <HAL_RCC_OscConfig+0x4c2>
 8001422:	687b      	ldr	r3, [r7, #4]
 8001424:	689b      	ldr	r3, [r3, #8]
 8001426:	2b00      	cmp	r3, #0
 8001428:	d10c      	bne.n	8001444 <HAL_RCC_OscConfig+0x488>
 800142a:	4b24      	ldr	r3, [pc, #144]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800142c:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800142e:	4a23      	ldr	r2, [pc, #140]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001430:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 8001434:	6353      	str	r3, [r2, #52]	; 0x34
 8001436:	4b21      	ldr	r3, [pc, #132]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001438:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800143a:	4a20      	ldr	r2, [pc, #128]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800143c:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
 8001440:	6353      	str	r3, [r2, #52]	; 0x34
 8001442:	e01c      	b.n	800147e <HAL_RCC_OscConfig+0x4c2>
 8001444:	687b      	ldr	r3, [r7, #4]
 8001446:	689b      	ldr	r3, [r3, #8]
 8001448:	2b05      	cmp	r3, #5
 800144a:	d10c      	bne.n	8001466 <HAL_RCC_OscConfig+0x4aa>
 800144c:	4b1b      	ldr	r3, [pc, #108]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800144e:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001450:	4a1a      	ldr	r2, [pc, #104]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001452:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 8001456:	6353      	str	r3, [r2, #52]	; 0x34
 8001458:	4b18      	ldr	r3, [pc, #96]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800145a:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800145c:	4a17      	ldr	r2, [pc, #92]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800145e:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001462:	6353      	str	r3, [r2, #52]	; 0x34
 8001464:	e00b      	b.n	800147e <HAL_RCC_OscConfig+0x4c2>
 8001466:	4b15      	ldr	r3, [pc, #84]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001468:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 800146a:	4a14      	ldr	r2, [pc, #80]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 800146c:	f423 7380 	bic.w	r3, r3, #256	; 0x100
 8001470:	6353      	str	r3, [r2, #52]	; 0x34
 8001472:	4b12      	ldr	r3, [pc, #72]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001474:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001476:	4a11      	ldr	r2, [pc, #68]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 8001478:	f423 6380 	bic.w	r3, r3, #1024	; 0x400
 800147c:	6353      	str	r3, [r2, #52]	; 0x34
    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 800147e:	687b      	ldr	r3, [r7, #4]
 8001480:	689b      	ldr	r3, [r3, #8]
 8001482:	2b00      	cmp	r3, #0
 8001484:	d015      	beq.n	80014b2 <HAL_RCC_OscConfig+0x4f6>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8001486:	f7ff fae3 	bl	8000a50 <HAL_GetTick>
 800148a:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 800148c:	e00a      	b.n	80014a4 <HAL_RCC_OscConfig+0x4e8>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 800148e:	f7ff fadf 	bl	8000a50 <HAL_GetTick>
 8001492:	4602      	mov	r2, r0
 8001494:	693b      	ldr	r3, [r7, #16]
 8001496:	1ad3      	subs	r3, r2, r3
 8001498:	f241 3288 	movw	r2, #5000	; 0x1388
 800149c:	4293      	cmp	r3, r2
 800149e:	d901      	bls.n	80014a4 <HAL_RCC_OscConfig+0x4e8>
        {
          return HAL_TIMEOUT;
 80014a0:	2303      	movs	r3, #3
 80014a2:	e0b2      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 80014a4:	4b05      	ldr	r3, [pc, #20]	; (80014bc <HAL_RCC_OscConfig+0x500>)
 80014a6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 80014a8:	f403 7300 	and.w	r3, r3, #512	; 0x200
 80014ac:	2b00      	cmp	r3, #0
 80014ae:	d0ee      	beq.n	800148e <HAL_RCC_OscConfig+0x4d2>
 80014b0:	e023      	b.n	80014fa <HAL_RCC_OscConfig+0x53e>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80014b2:	f7ff facd 	bl	8000a50 <HAL_GetTick>
 80014b6:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 80014b8:	e019      	b.n	80014ee <HAL_RCC_OscConfig+0x532>
 80014ba:	bf00      	nop
 80014bc:	40023800 	.word	0x40023800
 80014c0:	080025f0 	.word	0x080025f0
 80014c4:	20000000 	.word	0x20000000
 80014c8:	20000004 	.word	0x20000004
 80014cc:	42470020 	.word	0x42470020
 80014d0:	42470680 	.word	0x42470680
 80014d4:	40007000 	.word	0x40007000
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 80014d8:	f7ff faba 	bl	8000a50 <HAL_GetTick>
 80014dc:	4602      	mov	r2, r0
 80014de:	693b      	ldr	r3, [r7, #16]
 80014e0:	1ad3      	subs	r3, r2, r3
 80014e2:	f241 3288 	movw	r2, #5000	; 0x1388
 80014e6:	4293      	cmp	r3, r2
 80014e8:	d901      	bls.n	80014ee <HAL_RCC_OscConfig+0x532>
        {
          return HAL_TIMEOUT;
 80014ea:	2303      	movs	r3, #3
 80014ec:	e08d      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
 80014ee:	4b49      	ldr	r3, [pc, #292]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 80014f0:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 80014f2:	f403 7300 	and.w	r3, r3, #512	; 0x200
 80014f6:	2b00      	cmp	r3, #0
 80014f8:	d1ee      	bne.n	80014d8 <HAL_RCC_OscConfig+0x51c>
        }
      }
    }

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 80014fa:	7ffb      	ldrb	r3, [r7, #31]
 80014fc:	2b01      	cmp	r3, #1
 80014fe:	d105      	bne.n	800150c <HAL_RCC_OscConfig+0x550>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8001500:	4b44      	ldr	r3, [pc, #272]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 8001502:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001504:	4a43      	ldr	r2, [pc, #268]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 8001506:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 800150a:	6253      	str	r3, [r2, #36]	; 0x24
  }

  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 800150c:	687b      	ldr	r3, [r7, #4]
 800150e:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001510:	2b00      	cmp	r3, #0
 8001512:	d079      	beq.n	8001608 <HAL_RCC_OscConfig+0x64c>
  {
    /* Check if the PLL is used as system clock or not */
    if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8001514:	69bb      	ldr	r3, [r7, #24]
 8001516:	2b0c      	cmp	r3, #12
 8001518:	d056      	beq.n	80015c8 <HAL_RCC_OscConfig+0x60c>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 800151a:	687b      	ldr	r3, [r7, #4]
 800151c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800151e:	2b02      	cmp	r3, #2
 8001520:	d13b      	bne.n	800159a <HAL_RCC_OscConfig+0x5de>
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001522:	4b3d      	ldr	r3, [pc, #244]	; (8001618 <HAL_RCC_OscConfig+0x65c>)
 8001524:	2200      	movs	r2, #0
 8001526:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001528:	f7ff fa92 	bl	8000a50 <HAL_GetTick>
 800152c:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 800152e:	e008      	b.n	8001542 <HAL_RCC_OscConfig+0x586>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8001530:	f7ff fa8e 	bl	8000a50 <HAL_GetTick>
 8001534:	4602      	mov	r2, r0
 8001536:	693b      	ldr	r3, [r7, #16]
 8001538:	1ad3      	subs	r3, r2, r3
 800153a:	2b02      	cmp	r3, #2
 800153c:	d901      	bls.n	8001542 <HAL_RCC_OscConfig+0x586>
          {
            return HAL_TIMEOUT;
 800153e:	2303      	movs	r3, #3
 8001540:	e063      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 8001542:	4b34      	ldr	r3, [pc, #208]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 8001544:	681b      	ldr	r3, [r3, #0]
 8001546:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 800154a:	2b00      	cmp	r3, #0
 800154c:	d1f0      	bne.n	8001530 <HAL_RCC_OscConfig+0x574>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 800154e:	4b31      	ldr	r3, [pc, #196]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 8001550:	689b      	ldr	r3, [r3, #8]
 8001552:	f423 027d 	bic.w	r2, r3, #16580608	; 0xfd0000
 8001556:	687b      	ldr	r3, [r7, #4]
 8001558:	6a99      	ldr	r1, [r3, #40]	; 0x28
 800155a:	687b      	ldr	r3, [r7, #4]
 800155c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800155e:	4319      	orrs	r1, r3
 8001560:	687b      	ldr	r3, [r7, #4]
 8001562:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001564:	430b      	orrs	r3, r1
 8001566:	492b      	ldr	r1, [pc, #172]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 8001568:	4313      	orrs	r3, r2
 800156a:	608b      	str	r3, [r1, #8]
                             RCC_OscInitStruct->PLL.PLLMUL,
                             RCC_OscInitStruct->PLL.PLLDIV);
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 800156c:	4b2a      	ldr	r3, [pc, #168]	; (8001618 <HAL_RCC_OscConfig+0x65c>)
 800156e:	2201      	movs	r2, #1
 8001570:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001572:	f7ff fa6d 	bl	8000a50 <HAL_GetTick>
 8001576:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 8001578:	e008      	b.n	800158c <HAL_RCC_OscConfig+0x5d0>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 800157a:	f7ff fa69 	bl	8000a50 <HAL_GetTick>
 800157e:	4602      	mov	r2, r0
 8001580:	693b      	ldr	r3, [r7, #16]
 8001582:	1ad3      	subs	r3, r2, r3
 8001584:	2b02      	cmp	r3, #2
 8001586:	d901      	bls.n	800158c <HAL_RCC_OscConfig+0x5d0>
          {
            return HAL_TIMEOUT;
 8001588:	2303      	movs	r3, #3
 800158a:	e03e      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 800158c:	4b21      	ldr	r3, [pc, #132]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 800158e:	681b      	ldr	r3, [r3, #0]
 8001590:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001594:	2b00      	cmp	r3, #0
 8001596:	d0f0      	beq.n	800157a <HAL_RCC_OscConfig+0x5be>
 8001598:	e036      	b.n	8001608 <HAL_RCC_OscConfig+0x64c>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 800159a:	4b1f      	ldr	r3, [pc, #124]	; (8001618 <HAL_RCC_OscConfig+0x65c>)
 800159c:	2200      	movs	r2, #0
 800159e:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80015a0:	f7ff fa56 	bl	8000a50 <HAL_GetTick>
 80015a4:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 80015a6:	e008      	b.n	80015ba <HAL_RCC_OscConfig+0x5fe>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 80015a8:	f7ff fa52 	bl	8000a50 <HAL_GetTick>
 80015ac:	4602      	mov	r2, r0
 80015ae:	693b      	ldr	r3, [r7, #16]
 80015b0:	1ad3      	subs	r3, r2, r3
 80015b2:	2b02      	cmp	r3, #2
 80015b4:	d901      	bls.n	80015ba <HAL_RCC_OscConfig+0x5fe>
          {
            return HAL_TIMEOUT;
 80015b6:	2303      	movs	r3, #3
 80015b8:	e027      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
 80015ba:	4b16      	ldr	r3, [pc, #88]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 80015bc:	681b      	ldr	r3, [r3, #0]
 80015be:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80015c2:	2b00      	cmp	r3, #0
 80015c4:	d1f0      	bne.n	80015a8 <HAL_RCC_OscConfig+0x5ec>
 80015c6:	e01f      	b.n	8001608 <HAL_RCC_OscConfig+0x64c>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 80015c8:	687b      	ldr	r3, [r7, #4]
 80015ca:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80015cc:	2b01      	cmp	r3, #1
 80015ce:	d101      	bne.n	80015d4 <HAL_RCC_OscConfig+0x618>
      {
        return HAL_ERROR;
 80015d0:	2301      	movs	r3, #1
 80015d2:	e01a      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->CFGR;
 80015d4:	4b0f      	ldr	r3, [pc, #60]	; (8001614 <HAL_RCC_OscConfig+0x658>)
 80015d6:	689b      	ldr	r3, [r3, #8]
 80015d8:	617b      	str	r3, [r7, #20]
        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 80015da:	697b      	ldr	r3, [r7, #20]
 80015dc:	f403 3280 	and.w	r2, r3, #65536	; 0x10000
 80015e0:	687b      	ldr	r3, [r7, #4]
 80015e2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80015e4:	429a      	cmp	r2, r3
 80015e6:	d10d      	bne.n	8001604 <HAL_RCC_OscConfig+0x648>
           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
 80015e8:	697b      	ldr	r3, [r7, #20]
 80015ea:	f403 1270 	and.w	r2, r3, #3932160	; 0x3c0000
 80015ee:	687b      	ldr	r3, [r7, #4]
 80015f0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
        if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 80015f2:	429a      	cmp	r2, r3
 80015f4:	d106      	bne.n	8001604 <HAL_RCC_OscConfig+0x648>
           (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
 80015f6:	697b      	ldr	r3, [r7, #20]
 80015f8:	f403 0240 	and.w	r2, r3, #12582912	; 0xc00000
 80015fc:	687b      	ldr	r3, [r7, #4]
 80015fe:	6b1b      	ldr	r3, [r3, #48]	; 0x30
           (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
 8001600:	429a      	cmp	r2, r3
 8001602:	d001      	beq.n	8001608 <HAL_RCC_OscConfig+0x64c>
        {
          return HAL_ERROR;
 8001604:	2301      	movs	r3, #1
 8001606:	e000      	b.n	800160a <HAL_RCC_OscConfig+0x64e>
        }
      }
    }
  }

  return HAL_OK;
 8001608:	2300      	movs	r3, #0
}
 800160a:	4618      	mov	r0, r3
 800160c:	3720      	adds	r7, #32
 800160e:	46bd      	mov	sp, r7
 8001610:	bd80      	pop	{r7, pc}
 8001612:	bf00      	nop
 8001614:	40023800 	.word	0x40023800
 8001618:	42470060 	.word	0x42470060

0800161c <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 800161c:	b580      	push	{r7, lr}
 800161e:	b084      	sub	sp, #16
 8001620:	af00      	add	r7, sp, #0
 8001622:	6078      	str	r0, [r7, #4]
 8001624:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;
  HAL_StatusTypeDef status;

  /* Check the parameters */
  if(RCC_ClkInitStruct == NULL)
 8001626:	687b      	ldr	r3, [r7, #4]
 8001628:	2b00      	cmp	r3, #0
 800162a:	d101      	bne.n	8001630 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 800162c:	2301      	movs	r3, #1
 800162e:	e11a      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  must be correctly programmed according to the frequency of the CPU clock
  (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 8001630:	4b8f      	ldr	r3, [pc, #572]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 8001632:	681b      	ldr	r3, [r3, #0]
 8001634:	f003 0301 	and.w	r3, r3, #1
 8001638:	683a      	ldr	r2, [r7, #0]
 800163a:	429a      	cmp	r2, r3
 800163c:	d919      	bls.n	8001672 <HAL_RCC_ClockConfig+0x56>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800163e:	683b      	ldr	r3, [r7, #0]
 8001640:	2b01      	cmp	r3, #1
 8001642:	d105      	bne.n	8001650 <HAL_RCC_ClockConfig+0x34>
 8001644:	4b8a      	ldr	r3, [pc, #552]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 8001646:	681b      	ldr	r3, [r3, #0]
 8001648:	4a89      	ldr	r2, [pc, #548]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 800164a:	f043 0304 	orr.w	r3, r3, #4
 800164e:	6013      	str	r3, [r2, #0]
 8001650:	4b87      	ldr	r3, [pc, #540]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 8001652:	681b      	ldr	r3, [r3, #0]
 8001654:	f023 0201 	bic.w	r2, r3, #1
 8001658:	4985      	ldr	r1, [pc, #532]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 800165a:	683b      	ldr	r3, [r7, #0]
 800165c:	4313      	orrs	r3, r2
 800165e:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 8001660:	4b83      	ldr	r3, [pc, #524]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 8001662:	681b      	ldr	r3, [r3, #0]
 8001664:	f003 0301 	and.w	r3, r3, #1
 8001668:	683a      	ldr	r2, [r7, #0]
 800166a:	429a      	cmp	r2, r3
 800166c:	d001      	beq.n	8001672 <HAL_RCC_ClockConfig+0x56>
    {
      return HAL_ERROR;
 800166e:	2301      	movs	r3, #1
 8001670:	e0f9      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8001672:	687b      	ldr	r3, [r7, #4]
 8001674:	681b      	ldr	r3, [r3, #0]
 8001676:	f003 0302 	and.w	r3, r3, #2
 800167a:	2b00      	cmp	r3, #0
 800167c:	d008      	beq.n	8001690 <HAL_RCC_ClockConfig+0x74>
  {
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 800167e:	4b7d      	ldr	r3, [pc, #500]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001680:	689b      	ldr	r3, [r3, #8]
 8001682:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8001686:	687b      	ldr	r3, [r7, #4]
 8001688:	689b      	ldr	r3, [r3, #8]
 800168a:	497a      	ldr	r1, [pc, #488]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 800168c:	4313      	orrs	r3, r2
 800168e:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8001690:	687b      	ldr	r3, [r7, #4]
 8001692:	681b      	ldr	r3, [r3, #0]
 8001694:	f003 0301 	and.w	r3, r3, #1
 8001698:	2b00      	cmp	r3, #0
 800169a:	f000 808e 	beq.w	80017ba <HAL_RCC_ClockConfig+0x19e>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800169e:	687b      	ldr	r3, [r7, #4]
 80016a0:	685b      	ldr	r3, [r3, #4]
 80016a2:	2b02      	cmp	r3, #2
 80016a4:	d107      	bne.n	80016b6 <HAL_RCC_ClockConfig+0x9a>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
 80016a6:	4b73      	ldr	r3, [pc, #460]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 80016a8:	681b      	ldr	r3, [r3, #0]
 80016aa:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80016ae:	2b00      	cmp	r3, #0
 80016b0:	d121      	bne.n	80016f6 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 80016b2:	2301      	movs	r3, #1
 80016b4:	e0d7      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      }
    }
    /* PLL is selected as System Clock Source */
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 80016b6:	687b      	ldr	r3, [r7, #4]
 80016b8:	685b      	ldr	r3, [r3, #4]
 80016ba:	2b03      	cmp	r3, #3
 80016bc:	d107      	bne.n	80016ce <HAL_RCC_ClockConfig+0xb2>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
 80016be:	4b6d      	ldr	r3, [pc, #436]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 80016c0:	681b      	ldr	r3, [r3, #0]
 80016c2:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80016c6:	2b00      	cmp	r3, #0
 80016c8:	d115      	bne.n	80016f6 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 80016ca:	2301      	movs	r3, #1
 80016cc:	e0cb      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      }
    }
    /* HSI is selected as System Clock Source */
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 80016ce:	687b      	ldr	r3, [r7, #4]
 80016d0:	685b      	ldr	r3, [r3, #4]
 80016d2:	2b01      	cmp	r3, #1
 80016d4:	d107      	bne.n	80016e6 <HAL_RCC_ClockConfig+0xca>
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
 80016d6:	4b67      	ldr	r3, [pc, #412]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 80016d8:	681b      	ldr	r3, [r3, #0]
 80016da:	f003 0302 	and.w	r3, r3, #2
 80016de:	2b00      	cmp	r3, #0
 80016e0:	d109      	bne.n	80016f6 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 80016e2:	2301      	movs	r3, #1
 80016e4:	e0bf      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
    }
    /* MSI is selected as System Clock Source */
    else
    {
      /* Check the MSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
 80016e6:	4b63      	ldr	r3, [pc, #396]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 80016e8:	681b      	ldr	r3, [r3, #0]
 80016ea:	f403 7300 	and.w	r3, r3, #512	; 0x200
 80016ee:	2b00      	cmp	r3, #0
 80016f0:	d101      	bne.n	80016f6 <HAL_RCC_ClockConfig+0xda>
      {
        return HAL_ERROR;
 80016f2:	2301      	movs	r3, #1
 80016f4:	e0b7      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      }
    }
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80016f6:	4b5f      	ldr	r3, [pc, #380]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 80016f8:	689b      	ldr	r3, [r3, #8]
 80016fa:	f023 0203 	bic.w	r2, r3, #3
 80016fe:	687b      	ldr	r3, [r7, #4]
 8001700:	685b      	ldr	r3, [r3, #4]
 8001702:	495c      	ldr	r1, [pc, #368]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001704:	4313      	orrs	r3, r2
 8001706:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8001708:	f7ff f9a2 	bl	8000a50 <HAL_GetTick>
 800170c:	60f8      	str	r0, [r7, #12]

    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800170e:	687b      	ldr	r3, [r7, #4]
 8001710:	685b      	ldr	r3, [r3, #4]
 8001712:	2b02      	cmp	r3, #2
 8001714:	d112      	bne.n	800173c <HAL_RCC_ClockConfig+0x120>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 8001716:	e00a      	b.n	800172e <HAL_RCC_ClockConfig+0x112>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001718:	f7ff f99a 	bl	8000a50 <HAL_GetTick>
 800171c:	4602      	mov	r2, r0
 800171e:	68fb      	ldr	r3, [r7, #12]
 8001720:	1ad3      	subs	r3, r2, r3
 8001722:	f241 3288 	movw	r2, #5000	; 0x1388
 8001726:	4293      	cmp	r3, r2
 8001728:	d901      	bls.n	800172e <HAL_RCC_ClockConfig+0x112>
        {
          return HAL_TIMEOUT;
 800172a:	2303      	movs	r3, #3
 800172c:	e09b      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
 800172e:	4b51      	ldr	r3, [pc, #324]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001730:	689b      	ldr	r3, [r3, #8]
 8001732:	f003 030c 	and.w	r3, r3, #12
 8001736:	2b08      	cmp	r3, #8
 8001738:	d1ee      	bne.n	8001718 <HAL_RCC_ClockConfig+0xfc>
 800173a:	e03e      	b.n	80017ba <HAL_RCC_ClockConfig+0x19e>
        }
      }
    }
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 800173c:	687b      	ldr	r3, [r7, #4]
 800173e:	685b      	ldr	r3, [r3, #4]
 8001740:	2b03      	cmp	r3, #3
 8001742:	d112      	bne.n	800176a <HAL_RCC_ClockConfig+0x14e>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8001744:	e00a      	b.n	800175c <HAL_RCC_ClockConfig+0x140>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001746:	f7ff f983 	bl	8000a50 <HAL_GetTick>
 800174a:	4602      	mov	r2, r0
 800174c:	68fb      	ldr	r3, [r7, #12]
 800174e:	1ad3      	subs	r3, r2, r3
 8001750:	f241 3288 	movw	r2, #5000	; 0x1388
 8001754:	4293      	cmp	r3, r2
 8001756:	d901      	bls.n	800175c <HAL_RCC_ClockConfig+0x140>
        {
          return HAL_TIMEOUT;
 8001758:	2303      	movs	r3, #3
 800175a:	e084      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 800175c:	4b45      	ldr	r3, [pc, #276]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 800175e:	689b      	ldr	r3, [r3, #8]
 8001760:	f003 030c 	and.w	r3, r3, #12
 8001764:	2b0c      	cmp	r3, #12
 8001766:	d1ee      	bne.n	8001746 <HAL_RCC_ClockConfig+0x12a>
 8001768:	e027      	b.n	80017ba <HAL_RCC_ClockConfig+0x19e>
        }
      }
    }
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
 800176a:	687b      	ldr	r3, [r7, #4]
 800176c:	685b      	ldr	r3, [r3, #4]
 800176e:	2b01      	cmp	r3, #1
 8001770:	d11d      	bne.n	80017ae <HAL_RCC_ClockConfig+0x192>
    {
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 8001772:	e00a      	b.n	800178a <HAL_RCC_ClockConfig+0x16e>
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001774:	f7ff f96c 	bl	8000a50 <HAL_GetTick>
 8001778:	4602      	mov	r2, r0
 800177a:	68fb      	ldr	r3, [r7, #12]
 800177c:	1ad3      	subs	r3, r2, r3
 800177e:	f241 3288 	movw	r2, #5000	; 0x1388
 8001782:	4293      	cmp	r3, r2
 8001784:	d901      	bls.n	800178a <HAL_RCC_ClockConfig+0x16e>
        {
          return HAL_TIMEOUT;
 8001786:	2303      	movs	r3, #3
 8001788:	e06d      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
 800178a:	4b3a      	ldr	r3, [pc, #232]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 800178c:	689b      	ldr	r3, [r3, #8]
 800178e:	f003 030c 	and.w	r3, r3, #12
 8001792:	2b04      	cmp	r3, #4
 8001794:	d1ee      	bne.n	8001774 <HAL_RCC_ClockConfig+0x158>
 8001796:	e010      	b.n	80017ba <HAL_RCC_ClockConfig+0x19e>
    }
    else
    {
      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
      {
        if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 8001798:	f7ff f95a 	bl	8000a50 <HAL_GetTick>
 800179c:	4602      	mov	r2, r0
 800179e:	68fb      	ldr	r3, [r7, #12]
 80017a0:	1ad3      	subs	r3, r2, r3
 80017a2:	f241 3288 	movw	r2, #5000	; 0x1388
 80017a6:	4293      	cmp	r3, r2
 80017a8:	d901      	bls.n	80017ae <HAL_RCC_ClockConfig+0x192>
        {
          return HAL_TIMEOUT;
 80017aa:	2303      	movs	r3, #3
 80017ac:	e05b      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
      while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
 80017ae:	4b31      	ldr	r3, [pc, #196]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 80017b0:	689b      	ldr	r3, [r3, #8]
 80017b2:	f003 030c 	and.w	r3, r3, #12
 80017b6:	2b00      	cmp	r3, #0
 80017b8:	d1ee      	bne.n	8001798 <HAL_RCC_ClockConfig+0x17c>
        }
      }
    }
  }
  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 80017ba:	4b2d      	ldr	r3, [pc, #180]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 80017bc:	681b      	ldr	r3, [r3, #0]
 80017be:	f003 0301 	and.w	r3, r3, #1
 80017c2:	683a      	ldr	r2, [r7, #0]
 80017c4:	429a      	cmp	r2, r3
 80017c6:	d219      	bcs.n	80017fc <HAL_RCC_ClockConfig+0x1e0>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 80017c8:	683b      	ldr	r3, [r7, #0]
 80017ca:	2b01      	cmp	r3, #1
 80017cc:	d105      	bne.n	80017da <HAL_RCC_ClockConfig+0x1be>
 80017ce:	4b28      	ldr	r3, [pc, #160]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 80017d0:	681b      	ldr	r3, [r3, #0]
 80017d2:	4a27      	ldr	r2, [pc, #156]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 80017d4:	f043 0304 	orr.w	r3, r3, #4
 80017d8:	6013      	str	r3, [r2, #0]
 80017da:	4b25      	ldr	r3, [pc, #148]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 80017dc:	681b      	ldr	r3, [r3, #0]
 80017de:	f023 0201 	bic.w	r2, r3, #1
 80017e2:	4923      	ldr	r1, [pc, #140]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 80017e4:	683b      	ldr	r3, [r7, #0]
 80017e6:	4313      	orrs	r3, r2
 80017e8:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 80017ea:	4b21      	ldr	r3, [pc, #132]	; (8001870 <HAL_RCC_ClockConfig+0x254>)
 80017ec:	681b      	ldr	r3, [r3, #0]
 80017ee:	f003 0301 	and.w	r3, r3, #1
 80017f2:	683a      	ldr	r2, [r7, #0]
 80017f4:	429a      	cmp	r2, r3
 80017f6:	d001      	beq.n	80017fc <HAL_RCC_ClockConfig+0x1e0>
    {
      return HAL_ERROR;
 80017f8:	2301      	movs	r3, #1
 80017fa:	e034      	b.n	8001866 <HAL_RCC_ClockConfig+0x24a>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80017fc:	687b      	ldr	r3, [r7, #4]
 80017fe:	681b      	ldr	r3, [r3, #0]
 8001800:	f003 0304 	and.w	r3, r3, #4
 8001804:	2b00      	cmp	r3, #0
 8001806:	d008      	beq.n	800181a <HAL_RCC_ClockConfig+0x1fe>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8001808:	4b1a      	ldr	r3, [pc, #104]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 800180a:	689b      	ldr	r3, [r3, #8]
 800180c:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
 8001810:	687b      	ldr	r3, [r7, #4]
 8001812:	68db      	ldr	r3, [r3, #12]
 8001814:	4917      	ldr	r1, [pc, #92]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001816:	4313      	orrs	r3, r2
 8001818:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 800181a:	687b      	ldr	r3, [r7, #4]
 800181c:	681b      	ldr	r3, [r3, #0]
 800181e:	f003 0308 	and.w	r3, r3, #8
 8001822:	2b00      	cmp	r3, #0
 8001824:	d009      	beq.n	800183a <HAL_RCC_ClockConfig+0x21e>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 8001826:	4b13      	ldr	r3, [pc, #76]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001828:	689b      	ldr	r3, [r3, #8]
 800182a:	f423 5260 	bic.w	r2, r3, #14336	; 0x3800
 800182e:	687b      	ldr	r3, [r7, #4]
 8001830:	691b      	ldr	r3, [r3, #16]
 8001832:	00db      	lsls	r3, r3, #3
 8001834:	490f      	ldr	r1, [pc, #60]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001836:	4313      	orrs	r3, r2
 8001838:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 800183a:	f000 f823 	bl	8001884 <HAL_RCC_GetSysClockFreq>
 800183e:	4601      	mov	r1, r0
 8001840:	4b0c      	ldr	r3, [pc, #48]	; (8001874 <HAL_RCC_ClockConfig+0x258>)
 8001842:	689b      	ldr	r3, [r3, #8]
 8001844:	091b      	lsrs	r3, r3, #4
 8001846:	f003 030f 	and.w	r3, r3, #15
 800184a:	4a0b      	ldr	r2, [pc, #44]	; (8001878 <HAL_RCC_ClockConfig+0x25c>)
 800184c:	5cd3      	ldrb	r3, [r2, r3]
 800184e:	fa21 f303 	lsr.w	r3, r1, r3
 8001852:	4a0a      	ldr	r2, [pc, #40]	; (800187c <HAL_RCC_ClockConfig+0x260>)
 8001854:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  status = HAL_InitTick(uwTickPrio);
 8001856:	4b0a      	ldr	r3, [pc, #40]	; (8001880 <HAL_RCC_ClockConfig+0x264>)
 8001858:	681b      	ldr	r3, [r3, #0]
 800185a:	4618      	mov	r0, r3
 800185c:	f7ff f8ac 	bl	80009b8 <HAL_InitTick>
 8001860:	4603      	mov	r3, r0
 8001862:	72fb      	strb	r3, [r7, #11]

  return status;
 8001864:	7afb      	ldrb	r3, [r7, #11]
}
 8001866:	4618      	mov	r0, r3
 8001868:	3710      	adds	r7, #16
 800186a:	46bd      	mov	sp, r7
 800186c:	bd80      	pop	{r7, pc}
 800186e:	bf00      	nop
 8001870:	40023c00 	.word	0x40023c00
 8001874:	40023800 	.word	0x40023800
 8001878:	080025f0 	.word	0x080025f0
 800187c:	20000000 	.word	0x20000000
 8001880:	20000004 	.word	0x20000004

08001884 <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8001884:	b5f0      	push	{r4, r5, r6, r7, lr}
 8001886:	b087      	sub	sp, #28
 8001888:	af00      	add	r7, sp, #0
  uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;

  tmpreg = RCC->CFGR;
 800188a:	4b5f      	ldr	r3, [pc, #380]	; (8001a08 <HAL_RCC_GetSysClockFreq+0x184>)
 800188c:	689b      	ldr	r3, [r3, #8]
 800188e:	60fb      	str	r3, [r7, #12]

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8001890:	68fb      	ldr	r3, [r7, #12]
 8001892:	f003 030c 	and.w	r3, r3, #12
 8001896:	2b08      	cmp	r3, #8
 8001898:	d007      	beq.n	80018aa <HAL_RCC_GetSysClockFreq+0x26>
 800189a:	2b0c      	cmp	r3, #12
 800189c:	d008      	beq.n	80018b0 <HAL_RCC_GetSysClockFreq+0x2c>
 800189e:	2b04      	cmp	r3, #4
 80018a0:	f040 809f 	bne.w	80019e2 <HAL_RCC_GetSysClockFreq+0x15e>
  {
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 80018a4:	4b59      	ldr	r3, [pc, #356]	; (8001a0c <HAL_RCC_GetSysClockFreq+0x188>)
 80018a6:	613b      	str	r3, [r7, #16]
      break;
 80018a8:	e0a9      	b.n	80019fe <HAL_RCC_GetSysClockFreq+0x17a>
    }
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
    {
      sysclockfreq = HSE_VALUE;
 80018aa:	4b59      	ldr	r3, [pc, #356]	; (8001a10 <HAL_RCC_GetSysClockFreq+0x18c>)
 80018ac:	613b      	str	r3, [r7, #16]
      break;
 80018ae:	e0a6      	b.n	80019fe <HAL_RCC_GetSysClockFreq+0x17a>
    }
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
    {
      pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
 80018b0:	68fb      	ldr	r3, [r7, #12]
 80018b2:	0c9b      	lsrs	r3, r3, #18
 80018b4:	f003 030f 	and.w	r3, r3, #15
 80018b8:	4a56      	ldr	r2, [pc, #344]	; (8001a14 <HAL_RCC_GetSysClockFreq+0x190>)
 80018ba:	5cd3      	ldrb	r3, [r2, r3]
 80018bc:	60bb      	str	r3, [r7, #8]
      plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
 80018be:	68fb      	ldr	r3, [r7, #12]
 80018c0:	0d9b      	lsrs	r3, r3, #22
 80018c2:	f003 0303 	and.w	r3, r3, #3
 80018c6:	3301      	adds	r3, #1
 80018c8:	607b      	str	r3, [r7, #4]
      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 80018ca:	4b4f      	ldr	r3, [pc, #316]	; (8001a08 <HAL_RCC_GetSysClockFreq+0x184>)
 80018cc:	689b      	ldr	r3, [r3, #8]
 80018ce:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 80018d2:	2b00      	cmp	r3, #0
 80018d4:	d041      	beq.n	800195a <HAL_RCC_GetSysClockFreq+0xd6>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
 80018d6:	68bb      	ldr	r3, [r7, #8]
 80018d8:	461d      	mov	r5, r3
 80018da:	f04f 0600 	mov.w	r6, #0
 80018de:	4629      	mov	r1, r5
 80018e0:	4632      	mov	r2, r6
 80018e2:	f04f 0300 	mov.w	r3, #0
 80018e6:	f04f 0400 	mov.w	r4, #0
 80018ea:	0154      	lsls	r4, r2, #5
 80018ec:	ea44 64d1 	orr.w	r4, r4, r1, lsr #27
 80018f0:	014b      	lsls	r3, r1, #5
 80018f2:	4619      	mov	r1, r3
 80018f4:	4622      	mov	r2, r4
 80018f6:	1b49      	subs	r1, r1, r5
 80018f8:	eb62 0206 	sbc.w	r2, r2, r6
 80018fc:	f04f 0300 	mov.w	r3, #0
 8001900:	f04f 0400 	mov.w	r4, #0
 8001904:	0194      	lsls	r4, r2, #6
 8001906:	ea44 6491 	orr.w	r4, r4, r1, lsr #26
 800190a:	018b      	lsls	r3, r1, #6
 800190c:	1a5b      	subs	r3, r3, r1
 800190e:	eb64 0402 	sbc.w	r4, r4, r2
 8001912:	f04f 0100 	mov.w	r1, #0
 8001916:	f04f 0200 	mov.w	r2, #0
 800191a:	00e2      	lsls	r2, r4, #3
 800191c:	ea42 7253 	orr.w	r2, r2, r3, lsr #29
 8001920:	00d9      	lsls	r1, r3, #3
 8001922:	460b      	mov	r3, r1
 8001924:	4614      	mov	r4, r2
 8001926:	195b      	adds	r3, r3, r5
 8001928:	eb44 0406 	adc.w	r4, r4, r6
 800192c:	f04f 0100 	mov.w	r1, #0
 8001930:	f04f 0200 	mov.w	r2, #0
 8001934:	0262      	lsls	r2, r4, #9
 8001936:	ea42 52d3 	orr.w	r2, r2, r3, lsr #23
 800193a:	0259      	lsls	r1, r3, #9
 800193c:	460b      	mov	r3, r1
 800193e:	4614      	mov	r4, r2
 8001940:	4618      	mov	r0, r3
 8001942:	4621      	mov	r1, r4
 8001944:	687b      	ldr	r3, [r7, #4]
 8001946:	f04f 0400 	mov.w	r4, #0
 800194a:	461a      	mov	r2, r3
 800194c:	4623      	mov	r3, r4
 800194e:	f7fe fc15 	bl	800017c <__aeabi_uldivmod>
 8001952:	4603      	mov	r3, r0
 8001954:	460c      	mov	r4, r1
 8001956:	617b      	str	r3, [r7, #20]
 8001958:	e040      	b.n	80019dc <HAL_RCC_GetSysClockFreq+0x158>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
 800195a:	68bb      	ldr	r3, [r7, #8]
 800195c:	461d      	mov	r5, r3
 800195e:	f04f 0600 	mov.w	r6, #0
 8001962:	4629      	mov	r1, r5
 8001964:	4632      	mov	r2, r6
 8001966:	f04f 0300 	mov.w	r3, #0
 800196a:	f04f 0400 	mov.w	r4, #0
 800196e:	0154      	lsls	r4, r2, #5
 8001970:	ea44 64d1 	orr.w	r4, r4, r1, lsr #27
 8001974:	014b      	lsls	r3, r1, #5
 8001976:	4619      	mov	r1, r3
 8001978:	4622      	mov	r2, r4
 800197a:	1b49      	subs	r1, r1, r5
 800197c:	eb62 0206 	sbc.w	r2, r2, r6
 8001980:	f04f 0300 	mov.w	r3, #0
 8001984:	f04f 0400 	mov.w	r4, #0
 8001988:	0194      	lsls	r4, r2, #6
 800198a:	ea44 6491 	orr.w	r4, r4, r1, lsr #26
 800198e:	018b      	lsls	r3, r1, #6
 8001990:	1a5b      	subs	r3, r3, r1
 8001992:	eb64 0402 	sbc.w	r4, r4, r2
 8001996:	f04f 0100 	mov.w	r1, #0
 800199a:	f04f 0200 	mov.w	r2, #0
 800199e:	00e2      	lsls	r2, r4, #3
 80019a0:	ea42 7253 	orr.w	r2, r2, r3, lsr #29
 80019a4:	00d9      	lsls	r1, r3, #3
 80019a6:	460b      	mov	r3, r1
 80019a8:	4614      	mov	r4, r2
 80019aa:	195b      	adds	r3, r3, r5
 80019ac:	eb44 0406 	adc.w	r4, r4, r6
 80019b0:	f04f 0100 	mov.w	r1, #0
 80019b4:	f04f 0200 	mov.w	r2, #0
 80019b8:	02a2      	lsls	r2, r4, #10
 80019ba:	ea42 5293 	orr.w	r2, r2, r3, lsr #22
 80019be:	0299      	lsls	r1, r3, #10
 80019c0:	460b      	mov	r3, r1
 80019c2:	4614      	mov	r4, r2
 80019c4:	4618      	mov	r0, r3
 80019c6:	4621      	mov	r1, r4
 80019c8:	687b      	ldr	r3, [r7, #4]
 80019ca:	f04f 0400 	mov.w	r4, #0
 80019ce:	461a      	mov	r2, r3
 80019d0:	4623      	mov	r3, r4
 80019d2:	f7fe fbd3 	bl	800017c <__aeabi_uldivmod>
 80019d6:	4603      	mov	r3, r0
 80019d8:	460c      	mov	r4, r1
 80019da:	617b      	str	r3, [r7, #20]
      }
      sysclockfreq = pllvco;
 80019dc:	697b      	ldr	r3, [r7, #20]
 80019de:	613b      	str	r3, [r7, #16]
      break;
 80019e0:	e00d      	b.n	80019fe <HAL_RCC_GetSysClockFreq+0x17a>
    }
    case RCC_SYSCLKSOURCE_STATUS_MSI:  /* MSI used as system clock source */
    default: /* MSI used as system clock */
    {
      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
 80019e2:	4b09      	ldr	r3, [pc, #36]	; (8001a08 <HAL_RCC_GetSysClockFreq+0x184>)
 80019e4:	685b      	ldr	r3, [r3, #4]
 80019e6:	0b5b      	lsrs	r3, r3, #13
 80019e8:	f003 0307 	and.w	r3, r3, #7
 80019ec:	603b      	str	r3, [r7, #0]
      sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
 80019ee:	683b      	ldr	r3, [r7, #0]
 80019f0:	3301      	adds	r3, #1
 80019f2:	f44f 4200 	mov.w	r2, #32768	; 0x8000
 80019f6:	fa02 f303 	lsl.w	r3, r2, r3
 80019fa:	613b      	str	r3, [r7, #16]
      break;
 80019fc:	bf00      	nop
    }
  }
  return sysclockfreq;
 80019fe:	693b      	ldr	r3, [r7, #16]
}
 8001a00:	4618      	mov	r0, r3
 8001a02:	371c      	adds	r7, #28
 8001a04:	46bd      	mov	sp, r7
 8001a06:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8001a08:	40023800 	.word	0x40023800
 8001a0c:	00f42400 	.word	0x00f42400
 8001a10:	007a1200 	.word	0x007a1200
 8001a14:	080025e4 	.word	0x080025e4

08001a18 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8001a18:	b480      	push	{r7}
 8001a1a:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8001a1c:	4b02      	ldr	r3, [pc, #8]	; (8001a28 <HAL_RCC_GetHCLKFreq+0x10>)
 8001a1e:	681b      	ldr	r3, [r3, #0]
}
 8001a20:	4618      	mov	r0, r3
 8001a22:	46bd      	mov	sp, r7
 8001a24:	bc80      	pop	{r7}
 8001a26:	4770      	bx	lr
 8001a28:	20000000 	.word	0x20000000

08001a2c <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8001a2c:	b580      	push	{r7, lr}
 8001a2e:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 8001a30:	f7ff fff2 	bl	8001a18 <HAL_RCC_GetHCLKFreq>
 8001a34:	4601      	mov	r1, r0
 8001a36:	4b05      	ldr	r3, [pc, #20]	; (8001a4c <HAL_RCC_GetPCLK1Freq+0x20>)
 8001a38:	689b      	ldr	r3, [r3, #8]
 8001a3a:	0a1b      	lsrs	r3, r3, #8
 8001a3c:	f003 0307 	and.w	r3, r3, #7
 8001a40:	4a03      	ldr	r2, [pc, #12]	; (8001a50 <HAL_RCC_GetPCLK1Freq+0x24>)
 8001a42:	5cd3      	ldrb	r3, [r2, r3]
 8001a44:	fa21 f303 	lsr.w	r3, r1, r3
}
 8001a48:	4618      	mov	r0, r3
 8001a4a:	bd80      	pop	{r7, pc}
 8001a4c:	40023800 	.word	0x40023800
 8001a50:	08002600 	.word	0x08002600

08001a54 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 8001a54:	b580      	push	{r7, lr}
 8001a56:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
 8001a58:	f7ff ffde 	bl	8001a18 <HAL_RCC_GetHCLKFreq>
 8001a5c:	4601      	mov	r1, r0
 8001a5e:	4b05      	ldr	r3, [pc, #20]	; (8001a74 <HAL_RCC_GetPCLK2Freq+0x20>)
 8001a60:	689b      	ldr	r3, [r3, #8]
 8001a62:	0adb      	lsrs	r3, r3, #11
 8001a64:	f003 0307 	and.w	r3, r3, #7
 8001a68:	4a03      	ldr	r2, [pc, #12]	; (8001a78 <HAL_RCC_GetPCLK2Freq+0x24>)
 8001a6a:	5cd3      	ldrb	r3, [r2, r3]
 8001a6c:	fa21 f303 	lsr.w	r3, r1, r3
}
 8001a70:	4618      	mov	r0, r3
 8001a72:	bd80      	pop	{r7, pc}
 8001a74:	40023800 	.word	0x40023800
 8001a78:	08002600 	.word	0x08002600

08001a7c <RCC_SetFlashLatencyFromMSIRange>:
            voltage range
  * @param  MSIrange  MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
  * @retval HAL status
  */
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
{
 8001a7c:	b480      	push	{r7}
 8001a7e:	b087      	sub	sp, #28
 8001a80:	af00      	add	r7, sp, #0
 8001a82:	6078      	str	r0, [r7, #4]
  uint32_t vos;
  uint32_t latency = FLASH_LATENCY_0;  /* default value 0WS */
 8001a84:	2300      	movs	r3, #0
 8001a86:	613b      	str	r3, [r7, #16]

  /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
  if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
 8001a88:	4b29      	ldr	r3, [pc, #164]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001a8a:	689b      	ldr	r3, [r3, #8]
 8001a8c:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8001a90:	2b00      	cmp	r3, #0
 8001a92:	d12c      	bne.n	8001aee <RCC_SetFlashLatencyFromMSIRange+0x72>
  {
    if(__HAL_RCC_PWR_IS_CLK_ENABLED())
 8001a94:	4b26      	ldr	r3, [pc, #152]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001a96:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001a98:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001a9c:	2b00      	cmp	r3, #0
 8001a9e:	d005      	beq.n	8001aac <RCC_SetFlashLatencyFromMSIRange+0x30>
    {
      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
 8001aa0:	4b24      	ldr	r3, [pc, #144]	; (8001b34 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8001aa2:	681b      	ldr	r3, [r3, #0]
 8001aa4:	f403 53c0 	and.w	r3, r3, #6144	; 0x1800
 8001aa8:	617b      	str	r3, [r7, #20]
 8001aaa:	e016      	b.n	8001ada <RCC_SetFlashLatencyFromMSIRange+0x5e>
    }
    else
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8001aac:	4b20      	ldr	r3, [pc, #128]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001aae:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001ab0:	4a1f      	ldr	r2, [pc, #124]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001ab2:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001ab6:	6253      	str	r3, [r2, #36]	; 0x24
 8001ab8:	4b1d      	ldr	r3, [pc, #116]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001aba:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001abc:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001ac0:	60fb      	str	r3, [r7, #12]
 8001ac2:	68fb      	ldr	r3, [r7, #12]
      vos = READ_BIT(PWR->CR, PWR_CR_VOS);
 8001ac4:	4b1b      	ldr	r3, [pc, #108]	; (8001b34 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
 8001ac6:	681b      	ldr	r3, [r3, #0]
 8001ac8:	f403 53c0 	and.w	r3, r3, #6144	; 0x1800
 8001acc:	617b      	str	r3, [r7, #20]
      __HAL_RCC_PWR_CLK_DISABLE();
 8001ace:	4b18      	ldr	r3, [pc, #96]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001ad0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001ad2:	4a17      	ldr	r2, [pc, #92]	; (8001b30 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
 8001ad4:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8001ad8:	6253      	str	r3, [r2, #36]	; 0x24
    }

    /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
    if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
 8001ada:	697b      	ldr	r3, [r7, #20]
 8001adc:	f5b3 5fc0 	cmp.w	r3, #6144	; 0x1800
 8001ae0:	d105      	bne.n	8001aee <RCC_SetFlashLatencyFromMSIRange+0x72>
 8001ae2:	687b      	ldr	r3, [r7, #4]
 8001ae4:	f5b3 4f40 	cmp.w	r3, #49152	; 0xc000
 8001ae8:	d101      	bne.n	8001aee <RCC_SetFlashLatencyFromMSIRange+0x72>
    {
      latency = FLASH_LATENCY_1; /* 1WS */
 8001aea:	2301      	movs	r3, #1
 8001aec:	613b      	str	r3, [r7, #16]
    }
  }

  __HAL_FLASH_SET_LATENCY(latency);
 8001aee:	693b      	ldr	r3, [r7, #16]
 8001af0:	2b01      	cmp	r3, #1
 8001af2:	d105      	bne.n	8001b00 <RCC_SetFlashLatencyFromMSIRange+0x84>
 8001af4:	4b10      	ldr	r3, [pc, #64]	; (8001b38 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8001af6:	681b      	ldr	r3, [r3, #0]
 8001af8:	4a0f      	ldr	r2, [pc, #60]	; (8001b38 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8001afa:	f043 0304 	orr.w	r3, r3, #4
 8001afe:	6013      	str	r3, [r2, #0]
 8001b00:	4b0d      	ldr	r3, [pc, #52]	; (8001b38 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8001b02:	681b      	ldr	r3, [r3, #0]
 8001b04:	f023 0201 	bic.w	r2, r3, #1
 8001b08:	490b      	ldr	r1, [pc, #44]	; (8001b38 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8001b0a:	693b      	ldr	r3, [r7, #16]
 8001b0c:	4313      	orrs	r3, r2
 8001b0e:	600b      	str	r3, [r1, #0]

  /* Check that the new number of wait states is taken into account to access the Flash
     memory by reading the FLASH_ACR register */
  if(__HAL_FLASH_GET_LATENCY() != latency)
 8001b10:	4b09      	ldr	r3, [pc, #36]	; (8001b38 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
 8001b12:	681b      	ldr	r3, [r3, #0]
 8001b14:	f003 0301 	and.w	r3, r3, #1
 8001b18:	693a      	ldr	r2, [r7, #16]
 8001b1a:	429a      	cmp	r2, r3
 8001b1c:	d001      	beq.n	8001b22 <RCC_SetFlashLatencyFromMSIRange+0xa6>
  {
    return HAL_ERROR;
 8001b1e:	2301      	movs	r3, #1
 8001b20:	e000      	b.n	8001b24 <RCC_SetFlashLatencyFromMSIRange+0xa8>
  }

  return HAL_OK;
 8001b22:	2300      	movs	r3, #0
}
 8001b24:	4618      	mov	r0, r3
 8001b26:	371c      	adds	r7, #28
 8001b28:	46bd      	mov	sp, r7
 8001b2a:	bc80      	pop	{r7}
 8001b2c:	4770      	bx	lr
 8001b2e:	bf00      	nop
 8001b30:	40023800 	.word	0x40023800
 8001b34:	40007000 	.word	0x40007000
 8001b38:	40023c00 	.word	0x40023c00

08001b3c <HAL_RCCEx_PeriphCLKConfig>:
  * @retval HAL status
  * @note   If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig()
  *         to possibly update HSE divider.
  */
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
{
 8001b3c:	b580      	push	{r7, lr}
 8001b3e:	b086      	sub	sp, #24
 8001b40:	af00      	add	r7, sp, #0
 8001b42:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));

  /*------------------------------- RTC/LCD Configuration ------------------------*/
  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
 8001b44:	687b      	ldr	r3, [r7, #4]
 8001b46:	681b      	ldr	r3, [r3, #0]
 8001b48:	f003 0301 	and.w	r3, r3, #1
 8001b4c:	2b00      	cmp	r3, #0
 8001b4e:	d106      	bne.n	8001b5e <HAL_RCCEx_PeriphCLKConfig+0x22>
#if defined(LCD)
   || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
 8001b50:	687b      	ldr	r3, [r7, #4]
 8001b52:	681b      	ldr	r3, [r3, #0]
 8001b54:	f003 0302 	and.w	r3, r3, #2
 8001b58:	2b00      	cmp	r3, #0
 8001b5a:	f000 80c6 	beq.w	8001cea <HAL_RCCEx_PeriphCLKConfig+0x1ae>
    {
      assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection));
    }
#endif /* LCD */

    FlagStatus       pwrclkchanged = RESET;
 8001b5e:	2300      	movs	r3, #0
 8001b60:	75fb      	strb	r3, [r7, #23]

    /* As soon as function is called to change RTC clock source, activation of the
       power domain is done. */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8001b62:	4b64      	ldr	r3, [pc, #400]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001b64:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001b66:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001b6a:	2b00      	cmp	r3, #0
 8001b6c:	d10d      	bne.n	8001b8a <HAL_RCCEx_PeriphCLKConfig+0x4e>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8001b6e:	4b61      	ldr	r3, [pc, #388]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001b70:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001b72:	4a60      	ldr	r2, [pc, #384]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001b74:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001b78:	6253      	str	r3, [r2, #36]	; 0x24
 8001b7a:	4b5e      	ldr	r3, [pc, #376]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001b7c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001b7e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001b82:	60bb      	str	r3, [r7, #8]
 8001b84:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 8001b86:	2301      	movs	r3, #1
 8001b88:	75fb      	strb	r3, [r7, #23]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001b8a:	4b5b      	ldr	r3, [pc, #364]	; (8001cf8 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
 8001b8c:	681b      	ldr	r3, [r3, #0]
 8001b8e:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001b92:	2b00      	cmp	r3, #0
 8001b94:	d118      	bne.n	8001bc8 <HAL_RCCEx_PeriphCLKConfig+0x8c>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8001b96:	4b58      	ldr	r3, [pc, #352]	; (8001cf8 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
 8001b98:	681b      	ldr	r3, [r3, #0]
 8001b9a:	4a57      	ldr	r2, [pc, #348]	; (8001cf8 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
 8001b9c:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001ba0:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8001ba2:	f7fe ff55 	bl	8000a50 <HAL_GetTick>
 8001ba6:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001ba8:	e008      	b.n	8001bbc <HAL_RCCEx_PeriphCLKConfig+0x80>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8001baa:	f7fe ff51 	bl	8000a50 <HAL_GetTick>
 8001bae:	4602      	mov	r2, r0
 8001bb0:	693b      	ldr	r3, [r7, #16]
 8001bb2:	1ad3      	subs	r3, r2, r3
 8001bb4:	2b64      	cmp	r3, #100	; 0x64
 8001bb6:	d901      	bls.n	8001bbc <HAL_RCCEx_PeriphCLKConfig+0x80>
        {
          return HAL_TIMEOUT;
 8001bb8:	2303      	movs	r3, #3
 8001bba:	e097      	b.n	8001cec <HAL_RCCEx_PeriphCLKConfig+0x1b0>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001bbc:	4b4e      	ldr	r3, [pc, #312]	; (8001cf8 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
 8001bbe:	681b      	ldr	r3, [r3, #0]
 8001bc0:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001bc4:	2b00      	cmp	r3, #0
 8001bc6:	d0f0      	beq.n	8001baa <HAL_RCCEx_PeriphCLKConfig+0x6e>
        }
      }
    }

    /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */
    temp_reg = (RCC->CR & RCC_CR_RTCPRE);
 8001bc8:	4b4a      	ldr	r3, [pc, #296]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001bca:	681b      	ldr	r3, [r3, #0]
 8001bcc:	f003 43c0 	and.w	r3, r3, #1610612736	; 0x60000000
 8001bd0:	60fb      	str	r3, [r7, #12]
    if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE))
 8001bd2:	687b      	ldr	r3, [r7, #4]
 8001bd4:	685b      	ldr	r3, [r3, #4]
 8001bd6:	f003 43c0 	and.w	r3, r3, #1610612736	; 0x60000000
 8001bda:	68fa      	ldr	r2, [r7, #12]
 8001bdc:	429a      	cmp	r2, r3
 8001bde:	d106      	bne.n	8001bee <HAL_RCCEx_PeriphCLKConfig+0xb2>
#if defined (LCD)
     || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE))
 8001be0:	687b      	ldr	r3, [r7, #4]
 8001be2:	689b      	ldr	r3, [r3, #8]
 8001be4:	f003 43c0 	and.w	r3, r3, #1610612736	; 0x60000000
 8001be8:	68fa      	ldr	r2, [r7, #12]
 8001bea:	429a      	cmp	r2, r3
 8001bec:	d00f      	beq.n	8001c0e <HAL_RCCEx_PeriphCLKConfig+0xd2>
#endif /* LCD */
       )
    { /* Check HSE State */
      if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE)
 8001bee:	687b      	ldr	r3, [r7, #4]
 8001bf0:	685b      	ldr	r3, [r3, #4]
 8001bf2:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001bf6:	f5b3 3f40 	cmp.w	r3, #196608	; 0x30000
 8001bfa:	d108      	bne.n	8001c0e <HAL_RCCEx_PeriphCLKConfig+0xd2>
      {
        if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY))
 8001bfc:	4b3d      	ldr	r3, [pc, #244]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001bfe:	681b      	ldr	r3, [r3, #0]
 8001c00:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001c04:	f5b3 3f00 	cmp.w	r3, #131072	; 0x20000
 8001c08:	d101      	bne.n	8001c0e <HAL_RCCEx_PeriphCLKConfig+0xd2>
        {
          /* To update HSE divider, first switch-OFF HSE clock oscillator*/
          return HAL_ERROR;
 8001c0a:	2301      	movs	r3, #1
 8001c0c:	e06e      	b.n	8001cec <HAL_RCCEx_PeriphCLKConfig+0x1b0>
        }
      }
    }

    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
    temp_reg = (RCC->CSR & RCC_CSR_RTCSEL);
 8001c0e:	4b39      	ldr	r3, [pc, #228]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001c10:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001c12:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001c16:	60fb      	str	r3, [r7, #12]

    if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \
 8001c18:	68fb      	ldr	r3, [r7, #12]
 8001c1a:	2b00      	cmp	r3, #0
 8001c1c:	d041      	beq.n	8001ca2 <HAL_RCCEx_PeriphCLKConfig+0x166>
 8001c1e:	687b      	ldr	r3, [r7, #4]
 8001c20:	685b      	ldr	r3, [r3, #4]
 8001c22:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001c26:	68fa      	ldr	r2, [r7, #12]
 8001c28:	429a      	cmp	r2, r3
 8001c2a:	d005      	beq.n	8001c38 <HAL_RCCEx_PeriphCLKConfig+0xfc>
      && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
 8001c2c:	687b      	ldr	r3, [r7, #4]
 8001c2e:	681b      	ldr	r3, [r3, #0]
 8001c30:	f003 0301 	and.w	r3, r3, #1
 8001c34:	2b00      	cmp	r3, #0
 8001c36:	d10c      	bne.n	8001c52 <HAL_RCCEx_PeriphCLKConfig+0x116>
#if defined(LCD)
      || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \
 8001c38:	687b      	ldr	r3, [r7, #4]
 8001c3a:	689b      	ldr	r3, [r3, #8]
 8001c3c:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001c40:	68fa      	ldr	r2, [r7, #12]
 8001c42:	429a      	cmp	r2, r3
 8001c44:	d02d      	beq.n	8001ca2 <HAL_RCCEx_PeriphCLKConfig+0x166>
       && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD))
 8001c46:	687b      	ldr	r3, [r7, #4]
 8001c48:	681b      	ldr	r3, [r3, #0]
 8001c4a:	f003 0302 	and.w	r3, r3, #2
 8001c4e:	2b00      	cmp	r3, #0
 8001c50:	d027      	beq.n	8001ca2 <HAL_RCCEx_PeriphCLKConfig+0x166>
#endif /* LCD */
     ))
    {
      /* Store the content of CSR register before the reset of Backup Domain */
      temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
 8001c52:	4b28      	ldr	r3, [pc, #160]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001c54:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001c56:	f423 3340 	bic.w	r3, r3, #196608	; 0x30000
 8001c5a:	60fb      	str	r3, [r7, #12]

      /* RTC Clock selection can be changed only if the Backup Domain is reset */
      __HAL_RCC_BACKUPRESET_FORCE();
 8001c5c:	4b27      	ldr	r3, [pc, #156]	; (8001cfc <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
 8001c5e:	2201      	movs	r2, #1
 8001c60:	601a      	str	r2, [r3, #0]
      __HAL_RCC_BACKUPRESET_RELEASE();
 8001c62:	4b26      	ldr	r3, [pc, #152]	; (8001cfc <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
 8001c64:	2200      	movs	r2, #0
 8001c66:	601a      	str	r2, [r3, #0]

      /* Restore the Content of CSR register */
      RCC->CSR = temp_reg;
 8001c68:	4a22      	ldr	r2, [pc, #136]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001c6a:	68fb      	ldr	r3, [r7, #12]
 8001c6c:	6353      	str	r3, [r2, #52]	; 0x34

       /* Wait for LSERDY if LSE was enabled */
      if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON))
 8001c6e:	68fb      	ldr	r3, [r7, #12]
 8001c70:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001c74:	2b00      	cmp	r3, #0
 8001c76:	d014      	beq.n	8001ca2 <HAL_RCCEx_PeriphCLKConfig+0x166>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001c78:	f7fe feea 	bl	8000a50 <HAL_GetTick>
 8001c7c:	6138      	str	r0, [r7, #16]

        /* Wait till LSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8001c7e:	e00a      	b.n	8001c96 <HAL_RCCEx_PeriphCLKConfig+0x15a>
        {
          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8001c80:	f7fe fee6 	bl	8000a50 <HAL_GetTick>
 8001c84:	4602      	mov	r2, r0
 8001c86:	693b      	ldr	r3, [r7, #16]
 8001c88:	1ad3      	subs	r3, r2, r3
 8001c8a:	f241 3288 	movw	r2, #5000	; 0x1388
 8001c8e:	4293      	cmp	r3, r2
 8001c90:	d901      	bls.n	8001c96 <HAL_RCCEx_PeriphCLKConfig+0x15a>
          {
            return HAL_TIMEOUT;
 8001c92:	2303      	movs	r3, #3
 8001c94:	e02a      	b.n	8001cec <HAL_RCCEx_PeriphCLKConfig+0x1b0>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
 8001c96:	4b17      	ldr	r3, [pc, #92]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001c98:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8001c9a:	f403 7300 	and.w	r3, r3, #512	; 0x200
 8001c9e:	2b00      	cmp	r3, #0
 8001ca0:	d0ee      	beq.n	8001c80 <HAL_RCCEx_PeriphCLKConfig+0x144>
          }
        }
      }
    }
    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
 8001ca2:	687b      	ldr	r3, [r7, #4]
 8001ca4:	685b      	ldr	r3, [r3, #4]
 8001ca6:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001caa:	f5b3 3f40 	cmp.w	r3, #196608	; 0x30000
 8001cae:	d10a      	bne.n	8001cc6 <HAL_RCCEx_PeriphCLKConfig+0x18a>
 8001cb0:	4b10      	ldr	r3, [pc, #64]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001cb2:	681b      	ldr	r3, [r3, #0]
 8001cb4:	f023 42c0 	bic.w	r2, r3, #1610612736	; 0x60000000
 8001cb8:	687b      	ldr	r3, [r7, #4]
 8001cba:	685b      	ldr	r3, [r3, #4]
 8001cbc:	f003 43c0 	and.w	r3, r3, #1610612736	; 0x60000000
 8001cc0:	490c      	ldr	r1, [pc, #48]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001cc2:	4313      	orrs	r3, r2
 8001cc4:	600b      	str	r3, [r1, #0]
 8001cc6:	4b0b      	ldr	r3, [pc, #44]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001cc8:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8001cca:	687b      	ldr	r3, [r7, #4]
 8001ccc:	685b      	ldr	r3, [r3, #4]
 8001cce:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001cd2:	4908      	ldr	r1, [pc, #32]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001cd4:	4313      	orrs	r3, r2
 8001cd6:	634b      	str	r3, [r1, #52]	; 0x34

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 8001cd8:	7dfb      	ldrb	r3, [r7, #23]
 8001cda:	2b01      	cmp	r3, #1
 8001cdc:	d105      	bne.n	8001cea <HAL_RCCEx_PeriphCLKConfig+0x1ae>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8001cde:	4b05      	ldr	r3, [pc, #20]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001ce0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001ce2:	4a04      	ldr	r2, [pc, #16]	; (8001cf4 <HAL_RCCEx_PeriphCLKConfig+0x1b8>)
 8001ce4:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8001ce8:	6253      	str	r3, [r2, #36]	; 0x24
    }
  }

  return HAL_OK;
 8001cea:	2300      	movs	r3, #0
}
 8001cec:	4618      	mov	r0, r3
 8001cee:	3718      	adds	r7, #24
 8001cf0:	46bd      	mov	sp, r7
 8001cf2:	bd80      	pop	{r7, pc}
 8001cf4:	40023800 	.word	0x40023800
 8001cf8:	40007000 	.word	0x40007000
 8001cfc:	424706dc 	.word	0x424706dc

08001d00 <HAL_RTC_Init>:
  * @brief  Initialize the RTC peripheral
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
{
 8001d00:	b580      	push	{r7, lr}
 8001d02:	b082      	sub	sp, #8
 8001d04:	af00      	add	r7, sp, #0
 8001d06:	6078      	str	r0, [r7, #4]
  /* Check the RTC peripheral state */
  if (hrtc == NULL)
 8001d08:	687b      	ldr	r3, [r7, #4]
 8001d0a:	2b00      	cmp	r3, #0
 8001d0c:	d101      	bne.n	8001d12 <HAL_RTC_Init+0x12>
  {
    return HAL_ERROR;
 8001d0e:	2301      	movs	r3, #1
 8001d10:	e06d      	b.n	8001dee <HAL_RTC_Init+0xee>
    {
      hrtc->MspDeInitCallback = HAL_RTC_MspDeInit;
    }
  }
#else
  if (hrtc->State == HAL_RTC_STATE_RESET)
 8001d12:	687b      	ldr	r3, [r7, #4]
 8001d14:	7f5b      	ldrb	r3, [r3, #29]
 8001d16:	b2db      	uxtb	r3, r3
 8001d18:	2b00      	cmp	r3, #0
 8001d1a:	d105      	bne.n	8001d28 <HAL_RTC_Init+0x28>
  {
    /* Allocate lock resource and initialize it */
    hrtc->Lock = HAL_UNLOCKED;
 8001d1c:	687b      	ldr	r3, [r7, #4]
 8001d1e:	2200      	movs	r2, #0
 8001d20:	771a      	strb	r2, [r3, #28]

    /* Initialize RTC MSP */
    HAL_RTC_MspInit(hrtc);
 8001d22:	6878      	ldr	r0, [r7, #4]
 8001d24:	f7fe fd7a 	bl	800081c <HAL_RTC_MspInit>
  }
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */

  /* Set RTC state */
  hrtc->State = HAL_RTC_STATE_BUSY;
 8001d28:	687b      	ldr	r3, [r7, #4]
 8001d2a:	2202      	movs	r2, #2
 8001d2c:	775a      	strb	r2, [r3, #29]

  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 8001d2e:	687b      	ldr	r3, [r7, #4]
 8001d30:	681b      	ldr	r3, [r3, #0]
 8001d32:	22ca      	movs	r2, #202	; 0xca
 8001d34:	625a      	str	r2, [r3, #36]	; 0x24
 8001d36:	687b      	ldr	r3, [r7, #4]
 8001d38:	681b      	ldr	r3, [r3, #0]
 8001d3a:	2253      	movs	r2, #83	; 0x53
 8001d3c:	625a      	str	r2, [r3, #36]	; 0x24

  /* Set Initialization mode */
  if (RTC_EnterInitMode(hrtc) != HAL_OK)
 8001d3e:	6878      	ldr	r0, [r7, #4]
 8001d40:	f000 fa82 	bl	8002248 <RTC_EnterInitMode>
 8001d44:	4603      	mov	r3, r0
 8001d46:	2b00      	cmp	r3, #0
 8001d48:	d008      	beq.n	8001d5c <HAL_RTC_Init+0x5c>
  {
    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8001d4a:	687b      	ldr	r3, [r7, #4]
 8001d4c:	681b      	ldr	r3, [r3, #0]
 8001d4e:	22ff      	movs	r2, #255	; 0xff
 8001d50:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_ERROR;
 8001d52:	687b      	ldr	r3, [r7, #4]
 8001d54:	2204      	movs	r2, #4
 8001d56:	775a      	strb	r2, [r3, #29]

    return HAL_ERROR;
 8001d58:	2301      	movs	r3, #1
 8001d5a:	e048      	b.n	8001dee <HAL_RTC_Init+0xee>
  }
  else
  {
    /* Clear RTC_CR FMT, OSEL and POL Bits */
    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
 8001d5c:	687b      	ldr	r3, [r7, #4]
 8001d5e:	681b      	ldr	r3, [r3, #0]
 8001d60:	689b      	ldr	r3, [r3, #8]
 8001d62:	687a      	ldr	r2, [r7, #4]
 8001d64:	6812      	ldr	r2, [r2, #0]
 8001d66:	f423 03e0 	bic.w	r3, r3, #7340032	; 0x700000
 8001d6a:	f023 0340 	bic.w	r3, r3, #64	; 0x40
 8001d6e:	6093      	str	r3, [r2, #8]
    /* Set RTC_CR register */
    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
 8001d70:	687b      	ldr	r3, [r7, #4]
 8001d72:	681b      	ldr	r3, [r3, #0]
 8001d74:	6899      	ldr	r1, [r3, #8]
 8001d76:	687b      	ldr	r3, [r7, #4]
 8001d78:	685a      	ldr	r2, [r3, #4]
 8001d7a:	687b      	ldr	r3, [r7, #4]
 8001d7c:	691b      	ldr	r3, [r3, #16]
 8001d7e:	431a      	orrs	r2, r3
 8001d80:	687b      	ldr	r3, [r7, #4]
 8001d82:	695b      	ldr	r3, [r3, #20]
 8001d84:	431a      	orrs	r2, r3
 8001d86:	687b      	ldr	r3, [r7, #4]
 8001d88:	681b      	ldr	r3, [r3, #0]
 8001d8a:	430a      	orrs	r2, r1
 8001d8c:	609a      	str	r2, [r3, #8]

    /* Configure the RTC PRER */
    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
 8001d8e:	687b      	ldr	r3, [r7, #4]
 8001d90:	681b      	ldr	r3, [r3, #0]
 8001d92:	687a      	ldr	r2, [r7, #4]
 8001d94:	68d2      	ldr	r2, [r2, #12]
 8001d96:	611a      	str	r2, [r3, #16]
    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U);
 8001d98:	687b      	ldr	r3, [r7, #4]
 8001d9a:	681b      	ldr	r3, [r3, #0]
 8001d9c:	6919      	ldr	r1, [r3, #16]
 8001d9e:	687b      	ldr	r3, [r7, #4]
 8001da0:	689b      	ldr	r3, [r3, #8]
 8001da2:	041a      	lsls	r2, r3, #16
 8001da4:	687b      	ldr	r3, [r7, #4]
 8001da6:	681b      	ldr	r3, [r3, #0]
 8001da8:	430a      	orrs	r2, r1
 8001daa:	611a      	str	r2, [r3, #16]

    /* Exit Initialization mode */
    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
 8001dac:	687b      	ldr	r3, [r7, #4]
 8001dae:	681b      	ldr	r3, [r3, #0]
 8001db0:	68da      	ldr	r2, [r3, #12]
 8001db2:	687b      	ldr	r3, [r7, #4]
 8001db4:	681b      	ldr	r3, [r3, #0]
 8001db6:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8001dba:	60da      	str	r2, [r3, #12]

    hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
 8001dbc:	687b      	ldr	r3, [r7, #4]
 8001dbe:	681b      	ldr	r3, [r3, #0]
 8001dc0:	6c1a      	ldr	r2, [r3, #64]	; 0x40
 8001dc2:	687b      	ldr	r3, [r7, #4]
 8001dc4:	681b      	ldr	r3, [r3, #0]
 8001dc6:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8001dca:	641a      	str	r2, [r3, #64]	; 0x40
    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
 8001dcc:	687b      	ldr	r3, [r7, #4]
 8001dce:	681b      	ldr	r3, [r3, #0]
 8001dd0:	6c19      	ldr	r1, [r3, #64]	; 0x40
 8001dd2:	687b      	ldr	r3, [r7, #4]
 8001dd4:	699a      	ldr	r2, [r3, #24]
 8001dd6:	687b      	ldr	r3, [r7, #4]
 8001dd8:	681b      	ldr	r3, [r3, #0]
 8001dda:	430a      	orrs	r2, r1
 8001ddc:	641a      	str	r2, [r3, #64]	; 0x40

    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8001dde:	687b      	ldr	r3, [r7, #4]
 8001de0:	681b      	ldr	r3, [r3, #0]
 8001de2:	22ff      	movs	r2, #255	; 0xff
 8001de4:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_READY;
 8001de6:	687b      	ldr	r3, [r7, #4]
 8001de8:	2201      	movs	r2, #1
 8001dea:	775a      	strb	r2, [r3, #29]

    return HAL_OK;
 8001dec:	2300      	movs	r3, #0
  }
}
 8001dee:	4618      	mov	r0, r3
 8001df0:	3708      	adds	r7, #8
 8001df2:	46bd      	mov	sp, r7
 8001df4:	bd80      	pop	{r7, pc}

08001df6 <HAL_RTC_SetTime>:
  *            @arg RTC_FORMAT_BIN: Binary data format
  *            @arg RTC_FORMAT_BCD: BCD data format
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
 8001df6:	b590      	push	{r4, r7, lr}
 8001df8:	b087      	sub	sp, #28
 8001dfa:	af00      	add	r7, sp, #0
 8001dfc:	60f8      	str	r0, [r7, #12]
 8001dfe:	60b9      	str	r1, [r7, #8]
 8001e00:	607a      	str	r2, [r7, #4]
  assert_param(IS_RTC_FORMAT(Format));
  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));

  /* Process Locked */
  __HAL_LOCK(hrtc);
 8001e02:	68fb      	ldr	r3, [r7, #12]
 8001e04:	7f1b      	ldrb	r3, [r3, #28]
 8001e06:	2b01      	cmp	r3, #1
 8001e08:	d101      	bne.n	8001e0e <HAL_RTC_SetTime+0x18>
 8001e0a:	2302      	movs	r3, #2
 8001e0c:	e0a3      	b.n	8001f56 <HAL_RTC_SetTime+0x160>
 8001e0e:	68fb      	ldr	r3, [r7, #12]
 8001e10:	2201      	movs	r2, #1
 8001e12:	771a      	strb	r2, [r3, #28]

  hrtc->State = HAL_RTC_STATE_BUSY;
 8001e14:	68fb      	ldr	r3, [r7, #12]
 8001e16:	2202      	movs	r2, #2
 8001e18:	775a      	strb	r2, [r3, #29]

  if (Format == RTC_FORMAT_BIN)
 8001e1a:	687b      	ldr	r3, [r7, #4]
 8001e1c:	2b00      	cmp	r3, #0
 8001e1e:	d126      	bne.n	8001e6e <HAL_RTC_SetTime+0x78>
  {
    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
 8001e20:	68fb      	ldr	r3, [r7, #12]
 8001e22:	681b      	ldr	r3, [r3, #0]
 8001e24:	689b      	ldr	r3, [r3, #8]
 8001e26:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8001e2a:	2b00      	cmp	r3, #0
 8001e2c:	d102      	bne.n	8001e34 <HAL_RTC_SetTime+0x3e>
      assert_param(IS_RTC_HOUR12(sTime->Hours));
      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
    }
    else
    {
      sTime->TimeFormat = 0x00U;
 8001e2e:	68bb      	ldr	r3, [r7, #8]
 8001e30:	2200      	movs	r2, #0
 8001e32:	70da      	strb	r2, [r3, #3]
      assert_param(IS_RTC_HOUR24(sTime->Hours));
    }
    assert_param(IS_RTC_MINUTES(sTime->Minutes));
    assert_param(IS_RTC_SECONDS(sTime->Seconds));

    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
 8001e34:	68bb      	ldr	r3, [r7, #8]
 8001e36:	781b      	ldrb	r3, [r3, #0]
 8001e38:	4618      	mov	r0, r3
 8001e3a:	f000 fa2f 	bl	800229c <RTC_ByteToBcd2>
 8001e3e:	4603      	mov	r3, r0
 8001e40:	041c      	lsls	r4, r3, #16
                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
 8001e42:	68bb      	ldr	r3, [r7, #8]
 8001e44:	785b      	ldrb	r3, [r3, #1]
 8001e46:	4618      	mov	r0, r3
 8001e48:	f000 fa28 	bl	800229c <RTC_ByteToBcd2>
 8001e4c:	4603      	mov	r3, r0
 8001e4e:	021b      	lsls	r3, r3, #8
    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
 8001e50:	431c      	orrs	r4, r3
                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
 8001e52:	68bb      	ldr	r3, [r7, #8]
 8001e54:	789b      	ldrb	r3, [r3, #2]
 8001e56:	4618      	mov	r0, r3
 8001e58:	f000 fa20 	bl	800229c <RTC_ByteToBcd2>
 8001e5c:	4603      	mov	r3, r0
                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \
 8001e5e:	ea44 0203 	orr.w	r2, r4, r3
                        (((uint32_t)sTime->TimeFormat) << 16U));
 8001e62:	68bb      	ldr	r3, [r7, #8]
 8001e64:	78db      	ldrb	r3, [r3, #3]
 8001e66:	041b      	lsls	r3, r3, #16
    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \
 8001e68:	4313      	orrs	r3, r2
 8001e6a:	617b      	str	r3, [r7, #20]
 8001e6c:	e018      	b.n	8001ea0 <HAL_RTC_SetTime+0xaa>
  }
  else
  {
    if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U)
 8001e6e:	68fb      	ldr	r3, [r7, #12]
 8001e70:	681b      	ldr	r3, [r3, #0]
 8001e72:	689b      	ldr	r3, [r3, #8]
 8001e74:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8001e78:	2b00      	cmp	r3, #0
 8001e7a:	d102      	bne.n	8001e82 <HAL_RTC_SetTime+0x8c>
      assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours)));
      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
    }
    else
    {
      sTime->TimeFormat = 0x00U;
 8001e7c:	68bb      	ldr	r3, [r7, #8]
 8001e7e:	2200      	movs	r2, #0
 8001e80:	70da      	strb	r2, [r3, #3]
      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
    }
    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
 8001e82:	68bb      	ldr	r3, [r7, #8]
 8001e84:	781b      	ldrb	r3, [r3, #0]
 8001e86:	041a      	lsls	r2, r3, #16
              ((uint32_t)(sTime->Minutes) << 8U) | \
 8001e88:	68bb      	ldr	r3, [r7, #8]
 8001e8a:	785b      	ldrb	r3, [r3, #1]
 8001e8c:	021b      	lsls	r3, r3, #8
    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
 8001e8e:	4313      	orrs	r3, r2
              ((uint32_t)sTime->Seconds) | \
 8001e90:	68ba      	ldr	r2, [r7, #8]
 8001e92:	7892      	ldrb	r2, [r2, #2]
              ((uint32_t)(sTime->Minutes) << 8U) | \
 8001e94:	431a      	orrs	r2, r3
              ((uint32_t)(sTime->TimeFormat) << 16U));
 8001e96:	68bb      	ldr	r3, [r7, #8]
 8001e98:	78db      	ldrb	r3, [r3, #3]
 8001e9a:	041b      	lsls	r3, r3, #16
    tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \
 8001e9c:	4313      	orrs	r3, r2
 8001e9e:	617b      	str	r3, [r7, #20]
  }
  UNUSED(tmpreg);
  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 8001ea0:	68fb      	ldr	r3, [r7, #12]
 8001ea2:	681b      	ldr	r3, [r3, #0]
 8001ea4:	22ca      	movs	r2, #202	; 0xca
 8001ea6:	625a      	str	r2, [r3, #36]	; 0x24
 8001ea8:	68fb      	ldr	r3, [r7, #12]
 8001eaa:	681b      	ldr	r3, [r3, #0]
 8001eac:	2253      	movs	r2, #83	; 0x53
 8001eae:	625a      	str	r2, [r3, #36]	; 0x24

  /* Set Initialization mode */
  if (RTC_EnterInitMode(hrtc) != HAL_OK)
 8001eb0:	68f8      	ldr	r0, [r7, #12]
 8001eb2:	f000 f9c9 	bl	8002248 <RTC_EnterInitMode>
 8001eb6:	4603      	mov	r3, r0
 8001eb8:	2b00      	cmp	r3, #0
 8001eba:	d00b      	beq.n	8001ed4 <HAL_RTC_SetTime+0xde>
  {
    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8001ebc:	68fb      	ldr	r3, [r7, #12]
 8001ebe:	681b      	ldr	r3, [r3, #0]
 8001ec0:	22ff      	movs	r2, #255	; 0xff
 8001ec2:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state */
    hrtc->State = HAL_RTC_STATE_ERROR;
 8001ec4:	68fb      	ldr	r3, [r7, #12]
 8001ec6:	2204      	movs	r2, #4
 8001ec8:	775a      	strb	r2, [r3, #29]

    /* Process Unlocked */
    __HAL_UNLOCK(hrtc);
 8001eca:	68fb      	ldr	r3, [r7, #12]
 8001ecc:	2200      	movs	r2, #0
 8001ece:	771a      	strb	r2, [r3, #28]

    return HAL_ERROR;
 8001ed0:	2301      	movs	r3, #1
 8001ed2:	e040      	b.n	8001f56 <HAL_RTC_SetTime+0x160>
  }
  else
  {
    /* Set the RTC_TR register */
    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
 8001ed4:	68fb      	ldr	r3, [r7, #12]
 8001ed6:	681a      	ldr	r2, [r3, #0]
 8001ed8:	697b      	ldr	r3, [r7, #20]
 8001eda:	f003 337f 	and.w	r3, r3, #2139062143	; 0x7f7f7f7f
 8001ede:	f023 43fe 	bic.w	r3, r3, #2130706432	; 0x7f000000
 8001ee2:	6013      	str	r3, [r2, #0]

    /* Clear the bits to be configured */
    hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BKP);
 8001ee4:	68fb      	ldr	r3, [r7, #12]
 8001ee6:	681b      	ldr	r3, [r3, #0]
 8001ee8:	689a      	ldr	r2, [r3, #8]
 8001eea:	68fb      	ldr	r3, [r7, #12]
 8001eec:	681b      	ldr	r3, [r3, #0]
 8001eee:	f422 2280 	bic.w	r2, r2, #262144	; 0x40000
 8001ef2:	609a      	str	r2, [r3, #8]

    /* Configure the RTC_CR register */
    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
 8001ef4:	68fb      	ldr	r3, [r7, #12]
 8001ef6:	681b      	ldr	r3, [r3, #0]
 8001ef8:	6899      	ldr	r1, [r3, #8]
 8001efa:	68bb      	ldr	r3, [r7, #8]
 8001efc:	68da      	ldr	r2, [r3, #12]
 8001efe:	68bb      	ldr	r3, [r7, #8]
 8001f00:	691b      	ldr	r3, [r3, #16]
 8001f02:	431a      	orrs	r2, r3
 8001f04:	68fb      	ldr	r3, [r7, #12]
 8001f06:	681b      	ldr	r3, [r3, #0]
 8001f08:	430a      	orrs	r2, r1
 8001f0a:	609a      	str	r2, [r3, #8]

    /* Exit Initialization mode */
    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
 8001f0c:	68fb      	ldr	r3, [r7, #12]
 8001f0e:	681b      	ldr	r3, [r3, #0]
 8001f10:	68da      	ldr	r2, [r3, #12]
 8001f12:	68fb      	ldr	r3, [r7, #12]
 8001f14:	681b      	ldr	r3, [r3, #0]
 8001f16:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8001f1a:	60da      	str	r2, [r3, #12]

    /* Wait for synchro */
    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 8001f1c:	68f8      	ldr	r0, [r7, #12]
 8001f1e:	f000 f966 	bl	80021ee <HAL_RTC_WaitForSynchro>
 8001f22:	4603      	mov	r3, r0
 8001f24:	2b00      	cmp	r3, #0
 8001f26:	d00b      	beq.n	8001f40 <HAL_RTC_SetTime+0x14a>
    {
      /* Enable the write protection for RTC registers */
      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8001f28:	68fb      	ldr	r3, [r7, #12]
 8001f2a:	681b      	ldr	r3, [r3, #0]
 8001f2c:	22ff      	movs	r2, #255	; 0xff
 8001f2e:	625a      	str	r2, [r3, #36]	; 0x24

      hrtc->State = HAL_RTC_STATE_ERROR;
 8001f30:	68fb      	ldr	r3, [r7, #12]
 8001f32:	2204      	movs	r2, #4
 8001f34:	775a      	strb	r2, [r3, #29]

      /* Process Unlocked */
      __HAL_UNLOCK(hrtc);
 8001f36:	68fb      	ldr	r3, [r7, #12]
 8001f38:	2200      	movs	r2, #0
 8001f3a:	771a      	strb	r2, [r3, #28]

      return HAL_ERROR;
 8001f3c:	2301      	movs	r3, #1
 8001f3e:	e00a      	b.n	8001f56 <HAL_RTC_SetTime+0x160>
    }

    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8001f40:	68fb      	ldr	r3, [r7, #12]
 8001f42:	681b      	ldr	r3, [r3, #0]
 8001f44:	22ff      	movs	r2, #255	; 0xff
 8001f46:	625a      	str	r2, [r3, #36]	; 0x24

    hrtc->State = HAL_RTC_STATE_READY;
 8001f48:	68fb      	ldr	r3, [r7, #12]
 8001f4a:	2201      	movs	r2, #1
 8001f4c:	775a      	strb	r2, [r3, #29]

    __HAL_UNLOCK(hrtc);
 8001f4e:	68fb      	ldr	r3, [r7, #12]
 8001f50:	2200      	movs	r2, #0
 8001f52:	771a      	strb	r2, [r3, #28]

    return HAL_OK;
 8001f54:	2300      	movs	r3, #0
  }
}
 8001f56:	4618      	mov	r0, r3
 8001f58:	371c      	adds	r7, #28
 8001f5a:	46bd      	mov	sp, r7
 8001f5c:	bd90      	pop	{r4, r7, pc}

08001f5e <HAL_RTC_GetTime>:
  *        Reading RTC current time locks the values in calendar shadow registers until Current date is read
  *        to ensure consistency between the time and date values.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
{
 8001f5e:	b580      	push	{r7, lr}
 8001f60:	b086      	sub	sp, #24
 8001f62:	af00      	add	r7, sp, #0
 8001f64:	60f8      	str	r0, [r7, #12]
 8001f66:	60b9      	str	r1, [r7, #8]
 8001f68:	607a      	str	r2, [r7, #4]
  /* Check the parameters */
  assert_param(IS_RTC_FORMAT(Format));

#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
  /* Get subseconds structure field from the corresponding register*/
  sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS);
 8001f6a:	68fb      	ldr	r3, [r7, #12]
 8001f6c:	681b      	ldr	r3, [r3, #0]
 8001f6e:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8001f70:	b29a      	uxth	r2, r3
 8001f72:	68bb      	ldr	r3, [r7, #8]
 8001f74:	605a      	str	r2, [r3, #4]

  /* Get SecondFraction structure field from the corresponding register field*/
  sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
 8001f76:	68fb      	ldr	r3, [r7, #12]
 8001f78:	681b      	ldr	r3, [r3, #0]
 8001f7a:	691b      	ldr	r3, [r3, #16]
 8001f7c:	f3c3 020e 	ubfx	r2, r3, #0, #15
 8001f80:	68bb      	ldr	r3, [r7, #8]
 8001f82:	609a      	str	r2, [r3, #8]
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  /* Get the TR register */
  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
 8001f84:	68fb      	ldr	r3, [r7, #12]
 8001f86:	681b      	ldr	r3, [r3, #0]
 8001f88:	681b      	ldr	r3, [r3, #0]
 8001f8a:	f003 337f 	and.w	r3, r3, #2139062143	; 0x7f7f7f7f
 8001f8e:	f023 43fe 	bic.w	r3, r3, #2130706432	; 0x7f000000
 8001f92:	617b      	str	r3, [r7, #20]

  /* Fill the structure fields with the read parameters */
  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
 8001f94:	697b      	ldr	r3, [r7, #20]
 8001f96:	0c1b      	lsrs	r3, r3, #16
 8001f98:	b2db      	uxtb	r3, r3
 8001f9a:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 8001f9e:	b2da      	uxtb	r2, r3
 8001fa0:	68bb      	ldr	r3, [r7, #8]
 8001fa2:	701a      	strb	r2, [r3, #0]
  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
 8001fa4:	697b      	ldr	r3, [r7, #20]
 8001fa6:	0a1b      	lsrs	r3, r3, #8
 8001fa8:	b2db      	uxtb	r3, r3
 8001faa:	f003 037f 	and.w	r3, r3, #127	; 0x7f
 8001fae:	b2da      	uxtb	r2, r3
 8001fb0:	68bb      	ldr	r3, [r7, #8]
 8001fb2:	705a      	strb	r2, [r3, #1]
  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
 8001fb4:	697b      	ldr	r3, [r7, #20]
 8001fb6:	b2db      	uxtb	r3, r3
 8001fb8:	f003 037f 	and.w	r3, r3, #127	; 0x7f
 8001fbc:	b2da      	uxtb	r2, r3
 8001fbe:	68bb      	ldr	r3, [r7, #8]
 8001fc0:	709a      	strb	r2, [r3, #2]
  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U);
 8001fc2:	697b      	ldr	r3, [r7, #20]
 8001fc4:	0c1b      	lsrs	r3, r3, #16
 8001fc6:	b2db      	uxtb	r3, r3
 8001fc8:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8001fcc:	b2da      	uxtb	r2, r3
 8001fce:	68bb      	ldr	r3, [r7, #8]
 8001fd0:	70da      	strb	r2, [r3, #3]

  /* Check the input parameters format */
  if (Format == RTC_FORMAT_BIN)
 8001fd2:	687b      	ldr	r3, [r7, #4]
 8001fd4:	2b00      	cmp	r3, #0
 8001fd6:	d11a      	bne.n	800200e <HAL_RTC_GetTime+0xb0>
  {
    /* Convert the time structure parameters to Binary format */
    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
 8001fd8:	68bb      	ldr	r3, [r7, #8]
 8001fda:	781b      	ldrb	r3, [r3, #0]
 8001fdc:	4618      	mov	r0, r3
 8001fde:	f000 f97c 	bl	80022da <RTC_Bcd2ToByte>
 8001fe2:	4603      	mov	r3, r0
 8001fe4:	461a      	mov	r2, r3
 8001fe6:	68bb      	ldr	r3, [r7, #8]
 8001fe8:	701a      	strb	r2, [r3, #0]
    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
 8001fea:	68bb      	ldr	r3, [r7, #8]
 8001fec:	785b      	ldrb	r3, [r3, #1]
 8001fee:	4618      	mov	r0, r3
 8001ff0:	f000 f973 	bl	80022da <RTC_Bcd2ToByte>
 8001ff4:	4603      	mov	r3, r0
 8001ff6:	461a      	mov	r2, r3
 8001ff8:	68bb      	ldr	r3, [r7, #8]
 8001ffa:	705a      	strb	r2, [r3, #1]
    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);
 8001ffc:	68bb      	ldr	r3, [r7, #8]
 8001ffe:	789b      	ldrb	r3, [r3, #2]
 8002000:	4618      	mov	r0, r3
 8002002:	f000 f96a 	bl	80022da <RTC_Bcd2ToByte>
 8002006:	4603      	mov	r3, r0
 8002008:	461a      	mov	r2, r3
 800200a:	68bb      	ldr	r3, [r7, #8]
 800200c:	709a      	strb	r2, [r3, #2]
  }

  return HAL_OK;
 800200e:	2300      	movs	r3, #0
}
 8002010:	4618      	mov	r0, r3
 8002012:	3718      	adds	r7, #24
 8002014:	46bd      	mov	sp, r7
 8002016:	bd80      	pop	{r7, pc}

08002018 <HAL_RTC_SetDate>:
  *            @arg RTC_FORMAT_BIN: Binary data format
  *            @arg RTC_FORMAT_BCD: BCD data format
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
 8002018:	b590      	push	{r4, r7, lr}
 800201a:	b087      	sub	sp, #28
 800201c:	af00      	add	r7, sp, #0
 800201e:	60f8      	str	r0, [r7, #12]
 8002020:	60b9      	str	r1, [r7, #8]
 8002022:	607a      	str	r2, [r7, #4]

  /* Check the parameters */
  assert_param(IS_RTC_FORMAT(Format));

  /* Process Locked */
  __HAL_LOCK(hrtc);
 8002024:	68fb      	ldr	r3, [r7, #12]
 8002026:	7f1b      	ldrb	r3, [r3, #28]
 8002028:	2b01      	cmp	r3, #1
 800202a:	d101      	bne.n	8002030 <HAL_RTC_SetDate+0x18>
 800202c:	2302      	movs	r3, #2
 800202e:	e08d      	b.n	800214c <HAL_RTC_SetDate+0x134>
 8002030:	68fb      	ldr	r3, [r7, #12]
 8002032:	2201      	movs	r2, #1
 8002034:	771a      	strb	r2, [r3, #28]

  hrtc->State = HAL_RTC_STATE_BUSY;
 8002036:	68fb      	ldr	r3, [r7, #12]
 8002038:	2202      	movs	r2, #2
 800203a:	775a      	strb	r2, [r3, #29]

  if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
 800203c:	687b      	ldr	r3, [r7, #4]
 800203e:	2b00      	cmp	r3, #0
 8002040:	d10e      	bne.n	8002060 <HAL_RTC_SetDate+0x48>
 8002042:	68bb      	ldr	r3, [r7, #8]
 8002044:	785b      	ldrb	r3, [r3, #1]
 8002046:	f003 0310 	and.w	r3, r3, #16
 800204a:	2b00      	cmp	r3, #0
 800204c:	d008      	beq.n	8002060 <HAL_RTC_SetDate+0x48>
  {
    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
 800204e:	68bb      	ldr	r3, [r7, #8]
 8002050:	785b      	ldrb	r3, [r3, #1]
 8002052:	f023 0310 	bic.w	r3, r3, #16
 8002056:	b2db      	uxtb	r3, r3
 8002058:	330a      	adds	r3, #10
 800205a:	b2da      	uxtb	r2, r3
 800205c:	68bb      	ldr	r3, [r7, #8]
 800205e:	705a      	strb	r2, [r3, #1]
  }

  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));

  if (Format == RTC_FORMAT_BIN)
 8002060:	687b      	ldr	r3, [r7, #4]
 8002062:	2b00      	cmp	r3, #0
 8002064:	d11c      	bne.n	80020a0 <HAL_RTC_SetDate+0x88>
  {
    assert_param(IS_RTC_YEAR(sDate->Year));
    assert_param(IS_RTC_MONTH(sDate->Month));
    assert_param(IS_RTC_DATE(sDate->Date));

    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
 8002066:	68bb      	ldr	r3, [r7, #8]
 8002068:	78db      	ldrb	r3, [r3, #3]
 800206a:	4618      	mov	r0, r3
 800206c:	f000 f916 	bl	800229c <RTC_ByteToBcd2>
 8002070:	4603      	mov	r3, r0
 8002072:	041c      	lsls	r4, r3, #16
                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
 8002074:	68bb      	ldr	r3, [r7, #8]
 8002076:	785b      	ldrb	r3, [r3, #1]
 8002078:	4618      	mov	r0, r3
 800207a:	f000 f90f 	bl	800229c <RTC_ByteToBcd2>
 800207e:	4603      	mov	r3, r0
 8002080:	021b      	lsls	r3, r3, #8
    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
 8002082:	431c      	orrs	r4, r3
                  ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
 8002084:	68bb      	ldr	r3, [r7, #8]
 8002086:	789b      	ldrb	r3, [r3, #2]
 8002088:	4618      	mov	r0, r3
 800208a:	f000 f907 	bl	800229c <RTC_ByteToBcd2>
 800208e:	4603      	mov	r3, r0
                  ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \
 8002090:	ea44 0203 	orr.w	r2, r4, r3
                  ((uint32_t)sDate->WeekDay << 13U));
 8002094:	68bb      	ldr	r3, [r7, #8]
 8002096:	781b      	ldrb	r3, [r3, #0]
 8002098:	035b      	lsls	r3, r3, #13
    datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \
 800209a:	4313      	orrs	r3, r2
 800209c:	617b      	str	r3, [r7, #20]
 800209e:	e00e      	b.n	80020be <HAL_RTC_SetDate+0xa6>
  {
    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
    assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month)));
    assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date)));

    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
 80020a0:	68bb      	ldr	r3, [r7, #8]
 80020a2:	78db      	ldrb	r3, [r3, #3]
 80020a4:	041a      	lsls	r2, r3, #16
                  (((uint32_t)sDate->Month) << 8U) | \
 80020a6:	68bb      	ldr	r3, [r7, #8]
 80020a8:	785b      	ldrb	r3, [r3, #1]
 80020aa:	021b      	lsls	r3, r3, #8
    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
 80020ac:	4313      	orrs	r3, r2
                  ((uint32_t)sDate->Date) | \
 80020ae:	68ba      	ldr	r2, [r7, #8]
 80020b0:	7892      	ldrb	r2, [r2, #2]
                  (((uint32_t)sDate->Month) << 8U) | \
 80020b2:	431a      	orrs	r2, r3
                  (((uint32_t)sDate->WeekDay) << 13U));
 80020b4:	68bb      	ldr	r3, [r7, #8]
 80020b6:	781b      	ldrb	r3, [r3, #0]
 80020b8:	035b      	lsls	r3, r3, #13
    datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
 80020ba:	4313      	orrs	r3, r2
 80020bc:	617b      	str	r3, [r7, #20]
  }

  /* Disable the write protection for RTC registers */
  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
 80020be:	68fb      	ldr	r3, [r7, #12]
 80020c0:	681b      	ldr	r3, [r3, #0]
 80020c2:	22ca      	movs	r2, #202	; 0xca
 80020c4:	625a      	str	r2, [r3, #36]	; 0x24
 80020c6:	68fb      	ldr	r3, [r7, #12]
 80020c8:	681b      	ldr	r3, [r3, #0]
 80020ca:	2253      	movs	r2, #83	; 0x53
 80020cc:	625a      	str	r2, [r3, #36]	; 0x24

  /* Set Initialization mode */
  if (RTC_EnterInitMode(hrtc) != HAL_OK)
 80020ce:	68f8      	ldr	r0, [r7, #12]
 80020d0:	f000 f8ba 	bl	8002248 <RTC_EnterInitMode>
 80020d4:	4603      	mov	r3, r0
 80020d6:	2b00      	cmp	r3, #0
 80020d8:	d00b      	beq.n	80020f2 <HAL_RTC_SetDate+0xda>
  {
    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 80020da:	68fb      	ldr	r3, [r7, #12]
 80020dc:	681b      	ldr	r3, [r3, #0]
 80020de:	22ff      	movs	r2, #255	; 0xff
 80020e0:	625a      	str	r2, [r3, #36]	; 0x24

    /* Set RTC state*/
    hrtc->State = HAL_RTC_STATE_ERROR;
 80020e2:	68fb      	ldr	r3, [r7, #12]
 80020e4:	2204      	movs	r2, #4
 80020e6:	775a      	strb	r2, [r3, #29]

    /* Process Unlocked */
    __HAL_UNLOCK(hrtc);
 80020e8:	68fb      	ldr	r3, [r7, #12]
 80020ea:	2200      	movs	r2, #0
 80020ec:	771a      	strb	r2, [r3, #28]

    return HAL_ERROR;
 80020ee:	2301      	movs	r3, #1
 80020f0:	e02c      	b.n	800214c <HAL_RTC_SetDate+0x134>
  }
  else
  {
    /* Set the RTC_DR register */
    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
 80020f2:	68fb      	ldr	r3, [r7, #12]
 80020f4:	681a      	ldr	r2, [r3, #0]
 80020f6:	697b      	ldr	r3, [r7, #20]
 80020f8:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
 80020fc:	f023 03c0 	bic.w	r3, r3, #192	; 0xc0
 8002100:	6053      	str	r3, [r2, #4]

    /* Exit Initialization mode */
    hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT);
 8002102:	68fb      	ldr	r3, [r7, #12]
 8002104:	681b      	ldr	r3, [r3, #0]
 8002106:	68da      	ldr	r2, [r3, #12]
 8002108:	68fb      	ldr	r3, [r7, #12]
 800210a:	681b      	ldr	r3, [r3, #0]
 800210c:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 8002110:	60da      	str	r2, [r3, #12]

    /* Wait for synchro */
    if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
 8002112:	68f8      	ldr	r0, [r7, #12]
 8002114:	f000 f86b 	bl	80021ee <HAL_RTC_WaitForSynchro>
 8002118:	4603      	mov	r3, r0
 800211a:	2b00      	cmp	r3, #0
 800211c:	d00b      	beq.n	8002136 <HAL_RTC_SetDate+0x11e>
    {
      /* Enable the write protection for RTC registers */
      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 800211e:	68fb      	ldr	r3, [r7, #12]
 8002120:	681b      	ldr	r3, [r3, #0]
 8002122:	22ff      	movs	r2, #255	; 0xff
 8002124:	625a      	str	r2, [r3, #36]	; 0x24

      hrtc->State = HAL_RTC_STATE_ERROR;
 8002126:	68fb      	ldr	r3, [r7, #12]
 8002128:	2204      	movs	r2, #4
 800212a:	775a      	strb	r2, [r3, #29]

      /* Process Unlocked */
      __HAL_UNLOCK(hrtc);
 800212c:	68fb      	ldr	r3, [r7, #12]
 800212e:	2200      	movs	r2, #0
 8002130:	771a      	strb	r2, [r3, #28]

      return HAL_ERROR;
 8002132:	2301      	movs	r3, #1
 8002134:	e00a      	b.n	800214c <HAL_RTC_SetDate+0x134>
    }

    /* Enable the write protection for RTC registers */
    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
 8002136:	68fb      	ldr	r3, [r7, #12]
 8002138:	681b      	ldr	r3, [r3, #0]
 800213a:	22ff      	movs	r2, #255	; 0xff
 800213c:	625a      	str	r2, [r3, #36]	; 0x24

    hrtc->State = HAL_RTC_STATE_READY ;
 800213e:	68fb      	ldr	r3, [r7, #12]
 8002140:	2201      	movs	r2, #1
 8002142:	775a      	strb	r2, [r3, #29]

    /* Process Unlocked */
    __HAL_UNLOCK(hrtc);
 8002144:	68fb      	ldr	r3, [r7, #12]
 8002146:	2200      	movs	r2, #0
 8002148:	771a      	strb	r2, [r3, #28]

    return HAL_OK;
 800214a:	2300      	movs	r3, #0
  }
}
 800214c:	4618      	mov	r0, r3
 800214e:	371c      	adds	r7, #28
 8002150:	46bd      	mov	sp, r7
 8002152:	bd90      	pop	{r4, r7, pc}

08002154 <HAL_RTC_GetDate>:
  * in the higher-order calendar shadow registers to ensure consistency between the time and date values.
  * Reading RTC current time locks the values in calendar shadow registers until Current date is read.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
{
 8002154:	b580      	push	{r7, lr}
 8002156:	b086      	sub	sp, #24
 8002158:	af00      	add	r7, sp, #0
 800215a:	60f8      	str	r0, [r7, #12]
 800215c:	60b9      	str	r1, [r7, #8]
 800215e:	607a      	str	r2, [r7, #4]

  /* Check the parameters */
  assert_param(IS_RTC_FORMAT(Format));

  /* Get the DR register */
  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK);
 8002160:	68fb      	ldr	r3, [r7, #12]
 8002162:	681b      	ldr	r3, [r3, #0]
 8002164:	685b      	ldr	r3, [r3, #4]
 8002166:	f023 437f 	bic.w	r3, r3, #4278190080	; 0xff000000
 800216a:	f023 03c0 	bic.w	r3, r3, #192	; 0xc0
 800216e:	617b      	str	r3, [r7, #20]

  /* Fill the structure fields with the read parameters */
  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U);
 8002170:	697b      	ldr	r3, [r7, #20]
 8002172:	0c1b      	lsrs	r3, r3, #16
 8002174:	b2da      	uxtb	r2, r3
 8002176:	68bb      	ldr	r3, [r7, #8]
 8002178:	70da      	strb	r2, [r3, #3]
  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
 800217a:	697b      	ldr	r3, [r7, #20]
 800217c:	0a1b      	lsrs	r3, r3, #8
 800217e:	b2db      	uxtb	r3, r3
 8002180:	f003 031f 	and.w	r3, r3, #31
 8002184:	b2da      	uxtb	r2, r3
 8002186:	68bb      	ldr	r3, [r7, #8]
 8002188:	705a      	strb	r2, [r3, #1]
  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
 800218a:	697b      	ldr	r3, [r7, #20]
 800218c:	b2db      	uxtb	r3, r3
 800218e:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 8002192:	b2da      	uxtb	r2, r3
 8002194:	68bb      	ldr	r3, [r7, #8]
 8002196:	709a      	strb	r2, [r3, #2]
  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U);
 8002198:	697b      	ldr	r3, [r7, #20]
 800219a:	0b5b      	lsrs	r3, r3, #13
 800219c:	b2db      	uxtb	r3, r3
 800219e:	f003 0307 	and.w	r3, r3, #7
 80021a2:	b2da      	uxtb	r2, r3
 80021a4:	68bb      	ldr	r3, [r7, #8]
 80021a6:	701a      	strb	r2, [r3, #0]

  /* Check the input parameters format */
  if (Format == RTC_FORMAT_BIN)
 80021a8:	687b      	ldr	r3, [r7, #4]
 80021aa:	2b00      	cmp	r3, #0
 80021ac:	d11a      	bne.n	80021e4 <HAL_RTC_GetDate+0x90>
  {
    /* Convert the date structure parameters to Binary format */
    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
 80021ae:	68bb      	ldr	r3, [r7, #8]
 80021b0:	78db      	ldrb	r3, [r3, #3]
 80021b2:	4618      	mov	r0, r3
 80021b4:	f000 f891 	bl	80022da <RTC_Bcd2ToByte>
 80021b8:	4603      	mov	r3, r0
 80021ba:	461a      	mov	r2, r3
 80021bc:	68bb      	ldr	r3, [r7, #8]
 80021be:	70da      	strb	r2, [r3, #3]
    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
 80021c0:	68bb      	ldr	r3, [r7, #8]
 80021c2:	785b      	ldrb	r3, [r3, #1]
 80021c4:	4618      	mov	r0, r3
 80021c6:	f000 f888 	bl	80022da <RTC_Bcd2ToByte>
 80021ca:	4603      	mov	r3, r0
 80021cc:	461a      	mov	r2, r3
 80021ce:	68bb      	ldr	r3, [r7, #8]
 80021d0:	705a      	strb	r2, [r3, #1]
    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);
 80021d2:	68bb      	ldr	r3, [r7, #8]
 80021d4:	789b      	ldrb	r3, [r3, #2]
 80021d6:	4618      	mov	r0, r3
 80021d8:	f000 f87f 	bl	80022da <RTC_Bcd2ToByte>
 80021dc:	4603      	mov	r3, r0
 80021de:	461a      	mov	r2, r3
 80021e0:	68bb      	ldr	r3, [r7, #8]
 80021e2:	709a      	strb	r2, [r3, #2]
  }
  return HAL_OK;
 80021e4:	2300      	movs	r3, #0
}
 80021e6:	4618      	mov	r0, r3
 80021e8:	3718      	adds	r7, #24
 80021ea:	46bd      	mov	sp, r7
 80021ec:	bd80      	pop	{r7, pc}

080021ee <HAL_RTC_WaitForSynchro>:
  *         correctly copied into the RTC_TR and RTC_DR shadow registers.
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc)
{
 80021ee:	b580      	push	{r7, lr}
 80021f0:	b084      	sub	sp, #16
 80021f2:	af00      	add	r7, sp, #0
 80021f4:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX)
  /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
  if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
 80021f6:	687b      	ldr	r3, [r7, #4]
 80021f8:	681b      	ldr	r3, [r3, #0]
 80021fa:	689b      	ldr	r3, [r3, #8]
 80021fc:	f003 0320 	and.w	r3, r3, #32
 8002200:	2b00      	cmp	r3, #0
 8002202:	d11c      	bne.n	800223e <HAL_RTC_WaitForSynchro+0x50>
#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */
  {
    /* Clear RSF flag */
    hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
 8002204:	687b      	ldr	r3, [r7, #4]
 8002206:	681b      	ldr	r3, [r3, #0]
 8002208:	68da      	ldr	r2, [r3, #12]
 800220a:	687b      	ldr	r3, [r7, #4]
 800220c:	681b      	ldr	r3, [r3, #0]
 800220e:	f022 02a0 	bic.w	r2, r2, #160	; 0xa0
 8002212:	60da      	str	r2, [r3, #12]

    tickstart = HAL_GetTick();
 8002214:	f7fe fc1c 	bl	8000a50 <HAL_GetTick>
 8002218:	60f8      	str	r0, [r7, #12]

    /* Wait the registers to be synchronised */
    while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
 800221a:	e009      	b.n	8002230 <HAL_RTC_WaitForSynchro+0x42>
    {
      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
 800221c:	f7fe fc18 	bl	8000a50 <HAL_GetTick>
 8002220:	4602      	mov	r2, r0
 8002222:	68fb      	ldr	r3, [r7, #12]
 8002224:	1ad3      	subs	r3, r2, r3
 8002226:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 800222a:	d901      	bls.n	8002230 <HAL_RTC_WaitForSynchro+0x42>
      {
        return HAL_TIMEOUT;
 800222c:	2303      	movs	r3, #3
 800222e:	e007      	b.n	8002240 <HAL_RTC_WaitForSynchro+0x52>
    while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U)
 8002230:	687b      	ldr	r3, [r7, #4]
 8002232:	681b      	ldr	r3, [r3, #0]
 8002234:	68db      	ldr	r3, [r3, #12]
 8002236:	f003 0320 	and.w	r3, r3, #32
 800223a:	2b00      	cmp	r3, #0
 800223c:	d0ee      	beq.n	800221c <HAL_RTC_WaitForSynchro+0x2e>
      }
    }
  }

  return HAL_OK;
 800223e:	2300      	movs	r3, #0
}
 8002240:	4618      	mov	r0, r3
 8002242:	3710      	adds	r7, #16
 8002244:	46bd      	mov	sp, r7
 8002246:	bd80      	pop	{r7, pc}

08002248 <RTC_EnterInitMode>:
  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
  * @param  hrtc RTC handle
  * @retval HAL status
  */
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc)
{
 8002248:	b580      	push	{r7, lr}
 800224a:	b084      	sub	sp, #16
 800224c:	af00      	add	r7, sp, #0
 800224e:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;

  /* Check if the Initialization mode is set */
  if ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
 8002250:	687b      	ldr	r3, [r7, #4]
 8002252:	681b      	ldr	r3, [r3, #0]
 8002254:	68db      	ldr	r3, [r3, #12]
 8002256:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800225a:	2b00      	cmp	r3, #0
 800225c:	d119      	bne.n	8002292 <RTC_EnterInitMode+0x4a>
  {
    /* Set the Initialization mode */
    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
 800225e:	687b      	ldr	r3, [r7, #4]
 8002260:	681b      	ldr	r3, [r3, #0]
 8002262:	f04f 32ff 	mov.w	r2, #4294967295
 8002266:	60da      	str	r2, [r3, #12]

    tickstart = HAL_GetTick();
 8002268:	f7fe fbf2 	bl	8000a50 <HAL_GetTick>
 800226c:	60f8      	str	r0, [r7, #12]
    /* Wait till RTC is in INIT state and if Time out is reached exit */
    while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
 800226e:	e009      	b.n	8002284 <RTC_EnterInitMode+0x3c>
    {
      if ((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
 8002270:	f7fe fbee 	bl	8000a50 <HAL_GetTick>
 8002274:	4602      	mov	r2, r0
 8002276:	68fb      	ldr	r3, [r7, #12]
 8002278:	1ad3      	subs	r3, r2, r3
 800227a:	f5b3 7f7a 	cmp.w	r3, #1000	; 0x3e8
 800227e:	d901      	bls.n	8002284 <RTC_EnterInitMode+0x3c>
      {
        return HAL_TIMEOUT;
 8002280:	2303      	movs	r3, #3
 8002282:	e007      	b.n	8002294 <RTC_EnterInitMode+0x4c>
    while ((hrtc->Instance->ISR & RTC_ISR_INITF) == 0U)
 8002284:	687b      	ldr	r3, [r7, #4]
 8002286:	681b      	ldr	r3, [r3, #0]
 8002288:	68db      	ldr	r3, [r3, #12]
 800228a:	f003 0340 	and.w	r3, r3, #64	; 0x40
 800228e:	2b00      	cmp	r3, #0
 8002290:	d0ee      	beq.n	8002270 <RTC_EnterInitMode+0x28>
      }
    }
  }

  return HAL_OK;
 8002292:	2300      	movs	r3, #0
}
 8002294:	4618      	mov	r0, r3
 8002296:	3710      	adds	r7, #16
 8002298:	46bd      	mov	sp, r7
 800229a:	bd80      	pop	{r7, pc}

0800229c <RTC_ByteToBcd2>:
  * @brief  Convert a 2 digit decimal to BCD format.
  * @param  Value Byte to be converted
  * @retval Converted byte
  */
uint8_t RTC_ByteToBcd2(uint8_t Value)
{
 800229c:	b480      	push	{r7}
 800229e:	b085      	sub	sp, #20
 80022a0:	af00      	add	r7, sp, #0
 80022a2:	4603      	mov	r3, r0
 80022a4:	71fb      	strb	r3, [r7, #7]
  uint32_t bcdhigh = 0U;
 80022a6:	2300      	movs	r3, #0
 80022a8:	60fb      	str	r3, [r7, #12]
  uint8_t Param = Value;
 80022aa:	79fb      	ldrb	r3, [r7, #7]
 80022ac:	72fb      	strb	r3, [r7, #11]

  while (Param >= 10U)
 80022ae:	e005      	b.n	80022bc <RTC_ByteToBcd2+0x20>
  {
    bcdhigh++;
 80022b0:	68fb      	ldr	r3, [r7, #12]
 80022b2:	3301      	adds	r3, #1
 80022b4:	60fb      	str	r3, [r7, #12]
    Param -= 10U;
 80022b6:	7afb      	ldrb	r3, [r7, #11]
 80022b8:	3b0a      	subs	r3, #10
 80022ba:	72fb      	strb	r3, [r7, #11]
  while (Param >= 10U)
 80022bc:	7afb      	ldrb	r3, [r7, #11]
 80022be:	2b09      	cmp	r3, #9
 80022c0:	d8f6      	bhi.n	80022b0 <RTC_ByteToBcd2+0x14>
  }

  return ((uint8_t)(bcdhigh << 4U) | Param);
 80022c2:	68fb      	ldr	r3, [r7, #12]
 80022c4:	b2db      	uxtb	r3, r3
 80022c6:	011b      	lsls	r3, r3, #4
 80022c8:	b2da      	uxtb	r2, r3
 80022ca:	7afb      	ldrb	r3, [r7, #11]
 80022cc:	4313      	orrs	r3, r2
 80022ce:	b2db      	uxtb	r3, r3
}
 80022d0:	4618      	mov	r0, r3
 80022d2:	3714      	adds	r7, #20
 80022d4:	46bd      	mov	sp, r7
 80022d6:	bc80      	pop	{r7}
 80022d8:	4770      	bx	lr

080022da <RTC_Bcd2ToByte>:
  * @brief  Convert from 2 digit BCD to Binary.
  * @param  Value BCD value to be converted
  * @retval Converted word
  */
uint8_t RTC_Bcd2ToByte(uint8_t Value)
{
 80022da:	b480      	push	{r7}
 80022dc:	b085      	sub	sp, #20
 80022de:	af00      	add	r7, sp, #0
 80022e0:	4603      	mov	r3, r0
 80022e2:	71fb      	strb	r3, [r7, #7]
  uint32_t tmp;
  tmp = (((uint32_t)Value & 0xF0U) >> 4U) * 10U;
 80022e4:	79fb      	ldrb	r3, [r7, #7]
 80022e6:	091b      	lsrs	r3, r3, #4
 80022e8:	b2db      	uxtb	r3, r3
 80022ea:	461a      	mov	r2, r3
 80022ec:	4613      	mov	r3, r2
 80022ee:	009b      	lsls	r3, r3, #2
 80022f0:	4413      	add	r3, r2
 80022f2:	005b      	lsls	r3, r3, #1
 80022f4:	60fb      	str	r3, [r7, #12]
  return (uint8_t)(tmp + ((uint32_t)Value & 0x0FU));
 80022f6:	68fb      	ldr	r3, [r7, #12]
 80022f8:	b2da      	uxtb	r2, r3
 80022fa:	79fb      	ldrb	r3, [r7, #7]
 80022fc:	f003 030f 	and.w	r3, r3, #15
 8002300:	b2db      	uxtb	r3, r3
 8002302:	4413      	add	r3, r2
 8002304:	b2db      	uxtb	r3, r3
}
 8002306:	4618      	mov	r0, r3
 8002308:	3714      	adds	r7, #20
 800230a:	46bd      	mov	sp, r7
 800230c:	bc80      	pop	{r7}
 800230e:	4770      	bx	lr

08002310 <HAL_UART_Init>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8002310:	b580      	push	{r7, lr}
 8002312:	b082      	sub	sp, #8
 8002314:	af00      	add	r7, sp, #0
 8002316:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8002318:	687b      	ldr	r3, [r7, #4]
 800231a:	2b00      	cmp	r3, #0
 800231c:	d101      	bne.n	8002322 <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 800231e:	2301      	movs	r3, #1
 8002320:	e03f      	b.n	80023a2 <HAL_UART_Init+0x92>
    assert_param(IS_UART_INSTANCE(huart->Instance));
  }
  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));

  if (huart->gState == HAL_UART_STATE_RESET)
 8002322:	687b      	ldr	r3, [r7, #4]
 8002324:	f893 3039 	ldrb.w	r3, [r3, #57]	; 0x39
 8002328:	b2db      	uxtb	r3, r3
 800232a:	2b00      	cmp	r3, #0
 800232c:	d106      	bne.n	800233c <HAL_UART_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 800232e:	687b      	ldr	r3, [r7, #4]
 8002330:	2200      	movs	r2, #0
 8002332:	f883 2038 	strb.w	r2, [r3, #56]	; 0x38

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8002336:	6878      	ldr	r0, [r7, #4]
 8002338:	f7fe fa86 	bl	8000848 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 800233c:	687b      	ldr	r3, [r7, #4]
 800233e:	2224      	movs	r2, #36	; 0x24
 8002340:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39

  /* Disable the peripheral */
  __HAL_UART_DISABLE(huart);
 8002344:	687b      	ldr	r3, [r7, #4]
 8002346:	681b      	ldr	r3, [r3, #0]
 8002348:	68da      	ldr	r2, [r3, #12]
 800234a:	687b      	ldr	r3, [r7, #4]
 800234c:	681b      	ldr	r3, [r3, #0]
 800234e:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 8002352:	60da      	str	r2, [r3, #12]

  /* Set the UART Communication parameters */
  UART_SetConfig(huart);
 8002354:	6878      	ldr	r0, [r7, #4]
 8002356:	f000 f829 	bl	80023ac <UART_SetConfig>

  /* In asynchronous mode, the following bits must be kept cleared:
     - LINEN and CLKEN bits in the USART_CR2 register,
     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 800235a:	687b      	ldr	r3, [r7, #4]
 800235c:	681b      	ldr	r3, [r3, #0]
 800235e:	691a      	ldr	r2, [r3, #16]
 8002360:	687b      	ldr	r3, [r7, #4]
 8002362:	681b      	ldr	r3, [r3, #0]
 8002364:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8002368:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 800236a:	687b      	ldr	r3, [r7, #4]
 800236c:	681b      	ldr	r3, [r3, #0]
 800236e:	695a      	ldr	r2, [r3, #20]
 8002370:	687b      	ldr	r3, [r7, #4]
 8002372:	681b      	ldr	r3, [r3, #0]
 8002374:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8002378:	615a      	str	r2, [r3, #20]

  /* Enable the peripheral */
  __HAL_UART_ENABLE(huart);
 800237a:	687b      	ldr	r3, [r7, #4]
 800237c:	681b      	ldr	r3, [r3, #0]
 800237e:	68da      	ldr	r2, [r3, #12]
 8002380:	687b      	ldr	r3, [r7, #4]
 8002382:	681b      	ldr	r3, [r3, #0]
 8002384:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8002388:	60da      	str	r2, [r3, #12]

  /* Initialize the UART state */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 800238a:	687b      	ldr	r3, [r7, #4]
 800238c:	2200      	movs	r2, #0
 800238e:	63da      	str	r2, [r3, #60]	; 0x3c
  huart->gState = HAL_UART_STATE_READY;
 8002390:	687b      	ldr	r3, [r7, #4]
 8002392:	2220      	movs	r2, #32
 8002394:	f883 2039 	strb.w	r2, [r3, #57]	; 0x39
  huart->RxState = HAL_UART_STATE_READY;
 8002398:	687b      	ldr	r3, [r7, #4]
 800239a:	2220      	movs	r2, #32
 800239c:	f883 203a 	strb.w	r2, [r3, #58]	; 0x3a

  return HAL_OK;
 80023a0:	2300      	movs	r3, #0
}
 80023a2:	4618      	mov	r0, r3
 80023a4:	3708      	adds	r7, #8
 80023a6:	46bd      	mov	sp, r7
 80023a8:	bd80      	pop	{r7, pc}
	...

080023ac <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 80023ac:	b580      	push	{r7, lr}
 80023ae:	b084      	sub	sp, #16
 80023b0:	af00      	add	r7, sp, #0
 80023b2:	6078      	str	r0, [r7, #4]
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 80023b4:	687b      	ldr	r3, [r7, #4]
 80023b6:	681b      	ldr	r3, [r3, #0]
 80023b8:	691b      	ldr	r3, [r3, #16]
 80023ba:	f423 5140 	bic.w	r1, r3, #12288	; 0x3000
 80023be:	687b      	ldr	r3, [r7, #4]
 80023c0:	68da      	ldr	r2, [r3, #12]
 80023c2:	687b      	ldr	r3, [r7, #4]
 80023c4:	681b      	ldr	r3, [r3, #0]
 80023c6:	430a      	orrs	r2, r1
 80023c8:	611a      	str	r2, [r3, #16]
     Set the M bits according to huart->Init.WordLength value
     Set PCE and PS bits according to huart->Init.Parity value
     Set TE and RE bits according to huart->Init.Mode value
     Set OVER8 bit according to huart->Init.OverSampling value */

  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
 80023ca:	687b      	ldr	r3, [r7, #4]
 80023cc:	689a      	ldr	r2, [r3, #8]
 80023ce:	687b      	ldr	r3, [r7, #4]
 80023d0:	691b      	ldr	r3, [r3, #16]
 80023d2:	431a      	orrs	r2, r3
 80023d4:	687b      	ldr	r3, [r7, #4]
 80023d6:	695b      	ldr	r3, [r3, #20]
 80023d8:	431a      	orrs	r2, r3
 80023da:	687b      	ldr	r3, [r7, #4]
 80023dc:	69db      	ldr	r3, [r3, #28]
 80023de:	4313      	orrs	r3, r2
 80023e0:	60bb      	str	r3, [r7, #8]
  MODIFY_REG(huart->Instance->CR1,
 80023e2:	687b      	ldr	r3, [r7, #4]
 80023e4:	681b      	ldr	r3, [r3, #0]
 80023e6:	68db      	ldr	r3, [r3, #12]
 80023e8:	f423 4316 	bic.w	r3, r3, #38400	; 0x9600
 80023ec:	f023 030c 	bic.w	r3, r3, #12
 80023f0:	687a      	ldr	r2, [r7, #4]
 80023f2:	6812      	ldr	r2, [r2, #0]
 80023f4:	68b9      	ldr	r1, [r7, #8]
 80023f6:	430b      	orrs	r3, r1
 80023f8:	60d3      	str	r3, [r2, #12]
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 80023fa:	687b      	ldr	r3, [r7, #4]
 80023fc:	681b      	ldr	r3, [r3, #0]
 80023fe:	695b      	ldr	r3, [r3, #20]
 8002400:	f423 7140 	bic.w	r1, r3, #768	; 0x300
 8002404:	687b      	ldr	r3, [r7, #4]
 8002406:	699a      	ldr	r2, [r3, #24]
 8002408:	687b      	ldr	r3, [r7, #4]
 800240a:	681b      	ldr	r3, [r3, #0]
 800240c:	430a      	orrs	r2, r1
 800240e:	615a      	str	r2, [r3, #20]


  if((huart->Instance == USART1))
 8002410:	687b      	ldr	r3, [r7, #4]
 8002412:	681b      	ldr	r3, [r3, #0]
 8002414:	4a55      	ldr	r2, [pc, #340]	; (800256c <UART_SetConfig+0x1c0>)
 8002416:	4293      	cmp	r3, r2
 8002418:	d103      	bne.n	8002422 <UART_SetConfig+0x76>
  {
    pclk = HAL_RCC_GetPCLK2Freq();
 800241a:	f7ff fb1b 	bl	8001a54 <HAL_RCC_GetPCLK2Freq>
 800241e:	60f8      	str	r0, [r7, #12]
 8002420:	e002      	b.n	8002428 <UART_SetConfig+0x7c>
  }
  else
  {
    pclk = HAL_RCC_GetPCLK1Freq();
 8002422:	f7ff fb03 	bl	8001a2c <HAL_RCC_GetPCLK1Freq>
 8002426:	60f8      	str	r0, [r7, #12]
  }

  /*-------------------------- USART BRR Configuration ---------------------*/
  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8002428:	687b      	ldr	r3, [r7, #4]
 800242a:	69db      	ldr	r3, [r3, #28]
 800242c:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 8002430:	d14c      	bne.n	80024cc <UART_SetConfig+0x120>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8002432:	68fa      	ldr	r2, [r7, #12]
 8002434:	4613      	mov	r3, r2
 8002436:	009b      	lsls	r3, r3, #2
 8002438:	4413      	add	r3, r2
 800243a:	009a      	lsls	r2, r3, #2
 800243c:	441a      	add	r2, r3
 800243e:	687b      	ldr	r3, [r7, #4]
 8002440:	685b      	ldr	r3, [r3, #4]
 8002442:	005b      	lsls	r3, r3, #1
 8002444:	fbb2 f3f3 	udiv	r3, r2, r3
 8002448:	4a49      	ldr	r2, [pc, #292]	; (8002570 <UART_SetConfig+0x1c4>)
 800244a:	fba2 2303 	umull	r2, r3, r2, r3
 800244e:	095b      	lsrs	r3, r3, #5
 8002450:	0119      	lsls	r1, r3, #4
 8002452:	68fa      	ldr	r2, [r7, #12]
 8002454:	4613      	mov	r3, r2
 8002456:	009b      	lsls	r3, r3, #2
 8002458:	4413      	add	r3, r2
 800245a:	009a      	lsls	r2, r3, #2
 800245c:	441a      	add	r2, r3
 800245e:	687b      	ldr	r3, [r7, #4]
 8002460:	685b      	ldr	r3, [r3, #4]
 8002462:	005b      	lsls	r3, r3, #1
 8002464:	fbb2 f2f3 	udiv	r2, r2, r3
 8002468:	4b41      	ldr	r3, [pc, #260]	; (8002570 <UART_SetConfig+0x1c4>)
 800246a:	fba3 0302 	umull	r0, r3, r3, r2
 800246e:	095b      	lsrs	r3, r3, #5
 8002470:	2064      	movs	r0, #100	; 0x64
 8002472:	fb00 f303 	mul.w	r3, r0, r3
 8002476:	1ad3      	subs	r3, r2, r3
 8002478:	00db      	lsls	r3, r3, #3
 800247a:	3332      	adds	r3, #50	; 0x32
 800247c:	4a3c      	ldr	r2, [pc, #240]	; (8002570 <UART_SetConfig+0x1c4>)
 800247e:	fba2 2303 	umull	r2, r3, r2, r3
 8002482:	095b      	lsrs	r3, r3, #5
 8002484:	005b      	lsls	r3, r3, #1
 8002486:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 800248a:	4419      	add	r1, r3
 800248c:	68fa      	ldr	r2, [r7, #12]
 800248e:	4613      	mov	r3, r2
 8002490:	009b      	lsls	r3, r3, #2
 8002492:	4413      	add	r3, r2
 8002494:	009a      	lsls	r2, r3, #2
 8002496:	441a      	add	r2, r3
 8002498:	687b      	ldr	r3, [r7, #4]
 800249a:	685b      	ldr	r3, [r3, #4]
 800249c:	005b      	lsls	r3, r3, #1
 800249e:	fbb2 f2f3 	udiv	r2, r2, r3
 80024a2:	4b33      	ldr	r3, [pc, #204]	; (8002570 <UART_SetConfig+0x1c4>)
 80024a4:	fba3 0302 	umull	r0, r3, r3, r2
 80024a8:	095b      	lsrs	r3, r3, #5
 80024aa:	2064      	movs	r0, #100	; 0x64
 80024ac:	fb00 f303 	mul.w	r3, r0, r3
 80024b0:	1ad3      	subs	r3, r2, r3
 80024b2:	00db      	lsls	r3, r3, #3
 80024b4:	3332      	adds	r3, #50	; 0x32
 80024b6:	4a2e      	ldr	r2, [pc, #184]	; (8002570 <UART_SetConfig+0x1c4>)
 80024b8:	fba2 2303 	umull	r2, r3, r2, r3
 80024bc:	095b      	lsrs	r3, r3, #5
 80024be:	f003 0207 	and.w	r2, r3, #7
 80024c2:	687b      	ldr	r3, [r7, #4]
 80024c4:	681b      	ldr	r3, [r3, #0]
 80024c6:	440a      	add	r2, r1
 80024c8:	609a      	str	r2, [r3, #8]
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
}
 80024ca:	e04a      	b.n	8002562 <UART_SetConfig+0x1b6>
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 80024cc:	68fa      	ldr	r2, [r7, #12]
 80024ce:	4613      	mov	r3, r2
 80024d0:	009b      	lsls	r3, r3, #2
 80024d2:	4413      	add	r3, r2
 80024d4:	009a      	lsls	r2, r3, #2
 80024d6:	441a      	add	r2, r3
 80024d8:	687b      	ldr	r3, [r7, #4]
 80024da:	685b      	ldr	r3, [r3, #4]
 80024dc:	009b      	lsls	r3, r3, #2
 80024de:	fbb2 f3f3 	udiv	r3, r2, r3
 80024e2:	4a23      	ldr	r2, [pc, #140]	; (8002570 <UART_SetConfig+0x1c4>)
 80024e4:	fba2 2303 	umull	r2, r3, r2, r3
 80024e8:	095b      	lsrs	r3, r3, #5
 80024ea:	0119      	lsls	r1, r3, #4
 80024ec:	68fa      	ldr	r2, [r7, #12]
 80024ee:	4613      	mov	r3, r2
 80024f0:	009b      	lsls	r3, r3, #2
 80024f2:	4413      	add	r3, r2
 80024f4:	009a      	lsls	r2, r3, #2
 80024f6:	441a      	add	r2, r3
 80024f8:	687b      	ldr	r3, [r7, #4]
 80024fa:	685b      	ldr	r3, [r3, #4]
 80024fc:	009b      	lsls	r3, r3, #2
 80024fe:	fbb2 f2f3 	udiv	r2, r2, r3
 8002502:	4b1b      	ldr	r3, [pc, #108]	; (8002570 <UART_SetConfig+0x1c4>)
 8002504:	fba3 0302 	umull	r0, r3, r3, r2
 8002508:	095b      	lsrs	r3, r3, #5
 800250a:	2064      	movs	r0, #100	; 0x64
 800250c:	fb00 f303 	mul.w	r3, r0, r3
 8002510:	1ad3      	subs	r3, r2, r3
 8002512:	011b      	lsls	r3, r3, #4
 8002514:	3332      	adds	r3, #50	; 0x32
 8002516:	4a16      	ldr	r2, [pc, #88]	; (8002570 <UART_SetConfig+0x1c4>)
 8002518:	fba2 2303 	umull	r2, r3, r2, r3
 800251c:	095b      	lsrs	r3, r3, #5
 800251e:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8002522:	4419      	add	r1, r3
 8002524:	68fa      	ldr	r2, [r7, #12]
 8002526:	4613      	mov	r3, r2
 8002528:	009b      	lsls	r3, r3, #2
 800252a:	4413      	add	r3, r2
 800252c:	009a      	lsls	r2, r3, #2
 800252e:	441a      	add	r2, r3
 8002530:	687b      	ldr	r3, [r7, #4]
 8002532:	685b      	ldr	r3, [r3, #4]
 8002534:	009b      	lsls	r3, r3, #2
 8002536:	fbb2 f2f3 	udiv	r2, r2, r3
 800253a:	4b0d      	ldr	r3, [pc, #52]	; (8002570 <UART_SetConfig+0x1c4>)
 800253c:	fba3 0302 	umull	r0, r3, r3, r2
 8002540:	095b      	lsrs	r3, r3, #5
 8002542:	2064      	movs	r0, #100	; 0x64
 8002544:	fb00 f303 	mul.w	r3, r0, r3
 8002548:	1ad3      	subs	r3, r2, r3
 800254a:	011b      	lsls	r3, r3, #4
 800254c:	3332      	adds	r3, #50	; 0x32
 800254e:	4a08      	ldr	r2, [pc, #32]	; (8002570 <UART_SetConfig+0x1c4>)
 8002550:	fba2 2303 	umull	r2, r3, r2, r3
 8002554:	095b      	lsrs	r3, r3, #5
 8002556:	f003 020f 	and.w	r2, r3, #15
 800255a:	687b      	ldr	r3, [r7, #4]
 800255c:	681b      	ldr	r3, [r3, #0]
 800255e:	440a      	add	r2, r1
 8002560:	609a      	str	r2, [r3, #8]
}
 8002562:	bf00      	nop
 8002564:	3710      	adds	r7, #16
 8002566:	46bd      	mov	sp, r7
 8002568:	bd80      	pop	{r7, pc}
 800256a:	bf00      	nop
 800256c:	40013800 	.word	0x40013800
 8002570:	51eb851f 	.word	0x51eb851f

08002574 <__libc_init_array>:
 8002574:	b570      	push	{r4, r5, r6, lr}
 8002576:	2500      	movs	r5, #0
 8002578:	4e0c      	ldr	r6, [pc, #48]	; (80025ac <__libc_init_array+0x38>)
 800257a:	4c0d      	ldr	r4, [pc, #52]	; (80025b0 <__libc_init_array+0x3c>)
 800257c:	1ba4      	subs	r4, r4, r6
 800257e:	10a4      	asrs	r4, r4, #2
 8002580:	42a5      	cmp	r5, r4
 8002582:	d109      	bne.n	8002598 <__libc_init_array+0x24>
 8002584:	f000 f822 	bl	80025cc <_init>
 8002588:	2500      	movs	r5, #0
 800258a:	4e0a      	ldr	r6, [pc, #40]	; (80025b4 <__libc_init_array+0x40>)
 800258c:	4c0a      	ldr	r4, [pc, #40]	; (80025b8 <__libc_init_array+0x44>)
 800258e:	1ba4      	subs	r4, r4, r6
 8002590:	10a4      	asrs	r4, r4, #2
 8002592:	42a5      	cmp	r5, r4
 8002594:	d105      	bne.n	80025a2 <__libc_init_array+0x2e>
 8002596:	bd70      	pop	{r4, r5, r6, pc}
 8002598:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 800259c:	4798      	blx	r3
 800259e:	3501      	adds	r5, #1
 80025a0:	e7ee      	b.n	8002580 <__libc_init_array+0xc>
 80025a2:	f856 3025 	ldr.w	r3, [r6, r5, lsl #2]
 80025a6:	4798      	blx	r3
 80025a8:	3501      	adds	r5, #1
 80025aa:	e7f2      	b.n	8002592 <__libc_init_array+0x1e>
 80025ac:	08002610 	.word	0x08002610
 80025b0:	08002610 	.word	0x08002610
 80025b4:	08002610 	.word	0x08002610
 80025b8:	08002614 	.word	0x08002614

080025bc <memset>:
 80025bc:	4603      	mov	r3, r0
 80025be:	4402      	add	r2, r0
 80025c0:	4293      	cmp	r3, r2
 80025c2:	d100      	bne.n	80025c6 <memset+0xa>
 80025c4:	4770      	bx	lr
 80025c6:	f803 1b01 	strb.w	r1, [r3], #1
 80025ca:	e7f9      	b.n	80025c0 <memset+0x4>

080025cc <_init>:
 80025cc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80025ce:	bf00      	nop
 80025d0:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80025d2:	bc08      	pop	{r3}
 80025d4:	469e      	mov	lr, r3
 80025d6:	4770      	bx	lr

080025d8 <_fini>:
 80025d8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 80025da:	bf00      	nop
 80025dc:	bcf8      	pop	{r3, r4, r5, r6, r7}
 80025de:	bc08      	pop	{r3}
 80025e0:	469e      	mov	lr, r3
 80025e2:	4770      	bx	lr