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stm32f4xx_hal_pwr.c 19KB

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  1. /**
  2. ******************************************************************************
  3. * @file stm32f4xx_hal_pwr.c
  4. * @author MCD Application Team
  5. * @brief PWR HAL module driver.
  6. * This file provides firmware functions to manage the following
  7. * functionalities of the Power Controller (PWR) peripheral:
  8. * + Initialization and de-initialization functions
  9. * + Peripheral Control functions
  10. *
  11. ******************************************************************************
  12. * @attention
  13. *
  14. * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  15. * All rights reserved.</center></h2>
  16. *
  17. * This software component is licensed by ST under BSD 3-Clause license,
  18. * the "License"; You may not use this file except in compliance with the
  19. * License. You may obtain a copy of the License at:
  20. * opensource.org/licenses/BSD-3-Clause
  21. *
  22. ******************************************************************************
  23. */
  24. /* Includes ------------------------------------------------------------------*/
  25. #include "stm32f4xx_hal.h"
  26. /** @addtogroup STM32F4xx_HAL_Driver
  27. * @{
  28. */
  29. /** @defgroup PWR PWR
  30. * @brief PWR HAL module driver
  31. * @{
  32. */
  33. #ifdef HAL_PWR_MODULE_ENABLED
  34. /* Private typedef -----------------------------------------------------------*/
  35. /* Private define ------------------------------------------------------------*/
  36. /** @addtogroup PWR_Private_Constants
  37. * @{
  38. */
  39. /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
  40. * @{
  41. */
  42. #define PVD_MODE_IT 0x00010000U
  43. #define PVD_MODE_EVT 0x00020000U
  44. #define PVD_RISING_EDGE 0x00000001U
  45. #define PVD_FALLING_EDGE 0x00000002U
  46. /**
  47. * @}
  48. */
  49. /**
  50. * @}
  51. */
  52. /* Private macro -------------------------------------------------------------*/
  53. /* Private variables ---------------------------------------------------------*/
  54. /* Private function prototypes -----------------------------------------------*/
  55. /* Private functions ---------------------------------------------------------*/
  56. /** @defgroup PWR_Exported_Functions PWR Exported Functions
  57. * @{
  58. */
  59. /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
  60. * @brief Initialization and de-initialization functions
  61. *
  62. @verbatim
  63. ===============================================================================
  64. ##### Initialization and de-initialization functions #####
  65. ===============================================================================
  66. [..]
  67. After reset, the backup domain (RTC registers, RTC backup data
  68. registers and backup SRAM) is protected against possible unwanted
  69. write accesses.
  70. To enable access to the RTC Domain and RTC registers, proceed as follows:
  71. (+) Enable the Power Controller (PWR) APB1 interface clock using the
  72. __HAL_RCC_PWR_CLK_ENABLE() macro.
  73. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
  74. @endverbatim
  75. * @{
  76. */
  77. /**
  78. * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
  79. * @retval None
  80. */
  81. void HAL_PWR_DeInit(void)
  82. {
  83. __HAL_RCC_PWR_FORCE_RESET();
  84. __HAL_RCC_PWR_RELEASE_RESET();
  85. }
  86. /**
  87. * @brief Enables access to the backup domain (RTC registers, RTC
  88. * backup data registers and backup SRAM).
  89. * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
  90. * Backup Domain Access should be kept enabled.
  91. * @retval None
  92. */
  93. void HAL_PWR_EnableBkUpAccess(void)
  94. {
  95. *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
  96. }
  97. /**
  98. * @brief Disables access to the backup domain (RTC registers, RTC
  99. * backup data registers and backup SRAM).
  100. * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
  101. * Backup Domain Access should be kept enabled.
  102. * @retval None
  103. */
  104. void HAL_PWR_DisableBkUpAccess(void)
  105. {
  106. *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
  107. }
  108. /**
  109. * @}
  110. */
  111. /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
  112. * @brief Low Power modes configuration functions
  113. *
  114. @verbatim
  115. ===============================================================================
  116. ##### Peripheral Control functions #####
  117. ===============================================================================
  118. *** PVD configuration ***
  119. =========================
  120. [..]
  121. (+) The PVD is used to monitor the VDD power supply by comparing it to a
  122. threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
  123. (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
  124. than the PVD threshold. This event is internally connected to the EXTI
  125. line16 and can generate an interrupt if enabled. This is done through
  126. __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
  127. (+) The PVD is stopped in Standby mode.
  128. *** Wake-up pin configuration ***
  129. ================================
  130. [..]
  131. (+) Wake-up pin is used to wake up the system from Standby mode. This pin is
  132. forced in input pull-down configuration and is active on rising edges.
  133. (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
  134. (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
  135. (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
  136. *** Low Power modes configuration ***
  137. =====================================
  138. [..]
  139. The devices feature 3 low-power modes:
  140. (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
  141. (+) Stop mode: all clocks are stopped, regulator running, regulator
  142. in low power mode
  143. (+) Standby mode: 1.2V domain powered off.
  144. *** Sleep mode ***
  145. ==================
  146. [..]
  147. (+) Entry:
  148. The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
  149. functions with
  150. (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  151. (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  152. -@@- The Regulator parameter is not used for the STM32F4 family
  153. and is kept as parameter just to maintain compatibility with the
  154. lower power families (STM32L).
  155. (+) Exit:
  156. Any peripheral interrupt acknowledged by the nested vectored interrupt
  157. controller (NVIC) can wake up the device from Sleep mode.
  158. *** Stop mode ***
  159. =================
  160. [..]
  161. In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
  162. and the HSE RC oscillators are disabled. Internal SRAM and register contents
  163. are preserved.
  164. The voltage regulator can be configured either in normal or low-power mode.
  165. To minimize the consumption In Stop mode, FLASH can be powered off before
  166. entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
  167. It can be switched on again by software after exiting the Stop mode using
  168. the HAL_PWREx_DisableFlashPowerDown() function.
  169. (+) Entry:
  170. The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
  171. function with:
  172. (++) Main regulator ON.
  173. (++) Low Power regulator ON.
  174. (+) Exit:
  175. Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
  176. *** Standby mode ***
  177. ====================
  178. [..]
  179. (+)
  180. The Standby mode allows to achieve the lowest power consumption. It is based
  181. on the Cortex-M4 deep sleep mode, with the voltage regulator disabled.
  182. The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
  183. the HSE oscillator are also switched off. SRAM and register contents are lost
  184. except for the RTC registers, RTC backup registers, backup SRAM and Standby
  185. circuitry.
  186. The voltage regulator is OFF.
  187. (++) Entry:
  188. (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
  189. (++) Exit:
  190. (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
  191. tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
  192. *** Auto-wake-up (AWU) from low-power mode ***
  193. =============================================
  194. [..]
  195. (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
  196. Wake-up event, a tamper event or a time-stamp event, without depending on
  197. an external interrupt (Auto-wake-up mode).
  198. (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
  199. (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
  200. configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
  201. (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
  202. is necessary to configure the RTC to detect the tamper or time stamp event using the
  203. HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
  204. (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
  205. configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
  206. @endverbatim
  207. * @{
  208. */
  209. /**
  210. * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
  211. * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
  212. * information for the PVD.
  213. * @note Refer to the electrical characteristics of your device datasheet for
  214. * more details about the voltage threshold corresponding to each
  215. * detection level.
  216. * @retval None
  217. */
  218. void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
  219. {
  220. /* Check the parameters */
  221. assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
  222. assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
  223. /* Set PLS[7:5] bits according to PVDLevel value */
  224. MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
  225. /* Clear any previous config. Keep it clear if no event or IT mode is selected */
  226. __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
  227. __HAL_PWR_PVD_EXTI_DISABLE_IT();
  228. __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
  229. __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
  230. /* Configure interrupt mode */
  231. if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
  232. {
  233. __HAL_PWR_PVD_EXTI_ENABLE_IT();
  234. }
  235. /* Configure event mode */
  236. if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
  237. {
  238. __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
  239. }
  240. /* Configure the edge */
  241. if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
  242. {
  243. __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
  244. }
  245. if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
  246. {
  247. __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
  248. }
  249. }
  250. /**
  251. * @brief Enables the Power Voltage Detector(PVD).
  252. * @retval None
  253. */
  254. void HAL_PWR_EnablePVD(void)
  255. {
  256. *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
  257. }
  258. /**
  259. * @brief Disables the Power Voltage Detector(PVD).
  260. * @retval None
  261. */
  262. void HAL_PWR_DisablePVD(void)
  263. {
  264. *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
  265. }
  266. /**
  267. * @brief Enables the Wake-up PINx functionality.
  268. * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
  269. * This parameter can be one of the following values:
  270. * @arg PWR_WAKEUP_PIN1
  271. * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
  272. * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
  273. * @retval None
  274. */
  275. void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
  276. {
  277. /* Check the parameter */
  278. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  279. /* Enable the wake up pin */
  280. SET_BIT(PWR->CSR, WakeUpPinx);
  281. }
  282. /**
  283. * @brief Disables the Wake-up PINx functionality.
  284. * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
  285. * This parameter can be one of the following values:
  286. * @arg PWR_WAKEUP_PIN1
  287. * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
  288. * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
  289. * @retval None
  290. */
  291. void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
  292. {
  293. /* Check the parameter */
  294. assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
  295. /* Disable the wake up pin */
  296. CLEAR_BIT(PWR->CSR, WakeUpPinx);
  297. }
  298. /**
  299. * @brief Enters Sleep mode.
  300. *
  301. * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
  302. *
  303. * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
  304. * systick interrupt when used as time base for Timeout
  305. *
  306. * @param Regulator Specifies the regulator state in SLEEP mode.
  307. * This parameter can be one of the following values:
  308. * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
  309. * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
  310. * @note This parameter is not used for the STM32F4 family and is kept as parameter
  311. * just to maintain compatibility with the lower power families.
  312. * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
  313. * This parameter can be one of the following values:
  314. * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
  315. * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
  316. * @retval None
  317. */
  318. void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
  319. {
  320. /* Check the parameters */
  321. assert_param(IS_PWR_REGULATOR(Regulator));
  322. assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
  323. /* Clear SLEEPDEEP bit of Cortex System Control Register */
  324. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  325. /* Select SLEEP mode entry -------------------------------------------------*/
  326. if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
  327. {
  328. /* Request Wait For Interrupt */
  329. __WFI();
  330. }
  331. else
  332. {
  333. /* Request Wait For Event */
  334. __SEV();
  335. __WFE();
  336. __WFE();
  337. }
  338. }
  339. /**
  340. * @brief Enters Stop mode.
  341. * @note In Stop mode, all I/O pins keep the same state as in Run mode.
  342. * @note When exiting Stop mode by issuing an interrupt or a wake-up event,
  343. * the HSI RC oscillator is selected as system clock.
  344. * @note When the voltage regulator operates in low power mode, an additional
  345. * startup delay is incurred when waking up from Stop mode.
  346. * By keeping the internal regulator ON during Stop mode, the consumption
  347. * is higher although the startup time is reduced.
  348. * @param Regulator Specifies the regulator state in Stop mode.
  349. * This parameter can be one of the following values:
  350. * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  351. * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
  352. * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
  353. * This parameter can be one of the following values:
  354. * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
  355. * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
  356. * @retval None
  357. */
  358. void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
  359. {
  360. /* Check the parameters */
  361. assert_param(IS_PWR_REGULATOR(Regulator));
  362. assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
  363. /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
  364. MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
  365. /* Set SLEEPDEEP bit of Cortex System Control Register */
  366. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  367. /* Select Stop mode entry --------------------------------------------------*/
  368. if(STOPEntry == PWR_STOPENTRY_WFI)
  369. {
  370. /* Request Wait For Interrupt */
  371. __WFI();
  372. }
  373. else
  374. {
  375. /* Request Wait For Event */
  376. __SEV();
  377. __WFE();
  378. __WFE();
  379. }
  380. /* Reset SLEEPDEEP bit of Cortex System Control Register */
  381. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  382. }
  383. /**
  384. * @brief Enters Standby mode.
  385. * @note In Standby mode, all I/O pins are high impedance except for:
  386. * - Reset pad (still available)
  387. * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
  388. * Alarm out, or RTC clock calibration out.
  389. * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
  390. * - WKUP pin 1 (PA0) if enabled.
  391. * @retval None
  392. */
  393. void HAL_PWR_EnterSTANDBYMode(void)
  394. {
  395. /* Select Standby mode */
  396. SET_BIT(PWR->CR, PWR_CR_PDDS);
  397. /* Set SLEEPDEEP bit of Cortex System Control Register */
  398. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
  399. /* This option is used to ensure that store operations are completed */
  400. #if defined ( __CC_ARM)
  401. __force_stores();
  402. #endif
  403. /* Request Wait For Interrupt */
  404. __WFI();
  405. }
  406. /**
  407. * @brief This function handles the PWR PVD interrupt request.
  408. * @note This API should be called under the PVD_IRQHandler().
  409. * @retval None
  410. */
  411. void HAL_PWR_PVD_IRQHandler(void)
  412. {
  413. /* Check PWR Exti flag */
  414. if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
  415. {
  416. /* PWR PVD interrupt user callback */
  417. HAL_PWR_PVDCallback();
  418. /* Clear PWR Exti pending bit */
  419. __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
  420. }
  421. }
  422. /**
  423. * @brief PWR PVD interrupt callback
  424. * @retval None
  425. */
  426. __weak void HAL_PWR_PVDCallback(void)
  427. {
  428. /* NOTE : This function Should not be modified, when the callback is needed,
  429. the HAL_PWR_PVDCallback could be implemented in the user file
  430. */
  431. }
  432. /**
  433. * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
  434. * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  435. * re-enters SLEEP mode when an interruption handling is over.
  436. * Setting this bit is useful when the processor is expected to run only on
  437. * interruptions handling.
  438. * @retval None
  439. */
  440. void HAL_PWR_EnableSleepOnExit(void)
  441. {
  442. /* Set SLEEPONEXIT bit of Cortex System Control Register */
  443. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  444. }
  445. /**
  446. * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
  447. * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
  448. * re-enters SLEEP mode when an interruption handling is over.
  449. * @retval None
  450. */
  451. void HAL_PWR_DisableSleepOnExit(void)
  452. {
  453. /* Clear SLEEPONEXIT bit of Cortex System Control Register */
  454. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
  455. }
  456. /**
  457. * @brief Enables CORTEX M4 SEVONPEND bit.
  458. * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
  459. * WFE to wake up when an interrupt moves from inactive to pended.
  460. * @retval None
  461. */
  462. void HAL_PWR_EnableSEVOnPend(void)
  463. {
  464. /* Set SEVONPEND bit of Cortex System Control Register */
  465. SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  466. }
  467. /**
  468. * @brief Disables CORTEX M4 SEVONPEND bit.
  469. * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
  470. * WFE to wake up when an interrupt moves from inactive to pended.
  471. * @retval None
  472. */
  473. void HAL_PWR_DisableSEVOnPend(void)
  474. {
  475. /* Clear SEVONPEND bit of Cortex System Control Register */
  476. CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
  477. }
  478. /**
  479. * @}
  480. */
  481. /**
  482. * @}
  483. */
  484. #endif /* HAL_PWR_MODULE_ENABLED */
  485. /**
  486. * @}
  487. */
  488. /**
  489. * @}
  490. */
  491. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/