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  1. SD_CARD_SPI.elf: file format elf32-littlearm
  2. Sections:
  3. Idx Name Size VMA LMA File off Algn
  4. 0 .isr_vector 0000013c 08000000 08000000 00010000 2**0
  5. CONTENTS, ALLOC, LOAD, READONLY, DATA
  6. 1 .text 00007914 0800013c 0800013c 0001013c 2**2
  7. CONTENTS, ALLOC, LOAD, READONLY, CODE
  8. 2 .rodata 000005a8 08007a50 08007a50 00017a50 2**2
  9. CONTENTS, ALLOC, LOAD, READONLY, DATA
  10. 3 .ARM.extab 00000000 08007ff8 08007ff8 00020088 2**0
  11. CONTENTS
  12. 4 .ARM 00000008 08007ff8 08007ff8 00017ff8 2**2
  13. CONTENTS, ALLOC, LOAD, READONLY, DATA
  14. 5 .preinit_array 00000000 08008000 08008000 00020088 2**0
  15. CONTENTS, ALLOC, LOAD, DATA
  16. 6 .init_array 00000004 08008000 08008000 00018000 2**2
  17. CONTENTS, ALLOC, LOAD, DATA
  18. 7 .fini_array 00000004 08008004 08008004 00018004 2**2
  19. CONTENTS, ALLOC, LOAD, DATA
  20. 8 .data 00000088 20000000 08008008 00020000 2**2
  21. CONTENTS, ALLOC, LOAD, DATA
  22. 9 .bss 000044cc 20000088 08008090 00020088 2**2
  23. ALLOC
  24. 10 ._user_heap_stack 00000604 20004554 08008090 00024554 2**0
  25. ALLOC
  26. 11 .ARM.attributes 00000029 00000000 00000000 00020088 2**0
  27. CONTENTS, READONLY
  28. 12 .debug_info 000113b4 00000000 00000000 000200b1 2**0
  29. CONTENTS, READONLY, DEBUGGING
  30. 13 .debug_abbrev 00002754 00000000 00000000 00031465 2**0
  31. CONTENTS, READONLY, DEBUGGING
  32. 14 .debug_aranges 00000cd8 00000000 00000000 00033bc0 2**3
  33. CONTENTS, READONLY, DEBUGGING
  34. 15 .debug_ranges 00000ba0 00000000 00000000 00034898 2**3
  35. CONTENTS, READONLY, DEBUGGING
  36. 16 .debug_macro 0001807c 00000000 00000000 00035438 2**0
  37. CONTENTS, READONLY, DEBUGGING
  38. 17 .debug_line 0000cbe7 00000000 00000000 0004d4b4 2**0
  39. CONTENTS, READONLY, DEBUGGING
  40. 18 .debug_str 0008e5ed 00000000 00000000 0005a09b 2**0
  41. CONTENTS, READONLY, DEBUGGING
  42. 19 .comment 0000007b 00000000 00000000 000e8688 2**0
  43. CONTENTS, READONLY
  44. 20 .debug_frame 0000375c 00000000 00000000 000e8704 2**2
  45. CONTENTS, READONLY, DEBUGGING
  46. Disassembly of section .text:
  47. 0800013c <__do_global_dtors_aux>:
  48. 800013c: b510 push {r4, lr}
  49. 800013e: 4c05 ldr r4, [pc, #20] ; (8000154 <__do_global_dtors_aux+0x18>)
  50. 8000140: 7823 ldrb r3, [r4, #0]
  51. 8000142: b933 cbnz r3, 8000152 <__do_global_dtors_aux+0x16>
  52. 8000144: 4b04 ldr r3, [pc, #16] ; (8000158 <__do_global_dtors_aux+0x1c>)
  53. 8000146: b113 cbz r3, 800014e <__do_global_dtors_aux+0x12>
  54. 8000148: 4804 ldr r0, [pc, #16] ; (800015c <__do_global_dtors_aux+0x20>)
  55. 800014a: f3af 8000 nop.w
  56. 800014e: 2301 movs r3, #1
  57. 8000150: 7023 strb r3, [r4, #0]
  58. 8000152: bd10 pop {r4, pc}
  59. 8000154: 20000088 .word 0x20000088
  60. 8000158: 00000000 .word 0x00000000
  61. 800015c: 08007a38 .word 0x08007a38
  62. 08000160 <frame_dummy>:
  63. 8000160: b508 push {r3, lr}
  64. 8000162: 4b03 ldr r3, [pc, #12] ; (8000170 <frame_dummy+0x10>)
  65. 8000164: b11b cbz r3, 800016e <frame_dummy+0xe>
  66. 8000166: 4903 ldr r1, [pc, #12] ; (8000174 <frame_dummy+0x14>)
  67. 8000168: 4803 ldr r0, [pc, #12] ; (8000178 <frame_dummy+0x18>)
  68. 800016a: f3af 8000 nop.w
  69. 800016e: bd08 pop {r3, pc}
  70. 8000170: 00000000 .word 0x00000000
  71. 8000174: 2000008c .word 0x2000008c
  72. 8000178: 08007a38 .word 0x08007a38
  73. 0800017c <strlen>:
  74. 800017c: 4603 mov r3, r0
  75. 800017e: f813 2b01 ldrb.w r2, [r3], #1
  76. 8000182: 2a00 cmp r2, #0
  77. 8000184: d1fb bne.n 800017e <strlen+0x2>
  78. 8000186: 1a18 subs r0, r3, r0
  79. 8000188: 3801 subs r0, #1
  80. 800018a: 4770 bx lr
  81. 0800018c <__aeabi_uldivmod>:
  82. 800018c: b953 cbnz r3, 80001a4 <__aeabi_uldivmod+0x18>
  83. 800018e: b94a cbnz r2, 80001a4 <__aeabi_uldivmod+0x18>
  84. 8000190: 2900 cmp r1, #0
  85. 8000192: bf08 it eq
  86. 8000194: 2800 cmpeq r0, #0
  87. 8000196: bf1c itt ne
  88. 8000198: f04f 31ff movne.w r1, #4294967295
  89. 800019c: f04f 30ff movne.w r0, #4294967295
  90. 80001a0: f000 b974 b.w 800048c <__aeabi_idiv0>
  91. 80001a4: f1ad 0c08 sub.w ip, sp, #8
  92. 80001a8: e96d ce04 strd ip, lr, [sp, #-16]!
  93. 80001ac: f000 f806 bl 80001bc <__udivmoddi4>
  94. 80001b0: f8dd e004 ldr.w lr, [sp, #4]
  95. 80001b4: e9dd 2302 ldrd r2, r3, [sp, #8]
  96. 80001b8: b004 add sp, #16
  97. 80001ba: 4770 bx lr
  98. 080001bc <__udivmoddi4>:
  99. 80001bc: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  100. 80001c0: 468c mov ip, r1
  101. 80001c2: 4604 mov r4, r0
  102. 80001c4: 9e08 ldr r6, [sp, #32]
  103. 80001c6: 2b00 cmp r3, #0
  104. 80001c8: d14b bne.n 8000262 <__udivmoddi4+0xa6>
  105. 80001ca: 428a cmp r2, r1
  106. 80001cc: 4615 mov r5, r2
  107. 80001ce: d967 bls.n 80002a0 <__udivmoddi4+0xe4>
  108. 80001d0: fab2 f282 clz r2, r2
  109. 80001d4: b14a cbz r2, 80001ea <__udivmoddi4+0x2e>
  110. 80001d6: f1c2 0720 rsb r7, r2, #32
  111. 80001da: fa01 f302 lsl.w r3, r1, r2
  112. 80001de: fa20 f707 lsr.w r7, r0, r7
  113. 80001e2: 4095 lsls r5, r2
  114. 80001e4: ea47 0c03 orr.w ip, r7, r3
  115. 80001e8: 4094 lsls r4, r2
  116. 80001ea: ea4f 4e15 mov.w lr, r5, lsr #16
  117. 80001ee: fbbc f7fe udiv r7, ip, lr
  118. 80001f2: fa1f f885 uxth.w r8, r5
  119. 80001f6: fb0e c317 mls r3, lr, r7, ip
  120. 80001fa: fb07 f908 mul.w r9, r7, r8
  121. 80001fe: 0c21 lsrs r1, r4, #16
  122. 8000200: ea41 4303 orr.w r3, r1, r3, lsl #16
  123. 8000204: 4599 cmp r9, r3
  124. 8000206: d909 bls.n 800021c <__udivmoddi4+0x60>
  125. 8000208: 18eb adds r3, r5, r3
  126. 800020a: f107 31ff add.w r1, r7, #4294967295
  127. 800020e: f080 811c bcs.w 800044a <__udivmoddi4+0x28e>
  128. 8000212: 4599 cmp r9, r3
  129. 8000214: f240 8119 bls.w 800044a <__udivmoddi4+0x28e>
  130. 8000218: 3f02 subs r7, #2
  131. 800021a: 442b add r3, r5
  132. 800021c: eba3 0309 sub.w r3, r3, r9
  133. 8000220: fbb3 f0fe udiv r0, r3, lr
  134. 8000224: fb0e 3310 mls r3, lr, r0, r3
  135. 8000228: fb00 f108 mul.w r1, r0, r8
  136. 800022c: b2a4 uxth r4, r4
  137. 800022e: ea44 4403 orr.w r4, r4, r3, lsl #16
  138. 8000232: 42a1 cmp r1, r4
  139. 8000234: d909 bls.n 800024a <__udivmoddi4+0x8e>
  140. 8000236: 192c adds r4, r5, r4
  141. 8000238: f100 33ff add.w r3, r0, #4294967295
  142. 800023c: f080 8107 bcs.w 800044e <__udivmoddi4+0x292>
  143. 8000240: 42a1 cmp r1, r4
  144. 8000242: f240 8104 bls.w 800044e <__udivmoddi4+0x292>
  145. 8000246: 3802 subs r0, #2
  146. 8000248: 442c add r4, r5
  147. 800024a: ea40 4007 orr.w r0, r0, r7, lsl #16
  148. 800024e: 2700 movs r7, #0
  149. 8000250: 1a64 subs r4, r4, r1
  150. 8000252: b11e cbz r6, 800025c <__udivmoddi4+0xa0>
  151. 8000254: 2300 movs r3, #0
  152. 8000256: 40d4 lsrs r4, r2
  153. 8000258: e9c6 4300 strd r4, r3, [r6]
  154. 800025c: 4639 mov r1, r7
  155. 800025e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  156. 8000262: 428b cmp r3, r1
  157. 8000264: d909 bls.n 800027a <__udivmoddi4+0xbe>
  158. 8000266: 2e00 cmp r6, #0
  159. 8000268: f000 80ec beq.w 8000444 <__udivmoddi4+0x288>
  160. 800026c: 2700 movs r7, #0
  161. 800026e: e9c6 0100 strd r0, r1, [r6]
  162. 8000272: 4638 mov r0, r7
  163. 8000274: 4639 mov r1, r7
  164. 8000276: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  165. 800027a: fab3 f783 clz r7, r3
  166. 800027e: 2f00 cmp r7, #0
  167. 8000280: d148 bne.n 8000314 <__udivmoddi4+0x158>
  168. 8000282: 428b cmp r3, r1
  169. 8000284: d302 bcc.n 800028c <__udivmoddi4+0xd0>
  170. 8000286: 4282 cmp r2, r0
  171. 8000288: f200 80fb bhi.w 8000482 <__udivmoddi4+0x2c6>
  172. 800028c: 1a84 subs r4, r0, r2
  173. 800028e: eb61 0303 sbc.w r3, r1, r3
  174. 8000292: 2001 movs r0, #1
  175. 8000294: 469c mov ip, r3
  176. 8000296: 2e00 cmp r6, #0
  177. 8000298: d0e0 beq.n 800025c <__udivmoddi4+0xa0>
  178. 800029a: e9c6 4c00 strd r4, ip, [r6]
  179. 800029e: e7dd b.n 800025c <__udivmoddi4+0xa0>
  180. 80002a0: b902 cbnz r2, 80002a4 <__udivmoddi4+0xe8>
  181. 80002a2: deff udf #255 ; 0xff
  182. 80002a4: fab2 f282 clz r2, r2
  183. 80002a8: 2a00 cmp r2, #0
  184. 80002aa: f040 808f bne.w 80003cc <__udivmoddi4+0x210>
  185. 80002ae: 2701 movs r7, #1
  186. 80002b0: 1b49 subs r1, r1, r5
  187. 80002b2: ea4f 4815 mov.w r8, r5, lsr #16
  188. 80002b6: fa1f f985 uxth.w r9, r5
  189. 80002ba: fbb1 fef8 udiv lr, r1, r8
  190. 80002be: fb08 111e mls r1, r8, lr, r1
  191. 80002c2: fb09 f00e mul.w r0, r9, lr
  192. 80002c6: ea4f 4c14 mov.w ip, r4, lsr #16
  193. 80002ca: ea4c 4301 orr.w r3, ip, r1, lsl #16
  194. 80002ce: 4298 cmp r0, r3
  195. 80002d0: d907 bls.n 80002e2 <__udivmoddi4+0x126>
  196. 80002d2: 18eb adds r3, r5, r3
  197. 80002d4: f10e 31ff add.w r1, lr, #4294967295
  198. 80002d8: d202 bcs.n 80002e0 <__udivmoddi4+0x124>
  199. 80002da: 4298 cmp r0, r3
  200. 80002dc: f200 80cd bhi.w 800047a <__udivmoddi4+0x2be>
  201. 80002e0: 468e mov lr, r1
  202. 80002e2: 1a1b subs r3, r3, r0
  203. 80002e4: fbb3 f0f8 udiv r0, r3, r8
  204. 80002e8: fb08 3310 mls r3, r8, r0, r3
  205. 80002ec: fb09 f900 mul.w r9, r9, r0
  206. 80002f0: b2a4 uxth r4, r4
  207. 80002f2: ea44 4403 orr.w r4, r4, r3, lsl #16
  208. 80002f6: 45a1 cmp r9, r4
  209. 80002f8: d907 bls.n 800030a <__udivmoddi4+0x14e>
  210. 80002fa: 192c adds r4, r5, r4
  211. 80002fc: f100 33ff add.w r3, r0, #4294967295
  212. 8000300: d202 bcs.n 8000308 <__udivmoddi4+0x14c>
  213. 8000302: 45a1 cmp r9, r4
  214. 8000304: f200 80b6 bhi.w 8000474 <__udivmoddi4+0x2b8>
  215. 8000308: 4618 mov r0, r3
  216. 800030a: eba4 0409 sub.w r4, r4, r9
  217. 800030e: ea40 400e orr.w r0, r0, lr, lsl #16
  218. 8000312: e79e b.n 8000252 <__udivmoddi4+0x96>
  219. 8000314: f1c7 0520 rsb r5, r7, #32
  220. 8000318: 40bb lsls r3, r7
  221. 800031a: fa22 fc05 lsr.w ip, r2, r5
  222. 800031e: ea4c 0c03 orr.w ip, ip, r3
  223. 8000322: fa21 f405 lsr.w r4, r1, r5
  224. 8000326: ea4f 4e1c mov.w lr, ip, lsr #16
  225. 800032a: fbb4 f9fe udiv r9, r4, lr
  226. 800032e: fa1f f88c uxth.w r8, ip
  227. 8000332: fb0e 4419 mls r4, lr, r9, r4
  228. 8000336: fa20 f305 lsr.w r3, r0, r5
  229. 800033a: 40b9 lsls r1, r7
  230. 800033c: fb09 fa08 mul.w sl, r9, r8
  231. 8000340: 4319 orrs r1, r3
  232. 8000342: 0c0b lsrs r3, r1, #16
  233. 8000344: ea43 4404 orr.w r4, r3, r4, lsl #16
  234. 8000348: 45a2 cmp sl, r4
  235. 800034a: fa02 f207 lsl.w r2, r2, r7
  236. 800034e: fa00 f307 lsl.w r3, r0, r7
  237. 8000352: d90b bls.n 800036c <__udivmoddi4+0x1b0>
  238. 8000354: eb1c 0404 adds.w r4, ip, r4
  239. 8000358: f109 30ff add.w r0, r9, #4294967295
  240. 800035c: f080 8088 bcs.w 8000470 <__udivmoddi4+0x2b4>
  241. 8000360: 45a2 cmp sl, r4
  242. 8000362: f240 8085 bls.w 8000470 <__udivmoddi4+0x2b4>
  243. 8000366: f1a9 0902 sub.w r9, r9, #2
  244. 800036a: 4464 add r4, ip
  245. 800036c: eba4 040a sub.w r4, r4, sl
  246. 8000370: fbb4 f0fe udiv r0, r4, lr
  247. 8000374: fb0e 4410 mls r4, lr, r0, r4
  248. 8000378: fb00 fa08 mul.w sl, r0, r8
  249. 800037c: b289 uxth r1, r1
  250. 800037e: ea41 4404 orr.w r4, r1, r4, lsl #16
  251. 8000382: 45a2 cmp sl, r4
  252. 8000384: d908 bls.n 8000398 <__udivmoddi4+0x1dc>
  253. 8000386: eb1c 0404 adds.w r4, ip, r4
  254. 800038a: f100 31ff add.w r1, r0, #4294967295
  255. 800038e: d26b bcs.n 8000468 <__udivmoddi4+0x2ac>
  256. 8000390: 45a2 cmp sl, r4
  257. 8000392: d969 bls.n 8000468 <__udivmoddi4+0x2ac>
  258. 8000394: 3802 subs r0, #2
  259. 8000396: 4464 add r4, ip
  260. 8000398: ea40 4009 orr.w r0, r0, r9, lsl #16
  261. 800039c: fba0 8902 umull r8, r9, r0, r2
  262. 80003a0: eba4 040a sub.w r4, r4, sl
  263. 80003a4: 454c cmp r4, r9
  264. 80003a6: 4641 mov r1, r8
  265. 80003a8: 46ce mov lr, r9
  266. 80003aa: d354 bcc.n 8000456 <__udivmoddi4+0x29a>
  267. 80003ac: d051 beq.n 8000452 <__udivmoddi4+0x296>
  268. 80003ae: 2e00 cmp r6, #0
  269. 80003b0: d069 beq.n 8000486 <__udivmoddi4+0x2ca>
  270. 80003b2: 1a5a subs r2, r3, r1
  271. 80003b4: eb64 040e sbc.w r4, r4, lr
  272. 80003b8: fa04 f505 lsl.w r5, r4, r5
  273. 80003bc: fa22 f307 lsr.w r3, r2, r7
  274. 80003c0: 40fc lsrs r4, r7
  275. 80003c2: 431d orrs r5, r3
  276. 80003c4: e9c6 5400 strd r5, r4, [r6]
  277. 80003c8: 2700 movs r7, #0
  278. 80003ca: e747 b.n 800025c <__udivmoddi4+0xa0>
  279. 80003cc: 4095 lsls r5, r2
  280. 80003ce: f1c2 0320 rsb r3, r2, #32
  281. 80003d2: fa21 f003 lsr.w r0, r1, r3
  282. 80003d6: ea4f 4815 mov.w r8, r5, lsr #16
  283. 80003da: fbb0 f7f8 udiv r7, r0, r8
  284. 80003de: fa1f f985 uxth.w r9, r5
  285. 80003e2: fb08 0017 mls r0, r8, r7, r0
  286. 80003e6: fa24 f303 lsr.w r3, r4, r3
  287. 80003ea: 4091 lsls r1, r2
  288. 80003ec: fb07 fc09 mul.w ip, r7, r9
  289. 80003f0: 430b orrs r3, r1
  290. 80003f2: 0c19 lsrs r1, r3, #16
  291. 80003f4: ea41 4100 orr.w r1, r1, r0, lsl #16
  292. 80003f8: 458c cmp ip, r1
  293. 80003fa: fa04 f402 lsl.w r4, r4, r2
  294. 80003fe: d907 bls.n 8000410 <__udivmoddi4+0x254>
  295. 8000400: 1869 adds r1, r5, r1
  296. 8000402: f107 30ff add.w r0, r7, #4294967295
  297. 8000406: d231 bcs.n 800046c <__udivmoddi4+0x2b0>
  298. 8000408: 458c cmp ip, r1
  299. 800040a: d92f bls.n 800046c <__udivmoddi4+0x2b0>
  300. 800040c: 3f02 subs r7, #2
  301. 800040e: 4429 add r1, r5
  302. 8000410: eba1 010c sub.w r1, r1, ip
  303. 8000414: fbb1 f0f8 udiv r0, r1, r8
  304. 8000418: fb08 1c10 mls ip, r8, r0, r1
  305. 800041c: fb00 fe09 mul.w lr, r0, r9
  306. 8000420: b299 uxth r1, r3
  307. 8000422: ea41 410c orr.w r1, r1, ip, lsl #16
  308. 8000426: 458e cmp lr, r1
  309. 8000428: d907 bls.n 800043a <__udivmoddi4+0x27e>
  310. 800042a: 1869 adds r1, r5, r1
  311. 800042c: f100 33ff add.w r3, r0, #4294967295
  312. 8000430: d218 bcs.n 8000464 <__udivmoddi4+0x2a8>
  313. 8000432: 458e cmp lr, r1
  314. 8000434: d916 bls.n 8000464 <__udivmoddi4+0x2a8>
  315. 8000436: 3802 subs r0, #2
  316. 8000438: 4429 add r1, r5
  317. 800043a: eba1 010e sub.w r1, r1, lr
  318. 800043e: ea40 4707 orr.w r7, r0, r7, lsl #16
  319. 8000442: e73a b.n 80002ba <__udivmoddi4+0xfe>
  320. 8000444: 4637 mov r7, r6
  321. 8000446: 4630 mov r0, r6
  322. 8000448: e708 b.n 800025c <__udivmoddi4+0xa0>
  323. 800044a: 460f mov r7, r1
  324. 800044c: e6e6 b.n 800021c <__udivmoddi4+0x60>
  325. 800044e: 4618 mov r0, r3
  326. 8000450: e6fb b.n 800024a <__udivmoddi4+0x8e>
  327. 8000452: 4543 cmp r3, r8
  328. 8000454: d2ab bcs.n 80003ae <__udivmoddi4+0x1f2>
  329. 8000456: ebb8 0102 subs.w r1, r8, r2
  330. 800045a: eb69 020c sbc.w r2, r9, ip
  331. 800045e: 3801 subs r0, #1
  332. 8000460: 4696 mov lr, r2
  333. 8000462: e7a4 b.n 80003ae <__udivmoddi4+0x1f2>
  334. 8000464: 4618 mov r0, r3
  335. 8000466: e7e8 b.n 800043a <__udivmoddi4+0x27e>
  336. 8000468: 4608 mov r0, r1
  337. 800046a: e795 b.n 8000398 <__udivmoddi4+0x1dc>
  338. 800046c: 4607 mov r7, r0
  339. 800046e: e7cf b.n 8000410 <__udivmoddi4+0x254>
  340. 8000470: 4681 mov r9, r0
  341. 8000472: e77b b.n 800036c <__udivmoddi4+0x1b0>
  342. 8000474: 3802 subs r0, #2
  343. 8000476: 442c add r4, r5
  344. 8000478: e747 b.n 800030a <__udivmoddi4+0x14e>
  345. 800047a: f1ae 0e02 sub.w lr, lr, #2
  346. 800047e: 442b add r3, r5
  347. 8000480: e72f b.n 80002e2 <__udivmoddi4+0x126>
  348. 8000482: 4638 mov r0, r7
  349. 8000484: e707 b.n 8000296 <__udivmoddi4+0xda>
  350. 8000486: 4637 mov r7, r6
  351. 8000488: e6e8 b.n 800025c <__udivmoddi4+0xa0>
  352. 800048a: bf00 nop
  353. 0800048c <__aeabi_idiv0>:
  354. 800048c: 4770 bx lr
  355. 800048e: bf00 nop
  356. 08000490 <SELECT>:
  357. * SPI functions
  358. **************************************/
  359. /* slave select */
  360. static void SELECT(void)
  361. {
  362. 8000490: b580 push {r7, lr}
  363. 8000492: af00 add r7, sp, #0
  364. HAL_GPIO_WritePin(SD_CS_PORT, SD_CS_PIN, GPIO_PIN_RESET);
  365. 8000494: 2200 movs r2, #0
  366. 8000496: 2140 movs r1, #64 ; 0x40
  367. 8000498: 4803 ldr r0, [pc, #12] ; (80004a8 <SELECT+0x18>)
  368. 800049a: f002 f807 bl 80024ac <HAL_GPIO_WritePin>
  369. HAL_Delay(1);
  370. 800049e: 2001 movs r0, #1
  371. 80004a0: f001 f966 bl 8001770 <HAL_Delay>
  372. }
  373. 80004a4: bf00 nop
  374. 80004a6: bd80 pop {r7, pc}
  375. 80004a8: 40020400 .word 0x40020400
  376. 080004ac <DESELECT>:
  377. /* slave deselect */
  378. static void DESELECT(void)
  379. {
  380. 80004ac: b580 push {r7, lr}
  381. 80004ae: af00 add r7, sp, #0
  382. HAL_GPIO_WritePin(SD_CS_PORT, SD_CS_PIN, GPIO_PIN_SET);
  383. 80004b0: 2201 movs r2, #1
  384. 80004b2: 2140 movs r1, #64 ; 0x40
  385. 80004b4: 4803 ldr r0, [pc, #12] ; (80004c4 <DESELECT+0x18>)
  386. 80004b6: f001 fff9 bl 80024ac <HAL_GPIO_WritePin>
  387. HAL_Delay(1);
  388. 80004ba: 2001 movs r0, #1
  389. 80004bc: f001 f958 bl 8001770 <HAL_Delay>
  390. }
  391. 80004c0: bf00 nop
  392. 80004c2: bd80 pop {r7, pc}
  393. 80004c4: 40020400 .word 0x40020400
  394. 080004c8 <SPI_TxByte>:
  395. /* SPI transmit a byte */
  396. static void SPI_TxByte(uint8_t data)
  397. {
  398. 80004c8: b580 push {r7, lr}
  399. 80004ca: b082 sub sp, #8
  400. 80004cc: af00 add r7, sp, #0
  401. 80004ce: 4603 mov r3, r0
  402. 80004d0: 71fb strb r3, [r7, #7]
  403. while(!__HAL_SPI_GET_FLAG(HSPI_SDCARD, SPI_FLAG_TXE));
  404. 80004d2: bf00 nop
  405. 80004d4: 4b08 ldr r3, [pc, #32] ; (80004f8 <SPI_TxByte+0x30>)
  406. 80004d6: 681b ldr r3, [r3, #0]
  407. 80004d8: 689b ldr r3, [r3, #8]
  408. 80004da: f003 0302 and.w r3, r3, #2
  409. 80004de: 2b02 cmp r3, #2
  410. 80004e0: d1f8 bne.n 80004d4 <SPI_TxByte+0xc>
  411. HAL_SPI_Transmit(HSPI_SDCARD, &data, 1, SPI_TIMEOUT);
  412. 80004e2: 1df9 adds r1, r7, #7
  413. 80004e4: 2364 movs r3, #100 ; 0x64
  414. 80004e6: 2201 movs r2, #1
  415. 80004e8: 4803 ldr r0, [pc, #12] ; (80004f8 <SPI_TxByte+0x30>)
  416. 80004ea: f002 fe40 bl 800316e <HAL_SPI_Transmit>
  417. }
  418. 80004ee: bf00 nop
  419. 80004f0: 3708 adds r7, #8
  420. 80004f2: 46bd mov sp, r7
  421. 80004f4: bd80 pop {r7, pc}
  422. 80004f6: bf00 nop
  423. 80004f8: 200013a0 .word 0x200013a0
  424. 080004fc <SPI_TxBuffer>:
  425. /* SPI transmit buffer */
  426. static void SPI_TxBuffer(uint8_t *buffer, uint16_t len)
  427. {
  428. 80004fc: b580 push {r7, lr}
  429. 80004fe: b082 sub sp, #8
  430. 8000500: af00 add r7, sp, #0
  431. 8000502: 6078 str r0, [r7, #4]
  432. 8000504: 460b mov r3, r1
  433. 8000506: 807b strh r3, [r7, #2]
  434. while(!__HAL_SPI_GET_FLAG(HSPI_SDCARD, SPI_FLAG_TXE));
  435. 8000508: bf00 nop
  436. 800050a: 4b08 ldr r3, [pc, #32] ; (800052c <SPI_TxBuffer+0x30>)
  437. 800050c: 681b ldr r3, [r3, #0]
  438. 800050e: 689b ldr r3, [r3, #8]
  439. 8000510: f003 0302 and.w r3, r3, #2
  440. 8000514: 2b02 cmp r3, #2
  441. 8000516: d1f8 bne.n 800050a <SPI_TxBuffer+0xe>
  442. HAL_SPI_Transmit(HSPI_SDCARD, buffer, len, SPI_TIMEOUT);
  443. 8000518: 887a ldrh r2, [r7, #2]
  444. 800051a: 2364 movs r3, #100 ; 0x64
  445. 800051c: 6879 ldr r1, [r7, #4]
  446. 800051e: 4803 ldr r0, [pc, #12] ; (800052c <SPI_TxBuffer+0x30>)
  447. 8000520: f002 fe25 bl 800316e <HAL_SPI_Transmit>
  448. }
  449. 8000524: bf00 nop
  450. 8000526: 3708 adds r7, #8
  451. 8000528: 46bd mov sp, r7
  452. 800052a: bd80 pop {r7, pc}
  453. 800052c: 200013a0 .word 0x200013a0
  454. 08000530 <SPI_RxByte>:
  455. /* SPI receive a byte */
  456. static uint8_t SPI_RxByte(void)
  457. {
  458. 8000530: b580 push {r7, lr}
  459. 8000532: b084 sub sp, #16
  460. 8000534: af02 add r7, sp, #8
  461. uint8_t dummy, data;
  462. dummy = 0xFF;
  463. 8000536: 23ff movs r3, #255 ; 0xff
  464. 8000538: 71fb strb r3, [r7, #7]
  465. while(!__HAL_SPI_GET_FLAG(HSPI_SDCARD, SPI_FLAG_TXE));
  466. 800053a: bf00 nop
  467. 800053c: 4b09 ldr r3, [pc, #36] ; (8000564 <SPI_RxByte+0x34>)
  468. 800053e: 681b ldr r3, [r3, #0]
  469. 8000540: 689b ldr r3, [r3, #8]
  470. 8000542: f003 0302 and.w r3, r3, #2
  471. 8000546: 2b02 cmp r3, #2
  472. 8000548: d1f8 bne.n 800053c <SPI_RxByte+0xc>
  473. HAL_SPI_TransmitReceive(HSPI_SDCARD, &dummy, &data, 1, SPI_TIMEOUT);
  474. 800054a: 1dba adds r2, r7, #6
  475. 800054c: 1df9 adds r1, r7, #7
  476. 800054e: 2364 movs r3, #100 ; 0x64
  477. 8000550: 9300 str r3, [sp, #0]
  478. 8000552: 2301 movs r3, #1
  479. 8000554: 4803 ldr r0, [pc, #12] ; (8000564 <SPI_RxByte+0x34>)
  480. 8000556: f002 ff46 bl 80033e6 <HAL_SPI_TransmitReceive>
  481. return data;
  482. 800055a: 79bb ldrb r3, [r7, #6]
  483. }
  484. 800055c: 4618 mov r0, r3
  485. 800055e: 3708 adds r7, #8
  486. 8000560: 46bd mov sp, r7
  487. 8000562: bd80 pop {r7, pc}
  488. 8000564: 200013a0 .word 0x200013a0
  489. 08000568 <SPI_RxBytePtr>:
  490. /* SPI receive a byte via pointer */
  491. static void SPI_RxBytePtr(uint8_t *buff)
  492. {
  493. 8000568: b580 push {r7, lr}
  494. 800056a: b082 sub sp, #8
  495. 800056c: af00 add r7, sp, #0
  496. 800056e: 6078 str r0, [r7, #4]
  497. *buff = SPI_RxByte();
  498. 8000570: f7ff ffde bl 8000530 <SPI_RxByte>
  499. 8000574: 4603 mov r3, r0
  500. 8000576: 461a mov r2, r3
  501. 8000578: 687b ldr r3, [r7, #4]
  502. 800057a: 701a strb r2, [r3, #0]
  503. }
  504. 800057c: bf00 nop
  505. 800057e: 3708 adds r7, #8
  506. 8000580: 46bd mov sp, r7
  507. 8000582: bd80 pop {r7, pc}
  508. 08000584 <SD_ReadyWait>:
  509. * SD functions
  510. **************************************/
  511. /* wait SD ready */
  512. static uint8_t SD_ReadyWait(void)
  513. {
  514. 8000584: b580 push {r7, lr}
  515. 8000586: b082 sub sp, #8
  516. 8000588: af00 add r7, sp, #0
  517. uint8_t res;
  518. /* timeout 500ms */
  519. Timer2 = 500;
  520. 800058a: 4b0a ldr r3, [pc, #40] ; (80005b4 <SD_ReadyWait+0x30>)
  521. 800058c: f44f 72fa mov.w r2, #500 ; 0x1f4
  522. 8000590: 801a strh r2, [r3, #0]
  523. /* if SD goes ready, receives 0xFF */
  524. do {
  525. res = SPI_RxByte();
  526. 8000592: f7ff ffcd bl 8000530 <SPI_RxByte>
  527. 8000596: 4603 mov r3, r0
  528. 8000598: 71fb strb r3, [r7, #7]
  529. } while ((res != 0xFF) && Timer2);
  530. 800059a: 79fb ldrb r3, [r7, #7]
  531. 800059c: 2bff cmp r3, #255 ; 0xff
  532. 800059e: d003 beq.n 80005a8 <SD_ReadyWait+0x24>
  533. 80005a0: 4b04 ldr r3, [pc, #16] ; (80005b4 <SD_ReadyWait+0x30>)
  534. 80005a2: 881b ldrh r3, [r3, #0]
  535. 80005a4: 2b00 cmp r3, #0
  536. 80005a6: d1f4 bne.n 8000592 <SD_ReadyWait+0xe>
  537. return res;
  538. 80005a8: 79fb ldrb r3, [r7, #7]
  539. }
  540. 80005aa: 4618 mov r0, r3
  541. 80005ac: 3708 adds r7, #8
  542. 80005ae: 46bd mov sp, r7
  543. 80005b0: bd80 pop {r7, pc}
  544. 80005b2: bf00 nop
  545. 80005b4: 200002e8 .word 0x200002e8
  546. 080005b8 <SD_PowerOn>:
  547. /* power on */
  548. static void SD_PowerOn(void)
  549. {
  550. 80005b8: b580 push {r7, lr}
  551. 80005ba: b084 sub sp, #16
  552. 80005bc: af00 add r7, sp, #0
  553. uint8_t args[6];
  554. uint32_t cnt = 0x1FFF;
  555. 80005be: f641 73ff movw r3, #8191 ; 0x1fff
  556. 80005c2: 60fb str r3, [r7, #12]
  557. /* transmit bytes to wake up */
  558. DESELECT();
  559. 80005c4: f7ff ff72 bl 80004ac <DESELECT>
  560. for(int i = 0; i < 10; i++)
  561. 80005c8: 2300 movs r3, #0
  562. 80005ca: 60bb str r3, [r7, #8]
  563. 80005cc: e005 b.n 80005da <SD_PowerOn+0x22>
  564. {
  565. SPI_TxByte(0xFF);
  566. 80005ce: 20ff movs r0, #255 ; 0xff
  567. 80005d0: f7ff ff7a bl 80004c8 <SPI_TxByte>
  568. for(int i = 0; i < 10; i++)
  569. 80005d4: 68bb ldr r3, [r7, #8]
  570. 80005d6: 3301 adds r3, #1
  571. 80005d8: 60bb str r3, [r7, #8]
  572. 80005da: 68bb ldr r3, [r7, #8]
  573. 80005dc: 2b09 cmp r3, #9
  574. 80005de: ddf6 ble.n 80005ce <SD_PowerOn+0x16>
  575. }
  576. /* slave select */
  577. SELECT();
  578. 80005e0: f7ff ff56 bl 8000490 <SELECT>
  579. /* make idle state */
  580. args[0] = CMD0; /* CMD0:GO_IDLE_STATE */
  581. 80005e4: 2340 movs r3, #64 ; 0x40
  582. 80005e6: 703b strb r3, [r7, #0]
  583. args[1] = 0;
  584. 80005e8: 2300 movs r3, #0
  585. 80005ea: 707b strb r3, [r7, #1]
  586. args[2] = 0;
  587. 80005ec: 2300 movs r3, #0
  588. 80005ee: 70bb strb r3, [r7, #2]
  589. args[3] = 0;
  590. 80005f0: 2300 movs r3, #0
  591. 80005f2: 70fb strb r3, [r7, #3]
  592. args[4] = 0;
  593. 80005f4: 2300 movs r3, #0
  594. 80005f6: 713b strb r3, [r7, #4]
  595. args[5] = 0x95; /* CRC */
  596. 80005f8: 2395 movs r3, #149 ; 0x95
  597. 80005fa: 717b strb r3, [r7, #5]
  598. SPI_TxBuffer(args, sizeof(args));
  599. 80005fc: 463b mov r3, r7
  600. 80005fe: 2106 movs r1, #6
  601. 8000600: 4618 mov r0, r3
  602. 8000602: f7ff ff7b bl 80004fc <SPI_TxBuffer>
  603. /* wait response */
  604. while ((SPI_RxByte() != 0x01) && cnt)
  605. 8000606: e002 b.n 800060e <SD_PowerOn+0x56>
  606. {
  607. cnt--;
  608. 8000608: 68fb ldr r3, [r7, #12]
  609. 800060a: 3b01 subs r3, #1
  610. 800060c: 60fb str r3, [r7, #12]
  611. while ((SPI_RxByte() != 0x01) && cnt)
  612. 800060e: f7ff ff8f bl 8000530 <SPI_RxByte>
  613. 8000612: 4603 mov r3, r0
  614. 8000614: 2b01 cmp r3, #1
  615. 8000616: d002 beq.n 800061e <SD_PowerOn+0x66>
  616. 8000618: 68fb ldr r3, [r7, #12]
  617. 800061a: 2b00 cmp r3, #0
  618. 800061c: d1f4 bne.n 8000608 <SD_PowerOn+0x50>
  619. }
  620. DESELECT();
  621. 800061e: f7ff ff45 bl 80004ac <DESELECT>
  622. SPI_TxByte(0XFF);
  623. 8000622: 20ff movs r0, #255 ; 0xff
  624. 8000624: f7ff ff50 bl 80004c8 <SPI_TxByte>
  625. PowerFlag = 1;
  626. 8000628: 4b03 ldr r3, [pc, #12] ; (8000638 <SD_PowerOn+0x80>)
  627. 800062a: 2201 movs r2, #1
  628. 800062c: 701a strb r2, [r3, #0]
  629. }
  630. 800062e: bf00 nop
  631. 8000630: 3710 adds r7, #16
  632. 8000632: 46bd mov sp, r7
  633. 8000634: bd80 pop {r7, pc}
  634. 8000636: bf00 nop
  635. 8000638: 200000a5 .word 0x200000a5
  636. 0800063c <SD_PowerOff>:
  637. /* power off */
  638. static void SD_PowerOff(void)
  639. {
  640. 800063c: b480 push {r7}
  641. 800063e: af00 add r7, sp, #0
  642. PowerFlag = 0;
  643. 8000640: 4b03 ldr r3, [pc, #12] ; (8000650 <SD_PowerOff+0x14>)
  644. 8000642: 2200 movs r2, #0
  645. 8000644: 701a strb r2, [r3, #0]
  646. }
  647. 8000646: bf00 nop
  648. 8000648: 46bd mov sp, r7
  649. 800064a: bc80 pop {r7}
  650. 800064c: 4770 bx lr
  651. 800064e: bf00 nop
  652. 8000650: 200000a5 .word 0x200000a5
  653. 08000654 <SD_CheckPower>:
  654. /* check power flag */
  655. static uint8_t SD_CheckPower(void)
  656. {
  657. 8000654: b480 push {r7}
  658. 8000656: af00 add r7, sp, #0
  659. return PowerFlag;
  660. 8000658: 4b02 ldr r3, [pc, #8] ; (8000664 <SD_CheckPower+0x10>)
  661. 800065a: 781b ldrb r3, [r3, #0]
  662. }
  663. 800065c: 4618 mov r0, r3
  664. 800065e: 46bd mov sp, r7
  665. 8000660: bc80 pop {r7}
  666. 8000662: 4770 bx lr
  667. 8000664: 200000a5 .word 0x200000a5
  668. 08000668 <SD_RxDataBlock>:
  669. /* receive data block */
  670. static bool SD_RxDataBlock(BYTE *buff, UINT len)
  671. {
  672. 8000668: b580 push {r7, lr}
  673. 800066a: b084 sub sp, #16
  674. 800066c: af00 add r7, sp, #0
  675. 800066e: 6078 str r0, [r7, #4]
  676. 8000670: 6039 str r1, [r7, #0]
  677. uint8_t token;
  678. /* timeout 200ms */
  679. Timer1 = 200;
  680. 8000672: 4b13 ldr r3, [pc, #76] ; (80006c0 <SD_RxDataBlock+0x58>)
  681. 8000674: 22c8 movs r2, #200 ; 0xc8
  682. 8000676: 801a strh r2, [r3, #0]
  683. /* loop until receive a response or timeout */
  684. do {
  685. token = SPI_RxByte();
  686. 8000678: f7ff ff5a bl 8000530 <SPI_RxByte>
  687. 800067c: 4603 mov r3, r0
  688. 800067e: 73fb strb r3, [r7, #15]
  689. } while((token == 0xFF) && Timer1);
  690. 8000680: 7bfb ldrb r3, [r7, #15]
  691. 8000682: 2bff cmp r3, #255 ; 0xff
  692. 8000684: d103 bne.n 800068e <SD_RxDataBlock+0x26>
  693. 8000686: 4b0e ldr r3, [pc, #56] ; (80006c0 <SD_RxDataBlock+0x58>)
  694. 8000688: 881b ldrh r3, [r3, #0]
  695. 800068a: 2b00 cmp r3, #0
  696. 800068c: d1f4 bne.n 8000678 <SD_RxDataBlock+0x10>
  697. /* invalid response */
  698. if(token != 0xFE) return FALSE;
  699. 800068e: 7bfb ldrb r3, [r7, #15]
  700. 8000690: 2bfe cmp r3, #254 ; 0xfe
  701. 8000692: d001 beq.n 8000698 <SD_RxDataBlock+0x30>
  702. 8000694: 2300 movs r3, #0
  703. 8000696: e00f b.n 80006b8 <SD_RxDataBlock+0x50>
  704. /* receive data */
  705. do {
  706. SPI_RxBytePtr(buff++);
  707. 8000698: 687b ldr r3, [r7, #4]
  708. 800069a: 1c5a adds r2, r3, #1
  709. 800069c: 607a str r2, [r7, #4]
  710. 800069e: 4618 mov r0, r3
  711. 80006a0: f7ff ff62 bl 8000568 <SPI_RxBytePtr>
  712. } while(len--);
  713. 80006a4: 683b ldr r3, [r7, #0]
  714. 80006a6: 1e5a subs r2, r3, #1
  715. 80006a8: 603a str r2, [r7, #0]
  716. 80006aa: 2b00 cmp r3, #0
  717. 80006ac: d1f4 bne.n 8000698 <SD_RxDataBlock+0x30>
  718. /* discard CRC */
  719. SPI_RxByte();
  720. 80006ae: f7ff ff3f bl 8000530 <SPI_RxByte>
  721. SPI_RxByte();
  722. 80006b2: f7ff ff3d bl 8000530 <SPI_RxByte>
  723. return TRUE;
  724. 80006b6: 2301 movs r3, #1
  725. }
  726. 80006b8: 4618 mov r0, r3
  727. 80006ba: 3710 adds r7, #16
  728. 80006bc: 46bd mov sp, r7
  729. 80006be: bd80 pop {r7, pc}
  730. 80006c0: 200002ea .word 0x200002ea
  731. 080006c4 <SD_TxDataBlock>:
  732. /* transmit data block */
  733. #if _USE_WRITE == 1
  734. static bool SD_TxDataBlock(const uint8_t *buff, BYTE token)
  735. {
  736. 80006c4: b580 push {r7, lr}
  737. 80006c6: b084 sub sp, #16
  738. 80006c8: af00 add r7, sp, #0
  739. 80006ca: 6078 str r0, [r7, #4]
  740. 80006cc: 460b mov r3, r1
  741. 80006ce: 70fb strb r3, [r7, #3]
  742. uint8_t resp;
  743. uint8_t i = 0;
  744. 80006d0: 2300 movs r3, #0
  745. 80006d2: 73bb strb r3, [r7, #14]
  746. /* wait SD ready */
  747. if (SD_ReadyWait() != 0xFF) return FALSE;
  748. 80006d4: f7ff ff56 bl 8000584 <SD_ReadyWait>
  749. 80006d8: 4603 mov r3, r0
  750. 80006da: 2bff cmp r3, #255 ; 0xff
  751. 80006dc: d001 beq.n 80006e2 <SD_TxDataBlock+0x1e>
  752. 80006de: 2300 movs r3, #0
  753. 80006e0: e02f b.n 8000742 <SD_TxDataBlock+0x7e>
  754. /* transmit token */
  755. SPI_TxByte(token);
  756. 80006e2: 78fb ldrb r3, [r7, #3]
  757. 80006e4: 4618 mov r0, r3
  758. 80006e6: f7ff feef bl 80004c8 <SPI_TxByte>
  759. /* if it's not STOP token, transmit data */
  760. if (token != 0xFD)
  761. 80006ea: 78fb ldrb r3, [r7, #3]
  762. 80006ec: 2bfd cmp r3, #253 ; 0xfd
  763. 80006ee: d020 beq.n 8000732 <SD_TxDataBlock+0x6e>
  764. {
  765. SPI_TxBuffer((uint8_t*)buff, 512);
  766. 80006f0: f44f 7100 mov.w r1, #512 ; 0x200
  767. 80006f4: 6878 ldr r0, [r7, #4]
  768. 80006f6: f7ff ff01 bl 80004fc <SPI_TxBuffer>
  769. /* discard CRC */
  770. SPI_RxByte();
  771. 80006fa: f7ff ff19 bl 8000530 <SPI_RxByte>
  772. SPI_RxByte();
  773. 80006fe: f7ff ff17 bl 8000530 <SPI_RxByte>
  774. /* receive response */
  775. while (i <= 64)
  776. 8000702: e00b b.n 800071c <SD_TxDataBlock+0x58>
  777. {
  778. resp = SPI_RxByte();
  779. 8000704: f7ff ff14 bl 8000530 <SPI_RxByte>
  780. 8000708: 4603 mov r3, r0
  781. 800070a: 73fb strb r3, [r7, #15]
  782. /* transmit 0x05 accepted */
  783. if ((resp & 0x1F) == 0x05) break;
  784. 800070c: 7bfb ldrb r3, [r7, #15]
  785. 800070e: f003 031f and.w r3, r3, #31
  786. 8000712: 2b05 cmp r3, #5
  787. 8000714: d006 beq.n 8000724 <SD_TxDataBlock+0x60>
  788. i++;
  789. 8000716: 7bbb ldrb r3, [r7, #14]
  790. 8000718: 3301 adds r3, #1
  791. 800071a: 73bb strb r3, [r7, #14]
  792. while (i <= 64)
  793. 800071c: 7bbb ldrb r3, [r7, #14]
  794. 800071e: 2b40 cmp r3, #64 ; 0x40
  795. 8000720: d9f0 bls.n 8000704 <SD_TxDataBlock+0x40>
  796. 8000722: e000 b.n 8000726 <SD_TxDataBlock+0x62>
  797. if ((resp & 0x1F) == 0x05) break;
  798. 8000724: bf00 nop
  799. }
  800. /* recv buffer clear */
  801. while (SPI_RxByte() == 0);
  802. 8000726: bf00 nop
  803. 8000728: f7ff ff02 bl 8000530 <SPI_RxByte>
  804. 800072c: 4603 mov r3, r0
  805. 800072e: 2b00 cmp r3, #0
  806. 8000730: d0fa beq.n 8000728 <SD_TxDataBlock+0x64>
  807. }
  808. /* transmit 0x05 accepted */
  809. if ((resp & 0x1F) == 0x05) return TRUE;
  810. 8000732: 7bfb ldrb r3, [r7, #15]
  811. 8000734: f003 031f and.w r3, r3, #31
  812. 8000738: 2b05 cmp r3, #5
  813. 800073a: d101 bne.n 8000740 <SD_TxDataBlock+0x7c>
  814. 800073c: 2301 movs r3, #1
  815. 800073e: e000 b.n 8000742 <SD_TxDataBlock+0x7e>
  816. return FALSE;
  817. 8000740: 2300 movs r3, #0
  818. }
  819. 8000742: 4618 mov r0, r3
  820. 8000744: 3710 adds r7, #16
  821. 8000746: 46bd mov sp, r7
  822. 8000748: bd80 pop {r7, pc}
  823. 0800074a <SD_SendCmd>:
  824. #endif /* _USE_WRITE */
  825. /* transmit command */
  826. static BYTE SD_SendCmd(BYTE cmd, uint32_t arg)
  827. {
  828. 800074a: b580 push {r7, lr}
  829. 800074c: b084 sub sp, #16
  830. 800074e: af00 add r7, sp, #0
  831. 8000750: 4603 mov r3, r0
  832. 8000752: 6039 str r1, [r7, #0]
  833. 8000754: 71fb strb r3, [r7, #7]
  834. uint8_t crc, res;
  835. /* wait SD ready */
  836. if (SD_ReadyWait() != 0xFF) return 0xFF;
  837. 8000756: f7ff ff15 bl 8000584 <SD_ReadyWait>
  838. 800075a: 4603 mov r3, r0
  839. 800075c: 2bff cmp r3, #255 ; 0xff
  840. 800075e: d001 beq.n 8000764 <SD_SendCmd+0x1a>
  841. 8000760: 23ff movs r3, #255 ; 0xff
  842. 8000762: e042 b.n 80007ea <SD_SendCmd+0xa0>
  843. /* transmit command */
  844. SPI_TxByte(cmd); /* Command */
  845. 8000764: 79fb ldrb r3, [r7, #7]
  846. 8000766: 4618 mov r0, r3
  847. 8000768: f7ff feae bl 80004c8 <SPI_TxByte>
  848. SPI_TxByte((uint8_t)(arg >> 24)); /* Argument[31..24] */
  849. 800076c: 683b ldr r3, [r7, #0]
  850. 800076e: 0e1b lsrs r3, r3, #24
  851. 8000770: b2db uxtb r3, r3
  852. 8000772: 4618 mov r0, r3
  853. 8000774: f7ff fea8 bl 80004c8 <SPI_TxByte>
  854. SPI_TxByte((uint8_t)(arg >> 16)); /* Argument[23..16] */
  855. 8000778: 683b ldr r3, [r7, #0]
  856. 800077a: 0c1b lsrs r3, r3, #16
  857. 800077c: b2db uxtb r3, r3
  858. 800077e: 4618 mov r0, r3
  859. 8000780: f7ff fea2 bl 80004c8 <SPI_TxByte>
  860. SPI_TxByte((uint8_t)(arg >> 8)); /* Argument[15..8] */
  861. 8000784: 683b ldr r3, [r7, #0]
  862. 8000786: 0a1b lsrs r3, r3, #8
  863. 8000788: b2db uxtb r3, r3
  864. 800078a: 4618 mov r0, r3
  865. 800078c: f7ff fe9c bl 80004c8 <SPI_TxByte>
  866. SPI_TxByte((uint8_t)arg); /* Argument[7..0] */
  867. 8000790: 683b ldr r3, [r7, #0]
  868. 8000792: b2db uxtb r3, r3
  869. 8000794: 4618 mov r0, r3
  870. 8000796: f7ff fe97 bl 80004c8 <SPI_TxByte>
  871. /* prepare CRC */
  872. if(cmd == CMD0) crc = 0x95; /* CRC for CMD0(0) */
  873. 800079a: 79fb ldrb r3, [r7, #7]
  874. 800079c: 2b40 cmp r3, #64 ; 0x40
  875. 800079e: d102 bne.n 80007a6 <SD_SendCmd+0x5c>
  876. 80007a0: 2395 movs r3, #149 ; 0x95
  877. 80007a2: 73fb strb r3, [r7, #15]
  878. 80007a4: e007 b.n 80007b6 <SD_SendCmd+0x6c>
  879. else if(cmd == CMD8) crc = 0x87; /* CRC for CMD8(0x1AA) */
  880. 80007a6: 79fb ldrb r3, [r7, #7]
  881. 80007a8: 2b48 cmp r3, #72 ; 0x48
  882. 80007aa: d102 bne.n 80007b2 <SD_SendCmd+0x68>
  883. 80007ac: 2387 movs r3, #135 ; 0x87
  884. 80007ae: 73fb strb r3, [r7, #15]
  885. 80007b0: e001 b.n 80007b6 <SD_SendCmd+0x6c>
  886. else crc = 1;
  887. 80007b2: 2301 movs r3, #1
  888. 80007b4: 73fb strb r3, [r7, #15]
  889. /* transmit CRC */
  890. SPI_TxByte(crc);
  891. 80007b6: 7bfb ldrb r3, [r7, #15]
  892. 80007b8: 4618 mov r0, r3
  893. 80007ba: f7ff fe85 bl 80004c8 <SPI_TxByte>
  894. /* Skip a stuff byte when STOP_TRANSMISSION */
  895. if (cmd == CMD12) SPI_RxByte();
  896. 80007be: 79fb ldrb r3, [r7, #7]
  897. 80007c0: 2b4c cmp r3, #76 ; 0x4c
  898. 80007c2: d101 bne.n 80007c8 <SD_SendCmd+0x7e>
  899. 80007c4: f7ff feb4 bl 8000530 <SPI_RxByte>
  900. /* receive response */
  901. uint8_t n = 10;
  902. 80007c8: 230a movs r3, #10
  903. 80007ca: 73bb strb r3, [r7, #14]
  904. do {
  905. res = SPI_RxByte();
  906. 80007cc: f7ff feb0 bl 8000530 <SPI_RxByte>
  907. 80007d0: 4603 mov r3, r0
  908. 80007d2: 737b strb r3, [r7, #13]
  909. } while ((res & 0x80) && --n);
  910. 80007d4: f997 300d ldrsb.w r3, [r7, #13]
  911. 80007d8: 2b00 cmp r3, #0
  912. 80007da: da05 bge.n 80007e8 <SD_SendCmd+0x9e>
  913. 80007dc: 7bbb ldrb r3, [r7, #14]
  914. 80007de: 3b01 subs r3, #1
  915. 80007e0: 73bb strb r3, [r7, #14]
  916. 80007e2: 7bbb ldrb r3, [r7, #14]
  917. 80007e4: 2b00 cmp r3, #0
  918. 80007e6: d1f1 bne.n 80007cc <SD_SendCmd+0x82>
  919. return res;
  920. 80007e8: 7b7b ldrb r3, [r7, #13]
  921. }
  922. 80007ea: 4618 mov r0, r3
  923. 80007ec: 3710 adds r7, #16
  924. 80007ee: 46bd mov sp, r7
  925. 80007f0: bd80 pop {r7, pc}
  926. ...
  927. 080007f4 <SD_disk_initialize>:
  928. * user_diskio.c functions
  929. **************************************/
  930. /* initialize SD */
  931. DSTATUS SD_disk_initialize(BYTE drv)
  932. {
  933. 80007f4: b590 push {r4, r7, lr}
  934. 80007f6: b085 sub sp, #20
  935. 80007f8: af00 add r7, sp, #0
  936. 80007fa: 4603 mov r3, r0
  937. 80007fc: 71fb strb r3, [r7, #7]
  938. uint8_t n, type, ocr[4];
  939. /* single drive, drv should be 0 */
  940. if(drv) return STA_NOINIT;
  941. 80007fe: 79fb ldrb r3, [r7, #7]
  942. 8000800: 2b00 cmp r3, #0
  943. 8000802: d001 beq.n 8000808 <SD_disk_initialize+0x14>
  944. 8000804: 2301 movs r3, #1
  945. 8000806: e0d1 b.n 80009ac <SD_disk_initialize+0x1b8>
  946. /* no disk */
  947. if(Stat & STA_NODISK) return Stat;
  948. 8000808: 4b6a ldr r3, [pc, #424] ; (80009b4 <SD_disk_initialize+0x1c0>)
  949. 800080a: 781b ldrb r3, [r3, #0]
  950. 800080c: b2db uxtb r3, r3
  951. 800080e: f003 0302 and.w r3, r3, #2
  952. 8000812: 2b00 cmp r3, #0
  953. 8000814: d003 beq.n 800081e <SD_disk_initialize+0x2a>
  954. 8000816: 4b67 ldr r3, [pc, #412] ; (80009b4 <SD_disk_initialize+0x1c0>)
  955. 8000818: 781b ldrb r3, [r3, #0]
  956. 800081a: b2db uxtb r3, r3
  957. 800081c: e0c6 b.n 80009ac <SD_disk_initialize+0x1b8>
  958. /* power on */
  959. SD_PowerOn();
  960. 800081e: f7ff fecb bl 80005b8 <SD_PowerOn>
  961. /* slave select */
  962. SELECT();
  963. 8000822: f7ff fe35 bl 8000490 <SELECT>
  964. /* check disk type */
  965. type = 0;
  966. 8000826: 2300 movs r3, #0
  967. 8000828: 73bb strb r3, [r7, #14]
  968. /* send GO_IDLE_STATE command */
  969. if (SD_SendCmd(CMD0, 0) == 1)
  970. 800082a: 2100 movs r1, #0
  971. 800082c: 2040 movs r0, #64 ; 0x40
  972. 800082e: f7ff ff8c bl 800074a <SD_SendCmd>
  973. 8000832: 4603 mov r3, r0
  974. 8000834: 2b01 cmp r3, #1
  975. 8000836: f040 80a1 bne.w 800097c <SD_disk_initialize+0x188>
  976. {
  977. /* timeout 1 sec */
  978. Timer1 = 1000;
  979. 800083a: 4b5f ldr r3, [pc, #380] ; (80009b8 <SD_disk_initialize+0x1c4>)
  980. 800083c: f44f 727a mov.w r2, #1000 ; 0x3e8
  981. 8000840: 801a strh r2, [r3, #0]
  982. /* SDC V2+ accept CMD8 command, http://elm-chan.org/docs/mmc/mmc_e.html */
  983. if (SD_SendCmd(CMD8, 0x1AA) == 1)
  984. 8000842: f44f 71d5 mov.w r1, #426 ; 0x1aa
  985. 8000846: 2048 movs r0, #72 ; 0x48
  986. 8000848: f7ff ff7f bl 800074a <SD_SendCmd>
  987. 800084c: 4603 mov r3, r0
  988. 800084e: 2b01 cmp r3, #1
  989. 8000850: d155 bne.n 80008fe <SD_disk_initialize+0x10a>
  990. {
  991. /* operation condition register */
  992. for (n = 0; n < 4; n++)
  993. 8000852: 2300 movs r3, #0
  994. 8000854: 73fb strb r3, [r7, #15]
  995. 8000856: e00c b.n 8000872 <SD_disk_initialize+0x7e>
  996. {
  997. ocr[n] = SPI_RxByte();
  998. 8000858: 7bfc ldrb r4, [r7, #15]
  999. 800085a: f7ff fe69 bl 8000530 <SPI_RxByte>
  1000. 800085e: 4603 mov r3, r0
  1001. 8000860: 461a mov r2, r3
  1002. 8000862: f107 0310 add.w r3, r7, #16
  1003. 8000866: 4423 add r3, r4
  1004. 8000868: f803 2c08 strb.w r2, [r3, #-8]
  1005. for (n = 0; n < 4; n++)
  1006. 800086c: 7bfb ldrb r3, [r7, #15]
  1007. 800086e: 3301 adds r3, #1
  1008. 8000870: 73fb strb r3, [r7, #15]
  1009. 8000872: 7bfb ldrb r3, [r7, #15]
  1010. 8000874: 2b03 cmp r3, #3
  1011. 8000876: d9ef bls.n 8000858 <SD_disk_initialize+0x64>
  1012. }
  1013. /* voltage range 2.7-3.6V */
  1014. if (ocr[2] == 0x01 && ocr[3] == 0xAA)
  1015. 8000878: 7abb ldrb r3, [r7, #10]
  1016. 800087a: 2b01 cmp r3, #1
  1017. 800087c: d17e bne.n 800097c <SD_disk_initialize+0x188>
  1018. 800087e: 7afb ldrb r3, [r7, #11]
  1019. 8000880: 2baa cmp r3, #170 ; 0xaa
  1020. 8000882: d17b bne.n 800097c <SD_disk_initialize+0x188>
  1021. {
  1022. /* ACMD41 with HCS bit */
  1023. do {
  1024. if (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 1UL << 30) == 0) break;
  1025. 8000884: 2100 movs r1, #0
  1026. 8000886: 2077 movs r0, #119 ; 0x77
  1027. 8000888: f7ff ff5f bl 800074a <SD_SendCmd>
  1028. 800088c: 4603 mov r3, r0
  1029. 800088e: 2b01 cmp r3, #1
  1030. 8000890: d807 bhi.n 80008a2 <SD_disk_initialize+0xae>
  1031. 8000892: f04f 4180 mov.w r1, #1073741824 ; 0x40000000
  1032. 8000896: 2069 movs r0, #105 ; 0x69
  1033. 8000898: f7ff ff57 bl 800074a <SD_SendCmd>
  1034. 800089c: 4603 mov r3, r0
  1035. 800089e: 2b00 cmp r3, #0
  1036. 80008a0: d004 beq.n 80008ac <SD_disk_initialize+0xb8>
  1037. } while (Timer1);
  1038. 80008a2: 4b45 ldr r3, [pc, #276] ; (80009b8 <SD_disk_initialize+0x1c4>)
  1039. 80008a4: 881b ldrh r3, [r3, #0]
  1040. 80008a6: 2b00 cmp r3, #0
  1041. 80008a8: d1ec bne.n 8000884 <SD_disk_initialize+0x90>
  1042. 80008aa: e000 b.n 80008ae <SD_disk_initialize+0xba>
  1043. if (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 1UL << 30) == 0) break;
  1044. 80008ac: bf00 nop
  1045. /* READ_OCR */
  1046. if (Timer1 && SD_SendCmd(CMD58, 0) == 0)
  1047. 80008ae: 4b42 ldr r3, [pc, #264] ; (80009b8 <SD_disk_initialize+0x1c4>)
  1048. 80008b0: 881b ldrh r3, [r3, #0]
  1049. 80008b2: 2b00 cmp r3, #0
  1050. 80008b4: d062 beq.n 800097c <SD_disk_initialize+0x188>
  1051. 80008b6: 2100 movs r1, #0
  1052. 80008b8: 207a movs r0, #122 ; 0x7a
  1053. 80008ba: f7ff ff46 bl 800074a <SD_SendCmd>
  1054. 80008be: 4603 mov r3, r0
  1055. 80008c0: 2b00 cmp r3, #0
  1056. 80008c2: d15b bne.n 800097c <SD_disk_initialize+0x188>
  1057. {
  1058. /* Check CCS bit */
  1059. for (n = 0; n < 4; n++)
  1060. 80008c4: 2300 movs r3, #0
  1061. 80008c6: 73fb strb r3, [r7, #15]
  1062. 80008c8: e00c b.n 80008e4 <SD_disk_initialize+0xf0>
  1063. {
  1064. ocr[n] = SPI_RxByte();
  1065. 80008ca: 7bfc ldrb r4, [r7, #15]
  1066. 80008cc: f7ff fe30 bl 8000530 <SPI_RxByte>
  1067. 80008d0: 4603 mov r3, r0
  1068. 80008d2: 461a mov r2, r3
  1069. 80008d4: f107 0310 add.w r3, r7, #16
  1070. 80008d8: 4423 add r3, r4
  1071. 80008da: f803 2c08 strb.w r2, [r3, #-8]
  1072. for (n = 0; n < 4; n++)
  1073. 80008de: 7bfb ldrb r3, [r7, #15]
  1074. 80008e0: 3301 adds r3, #1
  1075. 80008e2: 73fb strb r3, [r7, #15]
  1076. 80008e4: 7bfb ldrb r3, [r7, #15]
  1077. 80008e6: 2b03 cmp r3, #3
  1078. 80008e8: d9ef bls.n 80008ca <SD_disk_initialize+0xd6>
  1079. }
  1080. /* SDv2 (HC or SC) */
  1081. type = (ocr[0] & 0x40) ? CT_SD2 | CT_BLOCK : CT_SD2;
  1082. 80008ea: 7a3b ldrb r3, [r7, #8]
  1083. 80008ec: f003 0340 and.w r3, r3, #64 ; 0x40
  1084. 80008f0: 2b00 cmp r3, #0
  1085. 80008f2: d001 beq.n 80008f8 <SD_disk_initialize+0x104>
  1086. 80008f4: 230c movs r3, #12
  1087. 80008f6: e000 b.n 80008fa <SD_disk_initialize+0x106>
  1088. 80008f8: 2304 movs r3, #4
  1089. 80008fa: 73bb strb r3, [r7, #14]
  1090. 80008fc: e03e b.n 800097c <SD_disk_initialize+0x188>
  1091. }
  1092. }
  1093. else
  1094. {
  1095. /* SDC V1 or MMC */
  1096. type = (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 0) <= 1) ? CT_SD1 : CT_MMC;
  1097. 80008fe: 2100 movs r1, #0
  1098. 8000900: 2077 movs r0, #119 ; 0x77
  1099. 8000902: f7ff ff22 bl 800074a <SD_SendCmd>
  1100. 8000906: 4603 mov r3, r0
  1101. 8000908: 2b01 cmp r3, #1
  1102. 800090a: d808 bhi.n 800091e <SD_disk_initialize+0x12a>
  1103. 800090c: 2100 movs r1, #0
  1104. 800090e: 2069 movs r0, #105 ; 0x69
  1105. 8000910: f7ff ff1b bl 800074a <SD_SendCmd>
  1106. 8000914: 4603 mov r3, r0
  1107. 8000916: 2b01 cmp r3, #1
  1108. 8000918: d801 bhi.n 800091e <SD_disk_initialize+0x12a>
  1109. 800091a: 2302 movs r3, #2
  1110. 800091c: e000 b.n 8000920 <SD_disk_initialize+0x12c>
  1111. 800091e: 2301 movs r3, #1
  1112. 8000920: 73bb strb r3, [r7, #14]
  1113. do
  1114. {
  1115. if (type == CT_SD1)
  1116. 8000922: 7bbb ldrb r3, [r7, #14]
  1117. 8000924: 2b02 cmp r3, #2
  1118. 8000926: d10e bne.n 8000946 <SD_disk_initialize+0x152>
  1119. {
  1120. if (SD_SendCmd(CMD55, 0) <= 1 && SD_SendCmd(CMD41, 0) == 0) break; /* ACMD41 */
  1121. 8000928: 2100 movs r1, #0
  1122. 800092a: 2077 movs r0, #119 ; 0x77
  1123. 800092c: f7ff ff0d bl 800074a <SD_SendCmd>
  1124. 8000930: 4603 mov r3, r0
  1125. 8000932: 2b01 cmp r3, #1
  1126. 8000934: d80e bhi.n 8000954 <SD_disk_initialize+0x160>
  1127. 8000936: 2100 movs r1, #0
  1128. 8000938: 2069 movs r0, #105 ; 0x69
  1129. 800093a: f7ff ff06 bl 800074a <SD_SendCmd>
  1130. 800093e: 4603 mov r3, r0
  1131. 8000940: 2b00 cmp r3, #0
  1132. 8000942: d107 bne.n 8000954 <SD_disk_initialize+0x160>
  1133. 8000944: e00c b.n 8000960 <SD_disk_initialize+0x16c>
  1134. }
  1135. else
  1136. {
  1137. if (SD_SendCmd(CMD1, 0) == 0) break; /* CMD1 */
  1138. 8000946: 2100 movs r1, #0
  1139. 8000948: 2041 movs r0, #65 ; 0x41
  1140. 800094a: f7ff fefe bl 800074a <SD_SendCmd>
  1141. 800094e: 4603 mov r3, r0
  1142. 8000950: 2b00 cmp r3, #0
  1143. 8000952: d004 beq.n 800095e <SD_disk_initialize+0x16a>
  1144. }
  1145. } while (Timer1);
  1146. 8000954: 4b18 ldr r3, [pc, #96] ; (80009b8 <SD_disk_initialize+0x1c4>)
  1147. 8000956: 881b ldrh r3, [r3, #0]
  1148. 8000958: 2b00 cmp r3, #0
  1149. 800095a: d1e2 bne.n 8000922 <SD_disk_initialize+0x12e>
  1150. 800095c: e000 b.n 8000960 <SD_disk_initialize+0x16c>
  1151. if (SD_SendCmd(CMD1, 0) == 0) break; /* CMD1 */
  1152. 800095e: bf00 nop
  1153. /* SET_BLOCKLEN */
  1154. if (!Timer1 || SD_SendCmd(CMD16, 512) != 0) type = 0;
  1155. 8000960: 4b15 ldr r3, [pc, #84] ; (80009b8 <SD_disk_initialize+0x1c4>)
  1156. 8000962: 881b ldrh r3, [r3, #0]
  1157. 8000964: 2b00 cmp r3, #0
  1158. 8000966: d007 beq.n 8000978 <SD_disk_initialize+0x184>
  1159. 8000968: f44f 7100 mov.w r1, #512 ; 0x200
  1160. 800096c: 2050 movs r0, #80 ; 0x50
  1161. 800096e: f7ff feec bl 800074a <SD_SendCmd>
  1162. 8000972: 4603 mov r3, r0
  1163. 8000974: 2b00 cmp r3, #0
  1164. 8000976: d001 beq.n 800097c <SD_disk_initialize+0x188>
  1165. 8000978: 2300 movs r3, #0
  1166. 800097a: 73bb strb r3, [r7, #14]
  1167. }
  1168. }
  1169. CardType = type;
  1170. 800097c: 4a0f ldr r2, [pc, #60] ; (80009bc <SD_disk_initialize+0x1c8>)
  1171. 800097e: 7bbb ldrb r3, [r7, #14]
  1172. 8000980: 7013 strb r3, [r2, #0]
  1173. /* Idle */
  1174. DESELECT();
  1175. 8000982: f7ff fd93 bl 80004ac <DESELECT>
  1176. SPI_RxByte();
  1177. 8000986: f7ff fdd3 bl 8000530 <SPI_RxByte>
  1178. /* Clear STA_NOINIT */
  1179. if (type)
  1180. 800098a: 7bbb ldrb r3, [r7, #14]
  1181. 800098c: 2b00 cmp r3, #0
  1182. 800098e: d008 beq.n 80009a2 <SD_disk_initialize+0x1ae>
  1183. {
  1184. Stat &= ~STA_NOINIT;
  1185. 8000990: 4b08 ldr r3, [pc, #32] ; (80009b4 <SD_disk_initialize+0x1c0>)
  1186. 8000992: 781b ldrb r3, [r3, #0]
  1187. 8000994: b2db uxtb r3, r3
  1188. 8000996: f023 0301 bic.w r3, r3, #1
  1189. 800099a: b2da uxtb r2, r3
  1190. 800099c: 4b05 ldr r3, [pc, #20] ; (80009b4 <SD_disk_initialize+0x1c0>)
  1191. 800099e: 701a strb r2, [r3, #0]
  1192. 80009a0: e001 b.n 80009a6 <SD_disk_initialize+0x1b2>
  1193. }
  1194. else
  1195. {
  1196. /* Initialization failed */
  1197. SD_PowerOff();
  1198. 80009a2: f7ff fe4b bl 800063c <SD_PowerOff>
  1199. }
  1200. return Stat;
  1201. 80009a6: 4b03 ldr r3, [pc, #12] ; (80009b4 <SD_disk_initialize+0x1c0>)
  1202. 80009a8: 781b ldrb r3, [r3, #0]
  1203. 80009aa: b2db uxtb r3, r3
  1204. }
  1205. 80009ac: 4618 mov r0, r3
  1206. 80009ae: 3714 adds r7, #20
  1207. 80009b0: 46bd mov sp, r7
  1208. 80009b2: bd90 pop {r4, r7, pc}
  1209. 80009b4: 20000000 .word 0x20000000
  1210. 80009b8: 200002ea .word 0x200002ea
  1211. 80009bc: 200000a4 .word 0x200000a4
  1212. 080009c0 <SD_disk_status>:
  1213. /* return disk status */
  1214. DSTATUS SD_disk_status(BYTE drv)
  1215. {
  1216. 80009c0: b480 push {r7}
  1217. 80009c2: b083 sub sp, #12
  1218. 80009c4: af00 add r7, sp, #0
  1219. 80009c6: 4603 mov r3, r0
  1220. 80009c8: 71fb strb r3, [r7, #7]
  1221. if (drv) return STA_NOINIT;
  1222. 80009ca: 79fb ldrb r3, [r7, #7]
  1223. 80009cc: 2b00 cmp r3, #0
  1224. 80009ce: d001 beq.n 80009d4 <SD_disk_status+0x14>
  1225. 80009d0: 2301 movs r3, #1
  1226. 80009d2: e002 b.n 80009da <SD_disk_status+0x1a>
  1227. return Stat;
  1228. 80009d4: 4b03 ldr r3, [pc, #12] ; (80009e4 <SD_disk_status+0x24>)
  1229. 80009d6: 781b ldrb r3, [r3, #0]
  1230. 80009d8: b2db uxtb r3, r3
  1231. }
  1232. 80009da: 4618 mov r0, r3
  1233. 80009dc: 370c adds r7, #12
  1234. 80009de: 46bd mov sp, r7
  1235. 80009e0: bc80 pop {r7}
  1236. 80009e2: 4770 bx lr
  1237. 80009e4: 20000000 .word 0x20000000
  1238. 080009e8 <SD_disk_read>:
  1239. /* read sector */
  1240. DRESULT SD_disk_read(BYTE pdrv, BYTE* buff, DWORD sector, UINT count)
  1241. {
  1242. 80009e8: b580 push {r7, lr}
  1243. 80009ea: b084 sub sp, #16
  1244. 80009ec: af00 add r7, sp, #0
  1245. 80009ee: 60b9 str r1, [r7, #8]
  1246. 80009f0: 607a str r2, [r7, #4]
  1247. 80009f2: 603b str r3, [r7, #0]
  1248. 80009f4: 4603 mov r3, r0
  1249. 80009f6: 73fb strb r3, [r7, #15]
  1250. /* pdrv should be 0 */
  1251. if (pdrv || !count) return RES_PARERR;
  1252. 80009f8: 7bfb ldrb r3, [r7, #15]
  1253. 80009fa: 2b00 cmp r3, #0
  1254. 80009fc: d102 bne.n 8000a04 <SD_disk_read+0x1c>
  1255. 80009fe: 683b ldr r3, [r7, #0]
  1256. 8000a00: 2b00 cmp r3, #0
  1257. 8000a02: d101 bne.n 8000a08 <SD_disk_read+0x20>
  1258. 8000a04: 2304 movs r3, #4
  1259. 8000a06: e051 b.n 8000aac <SD_disk_read+0xc4>
  1260. /* no disk */
  1261. if (Stat & STA_NOINIT) return RES_NOTRDY;
  1262. 8000a08: 4b2a ldr r3, [pc, #168] ; (8000ab4 <SD_disk_read+0xcc>)
  1263. 8000a0a: 781b ldrb r3, [r3, #0]
  1264. 8000a0c: b2db uxtb r3, r3
  1265. 8000a0e: f003 0301 and.w r3, r3, #1
  1266. 8000a12: 2b00 cmp r3, #0
  1267. 8000a14: d001 beq.n 8000a1a <SD_disk_read+0x32>
  1268. 8000a16: 2303 movs r3, #3
  1269. 8000a18: e048 b.n 8000aac <SD_disk_read+0xc4>
  1270. /* convert to byte address */
  1271. if (!(CardType & CT_SD2)) sector *= 512;
  1272. 8000a1a: 4b27 ldr r3, [pc, #156] ; (8000ab8 <SD_disk_read+0xd0>)
  1273. 8000a1c: 781b ldrb r3, [r3, #0]
  1274. 8000a1e: f003 0304 and.w r3, r3, #4
  1275. 8000a22: 2b00 cmp r3, #0
  1276. 8000a24: d102 bne.n 8000a2c <SD_disk_read+0x44>
  1277. 8000a26: 687b ldr r3, [r7, #4]
  1278. 8000a28: 025b lsls r3, r3, #9
  1279. 8000a2a: 607b str r3, [r7, #4]
  1280. SELECT();
  1281. 8000a2c: f7ff fd30 bl 8000490 <SELECT>
  1282. if (count == 1)
  1283. 8000a30: 683b ldr r3, [r7, #0]
  1284. 8000a32: 2b01 cmp r3, #1
  1285. 8000a34: d111 bne.n 8000a5a <SD_disk_read+0x72>
  1286. {
  1287. /* READ_SINGLE_BLOCK */
  1288. if ((SD_SendCmd(CMD17, sector) == 0) && SD_RxDataBlock(buff, 512)) count = 0;
  1289. 8000a36: 6879 ldr r1, [r7, #4]
  1290. 8000a38: 2051 movs r0, #81 ; 0x51
  1291. 8000a3a: f7ff fe86 bl 800074a <SD_SendCmd>
  1292. 8000a3e: 4603 mov r3, r0
  1293. 8000a40: 2b00 cmp r3, #0
  1294. 8000a42: d129 bne.n 8000a98 <SD_disk_read+0xb0>
  1295. 8000a44: f44f 7100 mov.w r1, #512 ; 0x200
  1296. 8000a48: 68b8 ldr r0, [r7, #8]
  1297. 8000a4a: f7ff fe0d bl 8000668 <SD_RxDataBlock>
  1298. 8000a4e: 4603 mov r3, r0
  1299. 8000a50: 2b00 cmp r3, #0
  1300. 8000a52: d021 beq.n 8000a98 <SD_disk_read+0xb0>
  1301. 8000a54: 2300 movs r3, #0
  1302. 8000a56: 603b str r3, [r7, #0]
  1303. 8000a58: e01e b.n 8000a98 <SD_disk_read+0xb0>
  1304. }
  1305. else
  1306. {
  1307. /* READ_MULTIPLE_BLOCK */
  1308. if (SD_SendCmd(CMD18, sector) == 0)
  1309. 8000a5a: 6879 ldr r1, [r7, #4]
  1310. 8000a5c: 2052 movs r0, #82 ; 0x52
  1311. 8000a5e: f7ff fe74 bl 800074a <SD_SendCmd>
  1312. 8000a62: 4603 mov r3, r0
  1313. 8000a64: 2b00 cmp r3, #0
  1314. 8000a66: d117 bne.n 8000a98 <SD_disk_read+0xb0>
  1315. {
  1316. do {
  1317. if (!SD_RxDataBlock(buff, 512)) break;
  1318. 8000a68: f44f 7100 mov.w r1, #512 ; 0x200
  1319. 8000a6c: 68b8 ldr r0, [r7, #8]
  1320. 8000a6e: f7ff fdfb bl 8000668 <SD_RxDataBlock>
  1321. 8000a72: 4603 mov r3, r0
  1322. 8000a74: 2b00 cmp r3, #0
  1323. 8000a76: d00a beq.n 8000a8e <SD_disk_read+0xa6>
  1324. buff += 512;
  1325. 8000a78: 68bb ldr r3, [r7, #8]
  1326. 8000a7a: f503 7300 add.w r3, r3, #512 ; 0x200
  1327. 8000a7e: 60bb str r3, [r7, #8]
  1328. } while (--count);
  1329. 8000a80: 683b ldr r3, [r7, #0]
  1330. 8000a82: 3b01 subs r3, #1
  1331. 8000a84: 603b str r3, [r7, #0]
  1332. 8000a86: 683b ldr r3, [r7, #0]
  1333. 8000a88: 2b00 cmp r3, #0
  1334. 8000a8a: d1ed bne.n 8000a68 <SD_disk_read+0x80>
  1335. 8000a8c: e000 b.n 8000a90 <SD_disk_read+0xa8>
  1336. if (!SD_RxDataBlock(buff, 512)) break;
  1337. 8000a8e: bf00 nop
  1338. /* STOP_TRANSMISSION */
  1339. SD_SendCmd(CMD12, 0);
  1340. 8000a90: 2100 movs r1, #0
  1341. 8000a92: 204c movs r0, #76 ; 0x4c
  1342. 8000a94: f7ff fe59 bl 800074a <SD_SendCmd>
  1343. }
  1344. }
  1345. /* Idle */
  1346. DESELECT();
  1347. 8000a98: f7ff fd08 bl 80004ac <DESELECT>
  1348. SPI_RxByte();
  1349. 8000a9c: f7ff fd48 bl 8000530 <SPI_RxByte>
  1350. return count ? RES_ERROR : RES_OK;
  1351. 8000aa0: 683b ldr r3, [r7, #0]
  1352. 8000aa2: 2b00 cmp r3, #0
  1353. 8000aa4: bf14 ite ne
  1354. 8000aa6: 2301 movne r3, #1
  1355. 8000aa8: 2300 moveq r3, #0
  1356. 8000aaa: b2db uxtb r3, r3
  1357. }
  1358. 8000aac: 4618 mov r0, r3
  1359. 8000aae: 3710 adds r7, #16
  1360. 8000ab0: 46bd mov sp, r7
  1361. 8000ab2: bd80 pop {r7, pc}
  1362. 8000ab4: 20000000 .word 0x20000000
  1363. 8000ab8: 200000a4 .word 0x200000a4
  1364. 08000abc <SD_disk_write>:
  1365. /* write sector */
  1366. #if _USE_WRITE == 1
  1367. DRESULT SD_disk_write(BYTE pdrv, const BYTE* buff, DWORD sector, UINT count)
  1368. {
  1369. 8000abc: b580 push {r7, lr}
  1370. 8000abe: b084 sub sp, #16
  1371. 8000ac0: af00 add r7, sp, #0
  1372. 8000ac2: 60b9 str r1, [r7, #8]
  1373. 8000ac4: 607a str r2, [r7, #4]
  1374. 8000ac6: 603b str r3, [r7, #0]
  1375. 8000ac8: 4603 mov r3, r0
  1376. 8000aca: 73fb strb r3, [r7, #15]
  1377. /* pdrv should be 0 */
  1378. if (pdrv || !count) return RES_PARERR;
  1379. 8000acc: 7bfb ldrb r3, [r7, #15]
  1380. 8000ace: 2b00 cmp r3, #0
  1381. 8000ad0: d102 bne.n 8000ad8 <SD_disk_write+0x1c>
  1382. 8000ad2: 683b ldr r3, [r7, #0]
  1383. 8000ad4: 2b00 cmp r3, #0
  1384. 8000ad6: d101 bne.n 8000adc <SD_disk_write+0x20>
  1385. 8000ad8: 2304 movs r3, #4
  1386. 8000ada: e06b b.n 8000bb4 <SD_disk_write+0xf8>
  1387. /* no disk */
  1388. if (Stat & STA_NOINIT) return RES_NOTRDY;
  1389. 8000adc: 4b37 ldr r3, [pc, #220] ; (8000bbc <SD_disk_write+0x100>)
  1390. 8000ade: 781b ldrb r3, [r3, #0]
  1391. 8000ae0: b2db uxtb r3, r3
  1392. 8000ae2: f003 0301 and.w r3, r3, #1
  1393. 8000ae6: 2b00 cmp r3, #0
  1394. 8000ae8: d001 beq.n 8000aee <SD_disk_write+0x32>
  1395. 8000aea: 2303 movs r3, #3
  1396. 8000aec: e062 b.n 8000bb4 <SD_disk_write+0xf8>
  1397. /* write protection */
  1398. if (Stat & STA_PROTECT) return RES_WRPRT;
  1399. 8000aee: 4b33 ldr r3, [pc, #204] ; (8000bbc <SD_disk_write+0x100>)
  1400. 8000af0: 781b ldrb r3, [r3, #0]
  1401. 8000af2: b2db uxtb r3, r3
  1402. 8000af4: f003 0304 and.w r3, r3, #4
  1403. 8000af8: 2b00 cmp r3, #0
  1404. 8000afa: d001 beq.n 8000b00 <SD_disk_write+0x44>
  1405. 8000afc: 2302 movs r3, #2
  1406. 8000afe: e059 b.n 8000bb4 <SD_disk_write+0xf8>
  1407. /* convert to byte address */
  1408. if (!(CardType & CT_SD2)) sector *= 512;
  1409. 8000b00: 4b2f ldr r3, [pc, #188] ; (8000bc0 <SD_disk_write+0x104>)
  1410. 8000b02: 781b ldrb r3, [r3, #0]
  1411. 8000b04: f003 0304 and.w r3, r3, #4
  1412. 8000b08: 2b00 cmp r3, #0
  1413. 8000b0a: d102 bne.n 8000b12 <SD_disk_write+0x56>
  1414. 8000b0c: 687b ldr r3, [r7, #4]
  1415. 8000b0e: 025b lsls r3, r3, #9
  1416. 8000b10: 607b str r3, [r7, #4]
  1417. SELECT();
  1418. 8000b12: f7ff fcbd bl 8000490 <SELECT>
  1419. if (count == 1)
  1420. 8000b16: 683b ldr r3, [r7, #0]
  1421. 8000b18: 2b01 cmp r3, #1
  1422. 8000b1a: d110 bne.n 8000b3e <SD_disk_write+0x82>
  1423. {
  1424. /* WRITE_BLOCK */
  1425. if ((SD_SendCmd(CMD24, sector) == 0) && SD_TxDataBlock(buff, 0xFE))
  1426. 8000b1c: 6879 ldr r1, [r7, #4]
  1427. 8000b1e: 2058 movs r0, #88 ; 0x58
  1428. 8000b20: f7ff fe13 bl 800074a <SD_SendCmd>
  1429. 8000b24: 4603 mov r3, r0
  1430. 8000b26: 2b00 cmp r3, #0
  1431. 8000b28: d13a bne.n 8000ba0 <SD_disk_write+0xe4>
  1432. 8000b2a: 21fe movs r1, #254 ; 0xfe
  1433. 8000b2c: 68b8 ldr r0, [r7, #8]
  1434. 8000b2e: f7ff fdc9 bl 80006c4 <SD_TxDataBlock>
  1435. 8000b32: 4603 mov r3, r0
  1436. 8000b34: 2b00 cmp r3, #0
  1437. 8000b36: d033 beq.n 8000ba0 <SD_disk_write+0xe4>
  1438. count = 0;
  1439. 8000b38: 2300 movs r3, #0
  1440. 8000b3a: 603b str r3, [r7, #0]
  1441. 8000b3c: e030 b.n 8000ba0 <SD_disk_write+0xe4>
  1442. }
  1443. else
  1444. {
  1445. /* WRITE_MULTIPLE_BLOCK */
  1446. if (CardType & CT_SD1)
  1447. 8000b3e: 4b20 ldr r3, [pc, #128] ; (8000bc0 <SD_disk_write+0x104>)
  1448. 8000b40: 781b ldrb r3, [r3, #0]
  1449. 8000b42: f003 0302 and.w r3, r3, #2
  1450. 8000b46: 2b00 cmp r3, #0
  1451. 8000b48: d007 beq.n 8000b5a <SD_disk_write+0x9e>
  1452. {
  1453. SD_SendCmd(CMD55, 0);
  1454. 8000b4a: 2100 movs r1, #0
  1455. 8000b4c: 2077 movs r0, #119 ; 0x77
  1456. 8000b4e: f7ff fdfc bl 800074a <SD_SendCmd>
  1457. SD_SendCmd(CMD23, count); /* ACMD23 */
  1458. 8000b52: 6839 ldr r1, [r7, #0]
  1459. 8000b54: 2057 movs r0, #87 ; 0x57
  1460. 8000b56: f7ff fdf8 bl 800074a <SD_SendCmd>
  1461. }
  1462. if (SD_SendCmd(CMD25, sector) == 0)
  1463. 8000b5a: 6879 ldr r1, [r7, #4]
  1464. 8000b5c: 2059 movs r0, #89 ; 0x59
  1465. 8000b5e: f7ff fdf4 bl 800074a <SD_SendCmd>
  1466. 8000b62: 4603 mov r3, r0
  1467. 8000b64: 2b00 cmp r3, #0
  1468. 8000b66: d11b bne.n 8000ba0 <SD_disk_write+0xe4>
  1469. {
  1470. do {
  1471. if(!SD_TxDataBlock(buff, 0xFC)) break;
  1472. 8000b68: 21fc movs r1, #252 ; 0xfc
  1473. 8000b6a: 68b8 ldr r0, [r7, #8]
  1474. 8000b6c: f7ff fdaa bl 80006c4 <SD_TxDataBlock>
  1475. 8000b70: 4603 mov r3, r0
  1476. 8000b72: 2b00 cmp r3, #0
  1477. 8000b74: d00a beq.n 8000b8c <SD_disk_write+0xd0>
  1478. buff += 512;
  1479. 8000b76: 68bb ldr r3, [r7, #8]
  1480. 8000b78: f503 7300 add.w r3, r3, #512 ; 0x200
  1481. 8000b7c: 60bb str r3, [r7, #8]
  1482. } while (--count);
  1483. 8000b7e: 683b ldr r3, [r7, #0]
  1484. 8000b80: 3b01 subs r3, #1
  1485. 8000b82: 603b str r3, [r7, #0]
  1486. 8000b84: 683b ldr r3, [r7, #0]
  1487. 8000b86: 2b00 cmp r3, #0
  1488. 8000b88: d1ee bne.n 8000b68 <SD_disk_write+0xac>
  1489. 8000b8a: e000 b.n 8000b8e <SD_disk_write+0xd2>
  1490. if(!SD_TxDataBlock(buff, 0xFC)) break;
  1491. 8000b8c: bf00 nop
  1492. /* STOP_TRAN token */
  1493. if(!SD_TxDataBlock(0, 0xFD))
  1494. 8000b8e: 21fd movs r1, #253 ; 0xfd
  1495. 8000b90: 2000 movs r0, #0
  1496. 8000b92: f7ff fd97 bl 80006c4 <SD_TxDataBlock>
  1497. 8000b96: 4603 mov r3, r0
  1498. 8000b98: 2b00 cmp r3, #0
  1499. 8000b9a: d101 bne.n 8000ba0 <SD_disk_write+0xe4>
  1500. {
  1501. count = 1;
  1502. 8000b9c: 2301 movs r3, #1
  1503. 8000b9e: 603b str r3, [r7, #0]
  1504. }
  1505. }
  1506. }
  1507. /* Idle */
  1508. DESELECT();
  1509. 8000ba0: f7ff fc84 bl 80004ac <DESELECT>
  1510. SPI_RxByte();
  1511. 8000ba4: f7ff fcc4 bl 8000530 <SPI_RxByte>
  1512. return count ? RES_ERROR : RES_OK;
  1513. 8000ba8: 683b ldr r3, [r7, #0]
  1514. 8000baa: 2b00 cmp r3, #0
  1515. 8000bac: bf14 ite ne
  1516. 8000bae: 2301 movne r3, #1
  1517. 8000bb0: 2300 moveq r3, #0
  1518. 8000bb2: b2db uxtb r3, r3
  1519. }
  1520. 8000bb4: 4618 mov r0, r3
  1521. 8000bb6: 3710 adds r7, #16
  1522. 8000bb8: 46bd mov sp, r7
  1523. 8000bba: bd80 pop {r7, pc}
  1524. 8000bbc: 20000000 .word 0x20000000
  1525. 8000bc0: 200000a4 .word 0x200000a4
  1526. 08000bc4 <SD_disk_ioctl>:
  1527. #endif /* _USE_WRITE */
  1528. /* ioctl */
  1529. DRESULT SD_disk_ioctl(BYTE drv, BYTE ctrl, void *buff)
  1530. {
  1531. 8000bc4: b590 push {r4, r7, lr}
  1532. 8000bc6: b08b sub sp, #44 ; 0x2c
  1533. 8000bc8: af00 add r7, sp, #0
  1534. 8000bca: 4603 mov r3, r0
  1535. 8000bcc: 603a str r2, [r7, #0]
  1536. 8000bce: 71fb strb r3, [r7, #7]
  1537. 8000bd0: 460b mov r3, r1
  1538. 8000bd2: 71bb strb r3, [r7, #6]
  1539. DRESULT res;
  1540. uint8_t n, csd[16], *ptr = buff;
  1541. 8000bd4: 683b ldr r3, [r7, #0]
  1542. 8000bd6: 623b str r3, [r7, #32]
  1543. WORD csize;
  1544. /* pdrv should be 0 */
  1545. if (drv) return RES_PARERR;
  1546. 8000bd8: 79fb ldrb r3, [r7, #7]
  1547. 8000bda: 2b00 cmp r3, #0
  1548. 8000bdc: d001 beq.n 8000be2 <SD_disk_ioctl+0x1e>
  1549. 8000bde: 2304 movs r3, #4
  1550. 8000be0: e113 b.n 8000e0a <SD_disk_ioctl+0x246>
  1551. res = RES_ERROR;
  1552. 8000be2: 2301 movs r3, #1
  1553. 8000be4: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1554. if (ctrl == CTRL_POWER)
  1555. 8000be8: 79bb ldrb r3, [r7, #6]
  1556. 8000bea: 2b05 cmp r3, #5
  1557. 8000bec: d121 bne.n 8000c32 <SD_disk_ioctl+0x6e>
  1558. {
  1559. switch (*ptr)
  1560. 8000bee: 6a3b ldr r3, [r7, #32]
  1561. 8000bf0: 781b ldrb r3, [r3, #0]
  1562. 8000bf2: 2b01 cmp r3, #1
  1563. 8000bf4: d009 beq.n 8000c0a <SD_disk_ioctl+0x46>
  1564. 8000bf6: 2b02 cmp r3, #2
  1565. 8000bf8: d00d beq.n 8000c16 <SD_disk_ioctl+0x52>
  1566. 8000bfa: 2b00 cmp r3, #0
  1567. 8000bfc: d115 bne.n 8000c2a <SD_disk_ioctl+0x66>
  1568. {
  1569. case 0:
  1570. SD_PowerOff(); /* Power Off */
  1571. 8000bfe: f7ff fd1d bl 800063c <SD_PowerOff>
  1572. res = RES_OK;
  1573. 8000c02: 2300 movs r3, #0
  1574. 8000c04: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1575. break;
  1576. 8000c08: e0fd b.n 8000e06 <SD_disk_ioctl+0x242>
  1577. case 1:
  1578. SD_PowerOn(); /* Power On */
  1579. 8000c0a: f7ff fcd5 bl 80005b8 <SD_PowerOn>
  1580. res = RES_OK;
  1581. 8000c0e: 2300 movs r3, #0
  1582. 8000c10: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1583. break;
  1584. 8000c14: e0f7 b.n 8000e06 <SD_disk_ioctl+0x242>
  1585. case 2:
  1586. *(ptr + 1) = SD_CheckPower();
  1587. 8000c16: 6a3b ldr r3, [r7, #32]
  1588. 8000c18: 1c5c adds r4, r3, #1
  1589. 8000c1a: f7ff fd1b bl 8000654 <SD_CheckPower>
  1590. 8000c1e: 4603 mov r3, r0
  1591. 8000c20: 7023 strb r3, [r4, #0]
  1592. res = RES_OK; /* Power Check */
  1593. 8000c22: 2300 movs r3, #0
  1594. 8000c24: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1595. break;
  1596. 8000c28: e0ed b.n 8000e06 <SD_disk_ioctl+0x242>
  1597. default:
  1598. res = RES_PARERR;
  1599. 8000c2a: 2304 movs r3, #4
  1600. 8000c2c: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1601. 8000c30: e0e9 b.n 8000e06 <SD_disk_ioctl+0x242>
  1602. }
  1603. }
  1604. else
  1605. {
  1606. /* no disk */
  1607. if (Stat & STA_NOINIT) return RES_NOTRDY;
  1608. 8000c32: 4b78 ldr r3, [pc, #480] ; (8000e14 <SD_disk_ioctl+0x250>)
  1609. 8000c34: 781b ldrb r3, [r3, #0]
  1610. 8000c36: b2db uxtb r3, r3
  1611. 8000c38: f003 0301 and.w r3, r3, #1
  1612. 8000c3c: 2b00 cmp r3, #0
  1613. 8000c3e: d001 beq.n 8000c44 <SD_disk_ioctl+0x80>
  1614. 8000c40: 2303 movs r3, #3
  1615. 8000c42: e0e2 b.n 8000e0a <SD_disk_ioctl+0x246>
  1616. SELECT();
  1617. 8000c44: f7ff fc24 bl 8000490 <SELECT>
  1618. switch (ctrl)
  1619. 8000c48: 79bb ldrb r3, [r7, #6]
  1620. 8000c4a: 2b0d cmp r3, #13
  1621. 8000c4c: f200 80cc bhi.w 8000de8 <SD_disk_ioctl+0x224>
  1622. 8000c50: a201 add r2, pc, #4 ; (adr r2, 8000c58 <SD_disk_ioctl+0x94>)
  1623. 8000c52: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  1624. 8000c56: bf00 nop
  1625. 8000c58: 08000d53 .word 0x08000d53
  1626. 8000c5c: 08000c91 .word 0x08000c91
  1627. 8000c60: 08000d43 .word 0x08000d43
  1628. 8000c64: 08000de9 .word 0x08000de9
  1629. 8000c68: 08000de9 .word 0x08000de9
  1630. 8000c6c: 08000de9 .word 0x08000de9
  1631. 8000c70: 08000de9 .word 0x08000de9
  1632. 8000c74: 08000de9 .word 0x08000de9
  1633. 8000c78: 08000de9 .word 0x08000de9
  1634. 8000c7c: 08000de9 .word 0x08000de9
  1635. 8000c80: 08000de9 .word 0x08000de9
  1636. 8000c84: 08000d65 .word 0x08000d65
  1637. 8000c88: 08000d89 .word 0x08000d89
  1638. 8000c8c: 08000dad .word 0x08000dad
  1639. {
  1640. case GET_SECTOR_COUNT:
  1641. /* SEND_CSD */
  1642. if ((SD_SendCmd(CMD9, 0) == 0) && SD_RxDataBlock(csd, 16))
  1643. 8000c90: 2100 movs r1, #0
  1644. 8000c92: 2049 movs r0, #73 ; 0x49
  1645. 8000c94: f7ff fd59 bl 800074a <SD_SendCmd>
  1646. 8000c98: 4603 mov r3, r0
  1647. 8000c9a: 2b00 cmp r3, #0
  1648. 8000c9c: f040 80a8 bne.w 8000df0 <SD_disk_ioctl+0x22c>
  1649. 8000ca0: f107 030c add.w r3, r7, #12
  1650. 8000ca4: 2110 movs r1, #16
  1651. 8000ca6: 4618 mov r0, r3
  1652. 8000ca8: f7ff fcde bl 8000668 <SD_RxDataBlock>
  1653. 8000cac: 4603 mov r3, r0
  1654. 8000cae: 2b00 cmp r3, #0
  1655. 8000cb0: f000 809e beq.w 8000df0 <SD_disk_ioctl+0x22c>
  1656. {
  1657. if ((csd[0] >> 6) == 1)
  1658. 8000cb4: 7b3b ldrb r3, [r7, #12]
  1659. 8000cb6: 099b lsrs r3, r3, #6
  1660. 8000cb8: b2db uxtb r3, r3
  1661. 8000cba: 2b01 cmp r3, #1
  1662. 8000cbc: d10e bne.n 8000cdc <SD_disk_ioctl+0x118>
  1663. {
  1664. /* SDC V2 */
  1665. csize = csd[9] + ((WORD) csd[8] << 8) + 1;
  1666. 8000cbe: 7d7b ldrb r3, [r7, #21]
  1667. 8000cc0: b29a uxth r2, r3
  1668. 8000cc2: 7d3b ldrb r3, [r7, #20]
  1669. 8000cc4: b29b uxth r3, r3
  1670. 8000cc6: 021b lsls r3, r3, #8
  1671. 8000cc8: b29b uxth r3, r3
  1672. 8000cca: 4413 add r3, r2
  1673. 8000ccc: b29b uxth r3, r3
  1674. 8000cce: 3301 adds r3, #1
  1675. 8000cd0: 83fb strh r3, [r7, #30]
  1676. *(DWORD*) buff = (DWORD) csize << 10;
  1677. 8000cd2: 8bfb ldrh r3, [r7, #30]
  1678. 8000cd4: 029a lsls r2, r3, #10
  1679. 8000cd6: 683b ldr r3, [r7, #0]
  1680. 8000cd8: 601a str r2, [r3, #0]
  1681. 8000cda: e02e b.n 8000d3a <SD_disk_ioctl+0x176>
  1682. }
  1683. else
  1684. {
  1685. /* MMC or SDC V1 */
  1686. n = (csd[5] & 15) + ((csd[10] & 128) >> 7) + ((csd[9] & 3) << 1) + 2;
  1687. 8000cdc: 7c7b ldrb r3, [r7, #17]
  1688. 8000cde: f003 030f and.w r3, r3, #15
  1689. 8000ce2: b2da uxtb r2, r3
  1690. 8000ce4: 7dbb ldrb r3, [r7, #22]
  1691. 8000ce6: 09db lsrs r3, r3, #7
  1692. 8000ce8: b2db uxtb r3, r3
  1693. 8000cea: 4413 add r3, r2
  1694. 8000cec: b2da uxtb r2, r3
  1695. 8000cee: 7d7b ldrb r3, [r7, #21]
  1696. 8000cf0: 005b lsls r3, r3, #1
  1697. 8000cf2: b2db uxtb r3, r3
  1698. 8000cf4: f003 0306 and.w r3, r3, #6
  1699. 8000cf8: b2db uxtb r3, r3
  1700. 8000cfa: 4413 add r3, r2
  1701. 8000cfc: b2db uxtb r3, r3
  1702. 8000cfe: 3302 adds r3, #2
  1703. 8000d00: f887 3026 strb.w r3, [r7, #38] ; 0x26
  1704. csize = (csd[8] >> 6) + ((WORD) csd[7] << 2) + ((WORD) (csd[6] & 3) << 10) + 1;
  1705. 8000d04: 7d3b ldrb r3, [r7, #20]
  1706. 8000d06: 099b lsrs r3, r3, #6
  1707. 8000d08: b2db uxtb r3, r3
  1708. 8000d0a: b29a uxth r2, r3
  1709. 8000d0c: 7cfb ldrb r3, [r7, #19]
  1710. 8000d0e: b29b uxth r3, r3
  1711. 8000d10: 009b lsls r3, r3, #2
  1712. 8000d12: b29b uxth r3, r3
  1713. 8000d14: 4413 add r3, r2
  1714. 8000d16: b29a uxth r2, r3
  1715. 8000d18: 7cbb ldrb r3, [r7, #18]
  1716. 8000d1a: 029b lsls r3, r3, #10
  1717. 8000d1c: b29b uxth r3, r3
  1718. 8000d1e: f403 6340 and.w r3, r3, #3072 ; 0xc00
  1719. 8000d22: b29b uxth r3, r3
  1720. 8000d24: 4413 add r3, r2
  1721. 8000d26: b29b uxth r3, r3
  1722. 8000d28: 3301 adds r3, #1
  1723. 8000d2a: 83fb strh r3, [r7, #30]
  1724. *(DWORD*) buff = (DWORD) csize << (n - 9);
  1725. 8000d2c: 8bfa ldrh r2, [r7, #30]
  1726. 8000d2e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  1727. 8000d32: 3b09 subs r3, #9
  1728. 8000d34: 409a lsls r2, r3
  1729. 8000d36: 683b ldr r3, [r7, #0]
  1730. 8000d38: 601a str r2, [r3, #0]
  1731. }
  1732. res = RES_OK;
  1733. 8000d3a: 2300 movs r3, #0
  1734. 8000d3c: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1735. }
  1736. break;
  1737. 8000d40: e056 b.n 8000df0 <SD_disk_ioctl+0x22c>
  1738. case GET_SECTOR_SIZE:
  1739. *(WORD*) buff = 512;
  1740. 8000d42: 683b ldr r3, [r7, #0]
  1741. 8000d44: f44f 7200 mov.w r2, #512 ; 0x200
  1742. 8000d48: 801a strh r2, [r3, #0]
  1743. res = RES_OK;
  1744. 8000d4a: 2300 movs r3, #0
  1745. 8000d4c: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1746. break;
  1747. 8000d50: e055 b.n 8000dfe <SD_disk_ioctl+0x23a>
  1748. case CTRL_SYNC:
  1749. if (SD_ReadyWait() == 0xFF) res = RES_OK;
  1750. 8000d52: f7ff fc17 bl 8000584 <SD_ReadyWait>
  1751. 8000d56: 4603 mov r3, r0
  1752. 8000d58: 2bff cmp r3, #255 ; 0xff
  1753. 8000d5a: d14b bne.n 8000df4 <SD_disk_ioctl+0x230>
  1754. 8000d5c: 2300 movs r3, #0
  1755. 8000d5e: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1756. break;
  1757. 8000d62: e047 b.n 8000df4 <SD_disk_ioctl+0x230>
  1758. case MMC_GET_CSD:
  1759. /* SEND_CSD */
  1760. if (SD_SendCmd(CMD9, 0) == 0 && SD_RxDataBlock(ptr, 16)) res = RES_OK;
  1761. 8000d64: 2100 movs r1, #0
  1762. 8000d66: 2049 movs r0, #73 ; 0x49
  1763. 8000d68: f7ff fcef bl 800074a <SD_SendCmd>
  1764. 8000d6c: 4603 mov r3, r0
  1765. 8000d6e: 2b00 cmp r3, #0
  1766. 8000d70: d142 bne.n 8000df8 <SD_disk_ioctl+0x234>
  1767. 8000d72: 2110 movs r1, #16
  1768. 8000d74: 6a38 ldr r0, [r7, #32]
  1769. 8000d76: f7ff fc77 bl 8000668 <SD_RxDataBlock>
  1770. 8000d7a: 4603 mov r3, r0
  1771. 8000d7c: 2b00 cmp r3, #0
  1772. 8000d7e: d03b beq.n 8000df8 <SD_disk_ioctl+0x234>
  1773. 8000d80: 2300 movs r3, #0
  1774. 8000d82: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1775. break;
  1776. 8000d86: e037 b.n 8000df8 <SD_disk_ioctl+0x234>
  1777. case MMC_GET_CID:
  1778. /* SEND_CID */
  1779. if (SD_SendCmd(CMD10, 0) == 0 && SD_RxDataBlock(ptr, 16)) res = RES_OK;
  1780. 8000d88: 2100 movs r1, #0
  1781. 8000d8a: 204a movs r0, #74 ; 0x4a
  1782. 8000d8c: f7ff fcdd bl 800074a <SD_SendCmd>
  1783. 8000d90: 4603 mov r3, r0
  1784. 8000d92: 2b00 cmp r3, #0
  1785. 8000d94: d132 bne.n 8000dfc <SD_disk_ioctl+0x238>
  1786. 8000d96: 2110 movs r1, #16
  1787. 8000d98: 6a38 ldr r0, [r7, #32]
  1788. 8000d9a: f7ff fc65 bl 8000668 <SD_RxDataBlock>
  1789. 8000d9e: 4603 mov r3, r0
  1790. 8000da0: 2b00 cmp r3, #0
  1791. 8000da2: d02b beq.n 8000dfc <SD_disk_ioctl+0x238>
  1792. 8000da4: 2300 movs r3, #0
  1793. 8000da6: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1794. break;
  1795. 8000daa: e027 b.n 8000dfc <SD_disk_ioctl+0x238>
  1796. case MMC_GET_OCR:
  1797. /* READ_OCR */
  1798. if (SD_SendCmd(CMD58, 0) == 0)
  1799. 8000dac: 2100 movs r1, #0
  1800. 8000dae: 207a movs r0, #122 ; 0x7a
  1801. 8000db0: f7ff fccb bl 800074a <SD_SendCmd>
  1802. 8000db4: 4603 mov r3, r0
  1803. 8000db6: 2b00 cmp r3, #0
  1804. 8000db8: d116 bne.n 8000de8 <SD_disk_ioctl+0x224>
  1805. {
  1806. for (n = 0; n < 4; n++)
  1807. 8000dba: 2300 movs r3, #0
  1808. 8000dbc: f887 3026 strb.w r3, [r7, #38] ; 0x26
  1809. 8000dc0: e00b b.n 8000dda <SD_disk_ioctl+0x216>
  1810. {
  1811. *ptr++ = SPI_RxByte();
  1812. 8000dc2: 6a3c ldr r4, [r7, #32]
  1813. 8000dc4: 1c63 adds r3, r4, #1
  1814. 8000dc6: 623b str r3, [r7, #32]
  1815. 8000dc8: f7ff fbb2 bl 8000530 <SPI_RxByte>
  1816. 8000dcc: 4603 mov r3, r0
  1817. 8000dce: 7023 strb r3, [r4, #0]
  1818. for (n = 0; n < 4; n++)
  1819. 8000dd0: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  1820. 8000dd4: 3301 adds r3, #1
  1821. 8000dd6: f887 3026 strb.w r3, [r7, #38] ; 0x26
  1822. 8000dda: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  1823. 8000dde: 2b03 cmp r3, #3
  1824. 8000de0: d9ef bls.n 8000dc2 <SD_disk_ioctl+0x1fe>
  1825. }
  1826. res = RES_OK;
  1827. 8000de2: 2300 movs r3, #0
  1828. 8000de4: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1829. }
  1830. default:
  1831. res = RES_PARERR;
  1832. 8000de8: 2304 movs r3, #4
  1833. 8000dea: f887 3027 strb.w r3, [r7, #39] ; 0x27
  1834. 8000dee: e006 b.n 8000dfe <SD_disk_ioctl+0x23a>
  1835. break;
  1836. 8000df0: bf00 nop
  1837. 8000df2: e004 b.n 8000dfe <SD_disk_ioctl+0x23a>
  1838. break;
  1839. 8000df4: bf00 nop
  1840. 8000df6: e002 b.n 8000dfe <SD_disk_ioctl+0x23a>
  1841. break;
  1842. 8000df8: bf00 nop
  1843. 8000dfa: e000 b.n 8000dfe <SD_disk_ioctl+0x23a>
  1844. break;
  1845. 8000dfc: bf00 nop
  1846. }
  1847. DESELECT();
  1848. 8000dfe: f7ff fb55 bl 80004ac <DESELECT>
  1849. SPI_RxByte();
  1850. 8000e02: f7ff fb95 bl 8000530 <SPI_RxByte>
  1851. }
  1852. return res;
  1853. 8000e06: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  1854. }
  1855. 8000e0a: 4618 mov r0, r3
  1856. 8000e0c: 372c adds r7, #44 ; 0x2c
  1857. 8000e0e: 46bd mov sp, r7
  1858. 8000e10: bd90 pop {r4, r7, pc}
  1859. 8000e12: bf00 nop
  1860. 8000e14: 20000000 .word 0x20000000
  1861. 08000e18 <transmit_uart>:
  1862. /* Private user code ---------------------------------------------------------*/
  1863. /* USER CODE BEGIN 0 */
  1864. // sending to UART
  1865. void transmit_uart(char *string){
  1866. 8000e18: b580 push {r7, lr}
  1867. 8000e1a: b084 sub sp, #16
  1868. 8000e1c: af00 add r7, sp, #0
  1869. 8000e1e: 6078 str r0, [r7, #4]
  1870. uint8_t len = strlen(string);
  1871. 8000e20: 6878 ldr r0, [r7, #4]
  1872. 8000e22: f7ff f9ab bl 800017c <strlen>
  1873. 8000e26: 4603 mov r3, r0
  1874. 8000e28: 73fb strb r3, [r7, #15]
  1875. HAL_UART_Transmit(&huart2, (uint8_t*) string, len, 200);
  1876. 8000e2a: 7bfb ldrb r3, [r7, #15]
  1877. 8000e2c: b29a uxth r2, r3
  1878. 8000e2e: 23c8 movs r3, #200 ; 0xc8
  1879. 8000e30: 6879 ldr r1, [r7, #4]
  1880. 8000e32: 4803 ldr r0, [pc, #12] ; (8000e40 <transmit_uart+0x28>)
  1881. 8000e34: f002 fd91 bl 800395a <HAL_UART_Transmit>
  1882. }
  1883. 8000e38: bf00 nop
  1884. 8000e3a: 3710 adds r7, #16
  1885. 8000e3c: 46bd mov sp, r7
  1886. 8000e3e: bd80 pop {r7, pc}
  1887. 8000e40: 200013f8 .word 0x200013f8
  1888. 08000e44 <main>:
  1889. /**
  1890. * @brief The application entry point.
  1891. * @retval int
  1892. */
  1893. int main(void)
  1894. {
  1895. 8000e44: b580 push {r7, lr}
  1896. 8000e46: b08e sub sp, #56 ; 0x38
  1897. 8000e48: af00 add r7, sp, #0
  1898. /* USER CODE END 1 */
  1899. /* MCU Configuration--------------------------------------------------------*/
  1900. /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  1901. HAL_Init();
  1902. 8000e4a: f000 fc22 bl 8001692 <HAL_Init>
  1903. /* USER CODE BEGIN Init */
  1904. /* USER CODE END Init */
  1905. /* Configure the system clock */
  1906. SystemClock_Config();
  1907. 8000e4e: f000 f907 bl 8001060 <SystemClock_Config>
  1908. /* USER CODE BEGIN SysInit */
  1909. /* USER CODE END SysInit */
  1910. /* Initialize all configured peripherals */
  1911. MX_GPIO_Init();
  1912. 8000e52: f000 fa0d bl 8001270 <MX_GPIO_Init>
  1913. MX_USART2_UART_Init();
  1914. 8000e56: f000 f9e1 bl 800121c <MX_USART2_UART_Init>
  1915. MX_SPI1_Init();
  1916. 8000e5a: f000 f9a9 bl 80011b0 <MX_SPI1_Init>
  1917. MX_FATFS_Init();
  1918. 8000e5e: f002 ff43 bl 8003ce8 <MX_FATFS_Init>
  1919. MX_ADC_Init();
  1920. 8000e62: f000 f94b bl 80010fc <MX_ADC_Init>
  1921. /* USER CODE BEGIN 2 */
  1922. fres = f_mount(&fs, "", 0);
  1923. 8000e66: 2200 movs r2, #0
  1924. 8000e68: 4967 ldr r1, [pc, #412] ; (8001008 <main+0x1c4>)
  1925. 8000e6a: 4868 ldr r0, [pc, #416] ; (800100c <main+0x1c8>)
  1926. 8000e6c: f005 f96a bl 8006144 <f_mount>
  1927. 8000e70: 4603 mov r3, r0
  1928. 8000e72: 461a mov r2, r3
  1929. 8000e74: 4b66 ldr r3, [pc, #408] ; (8001010 <main+0x1cc>)
  1930. 8000e76: 701a strb r2, [r3, #0]
  1931. if (fres == FR_OK) {
  1932. 8000e78: 4b65 ldr r3, [pc, #404] ; (8001010 <main+0x1cc>)
  1933. 8000e7a: 781b ldrb r3, [r3, #0]
  1934. 8000e7c: 2b00 cmp r3, #0
  1935. 8000e7e: d103 bne.n 8000e88 <main+0x44>
  1936. transmit_uart("SD card is mounted successfully!\r\n");
  1937. 8000e80: 4864 ldr r0, [pc, #400] ; (8001014 <main+0x1d0>)
  1938. 8000e82: f7ff ffc9 bl 8000e18 <transmit_uart>
  1939. 8000e86: e006 b.n 8000e96 <main+0x52>
  1940. } else if (fres != FR_OK) {
  1941. 8000e88: 4b61 ldr r3, [pc, #388] ; (8001010 <main+0x1cc>)
  1942. 8000e8a: 781b ldrb r3, [r3, #0]
  1943. 8000e8c: 2b00 cmp r3, #0
  1944. 8000e8e: d002 beq.n 8000e96 <main+0x52>
  1945. transmit_uart("SD card is not mounted!\r\n");
  1946. 8000e90: 4861 ldr r0, [pc, #388] ; (8001018 <main+0x1d4>)
  1947. 8000e92: f7ff ffc1 bl 8000e18 <transmit_uart>
  1948. transmit_uart("SD card is unmounted!\r\n");
  1949. } else if (fres != FR_OK) {
  1950. transmit_uart("SD card was not unmounted!\r\n");
  1951. }*/
  1952. int day = 12;
  1953. 8000e96: 230c movs r3, #12
  1954. 8000e98: 637b str r3, [r7, #52] ; 0x34
  1955. int month = 2;
  1956. 8000e9a: 2302 movs r3, #2
  1957. 8000e9c: 633b str r3, [r7, #48] ; 0x30
  1958. int year = 21;
  1959. 8000e9e: 2315 movs r3, #21
  1960. 8000ea0: 62fb str r3, [r7, #44] ; 0x2c
  1961. char str_month[20];
  1962. char str_year[20];
  1963. sprintf(txtVar, "%ld", day);
  1964. 8000ea2: 6b7a ldr r2, [r7, #52] ; 0x34
  1965. 8000ea4: 495d ldr r1, [pc, #372] ; (800101c <main+0x1d8>)
  1966. 8000ea6: 485e ldr r0, [pc, #376] ; (8001020 <main+0x1dc>)
  1967. 8000ea8: f006 f9a4 bl 80071f4 <siprintf>
  1968. sprintf(str_month, "%ld", month);
  1969. 8000eac: f107 0318 add.w r3, r7, #24
  1970. 8000eb0: 6b3a ldr r2, [r7, #48] ; 0x30
  1971. 8000eb2: 495a ldr r1, [pc, #360] ; (800101c <main+0x1d8>)
  1972. 8000eb4: 4618 mov r0, r3
  1973. 8000eb6: f006 f99d bl 80071f4 <siprintf>
  1974. sprintf(str_year, "%ld", year);
  1975. 8000eba: 1d3b adds r3, r7, #4
  1976. 8000ebc: 6afa ldr r2, [r7, #44] ; 0x2c
  1977. 8000ebe: 4957 ldr r1, [pc, #348] ; (800101c <main+0x1d8>)
  1978. 8000ec0: 4618 mov r0, r3
  1979. 8000ec2: f006 f997 bl 80071f4 <siprintf>
  1980. strcat(txtVar, ".");
  1981. 8000ec6: 4856 ldr r0, [pc, #344] ; (8001020 <main+0x1dc>)
  1982. 8000ec8: f7ff f958 bl 800017c <strlen>
  1983. 8000ecc: 4603 mov r3, r0
  1984. 8000ece: 461a mov r2, r3
  1985. 8000ed0: 4b53 ldr r3, [pc, #332] ; (8001020 <main+0x1dc>)
  1986. 8000ed2: 4413 add r3, r2
  1987. 8000ed4: 4953 ldr r1, [pc, #332] ; (8001024 <main+0x1e0>)
  1988. 8000ed6: 461a mov r2, r3
  1989. 8000ed8: 460b mov r3, r1
  1990. 8000eda: 881b ldrh r3, [r3, #0]
  1991. 8000edc: 8013 strh r3, [r2, #0]
  1992. strcat(str_month, ".");
  1993. 8000ede: f107 0318 add.w r3, r7, #24
  1994. 8000ee2: 4618 mov r0, r3
  1995. 8000ee4: f7ff f94a bl 800017c <strlen>
  1996. 8000ee8: 4603 mov r3, r0
  1997. 8000eea: 461a mov r2, r3
  1998. 8000eec: f107 0318 add.w r3, r7, #24
  1999. 8000ef0: 4413 add r3, r2
  2000. 8000ef2: 494c ldr r1, [pc, #304] ; (8001024 <main+0x1e0>)
  2001. 8000ef4: 461a mov r2, r3
  2002. 8000ef6: 460b mov r3, r1
  2003. 8000ef8: 881b ldrh r3, [r3, #0]
  2004. 8000efa: 8013 strh r3, [r2, #0]
  2005. strcat(str_year, "_");
  2006. 8000efc: 1d3b adds r3, r7, #4
  2007. 8000efe: 4618 mov r0, r3
  2008. 8000f00: f7ff f93c bl 800017c <strlen>
  2009. 8000f04: 4603 mov r3, r0
  2010. 8000f06: 461a mov r2, r3
  2011. 8000f08: 1d3b adds r3, r7, #4
  2012. 8000f0a: 4413 add r3, r2
  2013. 8000f0c: 4946 ldr r1, [pc, #280] ; (8001028 <main+0x1e4>)
  2014. 8000f0e: 461a mov r2, r3
  2015. 8000f10: 460b mov r3, r1
  2016. 8000f12: 881b ldrh r3, [r3, #0]
  2017. 8000f14: 8013 strh r3, [r2, #0]
  2018. strcat(txtVar, str_month);
  2019. 8000f16: f107 0318 add.w r3, r7, #24
  2020. 8000f1a: 4619 mov r1, r3
  2021. 8000f1c: 4840 ldr r0, [pc, #256] ; (8001020 <main+0x1dc>)
  2022. 8000f1e: f006 f989 bl 8007234 <strcat>
  2023. strcat(txtVar, str_year);
  2024. 8000f22: 1d3b adds r3, r7, #4
  2025. 8000f24: 4619 mov r1, r3
  2026. 8000f26: 483e ldr r0, [pc, #248] ; (8001020 <main+0x1dc>)
  2027. 8000f28: f006 f984 bl 8007234 <strcat>
  2028. strcat(txtVar, "Values.txt");
  2029. 8000f2c: 483c ldr r0, [pc, #240] ; (8001020 <main+0x1dc>)
  2030. 8000f2e: f7ff f925 bl 800017c <strlen>
  2031. 8000f32: 4603 mov r3, r0
  2032. 8000f34: 461a mov r2, r3
  2033. 8000f36: 4b3a ldr r3, [pc, #232] ; (8001020 <main+0x1dc>)
  2034. 8000f38: 4413 add r3, r2
  2035. 8000f3a: 493c ldr r1, [pc, #240] ; (800102c <main+0x1e8>)
  2036. 8000f3c: 461a mov r2, r3
  2037. 8000f3e: 460b mov r3, r1
  2038. 8000f40: cb03 ldmia r3!, {r0, r1}
  2039. 8000f42: 6010 str r0, [r2, #0]
  2040. 8000f44: 6051 str r1, [r2, #4]
  2041. 8000f46: 8819 ldrh r1, [r3, #0]
  2042. 8000f48: 789b ldrb r3, [r3, #2]
  2043. 8000f4a: 8111 strh r1, [r2, #8]
  2044. 8000f4c: 7293 strb r3, [r2, #10]
  2045. /* Infinite loop */
  2046. /* USER CODE BEGIN WHILE */
  2047. while (1)
  2048. {
  2049. /* USER CODE END WHILE */
  2050. HAL_Delay(5000);
  2051. 8000f4e: f241 3088 movw r0, #5000 ; 0x1388
  2052. 8000f52: f000 fc0d bl 8001770 <HAL_Delay>
  2053. // Start ADC Conversion
  2054. HAL_ADC_Start(&hadc);
  2055. 8000f56: 4836 ldr r0, [pc, #216] ; (8001030 <main+0x1ec>)
  2056. 8000f58: f000 fd72 bl 8001a40 <HAL_ADC_Start>
  2057. // Poll ADC1 Perihperal & TimeOut = 1mSec
  2058. HAL_ADC_PollForConversion(&hadc, 1);
  2059. 8000f5c: 2101 movs r1, #1
  2060. 8000f5e: 4834 ldr r0, [pc, #208] ; (8001030 <main+0x1ec>)
  2061. 8000f60: f000 fdce bl 8001b00 <HAL_ADC_PollForConversion>
  2062. // Read The ADC Conversion Result
  2063. AD_RES = HAL_ADC_GetValue(&hadc);
  2064. 8000f64: 4832 ldr r0, [pc, #200] ; (8001030 <main+0x1ec>)
  2065. 8000f66: f000 fe54 bl 8001c12 <HAL_ADC_GetValue>
  2066. 8000f6a: 4603 mov r3, r0
  2067. 8000f6c: b29a uxth r2, r3
  2068. 8000f6e: 4b31 ldr r3, [pc, #196] ; (8001034 <main+0x1f0>)
  2069. 8000f70: 801a strh r2, [r3, #0]
  2070. num++;
  2071. 8000f72: 4b31 ldr r3, [pc, #196] ; (8001038 <main+0x1f4>)
  2072. 8000f74: 681b ldr r3, [r3, #0]
  2073. 8000f76: 3301 adds r3, #1
  2074. 8000f78: 4a2f ldr r2, [pc, #188] ; (8001038 <main+0x1f4>)
  2075. 8000f7a: 6013 str r3, [r2, #0]
  2076. // FA_OPEN_APPEND opens file if it exists and if not then creates it,
  2077. // the pointer is set at the end of the file for appending
  2078. fres = f_open(&fil, txtVar, FA_OPEN_APPEND | FA_WRITE | FA_READ);
  2079. 8000f7c: 2233 movs r2, #51 ; 0x33
  2080. 8000f7e: 4928 ldr r1, [pc, #160] ; (8001020 <main+0x1dc>)
  2081. 8000f80: 482e ldr r0, [pc, #184] ; (800103c <main+0x1f8>)
  2082. 8000f82: f005 f925 bl 80061d0 <f_open>
  2083. 8000f86: 4603 mov r3, r0
  2084. 8000f88: 461a mov r2, r3
  2085. 8000f8a: 4b21 ldr r3, [pc, #132] ; (8001010 <main+0x1cc>)
  2086. 8000f8c: 701a strb r2, [r3, #0]
  2087. if (fres == FR_OK) {
  2088. 8000f8e: 4b20 ldr r3, [pc, #128] ; (8001010 <main+0x1cc>)
  2089. 8000f90: 781b ldrb r3, [r3, #0]
  2090. 8000f92: 2b00 cmp r3, #0
  2091. 8000f94: d103 bne.n 8000f9e <main+0x15a>
  2092. transmit_uart("File opened.\r\n");
  2093. 8000f96: 482a ldr r0, [pc, #168] ; (8001040 <main+0x1fc>)
  2094. 8000f98: f7ff ff3e bl 8000e18 <transmit_uart>
  2095. 8000f9c: e006 b.n 8000fac <main+0x168>
  2096. } else if (fres != FR_OK) {
  2097. 8000f9e: 4b1c ldr r3, [pc, #112] ; (8001010 <main+0x1cc>)
  2098. 8000fa0: 781b ldrb r3, [r3, #0]
  2099. 8000fa2: 2b00 cmp r3, #0
  2100. 8000fa4: d002 beq.n 8000fac <main+0x168>
  2101. transmit_uart("File was not opened!\r\n");
  2102. 8000fa6: 4827 ldr r0, [pc, #156] ; (8001044 <main+0x200>)
  2103. 8000fa8: f7ff ff36 bl 8000e18 <transmit_uart>
  2104. }
  2105. f_puts("ADC_value_", &fil);
  2106. 8000fac: 4923 ldr r1, [pc, #140] ; (800103c <main+0x1f8>)
  2107. 8000fae: 4826 ldr r0, [pc, #152] ; (8001048 <main+0x204>)
  2108. 8000fb0: f005 fd8d bl 8006ace <f_puts>
  2109. f_printf(&fil, "%d", num);
  2110. 8000fb4: 4b20 ldr r3, [pc, #128] ; (8001038 <main+0x1f4>)
  2111. 8000fb6: 681b ldr r3, [r3, #0]
  2112. 8000fb8: 461a mov r2, r3
  2113. 8000fba: 4924 ldr r1, [pc, #144] ; (800104c <main+0x208>)
  2114. 8000fbc: 481f ldr r0, [pc, #124] ; (800103c <main+0x1f8>)
  2115. 8000fbe: f005 fdab bl 8006b18 <f_printf>
  2116. f_puts(" = ", &fil);
  2117. 8000fc2: 491e ldr r1, [pc, #120] ; (800103c <main+0x1f8>)
  2118. 8000fc4: 4822 ldr r0, [pc, #136] ; (8001050 <main+0x20c>)
  2119. 8000fc6: f005 fd82 bl 8006ace <f_puts>
  2120. f_printf(&fil, "%d\n", AD_RES);
  2121. 8000fca: 4b1a ldr r3, [pc, #104] ; (8001034 <main+0x1f0>)
  2122. 8000fcc: 881b ldrh r3, [r3, #0]
  2123. 8000fce: 461a mov r2, r3
  2124. 8000fd0: 4920 ldr r1, [pc, #128] ; (8001054 <main+0x210>)
  2125. 8000fd2: 481a ldr r0, [pc, #104] ; (800103c <main+0x1f8>)
  2126. 8000fd4: f005 fda0 bl 8006b18 <f_printf>
  2127. /* Close file */
  2128. fres = f_close(&fil);
  2129. 8000fd8: 4818 ldr r0, [pc, #96] ; (800103c <main+0x1f8>)
  2130. 8000fda: f005 fcd7 bl 800698c <f_close>
  2131. 8000fde: 4603 mov r3, r0
  2132. 8000fe0: 461a mov r2, r3
  2133. 8000fe2: 4b0b ldr r3, [pc, #44] ; (8001010 <main+0x1cc>)
  2134. 8000fe4: 701a strb r2, [r3, #0]
  2135. if (fres == FR_OK) {
  2136. 8000fe6: 4b0a ldr r3, [pc, #40] ; (8001010 <main+0x1cc>)
  2137. 8000fe8: 781b ldrb r3, [r3, #0]
  2138. 8000fea: 2b00 cmp r3, #0
  2139. 8000fec: d103 bne.n 8000ff6 <main+0x1b2>
  2140. transmit_uart("File is closed.\r\n");
  2141. 8000fee: 481a ldr r0, [pc, #104] ; (8001058 <main+0x214>)
  2142. 8000ff0: f7ff ff12 bl 8000e18 <transmit_uart>
  2143. 8000ff4: e7ab b.n 8000f4e <main+0x10a>
  2144. } else if (fres != FR_OK) {
  2145. 8000ff6: 4b06 ldr r3, [pc, #24] ; (8001010 <main+0x1cc>)
  2146. 8000ff8: 781b ldrb r3, [r3, #0]
  2147. 8000ffa: 2b00 cmp r3, #0
  2148. 8000ffc: d0a7 beq.n 8000f4e <main+0x10a>
  2149. transmit_uart("File was not closed.\r\n");
  2150. 8000ffe: 4817 ldr r0, [pc, #92] ; (800105c <main+0x218>)
  2151. 8001000: f7ff ff0a bl 8000e18 <transmit_uart>
  2152. HAL_Delay(5000);
  2153. 8001004: e7a3 b.n 8000f4e <main+0x10a>
  2154. 8001006: bf00 nop
  2155. 8001008: 08007a50 .word 0x08007a50
  2156. 800100c: 200002f4 .word 0x200002f4
  2157. 8001010: 20001438 .word 0x20001438
  2158. 8001014: 08007a54 .word 0x08007a54
  2159. 8001018: 08007a78 .word 0x08007a78
  2160. 800101c: 08007a94 .word 0x08007a94
  2161. 8001020: 2000143c .word 0x2000143c
  2162. 8001024: 08007a98 .word 0x08007a98
  2163. 8001028: 08007a9c .word 0x08007a9c
  2164. 800102c: 08007aa0 .word 0x08007aa0
  2165. 8001030: 20001458 .word 0x20001458
  2166. 8001034: 200002f0 .word 0x200002f0
  2167. 8001038: 20001394 .word 0x20001394
  2168. 800103c: 200014ac .word 0x200014ac
  2169. 8001040: 08007aac .word 0x08007aac
  2170. 8001044: 08007abc .word 0x08007abc
  2171. 8001048: 08007ad4 .word 0x08007ad4
  2172. 800104c: 08007ae0 .word 0x08007ae0
  2173. 8001050: 08007ae4 .word 0x08007ae4
  2174. 8001054: 08007ae8 .word 0x08007ae8
  2175. 8001058: 08007aec .word 0x08007aec
  2176. 800105c: 08007b00 .word 0x08007b00
  2177. 08001060 <SystemClock_Config>:
  2178. /**
  2179. * @brief System Clock Configuration
  2180. * @retval None
  2181. */
  2182. void SystemClock_Config(void)
  2183. {
  2184. 8001060: b580 push {r7, lr}
  2185. 8001062: b092 sub sp, #72 ; 0x48
  2186. 8001064: af00 add r7, sp, #0
  2187. RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  2188. 8001066: f107 0314 add.w r3, r7, #20
  2189. 800106a: 2234 movs r2, #52 ; 0x34
  2190. 800106c: 2100 movs r1, #0
  2191. 800106e: 4618 mov r0, r3
  2192. 8001070: f006 f8b8 bl 80071e4 <memset>
  2193. RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
  2194. 8001074: 463b mov r3, r7
  2195. 8001076: 2200 movs r2, #0
  2196. 8001078: 601a str r2, [r3, #0]
  2197. 800107a: 605a str r2, [r3, #4]
  2198. 800107c: 609a str r2, [r3, #8]
  2199. 800107e: 60da str r2, [r3, #12]
  2200. 8001080: 611a str r2, [r3, #16]
  2201. /** Configure the main internal regulator output voltage
  2202. */
  2203. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  2204. 8001082: 4b1d ldr r3, [pc, #116] ; (80010f8 <SystemClock_Config+0x98>)
  2205. 8001084: 681b ldr r3, [r3, #0]
  2206. 8001086: f423 53c0 bic.w r3, r3, #6144 ; 0x1800
  2207. 800108a: 4a1b ldr r2, [pc, #108] ; (80010f8 <SystemClock_Config+0x98>)
  2208. 800108c: f443 6300 orr.w r3, r3, #2048 ; 0x800
  2209. 8001090: 6013 str r3, [r2, #0]
  2210. /** Initializes the RCC Oscillators according to the specified parameters
  2211. * in the RCC_OscInitTypeDef structure.
  2212. */
  2213. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  2214. 8001092: 2302 movs r3, #2
  2215. 8001094: 617b str r3, [r7, #20]
  2216. RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  2217. 8001096: 2301 movs r3, #1
  2218. 8001098: 623b str r3, [r7, #32]
  2219. RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
  2220. 800109a: 2310 movs r3, #16
  2221. 800109c: 627b str r3, [r7, #36] ; 0x24
  2222. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  2223. 800109e: 2302 movs r3, #2
  2224. 80010a0: 63bb str r3, [r7, #56] ; 0x38
  2225. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
  2226. 80010a2: 2300 movs r3, #0
  2227. 80010a4: 63fb str r3, [r7, #60] ; 0x3c
  2228. RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
  2229. 80010a6: f44f 2300 mov.w r3, #524288 ; 0x80000
  2230. 80010aa: 643b str r3, [r7, #64] ; 0x40
  2231. RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
  2232. 80010ac: f44f 0300 mov.w r3, #8388608 ; 0x800000
  2233. 80010b0: 647b str r3, [r7, #68] ; 0x44
  2234. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  2235. 80010b2: f107 0314 add.w r3, r7, #20
  2236. 80010b6: 4618 mov r0, r3
  2237. 80010b8: f001 fa10 bl 80024dc <HAL_RCC_OscConfig>
  2238. 80010bc: 4603 mov r3, r0
  2239. 80010be: 2b00 cmp r3, #0
  2240. 80010c0: d001 beq.n 80010c6 <SystemClock_Config+0x66>
  2241. {
  2242. Error_Handler();
  2243. 80010c2: f000 f93d bl 8001340 <Error_Handler>
  2244. }
  2245. /** Initializes the CPU, AHB and APB buses clocks
  2246. */
  2247. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
  2248. 80010c6: 230f movs r3, #15
  2249. 80010c8: 603b str r3, [r7, #0]
  2250. |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  2251. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  2252. 80010ca: 2303 movs r3, #3
  2253. 80010cc: 607b str r3, [r7, #4]
  2254. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  2255. 80010ce: 2300 movs r3, #0
  2256. 80010d0: 60bb str r3, [r7, #8]
  2257. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  2258. 80010d2: 2300 movs r3, #0
  2259. 80010d4: 60fb str r3, [r7, #12]
  2260. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
  2261. 80010d6: 2300 movs r3, #0
  2262. 80010d8: 613b str r3, [r7, #16]
  2263. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
  2264. 80010da: 463b mov r3, r7
  2265. 80010dc: 2101 movs r1, #1
  2266. 80010de: 4618 mov r0, r3
  2267. 80010e0: f001 fd2c bl 8002b3c <HAL_RCC_ClockConfig>
  2268. 80010e4: 4603 mov r3, r0
  2269. 80010e6: 2b00 cmp r3, #0
  2270. 80010e8: d001 beq.n 80010ee <SystemClock_Config+0x8e>
  2271. {
  2272. Error_Handler();
  2273. 80010ea: f000 f929 bl 8001340 <Error_Handler>
  2274. }
  2275. }
  2276. 80010ee: bf00 nop
  2277. 80010f0: 3748 adds r7, #72 ; 0x48
  2278. 80010f2: 46bd mov sp, r7
  2279. 80010f4: bd80 pop {r7, pc}
  2280. 80010f6: bf00 nop
  2281. 80010f8: 40007000 .word 0x40007000
  2282. 080010fc <MX_ADC_Init>:
  2283. * @brief ADC Initialization Function
  2284. * @param None
  2285. * @retval None
  2286. */
  2287. static void MX_ADC_Init(void)
  2288. {
  2289. 80010fc: b580 push {r7, lr}
  2290. 80010fe: b084 sub sp, #16
  2291. 8001100: af00 add r7, sp, #0
  2292. /* USER CODE BEGIN ADC_Init 0 */
  2293. /* USER CODE END ADC_Init 0 */
  2294. ADC_ChannelConfTypeDef sConfig = {0};
  2295. 8001102: 1d3b adds r3, r7, #4
  2296. 8001104: 2200 movs r2, #0
  2297. 8001106: 601a str r2, [r3, #0]
  2298. 8001108: 605a str r2, [r3, #4]
  2299. 800110a: 609a str r2, [r3, #8]
  2300. /* USER CODE BEGIN ADC_Init 1 */
  2301. /* USER CODE END ADC_Init 1 */
  2302. /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
  2303. */
  2304. hadc.Instance = ADC1;
  2305. 800110c: 4b26 ldr r3, [pc, #152] ; (80011a8 <MX_ADC_Init+0xac>)
  2306. 800110e: 4a27 ldr r2, [pc, #156] ; (80011ac <MX_ADC_Init+0xb0>)
  2307. 8001110: 601a str r2, [r3, #0]
  2308. hadc.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV1;
  2309. 8001112: 4b25 ldr r3, [pc, #148] ; (80011a8 <MX_ADC_Init+0xac>)
  2310. 8001114: 2200 movs r2, #0
  2311. 8001116: 605a str r2, [r3, #4]
  2312. hadc.Init.Resolution = ADC_RESOLUTION_12B;
  2313. 8001118: 4b23 ldr r3, [pc, #140] ; (80011a8 <MX_ADC_Init+0xac>)
  2314. 800111a: 2200 movs r2, #0
  2315. 800111c: 609a str r2, [r3, #8]
  2316. hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT;
  2317. 800111e: 4b22 ldr r3, [pc, #136] ; (80011a8 <MX_ADC_Init+0xac>)
  2318. 8001120: 2200 movs r2, #0
  2319. 8001122: 60da str r2, [r3, #12]
  2320. hadc.Init.ScanConvMode = ADC_SCAN_DISABLE;
  2321. 8001124: 4b20 ldr r3, [pc, #128] ; (80011a8 <MX_ADC_Init+0xac>)
  2322. 8001126: 2200 movs r2, #0
  2323. 8001128: 611a str r2, [r3, #16]
  2324. hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
  2325. 800112a: 4b1f ldr r3, [pc, #124] ; (80011a8 <MX_ADC_Init+0xac>)
  2326. 800112c: f44f 6280 mov.w r2, #1024 ; 0x400
  2327. 8001130: 615a str r2, [r3, #20]
  2328. hadc.Init.LowPowerAutoWait = ADC_AUTOWAIT_DISABLE;
  2329. 8001132: 4b1d ldr r3, [pc, #116] ; (80011a8 <MX_ADC_Init+0xac>)
  2330. 8001134: 2200 movs r2, #0
  2331. 8001136: 619a str r2, [r3, #24]
  2332. hadc.Init.LowPowerAutoPowerOff = ADC_AUTOPOWEROFF_DISABLE;
  2333. 8001138: 4b1b ldr r3, [pc, #108] ; (80011a8 <MX_ADC_Init+0xac>)
  2334. 800113a: 2200 movs r2, #0
  2335. 800113c: 61da str r2, [r3, #28]
  2336. hadc.Init.ChannelsBank = ADC_CHANNELS_BANK_A;
  2337. 800113e: 4b1a ldr r3, [pc, #104] ; (80011a8 <MX_ADC_Init+0xac>)
  2338. 8001140: 2200 movs r2, #0
  2339. 8001142: 621a str r2, [r3, #32]
  2340. hadc.Init.ContinuousConvMode = DISABLE;
  2341. 8001144: 4b18 ldr r3, [pc, #96] ; (80011a8 <MX_ADC_Init+0xac>)
  2342. 8001146: 2200 movs r2, #0
  2343. 8001148: f883 2024 strb.w r2, [r3, #36] ; 0x24
  2344. hadc.Init.NbrOfConversion = 1;
  2345. 800114c: 4b16 ldr r3, [pc, #88] ; (80011a8 <MX_ADC_Init+0xac>)
  2346. 800114e: 2201 movs r2, #1
  2347. 8001150: 629a str r2, [r3, #40] ; 0x28
  2348. hadc.Init.DiscontinuousConvMode = DISABLE;
  2349. 8001152: 4b15 ldr r3, [pc, #84] ; (80011a8 <MX_ADC_Init+0xac>)
  2350. 8001154: 2200 movs r2, #0
  2351. 8001156: f883 202c strb.w r2, [r3, #44] ; 0x2c
  2352. hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START;
  2353. 800115a: 4b13 ldr r3, [pc, #76] ; (80011a8 <MX_ADC_Init+0xac>)
  2354. 800115c: 2210 movs r2, #16
  2355. 800115e: 635a str r2, [r3, #52] ; 0x34
  2356. hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
  2357. 8001160: 4b11 ldr r3, [pc, #68] ; (80011a8 <MX_ADC_Init+0xac>)
  2358. 8001162: 2200 movs r2, #0
  2359. 8001164: 639a str r2, [r3, #56] ; 0x38
  2360. hadc.Init.DMAContinuousRequests = DISABLE;
  2361. 8001166: 4b10 ldr r3, [pc, #64] ; (80011a8 <MX_ADC_Init+0xac>)
  2362. 8001168: 2200 movs r2, #0
  2363. 800116a: f883 203c strb.w r2, [r3, #60] ; 0x3c
  2364. if (HAL_ADC_Init(&hadc) != HAL_OK)
  2365. 800116e: 480e ldr r0, [pc, #56] ; (80011a8 <MX_ADC_Init+0xac>)
  2366. 8001170: f000 fb20 bl 80017b4 <HAL_ADC_Init>
  2367. 8001174: 4603 mov r3, r0
  2368. 8001176: 2b00 cmp r3, #0
  2369. 8001178: d001 beq.n 800117e <MX_ADC_Init+0x82>
  2370. {
  2371. Error_Handler();
  2372. 800117a: f000 f8e1 bl 8001340 <Error_Handler>
  2373. }
  2374. /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
  2375. */
  2376. sConfig.Channel = ADC_CHANNEL_0;
  2377. 800117e: 2300 movs r3, #0
  2378. 8001180: 607b str r3, [r7, #4]
  2379. sConfig.Rank = ADC_REGULAR_RANK_1;
  2380. 8001182: 2301 movs r3, #1
  2381. 8001184: 60bb str r3, [r7, #8]
  2382. sConfig.SamplingTime = ADC_SAMPLETIME_384CYCLES;
  2383. 8001186: 2307 movs r3, #7
  2384. 8001188: 60fb str r3, [r7, #12]
  2385. if (HAL_ADC_ConfigChannel(&hadc, &sConfig) != HAL_OK)
  2386. 800118a: 1d3b adds r3, r7, #4
  2387. 800118c: 4619 mov r1, r3
  2388. 800118e: 4806 ldr r0, [pc, #24] ; (80011a8 <MX_ADC_Init+0xac>)
  2389. 8001190: f000 fd4c bl 8001c2c <HAL_ADC_ConfigChannel>
  2390. 8001194: 4603 mov r3, r0
  2391. 8001196: 2b00 cmp r3, #0
  2392. 8001198: d001 beq.n 800119e <MX_ADC_Init+0xa2>
  2393. {
  2394. Error_Handler();
  2395. 800119a: f000 f8d1 bl 8001340 <Error_Handler>
  2396. }
  2397. /* USER CODE BEGIN ADC_Init 2 */
  2398. /* USER CODE END ADC_Init 2 */
  2399. }
  2400. 800119e: bf00 nop
  2401. 80011a0: 3710 adds r7, #16
  2402. 80011a2: 46bd mov sp, r7
  2403. 80011a4: bd80 pop {r7, pc}
  2404. 80011a6: bf00 nop
  2405. 80011a8: 20001458 .word 0x20001458
  2406. 80011ac: 40012400 .word 0x40012400
  2407. 080011b0 <MX_SPI1_Init>:
  2408. * @brief SPI1 Initialization Function
  2409. * @param None
  2410. * @retval None
  2411. */
  2412. static void MX_SPI1_Init(void)
  2413. {
  2414. 80011b0: b580 push {r7, lr}
  2415. 80011b2: af00 add r7, sp, #0
  2416. /* USER CODE BEGIN SPI1_Init 1 */
  2417. /* USER CODE END SPI1_Init 1 */
  2418. /* SPI1 parameter configuration*/
  2419. hspi1.Instance = SPI1;
  2420. 80011b4: 4b17 ldr r3, [pc, #92] ; (8001214 <MX_SPI1_Init+0x64>)
  2421. 80011b6: 4a18 ldr r2, [pc, #96] ; (8001218 <MX_SPI1_Init+0x68>)
  2422. 80011b8: 601a str r2, [r3, #0]
  2423. hspi1.Init.Mode = SPI_MODE_MASTER;
  2424. 80011ba: 4b16 ldr r3, [pc, #88] ; (8001214 <MX_SPI1_Init+0x64>)
  2425. 80011bc: f44f 7282 mov.w r2, #260 ; 0x104
  2426. 80011c0: 605a str r2, [r3, #4]
  2427. hspi1.Init.Direction = SPI_DIRECTION_2LINES;
  2428. 80011c2: 4b14 ldr r3, [pc, #80] ; (8001214 <MX_SPI1_Init+0x64>)
  2429. 80011c4: 2200 movs r2, #0
  2430. 80011c6: 609a str r2, [r3, #8]
  2431. hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
  2432. 80011c8: 4b12 ldr r3, [pc, #72] ; (8001214 <MX_SPI1_Init+0x64>)
  2433. 80011ca: 2200 movs r2, #0
  2434. 80011cc: 60da str r2, [r3, #12]
  2435. hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
  2436. 80011ce: 4b11 ldr r3, [pc, #68] ; (8001214 <MX_SPI1_Init+0x64>)
  2437. 80011d0: 2200 movs r2, #0
  2438. 80011d2: 611a str r2, [r3, #16]
  2439. hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
  2440. 80011d4: 4b0f ldr r3, [pc, #60] ; (8001214 <MX_SPI1_Init+0x64>)
  2441. 80011d6: 2200 movs r2, #0
  2442. 80011d8: 615a str r2, [r3, #20]
  2443. hspi1.Init.NSS = SPI_NSS_SOFT;
  2444. 80011da: 4b0e ldr r3, [pc, #56] ; (8001214 <MX_SPI1_Init+0x64>)
  2445. 80011dc: f44f 7200 mov.w r2, #512 ; 0x200
  2446. 80011e0: 619a str r2, [r3, #24]
  2447. hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
  2448. 80011e2: 4b0c ldr r3, [pc, #48] ; (8001214 <MX_SPI1_Init+0x64>)
  2449. 80011e4: 2208 movs r2, #8
  2450. 80011e6: 61da str r2, [r3, #28]
  2451. hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
  2452. 80011e8: 4b0a ldr r3, [pc, #40] ; (8001214 <MX_SPI1_Init+0x64>)
  2453. 80011ea: 2200 movs r2, #0
  2454. 80011ec: 621a str r2, [r3, #32]
  2455. hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
  2456. 80011ee: 4b09 ldr r3, [pc, #36] ; (8001214 <MX_SPI1_Init+0x64>)
  2457. 80011f0: 2200 movs r2, #0
  2458. 80011f2: 625a str r2, [r3, #36] ; 0x24
  2459. hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  2460. 80011f4: 4b07 ldr r3, [pc, #28] ; (8001214 <MX_SPI1_Init+0x64>)
  2461. 80011f6: 2200 movs r2, #0
  2462. 80011f8: 629a str r2, [r3, #40] ; 0x28
  2463. hspi1.Init.CRCPolynomial = 10;
  2464. 80011fa: 4b06 ldr r3, [pc, #24] ; (8001214 <MX_SPI1_Init+0x64>)
  2465. 80011fc: 220a movs r2, #10
  2466. 80011fe: 62da str r2, [r3, #44] ; 0x2c
  2467. if (HAL_SPI_Init(&hspi1) != HAL_OK)
  2468. 8001200: 4804 ldr r0, [pc, #16] ; (8001214 <MX_SPI1_Init+0x64>)
  2469. 8001202: f001 ff2b bl 800305c <HAL_SPI_Init>
  2470. 8001206: 4603 mov r3, r0
  2471. 8001208: 2b00 cmp r3, #0
  2472. 800120a: d001 beq.n 8001210 <MX_SPI1_Init+0x60>
  2473. {
  2474. Error_Handler();
  2475. 800120c: f000 f898 bl 8001340 <Error_Handler>
  2476. }
  2477. /* USER CODE BEGIN SPI1_Init 2 */
  2478. /* USER CODE END SPI1_Init 2 */
  2479. }
  2480. 8001210: bf00 nop
  2481. 8001212: bd80 pop {r7, pc}
  2482. 8001214: 200013a0 .word 0x200013a0
  2483. 8001218: 40013000 .word 0x40013000
  2484. 0800121c <MX_USART2_UART_Init>:
  2485. * @brief USART2 Initialization Function
  2486. * @param None
  2487. * @retval None
  2488. */
  2489. static void MX_USART2_UART_Init(void)
  2490. {
  2491. 800121c: b580 push {r7, lr}
  2492. 800121e: af00 add r7, sp, #0
  2493. /* USER CODE END USART2_Init 0 */
  2494. /* USER CODE BEGIN USART2_Init 1 */
  2495. /* USER CODE END USART2_Init 1 */
  2496. huart2.Instance = USART2;
  2497. 8001220: 4b11 ldr r3, [pc, #68] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2498. 8001222: 4a12 ldr r2, [pc, #72] ; (800126c <MX_USART2_UART_Init+0x50>)
  2499. 8001224: 601a str r2, [r3, #0]
  2500. huart2.Init.BaudRate = 115200;
  2501. 8001226: 4b10 ldr r3, [pc, #64] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2502. 8001228: f44f 32e1 mov.w r2, #115200 ; 0x1c200
  2503. 800122c: 605a str r2, [r3, #4]
  2504. huart2.Init.WordLength = UART_WORDLENGTH_8B;
  2505. 800122e: 4b0e ldr r3, [pc, #56] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2506. 8001230: 2200 movs r2, #0
  2507. 8001232: 609a str r2, [r3, #8]
  2508. huart2.Init.StopBits = UART_STOPBITS_1;
  2509. 8001234: 4b0c ldr r3, [pc, #48] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2510. 8001236: 2200 movs r2, #0
  2511. 8001238: 60da str r2, [r3, #12]
  2512. huart2.Init.Parity = UART_PARITY_NONE;
  2513. 800123a: 4b0b ldr r3, [pc, #44] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2514. 800123c: 2200 movs r2, #0
  2515. 800123e: 611a str r2, [r3, #16]
  2516. huart2.Init.Mode = UART_MODE_TX_RX;
  2517. 8001240: 4b09 ldr r3, [pc, #36] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2518. 8001242: 220c movs r2, #12
  2519. 8001244: 615a str r2, [r3, #20]
  2520. huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
  2521. 8001246: 4b08 ldr r3, [pc, #32] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2522. 8001248: 2200 movs r2, #0
  2523. 800124a: 619a str r2, [r3, #24]
  2524. huart2.Init.OverSampling = UART_OVERSAMPLING_16;
  2525. 800124c: 4b06 ldr r3, [pc, #24] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2526. 800124e: 2200 movs r2, #0
  2527. 8001250: 61da str r2, [r3, #28]
  2528. if (HAL_UART_Init(&huart2) != HAL_OK)
  2529. 8001252: 4805 ldr r0, [pc, #20] ; (8001268 <MX_USART2_UART_Init+0x4c>)
  2530. 8001254: f002 fb34 bl 80038c0 <HAL_UART_Init>
  2531. 8001258: 4603 mov r3, r0
  2532. 800125a: 2b00 cmp r3, #0
  2533. 800125c: d001 beq.n 8001262 <MX_USART2_UART_Init+0x46>
  2534. {
  2535. Error_Handler();
  2536. 800125e: f000 f86f bl 8001340 <Error_Handler>
  2537. }
  2538. /* USER CODE BEGIN USART2_Init 2 */
  2539. /* USER CODE END USART2_Init 2 */
  2540. }
  2541. 8001262: bf00 nop
  2542. 8001264: bd80 pop {r7, pc}
  2543. 8001266: bf00 nop
  2544. 8001268: 200013f8 .word 0x200013f8
  2545. 800126c: 40004400 .word 0x40004400
  2546. 08001270 <MX_GPIO_Init>:
  2547. * @brief GPIO Initialization Function
  2548. * @param None
  2549. * @retval None
  2550. */
  2551. static void MX_GPIO_Init(void)
  2552. {
  2553. 8001270: b580 push {r7, lr}
  2554. 8001272: b08a sub sp, #40 ; 0x28
  2555. 8001274: af00 add r7, sp, #0
  2556. GPIO_InitTypeDef GPIO_InitStruct = {0};
  2557. 8001276: f107 0314 add.w r3, r7, #20
  2558. 800127a: 2200 movs r2, #0
  2559. 800127c: 601a str r2, [r3, #0]
  2560. 800127e: 605a str r2, [r3, #4]
  2561. 8001280: 609a str r2, [r3, #8]
  2562. 8001282: 60da str r2, [r3, #12]
  2563. 8001284: 611a str r2, [r3, #16]
  2564. /* GPIO Ports Clock Enable */
  2565. __HAL_RCC_GPIOC_CLK_ENABLE();
  2566. 8001286: 4b2a ldr r3, [pc, #168] ; (8001330 <MX_GPIO_Init+0xc0>)
  2567. 8001288: 69db ldr r3, [r3, #28]
  2568. 800128a: 4a29 ldr r2, [pc, #164] ; (8001330 <MX_GPIO_Init+0xc0>)
  2569. 800128c: f043 0304 orr.w r3, r3, #4
  2570. 8001290: 61d3 str r3, [r2, #28]
  2571. 8001292: 4b27 ldr r3, [pc, #156] ; (8001330 <MX_GPIO_Init+0xc0>)
  2572. 8001294: 69db ldr r3, [r3, #28]
  2573. 8001296: f003 0304 and.w r3, r3, #4
  2574. 800129a: 613b str r3, [r7, #16]
  2575. 800129c: 693b ldr r3, [r7, #16]
  2576. __HAL_RCC_GPIOH_CLK_ENABLE();
  2577. 800129e: 4b24 ldr r3, [pc, #144] ; (8001330 <MX_GPIO_Init+0xc0>)
  2578. 80012a0: 69db ldr r3, [r3, #28]
  2579. 80012a2: 4a23 ldr r2, [pc, #140] ; (8001330 <MX_GPIO_Init+0xc0>)
  2580. 80012a4: f043 0320 orr.w r3, r3, #32
  2581. 80012a8: 61d3 str r3, [r2, #28]
  2582. 80012aa: 4b21 ldr r3, [pc, #132] ; (8001330 <MX_GPIO_Init+0xc0>)
  2583. 80012ac: 69db ldr r3, [r3, #28]
  2584. 80012ae: f003 0320 and.w r3, r3, #32
  2585. 80012b2: 60fb str r3, [r7, #12]
  2586. 80012b4: 68fb ldr r3, [r7, #12]
  2587. __HAL_RCC_GPIOA_CLK_ENABLE();
  2588. 80012b6: 4b1e ldr r3, [pc, #120] ; (8001330 <MX_GPIO_Init+0xc0>)
  2589. 80012b8: 69db ldr r3, [r3, #28]
  2590. 80012ba: 4a1d ldr r2, [pc, #116] ; (8001330 <MX_GPIO_Init+0xc0>)
  2591. 80012bc: f043 0301 orr.w r3, r3, #1
  2592. 80012c0: 61d3 str r3, [r2, #28]
  2593. 80012c2: 4b1b ldr r3, [pc, #108] ; (8001330 <MX_GPIO_Init+0xc0>)
  2594. 80012c4: 69db ldr r3, [r3, #28]
  2595. 80012c6: f003 0301 and.w r3, r3, #1
  2596. 80012ca: 60bb str r3, [r7, #8]
  2597. 80012cc: 68bb ldr r3, [r7, #8]
  2598. __HAL_RCC_GPIOB_CLK_ENABLE();
  2599. 80012ce: 4b18 ldr r3, [pc, #96] ; (8001330 <MX_GPIO_Init+0xc0>)
  2600. 80012d0: 69db ldr r3, [r3, #28]
  2601. 80012d2: 4a17 ldr r2, [pc, #92] ; (8001330 <MX_GPIO_Init+0xc0>)
  2602. 80012d4: f043 0302 orr.w r3, r3, #2
  2603. 80012d8: 61d3 str r3, [r2, #28]
  2604. 80012da: 4b15 ldr r3, [pc, #84] ; (8001330 <MX_GPIO_Init+0xc0>)
  2605. 80012dc: 69db ldr r3, [r3, #28]
  2606. 80012de: f003 0302 and.w r3, r3, #2
  2607. 80012e2: 607b str r3, [r7, #4]
  2608. 80012e4: 687b ldr r3, [r7, #4]
  2609. /*Configure GPIO pin Output Level */
  2610. HAL_GPIO_WritePin(GPIOB, GPIO_PIN_6, GPIO_PIN_SET);
  2611. 80012e6: 2201 movs r2, #1
  2612. 80012e8: 2140 movs r1, #64 ; 0x40
  2613. 80012ea: 4812 ldr r0, [pc, #72] ; (8001334 <MX_GPIO_Init+0xc4>)
  2614. 80012ec: f001 f8de bl 80024ac <HAL_GPIO_WritePin>
  2615. /*Configure GPIO pin : B1_Pin */
  2616. GPIO_InitStruct.Pin = B1_Pin;
  2617. 80012f0: f44f 5300 mov.w r3, #8192 ; 0x2000
  2618. 80012f4: 617b str r3, [r7, #20]
  2619. GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
  2620. 80012f6: 4b10 ldr r3, [pc, #64] ; (8001338 <MX_GPIO_Init+0xc8>)
  2621. 80012f8: 61bb str r3, [r7, #24]
  2622. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2623. 80012fa: 2300 movs r3, #0
  2624. 80012fc: 61fb str r3, [r7, #28]
  2625. HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
  2626. 80012fe: f107 0314 add.w r3, r7, #20
  2627. 8001302: 4619 mov r1, r3
  2628. 8001304: 480d ldr r0, [pc, #52] ; (800133c <MX_GPIO_Init+0xcc>)
  2629. 8001306: f000 ff43 bl 8002190 <HAL_GPIO_Init>
  2630. /*Configure GPIO pin : PB6 */
  2631. GPIO_InitStruct.Pin = GPIO_PIN_6;
  2632. 800130a: 2340 movs r3, #64 ; 0x40
  2633. 800130c: 617b str r3, [r7, #20]
  2634. GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  2635. 800130e: 2301 movs r3, #1
  2636. 8001310: 61bb str r3, [r7, #24]
  2637. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2638. 8001312: 2300 movs r3, #0
  2639. 8001314: 61fb str r3, [r7, #28]
  2640. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
  2641. 8001316: 2302 movs r3, #2
  2642. 8001318: 623b str r3, [r7, #32]
  2643. HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
  2644. 800131a: f107 0314 add.w r3, r7, #20
  2645. 800131e: 4619 mov r1, r3
  2646. 8001320: 4804 ldr r0, [pc, #16] ; (8001334 <MX_GPIO_Init+0xc4>)
  2647. 8001322: f000 ff35 bl 8002190 <HAL_GPIO_Init>
  2648. }
  2649. 8001326: bf00 nop
  2650. 8001328: 3728 adds r7, #40 ; 0x28
  2651. 800132a: 46bd mov sp, r7
  2652. 800132c: bd80 pop {r7, pc}
  2653. 800132e: bf00 nop
  2654. 8001330: 40023800 .word 0x40023800
  2655. 8001334: 40020400 .word 0x40020400
  2656. 8001338: 10110000 .word 0x10110000
  2657. 800133c: 40020800 .word 0x40020800
  2658. 08001340 <Error_Handler>:
  2659. /**
  2660. * @brief This function is executed in case of error occurrence.
  2661. * @retval None
  2662. */
  2663. void Error_Handler(void)
  2664. {
  2665. 8001340: b480 push {r7}
  2666. 8001342: af00 add r7, sp, #0
  2667. /* USER CODE BEGIN Error_Handler_Debug */
  2668. /* User can add his own implementation to report the HAL error return state */
  2669. /* USER CODE END Error_Handler_Debug */
  2670. }
  2671. 8001344: bf00 nop
  2672. 8001346: 46bd mov sp, r7
  2673. 8001348: bc80 pop {r7}
  2674. 800134a: 4770 bx lr
  2675. 0800134c <HAL_MspInit>:
  2676. /* USER CODE END 0 */
  2677. /**
  2678. * Initializes the Global MSP.
  2679. */
  2680. void HAL_MspInit(void)
  2681. {
  2682. 800134c: b580 push {r7, lr}
  2683. 800134e: b084 sub sp, #16
  2684. 8001350: af00 add r7, sp, #0
  2685. /* USER CODE BEGIN MspInit 0 */
  2686. /* USER CODE END MspInit 0 */
  2687. __HAL_RCC_COMP_CLK_ENABLE();
  2688. 8001352: 4b15 ldr r3, [pc, #84] ; (80013a8 <HAL_MspInit+0x5c>)
  2689. 8001354: 6a5b ldr r3, [r3, #36] ; 0x24
  2690. 8001356: 4a14 ldr r2, [pc, #80] ; (80013a8 <HAL_MspInit+0x5c>)
  2691. 8001358: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000
  2692. 800135c: 6253 str r3, [r2, #36] ; 0x24
  2693. 800135e: 4b12 ldr r3, [pc, #72] ; (80013a8 <HAL_MspInit+0x5c>)
  2694. 8001360: 6a5b ldr r3, [r3, #36] ; 0x24
  2695. 8001362: f003 4300 and.w r3, r3, #2147483648 ; 0x80000000
  2696. 8001366: 60fb str r3, [r7, #12]
  2697. 8001368: 68fb ldr r3, [r7, #12]
  2698. __HAL_RCC_SYSCFG_CLK_ENABLE();
  2699. 800136a: 4b0f ldr r3, [pc, #60] ; (80013a8 <HAL_MspInit+0x5c>)
  2700. 800136c: 6a1b ldr r3, [r3, #32]
  2701. 800136e: 4a0e ldr r2, [pc, #56] ; (80013a8 <HAL_MspInit+0x5c>)
  2702. 8001370: f043 0301 orr.w r3, r3, #1
  2703. 8001374: 6213 str r3, [r2, #32]
  2704. 8001376: 4b0c ldr r3, [pc, #48] ; (80013a8 <HAL_MspInit+0x5c>)
  2705. 8001378: 6a1b ldr r3, [r3, #32]
  2706. 800137a: f003 0301 and.w r3, r3, #1
  2707. 800137e: 60bb str r3, [r7, #8]
  2708. 8001380: 68bb ldr r3, [r7, #8]
  2709. __HAL_RCC_PWR_CLK_ENABLE();
  2710. 8001382: 4b09 ldr r3, [pc, #36] ; (80013a8 <HAL_MspInit+0x5c>)
  2711. 8001384: 6a5b ldr r3, [r3, #36] ; 0x24
  2712. 8001386: 4a08 ldr r2, [pc, #32] ; (80013a8 <HAL_MspInit+0x5c>)
  2713. 8001388: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  2714. 800138c: 6253 str r3, [r2, #36] ; 0x24
  2715. 800138e: 4b06 ldr r3, [pc, #24] ; (80013a8 <HAL_MspInit+0x5c>)
  2716. 8001390: 6a5b ldr r3, [r3, #36] ; 0x24
  2717. 8001392: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  2718. 8001396: 607b str r3, [r7, #4]
  2719. 8001398: 687b ldr r3, [r7, #4]
  2720. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
  2721. 800139a: 2007 movs r0, #7
  2722. 800139c: f000 feb8 bl 8002110 <HAL_NVIC_SetPriorityGrouping>
  2723. /* System interrupt init*/
  2724. /* USER CODE BEGIN MspInit 1 */
  2725. /* USER CODE END MspInit 1 */
  2726. }
  2727. 80013a0: bf00 nop
  2728. 80013a2: 3710 adds r7, #16
  2729. 80013a4: 46bd mov sp, r7
  2730. 80013a6: bd80 pop {r7, pc}
  2731. 80013a8: 40023800 .word 0x40023800
  2732. 080013ac <HAL_ADC_MspInit>:
  2733. * This function configures the hardware resources used in this example
  2734. * @param hadc: ADC handle pointer
  2735. * @retval None
  2736. */
  2737. void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
  2738. {
  2739. 80013ac: b580 push {r7, lr}
  2740. 80013ae: b08a sub sp, #40 ; 0x28
  2741. 80013b0: af00 add r7, sp, #0
  2742. 80013b2: 6078 str r0, [r7, #4]
  2743. GPIO_InitTypeDef GPIO_InitStruct = {0};
  2744. 80013b4: f107 0314 add.w r3, r7, #20
  2745. 80013b8: 2200 movs r2, #0
  2746. 80013ba: 601a str r2, [r3, #0]
  2747. 80013bc: 605a str r2, [r3, #4]
  2748. 80013be: 609a str r2, [r3, #8]
  2749. 80013c0: 60da str r2, [r3, #12]
  2750. 80013c2: 611a str r2, [r3, #16]
  2751. if(hadc->Instance==ADC1)
  2752. 80013c4: 687b ldr r3, [r7, #4]
  2753. 80013c6: 681b ldr r3, [r3, #0]
  2754. 80013c8: 4a15 ldr r2, [pc, #84] ; (8001420 <HAL_ADC_MspInit+0x74>)
  2755. 80013ca: 4293 cmp r3, r2
  2756. 80013cc: d123 bne.n 8001416 <HAL_ADC_MspInit+0x6a>
  2757. {
  2758. /* USER CODE BEGIN ADC1_MspInit 0 */
  2759. /* USER CODE END ADC1_MspInit 0 */
  2760. /* Peripheral clock enable */
  2761. __HAL_RCC_ADC1_CLK_ENABLE();
  2762. 80013ce: 4b15 ldr r3, [pc, #84] ; (8001424 <HAL_ADC_MspInit+0x78>)
  2763. 80013d0: 6a1b ldr r3, [r3, #32]
  2764. 80013d2: 4a14 ldr r2, [pc, #80] ; (8001424 <HAL_ADC_MspInit+0x78>)
  2765. 80013d4: f443 7300 orr.w r3, r3, #512 ; 0x200
  2766. 80013d8: 6213 str r3, [r2, #32]
  2767. 80013da: 4b12 ldr r3, [pc, #72] ; (8001424 <HAL_ADC_MspInit+0x78>)
  2768. 80013dc: 6a1b ldr r3, [r3, #32]
  2769. 80013de: f403 7300 and.w r3, r3, #512 ; 0x200
  2770. 80013e2: 613b str r3, [r7, #16]
  2771. 80013e4: 693b ldr r3, [r7, #16]
  2772. __HAL_RCC_GPIOA_CLK_ENABLE();
  2773. 80013e6: 4b0f ldr r3, [pc, #60] ; (8001424 <HAL_ADC_MspInit+0x78>)
  2774. 80013e8: 69db ldr r3, [r3, #28]
  2775. 80013ea: 4a0e ldr r2, [pc, #56] ; (8001424 <HAL_ADC_MspInit+0x78>)
  2776. 80013ec: f043 0301 orr.w r3, r3, #1
  2777. 80013f0: 61d3 str r3, [r2, #28]
  2778. 80013f2: 4b0c ldr r3, [pc, #48] ; (8001424 <HAL_ADC_MspInit+0x78>)
  2779. 80013f4: 69db ldr r3, [r3, #28]
  2780. 80013f6: f003 0301 and.w r3, r3, #1
  2781. 80013fa: 60fb str r3, [r7, #12]
  2782. 80013fc: 68fb ldr r3, [r7, #12]
  2783. /**ADC GPIO Configuration
  2784. PA0-WKUP1 ------> ADC_IN0
  2785. */
  2786. GPIO_InitStruct.Pin = GPIO_PIN_0;
  2787. 80013fe: 2301 movs r3, #1
  2788. 8001400: 617b str r3, [r7, #20]
  2789. GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
  2790. 8001402: 2303 movs r3, #3
  2791. 8001404: 61bb str r3, [r7, #24]
  2792. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2793. 8001406: 2300 movs r3, #0
  2794. 8001408: 61fb str r3, [r7, #28]
  2795. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  2796. 800140a: f107 0314 add.w r3, r7, #20
  2797. 800140e: 4619 mov r1, r3
  2798. 8001410: 4805 ldr r0, [pc, #20] ; (8001428 <HAL_ADC_MspInit+0x7c>)
  2799. 8001412: f000 febd bl 8002190 <HAL_GPIO_Init>
  2800. /* USER CODE BEGIN ADC1_MspInit 1 */
  2801. /* USER CODE END ADC1_MspInit 1 */
  2802. }
  2803. }
  2804. 8001416: bf00 nop
  2805. 8001418: 3728 adds r7, #40 ; 0x28
  2806. 800141a: 46bd mov sp, r7
  2807. 800141c: bd80 pop {r7, pc}
  2808. 800141e: bf00 nop
  2809. 8001420: 40012400 .word 0x40012400
  2810. 8001424: 40023800 .word 0x40023800
  2811. 8001428: 40020000 .word 0x40020000
  2812. 0800142c <HAL_SPI_MspInit>:
  2813. * This function configures the hardware resources used in this example
  2814. * @param hspi: SPI handle pointer
  2815. * @retval None
  2816. */
  2817. void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
  2818. {
  2819. 800142c: b580 push {r7, lr}
  2820. 800142e: b08a sub sp, #40 ; 0x28
  2821. 8001430: af00 add r7, sp, #0
  2822. 8001432: 6078 str r0, [r7, #4]
  2823. GPIO_InitTypeDef GPIO_InitStruct = {0};
  2824. 8001434: f107 0314 add.w r3, r7, #20
  2825. 8001438: 2200 movs r2, #0
  2826. 800143a: 601a str r2, [r3, #0]
  2827. 800143c: 605a str r2, [r3, #4]
  2828. 800143e: 609a str r2, [r3, #8]
  2829. 8001440: 60da str r2, [r3, #12]
  2830. 8001442: 611a str r2, [r3, #16]
  2831. if(hspi->Instance==SPI1)
  2832. 8001444: 687b ldr r3, [r7, #4]
  2833. 8001446: 681b ldr r3, [r3, #0]
  2834. 8001448: 4a17 ldr r2, [pc, #92] ; (80014a8 <HAL_SPI_MspInit+0x7c>)
  2835. 800144a: 4293 cmp r3, r2
  2836. 800144c: d127 bne.n 800149e <HAL_SPI_MspInit+0x72>
  2837. {
  2838. /* USER CODE BEGIN SPI1_MspInit 0 */
  2839. /* USER CODE END SPI1_MspInit 0 */
  2840. /* Peripheral clock enable */
  2841. __HAL_RCC_SPI1_CLK_ENABLE();
  2842. 800144e: 4b17 ldr r3, [pc, #92] ; (80014ac <HAL_SPI_MspInit+0x80>)
  2843. 8001450: 6a1b ldr r3, [r3, #32]
  2844. 8001452: 4a16 ldr r2, [pc, #88] ; (80014ac <HAL_SPI_MspInit+0x80>)
  2845. 8001454: f443 5380 orr.w r3, r3, #4096 ; 0x1000
  2846. 8001458: 6213 str r3, [r2, #32]
  2847. 800145a: 4b14 ldr r3, [pc, #80] ; (80014ac <HAL_SPI_MspInit+0x80>)
  2848. 800145c: 6a1b ldr r3, [r3, #32]
  2849. 800145e: f403 5380 and.w r3, r3, #4096 ; 0x1000
  2850. 8001462: 613b str r3, [r7, #16]
  2851. 8001464: 693b ldr r3, [r7, #16]
  2852. __HAL_RCC_GPIOA_CLK_ENABLE();
  2853. 8001466: 4b11 ldr r3, [pc, #68] ; (80014ac <HAL_SPI_MspInit+0x80>)
  2854. 8001468: 69db ldr r3, [r3, #28]
  2855. 800146a: 4a10 ldr r2, [pc, #64] ; (80014ac <HAL_SPI_MspInit+0x80>)
  2856. 800146c: f043 0301 orr.w r3, r3, #1
  2857. 8001470: 61d3 str r3, [r2, #28]
  2858. 8001472: 4b0e ldr r3, [pc, #56] ; (80014ac <HAL_SPI_MspInit+0x80>)
  2859. 8001474: 69db ldr r3, [r3, #28]
  2860. 8001476: f003 0301 and.w r3, r3, #1
  2861. 800147a: 60fb str r3, [r7, #12]
  2862. 800147c: 68fb ldr r3, [r7, #12]
  2863. /**SPI1 GPIO Configuration
  2864. PA5 ------> SPI1_SCK
  2865. PA6 ------> SPI1_MISO
  2866. PA7 ------> SPI1_MOSI
  2867. */
  2868. GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
  2869. 800147e: 23e0 movs r3, #224 ; 0xe0
  2870. 8001480: 617b str r3, [r7, #20]
  2871. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2872. 8001482: 2302 movs r3, #2
  2873. 8001484: 61bb str r3, [r7, #24]
  2874. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2875. 8001486: 2300 movs r3, #0
  2876. 8001488: 61fb str r3, [r7, #28]
  2877. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2878. 800148a: 2303 movs r3, #3
  2879. 800148c: 623b str r3, [r7, #32]
  2880. GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
  2881. 800148e: 2305 movs r3, #5
  2882. 8001490: 627b str r3, [r7, #36] ; 0x24
  2883. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  2884. 8001492: f107 0314 add.w r3, r7, #20
  2885. 8001496: 4619 mov r1, r3
  2886. 8001498: 4805 ldr r0, [pc, #20] ; (80014b0 <HAL_SPI_MspInit+0x84>)
  2887. 800149a: f000 fe79 bl 8002190 <HAL_GPIO_Init>
  2888. /* USER CODE BEGIN SPI1_MspInit 1 */
  2889. /* USER CODE END SPI1_MspInit 1 */
  2890. }
  2891. }
  2892. 800149e: bf00 nop
  2893. 80014a0: 3728 adds r7, #40 ; 0x28
  2894. 80014a2: 46bd mov sp, r7
  2895. 80014a4: bd80 pop {r7, pc}
  2896. 80014a6: bf00 nop
  2897. 80014a8: 40013000 .word 0x40013000
  2898. 80014ac: 40023800 .word 0x40023800
  2899. 80014b0: 40020000 .word 0x40020000
  2900. 080014b4 <HAL_UART_MspInit>:
  2901. * This function configures the hardware resources used in this example
  2902. * @param huart: UART handle pointer
  2903. * @retval None
  2904. */
  2905. void HAL_UART_MspInit(UART_HandleTypeDef* huart)
  2906. {
  2907. 80014b4: b580 push {r7, lr}
  2908. 80014b6: b08a sub sp, #40 ; 0x28
  2909. 80014b8: af00 add r7, sp, #0
  2910. 80014ba: 6078 str r0, [r7, #4]
  2911. GPIO_InitTypeDef GPIO_InitStruct = {0};
  2912. 80014bc: f107 0314 add.w r3, r7, #20
  2913. 80014c0: 2200 movs r2, #0
  2914. 80014c2: 601a str r2, [r3, #0]
  2915. 80014c4: 605a str r2, [r3, #4]
  2916. 80014c6: 609a str r2, [r3, #8]
  2917. 80014c8: 60da str r2, [r3, #12]
  2918. 80014ca: 611a str r2, [r3, #16]
  2919. if(huart->Instance==USART2)
  2920. 80014cc: 687b ldr r3, [r7, #4]
  2921. 80014ce: 681b ldr r3, [r3, #0]
  2922. 80014d0: 4a17 ldr r2, [pc, #92] ; (8001530 <HAL_UART_MspInit+0x7c>)
  2923. 80014d2: 4293 cmp r3, r2
  2924. 80014d4: d127 bne.n 8001526 <HAL_UART_MspInit+0x72>
  2925. {
  2926. /* USER CODE BEGIN USART2_MspInit 0 */
  2927. /* USER CODE END USART2_MspInit 0 */
  2928. /* Peripheral clock enable */
  2929. __HAL_RCC_USART2_CLK_ENABLE();
  2930. 80014d6: 4b17 ldr r3, [pc, #92] ; (8001534 <HAL_UART_MspInit+0x80>)
  2931. 80014d8: 6a5b ldr r3, [r3, #36] ; 0x24
  2932. 80014da: 4a16 ldr r2, [pc, #88] ; (8001534 <HAL_UART_MspInit+0x80>)
  2933. 80014dc: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  2934. 80014e0: 6253 str r3, [r2, #36] ; 0x24
  2935. 80014e2: 4b14 ldr r3, [pc, #80] ; (8001534 <HAL_UART_MspInit+0x80>)
  2936. 80014e4: 6a5b ldr r3, [r3, #36] ; 0x24
  2937. 80014e6: f403 3300 and.w r3, r3, #131072 ; 0x20000
  2938. 80014ea: 613b str r3, [r7, #16]
  2939. 80014ec: 693b ldr r3, [r7, #16]
  2940. __HAL_RCC_GPIOA_CLK_ENABLE();
  2941. 80014ee: 4b11 ldr r3, [pc, #68] ; (8001534 <HAL_UART_MspInit+0x80>)
  2942. 80014f0: 69db ldr r3, [r3, #28]
  2943. 80014f2: 4a10 ldr r2, [pc, #64] ; (8001534 <HAL_UART_MspInit+0x80>)
  2944. 80014f4: f043 0301 orr.w r3, r3, #1
  2945. 80014f8: 61d3 str r3, [r2, #28]
  2946. 80014fa: 4b0e ldr r3, [pc, #56] ; (8001534 <HAL_UART_MspInit+0x80>)
  2947. 80014fc: 69db ldr r3, [r3, #28]
  2948. 80014fe: f003 0301 and.w r3, r3, #1
  2949. 8001502: 60fb str r3, [r7, #12]
  2950. 8001504: 68fb ldr r3, [r7, #12]
  2951. /**USART2 GPIO Configuration
  2952. PA2 ------> USART2_TX
  2953. PA3 ------> USART2_RX
  2954. */
  2955. GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
  2956. 8001506: 230c movs r3, #12
  2957. 8001508: 617b str r3, [r7, #20]
  2958. GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
  2959. 800150a: 2302 movs r3, #2
  2960. 800150c: 61bb str r3, [r7, #24]
  2961. GPIO_InitStruct.Pull = GPIO_NOPULL;
  2962. 800150e: 2300 movs r3, #0
  2963. 8001510: 61fb str r3, [r7, #28]
  2964. GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
  2965. 8001512: 2303 movs r3, #3
  2966. 8001514: 623b str r3, [r7, #32]
  2967. GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
  2968. 8001516: 2307 movs r3, #7
  2969. 8001518: 627b str r3, [r7, #36] ; 0x24
  2970. HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
  2971. 800151a: f107 0314 add.w r3, r7, #20
  2972. 800151e: 4619 mov r1, r3
  2973. 8001520: 4805 ldr r0, [pc, #20] ; (8001538 <HAL_UART_MspInit+0x84>)
  2974. 8001522: f000 fe35 bl 8002190 <HAL_GPIO_Init>
  2975. /* USER CODE BEGIN USART2_MspInit 1 */
  2976. /* USER CODE END USART2_MspInit 1 */
  2977. }
  2978. }
  2979. 8001526: bf00 nop
  2980. 8001528: 3728 adds r7, #40 ; 0x28
  2981. 800152a: 46bd mov sp, r7
  2982. 800152c: bd80 pop {r7, pc}
  2983. 800152e: bf00 nop
  2984. 8001530: 40004400 .word 0x40004400
  2985. 8001534: 40023800 .word 0x40023800
  2986. 8001538: 40020000 .word 0x40020000
  2987. 0800153c <NMI_Handler>:
  2988. /******************************************************************************/
  2989. /**
  2990. * @brief This function handles Non maskable interrupt.
  2991. */
  2992. void NMI_Handler(void)
  2993. {
  2994. 800153c: b480 push {r7}
  2995. 800153e: af00 add r7, sp, #0
  2996. /* USER CODE END NonMaskableInt_IRQn 0 */
  2997. /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  2998. /* USER CODE END NonMaskableInt_IRQn 1 */
  2999. }
  3000. 8001540: bf00 nop
  3001. 8001542: 46bd mov sp, r7
  3002. 8001544: bc80 pop {r7}
  3003. 8001546: 4770 bx lr
  3004. 08001548 <HardFault_Handler>:
  3005. /**
  3006. * @brief This function handles Hard fault interrupt.
  3007. */
  3008. void HardFault_Handler(void)
  3009. {
  3010. 8001548: b480 push {r7}
  3011. 800154a: af00 add r7, sp, #0
  3012. /* USER CODE BEGIN HardFault_IRQn 0 */
  3013. /* USER CODE END HardFault_IRQn 0 */
  3014. while (1)
  3015. 800154c: e7fe b.n 800154c <HardFault_Handler+0x4>
  3016. 0800154e <MemManage_Handler>:
  3017. /**
  3018. * @brief This function handles Memory management fault.
  3019. */
  3020. void MemManage_Handler(void)
  3021. {
  3022. 800154e: b480 push {r7}
  3023. 8001550: af00 add r7, sp, #0
  3024. /* USER CODE BEGIN MemoryManagement_IRQn 0 */
  3025. /* USER CODE END MemoryManagement_IRQn 0 */
  3026. while (1)
  3027. 8001552: e7fe b.n 8001552 <MemManage_Handler+0x4>
  3028. 08001554 <BusFault_Handler>:
  3029. /**
  3030. * @brief This function handles Pre-fetch fault, memory access fault.
  3031. */
  3032. void BusFault_Handler(void)
  3033. {
  3034. 8001554: b480 push {r7}
  3035. 8001556: af00 add r7, sp, #0
  3036. /* USER CODE BEGIN BusFault_IRQn 0 */
  3037. /* USER CODE END BusFault_IRQn 0 */
  3038. while (1)
  3039. 8001558: e7fe b.n 8001558 <BusFault_Handler+0x4>
  3040. 0800155a <UsageFault_Handler>:
  3041. /**
  3042. * @brief This function handles Undefined instruction or illegal state.
  3043. */
  3044. void UsageFault_Handler(void)
  3045. {
  3046. 800155a: b480 push {r7}
  3047. 800155c: af00 add r7, sp, #0
  3048. /* USER CODE BEGIN UsageFault_IRQn 0 */
  3049. /* USER CODE END UsageFault_IRQn 0 */
  3050. while (1)
  3051. 800155e: e7fe b.n 800155e <UsageFault_Handler+0x4>
  3052. 08001560 <SVC_Handler>:
  3053. /**
  3054. * @brief This function handles System service call via SWI instruction.
  3055. */
  3056. void SVC_Handler(void)
  3057. {
  3058. 8001560: b480 push {r7}
  3059. 8001562: af00 add r7, sp, #0
  3060. /* USER CODE END SVC_IRQn 0 */
  3061. /* USER CODE BEGIN SVC_IRQn 1 */
  3062. /* USER CODE END SVC_IRQn 1 */
  3063. }
  3064. 8001564: bf00 nop
  3065. 8001566: 46bd mov sp, r7
  3066. 8001568: bc80 pop {r7}
  3067. 800156a: 4770 bx lr
  3068. 0800156c <DebugMon_Handler>:
  3069. /**
  3070. * @brief This function handles Debug monitor.
  3071. */
  3072. void DebugMon_Handler(void)
  3073. {
  3074. 800156c: b480 push {r7}
  3075. 800156e: af00 add r7, sp, #0
  3076. /* USER CODE END DebugMonitor_IRQn 0 */
  3077. /* USER CODE BEGIN DebugMonitor_IRQn 1 */
  3078. /* USER CODE END DebugMonitor_IRQn 1 */
  3079. }
  3080. 8001570: bf00 nop
  3081. 8001572: 46bd mov sp, r7
  3082. 8001574: bc80 pop {r7}
  3083. 8001576: 4770 bx lr
  3084. 08001578 <PendSV_Handler>:
  3085. /**
  3086. * @brief This function handles Pendable request for system service.
  3087. */
  3088. void PendSV_Handler(void)
  3089. {
  3090. 8001578: b480 push {r7}
  3091. 800157a: af00 add r7, sp, #0
  3092. /* USER CODE END PendSV_IRQn 0 */
  3093. /* USER CODE BEGIN PendSV_IRQn 1 */
  3094. /* USER CODE END PendSV_IRQn 1 */
  3095. }
  3096. 800157c: bf00 nop
  3097. 800157e: 46bd mov sp, r7
  3098. 8001580: bc80 pop {r7}
  3099. 8001582: 4770 bx lr
  3100. 08001584 <SysTick_Handler>:
  3101. /**
  3102. * @brief This function handles System tick timer.
  3103. */
  3104. void SysTick_Handler(void)
  3105. {
  3106. 8001584: b580 push {r7, lr}
  3107. 8001586: af00 add r7, sp, #0
  3108. /* USER CODE BEGIN SysTick_IRQn 0 */
  3109. if (Timer1 > 0){
  3110. 8001588: 4b0c ldr r3, [pc, #48] ; (80015bc <SysTick_Handler+0x38>)
  3111. 800158a: 881b ldrh r3, [r3, #0]
  3112. 800158c: 2b00 cmp r3, #0
  3113. 800158e: d005 beq.n 800159c <SysTick_Handler+0x18>
  3114. Timer1--;
  3115. 8001590: 4b0a ldr r3, [pc, #40] ; (80015bc <SysTick_Handler+0x38>)
  3116. 8001592: 881b ldrh r3, [r3, #0]
  3117. 8001594: 3b01 subs r3, #1
  3118. 8001596: b29a uxth r2, r3
  3119. 8001598: 4b08 ldr r3, [pc, #32] ; (80015bc <SysTick_Handler+0x38>)
  3120. 800159a: 801a strh r2, [r3, #0]
  3121. }
  3122. if (Timer2 > 0){
  3123. 800159c: 4b08 ldr r3, [pc, #32] ; (80015c0 <SysTick_Handler+0x3c>)
  3124. 800159e: 881b ldrh r3, [r3, #0]
  3125. 80015a0: 2b00 cmp r3, #0
  3126. 80015a2: d005 beq.n 80015b0 <SysTick_Handler+0x2c>
  3127. Timer2--;
  3128. 80015a4: 4b06 ldr r3, [pc, #24] ; (80015c0 <SysTick_Handler+0x3c>)
  3129. 80015a6: 881b ldrh r3, [r3, #0]
  3130. 80015a8: 3b01 subs r3, #1
  3131. 80015aa: b29a uxth r2, r3
  3132. 80015ac: 4b04 ldr r3, [pc, #16] ; (80015c0 <SysTick_Handler+0x3c>)
  3133. 80015ae: 801a strh r2, [r3, #0]
  3134. }
  3135. /* USER CODE END SysTick_IRQn 0 */
  3136. HAL_IncTick();
  3137. 80015b0: f000 f8c2 bl 8001738 <HAL_IncTick>
  3138. /* USER CODE BEGIN SysTick_IRQn 1 */
  3139. HAL_SYSTICK_IRQHandler();
  3140. 80015b4: f000 fddf bl 8002176 <HAL_SYSTICK_IRQHandler>
  3141. /* USER CODE END SysTick_IRQn 1 */
  3142. }
  3143. 80015b8: bf00 nop
  3144. 80015ba: bd80 pop {r7, pc}
  3145. 80015bc: 200002ea .word 0x200002ea
  3146. 80015c0: 200002e8 .word 0x200002e8
  3147. 080015c4 <_sbrk>:
  3148. *
  3149. * @param incr Memory size
  3150. * @return Pointer to allocated memory
  3151. */
  3152. void *_sbrk(ptrdiff_t incr)
  3153. {
  3154. 80015c4: b580 push {r7, lr}
  3155. 80015c6: b086 sub sp, #24
  3156. 80015c8: af00 add r7, sp, #0
  3157. 80015ca: 6078 str r0, [r7, #4]
  3158. extern uint8_t _end; /* Symbol defined in the linker script */
  3159. extern uint8_t _estack; /* Symbol defined in the linker script */
  3160. extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
  3161. const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
  3162. 80015cc: 4a14 ldr r2, [pc, #80] ; (8001620 <_sbrk+0x5c>)
  3163. 80015ce: 4b15 ldr r3, [pc, #84] ; (8001624 <_sbrk+0x60>)
  3164. 80015d0: 1ad3 subs r3, r2, r3
  3165. 80015d2: 617b str r3, [r7, #20]
  3166. const uint8_t *max_heap = (uint8_t *)stack_limit;
  3167. 80015d4: 697b ldr r3, [r7, #20]
  3168. 80015d6: 613b str r3, [r7, #16]
  3169. uint8_t *prev_heap_end;
  3170. /* Initalize heap end at first call */
  3171. if (NULL == __sbrk_heap_end)
  3172. 80015d8: 4b13 ldr r3, [pc, #76] ; (8001628 <_sbrk+0x64>)
  3173. 80015da: 681b ldr r3, [r3, #0]
  3174. 80015dc: 2b00 cmp r3, #0
  3175. 80015de: d102 bne.n 80015e6 <_sbrk+0x22>
  3176. {
  3177. __sbrk_heap_end = &_end;
  3178. 80015e0: 4b11 ldr r3, [pc, #68] ; (8001628 <_sbrk+0x64>)
  3179. 80015e2: 4a12 ldr r2, [pc, #72] ; (800162c <_sbrk+0x68>)
  3180. 80015e4: 601a str r2, [r3, #0]
  3181. }
  3182. /* Protect heap from growing into the reserved MSP stack */
  3183. if (__sbrk_heap_end + incr > max_heap)
  3184. 80015e6: 4b10 ldr r3, [pc, #64] ; (8001628 <_sbrk+0x64>)
  3185. 80015e8: 681a ldr r2, [r3, #0]
  3186. 80015ea: 687b ldr r3, [r7, #4]
  3187. 80015ec: 4413 add r3, r2
  3188. 80015ee: 693a ldr r2, [r7, #16]
  3189. 80015f0: 429a cmp r2, r3
  3190. 80015f2: d207 bcs.n 8001604 <_sbrk+0x40>
  3191. {
  3192. errno = ENOMEM;
  3193. 80015f4: f005 fdcc bl 8007190 <__errno>
  3194. 80015f8: 4602 mov r2, r0
  3195. 80015fa: 230c movs r3, #12
  3196. 80015fc: 6013 str r3, [r2, #0]
  3197. return (void *)-1;
  3198. 80015fe: f04f 33ff mov.w r3, #4294967295
  3199. 8001602: e009 b.n 8001618 <_sbrk+0x54>
  3200. }
  3201. prev_heap_end = __sbrk_heap_end;
  3202. 8001604: 4b08 ldr r3, [pc, #32] ; (8001628 <_sbrk+0x64>)
  3203. 8001606: 681b ldr r3, [r3, #0]
  3204. 8001608: 60fb str r3, [r7, #12]
  3205. __sbrk_heap_end += incr;
  3206. 800160a: 4b07 ldr r3, [pc, #28] ; (8001628 <_sbrk+0x64>)
  3207. 800160c: 681a ldr r2, [r3, #0]
  3208. 800160e: 687b ldr r3, [r7, #4]
  3209. 8001610: 4413 add r3, r2
  3210. 8001612: 4a05 ldr r2, [pc, #20] ; (8001628 <_sbrk+0x64>)
  3211. 8001614: 6013 str r3, [r2, #0]
  3212. return (void *)prev_heap_end;
  3213. 8001616: 68fb ldr r3, [r7, #12]
  3214. }
  3215. 8001618: 4618 mov r0, r3
  3216. 800161a: 3718 adds r7, #24
  3217. 800161c: 46bd mov sp, r7
  3218. 800161e: bd80 pop {r7, pc}
  3219. 8001620: 20014000 .word 0x20014000
  3220. 8001624: 00000400 .word 0x00000400
  3221. 8001628: 200000a8 .word 0x200000a8
  3222. 800162c: 20004558 .word 0x20004558
  3223. 08001630 <SystemInit>:
  3224. * SystemCoreClock variable.
  3225. * @param None
  3226. * @retval None
  3227. */
  3228. void SystemInit (void)
  3229. {
  3230. 8001630: b480 push {r7}
  3231. 8001632: af00 add r7, sp, #0
  3232. #endif /* DATA_IN_ExtSRAM */
  3233. #ifdef VECT_TAB_SRAM
  3234. SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
  3235. #else
  3236. SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
  3237. 8001634: 4b03 ldr r3, [pc, #12] ; (8001644 <SystemInit+0x14>)
  3238. 8001636: f04f 6200 mov.w r2, #134217728 ; 0x8000000
  3239. 800163a: 609a str r2, [r3, #8]
  3240. #endif
  3241. }
  3242. 800163c: bf00 nop
  3243. 800163e: 46bd mov sp, r7
  3244. 8001640: bc80 pop {r7}
  3245. 8001642: 4770 bx lr
  3246. 8001644: e000ed00 .word 0xe000ed00
  3247. 08001648 <Reset_Handler>:
  3248. .weak Reset_Handler
  3249. .type Reset_Handler, %function
  3250. Reset_Handler:
  3251. /* Copy the data segment initializers from flash to SRAM */
  3252. movs r1, #0
  3253. 8001648: 2100 movs r1, #0
  3254. b LoopCopyDataInit
  3255. 800164a: e003 b.n 8001654 <LoopCopyDataInit>
  3256. 0800164c <CopyDataInit>:
  3257. CopyDataInit:
  3258. ldr r3, =_sidata
  3259. 800164c: 4b0b ldr r3, [pc, #44] ; (800167c <LoopFillZerobss+0x14>)
  3260. ldr r3, [r3, r1]
  3261. 800164e: 585b ldr r3, [r3, r1]
  3262. str r3, [r0, r1]
  3263. 8001650: 5043 str r3, [r0, r1]
  3264. adds r1, r1, #4
  3265. 8001652: 3104 adds r1, #4
  3266. 08001654 <LoopCopyDataInit>:
  3267. LoopCopyDataInit:
  3268. ldr r0, =_sdata
  3269. 8001654: 480a ldr r0, [pc, #40] ; (8001680 <LoopFillZerobss+0x18>)
  3270. ldr r3, =_edata
  3271. 8001656: 4b0b ldr r3, [pc, #44] ; (8001684 <LoopFillZerobss+0x1c>)
  3272. adds r2, r0, r1
  3273. 8001658: 1842 adds r2, r0, r1
  3274. cmp r2, r3
  3275. 800165a: 429a cmp r2, r3
  3276. bcc CopyDataInit
  3277. 800165c: d3f6 bcc.n 800164c <CopyDataInit>
  3278. ldr r2, =_sbss
  3279. 800165e: 4a0a ldr r2, [pc, #40] ; (8001688 <LoopFillZerobss+0x20>)
  3280. b LoopFillZerobss
  3281. 8001660: e002 b.n 8001668 <LoopFillZerobss>
  3282. 08001662 <FillZerobss>:
  3283. /* Zero fill the bss segment. */
  3284. FillZerobss:
  3285. movs r3, #0
  3286. 8001662: 2300 movs r3, #0
  3287. str r3, [r2], #4
  3288. 8001664: f842 3b04 str.w r3, [r2], #4
  3289. 08001668 <LoopFillZerobss>:
  3290. LoopFillZerobss:
  3291. ldr r3, = _ebss
  3292. 8001668: 4b08 ldr r3, [pc, #32] ; (800168c <LoopFillZerobss+0x24>)
  3293. cmp r2, r3
  3294. 800166a: 429a cmp r2, r3
  3295. bcc FillZerobss
  3296. 800166c: d3f9 bcc.n 8001662 <FillZerobss>
  3297. /* Call the clock system intitialization function.*/
  3298. bl SystemInit
  3299. 800166e: f7ff ffdf bl 8001630 <SystemInit>
  3300. /* Call static constructors */
  3301. bl __libc_init_array
  3302. 8001672: f005 fd93 bl 800719c <__libc_init_array>
  3303. /* Call the application's entry point.*/
  3304. bl main
  3305. 8001676: f7ff fbe5 bl 8000e44 <main>
  3306. bx lr
  3307. 800167a: 4770 bx lr
  3308. ldr r3, =_sidata
  3309. 800167c: 08008008 .word 0x08008008
  3310. ldr r0, =_sdata
  3311. 8001680: 20000000 .word 0x20000000
  3312. ldr r3, =_edata
  3313. 8001684: 20000088 .word 0x20000088
  3314. ldr r2, =_sbss
  3315. 8001688: 20000088 .word 0x20000088
  3316. ldr r3, = _ebss
  3317. 800168c: 20004554 .word 0x20004554
  3318. 08001690 <ADC1_IRQHandler>:
  3319. * @retval : None
  3320. */
  3321. .section .text.Default_Handler,"ax",%progbits
  3322. Default_Handler:
  3323. Infinite_Loop:
  3324. b Infinite_Loop
  3325. 8001690: e7fe b.n 8001690 <ADC1_IRQHandler>
  3326. 08001692 <HAL_Init>:
  3327. * In the default implementation,Systick is used as source of time base.
  3328. * the tick variable is incremented each 1ms in its ISR.
  3329. * @retval HAL status
  3330. */
  3331. HAL_StatusTypeDef HAL_Init(void)
  3332. {
  3333. 8001692: b580 push {r7, lr}
  3334. 8001694: b082 sub sp, #8
  3335. 8001696: af00 add r7, sp, #0
  3336. HAL_StatusTypeDef status = HAL_OK;
  3337. 8001698: 2300 movs r3, #0
  3338. 800169a: 71fb strb r3, [r7, #7]
  3339. #if (PREFETCH_ENABLE != 0)
  3340. __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
  3341. #endif /* PREFETCH_ENABLE */
  3342. /* Set Interrupt Group Priority */
  3343. HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
  3344. 800169c: 2003 movs r0, #3
  3345. 800169e: f000 fd37 bl 8002110 <HAL_NVIC_SetPriorityGrouping>
  3346. /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
  3347. if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
  3348. 80016a2: 2000 movs r0, #0
  3349. 80016a4: f000 f80e bl 80016c4 <HAL_InitTick>
  3350. 80016a8: 4603 mov r3, r0
  3351. 80016aa: 2b00 cmp r3, #0
  3352. 80016ac: d002 beq.n 80016b4 <HAL_Init+0x22>
  3353. {
  3354. status = HAL_ERROR;
  3355. 80016ae: 2301 movs r3, #1
  3356. 80016b0: 71fb strb r3, [r7, #7]
  3357. 80016b2: e001 b.n 80016b8 <HAL_Init+0x26>
  3358. }
  3359. else
  3360. {
  3361. /* Init the low level hardware */
  3362. HAL_MspInit();
  3363. 80016b4: f7ff fe4a bl 800134c <HAL_MspInit>
  3364. }
  3365. /* Return function status */
  3366. return status;
  3367. 80016b8: 79fb ldrb r3, [r7, #7]
  3368. }
  3369. 80016ba: 4618 mov r0, r3
  3370. 80016bc: 3708 adds r7, #8
  3371. 80016be: 46bd mov sp, r7
  3372. 80016c0: bd80 pop {r7, pc}
  3373. ...
  3374. 080016c4 <HAL_InitTick>:
  3375. * implementation in user file.
  3376. * @param TickPriority Tick interrupt priority.
  3377. * @retval HAL status
  3378. */
  3379. __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
  3380. {
  3381. 80016c4: b580 push {r7, lr}
  3382. 80016c6: b084 sub sp, #16
  3383. 80016c8: af00 add r7, sp, #0
  3384. 80016ca: 6078 str r0, [r7, #4]
  3385. HAL_StatusTypeDef status = HAL_OK;
  3386. 80016cc: 2300 movs r3, #0
  3387. 80016ce: 73fb strb r3, [r7, #15]
  3388. if (uwTickFreq != 0U)
  3389. 80016d0: 4b16 ldr r3, [pc, #88] ; (800172c <HAL_InitTick+0x68>)
  3390. 80016d2: 681b ldr r3, [r3, #0]
  3391. 80016d4: 2b00 cmp r3, #0
  3392. 80016d6: d022 beq.n 800171e <HAL_InitTick+0x5a>
  3393. {
  3394. /*Configure the SysTick to have interrupt in 1ms time basis*/
  3395. if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
  3396. 80016d8: 4b15 ldr r3, [pc, #84] ; (8001730 <HAL_InitTick+0x6c>)
  3397. 80016da: 681a ldr r2, [r3, #0]
  3398. 80016dc: 4b13 ldr r3, [pc, #76] ; (800172c <HAL_InitTick+0x68>)
  3399. 80016de: 681b ldr r3, [r3, #0]
  3400. 80016e0: f44f 717a mov.w r1, #1000 ; 0x3e8
  3401. 80016e4: fbb1 f3f3 udiv r3, r1, r3
  3402. 80016e8: fbb2 f3f3 udiv r3, r2, r3
  3403. 80016ec: 4618 mov r0, r3
  3404. 80016ee: f000 fd36 bl 800215e <HAL_SYSTICK_Config>
  3405. 80016f2: 4603 mov r3, r0
  3406. 80016f4: 2b00 cmp r3, #0
  3407. 80016f6: d10f bne.n 8001718 <HAL_InitTick+0x54>
  3408. {
  3409. /* Configure the SysTick IRQ priority */
  3410. if (TickPriority < (1UL << __NVIC_PRIO_BITS))
  3411. 80016f8: 687b ldr r3, [r7, #4]
  3412. 80016fa: 2b0f cmp r3, #15
  3413. 80016fc: d809 bhi.n 8001712 <HAL_InitTick+0x4e>
  3414. {
  3415. HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
  3416. 80016fe: 2200 movs r2, #0
  3417. 8001700: 6879 ldr r1, [r7, #4]
  3418. 8001702: f04f 30ff mov.w r0, #4294967295
  3419. 8001706: f000 fd0e bl 8002126 <HAL_NVIC_SetPriority>
  3420. uwTickPrio = TickPriority;
  3421. 800170a: 4a0a ldr r2, [pc, #40] ; (8001734 <HAL_InitTick+0x70>)
  3422. 800170c: 687b ldr r3, [r7, #4]
  3423. 800170e: 6013 str r3, [r2, #0]
  3424. 8001710: e007 b.n 8001722 <HAL_InitTick+0x5e>
  3425. }
  3426. else
  3427. {
  3428. status = HAL_ERROR;
  3429. 8001712: 2301 movs r3, #1
  3430. 8001714: 73fb strb r3, [r7, #15]
  3431. 8001716: e004 b.n 8001722 <HAL_InitTick+0x5e>
  3432. }
  3433. }
  3434. else
  3435. {
  3436. status = HAL_ERROR;
  3437. 8001718: 2301 movs r3, #1
  3438. 800171a: 73fb strb r3, [r7, #15]
  3439. 800171c: e001 b.n 8001722 <HAL_InitTick+0x5e>
  3440. }
  3441. }
  3442. else
  3443. {
  3444. status = HAL_ERROR;
  3445. 800171e: 2301 movs r3, #1
  3446. 8001720: 73fb strb r3, [r7, #15]
  3447. }
  3448. /* Return function status */
  3449. return status;
  3450. 8001722: 7bfb ldrb r3, [r7, #15]
  3451. }
  3452. 8001724: 4618 mov r0, r3
  3453. 8001726: 3710 adds r7, #16
  3454. 8001728: 46bd mov sp, r7
  3455. 800172a: bd80 pop {r7, pc}
  3456. 800172c: 2000000c .word 0x2000000c
  3457. 8001730: 20000004 .word 0x20000004
  3458. 8001734: 20000008 .word 0x20000008
  3459. 08001738 <HAL_IncTick>:
  3460. * @note This function is declared as __weak to be overwritten in case of other
  3461. * implementations in user file.
  3462. * @retval None
  3463. */
  3464. __weak void HAL_IncTick(void)
  3465. {
  3466. 8001738: b480 push {r7}
  3467. 800173a: af00 add r7, sp, #0
  3468. uwTick += uwTickFreq;
  3469. 800173c: 4b05 ldr r3, [pc, #20] ; (8001754 <HAL_IncTick+0x1c>)
  3470. 800173e: 681a ldr r2, [r3, #0]
  3471. 8001740: 4b05 ldr r3, [pc, #20] ; (8001758 <HAL_IncTick+0x20>)
  3472. 8001742: 681b ldr r3, [r3, #0]
  3473. 8001744: 4413 add r3, r2
  3474. 8001746: 4a03 ldr r2, [pc, #12] ; (8001754 <HAL_IncTick+0x1c>)
  3475. 8001748: 6013 str r3, [r2, #0]
  3476. }
  3477. 800174a: bf00 nop
  3478. 800174c: 46bd mov sp, r7
  3479. 800174e: bc80 pop {r7}
  3480. 8001750: 4770 bx lr
  3481. 8001752: bf00 nop
  3482. 8001754: 200024dc .word 0x200024dc
  3483. 8001758: 2000000c .word 0x2000000c
  3484. 0800175c <HAL_GetTick>:
  3485. * @note This function is declared as __weak to be overwritten in case of other
  3486. * implementations in user file.
  3487. * @retval tick value
  3488. */
  3489. __weak uint32_t HAL_GetTick(void)
  3490. {
  3491. 800175c: b480 push {r7}
  3492. 800175e: af00 add r7, sp, #0
  3493. return uwTick;
  3494. 8001760: 4b02 ldr r3, [pc, #8] ; (800176c <HAL_GetTick+0x10>)
  3495. 8001762: 681b ldr r3, [r3, #0]
  3496. }
  3497. 8001764: 4618 mov r0, r3
  3498. 8001766: 46bd mov sp, r7
  3499. 8001768: bc80 pop {r7}
  3500. 800176a: 4770 bx lr
  3501. 800176c: 200024dc .word 0x200024dc
  3502. 08001770 <HAL_Delay>:
  3503. * implementations in user file.
  3504. * @param Delay specifies the delay time length, in milliseconds.
  3505. * @retval None
  3506. */
  3507. __weak void HAL_Delay(uint32_t Delay)
  3508. {
  3509. 8001770: b580 push {r7, lr}
  3510. 8001772: b084 sub sp, #16
  3511. 8001774: af00 add r7, sp, #0
  3512. 8001776: 6078 str r0, [r7, #4]
  3513. uint32_t tickstart = HAL_GetTick();
  3514. 8001778: f7ff fff0 bl 800175c <HAL_GetTick>
  3515. 800177c: 60b8 str r0, [r7, #8]
  3516. uint32_t wait = Delay;
  3517. 800177e: 687b ldr r3, [r7, #4]
  3518. 8001780: 60fb str r3, [r7, #12]
  3519. /* Add a period to guaranty minimum wait */
  3520. if (wait < HAL_MAX_DELAY)
  3521. 8001782: 68fb ldr r3, [r7, #12]
  3522. 8001784: f1b3 3fff cmp.w r3, #4294967295
  3523. 8001788: d004 beq.n 8001794 <HAL_Delay+0x24>
  3524. {
  3525. wait += (uint32_t)(uwTickFreq);
  3526. 800178a: 4b09 ldr r3, [pc, #36] ; (80017b0 <HAL_Delay+0x40>)
  3527. 800178c: 681b ldr r3, [r3, #0]
  3528. 800178e: 68fa ldr r2, [r7, #12]
  3529. 8001790: 4413 add r3, r2
  3530. 8001792: 60fb str r3, [r7, #12]
  3531. }
  3532. while((HAL_GetTick() - tickstart) < wait)
  3533. 8001794: bf00 nop
  3534. 8001796: f7ff ffe1 bl 800175c <HAL_GetTick>
  3535. 800179a: 4602 mov r2, r0
  3536. 800179c: 68bb ldr r3, [r7, #8]
  3537. 800179e: 1ad3 subs r3, r2, r3
  3538. 80017a0: 68fa ldr r2, [r7, #12]
  3539. 80017a2: 429a cmp r2, r3
  3540. 80017a4: d8f7 bhi.n 8001796 <HAL_Delay+0x26>
  3541. {
  3542. }
  3543. }
  3544. 80017a6: bf00 nop
  3545. 80017a8: 3710 adds r7, #16
  3546. 80017aa: 46bd mov sp, r7
  3547. 80017ac: bd80 pop {r7, pc}
  3548. 80017ae: bf00 nop
  3549. 80017b0: 2000000c .word 0x2000000c
  3550. 080017b4 <HAL_ADC_Init>:
  3551. * of structure "ADC_InitTypeDef".
  3552. * @param hadc ADC handle
  3553. * @retval HAL status
  3554. */
  3555. HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
  3556. {
  3557. 80017b4: b580 push {r7, lr}
  3558. 80017b6: b08e sub sp, #56 ; 0x38
  3559. 80017b8: af00 add r7, sp, #0
  3560. 80017ba: 6078 str r0, [r7, #4]
  3561. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  3562. 80017bc: 2300 movs r3, #0
  3563. 80017be: f887 3037 strb.w r3, [r7, #55] ; 0x37
  3564. uint32_t tmp_cr1 = 0;
  3565. 80017c2: 2300 movs r3, #0
  3566. 80017c4: 633b str r3, [r7, #48] ; 0x30
  3567. uint32_t tmp_cr2 = 0;
  3568. 80017c6: 2300 movs r3, #0
  3569. 80017c8: 62fb str r3, [r7, #44] ; 0x2c
  3570. /* Check ADC handle */
  3571. if(hadc == NULL)
  3572. 80017ca: 687b ldr r3, [r7, #4]
  3573. 80017cc: 2b00 cmp r3, #0
  3574. 80017ce: d101 bne.n 80017d4 <HAL_ADC_Init+0x20>
  3575. {
  3576. return HAL_ERROR;
  3577. 80017d0: 2301 movs r3, #1
  3578. 80017d2: e127 b.n 8001a24 <HAL_ADC_Init+0x270>
  3579. assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
  3580. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  3581. assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
  3582. assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
  3583. if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
  3584. 80017d4: 687b ldr r3, [r7, #4]
  3585. 80017d6: 691b ldr r3, [r3, #16]
  3586. 80017d8: 2b00 cmp r3, #0
  3587. /* Refer to header of this file for more details on clock enabling */
  3588. /* procedure. */
  3589. /* Actions performed only if ADC is coming from state reset: */
  3590. /* - Initialization of ADC MSP */
  3591. if (hadc->State == HAL_ADC_STATE_RESET)
  3592. 80017da: 687b ldr r3, [r7, #4]
  3593. 80017dc: 6cdb ldr r3, [r3, #76] ; 0x4c
  3594. 80017de: 2b00 cmp r3, #0
  3595. 80017e0: d115 bne.n 800180e <HAL_ADC_Init+0x5a>
  3596. {
  3597. /* Initialize ADC error code */
  3598. ADC_CLEAR_ERRORCODE(hadc);
  3599. 80017e2: 687b ldr r3, [r7, #4]
  3600. 80017e4: 2200 movs r2, #0
  3601. 80017e6: 651a str r2, [r3, #80] ; 0x50
  3602. /* Allocate lock resource and initialize it */
  3603. hadc->Lock = HAL_UNLOCKED;
  3604. 80017e8: 687b ldr r3, [r7, #4]
  3605. 80017ea: 2200 movs r2, #0
  3606. 80017ec: f883 2048 strb.w r2, [r3, #72] ; 0x48
  3607. /* Enable SYSCFG clock to control the routing Interface (RI) */
  3608. __HAL_RCC_SYSCFG_CLK_ENABLE();
  3609. 80017f0: 4b8e ldr r3, [pc, #568] ; (8001a2c <HAL_ADC_Init+0x278>)
  3610. 80017f2: 6a1b ldr r3, [r3, #32]
  3611. 80017f4: 4a8d ldr r2, [pc, #564] ; (8001a2c <HAL_ADC_Init+0x278>)
  3612. 80017f6: f043 0301 orr.w r3, r3, #1
  3613. 80017fa: 6213 str r3, [r2, #32]
  3614. 80017fc: 4b8b ldr r3, [pc, #556] ; (8001a2c <HAL_ADC_Init+0x278>)
  3615. 80017fe: 6a1b ldr r3, [r3, #32]
  3616. 8001800: f003 0301 and.w r3, r3, #1
  3617. 8001804: 60bb str r3, [r7, #8]
  3618. 8001806: 68bb ldr r3, [r7, #8]
  3619. /* Init the low level hardware */
  3620. hadc->MspInitCallback(hadc);
  3621. #else
  3622. /* Init the low level hardware */
  3623. HAL_ADC_MspInit(hadc);
  3624. 8001808: 6878 ldr r0, [r7, #4]
  3625. 800180a: f7ff fdcf bl 80013ac <HAL_ADC_MspInit>
  3626. #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
  3627. }
  3628. /* Configuration of ADC parameters if previous preliminary actions are */
  3629. /* correctly completed. */
  3630. if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
  3631. 800180e: 687b ldr r3, [r7, #4]
  3632. 8001810: 6cdb ldr r3, [r3, #76] ; 0x4c
  3633. 8001812: f003 0310 and.w r3, r3, #16
  3634. 8001816: 2b00 cmp r3, #0
  3635. 8001818: f040 80ff bne.w 8001a1a <HAL_ADC_Init+0x266>
  3636. {
  3637. /* Set ADC state */
  3638. ADC_STATE_CLR_SET(hadc->State,
  3639. 800181c: 687b ldr r3, [r7, #4]
  3640. 800181e: 6cdb ldr r3, [r3, #76] ; 0x4c
  3641. 8001820: f423 5388 bic.w r3, r3, #4352 ; 0x1100
  3642. 8001824: f023 0302 bic.w r3, r3, #2
  3643. 8001828: f043 0202 orr.w r2, r3, #2
  3644. 800182c: 687b ldr r3, [r7, #4]
  3645. 800182e: 64da str r2, [r3, #76] ; 0x4c
  3646. /* Set ADC parameters */
  3647. /* Configuration of common ADC clock: clock source HSI with selectable */
  3648. /* prescaler */
  3649. MODIFY_REG(ADC->CCR ,
  3650. 8001830: 4b7f ldr r3, [pc, #508] ; (8001a30 <HAL_ADC_Init+0x27c>)
  3651. 8001832: 685b ldr r3, [r3, #4]
  3652. 8001834: f423 3240 bic.w r2, r3, #196608 ; 0x30000
  3653. 8001838: 687b ldr r3, [r7, #4]
  3654. 800183a: 685b ldr r3, [r3, #4]
  3655. 800183c: 497c ldr r1, [pc, #496] ; (8001a30 <HAL_ADC_Init+0x27c>)
  3656. 800183e: 4313 orrs r3, r2
  3657. 8001840: 604b str r3, [r1, #4]
  3658. /* - external trigger polarity */
  3659. /* - End of conversion selection */
  3660. /* - DMA continuous request */
  3661. /* - Channels bank (Banks availability depends on devices categories) */
  3662. /* - continuous conversion mode */
  3663. tmp_cr2 |= (hadc->Init.DataAlign |
  3664. 8001842: 687b ldr r3, [r7, #4]
  3665. 8001844: 68da ldr r2, [r3, #12]
  3666. hadc->Init.EOCSelection |
  3667. 8001846: 687b ldr r3, [r7, #4]
  3668. 8001848: 695b ldr r3, [r3, #20]
  3669. tmp_cr2 |= (hadc->Init.DataAlign |
  3670. 800184a: 431a orrs r2, r3
  3671. ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
  3672. 800184c: 687b ldr r3, [r7, #4]
  3673. 800184e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
  3674. 8001852: 4619 mov r1, r3
  3675. 8001854: f44f 7300 mov.w r3, #512 ; 0x200
  3676. 8001858: 623b str r3, [r7, #32]
  3677. uint32_t result;
  3678. #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
  3679. (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
  3680. (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
  3681. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  3682. 800185a: 6a3b ldr r3, [r7, #32]
  3683. 800185c: fa93 f3a3 rbit r3, r3
  3684. 8001860: 61fb str r3, [r7, #28]
  3685. result |= value & 1U;
  3686. s--;
  3687. }
  3688. result <<= s; /* shift when v's highest bits are zero */
  3689. #endif
  3690. return result;
  3691. 8001862: 69fb ldr r3, [r7, #28]
  3692. 8001864: fab3 f383 clz r3, r3
  3693. 8001868: b2db uxtb r3, r3
  3694. 800186a: fa01 f303 lsl.w r3, r1, r3
  3695. hadc->Init.EOCSelection |
  3696. 800186e: 431a orrs r2, r3
  3697. hadc->Init.ChannelsBank |
  3698. 8001870: 687b ldr r3, [r7, #4]
  3699. 8001872: 6a1b ldr r3, [r3, #32]
  3700. ADC_CR2_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests) |
  3701. 8001874: 431a orrs r2, r3
  3702. ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) );
  3703. 8001876: 687b ldr r3, [r7, #4]
  3704. 8001878: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
  3705. 800187c: 4619 mov r1, r3
  3706. 800187e: 2302 movs r3, #2
  3707. 8001880: 62bb str r3, [r7, #40] ; 0x28
  3708. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  3709. 8001882: 6abb ldr r3, [r7, #40] ; 0x28
  3710. 8001884: fa93 f3a3 rbit r3, r3
  3711. 8001888: 627b str r3, [r7, #36] ; 0x24
  3712. return result;
  3713. 800188a: 6a7b ldr r3, [r7, #36] ; 0x24
  3714. 800188c: fab3 f383 clz r3, r3
  3715. 8001890: b2db uxtb r3, r3
  3716. 8001892: fa01 f303 lsl.w r3, r1, r3
  3717. hadc->Init.ChannelsBank |
  3718. 8001896: 4313 orrs r3, r2
  3719. tmp_cr2 |= (hadc->Init.DataAlign |
  3720. 8001898: 6afa ldr r2, [r7, #44] ; 0x2c
  3721. 800189a: 4313 orrs r3, r2
  3722. 800189c: 62fb str r3, [r7, #44] ; 0x2c
  3723. /* Enable external trigger if trigger selection is different of software */
  3724. /* start. */
  3725. /* Note: This configuration keeps the hardware feature of parameter */
  3726. /* ExternalTrigConvEdge "trigger edge none" equivalent to */
  3727. /* software start. */
  3728. if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
  3729. 800189e: 687b ldr r3, [r7, #4]
  3730. 80018a0: 6b5b ldr r3, [r3, #52] ; 0x34
  3731. 80018a2: 2b10 cmp r3, #16
  3732. 80018a4: d007 beq.n 80018b6 <HAL_ADC_Init+0x102>
  3733. {
  3734. tmp_cr2 |= ( hadc->Init.ExternalTrigConv |
  3735. 80018a6: 687b ldr r3, [r7, #4]
  3736. 80018a8: 6b5a ldr r2, [r3, #52] ; 0x34
  3737. hadc->Init.ExternalTrigConvEdge );
  3738. 80018aa: 687b ldr r3, [r7, #4]
  3739. 80018ac: 6b9b ldr r3, [r3, #56] ; 0x38
  3740. tmp_cr2 |= ( hadc->Init.ExternalTrigConv |
  3741. 80018ae: 4313 orrs r3, r2
  3742. 80018b0: 6afa ldr r2, [r7, #44] ; 0x2c
  3743. 80018b2: 4313 orrs r3, r2
  3744. 80018b4: 62fb str r3, [r7, #44] ; 0x2c
  3745. /* - resolution */
  3746. /* - auto power off (LowPowerAutoPowerOff mode) */
  3747. /* - scan mode */
  3748. /* - discontinuous mode disable/enable */
  3749. /* - discontinuous mode number of conversions */
  3750. if ((ADC_IS_ENABLE(hadc) == RESET))
  3751. 80018b6: 687b ldr r3, [r7, #4]
  3752. 80018b8: 681b ldr r3, [r3, #0]
  3753. 80018ba: 681b ldr r3, [r3, #0]
  3754. 80018bc: f003 0340 and.w r3, r3, #64 ; 0x40
  3755. 80018c0: 2b40 cmp r3, #64 ; 0x40
  3756. 80018c2: d04f beq.n 8001964 <HAL_ADC_Init+0x1b0>
  3757. {
  3758. tmp_cr2 |= hadc->Init.LowPowerAutoWait;
  3759. 80018c4: 687b ldr r3, [r7, #4]
  3760. 80018c6: 699b ldr r3, [r3, #24]
  3761. 80018c8: 6afa ldr r2, [r7, #44] ; 0x2c
  3762. 80018ca: 4313 orrs r3, r2
  3763. 80018cc: 62fb str r3, [r7, #44] ; 0x2c
  3764. tmp_cr1 |= (hadc->Init.Resolution |
  3765. 80018ce: 687b ldr r3, [r7, #4]
  3766. 80018d0: 689a ldr r2, [r3, #8]
  3767. hadc->Init.LowPowerAutoPowerOff |
  3768. 80018d2: 687b ldr r3, [r7, #4]
  3769. 80018d4: 69db ldr r3, [r3, #28]
  3770. tmp_cr1 |= (hadc->Init.Resolution |
  3771. 80018d6: 4313 orrs r3, r2
  3772. ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) );
  3773. 80018d8: 687a ldr r2, [r7, #4]
  3774. 80018da: 6912 ldr r2, [r2, #16]
  3775. 80018dc: f5b2 7f80 cmp.w r2, #256 ; 0x100
  3776. 80018e0: d003 beq.n 80018ea <HAL_ADC_Init+0x136>
  3777. 80018e2: 687a ldr r2, [r7, #4]
  3778. 80018e4: 6912 ldr r2, [r2, #16]
  3779. 80018e6: 2a01 cmp r2, #1
  3780. 80018e8: d102 bne.n 80018f0 <HAL_ADC_Init+0x13c>
  3781. 80018ea: f44f 7280 mov.w r2, #256 ; 0x100
  3782. 80018ee: e000 b.n 80018f2 <HAL_ADC_Init+0x13e>
  3783. 80018f0: 2200 movs r2, #0
  3784. hadc->Init.LowPowerAutoPowerOff |
  3785. 80018f2: 4313 orrs r3, r2
  3786. tmp_cr1 |= (hadc->Init.Resolution |
  3787. 80018f4: 6b3a ldr r2, [r7, #48] ; 0x30
  3788. 80018f6: 4313 orrs r3, r2
  3789. 80018f8: 633b str r3, [r7, #48] ; 0x30
  3790. /* Enable discontinuous mode only if continuous mode is disabled */
  3791. /* Note: If parameter "Init.ScanConvMode" is set to disable, parameter */
  3792. /* discontinuous is set anyway, but has no effect on ADC HW. */
  3793. if (hadc->Init.DiscontinuousConvMode == ENABLE)
  3794. 80018fa: 687b ldr r3, [r7, #4]
  3795. 80018fc: f893 302c ldrb.w r3, [r3, #44] ; 0x2c
  3796. 8001900: 2b01 cmp r3, #1
  3797. 8001902: d125 bne.n 8001950 <HAL_ADC_Init+0x19c>
  3798. {
  3799. if (hadc->Init.ContinuousConvMode == DISABLE)
  3800. 8001904: 687b ldr r3, [r7, #4]
  3801. 8001906: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
  3802. 800190a: 2b00 cmp r3, #0
  3803. 800190c: d114 bne.n 8001938 <HAL_ADC_Init+0x184>
  3804. {
  3805. /* Enable the selected ADC regular discontinuous mode */
  3806. /* Set the number of channels to be converted in discontinuous mode */
  3807. SET_BIT(tmp_cr1, ADC_CR1_DISCEN |
  3808. 800190e: 687b ldr r3, [r7, #4]
  3809. 8001910: 6b1b ldr r3, [r3, #48] ; 0x30
  3810. 8001912: 3b01 subs r3, #1
  3811. 8001914: f44f 4260 mov.w r2, #57344 ; 0xe000
  3812. 8001918: 61ba str r2, [r7, #24]
  3813. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  3814. 800191a: 69ba ldr r2, [r7, #24]
  3815. 800191c: fa92 f2a2 rbit r2, r2
  3816. 8001920: 617a str r2, [r7, #20]
  3817. return result;
  3818. 8001922: 697a ldr r2, [r7, #20]
  3819. 8001924: fab2 f282 clz r2, r2
  3820. 8001928: b2d2 uxtb r2, r2
  3821. 800192a: 4093 lsls r3, r2
  3822. 800192c: f443 6300 orr.w r3, r3, #2048 ; 0x800
  3823. 8001930: 6b3a ldr r2, [r7, #48] ; 0x30
  3824. 8001932: 4313 orrs r3, r2
  3825. 8001934: 633b str r3, [r7, #48] ; 0x30
  3826. 8001936: e00b b.n 8001950 <HAL_ADC_Init+0x19c>
  3827. {
  3828. /* ADC regular group settings continuous and sequencer discontinuous*/
  3829. /* cannot be enabled simultaneously. */
  3830. /* Update ADC state machine to error */
  3831. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  3832. 8001938: 687b ldr r3, [r7, #4]
  3833. 800193a: 6cdb ldr r3, [r3, #76] ; 0x4c
  3834. 800193c: f043 0220 orr.w r2, r3, #32
  3835. 8001940: 687b ldr r3, [r7, #4]
  3836. 8001942: 64da str r2, [r3, #76] ; 0x4c
  3837. /* Set ADC error code to ADC IP internal error */
  3838. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  3839. 8001944: 687b ldr r3, [r7, #4]
  3840. 8001946: 6d1b ldr r3, [r3, #80] ; 0x50
  3841. 8001948: f043 0201 orr.w r2, r3, #1
  3842. 800194c: 687b ldr r3, [r7, #4]
  3843. 800194e: 651a str r2, [r3, #80] ; 0x50
  3844. }
  3845. }
  3846. /* Update ADC configuration register CR1 with previous settings */
  3847. MODIFY_REG(hadc->Instance->CR1,
  3848. 8001950: 687b ldr r3, [r7, #4]
  3849. 8001952: 681b ldr r3, [r3, #0]
  3850. 8001954: 685a ldr r2, [r3, #4]
  3851. 8001956: 4b37 ldr r3, [pc, #220] ; (8001a34 <HAL_ADC_Init+0x280>)
  3852. 8001958: 4013 ands r3, r2
  3853. 800195a: 687a ldr r2, [r7, #4]
  3854. 800195c: 6812 ldr r2, [r2, #0]
  3855. 800195e: 6b39 ldr r1, [r7, #48] ; 0x30
  3856. 8001960: 430b orrs r3, r1
  3857. 8001962: 6053 str r3, [r2, #4]
  3858. ADC_CR1_SCAN ,
  3859. tmp_cr1 );
  3860. }
  3861. /* Update ADC configuration register CR2 with previous settings */
  3862. MODIFY_REG(hadc->Instance->CR2 ,
  3863. 8001964: 687b ldr r3, [r7, #4]
  3864. 8001966: 681b ldr r3, [r3, #0]
  3865. 8001968: 689a ldr r2, [r3, #8]
  3866. 800196a: 4b33 ldr r3, [pc, #204] ; (8001a38 <HAL_ADC_Init+0x284>)
  3867. 800196c: 4013 ands r3, r2
  3868. 800196e: 687a ldr r2, [r7, #4]
  3869. 8001970: 6812 ldr r2, [r2, #0]
  3870. 8001972: 6af9 ldr r1, [r7, #44] ; 0x2c
  3871. 8001974: 430b orrs r3, r1
  3872. 8001976: 6093 str r3, [r2, #8]
  3873. /* Note: Scan mode is present by hardware on this device and, if */
  3874. /* disabled, discards automatically nb of conversions. Anyway, nb of */
  3875. /* conversions is forced to 0x00 for alignment over all STM32 devices. */
  3876. /* - if scan mode is enabled, regular channels sequence length is set to */
  3877. /* parameter "NbrOfConversion" */
  3878. if (ADC_CR1_SCAN_SET(hadc->Init.ScanConvMode) == ADC_SCAN_ENABLE)
  3879. 8001978: 687b ldr r3, [r7, #4]
  3880. 800197a: 691b ldr r3, [r3, #16]
  3881. 800197c: f5b3 7f80 cmp.w r3, #256 ; 0x100
  3882. 8001980: d003 beq.n 800198a <HAL_ADC_Init+0x1d6>
  3883. 8001982: 687b ldr r3, [r7, #4]
  3884. 8001984: 691b ldr r3, [r3, #16]
  3885. 8001986: 2b01 cmp r3, #1
  3886. 8001988: d119 bne.n 80019be <HAL_ADC_Init+0x20a>
  3887. {
  3888. MODIFY_REG(hadc->Instance->SQR1 ,
  3889. 800198a: 687b ldr r3, [r7, #4]
  3890. 800198c: 681b ldr r3, [r3, #0]
  3891. 800198e: 6b1b ldr r3, [r3, #48] ; 0x30
  3892. 8001990: f023 71f8 bic.w r1, r3, #32505856 ; 0x1f00000
  3893. 8001994: 687b ldr r3, [r7, #4]
  3894. 8001996: 6a9b ldr r3, [r3, #40] ; 0x28
  3895. 8001998: 3b01 subs r3, #1
  3896. 800199a: f04f 72f8 mov.w r2, #32505856 ; 0x1f00000
  3897. 800199e: 613a str r2, [r7, #16]
  3898. __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
  3899. 80019a0: 693a ldr r2, [r7, #16]
  3900. 80019a2: fa92 f2a2 rbit r2, r2
  3901. 80019a6: 60fa str r2, [r7, #12]
  3902. return result;
  3903. 80019a8: 68fa ldr r2, [r7, #12]
  3904. 80019aa: fab2 f282 clz r2, r2
  3905. 80019ae: b2d2 uxtb r2, r2
  3906. 80019b0: fa03 f202 lsl.w r2, r3, r2
  3907. 80019b4: 687b ldr r3, [r7, #4]
  3908. 80019b6: 681b ldr r3, [r3, #0]
  3909. 80019b8: 430a orrs r2, r1
  3910. 80019ba: 631a str r2, [r3, #48] ; 0x30
  3911. 80019bc: e007 b.n 80019ce <HAL_ADC_Init+0x21a>
  3912. ADC_SQR1_L ,
  3913. ADC_SQR1_L_SHIFT(hadc->Init.NbrOfConversion) );
  3914. }
  3915. else
  3916. {
  3917. MODIFY_REG(hadc->Instance->SQR1,
  3918. 80019be: 687b ldr r3, [r7, #4]
  3919. 80019c0: 681b ldr r3, [r3, #0]
  3920. 80019c2: 6b1a ldr r2, [r3, #48] ; 0x30
  3921. 80019c4: 687b ldr r3, [r7, #4]
  3922. 80019c6: 681b ldr r3, [r3, #0]
  3923. 80019c8: f022 72f8 bic.w r2, r2, #32505856 ; 0x1f00000
  3924. 80019cc: 631a str r2, [r3, #48] ; 0x30
  3925. /* Check back that ADC registers have effectively been configured to */
  3926. /* ensure of no potential problem of ADC core IP clocking. */
  3927. /* Check through register CR2 (excluding execution control bits ADON, */
  3928. /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL). */
  3929. if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
  3930. 80019ce: 687b ldr r3, [r7, #4]
  3931. 80019d0: 681b ldr r3, [r3, #0]
  3932. 80019d2: 689a ldr r2, [r3, #8]
  3933. 80019d4: 4b19 ldr r3, [pc, #100] ; (8001a3c <HAL_ADC_Init+0x288>)
  3934. 80019d6: 4013 ands r3, r2
  3935. 80019d8: 6afa ldr r2, [r7, #44] ; 0x2c
  3936. 80019da: 429a cmp r2, r3
  3937. 80019dc: d10b bne.n 80019f6 <HAL_ADC_Init+0x242>
  3938. ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
  3939. ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL ))
  3940. == tmp_cr2)
  3941. {
  3942. /* Set ADC error code to none */
  3943. ADC_CLEAR_ERRORCODE(hadc);
  3944. 80019de: 687b ldr r3, [r7, #4]
  3945. 80019e0: 2200 movs r2, #0
  3946. 80019e2: 651a str r2, [r3, #80] ; 0x50
  3947. /* Set the ADC state */
  3948. ADC_STATE_CLR_SET(hadc->State,
  3949. 80019e4: 687b ldr r3, [r7, #4]
  3950. 80019e6: 6cdb ldr r3, [r3, #76] ; 0x4c
  3951. 80019e8: f023 0303 bic.w r3, r3, #3
  3952. 80019ec: f043 0201 orr.w r2, r3, #1
  3953. 80019f0: 687b ldr r3, [r7, #4]
  3954. 80019f2: 64da str r2, [r3, #76] ; 0x4c
  3955. 80019f4: e014 b.n 8001a20 <HAL_ADC_Init+0x26c>
  3956. HAL_ADC_STATE_READY);
  3957. }
  3958. else
  3959. {
  3960. /* Update ADC state machine to error */
  3961. ADC_STATE_CLR_SET(hadc->State,
  3962. 80019f6: 687b ldr r3, [r7, #4]
  3963. 80019f8: 6cdb ldr r3, [r3, #76] ; 0x4c
  3964. 80019fa: f023 0312 bic.w r3, r3, #18
  3965. 80019fe: f043 0210 orr.w r2, r3, #16
  3966. 8001a02: 687b ldr r3, [r7, #4]
  3967. 8001a04: 64da str r2, [r3, #76] ; 0x4c
  3968. HAL_ADC_STATE_BUSY_INTERNAL,
  3969. HAL_ADC_STATE_ERROR_INTERNAL);
  3970. /* Set ADC error code to ADC IP internal error */
  3971. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  3972. 8001a06: 687b ldr r3, [r7, #4]
  3973. 8001a08: 6d1b ldr r3, [r3, #80] ; 0x50
  3974. 8001a0a: f043 0201 orr.w r2, r3, #1
  3975. 8001a0e: 687b ldr r3, [r7, #4]
  3976. 8001a10: 651a str r2, [r3, #80] ; 0x50
  3977. tmp_hal_status = HAL_ERROR;
  3978. 8001a12: 2301 movs r3, #1
  3979. 8001a14: f887 3037 strb.w r3, [r7, #55] ; 0x37
  3980. 8001a18: e002 b.n 8001a20 <HAL_ADC_Init+0x26c>
  3981. }
  3982. }
  3983. else
  3984. {
  3985. tmp_hal_status = HAL_ERROR;
  3986. 8001a1a: 2301 movs r3, #1
  3987. 8001a1c: f887 3037 strb.w r3, [r7, #55] ; 0x37
  3988. }
  3989. /* Return function status */
  3990. return tmp_hal_status;
  3991. 8001a20: f897 3037 ldrb.w r3, [r7, #55] ; 0x37
  3992. }
  3993. 8001a24: 4618 mov r0, r3
  3994. 8001a26: 3738 adds r7, #56 ; 0x38
  3995. 8001a28: 46bd mov sp, r7
  3996. 8001a2a: bd80 pop {r7, pc}
  3997. 8001a2c: 40023800 .word 0x40023800
  3998. 8001a30: 40012700 .word 0x40012700
  3999. 8001a34: fcfc16ff .word 0xfcfc16ff
  4000. 8001a38: c0fff189 .word 0xc0fff189
  4001. 8001a3c: bf80fffe .word 0xbf80fffe
  4002. 08001a40 <HAL_ADC_Start>:
  4003. * Interruptions enabled in this function: None.
  4004. * @param hadc ADC handle
  4005. * @retval HAL status
  4006. */
  4007. HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
  4008. {
  4009. 8001a40: b580 push {r7, lr}
  4010. 8001a42: b084 sub sp, #16
  4011. 8001a44: af00 add r7, sp, #0
  4012. 8001a46: 6078 str r0, [r7, #4]
  4013. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  4014. 8001a48: 2300 movs r3, #0
  4015. 8001a4a: 73fb strb r3, [r7, #15]
  4016. /* Check the parameters */
  4017. assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
  4018. /* Process locked */
  4019. __HAL_LOCK(hadc);
  4020. 8001a4c: 687b ldr r3, [r7, #4]
  4021. 8001a4e: f893 3048 ldrb.w r3, [r3, #72] ; 0x48
  4022. 8001a52: 2b01 cmp r3, #1
  4023. 8001a54: d101 bne.n 8001a5a <HAL_ADC_Start+0x1a>
  4024. 8001a56: 2302 movs r3, #2
  4025. 8001a58: e04e b.n 8001af8 <HAL_ADC_Start+0xb8>
  4026. 8001a5a: 687b ldr r3, [r7, #4]
  4027. 8001a5c: 2201 movs r2, #1
  4028. 8001a5e: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4029. /* Enable the ADC peripheral */
  4030. tmp_hal_status = ADC_Enable(hadc);
  4031. 8001a62: 6878 ldr r0, [r7, #4]
  4032. 8001a64: f000 fa4e bl 8001f04 <ADC_Enable>
  4033. 8001a68: 4603 mov r3, r0
  4034. 8001a6a: 73fb strb r3, [r7, #15]
  4035. /* Start conversion if ADC is effectively enabled */
  4036. if (tmp_hal_status == HAL_OK)
  4037. 8001a6c: 7bfb ldrb r3, [r7, #15]
  4038. 8001a6e: 2b00 cmp r3, #0
  4039. 8001a70: d141 bne.n 8001af6 <HAL_ADC_Start+0xb6>
  4040. {
  4041. /* Set ADC state */
  4042. /* - Clear state bitfield related to regular group conversion results */
  4043. /* - Set state bitfield related to regular group operation */
  4044. ADC_STATE_CLR_SET(hadc->State,
  4045. 8001a72: 687b ldr r3, [r7, #4]
  4046. 8001a74: 6cdb ldr r3, [r3, #76] ; 0x4c
  4047. 8001a76: f423 63e0 bic.w r3, r3, #1792 ; 0x700
  4048. 8001a7a: f023 0301 bic.w r3, r3, #1
  4049. 8001a7e: f443 7280 orr.w r2, r3, #256 ; 0x100
  4050. 8001a82: 687b ldr r3, [r7, #4]
  4051. 8001a84: 64da str r2, [r3, #76] ; 0x4c
  4052. HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
  4053. HAL_ADC_STATE_REG_BUSY);
  4054. /* If conversions on group regular are also triggering group injected, */
  4055. /* update ADC state. */
  4056. if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
  4057. 8001a86: 687b ldr r3, [r7, #4]
  4058. 8001a88: 681b ldr r3, [r3, #0]
  4059. 8001a8a: 685b ldr r3, [r3, #4]
  4060. 8001a8c: f403 6380 and.w r3, r3, #1024 ; 0x400
  4061. 8001a90: 2b00 cmp r3, #0
  4062. 8001a92: d007 beq.n 8001aa4 <HAL_ADC_Start+0x64>
  4063. {
  4064. ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
  4065. 8001a94: 687b ldr r3, [r7, #4]
  4066. 8001a96: 6cdb ldr r3, [r3, #76] ; 0x4c
  4067. 8001a98: f423 5340 bic.w r3, r3, #12288 ; 0x3000
  4068. 8001a9c: f443 5280 orr.w r2, r3, #4096 ; 0x1000
  4069. 8001aa0: 687b ldr r3, [r7, #4]
  4070. 8001aa2: 64da str r2, [r3, #76] ; 0x4c
  4071. }
  4072. /* State machine update: Check if an injected conversion is ongoing */
  4073. if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
  4074. 8001aa4: 687b ldr r3, [r7, #4]
  4075. 8001aa6: 6cdb ldr r3, [r3, #76] ; 0x4c
  4076. 8001aa8: f403 5380 and.w r3, r3, #4096 ; 0x1000
  4077. 8001aac: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  4078. 8001ab0: d106 bne.n 8001ac0 <HAL_ADC_Start+0x80>
  4079. {
  4080. /* Reset ADC error code fields related to conversions on group regular */
  4081. CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
  4082. 8001ab2: 687b ldr r3, [r7, #4]
  4083. 8001ab4: 6d1b ldr r3, [r3, #80] ; 0x50
  4084. 8001ab6: f023 0206 bic.w r2, r3, #6
  4085. 8001aba: 687b ldr r3, [r7, #4]
  4086. 8001abc: 651a str r2, [r3, #80] ; 0x50
  4087. 8001abe: e002 b.n 8001ac6 <HAL_ADC_Start+0x86>
  4088. }
  4089. else
  4090. {
  4091. /* Reset ADC all error code fields */
  4092. ADC_CLEAR_ERRORCODE(hadc);
  4093. 8001ac0: 687b ldr r3, [r7, #4]
  4094. 8001ac2: 2200 movs r2, #0
  4095. 8001ac4: 651a str r2, [r3, #80] ; 0x50
  4096. }
  4097. /* Process unlocked */
  4098. /* Unlock before starting ADC conversions: in case of potential */
  4099. /* interruption, to let the process to ADC IRQ Handler. */
  4100. __HAL_UNLOCK(hadc);
  4101. 8001ac6: 687b ldr r3, [r7, #4]
  4102. 8001ac8: 2200 movs r2, #0
  4103. 8001aca: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4104. /* Clear regular group conversion flag and overrun flag */
  4105. /* (To ensure of no unknown state from potential previous ADC operations) */
  4106. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
  4107. 8001ace: 687b ldr r3, [r7, #4]
  4108. 8001ad0: 681b ldr r3, [r3, #0]
  4109. 8001ad2: f06f 0222 mvn.w r2, #34 ; 0x22
  4110. 8001ad6: 601a str r2, [r3, #0]
  4111. /* Enable conversion of regular group. */
  4112. /* If software start has been selected, conversion starts immediately. */
  4113. /* If external trigger has been selected, conversion will start at next */
  4114. /* trigger event. */
  4115. if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
  4116. 8001ad8: 687b ldr r3, [r7, #4]
  4117. 8001ada: 681b ldr r3, [r3, #0]
  4118. 8001adc: 689b ldr r3, [r3, #8]
  4119. 8001ade: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
  4120. 8001ae2: 2b00 cmp r3, #0
  4121. 8001ae4: d107 bne.n 8001af6 <HAL_ADC_Start+0xb6>
  4122. {
  4123. /* Start ADC conversion on regular group */
  4124. SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
  4125. 8001ae6: 687b ldr r3, [r7, #4]
  4126. 8001ae8: 681b ldr r3, [r3, #0]
  4127. 8001aea: 689a ldr r2, [r3, #8]
  4128. 8001aec: 687b ldr r3, [r7, #4]
  4129. 8001aee: 681b ldr r3, [r3, #0]
  4130. 8001af0: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000
  4131. 8001af4: 609a str r2, [r3, #8]
  4132. }
  4133. }
  4134. /* Return function status */
  4135. return tmp_hal_status;
  4136. 8001af6: 7bfb ldrb r3, [r7, #15]
  4137. }
  4138. 8001af8: 4618 mov r0, r3
  4139. 8001afa: 3710 adds r7, #16
  4140. 8001afc: 46bd mov sp, r7
  4141. 8001afe: bd80 pop {r7, pc}
  4142. 08001b00 <HAL_ADC_PollForConversion>:
  4143. * @param hadc ADC handle
  4144. * @param Timeout Timeout value in millisecond.
  4145. * @retval HAL status
  4146. */
  4147. HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
  4148. {
  4149. 8001b00: b580 push {r7, lr}
  4150. 8001b02: b084 sub sp, #16
  4151. 8001b04: af00 add r7, sp, #0
  4152. 8001b06: 6078 str r0, [r7, #4]
  4153. 8001b08: 6039 str r1, [r7, #0]
  4154. uint32_t tickstart = 0;
  4155. 8001b0a: 2300 movs r3, #0
  4156. 8001b0c: 60fb str r3, [r7, #12]
  4157. /* each conversion: */
  4158. /* Particular case is ADC configured in DMA mode and ADC sequencer with */
  4159. /* several ranks and polling for end of each conversion. */
  4160. /* For code simplicity sake, this particular case is generalized to */
  4161. /* ADC configured in DMA mode and and polling for end of each conversion. */
  4162. if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
  4163. 8001b0e: 687b ldr r3, [r7, #4]
  4164. 8001b10: 681b ldr r3, [r3, #0]
  4165. 8001b12: 689b ldr r3, [r3, #8]
  4166. 8001b14: f403 6380 and.w r3, r3, #1024 ; 0x400
  4167. 8001b18: f5b3 6f80 cmp.w r3, #1024 ; 0x400
  4168. 8001b1c: d113 bne.n 8001b46 <HAL_ADC_PollForConversion+0x46>
  4169. HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) )
  4170. 8001b1e: 687b ldr r3, [r7, #4]
  4171. 8001b20: 681b ldr r3, [r3, #0]
  4172. 8001b22: 689b ldr r3, [r3, #8]
  4173. 8001b24: f403 7380 and.w r3, r3, #256 ; 0x100
  4174. if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) &&
  4175. 8001b28: f5b3 7f80 cmp.w r3, #256 ; 0x100
  4176. 8001b2c: d10b bne.n 8001b46 <HAL_ADC_PollForConversion+0x46>
  4177. {
  4178. /* Update ADC state machine to error */
  4179. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
  4180. 8001b2e: 687b ldr r3, [r7, #4]
  4181. 8001b30: 6cdb ldr r3, [r3, #76] ; 0x4c
  4182. 8001b32: f043 0220 orr.w r2, r3, #32
  4183. 8001b36: 687b ldr r3, [r7, #4]
  4184. 8001b38: 64da str r2, [r3, #76] ; 0x4c
  4185. /* Process unlocked */
  4186. __HAL_UNLOCK(hadc);
  4187. 8001b3a: 687b ldr r3, [r7, #4]
  4188. 8001b3c: 2200 movs r2, #0
  4189. 8001b3e: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4190. return HAL_ERROR;
  4191. 8001b42: 2301 movs r3, #1
  4192. 8001b44: e061 b.n 8001c0a <HAL_ADC_PollForConversion+0x10a>
  4193. }
  4194. /* Get tick count */
  4195. tickstart = HAL_GetTick();
  4196. 8001b46: f7ff fe09 bl 800175c <HAL_GetTick>
  4197. 8001b4a: 60f8 str r0, [r7, #12]
  4198. /* Wait until End of Conversion flag is raised */
  4199. while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
  4200. 8001b4c: e01a b.n 8001b84 <HAL_ADC_PollForConversion+0x84>
  4201. {
  4202. /* Check if timeout is disabled (set to infinite wait) */
  4203. if(Timeout != HAL_MAX_DELAY)
  4204. 8001b4e: 683b ldr r3, [r7, #0]
  4205. 8001b50: f1b3 3fff cmp.w r3, #4294967295
  4206. 8001b54: d016 beq.n 8001b84 <HAL_ADC_PollForConversion+0x84>
  4207. {
  4208. if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
  4209. 8001b56: 683b ldr r3, [r7, #0]
  4210. 8001b58: 2b00 cmp r3, #0
  4211. 8001b5a: d007 beq.n 8001b6c <HAL_ADC_PollForConversion+0x6c>
  4212. 8001b5c: f7ff fdfe bl 800175c <HAL_GetTick>
  4213. 8001b60: 4602 mov r2, r0
  4214. 8001b62: 68fb ldr r3, [r7, #12]
  4215. 8001b64: 1ad3 subs r3, r2, r3
  4216. 8001b66: 683a ldr r2, [r7, #0]
  4217. 8001b68: 429a cmp r2, r3
  4218. 8001b6a: d20b bcs.n 8001b84 <HAL_ADC_PollForConversion+0x84>
  4219. {
  4220. /* Update ADC state machine to timeout */
  4221. SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
  4222. 8001b6c: 687b ldr r3, [r7, #4]
  4223. 8001b6e: 6cdb ldr r3, [r3, #76] ; 0x4c
  4224. 8001b70: f043 0204 orr.w r2, r3, #4
  4225. 8001b74: 687b ldr r3, [r7, #4]
  4226. 8001b76: 64da str r2, [r3, #76] ; 0x4c
  4227. /* Process unlocked */
  4228. __HAL_UNLOCK(hadc);
  4229. 8001b78: 687b ldr r3, [r7, #4]
  4230. 8001b7a: 2200 movs r2, #0
  4231. 8001b7c: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4232. return HAL_TIMEOUT;
  4233. 8001b80: 2303 movs r3, #3
  4234. 8001b82: e042 b.n 8001c0a <HAL_ADC_PollForConversion+0x10a>
  4235. while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
  4236. 8001b84: 687b ldr r3, [r7, #4]
  4237. 8001b86: 681b ldr r3, [r3, #0]
  4238. 8001b88: 681b ldr r3, [r3, #0]
  4239. 8001b8a: f003 0302 and.w r3, r3, #2
  4240. 8001b8e: 2b00 cmp r3, #0
  4241. 8001b90: d0dd beq.n 8001b4e <HAL_ADC_PollForConversion+0x4e>
  4242. }
  4243. /* Clear end of conversion flag of regular group if low power feature */
  4244. /* "Auto Wait" is disabled, to not interfere with this feature until data */
  4245. /* register is read using function HAL_ADC_GetValue(). */
  4246. if (hadc->Init.LowPowerAutoWait == DISABLE)
  4247. 8001b92: 687b ldr r3, [r7, #4]
  4248. 8001b94: 699b ldr r3, [r3, #24]
  4249. 8001b96: 2b00 cmp r3, #0
  4250. 8001b98: d104 bne.n 8001ba4 <HAL_ADC_PollForConversion+0xa4>
  4251. {
  4252. /* Clear regular group conversion flag */
  4253. __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
  4254. 8001b9a: 687b ldr r3, [r7, #4]
  4255. 8001b9c: 681b ldr r3, [r3, #0]
  4256. 8001b9e: f06f 0212 mvn.w r2, #18
  4257. 8001ba2: 601a str r2, [r3, #0]
  4258. }
  4259. /* Update ADC state machine */
  4260. SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
  4261. 8001ba4: 687b ldr r3, [r7, #4]
  4262. 8001ba6: 6cdb ldr r3, [r3, #76] ; 0x4c
  4263. 8001ba8: f443 7200 orr.w r2, r3, #512 ; 0x200
  4264. 8001bac: 687b ldr r3, [r7, #4]
  4265. 8001bae: 64da str r2, [r3, #76] ; 0x4c
  4266. /* by external trigger, continuous mode or scan sequence on going. */
  4267. /* Note: On STM32L1, there is no independent flag of end of sequence. */
  4268. /* The test of scan sequence on going is done either with scan */
  4269. /* sequence disabled or with end of conversion flag set to */
  4270. /* of end of sequence. */
  4271. if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
  4272. 8001bb0: 687b ldr r3, [r7, #4]
  4273. 8001bb2: 681b ldr r3, [r3, #0]
  4274. 8001bb4: 689b ldr r3, [r3, #8]
  4275. 8001bb6: f003 5340 and.w r3, r3, #805306368 ; 0x30000000
  4276. 8001bba: 2b00 cmp r3, #0
  4277. 8001bbc: d124 bne.n 8001c08 <HAL_ADC_PollForConversion+0x108>
  4278. (hadc->Init.ContinuousConvMode == DISABLE) &&
  4279. 8001bbe: 687b ldr r3, [r7, #4]
  4280. 8001bc0: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
  4281. if(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
  4282. 8001bc4: 2b00 cmp r3, #0
  4283. 8001bc6: d11f bne.n 8001c08 <HAL_ADC_PollForConversion+0x108>
  4284. (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
  4285. 8001bc8: 687b ldr r3, [r7, #4]
  4286. 8001bca: 681b ldr r3, [r3, #0]
  4287. 8001bcc: 6b1b ldr r3, [r3, #48] ; 0x30
  4288. 8001bce: f003 73f8 and.w r3, r3, #32505856 ; 0x1f00000
  4289. (hadc->Init.ContinuousConvMode == DISABLE) &&
  4290. 8001bd2: 2b00 cmp r3, #0
  4291. 8001bd4: d006 beq.n 8001be4 <HAL_ADC_PollForConversion+0xe4>
  4292. HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) )
  4293. 8001bd6: 687b ldr r3, [r7, #4]
  4294. 8001bd8: 681b ldr r3, [r3, #0]
  4295. 8001bda: 689b ldr r3, [r3, #8]
  4296. 8001bdc: f403 6380 and.w r3, r3, #1024 ; 0x400
  4297. (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
  4298. 8001be0: 2b00 cmp r3, #0
  4299. 8001be2: d111 bne.n 8001c08 <HAL_ADC_PollForConversion+0x108>
  4300. {
  4301. /* Set ADC state */
  4302. CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
  4303. 8001be4: 687b ldr r3, [r7, #4]
  4304. 8001be6: 6cdb ldr r3, [r3, #76] ; 0x4c
  4305. 8001be8: f423 7280 bic.w r2, r3, #256 ; 0x100
  4306. 8001bec: 687b ldr r3, [r7, #4]
  4307. 8001bee: 64da str r2, [r3, #76] ; 0x4c
  4308. if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
  4309. 8001bf0: 687b ldr r3, [r7, #4]
  4310. 8001bf2: 6cdb ldr r3, [r3, #76] ; 0x4c
  4311. 8001bf4: f403 5380 and.w r3, r3, #4096 ; 0x1000
  4312. 8001bf8: 2b00 cmp r3, #0
  4313. 8001bfa: d105 bne.n 8001c08 <HAL_ADC_PollForConversion+0x108>
  4314. {
  4315. SET_BIT(hadc->State, HAL_ADC_STATE_READY);
  4316. 8001bfc: 687b ldr r3, [r7, #4]
  4317. 8001bfe: 6cdb ldr r3, [r3, #76] ; 0x4c
  4318. 8001c00: f043 0201 orr.w r2, r3, #1
  4319. 8001c04: 687b ldr r3, [r7, #4]
  4320. 8001c06: 64da str r2, [r3, #76] ; 0x4c
  4321. }
  4322. }
  4323. /* Return ADC state */
  4324. return HAL_OK;
  4325. 8001c08: 2300 movs r3, #0
  4326. }
  4327. 8001c0a: 4618 mov r0, r3
  4328. 8001c0c: 3710 adds r7, #16
  4329. 8001c0e: 46bd mov sp, r7
  4330. 8001c10: bd80 pop {r7, pc}
  4331. 08001c12 <HAL_ADC_GetValue>:
  4332. * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
  4333. * @param hadc ADC handle
  4334. * @retval ADC group regular conversion data
  4335. */
  4336. uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
  4337. {
  4338. 8001c12: b480 push {r7}
  4339. 8001c14: b083 sub sp, #12
  4340. 8001c16: af00 add r7, sp, #0
  4341. 8001c18: 6078 str r0, [r7, #4]
  4342. /* Note: EOC flag is not cleared here by software because automatically */
  4343. /* cleared by hardware when reading register DR. */
  4344. /* Return ADC converted value */
  4345. return hadc->Instance->DR;
  4346. 8001c1a: 687b ldr r3, [r7, #4]
  4347. 8001c1c: 681b ldr r3, [r3, #0]
  4348. 8001c1e: 6d9b ldr r3, [r3, #88] ; 0x58
  4349. }
  4350. 8001c20: 4618 mov r0, r3
  4351. 8001c22: 370c adds r7, #12
  4352. 8001c24: 46bd mov sp, r7
  4353. 8001c26: bc80 pop {r7}
  4354. 8001c28: 4770 bx lr
  4355. ...
  4356. 08001c2c <HAL_ADC_ConfigChannel>:
  4357. * @param hadc ADC handle
  4358. * @param sConfig Structure of ADC channel for regular group.
  4359. * @retval HAL status
  4360. */
  4361. HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
  4362. {
  4363. 8001c2c: b480 push {r7}
  4364. 8001c2e: b085 sub sp, #20
  4365. 8001c30: af00 add r7, sp, #0
  4366. 8001c32: 6078 str r0, [r7, #4]
  4367. 8001c34: 6039 str r1, [r7, #0]
  4368. HAL_StatusTypeDef tmp_hal_status = HAL_OK;
  4369. 8001c36: 2300 movs r3, #0
  4370. 8001c38: 73fb strb r3, [r7, #15]
  4371. __IO uint32_t wait_loop_index = 0;
  4372. 8001c3a: 2300 movs r3, #0
  4373. 8001c3c: 60bb str r3, [r7, #8]
  4374. assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  4375. assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  4376. assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  4377. /* Process locked */
  4378. __HAL_LOCK(hadc);
  4379. 8001c3e: 687b ldr r3, [r7, #4]
  4380. 8001c40: f893 3048 ldrb.w r3, [r3, #72] ; 0x48
  4381. 8001c44: 2b01 cmp r3, #1
  4382. 8001c46: d101 bne.n 8001c4c <HAL_ADC_ConfigChannel+0x20>
  4383. 8001c48: 2302 movs r3, #2
  4384. 8001c4a: e14f b.n 8001eec <HAL_ADC_ConfigChannel+0x2c0>
  4385. 8001c4c: 687b ldr r3, [r7, #4]
  4386. 8001c4e: 2201 movs r2, #1
  4387. 8001c50: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4388. /* Regular sequence configuration */
  4389. /* For Rank 1 to 6 */
  4390. if (sConfig->Rank < 7)
  4391. 8001c54: 683b ldr r3, [r7, #0]
  4392. 8001c56: 685b ldr r3, [r3, #4]
  4393. 8001c58: 2b06 cmp r3, #6
  4394. 8001c5a: d81c bhi.n 8001c96 <HAL_ADC_ConfigChannel+0x6a>
  4395. {
  4396. MODIFY_REG(hadc->Instance->SQR5,
  4397. 8001c5c: 687b ldr r3, [r7, #4]
  4398. 8001c5e: 681b ldr r3, [r3, #0]
  4399. 8001c60: 6c19 ldr r1, [r3, #64] ; 0x40
  4400. 8001c62: 683b ldr r3, [r7, #0]
  4401. 8001c64: 685a ldr r2, [r3, #4]
  4402. 8001c66: 4613 mov r3, r2
  4403. 8001c68: 009b lsls r3, r3, #2
  4404. 8001c6a: 4413 add r3, r2
  4405. 8001c6c: 3b05 subs r3, #5
  4406. 8001c6e: 221f movs r2, #31
  4407. 8001c70: fa02 f303 lsl.w r3, r2, r3
  4408. 8001c74: 43db mvns r3, r3
  4409. 8001c76: 4019 ands r1, r3
  4410. 8001c78: 683b ldr r3, [r7, #0]
  4411. 8001c7a: 6818 ldr r0, [r3, #0]
  4412. 8001c7c: 683b ldr r3, [r7, #0]
  4413. 8001c7e: 685a ldr r2, [r3, #4]
  4414. 8001c80: 4613 mov r3, r2
  4415. 8001c82: 009b lsls r3, r3, #2
  4416. 8001c84: 4413 add r3, r2
  4417. 8001c86: 3b05 subs r3, #5
  4418. 8001c88: fa00 f203 lsl.w r2, r0, r3
  4419. 8001c8c: 687b ldr r3, [r7, #4]
  4420. 8001c8e: 681b ldr r3, [r3, #0]
  4421. 8001c90: 430a orrs r2, r1
  4422. 8001c92: 641a str r2, [r3, #64] ; 0x40
  4423. 8001c94: e07e b.n 8001d94 <HAL_ADC_ConfigChannel+0x168>
  4424. ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
  4425. ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
  4426. }
  4427. /* For Rank 7 to 12 */
  4428. else if (sConfig->Rank < 13)
  4429. 8001c96: 683b ldr r3, [r7, #0]
  4430. 8001c98: 685b ldr r3, [r3, #4]
  4431. 8001c9a: 2b0c cmp r3, #12
  4432. 8001c9c: d81c bhi.n 8001cd8 <HAL_ADC_ConfigChannel+0xac>
  4433. {
  4434. MODIFY_REG(hadc->Instance->SQR4,
  4435. 8001c9e: 687b ldr r3, [r7, #4]
  4436. 8001ca0: 681b ldr r3, [r3, #0]
  4437. 8001ca2: 6bd9 ldr r1, [r3, #60] ; 0x3c
  4438. 8001ca4: 683b ldr r3, [r7, #0]
  4439. 8001ca6: 685a ldr r2, [r3, #4]
  4440. 8001ca8: 4613 mov r3, r2
  4441. 8001caa: 009b lsls r3, r3, #2
  4442. 8001cac: 4413 add r3, r2
  4443. 8001cae: 3b23 subs r3, #35 ; 0x23
  4444. 8001cb0: 221f movs r2, #31
  4445. 8001cb2: fa02 f303 lsl.w r3, r2, r3
  4446. 8001cb6: 43db mvns r3, r3
  4447. 8001cb8: 4019 ands r1, r3
  4448. 8001cba: 683b ldr r3, [r7, #0]
  4449. 8001cbc: 6818 ldr r0, [r3, #0]
  4450. 8001cbe: 683b ldr r3, [r7, #0]
  4451. 8001cc0: 685a ldr r2, [r3, #4]
  4452. 8001cc2: 4613 mov r3, r2
  4453. 8001cc4: 009b lsls r3, r3, #2
  4454. 8001cc6: 4413 add r3, r2
  4455. 8001cc8: 3b23 subs r3, #35 ; 0x23
  4456. 8001cca: fa00 f203 lsl.w r2, r0, r3
  4457. 8001cce: 687b ldr r3, [r7, #4]
  4458. 8001cd0: 681b ldr r3, [r3, #0]
  4459. 8001cd2: 430a orrs r2, r1
  4460. 8001cd4: 63da str r2, [r3, #60] ; 0x3c
  4461. 8001cd6: e05d b.n 8001d94 <HAL_ADC_ConfigChannel+0x168>
  4462. ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
  4463. ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
  4464. }
  4465. /* For Rank 13 to 18 */
  4466. else if (sConfig->Rank < 19)
  4467. 8001cd8: 683b ldr r3, [r7, #0]
  4468. 8001cda: 685b ldr r3, [r3, #4]
  4469. 8001cdc: 2b12 cmp r3, #18
  4470. 8001cde: d81c bhi.n 8001d1a <HAL_ADC_ConfigChannel+0xee>
  4471. {
  4472. MODIFY_REG(hadc->Instance->SQR3,
  4473. 8001ce0: 687b ldr r3, [r7, #4]
  4474. 8001ce2: 681b ldr r3, [r3, #0]
  4475. 8001ce4: 6b99 ldr r1, [r3, #56] ; 0x38
  4476. 8001ce6: 683b ldr r3, [r7, #0]
  4477. 8001ce8: 685a ldr r2, [r3, #4]
  4478. 8001cea: 4613 mov r3, r2
  4479. 8001cec: 009b lsls r3, r3, #2
  4480. 8001cee: 4413 add r3, r2
  4481. 8001cf0: 3b41 subs r3, #65 ; 0x41
  4482. 8001cf2: 221f movs r2, #31
  4483. 8001cf4: fa02 f303 lsl.w r3, r2, r3
  4484. 8001cf8: 43db mvns r3, r3
  4485. 8001cfa: 4019 ands r1, r3
  4486. 8001cfc: 683b ldr r3, [r7, #0]
  4487. 8001cfe: 6818 ldr r0, [r3, #0]
  4488. 8001d00: 683b ldr r3, [r7, #0]
  4489. 8001d02: 685a ldr r2, [r3, #4]
  4490. 8001d04: 4613 mov r3, r2
  4491. 8001d06: 009b lsls r3, r3, #2
  4492. 8001d08: 4413 add r3, r2
  4493. 8001d0a: 3b41 subs r3, #65 ; 0x41
  4494. 8001d0c: fa00 f203 lsl.w r2, r0, r3
  4495. 8001d10: 687b ldr r3, [r7, #4]
  4496. 8001d12: 681b ldr r3, [r3, #0]
  4497. 8001d14: 430a orrs r2, r1
  4498. 8001d16: 639a str r2, [r3, #56] ; 0x38
  4499. 8001d18: e03c b.n 8001d94 <HAL_ADC_ConfigChannel+0x168>
  4500. ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
  4501. ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
  4502. }
  4503. /* For Rank 19 to 24 */
  4504. else if (sConfig->Rank < 25)
  4505. 8001d1a: 683b ldr r3, [r7, #0]
  4506. 8001d1c: 685b ldr r3, [r3, #4]
  4507. 8001d1e: 2b18 cmp r3, #24
  4508. 8001d20: d81c bhi.n 8001d5c <HAL_ADC_ConfigChannel+0x130>
  4509. {
  4510. MODIFY_REG(hadc->Instance->SQR2,
  4511. 8001d22: 687b ldr r3, [r7, #4]
  4512. 8001d24: 681b ldr r3, [r3, #0]
  4513. 8001d26: 6b59 ldr r1, [r3, #52] ; 0x34
  4514. 8001d28: 683b ldr r3, [r7, #0]
  4515. 8001d2a: 685a ldr r2, [r3, #4]
  4516. 8001d2c: 4613 mov r3, r2
  4517. 8001d2e: 009b lsls r3, r3, #2
  4518. 8001d30: 4413 add r3, r2
  4519. 8001d32: 3b5f subs r3, #95 ; 0x5f
  4520. 8001d34: 221f movs r2, #31
  4521. 8001d36: fa02 f303 lsl.w r3, r2, r3
  4522. 8001d3a: 43db mvns r3, r3
  4523. 8001d3c: 4019 ands r1, r3
  4524. 8001d3e: 683b ldr r3, [r7, #0]
  4525. 8001d40: 6818 ldr r0, [r3, #0]
  4526. 8001d42: 683b ldr r3, [r7, #0]
  4527. 8001d44: 685a ldr r2, [r3, #4]
  4528. 8001d46: 4613 mov r3, r2
  4529. 8001d48: 009b lsls r3, r3, #2
  4530. 8001d4a: 4413 add r3, r2
  4531. 8001d4c: 3b5f subs r3, #95 ; 0x5f
  4532. 8001d4e: fa00 f203 lsl.w r2, r0, r3
  4533. 8001d52: 687b ldr r3, [r7, #4]
  4534. 8001d54: 681b ldr r3, [r3, #0]
  4535. 8001d56: 430a orrs r2, r1
  4536. 8001d58: 635a str r2, [r3, #52] ; 0x34
  4537. 8001d5a: e01b b.n 8001d94 <HAL_ADC_ConfigChannel+0x168>
  4538. ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
  4539. }
  4540. /* For Rank 25 to 28 */
  4541. else
  4542. {
  4543. MODIFY_REG(hadc->Instance->SQR1,
  4544. 8001d5c: 687b ldr r3, [r7, #4]
  4545. 8001d5e: 681b ldr r3, [r3, #0]
  4546. 8001d60: 6b19 ldr r1, [r3, #48] ; 0x30
  4547. 8001d62: 683b ldr r3, [r7, #0]
  4548. 8001d64: 685a ldr r2, [r3, #4]
  4549. 8001d66: 4613 mov r3, r2
  4550. 8001d68: 009b lsls r3, r3, #2
  4551. 8001d6a: 4413 add r3, r2
  4552. 8001d6c: 3b7d subs r3, #125 ; 0x7d
  4553. 8001d6e: 221f movs r2, #31
  4554. 8001d70: fa02 f303 lsl.w r3, r2, r3
  4555. 8001d74: 43db mvns r3, r3
  4556. 8001d76: 4019 ands r1, r3
  4557. 8001d78: 683b ldr r3, [r7, #0]
  4558. 8001d7a: 6818 ldr r0, [r3, #0]
  4559. 8001d7c: 683b ldr r3, [r7, #0]
  4560. 8001d7e: 685a ldr r2, [r3, #4]
  4561. 8001d80: 4613 mov r3, r2
  4562. 8001d82: 009b lsls r3, r3, #2
  4563. 8001d84: 4413 add r3, r2
  4564. 8001d86: 3b7d subs r3, #125 ; 0x7d
  4565. 8001d88: fa00 f203 lsl.w r2, r0, r3
  4566. 8001d8c: 687b ldr r3, [r7, #4]
  4567. 8001d8e: 681b ldr r3, [r3, #0]
  4568. 8001d90: 430a orrs r2, r1
  4569. 8001d92: 631a str r2, [r3, #48] ; 0x30
  4570. }
  4571. /* Channel sampling time configuration */
  4572. /* For channels 0 to 9 */
  4573. if (sConfig->Channel < ADC_CHANNEL_10)
  4574. 8001d94: 683b ldr r3, [r7, #0]
  4575. 8001d96: 681b ldr r3, [r3, #0]
  4576. 8001d98: 2b09 cmp r3, #9
  4577. 8001d9a: d81a bhi.n 8001dd2 <HAL_ADC_ConfigChannel+0x1a6>
  4578. {
  4579. MODIFY_REG(hadc->Instance->SMPR3,
  4580. 8001d9c: 687b ldr r3, [r7, #4]
  4581. 8001d9e: 681b ldr r3, [r3, #0]
  4582. 8001da0: 6959 ldr r1, [r3, #20]
  4583. 8001da2: 683b ldr r3, [r7, #0]
  4584. 8001da4: 681a ldr r2, [r3, #0]
  4585. 8001da6: 4613 mov r3, r2
  4586. 8001da8: 005b lsls r3, r3, #1
  4587. 8001daa: 4413 add r3, r2
  4588. 8001dac: 2207 movs r2, #7
  4589. 8001dae: fa02 f303 lsl.w r3, r2, r3
  4590. 8001db2: 43db mvns r3, r3
  4591. 8001db4: 4019 ands r1, r3
  4592. 8001db6: 683b ldr r3, [r7, #0]
  4593. 8001db8: 6898 ldr r0, [r3, #8]
  4594. 8001dba: 683b ldr r3, [r7, #0]
  4595. 8001dbc: 681a ldr r2, [r3, #0]
  4596. 8001dbe: 4613 mov r3, r2
  4597. 8001dc0: 005b lsls r3, r3, #1
  4598. 8001dc2: 4413 add r3, r2
  4599. 8001dc4: fa00 f203 lsl.w r2, r0, r3
  4600. 8001dc8: 687b ldr r3, [r7, #4]
  4601. 8001dca: 681b ldr r3, [r3, #0]
  4602. 8001dcc: 430a orrs r2, r1
  4603. 8001dce: 615a str r2, [r3, #20]
  4604. 8001dd0: e05d b.n 8001e8e <HAL_ADC_ConfigChannel+0x262>
  4605. ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
  4606. ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
  4607. }
  4608. /* For channels 10 to 19 */
  4609. else if (sConfig->Channel < ADC_CHANNEL_20)
  4610. 8001dd2: 683b ldr r3, [r7, #0]
  4611. 8001dd4: 681b ldr r3, [r3, #0]
  4612. 8001dd6: 2b13 cmp r3, #19
  4613. 8001dd8: d81c bhi.n 8001e14 <HAL_ADC_ConfigChannel+0x1e8>
  4614. {
  4615. MODIFY_REG(hadc->Instance->SMPR2,
  4616. 8001dda: 687b ldr r3, [r7, #4]
  4617. 8001ddc: 681b ldr r3, [r3, #0]
  4618. 8001dde: 6919 ldr r1, [r3, #16]
  4619. 8001de0: 683b ldr r3, [r7, #0]
  4620. 8001de2: 681a ldr r2, [r3, #0]
  4621. 8001de4: 4613 mov r3, r2
  4622. 8001de6: 005b lsls r3, r3, #1
  4623. 8001de8: 4413 add r3, r2
  4624. 8001dea: 3b1e subs r3, #30
  4625. 8001dec: 2207 movs r2, #7
  4626. 8001dee: fa02 f303 lsl.w r3, r2, r3
  4627. 8001df2: 43db mvns r3, r3
  4628. 8001df4: 4019 ands r1, r3
  4629. 8001df6: 683b ldr r3, [r7, #0]
  4630. 8001df8: 6898 ldr r0, [r3, #8]
  4631. 8001dfa: 683b ldr r3, [r7, #0]
  4632. 8001dfc: 681a ldr r2, [r3, #0]
  4633. 8001dfe: 4613 mov r3, r2
  4634. 8001e00: 005b lsls r3, r3, #1
  4635. 8001e02: 4413 add r3, r2
  4636. 8001e04: 3b1e subs r3, #30
  4637. 8001e06: fa00 f203 lsl.w r2, r0, r3
  4638. 8001e0a: 687b ldr r3, [r7, #4]
  4639. 8001e0c: 681b ldr r3, [r3, #0]
  4640. 8001e0e: 430a orrs r2, r1
  4641. 8001e10: 611a str r2, [r3, #16]
  4642. 8001e12: e03c b.n 8001e8e <HAL_ADC_ConfigChannel+0x262>
  4643. ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
  4644. ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
  4645. }
  4646. /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
  4647. /* For channels 20 to 29 for devices Cat4, Cat.5 */
  4648. else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
  4649. 8001e14: 683b ldr r3, [r7, #0]
  4650. 8001e16: 681b ldr r3, [r3, #0]
  4651. 8001e18: 2b1d cmp r3, #29
  4652. 8001e1a: d81c bhi.n 8001e56 <HAL_ADC_ConfigChannel+0x22a>
  4653. {
  4654. MODIFY_REG(hadc->Instance->SMPR1,
  4655. 8001e1c: 687b ldr r3, [r7, #4]
  4656. 8001e1e: 681b ldr r3, [r3, #0]
  4657. 8001e20: 68d9 ldr r1, [r3, #12]
  4658. 8001e22: 683b ldr r3, [r7, #0]
  4659. 8001e24: 681a ldr r2, [r3, #0]
  4660. 8001e26: 4613 mov r3, r2
  4661. 8001e28: 005b lsls r3, r3, #1
  4662. 8001e2a: 4413 add r3, r2
  4663. 8001e2c: 3b3c subs r3, #60 ; 0x3c
  4664. 8001e2e: 2207 movs r2, #7
  4665. 8001e30: fa02 f303 lsl.w r3, r2, r3
  4666. 8001e34: 43db mvns r3, r3
  4667. 8001e36: 4019 ands r1, r3
  4668. 8001e38: 683b ldr r3, [r7, #0]
  4669. 8001e3a: 6898 ldr r0, [r3, #8]
  4670. 8001e3c: 683b ldr r3, [r7, #0]
  4671. 8001e3e: 681a ldr r2, [r3, #0]
  4672. 8001e40: 4613 mov r3, r2
  4673. 8001e42: 005b lsls r3, r3, #1
  4674. 8001e44: 4413 add r3, r2
  4675. 8001e46: 3b3c subs r3, #60 ; 0x3c
  4676. 8001e48: fa00 f203 lsl.w r2, r0, r3
  4677. 8001e4c: 687b ldr r3, [r7, #4]
  4678. 8001e4e: 681b ldr r3, [r3, #0]
  4679. 8001e50: 430a orrs r2, r1
  4680. 8001e52: 60da str r2, [r3, #12]
  4681. 8001e54: e01b b.n 8001e8e <HAL_ADC_ConfigChannel+0x262>
  4682. ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
  4683. }
  4684. /* For channels 30 to 31 for devices Cat4, Cat.5 */
  4685. else
  4686. {
  4687. ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
  4688. 8001e56: 687b ldr r3, [r7, #4]
  4689. 8001e58: 681b ldr r3, [r3, #0]
  4690. 8001e5a: 6dd9 ldr r1, [r3, #92] ; 0x5c
  4691. 8001e5c: 683b ldr r3, [r7, #0]
  4692. 8001e5e: 681a ldr r2, [r3, #0]
  4693. 8001e60: 4613 mov r3, r2
  4694. 8001e62: 005b lsls r3, r3, #1
  4695. 8001e64: 4413 add r3, r2
  4696. 8001e66: 3b5a subs r3, #90 ; 0x5a
  4697. 8001e68: 2207 movs r2, #7
  4698. 8001e6a: fa02 f303 lsl.w r3, r2, r3
  4699. 8001e6e: 43db mvns r3, r3
  4700. 8001e70: 4019 ands r1, r3
  4701. 8001e72: 683b ldr r3, [r7, #0]
  4702. 8001e74: 6898 ldr r0, [r3, #8]
  4703. 8001e76: 683b ldr r3, [r7, #0]
  4704. 8001e78: 681a ldr r2, [r3, #0]
  4705. 8001e7a: 4613 mov r3, r2
  4706. 8001e7c: 005b lsls r3, r3, #1
  4707. 8001e7e: 4413 add r3, r2
  4708. 8001e80: 3b5a subs r3, #90 ; 0x5a
  4709. 8001e82: fa00 f203 lsl.w r2, r0, r3
  4710. 8001e86: 687b ldr r3, [r7, #4]
  4711. 8001e88: 681b ldr r3, [r3, #0]
  4712. 8001e8a: 430a orrs r2, r1
  4713. 8001e8c: 65da str r2, [r3, #92] ; 0x5c
  4714. }
  4715. /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
  4716. /* and VREFINT measurement path. */
  4717. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
  4718. 8001e8e: 683b ldr r3, [r7, #0]
  4719. 8001e90: 681b ldr r3, [r3, #0]
  4720. 8001e92: 2b10 cmp r3, #16
  4721. 8001e94: d003 beq.n 8001e9e <HAL_ADC_ConfigChannel+0x272>
  4722. (sConfig->Channel == ADC_CHANNEL_VREFINT) )
  4723. 8001e96: 683b ldr r3, [r7, #0]
  4724. 8001e98: 681b ldr r3, [r3, #0]
  4725. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
  4726. 8001e9a: 2b11 cmp r3, #17
  4727. 8001e9c: d121 bne.n 8001ee2 <HAL_ADC_ConfigChannel+0x2b6>
  4728. {
  4729. if (READ_BIT(ADC->CCR, ADC_CCR_TSVREFE) == RESET)
  4730. 8001e9e: 4b16 ldr r3, [pc, #88] ; (8001ef8 <HAL_ADC_ConfigChannel+0x2cc>)
  4731. 8001ea0: 685b ldr r3, [r3, #4]
  4732. 8001ea2: f403 0300 and.w r3, r3, #8388608 ; 0x800000
  4733. 8001ea6: 2b00 cmp r3, #0
  4734. 8001ea8: d11b bne.n 8001ee2 <HAL_ADC_ConfigChannel+0x2b6>
  4735. {
  4736. SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
  4737. 8001eaa: 4b13 ldr r3, [pc, #76] ; (8001ef8 <HAL_ADC_ConfigChannel+0x2cc>)
  4738. 8001eac: 685b ldr r3, [r3, #4]
  4739. 8001eae: 4a12 ldr r2, [pc, #72] ; (8001ef8 <HAL_ADC_ConfigChannel+0x2cc>)
  4740. 8001eb0: f443 0300 orr.w r3, r3, #8388608 ; 0x800000
  4741. 8001eb4: 6053 str r3, [r2, #4]
  4742. if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR))
  4743. 8001eb6: 683b ldr r3, [r7, #0]
  4744. 8001eb8: 681b ldr r3, [r3, #0]
  4745. 8001eba: 2b10 cmp r3, #16
  4746. 8001ebc: d111 bne.n 8001ee2 <HAL_ADC_ConfigChannel+0x2b6>
  4747. {
  4748. /* Delay for temperature sensor stabilization time */
  4749. /* Compute number of CPU cycles to wait for */
  4750. wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000));
  4751. 8001ebe: 4b0f ldr r3, [pc, #60] ; (8001efc <HAL_ADC_ConfigChannel+0x2d0>)
  4752. 8001ec0: 681b ldr r3, [r3, #0]
  4753. 8001ec2: 4a0f ldr r2, [pc, #60] ; (8001f00 <HAL_ADC_ConfigChannel+0x2d4>)
  4754. 8001ec4: fba2 2303 umull r2, r3, r2, r3
  4755. 8001ec8: 0c9a lsrs r2, r3, #18
  4756. 8001eca: 4613 mov r3, r2
  4757. 8001ecc: 009b lsls r3, r3, #2
  4758. 8001ece: 4413 add r3, r2
  4759. 8001ed0: 005b lsls r3, r3, #1
  4760. 8001ed2: 60bb str r3, [r7, #8]
  4761. while(wait_loop_index != 0)
  4762. 8001ed4: e002 b.n 8001edc <HAL_ADC_ConfigChannel+0x2b0>
  4763. {
  4764. wait_loop_index--;
  4765. 8001ed6: 68bb ldr r3, [r7, #8]
  4766. 8001ed8: 3b01 subs r3, #1
  4767. 8001eda: 60bb str r3, [r7, #8]
  4768. while(wait_loop_index != 0)
  4769. 8001edc: 68bb ldr r3, [r7, #8]
  4770. 8001ede: 2b00 cmp r3, #0
  4771. 8001ee0: d1f9 bne.n 8001ed6 <HAL_ADC_ConfigChannel+0x2aa>
  4772. }
  4773. }
  4774. }
  4775. /* Process unlocked */
  4776. __HAL_UNLOCK(hadc);
  4777. 8001ee2: 687b ldr r3, [r7, #4]
  4778. 8001ee4: 2200 movs r2, #0
  4779. 8001ee6: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4780. /* Return function status */
  4781. return tmp_hal_status;
  4782. 8001eea: 7bfb ldrb r3, [r7, #15]
  4783. }
  4784. 8001eec: 4618 mov r0, r3
  4785. 8001eee: 3714 adds r7, #20
  4786. 8001ef0: 46bd mov sp, r7
  4787. 8001ef2: bc80 pop {r7}
  4788. 8001ef4: 4770 bx lr
  4789. 8001ef6: bf00 nop
  4790. 8001ef8: 40012700 .word 0x40012700
  4791. 8001efc: 20000004 .word 0x20000004
  4792. 8001f00: 431bde83 .word 0x431bde83
  4793. 08001f04 <ADC_Enable>:
  4794. * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)".
  4795. * @param hadc ADC handle
  4796. * @retval HAL status.
  4797. */
  4798. HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
  4799. {
  4800. 8001f04: b580 push {r7, lr}
  4801. 8001f06: b084 sub sp, #16
  4802. 8001f08: af00 add r7, sp, #0
  4803. 8001f0a: 6078 str r0, [r7, #4]
  4804. uint32_t tickstart = 0;
  4805. 8001f0c: 2300 movs r3, #0
  4806. 8001f0e: 60fb str r3, [r7, #12]
  4807. __IO uint32_t wait_loop_index = 0;
  4808. 8001f10: 2300 movs r3, #0
  4809. 8001f12: 60bb str r3, [r7, #8]
  4810. /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
  4811. /* enabling phase not yet completed: flag ADC ready not yet set). */
  4812. /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
  4813. /* causes: ADC clock not running, ...). */
  4814. if (ADC_IS_ENABLE(hadc) == RESET)
  4815. 8001f14: 687b ldr r3, [r7, #4]
  4816. 8001f16: 681b ldr r3, [r3, #0]
  4817. 8001f18: 681b ldr r3, [r3, #0]
  4818. 8001f1a: f003 0340 and.w r3, r3, #64 ; 0x40
  4819. 8001f1e: 2b40 cmp r3, #64 ; 0x40
  4820. 8001f20: d03c beq.n 8001f9c <ADC_Enable+0x98>
  4821. {
  4822. /* Enable the Peripheral */
  4823. __HAL_ADC_ENABLE(hadc);
  4824. 8001f22: 687b ldr r3, [r7, #4]
  4825. 8001f24: 681b ldr r3, [r3, #0]
  4826. 8001f26: 689a ldr r2, [r3, #8]
  4827. 8001f28: 687b ldr r3, [r7, #4]
  4828. 8001f2a: 681b ldr r3, [r3, #0]
  4829. 8001f2c: f042 0201 orr.w r2, r2, #1
  4830. 8001f30: 609a str r2, [r3, #8]
  4831. /* Delay for ADC stabilization time */
  4832. /* Compute number of CPU cycles to wait for */
  4833. wait_loop_index = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000));
  4834. 8001f32: 4b1d ldr r3, [pc, #116] ; (8001fa8 <ADC_Enable+0xa4>)
  4835. 8001f34: 681b ldr r3, [r3, #0]
  4836. 8001f36: 4a1d ldr r2, [pc, #116] ; (8001fac <ADC_Enable+0xa8>)
  4837. 8001f38: fba2 2303 umull r2, r3, r2, r3
  4838. 8001f3c: 0c9a lsrs r2, r3, #18
  4839. 8001f3e: 4613 mov r3, r2
  4840. 8001f40: 005b lsls r3, r3, #1
  4841. 8001f42: 4413 add r3, r2
  4842. 8001f44: 60bb str r3, [r7, #8]
  4843. while(wait_loop_index != 0)
  4844. 8001f46: e002 b.n 8001f4e <ADC_Enable+0x4a>
  4845. {
  4846. wait_loop_index--;
  4847. 8001f48: 68bb ldr r3, [r7, #8]
  4848. 8001f4a: 3b01 subs r3, #1
  4849. 8001f4c: 60bb str r3, [r7, #8]
  4850. while(wait_loop_index != 0)
  4851. 8001f4e: 68bb ldr r3, [r7, #8]
  4852. 8001f50: 2b00 cmp r3, #0
  4853. 8001f52: d1f9 bne.n 8001f48 <ADC_Enable+0x44>
  4854. }
  4855. /* Get tick count */
  4856. tickstart = HAL_GetTick();
  4857. 8001f54: f7ff fc02 bl 800175c <HAL_GetTick>
  4858. 8001f58: 60f8 str r0, [r7, #12]
  4859. /* Wait for ADC effectively enabled */
  4860. while(ADC_IS_ENABLE(hadc) == RESET)
  4861. 8001f5a: e018 b.n 8001f8e <ADC_Enable+0x8a>
  4862. {
  4863. if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
  4864. 8001f5c: f7ff fbfe bl 800175c <HAL_GetTick>
  4865. 8001f60: 4602 mov r2, r0
  4866. 8001f62: 68fb ldr r3, [r7, #12]
  4867. 8001f64: 1ad3 subs r3, r2, r3
  4868. 8001f66: 2b02 cmp r3, #2
  4869. 8001f68: d911 bls.n 8001f8e <ADC_Enable+0x8a>
  4870. {
  4871. /* Update ADC state machine to error */
  4872. SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
  4873. 8001f6a: 687b ldr r3, [r7, #4]
  4874. 8001f6c: 6cdb ldr r3, [r3, #76] ; 0x4c
  4875. 8001f6e: f043 0210 orr.w r2, r3, #16
  4876. 8001f72: 687b ldr r3, [r7, #4]
  4877. 8001f74: 64da str r2, [r3, #76] ; 0x4c
  4878. /* Set ADC error code to ADC IP internal error */
  4879. SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
  4880. 8001f76: 687b ldr r3, [r7, #4]
  4881. 8001f78: 6d1b ldr r3, [r3, #80] ; 0x50
  4882. 8001f7a: f043 0201 orr.w r2, r3, #1
  4883. 8001f7e: 687b ldr r3, [r7, #4]
  4884. 8001f80: 651a str r2, [r3, #80] ; 0x50
  4885. /* Process unlocked */
  4886. __HAL_UNLOCK(hadc);
  4887. 8001f82: 687b ldr r3, [r7, #4]
  4888. 8001f84: 2200 movs r2, #0
  4889. 8001f86: f883 2048 strb.w r2, [r3, #72] ; 0x48
  4890. return HAL_ERROR;
  4891. 8001f8a: 2301 movs r3, #1
  4892. 8001f8c: e007 b.n 8001f9e <ADC_Enable+0x9a>
  4893. while(ADC_IS_ENABLE(hadc) == RESET)
  4894. 8001f8e: 687b ldr r3, [r7, #4]
  4895. 8001f90: 681b ldr r3, [r3, #0]
  4896. 8001f92: 681b ldr r3, [r3, #0]
  4897. 8001f94: f003 0340 and.w r3, r3, #64 ; 0x40
  4898. 8001f98: 2b40 cmp r3, #64 ; 0x40
  4899. 8001f9a: d1df bne.n 8001f5c <ADC_Enable+0x58>
  4900. }
  4901. }
  4902. }
  4903. /* Return HAL status */
  4904. return HAL_OK;
  4905. 8001f9c: 2300 movs r3, #0
  4906. }
  4907. 8001f9e: 4618 mov r0, r3
  4908. 8001fa0: 3710 adds r7, #16
  4909. 8001fa2: 46bd mov sp, r7
  4910. 8001fa4: bd80 pop {r7, pc}
  4911. 8001fa6: bf00 nop
  4912. 8001fa8: 20000004 .word 0x20000004
  4913. 8001fac: 431bde83 .word 0x431bde83
  4914. 08001fb0 <__NVIC_SetPriorityGrouping>:
  4915. In case of a conflict between priority grouping and available
  4916. priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  4917. \param [in] PriorityGroup Priority grouping field.
  4918. */
  4919. __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  4920. {
  4921. 8001fb0: b480 push {r7}
  4922. 8001fb2: b085 sub sp, #20
  4923. 8001fb4: af00 add r7, sp, #0
  4924. 8001fb6: 6078 str r0, [r7, #4]
  4925. uint32_t reg_value;
  4926. uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
  4927. 8001fb8: 687b ldr r3, [r7, #4]
  4928. 8001fba: f003 0307 and.w r3, r3, #7
  4929. 8001fbe: 60fb str r3, [r7, #12]
  4930. reg_value = SCB->AIRCR; /* read old register configuration */
  4931. 8001fc0: 4b0c ldr r3, [pc, #48] ; (8001ff4 <__NVIC_SetPriorityGrouping+0x44>)
  4932. 8001fc2: 68db ldr r3, [r3, #12]
  4933. 8001fc4: 60bb str r3, [r7, #8]
  4934. reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
  4935. 8001fc6: 68ba ldr r2, [r7, #8]
  4936. 8001fc8: f64f 03ff movw r3, #63743 ; 0xf8ff
  4937. 8001fcc: 4013 ands r3, r2
  4938. 8001fce: 60bb str r3, [r7, #8]
  4939. reg_value = (reg_value |
  4940. ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  4941. (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
  4942. 8001fd0: 68fb ldr r3, [r7, #12]
  4943. 8001fd2: 021a lsls r2, r3, #8
  4944. ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
  4945. 8001fd4: 68bb ldr r3, [r7, #8]
  4946. 8001fd6: 4313 orrs r3, r2
  4947. reg_value = (reg_value |
  4948. 8001fd8: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
  4949. 8001fdc: f443 3300 orr.w r3, r3, #131072 ; 0x20000
  4950. 8001fe0: 60bb str r3, [r7, #8]
  4951. SCB->AIRCR = reg_value;
  4952. 8001fe2: 4a04 ldr r2, [pc, #16] ; (8001ff4 <__NVIC_SetPriorityGrouping+0x44>)
  4953. 8001fe4: 68bb ldr r3, [r7, #8]
  4954. 8001fe6: 60d3 str r3, [r2, #12]
  4955. }
  4956. 8001fe8: bf00 nop
  4957. 8001fea: 3714 adds r7, #20
  4958. 8001fec: 46bd mov sp, r7
  4959. 8001fee: bc80 pop {r7}
  4960. 8001ff0: 4770 bx lr
  4961. 8001ff2: bf00 nop
  4962. 8001ff4: e000ed00 .word 0xe000ed00
  4963. 08001ff8 <__NVIC_GetPriorityGrouping>:
  4964. \brief Get Priority Grouping
  4965. \details Reads the priority grouping field from the NVIC Interrupt Controller.
  4966. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
  4967. */
  4968. __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
  4969. {
  4970. 8001ff8: b480 push {r7}
  4971. 8001ffa: af00 add r7, sp, #0
  4972. return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
  4973. 8001ffc: 4b04 ldr r3, [pc, #16] ; (8002010 <__NVIC_GetPriorityGrouping+0x18>)
  4974. 8001ffe: 68db ldr r3, [r3, #12]
  4975. 8002000: 0a1b lsrs r3, r3, #8
  4976. 8002002: f003 0307 and.w r3, r3, #7
  4977. }
  4978. 8002006: 4618 mov r0, r3
  4979. 8002008: 46bd mov sp, r7
  4980. 800200a: bc80 pop {r7}
  4981. 800200c: 4770 bx lr
  4982. 800200e: bf00 nop
  4983. 8002010: e000ed00 .word 0xe000ed00
  4984. 08002014 <__NVIC_SetPriority>:
  4985. \param [in] IRQn Interrupt number.
  4986. \param [in] priority Priority to set.
  4987. \note The priority cannot be set for every processor exception.
  4988. */
  4989. __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
  4990. {
  4991. 8002014: b480 push {r7}
  4992. 8002016: b083 sub sp, #12
  4993. 8002018: af00 add r7, sp, #0
  4994. 800201a: 4603 mov r3, r0
  4995. 800201c: 6039 str r1, [r7, #0]
  4996. 800201e: 71fb strb r3, [r7, #7]
  4997. if ((int32_t)(IRQn) >= 0)
  4998. 8002020: f997 3007 ldrsb.w r3, [r7, #7]
  4999. 8002024: 2b00 cmp r3, #0
  5000. 8002026: db0a blt.n 800203e <__NVIC_SetPriority+0x2a>
  5001. {
  5002. NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  5003. 8002028: 683b ldr r3, [r7, #0]
  5004. 800202a: b2da uxtb r2, r3
  5005. 800202c: 490c ldr r1, [pc, #48] ; (8002060 <__NVIC_SetPriority+0x4c>)
  5006. 800202e: f997 3007 ldrsb.w r3, [r7, #7]
  5007. 8002032: 0112 lsls r2, r2, #4
  5008. 8002034: b2d2 uxtb r2, r2
  5009. 8002036: 440b add r3, r1
  5010. 8002038: f883 2300 strb.w r2, [r3, #768] ; 0x300
  5011. }
  5012. else
  5013. {
  5014. SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  5015. }
  5016. }
  5017. 800203c: e00a b.n 8002054 <__NVIC_SetPriority+0x40>
  5018. SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  5019. 800203e: 683b ldr r3, [r7, #0]
  5020. 8002040: b2da uxtb r2, r3
  5021. 8002042: 4908 ldr r1, [pc, #32] ; (8002064 <__NVIC_SetPriority+0x50>)
  5022. 8002044: 79fb ldrb r3, [r7, #7]
  5023. 8002046: f003 030f and.w r3, r3, #15
  5024. 800204a: 3b04 subs r3, #4
  5025. 800204c: 0112 lsls r2, r2, #4
  5026. 800204e: b2d2 uxtb r2, r2
  5027. 8002050: 440b add r3, r1
  5028. 8002052: 761a strb r2, [r3, #24]
  5029. }
  5030. 8002054: bf00 nop
  5031. 8002056: 370c adds r7, #12
  5032. 8002058: 46bd mov sp, r7
  5033. 800205a: bc80 pop {r7}
  5034. 800205c: 4770 bx lr
  5035. 800205e: bf00 nop
  5036. 8002060: e000e100 .word 0xe000e100
  5037. 8002064: e000ed00 .word 0xe000ed00
  5038. 08002068 <NVIC_EncodePriority>:
  5039. \param [in] PreemptPriority Preemptive priority value (starting from 0).
  5040. \param [in] SubPriority Subpriority value (starting from 0).
  5041. \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
  5042. */
  5043. __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
  5044. {
  5045. 8002068: b480 push {r7}
  5046. 800206a: b089 sub sp, #36 ; 0x24
  5047. 800206c: af00 add r7, sp, #0
  5048. 800206e: 60f8 str r0, [r7, #12]
  5049. 8002070: 60b9 str r1, [r7, #8]
  5050. 8002072: 607a str r2, [r7, #4]
  5051. uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
  5052. 8002074: 68fb ldr r3, [r7, #12]
  5053. 8002076: f003 0307 and.w r3, r3, #7
  5054. 800207a: 61fb str r3, [r7, #28]
  5055. uint32_t PreemptPriorityBits;
  5056. uint32_t SubPriorityBits;
  5057. PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
  5058. 800207c: 69fb ldr r3, [r7, #28]
  5059. 800207e: f1c3 0307 rsb r3, r3, #7
  5060. 8002082: 2b04 cmp r3, #4
  5061. 8002084: bf28 it cs
  5062. 8002086: 2304 movcs r3, #4
  5063. 8002088: 61bb str r3, [r7, #24]
  5064. SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
  5065. 800208a: 69fb ldr r3, [r7, #28]
  5066. 800208c: 3304 adds r3, #4
  5067. 800208e: 2b06 cmp r3, #6
  5068. 8002090: d902 bls.n 8002098 <NVIC_EncodePriority+0x30>
  5069. 8002092: 69fb ldr r3, [r7, #28]
  5070. 8002094: 3b03 subs r3, #3
  5071. 8002096: e000 b.n 800209a <NVIC_EncodePriority+0x32>
  5072. 8002098: 2300 movs r3, #0
  5073. 800209a: 617b str r3, [r7, #20]
  5074. return (
  5075. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  5076. 800209c: f04f 32ff mov.w r2, #4294967295
  5077. 80020a0: 69bb ldr r3, [r7, #24]
  5078. 80020a2: fa02 f303 lsl.w r3, r2, r3
  5079. 80020a6: 43da mvns r2, r3
  5080. 80020a8: 68bb ldr r3, [r7, #8]
  5081. 80020aa: 401a ands r2, r3
  5082. 80020ac: 697b ldr r3, [r7, #20]
  5083. 80020ae: 409a lsls r2, r3
  5084. ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
  5085. 80020b0: f04f 31ff mov.w r1, #4294967295
  5086. 80020b4: 697b ldr r3, [r7, #20]
  5087. 80020b6: fa01 f303 lsl.w r3, r1, r3
  5088. 80020ba: 43d9 mvns r1, r3
  5089. 80020bc: 687b ldr r3, [r7, #4]
  5090. 80020be: 400b ands r3, r1
  5091. ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
  5092. 80020c0: 4313 orrs r3, r2
  5093. );
  5094. }
  5095. 80020c2: 4618 mov r0, r3
  5096. 80020c4: 3724 adds r7, #36 ; 0x24
  5097. 80020c6: 46bd mov sp, r7
  5098. 80020c8: bc80 pop {r7}
  5099. 80020ca: 4770 bx lr
  5100. 080020cc <SysTick_Config>:
  5101. \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
  5102. function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
  5103. must contain a vendor-specific implementation of this function.
  5104. */
  5105. __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
  5106. {
  5107. 80020cc: b580 push {r7, lr}
  5108. 80020ce: b082 sub sp, #8
  5109. 80020d0: af00 add r7, sp, #0
  5110. 80020d2: 6078 str r0, [r7, #4]
  5111. if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
  5112. 80020d4: 687b ldr r3, [r7, #4]
  5113. 80020d6: 3b01 subs r3, #1
  5114. 80020d8: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
  5115. 80020dc: d301 bcc.n 80020e2 <SysTick_Config+0x16>
  5116. {
  5117. return (1UL); /* Reload value impossible */
  5118. 80020de: 2301 movs r3, #1
  5119. 80020e0: e00f b.n 8002102 <SysTick_Config+0x36>
  5120. }
  5121. SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
  5122. 80020e2: 4a0a ldr r2, [pc, #40] ; (800210c <SysTick_Config+0x40>)
  5123. 80020e4: 687b ldr r3, [r7, #4]
  5124. 80020e6: 3b01 subs r3, #1
  5125. 80020e8: 6053 str r3, [r2, #4]
  5126. NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  5127. 80020ea: 210f movs r1, #15
  5128. 80020ec: f04f 30ff mov.w r0, #4294967295
  5129. 80020f0: f7ff ff90 bl 8002014 <__NVIC_SetPriority>
  5130. SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
  5131. 80020f4: 4b05 ldr r3, [pc, #20] ; (800210c <SysTick_Config+0x40>)
  5132. 80020f6: 2200 movs r2, #0
  5133. 80020f8: 609a str r2, [r3, #8]
  5134. SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
  5135. 80020fa: 4b04 ldr r3, [pc, #16] ; (800210c <SysTick_Config+0x40>)
  5136. 80020fc: 2207 movs r2, #7
  5137. 80020fe: 601a str r2, [r3, #0]
  5138. SysTick_CTRL_TICKINT_Msk |
  5139. SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
  5140. return (0UL); /* Function successful */
  5141. 8002100: 2300 movs r3, #0
  5142. }
  5143. 8002102: 4618 mov r0, r3
  5144. 8002104: 3708 adds r7, #8
  5145. 8002106: 46bd mov sp, r7
  5146. 8002108: bd80 pop {r7, pc}
  5147. 800210a: bf00 nop
  5148. 800210c: e000e010 .word 0xe000e010
  5149. 08002110 <HAL_NVIC_SetPriorityGrouping>:
  5150. * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
  5151. * The pending IRQ priority will be managed only by the subpriority.
  5152. * @retval None
  5153. */
  5154. void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
  5155. {
  5156. 8002110: b580 push {r7, lr}
  5157. 8002112: b082 sub sp, #8
  5158. 8002114: af00 add r7, sp, #0
  5159. 8002116: 6078 str r0, [r7, #4]
  5160. /* Check the parameters */
  5161. assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  5162. /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  5163. NVIC_SetPriorityGrouping(PriorityGroup);
  5164. 8002118: 6878 ldr r0, [r7, #4]
  5165. 800211a: f7ff ff49 bl 8001fb0 <__NVIC_SetPriorityGrouping>
  5166. }
  5167. 800211e: bf00 nop
  5168. 8002120: 3708 adds r7, #8
  5169. 8002122: 46bd mov sp, r7
  5170. 8002124: bd80 pop {r7, pc}
  5171. 08002126 <HAL_NVIC_SetPriority>:
  5172. * This parameter can be a value between 0 and 15
  5173. * A lower priority value indicates a higher priority.
  5174. * @retval None
  5175. */
  5176. void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
  5177. {
  5178. 8002126: b580 push {r7, lr}
  5179. 8002128: b086 sub sp, #24
  5180. 800212a: af00 add r7, sp, #0
  5181. 800212c: 4603 mov r3, r0
  5182. 800212e: 60b9 str r1, [r7, #8]
  5183. 8002130: 607a str r2, [r7, #4]
  5184. 8002132: 73fb strb r3, [r7, #15]
  5185. uint32_t prioritygroup = 0x00;
  5186. 8002134: 2300 movs r3, #0
  5187. 8002136: 617b str r3, [r7, #20]
  5188. /* Check the parameters */
  5189. assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  5190. assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  5191. prioritygroup = NVIC_GetPriorityGrouping();
  5192. 8002138: f7ff ff5e bl 8001ff8 <__NVIC_GetPriorityGrouping>
  5193. 800213c: 6178 str r0, [r7, #20]
  5194. NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
  5195. 800213e: 687a ldr r2, [r7, #4]
  5196. 8002140: 68b9 ldr r1, [r7, #8]
  5197. 8002142: 6978 ldr r0, [r7, #20]
  5198. 8002144: f7ff ff90 bl 8002068 <NVIC_EncodePriority>
  5199. 8002148: 4602 mov r2, r0
  5200. 800214a: f997 300f ldrsb.w r3, [r7, #15]
  5201. 800214e: 4611 mov r1, r2
  5202. 8002150: 4618 mov r0, r3
  5203. 8002152: f7ff ff5f bl 8002014 <__NVIC_SetPriority>
  5204. }
  5205. 8002156: bf00 nop
  5206. 8002158: 3718 adds r7, #24
  5207. 800215a: 46bd mov sp, r7
  5208. 800215c: bd80 pop {r7, pc}
  5209. 0800215e <HAL_SYSTICK_Config>:
  5210. * @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
  5211. * @retval status: - 0 Function succeeded.
  5212. * - 1 Function failed.
  5213. */
  5214. uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
  5215. {
  5216. 800215e: b580 push {r7, lr}
  5217. 8002160: b082 sub sp, #8
  5218. 8002162: af00 add r7, sp, #0
  5219. 8002164: 6078 str r0, [r7, #4]
  5220. return SysTick_Config(TicksNumb);
  5221. 8002166: 6878 ldr r0, [r7, #4]
  5222. 8002168: f7ff ffb0 bl 80020cc <SysTick_Config>
  5223. 800216c: 4603 mov r3, r0
  5224. }
  5225. 800216e: 4618 mov r0, r3
  5226. 8002170: 3708 adds r7, #8
  5227. 8002172: 46bd mov sp, r7
  5228. 8002174: bd80 pop {r7, pc}
  5229. 08002176 <HAL_SYSTICK_IRQHandler>:
  5230. /**
  5231. * @brief This function handles SYSTICK interrupt request.
  5232. * @retval None
  5233. */
  5234. void HAL_SYSTICK_IRQHandler(void)
  5235. {
  5236. 8002176: b580 push {r7, lr}
  5237. 8002178: af00 add r7, sp, #0
  5238. HAL_SYSTICK_Callback();
  5239. 800217a: f000 f802 bl 8002182 <HAL_SYSTICK_Callback>
  5240. }
  5241. 800217e: bf00 nop
  5242. 8002180: bd80 pop {r7, pc}
  5243. 08002182 <HAL_SYSTICK_Callback>:
  5244. /**
  5245. * @brief SYSTICK callback.
  5246. * @retval None
  5247. */
  5248. __weak void HAL_SYSTICK_Callback(void)
  5249. {
  5250. 8002182: b480 push {r7}
  5251. 8002184: af00 add r7, sp, #0
  5252. /* NOTE : This function Should not be modified, when the callback is needed,
  5253. the HAL_SYSTICK_Callback could be implemented in the user file
  5254. */
  5255. }
  5256. 8002186: bf00 nop
  5257. 8002188: 46bd mov sp, r7
  5258. 800218a: bc80 pop {r7}
  5259. 800218c: 4770 bx lr
  5260. ...
  5261. 08002190 <HAL_GPIO_Init>:
  5262. * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  5263. * the configuration information for the specified GPIO peripheral.
  5264. * @retval None
  5265. */
  5266. void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
  5267. {
  5268. 8002190: b480 push {r7}
  5269. 8002192: b087 sub sp, #28
  5270. 8002194: af00 add r7, sp, #0
  5271. 8002196: 6078 str r0, [r7, #4]
  5272. 8002198: 6039 str r1, [r7, #0]
  5273. uint32_t position = 0x00;
  5274. 800219a: 2300 movs r3, #0
  5275. 800219c: 617b str r3, [r7, #20]
  5276. uint32_t iocurrent = 0x00;
  5277. 800219e: 2300 movs r3, #0
  5278. 80021a0: 60fb str r3, [r7, #12]
  5279. uint32_t temp = 0x00;
  5280. 80021a2: 2300 movs r3, #0
  5281. 80021a4: 613b str r3, [r7, #16]
  5282. assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  5283. assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
  5284. assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
  5285. /* Configure the port pins */
  5286. while (((GPIO_Init->Pin) >> position) != 0)
  5287. 80021a6: e160 b.n 800246a <HAL_GPIO_Init+0x2da>
  5288. {
  5289. /* Get current io position */
  5290. iocurrent = (GPIO_Init->Pin) & (1U << position);
  5291. 80021a8: 683b ldr r3, [r7, #0]
  5292. 80021aa: 681a ldr r2, [r3, #0]
  5293. 80021ac: 2101 movs r1, #1
  5294. 80021ae: 697b ldr r3, [r7, #20]
  5295. 80021b0: fa01 f303 lsl.w r3, r1, r3
  5296. 80021b4: 4013 ands r3, r2
  5297. 80021b6: 60fb str r3, [r7, #12]
  5298. if (iocurrent)
  5299. 80021b8: 68fb ldr r3, [r7, #12]
  5300. 80021ba: 2b00 cmp r3, #0
  5301. 80021bc: f000 8152 beq.w 8002464 <HAL_GPIO_Init+0x2d4>
  5302. {
  5303. /*--------------------- GPIO Mode Configuration ------------------------*/
  5304. /* In case of Output or Alternate function mode selection */
  5305. if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
  5306. 80021c0: 683b ldr r3, [r7, #0]
  5307. 80021c2: 685b ldr r3, [r3, #4]
  5308. 80021c4: 2b01 cmp r3, #1
  5309. 80021c6: d00b beq.n 80021e0 <HAL_GPIO_Init+0x50>
  5310. 80021c8: 683b ldr r3, [r7, #0]
  5311. 80021ca: 685b ldr r3, [r3, #4]
  5312. 80021cc: 2b02 cmp r3, #2
  5313. 80021ce: d007 beq.n 80021e0 <HAL_GPIO_Init+0x50>
  5314. (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
  5315. 80021d0: 683b ldr r3, [r7, #0]
  5316. 80021d2: 685b ldr r3, [r3, #4]
  5317. if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
  5318. 80021d4: 2b11 cmp r3, #17
  5319. 80021d6: d003 beq.n 80021e0 <HAL_GPIO_Init+0x50>
  5320. (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
  5321. 80021d8: 683b ldr r3, [r7, #0]
  5322. 80021da: 685b ldr r3, [r3, #4]
  5323. 80021dc: 2b12 cmp r3, #18
  5324. 80021de: d130 bne.n 8002242 <HAL_GPIO_Init+0xb2>
  5325. {
  5326. /* Check the Speed parameter */
  5327. assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
  5328. /* Configure the IO Speed */
  5329. temp = GPIOx->OSPEEDR;
  5330. 80021e0: 687b ldr r3, [r7, #4]
  5331. 80021e2: 689b ldr r3, [r3, #8]
  5332. 80021e4: 613b str r3, [r7, #16]
  5333. CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
  5334. 80021e6: 697b ldr r3, [r7, #20]
  5335. 80021e8: 005b lsls r3, r3, #1
  5336. 80021ea: 2203 movs r2, #3
  5337. 80021ec: fa02 f303 lsl.w r3, r2, r3
  5338. 80021f0: 43db mvns r3, r3
  5339. 80021f2: 693a ldr r2, [r7, #16]
  5340. 80021f4: 4013 ands r3, r2
  5341. 80021f6: 613b str r3, [r7, #16]
  5342. SET_BIT(temp, GPIO_Init->Speed << (position * 2));
  5343. 80021f8: 683b ldr r3, [r7, #0]
  5344. 80021fa: 68da ldr r2, [r3, #12]
  5345. 80021fc: 697b ldr r3, [r7, #20]
  5346. 80021fe: 005b lsls r3, r3, #1
  5347. 8002200: fa02 f303 lsl.w r3, r2, r3
  5348. 8002204: 693a ldr r2, [r7, #16]
  5349. 8002206: 4313 orrs r3, r2
  5350. 8002208: 613b str r3, [r7, #16]
  5351. GPIOx->OSPEEDR = temp;
  5352. 800220a: 687b ldr r3, [r7, #4]
  5353. 800220c: 693a ldr r2, [r7, #16]
  5354. 800220e: 609a str r2, [r3, #8]
  5355. /* Configure the IO Output Type */
  5356. temp = GPIOx->OTYPER;
  5357. 8002210: 687b ldr r3, [r7, #4]
  5358. 8002212: 685b ldr r3, [r3, #4]
  5359. 8002214: 613b str r3, [r7, #16]
  5360. CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
  5361. 8002216: 2201 movs r2, #1
  5362. 8002218: 697b ldr r3, [r7, #20]
  5363. 800221a: fa02 f303 lsl.w r3, r2, r3
  5364. 800221e: 43db mvns r3, r3
  5365. 8002220: 693a ldr r2, [r7, #16]
  5366. 8002222: 4013 ands r3, r2
  5367. 8002224: 613b str r3, [r7, #16]
  5368. SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
  5369. 8002226: 683b ldr r3, [r7, #0]
  5370. 8002228: 685b ldr r3, [r3, #4]
  5371. 800222a: 091b lsrs r3, r3, #4
  5372. 800222c: f003 0201 and.w r2, r3, #1
  5373. 8002230: 697b ldr r3, [r7, #20]
  5374. 8002232: fa02 f303 lsl.w r3, r2, r3
  5375. 8002236: 693a ldr r2, [r7, #16]
  5376. 8002238: 4313 orrs r3, r2
  5377. 800223a: 613b str r3, [r7, #16]
  5378. GPIOx->OTYPER = temp;
  5379. 800223c: 687b ldr r3, [r7, #4]
  5380. 800223e: 693a ldr r2, [r7, #16]
  5381. 8002240: 605a str r2, [r3, #4]
  5382. }
  5383. /* Activate the Pull-up or Pull down resistor for the current IO */
  5384. temp = GPIOx->PUPDR;
  5385. 8002242: 687b ldr r3, [r7, #4]
  5386. 8002244: 68db ldr r3, [r3, #12]
  5387. 8002246: 613b str r3, [r7, #16]
  5388. CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
  5389. 8002248: 697b ldr r3, [r7, #20]
  5390. 800224a: 005b lsls r3, r3, #1
  5391. 800224c: 2203 movs r2, #3
  5392. 800224e: fa02 f303 lsl.w r3, r2, r3
  5393. 8002252: 43db mvns r3, r3
  5394. 8002254: 693a ldr r2, [r7, #16]
  5395. 8002256: 4013 ands r3, r2
  5396. 8002258: 613b str r3, [r7, #16]
  5397. SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
  5398. 800225a: 683b ldr r3, [r7, #0]
  5399. 800225c: 689a ldr r2, [r3, #8]
  5400. 800225e: 697b ldr r3, [r7, #20]
  5401. 8002260: 005b lsls r3, r3, #1
  5402. 8002262: fa02 f303 lsl.w r3, r2, r3
  5403. 8002266: 693a ldr r2, [r7, #16]
  5404. 8002268: 4313 orrs r3, r2
  5405. 800226a: 613b str r3, [r7, #16]
  5406. GPIOx->PUPDR = temp;
  5407. 800226c: 687b ldr r3, [r7, #4]
  5408. 800226e: 693a ldr r2, [r7, #16]
  5409. 8002270: 60da str r2, [r3, #12]
  5410. /* In case of Alternate function mode selection */
  5411. if ((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
  5412. 8002272: 683b ldr r3, [r7, #0]
  5413. 8002274: 685b ldr r3, [r3, #4]
  5414. 8002276: 2b02 cmp r3, #2
  5415. 8002278: d003 beq.n 8002282 <HAL_GPIO_Init+0xf2>
  5416. 800227a: 683b ldr r3, [r7, #0]
  5417. 800227c: 685b ldr r3, [r3, #4]
  5418. 800227e: 2b12 cmp r3, #18
  5419. 8002280: d123 bne.n 80022ca <HAL_GPIO_Init+0x13a>
  5420. assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
  5421. assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
  5422. /* Configure Alternate function mapped with the current IO */
  5423. /* Identify AFRL or AFRH register based on IO position*/
  5424. temp = GPIOx->AFR[position >> 3];
  5425. 8002282: 697b ldr r3, [r7, #20]
  5426. 8002284: 08da lsrs r2, r3, #3
  5427. 8002286: 687b ldr r3, [r7, #4]
  5428. 8002288: 3208 adds r2, #8
  5429. 800228a: f853 3022 ldr.w r3, [r3, r2, lsl #2]
  5430. 800228e: 613b str r3, [r7, #16]
  5431. CLEAR_BIT(temp, 0xFU << ((uint32_t)(position & 0x07U) * 4));
  5432. 8002290: 697b ldr r3, [r7, #20]
  5433. 8002292: f003 0307 and.w r3, r3, #7
  5434. 8002296: 009b lsls r3, r3, #2
  5435. 8002298: 220f movs r2, #15
  5436. 800229a: fa02 f303 lsl.w r3, r2, r3
  5437. 800229e: 43db mvns r3, r3
  5438. 80022a0: 693a ldr r2, [r7, #16]
  5439. 80022a2: 4013 ands r3, r2
  5440. 80022a4: 613b str r3, [r7, #16]
  5441. SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4));
  5442. 80022a6: 683b ldr r3, [r7, #0]
  5443. 80022a8: 691a ldr r2, [r3, #16]
  5444. 80022aa: 697b ldr r3, [r7, #20]
  5445. 80022ac: f003 0307 and.w r3, r3, #7
  5446. 80022b0: 009b lsls r3, r3, #2
  5447. 80022b2: fa02 f303 lsl.w r3, r2, r3
  5448. 80022b6: 693a ldr r2, [r7, #16]
  5449. 80022b8: 4313 orrs r3, r2
  5450. 80022ba: 613b str r3, [r7, #16]
  5451. GPIOx->AFR[position >> 3] = temp;
  5452. 80022bc: 697b ldr r3, [r7, #20]
  5453. 80022be: 08da lsrs r2, r3, #3
  5454. 80022c0: 687b ldr r3, [r7, #4]
  5455. 80022c2: 3208 adds r2, #8
  5456. 80022c4: 6939 ldr r1, [r7, #16]
  5457. 80022c6: f843 1022 str.w r1, [r3, r2, lsl #2]
  5458. }
  5459. /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
  5460. temp = GPIOx->MODER;
  5461. 80022ca: 687b ldr r3, [r7, #4]
  5462. 80022cc: 681b ldr r3, [r3, #0]
  5463. 80022ce: 613b str r3, [r7, #16]
  5464. CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));
  5465. 80022d0: 697b ldr r3, [r7, #20]
  5466. 80022d2: 005b lsls r3, r3, #1
  5467. 80022d4: 2203 movs r2, #3
  5468. 80022d6: fa02 f303 lsl.w r3, r2, r3
  5469. 80022da: 43db mvns r3, r3
  5470. 80022dc: 693a ldr r2, [r7, #16]
  5471. 80022de: 4013 ands r3, r2
  5472. 80022e0: 613b str r3, [r7, #16]
  5473. SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
  5474. 80022e2: 683b ldr r3, [r7, #0]
  5475. 80022e4: 685b ldr r3, [r3, #4]
  5476. 80022e6: f003 0203 and.w r2, r3, #3
  5477. 80022ea: 697b ldr r3, [r7, #20]
  5478. 80022ec: 005b lsls r3, r3, #1
  5479. 80022ee: fa02 f303 lsl.w r3, r2, r3
  5480. 80022f2: 693a ldr r2, [r7, #16]
  5481. 80022f4: 4313 orrs r3, r2
  5482. 80022f6: 613b str r3, [r7, #16]
  5483. GPIOx->MODER = temp;
  5484. 80022f8: 687b ldr r3, [r7, #4]
  5485. 80022fa: 693a ldr r2, [r7, #16]
  5486. 80022fc: 601a str r2, [r3, #0]
  5487. /*--------------------- EXTI Mode Configuration ------------------------*/
  5488. /* Configure the External Interrupt or event for the current IO */
  5489. if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
  5490. 80022fe: 683b ldr r3, [r7, #0]
  5491. 8002300: 685b ldr r3, [r3, #4]
  5492. 8002302: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  5493. 8002306: 2b00 cmp r3, #0
  5494. 8002308: f000 80ac beq.w 8002464 <HAL_GPIO_Init+0x2d4>
  5495. {
  5496. /* Enable SYSCFG Clock */
  5497. __HAL_RCC_SYSCFG_CLK_ENABLE();
  5498. 800230c: 4b5d ldr r3, [pc, #372] ; (8002484 <HAL_GPIO_Init+0x2f4>)
  5499. 800230e: 6a1b ldr r3, [r3, #32]
  5500. 8002310: 4a5c ldr r2, [pc, #368] ; (8002484 <HAL_GPIO_Init+0x2f4>)
  5501. 8002312: f043 0301 orr.w r3, r3, #1
  5502. 8002316: 6213 str r3, [r2, #32]
  5503. 8002318: 4b5a ldr r3, [pc, #360] ; (8002484 <HAL_GPIO_Init+0x2f4>)
  5504. 800231a: 6a1b ldr r3, [r3, #32]
  5505. 800231c: f003 0301 and.w r3, r3, #1
  5506. 8002320: 60bb str r3, [r7, #8]
  5507. 8002322: 68bb ldr r3, [r7, #8]
  5508. temp = SYSCFG->EXTICR[position >> 2];
  5509. 8002324: 4a58 ldr r2, [pc, #352] ; (8002488 <HAL_GPIO_Init+0x2f8>)
  5510. 8002326: 697b ldr r3, [r7, #20]
  5511. 8002328: 089b lsrs r3, r3, #2
  5512. 800232a: 3302 adds r3, #2
  5513. 800232c: f852 3023 ldr.w r3, [r2, r3, lsl #2]
  5514. 8002330: 613b str r3, [r7, #16]
  5515. CLEAR_BIT(temp, (0x0FU) << (4 * (position & 0x03)));
  5516. 8002332: 697b ldr r3, [r7, #20]
  5517. 8002334: f003 0303 and.w r3, r3, #3
  5518. 8002338: 009b lsls r3, r3, #2
  5519. 800233a: 220f movs r2, #15
  5520. 800233c: fa02 f303 lsl.w r3, r2, r3
  5521. 8002340: 43db mvns r3, r3
  5522. 8002342: 693a ldr r2, [r7, #16]
  5523. 8002344: 4013 ands r3, r2
  5524. 8002346: 613b str r3, [r7, #16]
  5525. SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
  5526. 8002348: 687b ldr r3, [r7, #4]
  5527. 800234a: 4a50 ldr r2, [pc, #320] ; (800248c <HAL_GPIO_Init+0x2fc>)
  5528. 800234c: 4293 cmp r3, r2
  5529. 800234e: d025 beq.n 800239c <HAL_GPIO_Init+0x20c>
  5530. 8002350: 687b ldr r3, [r7, #4]
  5531. 8002352: 4a4f ldr r2, [pc, #316] ; (8002490 <HAL_GPIO_Init+0x300>)
  5532. 8002354: 4293 cmp r3, r2
  5533. 8002356: d01f beq.n 8002398 <HAL_GPIO_Init+0x208>
  5534. 8002358: 687b ldr r3, [r7, #4]
  5535. 800235a: 4a4e ldr r2, [pc, #312] ; (8002494 <HAL_GPIO_Init+0x304>)
  5536. 800235c: 4293 cmp r3, r2
  5537. 800235e: d019 beq.n 8002394 <HAL_GPIO_Init+0x204>
  5538. 8002360: 687b ldr r3, [r7, #4]
  5539. 8002362: 4a4d ldr r2, [pc, #308] ; (8002498 <HAL_GPIO_Init+0x308>)
  5540. 8002364: 4293 cmp r3, r2
  5541. 8002366: d013 beq.n 8002390 <HAL_GPIO_Init+0x200>
  5542. 8002368: 687b ldr r3, [r7, #4]
  5543. 800236a: 4a4c ldr r2, [pc, #304] ; (800249c <HAL_GPIO_Init+0x30c>)
  5544. 800236c: 4293 cmp r3, r2
  5545. 800236e: d00d beq.n 800238c <HAL_GPIO_Init+0x1fc>
  5546. 8002370: 687b ldr r3, [r7, #4]
  5547. 8002372: 4a4b ldr r2, [pc, #300] ; (80024a0 <HAL_GPIO_Init+0x310>)
  5548. 8002374: 4293 cmp r3, r2
  5549. 8002376: d007 beq.n 8002388 <HAL_GPIO_Init+0x1f8>
  5550. 8002378: 687b ldr r3, [r7, #4]
  5551. 800237a: 4a4a ldr r2, [pc, #296] ; (80024a4 <HAL_GPIO_Init+0x314>)
  5552. 800237c: 4293 cmp r3, r2
  5553. 800237e: d101 bne.n 8002384 <HAL_GPIO_Init+0x1f4>
  5554. 8002380: 2306 movs r3, #6
  5555. 8002382: e00c b.n 800239e <HAL_GPIO_Init+0x20e>
  5556. 8002384: 2307 movs r3, #7
  5557. 8002386: e00a b.n 800239e <HAL_GPIO_Init+0x20e>
  5558. 8002388: 2305 movs r3, #5
  5559. 800238a: e008 b.n 800239e <HAL_GPIO_Init+0x20e>
  5560. 800238c: 2304 movs r3, #4
  5561. 800238e: e006 b.n 800239e <HAL_GPIO_Init+0x20e>
  5562. 8002390: 2303 movs r3, #3
  5563. 8002392: e004 b.n 800239e <HAL_GPIO_Init+0x20e>
  5564. 8002394: 2302 movs r3, #2
  5565. 8002396: e002 b.n 800239e <HAL_GPIO_Init+0x20e>
  5566. 8002398: 2301 movs r3, #1
  5567. 800239a: e000 b.n 800239e <HAL_GPIO_Init+0x20e>
  5568. 800239c: 2300 movs r3, #0
  5569. 800239e: 697a ldr r2, [r7, #20]
  5570. 80023a0: f002 0203 and.w r2, r2, #3
  5571. 80023a4: 0092 lsls r2, r2, #2
  5572. 80023a6: 4093 lsls r3, r2
  5573. 80023a8: 693a ldr r2, [r7, #16]
  5574. 80023aa: 4313 orrs r3, r2
  5575. 80023ac: 613b str r3, [r7, #16]
  5576. SYSCFG->EXTICR[position >> 2] = temp;
  5577. 80023ae: 4936 ldr r1, [pc, #216] ; (8002488 <HAL_GPIO_Init+0x2f8>)
  5578. 80023b0: 697b ldr r3, [r7, #20]
  5579. 80023b2: 089b lsrs r3, r3, #2
  5580. 80023b4: 3302 adds r3, #2
  5581. 80023b6: 693a ldr r2, [r7, #16]
  5582. 80023b8: f841 2023 str.w r2, [r1, r3, lsl #2]
  5583. /* Clear EXTI line configuration */
  5584. temp = EXTI->IMR;
  5585. 80023bc: 4b3a ldr r3, [pc, #232] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5586. 80023be: 681b ldr r3, [r3, #0]
  5587. 80023c0: 613b str r3, [r7, #16]
  5588. CLEAR_BIT(temp, (uint32_t)iocurrent);
  5589. 80023c2: 68fb ldr r3, [r7, #12]
  5590. 80023c4: 43db mvns r3, r3
  5591. 80023c6: 693a ldr r2, [r7, #16]
  5592. 80023c8: 4013 ands r3, r2
  5593. 80023ca: 613b str r3, [r7, #16]
  5594. if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
  5595. 80023cc: 683b ldr r3, [r7, #0]
  5596. 80023ce: 685b ldr r3, [r3, #4]
  5597. 80023d0: f403 3380 and.w r3, r3, #65536 ; 0x10000
  5598. 80023d4: 2b00 cmp r3, #0
  5599. 80023d6: d003 beq.n 80023e0 <HAL_GPIO_Init+0x250>
  5600. {
  5601. SET_BIT(temp, iocurrent);
  5602. 80023d8: 693a ldr r2, [r7, #16]
  5603. 80023da: 68fb ldr r3, [r7, #12]
  5604. 80023dc: 4313 orrs r3, r2
  5605. 80023de: 613b str r3, [r7, #16]
  5606. }
  5607. EXTI->IMR = temp;
  5608. 80023e0: 4a31 ldr r2, [pc, #196] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5609. 80023e2: 693b ldr r3, [r7, #16]
  5610. 80023e4: 6013 str r3, [r2, #0]
  5611. temp = EXTI->EMR;
  5612. 80023e6: 4b30 ldr r3, [pc, #192] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5613. 80023e8: 685b ldr r3, [r3, #4]
  5614. 80023ea: 613b str r3, [r7, #16]
  5615. CLEAR_BIT(temp, (uint32_t)iocurrent);
  5616. 80023ec: 68fb ldr r3, [r7, #12]
  5617. 80023ee: 43db mvns r3, r3
  5618. 80023f0: 693a ldr r2, [r7, #16]
  5619. 80023f2: 4013 ands r3, r2
  5620. 80023f4: 613b str r3, [r7, #16]
  5621. if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
  5622. 80023f6: 683b ldr r3, [r7, #0]
  5623. 80023f8: 685b ldr r3, [r3, #4]
  5624. 80023fa: f403 3300 and.w r3, r3, #131072 ; 0x20000
  5625. 80023fe: 2b00 cmp r3, #0
  5626. 8002400: d003 beq.n 800240a <HAL_GPIO_Init+0x27a>
  5627. {
  5628. SET_BIT(temp, iocurrent);
  5629. 8002402: 693a ldr r2, [r7, #16]
  5630. 8002404: 68fb ldr r3, [r7, #12]
  5631. 8002406: 4313 orrs r3, r2
  5632. 8002408: 613b str r3, [r7, #16]
  5633. }
  5634. EXTI->EMR = temp;
  5635. 800240a: 4a27 ldr r2, [pc, #156] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5636. 800240c: 693b ldr r3, [r7, #16]
  5637. 800240e: 6053 str r3, [r2, #4]
  5638. /* Clear Rising Falling edge configuration */
  5639. temp = EXTI->RTSR;
  5640. 8002410: 4b25 ldr r3, [pc, #148] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5641. 8002412: 689b ldr r3, [r3, #8]
  5642. 8002414: 613b str r3, [r7, #16]
  5643. CLEAR_BIT(temp, (uint32_t)iocurrent);
  5644. 8002416: 68fb ldr r3, [r7, #12]
  5645. 8002418: 43db mvns r3, r3
  5646. 800241a: 693a ldr r2, [r7, #16]
  5647. 800241c: 4013 ands r3, r2
  5648. 800241e: 613b str r3, [r7, #16]
  5649. if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
  5650. 8002420: 683b ldr r3, [r7, #0]
  5651. 8002422: 685b ldr r3, [r3, #4]
  5652. 8002424: f403 1380 and.w r3, r3, #1048576 ; 0x100000
  5653. 8002428: 2b00 cmp r3, #0
  5654. 800242a: d003 beq.n 8002434 <HAL_GPIO_Init+0x2a4>
  5655. {
  5656. SET_BIT(temp, iocurrent);
  5657. 800242c: 693a ldr r2, [r7, #16]
  5658. 800242e: 68fb ldr r3, [r7, #12]
  5659. 8002430: 4313 orrs r3, r2
  5660. 8002432: 613b str r3, [r7, #16]
  5661. }
  5662. EXTI->RTSR = temp;
  5663. 8002434: 4a1c ldr r2, [pc, #112] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5664. 8002436: 693b ldr r3, [r7, #16]
  5665. 8002438: 6093 str r3, [r2, #8]
  5666. temp = EXTI->FTSR;
  5667. 800243a: 4b1b ldr r3, [pc, #108] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5668. 800243c: 68db ldr r3, [r3, #12]
  5669. 800243e: 613b str r3, [r7, #16]
  5670. CLEAR_BIT(temp, (uint32_t)iocurrent);
  5671. 8002440: 68fb ldr r3, [r7, #12]
  5672. 8002442: 43db mvns r3, r3
  5673. 8002444: 693a ldr r2, [r7, #16]
  5674. 8002446: 4013 ands r3, r2
  5675. 8002448: 613b str r3, [r7, #16]
  5676. if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
  5677. 800244a: 683b ldr r3, [r7, #0]
  5678. 800244c: 685b ldr r3, [r3, #4]
  5679. 800244e: f403 1300 and.w r3, r3, #2097152 ; 0x200000
  5680. 8002452: 2b00 cmp r3, #0
  5681. 8002454: d003 beq.n 800245e <HAL_GPIO_Init+0x2ce>
  5682. {
  5683. SET_BIT(temp, iocurrent);
  5684. 8002456: 693a ldr r2, [r7, #16]
  5685. 8002458: 68fb ldr r3, [r7, #12]
  5686. 800245a: 4313 orrs r3, r2
  5687. 800245c: 613b str r3, [r7, #16]
  5688. }
  5689. EXTI->FTSR = temp;
  5690. 800245e: 4a12 ldr r2, [pc, #72] ; (80024a8 <HAL_GPIO_Init+0x318>)
  5691. 8002460: 693b ldr r3, [r7, #16]
  5692. 8002462: 60d3 str r3, [r2, #12]
  5693. }
  5694. }
  5695. position++;
  5696. 8002464: 697b ldr r3, [r7, #20]
  5697. 8002466: 3301 adds r3, #1
  5698. 8002468: 617b str r3, [r7, #20]
  5699. while (((GPIO_Init->Pin) >> position) != 0)
  5700. 800246a: 683b ldr r3, [r7, #0]
  5701. 800246c: 681a ldr r2, [r3, #0]
  5702. 800246e: 697b ldr r3, [r7, #20]
  5703. 8002470: fa22 f303 lsr.w r3, r2, r3
  5704. 8002474: 2b00 cmp r3, #0
  5705. 8002476: f47f ae97 bne.w 80021a8 <HAL_GPIO_Init+0x18>
  5706. }
  5707. }
  5708. 800247a: bf00 nop
  5709. 800247c: 371c adds r7, #28
  5710. 800247e: 46bd mov sp, r7
  5711. 8002480: bc80 pop {r7}
  5712. 8002482: 4770 bx lr
  5713. 8002484: 40023800 .word 0x40023800
  5714. 8002488: 40010000 .word 0x40010000
  5715. 800248c: 40020000 .word 0x40020000
  5716. 8002490: 40020400 .word 0x40020400
  5717. 8002494: 40020800 .word 0x40020800
  5718. 8002498: 40020c00 .word 0x40020c00
  5719. 800249c: 40021000 .word 0x40021000
  5720. 80024a0: 40021400 .word 0x40021400
  5721. 80024a4: 40021800 .word 0x40021800
  5722. 80024a8: 40010400 .word 0x40010400
  5723. 080024ac <HAL_GPIO_WritePin>:
  5724. * @arg GPIO_PIN_RESET: to clear the port pin
  5725. * @arg GPIO_PIN_SET: to set the port pin
  5726. * @retval None
  5727. */
  5728. void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
  5729. {
  5730. 80024ac: b480 push {r7}
  5731. 80024ae: b083 sub sp, #12
  5732. 80024b0: af00 add r7, sp, #0
  5733. 80024b2: 6078 str r0, [r7, #4]
  5734. 80024b4: 460b mov r3, r1
  5735. 80024b6: 807b strh r3, [r7, #2]
  5736. 80024b8: 4613 mov r3, r2
  5737. 80024ba: 707b strb r3, [r7, #1]
  5738. /* Check the parameters */
  5739. assert_param(IS_GPIO_PIN(GPIO_Pin));
  5740. assert_param(IS_GPIO_PIN_ACTION(PinState));
  5741. if (PinState != GPIO_PIN_RESET)
  5742. 80024bc: 787b ldrb r3, [r7, #1]
  5743. 80024be: 2b00 cmp r3, #0
  5744. 80024c0: d003 beq.n 80024ca <HAL_GPIO_WritePin+0x1e>
  5745. {
  5746. GPIOx->BSRR = (uint32_t)GPIO_Pin;
  5747. 80024c2: 887a ldrh r2, [r7, #2]
  5748. 80024c4: 687b ldr r3, [r7, #4]
  5749. 80024c6: 619a str r2, [r3, #24]
  5750. }
  5751. else
  5752. {
  5753. GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
  5754. }
  5755. }
  5756. 80024c8: e003 b.n 80024d2 <HAL_GPIO_WritePin+0x26>
  5757. GPIOx->BSRR = (uint32_t)GPIO_Pin << 16 ;
  5758. 80024ca: 887b ldrh r3, [r7, #2]
  5759. 80024cc: 041a lsls r2, r3, #16
  5760. 80024ce: 687b ldr r3, [r7, #4]
  5761. 80024d0: 619a str r2, [r3, #24]
  5762. }
  5763. 80024d2: bf00 nop
  5764. 80024d4: 370c adds r7, #12
  5765. 80024d6: 46bd mov sp, r7
  5766. 80024d8: bc80 pop {r7}
  5767. 80024da: 4770 bx lr
  5768. 080024dc <HAL_RCC_OscConfig>:
  5769. * supported by this macro. User should request a transition to HSE Off
  5770. * first and then HSE On or HSE Bypass.
  5771. * @retval HAL status
  5772. */
  5773. HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
  5774. {
  5775. 80024dc: b580 push {r7, lr}
  5776. 80024de: b088 sub sp, #32
  5777. 80024e0: af00 add r7, sp, #0
  5778. 80024e2: 6078 str r0, [r7, #4]
  5779. uint32_t tickstart;
  5780. HAL_StatusTypeDef status;
  5781. uint32_t sysclk_source, pll_config;
  5782. /* Check the parameters */
  5783. if(RCC_OscInitStruct == NULL)
  5784. 80024e4: 687b ldr r3, [r7, #4]
  5785. 80024e6: 2b00 cmp r3, #0
  5786. 80024e8: d101 bne.n 80024ee <HAL_RCC_OscConfig+0x12>
  5787. {
  5788. return HAL_ERROR;
  5789. 80024ea: 2301 movs r3, #1
  5790. 80024ec: e31d b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  5791. }
  5792. assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  5793. sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
  5794. 80024ee: 4b94 ldr r3, [pc, #592] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5795. 80024f0: 689b ldr r3, [r3, #8]
  5796. 80024f2: f003 030c and.w r3, r3, #12
  5797. 80024f6: 61bb str r3, [r7, #24]
  5798. pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
  5799. 80024f8: 4b91 ldr r3, [pc, #580] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5800. 80024fa: 689b ldr r3, [r3, #8]
  5801. 80024fc: f403 3380 and.w r3, r3, #65536 ; 0x10000
  5802. 8002500: 617b str r3, [r7, #20]
  5803. /*------------------------------- HSE Configuration ------------------------*/
  5804. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
  5805. 8002502: 687b ldr r3, [r7, #4]
  5806. 8002504: 681b ldr r3, [r3, #0]
  5807. 8002506: f003 0301 and.w r3, r3, #1
  5808. 800250a: 2b00 cmp r3, #0
  5809. 800250c: d07b beq.n 8002606 <HAL_RCC_OscConfig+0x12a>
  5810. {
  5811. /* Check the parameters */
  5812. assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
  5813. /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
  5814. if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE)
  5815. 800250e: 69bb ldr r3, [r7, #24]
  5816. 8002510: 2b08 cmp r3, #8
  5817. 8002512: d006 beq.n 8002522 <HAL_RCC_OscConfig+0x46>
  5818. || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE)))
  5819. 8002514: 69bb ldr r3, [r7, #24]
  5820. 8002516: 2b0c cmp r3, #12
  5821. 8002518: d10f bne.n 800253a <HAL_RCC_OscConfig+0x5e>
  5822. 800251a: 697b ldr r3, [r7, #20]
  5823. 800251c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
  5824. 8002520: d10b bne.n 800253a <HAL_RCC_OscConfig+0x5e>
  5825. {
  5826. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  5827. 8002522: 4b87 ldr r3, [pc, #540] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5828. 8002524: 681b ldr r3, [r3, #0]
  5829. 8002526: f403 3300 and.w r3, r3, #131072 ; 0x20000
  5830. 800252a: 2b00 cmp r3, #0
  5831. 800252c: d06a beq.n 8002604 <HAL_RCC_OscConfig+0x128>
  5832. 800252e: 687b ldr r3, [r7, #4]
  5833. 8002530: 685b ldr r3, [r3, #4]
  5834. 8002532: 2b00 cmp r3, #0
  5835. 8002534: d166 bne.n 8002604 <HAL_RCC_OscConfig+0x128>
  5836. {
  5837. return HAL_ERROR;
  5838. 8002536: 2301 movs r3, #1
  5839. 8002538: e2f7 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  5840. }
  5841. }
  5842. else
  5843. {
  5844. /* Set the new HSE configuration ---------------------------------------*/
  5845. __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
  5846. 800253a: 687b ldr r3, [r7, #4]
  5847. 800253c: 685b ldr r3, [r3, #4]
  5848. 800253e: 2b01 cmp r3, #1
  5849. 8002540: d106 bne.n 8002550 <HAL_RCC_OscConfig+0x74>
  5850. 8002542: 4b7f ldr r3, [pc, #508] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5851. 8002544: 681b ldr r3, [r3, #0]
  5852. 8002546: 4a7e ldr r2, [pc, #504] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5853. 8002548: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  5854. 800254c: 6013 str r3, [r2, #0]
  5855. 800254e: e02d b.n 80025ac <HAL_RCC_OscConfig+0xd0>
  5856. 8002550: 687b ldr r3, [r7, #4]
  5857. 8002552: 685b ldr r3, [r3, #4]
  5858. 8002554: 2b00 cmp r3, #0
  5859. 8002556: d10c bne.n 8002572 <HAL_RCC_OscConfig+0x96>
  5860. 8002558: 4b79 ldr r3, [pc, #484] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5861. 800255a: 681b ldr r3, [r3, #0]
  5862. 800255c: 4a78 ldr r2, [pc, #480] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5863. 800255e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  5864. 8002562: 6013 str r3, [r2, #0]
  5865. 8002564: 4b76 ldr r3, [pc, #472] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5866. 8002566: 681b ldr r3, [r3, #0]
  5867. 8002568: 4a75 ldr r2, [pc, #468] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5868. 800256a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  5869. 800256e: 6013 str r3, [r2, #0]
  5870. 8002570: e01c b.n 80025ac <HAL_RCC_OscConfig+0xd0>
  5871. 8002572: 687b ldr r3, [r7, #4]
  5872. 8002574: 685b ldr r3, [r3, #4]
  5873. 8002576: 2b05 cmp r3, #5
  5874. 8002578: d10c bne.n 8002594 <HAL_RCC_OscConfig+0xb8>
  5875. 800257a: 4b71 ldr r3, [pc, #452] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5876. 800257c: 681b ldr r3, [r3, #0]
  5877. 800257e: 4a70 ldr r2, [pc, #448] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5878. 8002580: f443 2380 orr.w r3, r3, #262144 ; 0x40000
  5879. 8002584: 6013 str r3, [r2, #0]
  5880. 8002586: 4b6e ldr r3, [pc, #440] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5881. 8002588: 681b ldr r3, [r3, #0]
  5882. 800258a: 4a6d ldr r2, [pc, #436] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5883. 800258c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
  5884. 8002590: 6013 str r3, [r2, #0]
  5885. 8002592: e00b b.n 80025ac <HAL_RCC_OscConfig+0xd0>
  5886. 8002594: 4b6a ldr r3, [pc, #424] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5887. 8002596: 681b ldr r3, [r3, #0]
  5888. 8002598: 4a69 ldr r2, [pc, #420] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5889. 800259a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
  5890. 800259e: 6013 str r3, [r2, #0]
  5891. 80025a0: 4b67 ldr r3, [pc, #412] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5892. 80025a2: 681b ldr r3, [r3, #0]
  5893. 80025a4: 4a66 ldr r2, [pc, #408] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5894. 80025a6: f423 2380 bic.w r3, r3, #262144 ; 0x40000
  5895. 80025aa: 6013 str r3, [r2, #0]
  5896. /* Check the HSE State */
  5897. if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
  5898. 80025ac: 687b ldr r3, [r7, #4]
  5899. 80025ae: 685b ldr r3, [r3, #4]
  5900. 80025b0: 2b00 cmp r3, #0
  5901. 80025b2: d013 beq.n 80025dc <HAL_RCC_OscConfig+0x100>
  5902. {
  5903. /* Get Start Tick */
  5904. tickstart = HAL_GetTick();
  5905. 80025b4: f7ff f8d2 bl 800175c <HAL_GetTick>
  5906. 80025b8: 6138 str r0, [r7, #16]
  5907. /* Wait till HSE is ready */
  5908. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  5909. 80025ba: e008 b.n 80025ce <HAL_RCC_OscConfig+0xf2>
  5910. {
  5911. if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  5912. 80025bc: f7ff f8ce bl 800175c <HAL_GetTick>
  5913. 80025c0: 4602 mov r2, r0
  5914. 80025c2: 693b ldr r3, [r7, #16]
  5915. 80025c4: 1ad3 subs r3, r2, r3
  5916. 80025c6: 2b64 cmp r3, #100 ; 0x64
  5917. 80025c8: d901 bls.n 80025ce <HAL_RCC_OscConfig+0xf2>
  5918. {
  5919. return HAL_TIMEOUT;
  5920. 80025ca: 2303 movs r3, #3
  5921. 80025cc: e2ad b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  5922. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  5923. 80025ce: 4b5c ldr r3, [pc, #368] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5924. 80025d0: 681b ldr r3, [r3, #0]
  5925. 80025d2: f403 3300 and.w r3, r3, #131072 ; 0x20000
  5926. 80025d6: 2b00 cmp r3, #0
  5927. 80025d8: d0f0 beq.n 80025bc <HAL_RCC_OscConfig+0xe0>
  5928. 80025da: e014 b.n 8002606 <HAL_RCC_OscConfig+0x12a>
  5929. }
  5930. }
  5931. else
  5932. {
  5933. /* Get Start Tick */
  5934. tickstart = HAL_GetTick();
  5935. 80025dc: f7ff f8be bl 800175c <HAL_GetTick>
  5936. 80025e0: 6138 str r0, [r7, #16]
  5937. /* Wait till HSE is disabled */
  5938. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
  5939. 80025e2: e008 b.n 80025f6 <HAL_RCC_OscConfig+0x11a>
  5940. {
  5941. if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
  5942. 80025e4: f7ff f8ba bl 800175c <HAL_GetTick>
  5943. 80025e8: 4602 mov r2, r0
  5944. 80025ea: 693b ldr r3, [r7, #16]
  5945. 80025ec: 1ad3 subs r3, r2, r3
  5946. 80025ee: 2b64 cmp r3, #100 ; 0x64
  5947. 80025f0: d901 bls.n 80025f6 <HAL_RCC_OscConfig+0x11a>
  5948. {
  5949. return HAL_TIMEOUT;
  5950. 80025f2: 2303 movs r3, #3
  5951. 80025f4: e299 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  5952. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U)
  5953. 80025f6: 4b52 ldr r3, [pc, #328] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5954. 80025f8: 681b ldr r3, [r3, #0]
  5955. 80025fa: f403 3300 and.w r3, r3, #131072 ; 0x20000
  5956. 80025fe: 2b00 cmp r3, #0
  5957. 8002600: d1f0 bne.n 80025e4 <HAL_RCC_OscConfig+0x108>
  5958. 8002602: e000 b.n 8002606 <HAL_RCC_OscConfig+0x12a>
  5959. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
  5960. 8002604: bf00 nop
  5961. }
  5962. }
  5963. }
  5964. }
  5965. /*----------------------------- HSI Configuration --------------------------*/
  5966. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
  5967. 8002606: 687b ldr r3, [r7, #4]
  5968. 8002608: 681b ldr r3, [r3, #0]
  5969. 800260a: f003 0302 and.w r3, r3, #2
  5970. 800260e: 2b00 cmp r3, #0
  5971. 8002610: d05a beq.n 80026c8 <HAL_RCC_OscConfig+0x1ec>
  5972. /* Check the parameters */
  5973. assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
  5974. assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
  5975. /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
  5976. if((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI)
  5977. 8002612: 69bb ldr r3, [r7, #24]
  5978. 8002614: 2b04 cmp r3, #4
  5979. 8002616: d005 beq.n 8002624 <HAL_RCC_OscConfig+0x148>
  5980. || ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI)))
  5981. 8002618: 69bb ldr r3, [r7, #24]
  5982. 800261a: 2b0c cmp r3, #12
  5983. 800261c: d119 bne.n 8002652 <HAL_RCC_OscConfig+0x176>
  5984. 800261e: 697b ldr r3, [r7, #20]
  5985. 8002620: 2b00 cmp r3, #0
  5986. 8002622: d116 bne.n 8002652 <HAL_RCC_OscConfig+0x176>
  5987. {
  5988. /* When HSI is used as system clock it will not disabled */
  5989. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
  5990. 8002624: 4b46 ldr r3, [pc, #280] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  5991. 8002626: 681b ldr r3, [r3, #0]
  5992. 8002628: f003 0302 and.w r3, r3, #2
  5993. 800262c: 2b00 cmp r3, #0
  5994. 800262e: d005 beq.n 800263c <HAL_RCC_OscConfig+0x160>
  5995. 8002630: 687b ldr r3, [r7, #4]
  5996. 8002632: 68db ldr r3, [r3, #12]
  5997. 8002634: 2b01 cmp r3, #1
  5998. 8002636: d001 beq.n 800263c <HAL_RCC_OscConfig+0x160>
  5999. {
  6000. return HAL_ERROR;
  6001. 8002638: 2301 movs r3, #1
  6002. 800263a: e276 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6003. }
  6004. /* Otherwise, just the calibration is allowed */
  6005. else
  6006. {
  6007. /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  6008. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  6009. 800263c: 4b40 ldr r3, [pc, #256] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6010. 800263e: 685b ldr r3, [r3, #4]
  6011. 8002640: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
  6012. 8002644: 687b ldr r3, [r7, #4]
  6013. 8002646: 691b ldr r3, [r3, #16]
  6014. 8002648: 021b lsls r3, r3, #8
  6015. 800264a: 493d ldr r1, [pc, #244] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6016. 800264c: 4313 orrs r3, r2
  6017. 800264e: 604b str r3, [r1, #4]
  6018. if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
  6019. 8002650: e03a b.n 80026c8 <HAL_RCC_OscConfig+0x1ec>
  6020. }
  6021. }
  6022. else
  6023. {
  6024. /* Check the HSI State */
  6025. if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
  6026. 8002652: 687b ldr r3, [r7, #4]
  6027. 8002654: 68db ldr r3, [r3, #12]
  6028. 8002656: 2b00 cmp r3, #0
  6029. 8002658: d020 beq.n 800269c <HAL_RCC_OscConfig+0x1c0>
  6030. {
  6031. /* Enable the Internal High Speed oscillator (HSI). */
  6032. __HAL_RCC_HSI_ENABLE();
  6033. 800265a: 4b3a ldr r3, [pc, #232] ; (8002744 <HAL_RCC_OscConfig+0x268>)
  6034. 800265c: 2201 movs r2, #1
  6035. 800265e: 601a str r2, [r3, #0]
  6036. /* Get Start Tick */
  6037. tickstart = HAL_GetTick();
  6038. 8002660: f7ff f87c bl 800175c <HAL_GetTick>
  6039. 8002664: 6138 str r0, [r7, #16]
  6040. /* Wait till HSI is ready */
  6041. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  6042. 8002666: e008 b.n 800267a <HAL_RCC_OscConfig+0x19e>
  6043. {
  6044. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  6045. 8002668: f7ff f878 bl 800175c <HAL_GetTick>
  6046. 800266c: 4602 mov r2, r0
  6047. 800266e: 693b ldr r3, [r7, #16]
  6048. 8002670: 1ad3 subs r3, r2, r3
  6049. 8002672: 2b02 cmp r3, #2
  6050. 8002674: d901 bls.n 800267a <HAL_RCC_OscConfig+0x19e>
  6051. {
  6052. return HAL_TIMEOUT;
  6053. 8002676: 2303 movs r3, #3
  6054. 8002678: e257 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6055. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  6056. 800267a: 4b31 ldr r3, [pc, #196] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6057. 800267c: 681b ldr r3, [r3, #0]
  6058. 800267e: f003 0302 and.w r3, r3, #2
  6059. 8002682: 2b00 cmp r3, #0
  6060. 8002684: d0f0 beq.n 8002668 <HAL_RCC_OscConfig+0x18c>
  6061. }
  6062. }
  6063. /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
  6064. __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
  6065. 8002686: 4b2e ldr r3, [pc, #184] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6066. 8002688: 685b ldr r3, [r3, #4]
  6067. 800268a: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00
  6068. 800268e: 687b ldr r3, [r7, #4]
  6069. 8002690: 691b ldr r3, [r3, #16]
  6070. 8002692: 021b lsls r3, r3, #8
  6071. 8002694: 492a ldr r1, [pc, #168] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6072. 8002696: 4313 orrs r3, r2
  6073. 8002698: 604b str r3, [r1, #4]
  6074. 800269a: e015 b.n 80026c8 <HAL_RCC_OscConfig+0x1ec>
  6075. }
  6076. else
  6077. {
  6078. /* Disable the Internal High Speed oscillator (HSI). */
  6079. __HAL_RCC_HSI_DISABLE();
  6080. 800269c: 4b29 ldr r3, [pc, #164] ; (8002744 <HAL_RCC_OscConfig+0x268>)
  6081. 800269e: 2200 movs r2, #0
  6082. 80026a0: 601a str r2, [r3, #0]
  6083. /* Get Start Tick */
  6084. tickstart = HAL_GetTick();
  6085. 80026a2: f7ff f85b bl 800175c <HAL_GetTick>
  6086. 80026a6: 6138 str r0, [r7, #16]
  6087. /* Wait till HSI is disabled */
  6088. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
  6089. 80026a8: e008 b.n 80026bc <HAL_RCC_OscConfig+0x1e0>
  6090. {
  6091. if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
  6092. 80026aa: f7ff f857 bl 800175c <HAL_GetTick>
  6093. 80026ae: 4602 mov r2, r0
  6094. 80026b0: 693b ldr r3, [r7, #16]
  6095. 80026b2: 1ad3 subs r3, r2, r3
  6096. 80026b4: 2b02 cmp r3, #2
  6097. 80026b6: d901 bls.n 80026bc <HAL_RCC_OscConfig+0x1e0>
  6098. {
  6099. return HAL_TIMEOUT;
  6100. 80026b8: 2303 movs r3, #3
  6101. 80026ba: e236 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6102. while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != 0U)
  6103. 80026bc: 4b20 ldr r3, [pc, #128] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6104. 80026be: 681b ldr r3, [r3, #0]
  6105. 80026c0: f003 0302 and.w r3, r3, #2
  6106. 80026c4: 2b00 cmp r3, #0
  6107. 80026c6: d1f0 bne.n 80026aa <HAL_RCC_OscConfig+0x1ce>
  6108. }
  6109. }
  6110. }
  6111. }
  6112. /*----------------------------- MSI Configuration --------------------------*/
  6113. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
  6114. 80026c8: 687b ldr r3, [r7, #4]
  6115. 80026ca: 681b ldr r3, [r3, #0]
  6116. 80026cc: f003 0310 and.w r3, r3, #16
  6117. 80026d0: 2b00 cmp r3, #0
  6118. 80026d2: f000 80b8 beq.w 8002846 <HAL_RCC_OscConfig+0x36a>
  6119. {
  6120. /* When the MSI is used as system clock it will not be disabled */
  6121. if(sysclk_source == RCC_CFGR_SWS_MSI)
  6122. 80026d6: 69bb ldr r3, [r7, #24]
  6123. 80026d8: 2b00 cmp r3, #0
  6124. 80026da: d170 bne.n 80027be <HAL_RCC_OscConfig+0x2e2>
  6125. {
  6126. if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
  6127. 80026dc: 4b18 ldr r3, [pc, #96] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6128. 80026de: 681b ldr r3, [r3, #0]
  6129. 80026e0: f403 7300 and.w r3, r3, #512 ; 0x200
  6130. 80026e4: 2b00 cmp r3, #0
  6131. 80026e6: d005 beq.n 80026f4 <HAL_RCC_OscConfig+0x218>
  6132. 80026e8: 687b ldr r3, [r7, #4]
  6133. 80026ea: 699b ldr r3, [r3, #24]
  6134. 80026ec: 2b00 cmp r3, #0
  6135. 80026ee: d101 bne.n 80026f4 <HAL_RCC_OscConfig+0x218>
  6136. {
  6137. return HAL_ERROR;
  6138. 80026f0: 2301 movs r3, #1
  6139. 80026f2: e21a b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6140. assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
  6141. /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  6142. must be correctly programmed according to the frequency of the CPU clock
  6143. (HCLK) and the supply voltage of the device. */
  6144. if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
  6145. 80026f4: 687b ldr r3, [r7, #4]
  6146. 80026f6: 6a1a ldr r2, [r3, #32]
  6147. 80026f8: 4b11 ldr r3, [pc, #68] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6148. 80026fa: 685b ldr r3, [r3, #4]
  6149. 80026fc: f403 4360 and.w r3, r3, #57344 ; 0xe000
  6150. 8002700: 429a cmp r2, r3
  6151. 8002702: d921 bls.n 8002748 <HAL_RCC_OscConfig+0x26c>
  6152. {
  6153. /* First increase number of wait states update if necessary */
  6154. if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
  6155. 8002704: 687b ldr r3, [r7, #4]
  6156. 8002706: 6a1b ldr r3, [r3, #32]
  6157. 8002708: 4618 mov r0, r3
  6158. 800270a: f000 fc47 bl 8002f9c <RCC_SetFlashLatencyFromMSIRange>
  6159. 800270e: 4603 mov r3, r0
  6160. 8002710: 2b00 cmp r3, #0
  6161. 8002712: d001 beq.n 8002718 <HAL_RCC_OscConfig+0x23c>
  6162. {
  6163. return HAL_ERROR;
  6164. 8002714: 2301 movs r3, #1
  6165. 8002716: e208 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6166. }
  6167. /* Selects the Multiple Speed oscillator (MSI) clock range .*/
  6168. __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
  6169. 8002718: 4b09 ldr r3, [pc, #36] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6170. 800271a: 685b ldr r3, [r3, #4]
  6171. 800271c: f423 4260 bic.w r2, r3, #57344 ; 0xe000
  6172. 8002720: 687b ldr r3, [r7, #4]
  6173. 8002722: 6a1b ldr r3, [r3, #32]
  6174. 8002724: 4906 ldr r1, [pc, #24] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6175. 8002726: 4313 orrs r3, r2
  6176. 8002728: 604b str r3, [r1, #4]
  6177. /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
  6178. __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
  6179. 800272a: 4b05 ldr r3, [pc, #20] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6180. 800272c: 685b ldr r3, [r3, #4]
  6181. 800272e: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000
  6182. 8002732: 687b ldr r3, [r7, #4]
  6183. 8002734: 69db ldr r3, [r3, #28]
  6184. 8002736: 061b lsls r3, r3, #24
  6185. 8002738: 4901 ldr r1, [pc, #4] ; (8002740 <HAL_RCC_OscConfig+0x264>)
  6186. 800273a: 4313 orrs r3, r2
  6187. 800273c: 604b str r3, [r1, #4]
  6188. 800273e: e020 b.n 8002782 <HAL_RCC_OscConfig+0x2a6>
  6189. 8002740: 40023800 .word 0x40023800
  6190. 8002744: 42470000 .word 0x42470000
  6191. }
  6192. else
  6193. {
  6194. /* Else, keep current flash latency while decreasing applies */
  6195. /* Selects the Multiple Speed oscillator (MSI) clock range .*/
  6196. __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
  6197. 8002748: 4ba4 ldr r3, [pc, #656] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6198. 800274a: 685b ldr r3, [r3, #4]
  6199. 800274c: f423 4260 bic.w r2, r3, #57344 ; 0xe000
  6200. 8002750: 687b ldr r3, [r7, #4]
  6201. 8002752: 6a1b ldr r3, [r3, #32]
  6202. 8002754: 49a1 ldr r1, [pc, #644] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6203. 8002756: 4313 orrs r3, r2
  6204. 8002758: 604b str r3, [r1, #4]
  6205. /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
  6206. __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
  6207. 800275a: 4ba0 ldr r3, [pc, #640] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6208. 800275c: 685b ldr r3, [r3, #4]
  6209. 800275e: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000
  6210. 8002762: 687b ldr r3, [r7, #4]
  6211. 8002764: 69db ldr r3, [r3, #28]
  6212. 8002766: 061b lsls r3, r3, #24
  6213. 8002768: 499c ldr r1, [pc, #624] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6214. 800276a: 4313 orrs r3, r2
  6215. 800276c: 604b str r3, [r1, #4]
  6216. /* Decrease number of wait states update if necessary */
  6217. if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
  6218. 800276e: 687b ldr r3, [r7, #4]
  6219. 8002770: 6a1b ldr r3, [r3, #32]
  6220. 8002772: 4618 mov r0, r3
  6221. 8002774: f000 fc12 bl 8002f9c <RCC_SetFlashLatencyFromMSIRange>
  6222. 8002778: 4603 mov r3, r0
  6223. 800277a: 2b00 cmp r3, #0
  6224. 800277c: d001 beq.n 8002782 <HAL_RCC_OscConfig+0x2a6>
  6225. {
  6226. return HAL_ERROR;
  6227. 800277e: 2301 movs r3, #1
  6228. 8002780: e1d3 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6229. }
  6230. }
  6231. /* Update the SystemCoreClock global variable */
  6232. SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
  6233. 8002782: 687b ldr r3, [r7, #4]
  6234. 8002784: 6a1b ldr r3, [r3, #32]
  6235. 8002786: 0b5b lsrs r3, r3, #13
  6236. 8002788: 3301 adds r3, #1
  6237. 800278a: f44f 4200 mov.w r2, #32768 ; 0x8000
  6238. 800278e: fa02 f303 lsl.w r3, r2, r3
  6239. >> AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
  6240. 8002792: 4a92 ldr r2, [pc, #584] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6241. 8002794: 6892 ldr r2, [r2, #8]
  6242. 8002796: 0912 lsrs r2, r2, #4
  6243. 8002798: f002 020f and.w r2, r2, #15
  6244. 800279c: 4990 ldr r1, [pc, #576] ; (80029e0 <HAL_RCC_OscConfig+0x504>)
  6245. 800279e: 5c8a ldrb r2, [r1, r2]
  6246. 80027a0: 40d3 lsrs r3, r2
  6247. SystemCoreClock = (32768U * (1UL << ((RCC_OscInitStruct->MSIClockRange >> RCC_ICSCR_MSIRANGE_Pos) + 1U)))
  6248. 80027a2: 4a90 ldr r2, [pc, #576] ; (80029e4 <HAL_RCC_OscConfig+0x508>)
  6249. 80027a4: 6013 str r3, [r2, #0]
  6250. /* Configure the source of time base considering new system clocks settings*/
  6251. status = HAL_InitTick(uwTickPrio);
  6252. 80027a6: 4b90 ldr r3, [pc, #576] ; (80029e8 <HAL_RCC_OscConfig+0x50c>)
  6253. 80027a8: 681b ldr r3, [r3, #0]
  6254. 80027aa: 4618 mov r0, r3
  6255. 80027ac: f7fe ff8a bl 80016c4 <HAL_InitTick>
  6256. 80027b0: 4603 mov r3, r0
  6257. 80027b2: 73fb strb r3, [r7, #15]
  6258. if(status != HAL_OK)
  6259. 80027b4: 7bfb ldrb r3, [r7, #15]
  6260. 80027b6: 2b00 cmp r3, #0
  6261. 80027b8: d045 beq.n 8002846 <HAL_RCC_OscConfig+0x36a>
  6262. {
  6263. return status;
  6264. 80027ba: 7bfb ldrb r3, [r7, #15]
  6265. 80027bc: e1b5 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6266. {
  6267. /* Check MSI State */
  6268. assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
  6269. /* Check the MSI State */
  6270. if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
  6271. 80027be: 687b ldr r3, [r7, #4]
  6272. 80027c0: 699b ldr r3, [r3, #24]
  6273. 80027c2: 2b00 cmp r3, #0
  6274. 80027c4: d029 beq.n 800281a <HAL_RCC_OscConfig+0x33e>
  6275. {
  6276. /* Enable the Multi Speed oscillator (MSI). */
  6277. __HAL_RCC_MSI_ENABLE();
  6278. 80027c6: 4b89 ldr r3, [pc, #548] ; (80029ec <HAL_RCC_OscConfig+0x510>)
  6279. 80027c8: 2201 movs r2, #1
  6280. 80027ca: 601a str r2, [r3, #0]
  6281. /* Get Start Tick */
  6282. tickstart = HAL_GetTick();
  6283. 80027cc: f7fe ffc6 bl 800175c <HAL_GetTick>
  6284. 80027d0: 6138 str r0, [r7, #16]
  6285. /* Wait till MSI is ready */
  6286. while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
  6287. 80027d2: e008 b.n 80027e6 <HAL_RCC_OscConfig+0x30a>
  6288. {
  6289. if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
  6290. 80027d4: f7fe ffc2 bl 800175c <HAL_GetTick>
  6291. 80027d8: 4602 mov r2, r0
  6292. 80027da: 693b ldr r3, [r7, #16]
  6293. 80027dc: 1ad3 subs r3, r2, r3
  6294. 80027de: 2b02 cmp r3, #2
  6295. 80027e0: d901 bls.n 80027e6 <HAL_RCC_OscConfig+0x30a>
  6296. {
  6297. return HAL_TIMEOUT;
  6298. 80027e2: 2303 movs r3, #3
  6299. 80027e4: e1a1 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6300. while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
  6301. 80027e6: 4b7d ldr r3, [pc, #500] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6302. 80027e8: 681b ldr r3, [r3, #0]
  6303. 80027ea: f403 7300 and.w r3, r3, #512 ; 0x200
  6304. 80027ee: 2b00 cmp r3, #0
  6305. 80027f0: d0f0 beq.n 80027d4 <HAL_RCC_OscConfig+0x2f8>
  6306. /* Check MSICalibrationValue and MSIClockRange input parameters */
  6307. assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
  6308. assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
  6309. /* Selects the Multiple Speed oscillator (MSI) clock range .*/
  6310. __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
  6311. 80027f2: 4b7a ldr r3, [pc, #488] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6312. 80027f4: 685b ldr r3, [r3, #4]
  6313. 80027f6: f423 4260 bic.w r2, r3, #57344 ; 0xe000
  6314. 80027fa: 687b ldr r3, [r7, #4]
  6315. 80027fc: 6a1b ldr r3, [r3, #32]
  6316. 80027fe: 4977 ldr r1, [pc, #476] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6317. 8002800: 4313 orrs r3, r2
  6318. 8002802: 604b str r3, [r1, #4]
  6319. /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
  6320. __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
  6321. 8002804: 4b75 ldr r3, [pc, #468] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6322. 8002806: 685b ldr r3, [r3, #4]
  6323. 8002808: f023 427f bic.w r2, r3, #4278190080 ; 0xff000000
  6324. 800280c: 687b ldr r3, [r7, #4]
  6325. 800280e: 69db ldr r3, [r3, #28]
  6326. 8002810: 061b lsls r3, r3, #24
  6327. 8002812: 4972 ldr r1, [pc, #456] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6328. 8002814: 4313 orrs r3, r2
  6329. 8002816: 604b str r3, [r1, #4]
  6330. 8002818: e015 b.n 8002846 <HAL_RCC_OscConfig+0x36a>
  6331. }
  6332. else
  6333. {
  6334. /* Disable the Multi Speed oscillator (MSI). */
  6335. __HAL_RCC_MSI_DISABLE();
  6336. 800281a: 4b74 ldr r3, [pc, #464] ; (80029ec <HAL_RCC_OscConfig+0x510>)
  6337. 800281c: 2200 movs r2, #0
  6338. 800281e: 601a str r2, [r3, #0]
  6339. /* Get Start Tick */
  6340. tickstart = HAL_GetTick();
  6341. 8002820: f7fe ff9c bl 800175c <HAL_GetTick>
  6342. 8002824: 6138 str r0, [r7, #16]
  6343. /* Wait till MSI is ready */
  6344. while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
  6345. 8002826: e008 b.n 800283a <HAL_RCC_OscConfig+0x35e>
  6346. {
  6347. if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
  6348. 8002828: f7fe ff98 bl 800175c <HAL_GetTick>
  6349. 800282c: 4602 mov r2, r0
  6350. 800282e: 693b ldr r3, [r7, #16]
  6351. 8002830: 1ad3 subs r3, r2, r3
  6352. 8002832: 2b02 cmp r3, #2
  6353. 8002834: d901 bls.n 800283a <HAL_RCC_OscConfig+0x35e>
  6354. {
  6355. return HAL_TIMEOUT;
  6356. 8002836: 2303 movs r3, #3
  6357. 8002838: e177 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6358. while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != 0U)
  6359. 800283a: 4b68 ldr r3, [pc, #416] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6360. 800283c: 681b ldr r3, [r3, #0]
  6361. 800283e: f403 7300 and.w r3, r3, #512 ; 0x200
  6362. 8002842: 2b00 cmp r3, #0
  6363. 8002844: d1f0 bne.n 8002828 <HAL_RCC_OscConfig+0x34c>
  6364. }
  6365. }
  6366. }
  6367. }
  6368. /*------------------------------ LSI Configuration -------------------------*/
  6369. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
  6370. 8002846: 687b ldr r3, [r7, #4]
  6371. 8002848: 681b ldr r3, [r3, #0]
  6372. 800284a: f003 0308 and.w r3, r3, #8
  6373. 800284e: 2b00 cmp r3, #0
  6374. 8002850: d030 beq.n 80028b4 <HAL_RCC_OscConfig+0x3d8>
  6375. {
  6376. /* Check the parameters */
  6377. assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
  6378. /* Check the LSI State */
  6379. if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
  6380. 8002852: 687b ldr r3, [r7, #4]
  6381. 8002854: 695b ldr r3, [r3, #20]
  6382. 8002856: 2b00 cmp r3, #0
  6383. 8002858: d016 beq.n 8002888 <HAL_RCC_OscConfig+0x3ac>
  6384. {
  6385. /* Enable the Internal Low Speed oscillator (LSI). */
  6386. __HAL_RCC_LSI_ENABLE();
  6387. 800285a: 4b65 ldr r3, [pc, #404] ; (80029f0 <HAL_RCC_OscConfig+0x514>)
  6388. 800285c: 2201 movs r2, #1
  6389. 800285e: 601a str r2, [r3, #0]
  6390. /* Get Start Tick */
  6391. tickstart = HAL_GetTick();
  6392. 8002860: f7fe ff7c bl 800175c <HAL_GetTick>
  6393. 8002864: 6138 str r0, [r7, #16]
  6394. /* Wait till LSI is ready */
  6395. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
  6396. 8002866: e008 b.n 800287a <HAL_RCC_OscConfig+0x39e>
  6397. {
  6398. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  6399. 8002868: f7fe ff78 bl 800175c <HAL_GetTick>
  6400. 800286c: 4602 mov r2, r0
  6401. 800286e: 693b ldr r3, [r7, #16]
  6402. 8002870: 1ad3 subs r3, r2, r3
  6403. 8002872: 2b02 cmp r3, #2
  6404. 8002874: d901 bls.n 800287a <HAL_RCC_OscConfig+0x39e>
  6405. {
  6406. return HAL_TIMEOUT;
  6407. 8002876: 2303 movs r3, #3
  6408. 8002878: e157 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6409. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == 0U)
  6410. 800287a: 4b58 ldr r3, [pc, #352] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6411. 800287c: 6b5b ldr r3, [r3, #52] ; 0x34
  6412. 800287e: f003 0302 and.w r3, r3, #2
  6413. 8002882: 2b00 cmp r3, #0
  6414. 8002884: d0f0 beq.n 8002868 <HAL_RCC_OscConfig+0x38c>
  6415. 8002886: e015 b.n 80028b4 <HAL_RCC_OscConfig+0x3d8>
  6416. }
  6417. }
  6418. else
  6419. {
  6420. /* Disable the Internal Low Speed oscillator (LSI). */
  6421. __HAL_RCC_LSI_DISABLE();
  6422. 8002888: 4b59 ldr r3, [pc, #356] ; (80029f0 <HAL_RCC_OscConfig+0x514>)
  6423. 800288a: 2200 movs r2, #0
  6424. 800288c: 601a str r2, [r3, #0]
  6425. /* Get Start Tick */
  6426. tickstart = HAL_GetTick();
  6427. 800288e: f7fe ff65 bl 800175c <HAL_GetTick>
  6428. 8002892: 6138 str r0, [r7, #16]
  6429. /* Wait till LSI is disabled */
  6430. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
  6431. 8002894: e008 b.n 80028a8 <HAL_RCC_OscConfig+0x3cc>
  6432. {
  6433. if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
  6434. 8002896: f7fe ff61 bl 800175c <HAL_GetTick>
  6435. 800289a: 4602 mov r2, r0
  6436. 800289c: 693b ldr r3, [r7, #16]
  6437. 800289e: 1ad3 subs r3, r2, r3
  6438. 80028a0: 2b02 cmp r3, #2
  6439. 80028a2: d901 bls.n 80028a8 <HAL_RCC_OscConfig+0x3cc>
  6440. {
  6441. return HAL_TIMEOUT;
  6442. 80028a4: 2303 movs r3, #3
  6443. 80028a6: e140 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6444. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != 0U)
  6445. 80028a8: 4b4c ldr r3, [pc, #304] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6446. 80028aa: 6b5b ldr r3, [r3, #52] ; 0x34
  6447. 80028ac: f003 0302 and.w r3, r3, #2
  6448. 80028b0: 2b00 cmp r3, #0
  6449. 80028b2: d1f0 bne.n 8002896 <HAL_RCC_OscConfig+0x3ba>
  6450. }
  6451. }
  6452. }
  6453. }
  6454. /*------------------------------ LSE Configuration -------------------------*/
  6455. if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
  6456. 80028b4: 687b ldr r3, [r7, #4]
  6457. 80028b6: 681b ldr r3, [r3, #0]
  6458. 80028b8: f003 0304 and.w r3, r3, #4
  6459. 80028bc: 2b00 cmp r3, #0
  6460. 80028be: f000 80b5 beq.w 8002a2c <HAL_RCC_OscConfig+0x550>
  6461. {
  6462. FlagStatus pwrclkchanged = RESET;
  6463. 80028c2: 2300 movs r3, #0
  6464. 80028c4: 77fb strb r3, [r7, #31]
  6465. /* Check the parameters */
  6466. assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
  6467. /* Update LSE configuration in Backup Domain control register */
  6468. /* Requires to enable write access to Backup Domain of necessary */
  6469. if(__HAL_RCC_PWR_IS_CLK_DISABLED())
  6470. 80028c6: 4b45 ldr r3, [pc, #276] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6471. 80028c8: 6a5b ldr r3, [r3, #36] ; 0x24
  6472. 80028ca: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  6473. 80028ce: 2b00 cmp r3, #0
  6474. 80028d0: d10d bne.n 80028ee <HAL_RCC_OscConfig+0x412>
  6475. {
  6476. __HAL_RCC_PWR_CLK_ENABLE();
  6477. 80028d2: 4b42 ldr r3, [pc, #264] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6478. 80028d4: 6a5b ldr r3, [r3, #36] ; 0x24
  6479. 80028d6: 4a41 ldr r2, [pc, #260] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6480. 80028d8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  6481. 80028dc: 6253 str r3, [r2, #36] ; 0x24
  6482. 80028de: 4b3f ldr r3, [pc, #252] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6483. 80028e0: 6a5b ldr r3, [r3, #36] ; 0x24
  6484. 80028e2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  6485. 80028e6: 60bb str r3, [r7, #8]
  6486. 80028e8: 68bb ldr r3, [r7, #8]
  6487. pwrclkchanged = SET;
  6488. 80028ea: 2301 movs r3, #1
  6489. 80028ec: 77fb strb r3, [r7, #31]
  6490. }
  6491. if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  6492. 80028ee: 4b41 ldr r3, [pc, #260] ; (80029f4 <HAL_RCC_OscConfig+0x518>)
  6493. 80028f0: 681b ldr r3, [r3, #0]
  6494. 80028f2: f403 7380 and.w r3, r3, #256 ; 0x100
  6495. 80028f6: 2b00 cmp r3, #0
  6496. 80028f8: d118 bne.n 800292c <HAL_RCC_OscConfig+0x450>
  6497. {
  6498. /* Enable write access to Backup domain */
  6499. SET_BIT(PWR->CR, PWR_CR_DBP);
  6500. 80028fa: 4b3e ldr r3, [pc, #248] ; (80029f4 <HAL_RCC_OscConfig+0x518>)
  6501. 80028fc: 681b ldr r3, [r3, #0]
  6502. 80028fe: 4a3d ldr r2, [pc, #244] ; (80029f4 <HAL_RCC_OscConfig+0x518>)
  6503. 8002900: f443 7380 orr.w r3, r3, #256 ; 0x100
  6504. 8002904: 6013 str r3, [r2, #0]
  6505. /* Wait for Backup domain Write protection disable */
  6506. tickstart = HAL_GetTick();
  6507. 8002906: f7fe ff29 bl 800175c <HAL_GetTick>
  6508. 800290a: 6138 str r0, [r7, #16]
  6509. while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  6510. 800290c: e008 b.n 8002920 <HAL_RCC_OscConfig+0x444>
  6511. {
  6512. if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
  6513. 800290e: f7fe ff25 bl 800175c <HAL_GetTick>
  6514. 8002912: 4602 mov r2, r0
  6515. 8002914: 693b ldr r3, [r7, #16]
  6516. 8002916: 1ad3 subs r3, r2, r3
  6517. 8002918: 2b64 cmp r3, #100 ; 0x64
  6518. 800291a: d901 bls.n 8002920 <HAL_RCC_OscConfig+0x444>
  6519. {
  6520. return HAL_TIMEOUT;
  6521. 800291c: 2303 movs r3, #3
  6522. 800291e: e104 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6523. while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
  6524. 8002920: 4b34 ldr r3, [pc, #208] ; (80029f4 <HAL_RCC_OscConfig+0x518>)
  6525. 8002922: 681b ldr r3, [r3, #0]
  6526. 8002924: f403 7380 and.w r3, r3, #256 ; 0x100
  6527. 8002928: 2b00 cmp r3, #0
  6528. 800292a: d0f0 beq.n 800290e <HAL_RCC_OscConfig+0x432>
  6529. }
  6530. }
  6531. }
  6532. /* Set the new LSE configuration -----------------------------------------*/
  6533. __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
  6534. 800292c: 687b ldr r3, [r7, #4]
  6535. 800292e: 689b ldr r3, [r3, #8]
  6536. 8002930: 2b01 cmp r3, #1
  6537. 8002932: d106 bne.n 8002942 <HAL_RCC_OscConfig+0x466>
  6538. 8002934: 4b29 ldr r3, [pc, #164] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6539. 8002936: 6b5b ldr r3, [r3, #52] ; 0x34
  6540. 8002938: 4a28 ldr r2, [pc, #160] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6541. 800293a: f443 7380 orr.w r3, r3, #256 ; 0x100
  6542. 800293e: 6353 str r3, [r2, #52] ; 0x34
  6543. 8002940: e02d b.n 800299e <HAL_RCC_OscConfig+0x4c2>
  6544. 8002942: 687b ldr r3, [r7, #4]
  6545. 8002944: 689b ldr r3, [r3, #8]
  6546. 8002946: 2b00 cmp r3, #0
  6547. 8002948: d10c bne.n 8002964 <HAL_RCC_OscConfig+0x488>
  6548. 800294a: 4b24 ldr r3, [pc, #144] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6549. 800294c: 6b5b ldr r3, [r3, #52] ; 0x34
  6550. 800294e: 4a23 ldr r2, [pc, #140] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6551. 8002950: f423 7380 bic.w r3, r3, #256 ; 0x100
  6552. 8002954: 6353 str r3, [r2, #52] ; 0x34
  6553. 8002956: 4b21 ldr r3, [pc, #132] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6554. 8002958: 6b5b ldr r3, [r3, #52] ; 0x34
  6555. 800295a: 4a20 ldr r2, [pc, #128] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6556. 800295c: f423 6380 bic.w r3, r3, #1024 ; 0x400
  6557. 8002960: 6353 str r3, [r2, #52] ; 0x34
  6558. 8002962: e01c b.n 800299e <HAL_RCC_OscConfig+0x4c2>
  6559. 8002964: 687b ldr r3, [r7, #4]
  6560. 8002966: 689b ldr r3, [r3, #8]
  6561. 8002968: 2b05 cmp r3, #5
  6562. 800296a: d10c bne.n 8002986 <HAL_RCC_OscConfig+0x4aa>
  6563. 800296c: 4b1b ldr r3, [pc, #108] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6564. 800296e: 6b5b ldr r3, [r3, #52] ; 0x34
  6565. 8002970: 4a1a ldr r2, [pc, #104] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6566. 8002972: f443 6380 orr.w r3, r3, #1024 ; 0x400
  6567. 8002976: 6353 str r3, [r2, #52] ; 0x34
  6568. 8002978: 4b18 ldr r3, [pc, #96] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6569. 800297a: 6b5b ldr r3, [r3, #52] ; 0x34
  6570. 800297c: 4a17 ldr r2, [pc, #92] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6571. 800297e: f443 7380 orr.w r3, r3, #256 ; 0x100
  6572. 8002982: 6353 str r3, [r2, #52] ; 0x34
  6573. 8002984: e00b b.n 800299e <HAL_RCC_OscConfig+0x4c2>
  6574. 8002986: 4b15 ldr r3, [pc, #84] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6575. 8002988: 6b5b ldr r3, [r3, #52] ; 0x34
  6576. 800298a: 4a14 ldr r2, [pc, #80] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6577. 800298c: f423 7380 bic.w r3, r3, #256 ; 0x100
  6578. 8002990: 6353 str r3, [r2, #52] ; 0x34
  6579. 8002992: 4b12 ldr r3, [pc, #72] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6580. 8002994: 6b5b ldr r3, [r3, #52] ; 0x34
  6581. 8002996: 4a11 ldr r2, [pc, #68] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6582. 8002998: f423 6380 bic.w r3, r3, #1024 ; 0x400
  6583. 800299c: 6353 str r3, [r2, #52] ; 0x34
  6584. /* Check the LSE State */
  6585. if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
  6586. 800299e: 687b ldr r3, [r7, #4]
  6587. 80029a0: 689b ldr r3, [r3, #8]
  6588. 80029a2: 2b00 cmp r3, #0
  6589. 80029a4: d015 beq.n 80029d2 <HAL_RCC_OscConfig+0x4f6>
  6590. {
  6591. /* Get Start Tick */
  6592. tickstart = HAL_GetTick();
  6593. 80029a6: f7fe fed9 bl 800175c <HAL_GetTick>
  6594. 80029aa: 6138 str r0, [r7, #16]
  6595. /* Wait till LSE is ready */
  6596. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  6597. 80029ac: e00a b.n 80029c4 <HAL_RCC_OscConfig+0x4e8>
  6598. {
  6599. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  6600. 80029ae: f7fe fed5 bl 800175c <HAL_GetTick>
  6601. 80029b2: 4602 mov r2, r0
  6602. 80029b4: 693b ldr r3, [r7, #16]
  6603. 80029b6: 1ad3 subs r3, r2, r3
  6604. 80029b8: f241 3288 movw r2, #5000 ; 0x1388
  6605. 80029bc: 4293 cmp r3, r2
  6606. 80029be: d901 bls.n 80029c4 <HAL_RCC_OscConfig+0x4e8>
  6607. {
  6608. return HAL_TIMEOUT;
  6609. 80029c0: 2303 movs r3, #3
  6610. 80029c2: e0b2 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6611. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U)
  6612. 80029c4: 4b05 ldr r3, [pc, #20] ; (80029dc <HAL_RCC_OscConfig+0x500>)
  6613. 80029c6: 6b5b ldr r3, [r3, #52] ; 0x34
  6614. 80029c8: f403 7300 and.w r3, r3, #512 ; 0x200
  6615. 80029cc: 2b00 cmp r3, #0
  6616. 80029ce: d0ee beq.n 80029ae <HAL_RCC_OscConfig+0x4d2>
  6617. 80029d0: e023 b.n 8002a1a <HAL_RCC_OscConfig+0x53e>
  6618. }
  6619. }
  6620. else
  6621. {
  6622. /* Get Start Tick */
  6623. tickstart = HAL_GetTick();
  6624. 80029d2: f7fe fec3 bl 800175c <HAL_GetTick>
  6625. 80029d6: 6138 str r0, [r7, #16]
  6626. /* Wait till LSE is disabled */
  6627. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
  6628. 80029d8: e019 b.n 8002a0e <HAL_RCC_OscConfig+0x532>
  6629. 80029da: bf00 nop
  6630. 80029dc: 40023800 .word 0x40023800
  6631. 80029e0: 08007b6c .word 0x08007b6c
  6632. 80029e4: 20000004 .word 0x20000004
  6633. 80029e8: 20000008 .word 0x20000008
  6634. 80029ec: 42470020 .word 0x42470020
  6635. 80029f0: 42470680 .word 0x42470680
  6636. 80029f4: 40007000 .word 0x40007000
  6637. {
  6638. if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
  6639. 80029f8: f7fe feb0 bl 800175c <HAL_GetTick>
  6640. 80029fc: 4602 mov r2, r0
  6641. 80029fe: 693b ldr r3, [r7, #16]
  6642. 8002a00: 1ad3 subs r3, r2, r3
  6643. 8002a02: f241 3288 movw r2, #5000 ; 0x1388
  6644. 8002a06: 4293 cmp r3, r2
  6645. 8002a08: d901 bls.n 8002a0e <HAL_RCC_OscConfig+0x532>
  6646. {
  6647. return HAL_TIMEOUT;
  6648. 8002a0a: 2303 movs r3, #3
  6649. 8002a0c: e08d b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6650. while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != 0U)
  6651. 8002a0e: 4b49 ldr r3, [pc, #292] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6652. 8002a10: 6b5b ldr r3, [r3, #52] ; 0x34
  6653. 8002a12: f403 7300 and.w r3, r3, #512 ; 0x200
  6654. 8002a16: 2b00 cmp r3, #0
  6655. 8002a18: d1ee bne.n 80029f8 <HAL_RCC_OscConfig+0x51c>
  6656. }
  6657. }
  6658. }
  6659. /* Require to disable power clock if necessary */
  6660. if(pwrclkchanged == SET)
  6661. 8002a1a: 7ffb ldrb r3, [r7, #31]
  6662. 8002a1c: 2b01 cmp r3, #1
  6663. 8002a1e: d105 bne.n 8002a2c <HAL_RCC_OscConfig+0x550>
  6664. {
  6665. __HAL_RCC_PWR_CLK_DISABLE();
  6666. 8002a20: 4b44 ldr r3, [pc, #272] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6667. 8002a22: 6a5b ldr r3, [r3, #36] ; 0x24
  6668. 8002a24: 4a43 ldr r2, [pc, #268] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6669. 8002a26: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
  6670. 8002a2a: 6253 str r3, [r2, #36] ; 0x24
  6671. }
  6672. /*-------------------------------- PLL Configuration -----------------------*/
  6673. /* Check the parameters */
  6674. assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  6675. if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
  6676. 8002a2c: 687b ldr r3, [r7, #4]
  6677. 8002a2e: 6a5b ldr r3, [r3, #36] ; 0x24
  6678. 8002a30: 2b00 cmp r3, #0
  6679. 8002a32: d079 beq.n 8002b28 <HAL_RCC_OscConfig+0x64c>
  6680. {
  6681. /* Check if the PLL is used as system clock or not */
  6682. if(sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  6683. 8002a34: 69bb ldr r3, [r7, #24]
  6684. 8002a36: 2b0c cmp r3, #12
  6685. 8002a38: d056 beq.n 8002ae8 <HAL_RCC_OscConfig+0x60c>
  6686. {
  6687. if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
  6688. 8002a3a: 687b ldr r3, [r7, #4]
  6689. 8002a3c: 6a5b ldr r3, [r3, #36] ; 0x24
  6690. 8002a3e: 2b02 cmp r3, #2
  6691. 8002a40: d13b bne.n 8002aba <HAL_RCC_OscConfig+0x5de>
  6692. assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
  6693. assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
  6694. assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
  6695. /* Disable the main PLL. */
  6696. __HAL_RCC_PLL_DISABLE();
  6697. 8002a42: 4b3d ldr r3, [pc, #244] ; (8002b38 <HAL_RCC_OscConfig+0x65c>)
  6698. 8002a44: 2200 movs r2, #0
  6699. 8002a46: 601a str r2, [r3, #0]
  6700. /* Get Start Tick */
  6701. tickstart = HAL_GetTick();
  6702. 8002a48: f7fe fe88 bl 800175c <HAL_GetTick>
  6703. 8002a4c: 6138 str r0, [r7, #16]
  6704. /* Wait till PLL is disabled */
  6705. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  6706. 8002a4e: e008 b.n 8002a62 <HAL_RCC_OscConfig+0x586>
  6707. {
  6708. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  6709. 8002a50: f7fe fe84 bl 800175c <HAL_GetTick>
  6710. 8002a54: 4602 mov r2, r0
  6711. 8002a56: 693b ldr r3, [r7, #16]
  6712. 8002a58: 1ad3 subs r3, r2, r3
  6713. 8002a5a: 2b02 cmp r3, #2
  6714. 8002a5c: d901 bls.n 8002a62 <HAL_RCC_OscConfig+0x586>
  6715. {
  6716. return HAL_TIMEOUT;
  6717. 8002a5e: 2303 movs r3, #3
  6718. 8002a60: e063 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6719. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  6720. 8002a62: 4b34 ldr r3, [pc, #208] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6721. 8002a64: 681b ldr r3, [r3, #0]
  6722. 8002a66: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  6723. 8002a6a: 2b00 cmp r3, #0
  6724. 8002a6c: d1f0 bne.n 8002a50 <HAL_RCC_OscConfig+0x574>
  6725. }
  6726. }
  6727. /* Configure the main PLL clock source, multiplication and division factors. */
  6728. __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
  6729. 8002a6e: 4b31 ldr r3, [pc, #196] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6730. 8002a70: 689b ldr r3, [r3, #8]
  6731. 8002a72: f423 027d bic.w r2, r3, #16580608 ; 0xfd0000
  6732. 8002a76: 687b ldr r3, [r7, #4]
  6733. 8002a78: 6a99 ldr r1, [r3, #40] ; 0x28
  6734. 8002a7a: 687b ldr r3, [r7, #4]
  6735. 8002a7c: 6adb ldr r3, [r3, #44] ; 0x2c
  6736. 8002a7e: 4319 orrs r1, r3
  6737. 8002a80: 687b ldr r3, [r7, #4]
  6738. 8002a82: 6b1b ldr r3, [r3, #48] ; 0x30
  6739. 8002a84: 430b orrs r3, r1
  6740. 8002a86: 492b ldr r1, [pc, #172] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6741. 8002a88: 4313 orrs r3, r2
  6742. 8002a8a: 608b str r3, [r1, #8]
  6743. RCC_OscInitStruct->PLL.PLLMUL,
  6744. RCC_OscInitStruct->PLL.PLLDIV);
  6745. /* Enable the main PLL. */
  6746. __HAL_RCC_PLL_ENABLE();
  6747. 8002a8c: 4b2a ldr r3, [pc, #168] ; (8002b38 <HAL_RCC_OscConfig+0x65c>)
  6748. 8002a8e: 2201 movs r2, #1
  6749. 8002a90: 601a str r2, [r3, #0]
  6750. /* Get Start Tick */
  6751. tickstart = HAL_GetTick();
  6752. 8002a92: f7fe fe63 bl 800175c <HAL_GetTick>
  6753. 8002a96: 6138 str r0, [r7, #16]
  6754. /* Wait till PLL is ready */
  6755. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  6756. 8002a98: e008 b.n 8002aac <HAL_RCC_OscConfig+0x5d0>
  6757. {
  6758. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  6759. 8002a9a: f7fe fe5f bl 800175c <HAL_GetTick>
  6760. 8002a9e: 4602 mov r2, r0
  6761. 8002aa0: 693b ldr r3, [r7, #16]
  6762. 8002aa2: 1ad3 subs r3, r2, r3
  6763. 8002aa4: 2b02 cmp r3, #2
  6764. 8002aa6: d901 bls.n 8002aac <HAL_RCC_OscConfig+0x5d0>
  6765. {
  6766. return HAL_TIMEOUT;
  6767. 8002aa8: 2303 movs r3, #3
  6768. 8002aaa: e03e b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6769. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  6770. 8002aac: 4b21 ldr r3, [pc, #132] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6771. 8002aae: 681b ldr r3, [r3, #0]
  6772. 8002ab0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  6773. 8002ab4: 2b00 cmp r3, #0
  6774. 8002ab6: d0f0 beq.n 8002a9a <HAL_RCC_OscConfig+0x5be>
  6775. 8002ab8: e036 b.n 8002b28 <HAL_RCC_OscConfig+0x64c>
  6776. }
  6777. }
  6778. else
  6779. {
  6780. /* Disable the main PLL. */
  6781. __HAL_RCC_PLL_DISABLE();
  6782. 8002aba: 4b1f ldr r3, [pc, #124] ; (8002b38 <HAL_RCC_OscConfig+0x65c>)
  6783. 8002abc: 2200 movs r2, #0
  6784. 8002abe: 601a str r2, [r3, #0]
  6785. /* Get Start Tick */
  6786. tickstart = HAL_GetTick();
  6787. 8002ac0: f7fe fe4c bl 800175c <HAL_GetTick>
  6788. 8002ac4: 6138 str r0, [r7, #16]
  6789. /* Wait till PLL is disabled */
  6790. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  6791. 8002ac6: e008 b.n 8002ada <HAL_RCC_OscConfig+0x5fe>
  6792. {
  6793. if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
  6794. 8002ac8: f7fe fe48 bl 800175c <HAL_GetTick>
  6795. 8002acc: 4602 mov r2, r0
  6796. 8002ace: 693b ldr r3, [r7, #16]
  6797. 8002ad0: 1ad3 subs r3, r2, r3
  6798. 8002ad2: 2b02 cmp r3, #2
  6799. 8002ad4: d901 bls.n 8002ada <HAL_RCC_OscConfig+0x5fe>
  6800. {
  6801. return HAL_TIMEOUT;
  6802. 8002ad6: 2303 movs r3, #3
  6803. 8002ad8: e027 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6804. while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != 0U)
  6805. 8002ada: 4b16 ldr r3, [pc, #88] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6806. 8002adc: 681b ldr r3, [r3, #0]
  6807. 8002ade: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  6808. 8002ae2: 2b00 cmp r3, #0
  6809. 8002ae4: d1f0 bne.n 8002ac8 <HAL_RCC_OscConfig+0x5ec>
  6810. 8002ae6: e01f b.n 8002b28 <HAL_RCC_OscConfig+0x64c>
  6811. }
  6812. }
  6813. else
  6814. {
  6815. /* Check if there is a request to disable the PLL used as System clock source */
  6816. if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
  6817. 8002ae8: 687b ldr r3, [r7, #4]
  6818. 8002aea: 6a5b ldr r3, [r3, #36] ; 0x24
  6819. 8002aec: 2b01 cmp r3, #1
  6820. 8002aee: d101 bne.n 8002af4 <HAL_RCC_OscConfig+0x618>
  6821. {
  6822. return HAL_ERROR;
  6823. 8002af0: 2301 movs r3, #1
  6824. 8002af2: e01a b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6825. }
  6826. else
  6827. {
  6828. /* Do not return HAL_ERROR if request repeats the current configuration */
  6829. pll_config = RCC->CFGR;
  6830. 8002af4: 4b0f ldr r3, [pc, #60] ; (8002b34 <HAL_RCC_OscConfig+0x658>)
  6831. 8002af6: 689b ldr r3, [r3, #8]
  6832. 8002af8: 617b str r3, [r7, #20]
  6833. if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
  6834. 8002afa: 697b ldr r3, [r7, #20]
  6835. 8002afc: f403 3280 and.w r2, r3, #65536 ; 0x10000
  6836. 8002b00: 687b ldr r3, [r7, #4]
  6837. 8002b02: 6a9b ldr r3, [r3, #40] ; 0x28
  6838. 8002b04: 429a cmp r2, r3
  6839. 8002b06: d10d bne.n 8002b24 <HAL_RCC_OscConfig+0x648>
  6840. (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
  6841. 8002b08: 697b ldr r3, [r7, #20]
  6842. 8002b0a: f403 1270 and.w r2, r3, #3932160 ; 0x3c0000
  6843. 8002b0e: 687b ldr r3, [r7, #4]
  6844. 8002b10: 6adb ldr r3, [r3, #44] ; 0x2c
  6845. if((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
  6846. 8002b12: 429a cmp r2, r3
  6847. 8002b14: d106 bne.n 8002b24 <HAL_RCC_OscConfig+0x648>
  6848. (READ_BIT(pll_config, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV))
  6849. 8002b16: 697b ldr r3, [r7, #20]
  6850. 8002b18: f403 0240 and.w r2, r3, #12582912 ; 0xc00000
  6851. 8002b1c: 687b ldr r3, [r7, #4]
  6852. 8002b1e: 6b1b ldr r3, [r3, #48] ; 0x30
  6853. (READ_BIT(pll_config, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) ||
  6854. 8002b20: 429a cmp r2, r3
  6855. 8002b22: d001 beq.n 8002b28 <HAL_RCC_OscConfig+0x64c>
  6856. {
  6857. return HAL_ERROR;
  6858. 8002b24: 2301 movs r3, #1
  6859. 8002b26: e000 b.n 8002b2a <HAL_RCC_OscConfig+0x64e>
  6860. }
  6861. }
  6862. }
  6863. }
  6864. return HAL_OK;
  6865. 8002b28: 2300 movs r3, #0
  6866. }
  6867. 8002b2a: 4618 mov r0, r3
  6868. 8002b2c: 3720 adds r7, #32
  6869. 8002b2e: 46bd mov sp, r7
  6870. 8002b30: bd80 pop {r7, pc}
  6871. 8002b32: bf00 nop
  6872. 8002b34: 40023800 .word 0x40023800
  6873. 8002b38: 42470060 .word 0x42470060
  6874. 08002b3c <HAL_RCC_ClockConfig>:
  6875. * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  6876. * (for more details refer to section above "Initialization/de-initialization functions")
  6877. * @retval HAL status
  6878. */
  6879. HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
  6880. {
  6881. 8002b3c: b580 push {r7, lr}
  6882. 8002b3e: b084 sub sp, #16
  6883. 8002b40: af00 add r7, sp, #0
  6884. 8002b42: 6078 str r0, [r7, #4]
  6885. 8002b44: 6039 str r1, [r7, #0]
  6886. uint32_t tickstart;
  6887. HAL_StatusTypeDef status;
  6888. /* Check the parameters */
  6889. if(RCC_ClkInitStruct == NULL)
  6890. 8002b46: 687b ldr r3, [r7, #4]
  6891. 8002b48: 2b00 cmp r3, #0
  6892. 8002b4a: d101 bne.n 8002b50 <HAL_RCC_ClockConfig+0x14>
  6893. {
  6894. return HAL_ERROR;
  6895. 8002b4c: 2301 movs r3, #1
  6896. 8002b4e: e11a b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  6897. /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
  6898. must be correctly programmed according to the frequency of the CPU clock
  6899. (HCLK) and the supply voltage of the device. */
  6900. /* Increasing the number of wait states because of higher CPU frequency */
  6901. if(FLatency > __HAL_FLASH_GET_LATENCY())
  6902. 8002b50: 4b8f ldr r3, [pc, #572] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  6903. 8002b52: 681b ldr r3, [r3, #0]
  6904. 8002b54: f003 0301 and.w r3, r3, #1
  6905. 8002b58: 683a ldr r2, [r7, #0]
  6906. 8002b5a: 429a cmp r2, r3
  6907. 8002b5c: d919 bls.n 8002b92 <HAL_RCC_ClockConfig+0x56>
  6908. {
  6909. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  6910. __HAL_FLASH_SET_LATENCY(FLatency);
  6911. 8002b5e: 683b ldr r3, [r7, #0]
  6912. 8002b60: 2b01 cmp r3, #1
  6913. 8002b62: d105 bne.n 8002b70 <HAL_RCC_ClockConfig+0x34>
  6914. 8002b64: 4b8a ldr r3, [pc, #552] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  6915. 8002b66: 681b ldr r3, [r3, #0]
  6916. 8002b68: 4a89 ldr r2, [pc, #548] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  6917. 8002b6a: f043 0304 orr.w r3, r3, #4
  6918. 8002b6e: 6013 str r3, [r2, #0]
  6919. 8002b70: 4b87 ldr r3, [pc, #540] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  6920. 8002b72: 681b ldr r3, [r3, #0]
  6921. 8002b74: f023 0201 bic.w r2, r3, #1
  6922. 8002b78: 4985 ldr r1, [pc, #532] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  6923. 8002b7a: 683b ldr r3, [r7, #0]
  6924. 8002b7c: 4313 orrs r3, r2
  6925. 8002b7e: 600b str r3, [r1, #0]
  6926. /* Check that the new number of wait states is taken into account to access the Flash
  6927. memory by reading the FLASH_ACR register */
  6928. if(__HAL_FLASH_GET_LATENCY() != FLatency)
  6929. 8002b80: 4b83 ldr r3, [pc, #524] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  6930. 8002b82: 681b ldr r3, [r3, #0]
  6931. 8002b84: f003 0301 and.w r3, r3, #1
  6932. 8002b88: 683a ldr r2, [r7, #0]
  6933. 8002b8a: 429a cmp r2, r3
  6934. 8002b8c: d001 beq.n 8002b92 <HAL_RCC_ClockConfig+0x56>
  6935. {
  6936. return HAL_ERROR;
  6937. 8002b8e: 2301 movs r3, #1
  6938. 8002b90: e0f9 b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  6939. }
  6940. }
  6941. /*-------------------------- HCLK Configuration --------------------------*/
  6942. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
  6943. 8002b92: 687b ldr r3, [r7, #4]
  6944. 8002b94: 681b ldr r3, [r3, #0]
  6945. 8002b96: f003 0302 and.w r3, r3, #2
  6946. 8002b9a: 2b00 cmp r3, #0
  6947. 8002b9c: d008 beq.n 8002bb0 <HAL_RCC_ClockConfig+0x74>
  6948. {
  6949. assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
  6950. MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
  6951. 8002b9e: 4b7d ldr r3, [pc, #500] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  6952. 8002ba0: 689b ldr r3, [r3, #8]
  6953. 8002ba2: f023 02f0 bic.w r2, r3, #240 ; 0xf0
  6954. 8002ba6: 687b ldr r3, [r7, #4]
  6955. 8002ba8: 689b ldr r3, [r3, #8]
  6956. 8002baa: 497a ldr r1, [pc, #488] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  6957. 8002bac: 4313 orrs r3, r2
  6958. 8002bae: 608b str r3, [r1, #8]
  6959. }
  6960. /*------------------------- SYSCLK Configuration ---------------------------*/
  6961. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
  6962. 8002bb0: 687b ldr r3, [r7, #4]
  6963. 8002bb2: 681b ldr r3, [r3, #0]
  6964. 8002bb4: f003 0301 and.w r3, r3, #1
  6965. 8002bb8: 2b00 cmp r3, #0
  6966. 8002bba: f000 808e beq.w 8002cda <HAL_RCC_ClockConfig+0x19e>
  6967. {
  6968. assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
  6969. /* HSE is selected as System Clock Source */
  6970. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  6971. 8002bbe: 687b ldr r3, [r7, #4]
  6972. 8002bc0: 685b ldr r3, [r3, #4]
  6973. 8002bc2: 2b02 cmp r3, #2
  6974. 8002bc4: d107 bne.n 8002bd6 <HAL_RCC_ClockConfig+0x9a>
  6975. {
  6976. /* Check the HSE ready flag */
  6977. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == 0U)
  6978. 8002bc6: 4b73 ldr r3, [pc, #460] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  6979. 8002bc8: 681b ldr r3, [r3, #0]
  6980. 8002bca: f403 3300 and.w r3, r3, #131072 ; 0x20000
  6981. 8002bce: 2b00 cmp r3, #0
  6982. 8002bd0: d121 bne.n 8002c16 <HAL_RCC_ClockConfig+0xda>
  6983. {
  6984. return HAL_ERROR;
  6985. 8002bd2: 2301 movs r3, #1
  6986. 8002bd4: e0d7 b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  6987. }
  6988. }
  6989. /* PLL is selected as System Clock Source */
  6990. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  6991. 8002bd6: 687b ldr r3, [r7, #4]
  6992. 8002bd8: 685b ldr r3, [r3, #4]
  6993. 8002bda: 2b03 cmp r3, #3
  6994. 8002bdc: d107 bne.n 8002bee <HAL_RCC_ClockConfig+0xb2>
  6995. {
  6996. /* Check the PLL ready flag */
  6997. if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == 0U)
  6998. 8002bde: 4b6d ldr r3, [pc, #436] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  6999. 8002be0: 681b ldr r3, [r3, #0]
  7000. 8002be2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
  7001. 8002be6: 2b00 cmp r3, #0
  7002. 8002be8: d115 bne.n 8002c16 <HAL_RCC_ClockConfig+0xda>
  7003. {
  7004. return HAL_ERROR;
  7005. 8002bea: 2301 movs r3, #1
  7006. 8002bec: e0cb b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7007. }
  7008. }
  7009. /* HSI is selected as System Clock Source */
  7010. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
  7011. 8002bee: 687b ldr r3, [r7, #4]
  7012. 8002bf0: 685b ldr r3, [r3, #4]
  7013. 8002bf2: 2b01 cmp r3, #1
  7014. 8002bf4: d107 bne.n 8002c06 <HAL_RCC_ClockConfig+0xca>
  7015. {
  7016. /* Check the HSI ready flag */
  7017. if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == 0U)
  7018. 8002bf6: 4b67 ldr r3, [pc, #412] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7019. 8002bf8: 681b ldr r3, [r3, #0]
  7020. 8002bfa: f003 0302 and.w r3, r3, #2
  7021. 8002bfe: 2b00 cmp r3, #0
  7022. 8002c00: d109 bne.n 8002c16 <HAL_RCC_ClockConfig+0xda>
  7023. {
  7024. return HAL_ERROR;
  7025. 8002c02: 2301 movs r3, #1
  7026. 8002c04: e0bf b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7027. }
  7028. /* MSI is selected as System Clock Source */
  7029. else
  7030. {
  7031. /* Check the MSI ready flag */
  7032. if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == 0U)
  7033. 8002c06: 4b63 ldr r3, [pc, #396] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7034. 8002c08: 681b ldr r3, [r3, #0]
  7035. 8002c0a: f403 7300 and.w r3, r3, #512 ; 0x200
  7036. 8002c0e: 2b00 cmp r3, #0
  7037. 8002c10: d101 bne.n 8002c16 <HAL_RCC_ClockConfig+0xda>
  7038. {
  7039. return HAL_ERROR;
  7040. 8002c12: 2301 movs r3, #1
  7041. 8002c14: e0b7 b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7042. }
  7043. }
  7044. __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
  7045. 8002c16: 4b5f ldr r3, [pc, #380] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7046. 8002c18: 689b ldr r3, [r3, #8]
  7047. 8002c1a: f023 0203 bic.w r2, r3, #3
  7048. 8002c1e: 687b ldr r3, [r7, #4]
  7049. 8002c20: 685b ldr r3, [r3, #4]
  7050. 8002c22: 495c ldr r1, [pc, #368] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7051. 8002c24: 4313 orrs r3, r2
  7052. 8002c26: 608b str r3, [r1, #8]
  7053. /* Get Start Tick */
  7054. tickstart = HAL_GetTick();
  7055. 8002c28: f7fe fd98 bl 800175c <HAL_GetTick>
  7056. 8002c2c: 60f8 str r0, [r7, #12]
  7057. if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
  7058. 8002c2e: 687b ldr r3, [r7, #4]
  7059. 8002c30: 685b ldr r3, [r3, #4]
  7060. 8002c32: 2b02 cmp r3, #2
  7061. 8002c34: d112 bne.n 8002c5c <HAL_RCC_ClockConfig+0x120>
  7062. {
  7063. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
  7064. 8002c36: e00a b.n 8002c4e <HAL_RCC_ClockConfig+0x112>
  7065. {
  7066. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  7067. 8002c38: f7fe fd90 bl 800175c <HAL_GetTick>
  7068. 8002c3c: 4602 mov r2, r0
  7069. 8002c3e: 68fb ldr r3, [r7, #12]
  7070. 8002c40: 1ad3 subs r3, r2, r3
  7071. 8002c42: f241 3288 movw r2, #5000 ; 0x1388
  7072. 8002c46: 4293 cmp r3, r2
  7073. 8002c48: d901 bls.n 8002c4e <HAL_RCC_ClockConfig+0x112>
  7074. {
  7075. return HAL_TIMEOUT;
  7076. 8002c4a: 2303 movs r3, #3
  7077. 8002c4c: e09b b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7078. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
  7079. 8002c4e: 4b51 ldr r3, [pc, #324] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7080. 8002c50: 689b ldr r3, [r3, #8]
  7081. 8002c52: f003 030c and.w r3, r3, #12
  7082. 8002c56: 2b08 cmp r3, #8
  7083. 8002c58: d1ee bne.n 8002c38 <HAL_RCC_ClockConfig+0xfc>
  7084. 8002c5a: e03e b.n 8002cda <HAL_RCC_ClockConfig+0x19e>
  7085. }
  7086. }
  7087. }
  7088. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
  7089. 8002c5c: 687b ldr r3, [r7, #4]
  7090. 8002c5e: 685b ldr r3, [r3, #4]
  7091. 8002c60: 2b03 cmp r3, #3
  7092. 8002c62: d112 bne.n 8002c8a <HAL_RCC_ClockConfig+0x14e>
  7093. {
  7094. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  7095. 8002c64: e00a b.n 8002c7c <HAL_RCC_ClockConfig+0x140>
  7096. {
  7097. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  7098. 8002c66: f7fe fd79 bl 800175c <HAL_GetTick>
  7099. 8002c6a: 4602 mov r2, r0
  7100. 8002c6c: 68fb ldr r3, [r7, #12]
  7101. 8002c6e: 1ad3 subs r3, r2, r3
  7102. 8002c70: f241 3288 movw r2, #5000 ; 0x1388
  7103. 8002c74: 4293 cmp r3, r2
  7104. 8002c76: d901 bls.n 8002c7c <HAL_RCC_ClockConfig+0x140>
  7105. {
  7106. return HAL_TIMEOUT;
  7107. 8002c78: 2303 movs r3, #3
  7108. 8002c7a: e084 b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7109. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
  7110. 8002c7c: 4b45 ldr r3, [pc, #276] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7111. 8002c7e: 689b ldr r3, [r3, #8]
  7112. 8002c80: f003 030c and.w r3, r3, #12
  7113. 8002c84: 2b0c cmp r3, #12
  7114. 8002c86: d1ee bne.n 8002c66 <HAL_RCC_ClockConfig+0x12a>
  7115. 8002c88: e027 b.n 8002cda <HAL_RCC_ClockConfig+0x19e>
  7116. }
  7117. }
  7118. }
  7119. else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
  7120. 8002c8a: 687b ldr r3, [r7, #4]
  7121. 8002c8c: 685b ldr r3, [r3, #4]
  7122. 8002c8e: 2b01 cmp r3, #1
  7123. 8002c90: d11d bne.n 8002cce <HAL_RCC_ClockConfig+0x192>
  7124. {
  7125. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
  7126. 8002c92: e00a b.n 8002caa <HAL_RCC_ClockConfig+0x16e>
  7127. {
  7128. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  7129. 8002c94: f7fe fd62 bl 800175c <HAL_GetTick>
  7130. 8002c98: 4602 mov r2, r0
  7131. 8002c9a: 68fb ldr r3, [r7, #12]
  7132. 8002c9c: 1ad3 subs r3, r2, r3
  7133. 8002c9e: f241 3288 movw r2, #5000 ; 0x1388
  7134. 8002ca2: 4293 cmp r3, r2
  7135. 8002ca4: d901 bls.n 8002caa <HAL_RCC_ClockConfig+0x16e>
  7136. {
  7137. return HAL_TIMEOUT;
  7138. 8002ca6: 2303 movs r3, #3
  7139. 8002ca8: e06d b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7140. while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
  7141. 8002caa: 4b3a ldr r3, [pc, #232] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7142. 8002cac: 689b ldr r3, [r3, #8]
  7143. 8002cae: f003 030c and.w r3, r3, #12
  7144. 8002cb2: 2b04 cmp r3, #4
  7145. 8002cb4: d1ee bne.n 8002c94 <HAL_RCC_ClockConfig+0x158>
  7146. 8002cb6: e010 b.n 8002cda <HAL_RCC_ClockConfig+0x19e>
  7147. }
  7148. else
  7149. {
  7150. while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
  7151. {
  7152. if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
  7153. 8002cb8: f7fe fd50 bl 800175c <HAL_GetTick>
  7154. 8002cbc: 4602 mov r2, r0
  7155. 8002cbe: 68fb ldr r3, [r7, #12]
  7156. 8002cc0: 1ad3 subs r3, r2, r3
  7157. 8002cc2: f241 3288 movw r2, #5000 ; 0x1388
  7158. 8002cc6: 4293 cmp r3, r2
  7159. 8002cc8: d901 bls.n 8002cce <HAL_RCC_ClockConfig+0x192>
  7160. {
  7161. return HAL_TIMEOUT;
  7162. 8002cca: 2303 movs r3, #3
  7163. 8002ccc: e05b b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7164. while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI)
  7165. 8002cce: 4b31 ldr r3, [pc, #196] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7166. 8002cd0: 689b ldr r3, [r3, #8]
  7167. 8002cd2: f003 030c and.w r3, r3, #12
  7168. 8002cd6: 2b00 cmp r3, #0
  7169. 8002cd8: d1ee bne.n 8002cb8 <HAL_RCC_ClockConfig+0x17c>
  7170. }
  7171. }
  7172. }
  7173. }
  7174. /* Decreasing the number of wait states because of lower CPU frequency */
  7175. if(FLatency < __HAL_FLASH_GET_LATENCY())
  7176. 8002cda: 4b2d ldr r3, [pc, #180] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  7177. 8002cdc: 681b ldr r3, [r3, #0]
  7178. 8002cde: f003 0301 and.w r3, r3, #1
  7179. 8002ce2: 683a ldr r2, [r7, #0]
  7180. 8002ce4: 429a cmp r2, r3
  7181. 8002ce6: d219 bcs.n 8002d1c <HAL_RCC_ClockConfig+0x1e0>
  7182. {
  7183. /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
  7184. __HAL_FLASH_SET_LATENCY(FLatency);
  7185. 8002ce8: 683b ldr r3, [r7, #0]
  7186. 8002cea: 2b01 cmp r3, #1
  7187. 8002cec: d105 bne.n 8002cfa <HAL_RCC_ClockConfig+0x1be>
  7188. 8002cee: 4b28 ldr r3, [pc, #160] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  7189. 8002cf0: 681b ldr r3, [r3, #0]
  7190. 8002cf2: 4a27 ldr r2, [pc, #156] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  7191. 8002cf4: f043 0304 orr.w r3, r3, #4
  7192. 8002cf8: 6013 str r3, [r2, #0]
  7193. 8002cfa: 4b25 ldr r3, [pc, #148] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  7194. 8002cfc: 681b ldr r3, [r3, #0]
  7195. 8002cfe: f023 0201 bic.w r2, r3, #1
  7196. 8002d02: 4923 ldr r1, [pc, #140] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  7197. 8002d04: 683b ldr r3, [r7, #0]
  7198. 8002d06: 4313 orrs r3, r2
  7199. 8002d08: 600b str r3, [r1, #0]
  7200. /* Check that the new number of wait states is taken into account to access the Flash
  7201. memory by reading the FLASH_ACR register */
  7202. if(__HAL_FLASH_GET_LATENCY() != FLatency)
  7203. 8002d0a: 4b21 ldr r3, [pc, #132] ; (8002d90 <HAL_RCC_ClockConfig+0x254>)
  7204. 8002d0c: 681b ldr r3, [r3, #0]
  7205. 8002d0e: f003 0301 and.w r3, r3, #1
  7206. 8002d12: 683a ldr r2, [r7, #0]
  7207. 8002d14: 429a cmp r2, r3
  7208. 8002d16: d001 beq.n 8002d1c <HAL_RCC_ClockConfig+0x1e0>
  7209. {
  7210. return HAL_ERROR;
  7211. 8002d18: 2301 movs r3, #1
  7212. 8002d1a: e034 b.n 8002d86 <HAL_RCC_ClockConfig+0x24a>
  7213. }
  7214. }
  7215. /*-------------------------- PCLK1 Configuration ---------------------------*/
  7216. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  7217. 8002d1c: 687b ldr r3, [r7, #4]
  7218. 8002d1e: 681b ldr r3, [r3, #0]
  7219. 8002d20: f003 0304 and.w r3, r3, #4
  7220. 8002d24: 2b00 cmp r3, #0
  7221. 8002d26: d008 beq.n 8002d3a <HAL_RCC_ClockConfig+0x1fe>
  7222. {
  7223. assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
  7224. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
  7225. 8002d28: 4b1a ldr r3, [pc, #104] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7226. 8002d2a: 689b ldr r3, [r3, #8]
  7227. 8002d2c: f423 62e0 bic.w r2, r3, #1792 ; 0x700
  7228. 8002d30: 687b ldr r3, [r7, #4]
  7229. 8002d32: 68db ldr r3, [r3, #12]
  7230. 8002d34: 4917 ldr r1, [pc, #92] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7231. 8002d36: 4313 orrs r3, r2
  7232. 8002d38: 608b str r3, [r1, #8]
  7233. }
  7234. /*-------------------------- PCLK2 Configuration ---------------------------*/
  7235. if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  7236. 8002d3a: 687b ldr r3, [r7, #4]
  7237. 8002d3c: 681b ldr r3, [r3, #0]
  7238. 8002d3e: f003 0308 and.w r3, r3, #8
  7239. 8002d42: 2b00 cmp r3, #0
  7240. 8002d44: d009 beq.n 8002d5a <HAL_RCC_ClockConfig+0x21e>
  7241. {
  7242. assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
  7243. MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
  7244. 8002d46: 4b13 ldr r3, [pc, #76] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7245. 8002d48: 689b ldr r3, [r3, #8]
  7246. 8002d4a: f423 5260 bic.w r2, r3, #14336 ; 0x3800
  7247. 8002d4e: 687b ldr r3, [r7, #4]
  7248. 8002d50: 691b ldr r3, [r3, #16]
  7249. 8002d52: 00db lsls r3, r3, #3
  7250. 8002d54: 490f ldr r1, [pc, #60] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7251. 8002d56: 4313 orrs r3, r2
  7252. 8002d58: 608b str r3, [r1, #8]
  7253. }
  7254. /* Update the SystemCoreClock global variable */
  7255. SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
  7256. 8002d5a: f000 f823 bl 8002da4 <HAL_RCC_GetSysClockFreq>
  7257. 8002d5e: 4601 mov r1, r0
  7258. 8002d60: 4b0c ldr r3, [pc, #48] ; (8002d94 <HAL_RCC_ClockConfig+0x258>)
  7259. 8002d62: 689b ldr r3, [r3, #8]
  7260. 8002d64: 091b lsrs r3, r3, #4
  7261. 8002d66: f003 030f and.w r3, r3, #15
  7262. 8002d6a: 4a0b ldr r2, [pc, #44] ; (8002d98 <HAL_RCC_ClockConfig+0x25c>)
  7263. 8002d6c: 5cd3 ldrb r3, [r2, r3]
  7264. 8002d6e: fa21 f303 lsr.w r3, r1, r3
  7265. 8002d72: 4a0a ldr r2, [pc, #40] ; (8002d9c <HAL_RCC_ClockConfig+0x260>)
  7266. 8002d74: 6013 str r3, [r2, #0]
  7267. /* Configure the source of time base considering new system clocks settings*/
  7268. status = HAL_InitTick(uwTickPrio);
  7269. 8002d76: 4b0a ldr r3, [pc, #40] ; (8002da0 <HAL_RCC_ClockConfig+0x264>)
  7270. 8002d78: 681b ldr r3, [r3, #0]
  7271. 8002d7a: 4618 mov r0, r3
  7272. 8002d7c: f7fe fca2 bl 80016c4 <HAL_InitTick>
  7273. 8002d80: 4603 mov r3, r0
  7274. 8002d82: 72fb strb r3, [r7, #11]
  7275. return status;
  7276. 8002d84: 7afb ldrb r3, [r7, #11]
  7277. }
  7278. 8002d86: 4618 mov r0, r3
  7279. 8002d88: 3710 adds r7, #16
  7280. 8002d8a: 46bd mov sp, r7
  7281. 8002d8c: bd80 pop {r7, pc}
  7282. 8002d8e: bf00 nop
  7283. 8002d90: 40023c00 .word 0x40023c00
  7284. 8002d94: 40023800 .word 0x40023800
  7285. 8002d98: 08007b6c .word 0x08007b6c
  7286. 8002d9c: 20000004 .word 0x20000004
  7287. 8002da0: 20000008 .word 0x20000008
  7288. 08002da4 <HAL_RCC_GetSysClockFreq>:
  7289. * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  7290. *
  7291. * @retval SYSCLK frequency
  7292. */
  7293. uint32_t HAL_RCC_GetSysClockFreq(void)
  7294. {
  7295. 8002da4: b5f0 push {r4, r5, r6, r7, lr}
  7296. 8002da6: b087 sub sp, #28
  7297. 8002da8: af00 add r7, sp, #0
  7298. uint32_t tmpreg, pllm, plld, pllvco, msiclkrange, sysclockfreq;
  7299. tmpreg = RCC->CFGR;
  7300. 8002daa: 4b5f ldr r3, [pc, #380] ; (8002f28 <HAL_RCC_GetSysClockFreq+0x184>)
  7301. 8002dac: 689b ldr r3, [r3, #8]
  7302. 8002dae: 60fb str r3, [r7, #12]
  7303. /* Get SYSCLK source -------------------------------------------------------*/
  7304. switch (tmpreg & RCC_CFGR_SWS)
  7305. 8002db0: 68fb ldr r3, [r7, #12]
  7306. 8002db2: f003 030c and.w r3, r3, #12
  7307. 8002db6: 2b08 cmp r3, #8
  7308. 8002db8: d007 beq.n 8002dca <HAL_RCC_GetSysClockFreq+0x26>
  7309. 8002dba: 2b0c cmp r3, #12
  7310. 8002dbc: d008 beq.n 8002dd0 <HAL_RCC_GetSysClockFreq+0x2c>
  7311. 8002dbe: 2b04 cmp r3, #4
  7312. 8002dc0: f040 809f bne.w 8002f02 <HAL_RCC_GetSysClockFreq+0x15e>
  7313. {
  7314. case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
  7315. {
  7316. sysclockfreq = HSI_VALUE;
  7317. 8002dc4: 4b59 ldr r3, [pc, #356] ; (8002f2c <HAL_RCC_GetSysClockFreq+0x188>)
  7318. 8002dc6: 613b str r3, [r7, #16]
  7319. break;
  7320. 8002dc8: e0a9 b.n 8002f1e <HAL_RCC_GetSysClockFreq+0x17a>
  7321. }
  7322. case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
  7323. {
  7324. sysclockfreq = HSE_VALUE;
  7325. 8002dca: 4b59 ldr r3, [pc, #356] ; (8002f30 <HAL_RCC_GetSysClockFreq+0x18c>)
  7326. 8002dcc: 613b str r3, [r7, #16]
  7327. break;
  7328. 8002dce: e0a6 b.n 8002f1e <HAL_RCC_GetSysClockFreq+0x17a>
  7329. }
  7330. case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
  7331. {
  7332. pllm = PLLMulTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_Pos];
  7333. 8002dd0: 68fb ldr r3, [r7, #12]
  7334. 8002dd2: 0c9b lsrs r3, r3, #18
  7335. 8002dd4: f003 030f and.w r3, r3, #15
  7336. 8002dd8: 4a56 ldr r2, [pc, #344] ; (8002f34 <HAL_RCC_GetSysClockFreq+0x190>)
  7337. 8002dda: 5cd3 ldrb r3, [r2, r3]
  7338. 8002ddc: 60bb str r3, [r7, #8]
  7339. plld = ((uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> RCC_CFGR_PLLDIV_Pos) + 1U;
  7340. 8002dde: 68fb ldr r3, [r7, #12]
  7341. 8002de0: 0d9b lsrs r3, r3, #22
  7342. 8002de2: f003 0303 and.w r3, r3, #3
  7343. 8002de6: 3301 adds r3, #1
  7344. 8002de8: 607b str r3, [r7, #4]
  7345. if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
  7346. 8002dea: 4b4f ldr r3, [pc, #316] ; (8002f28 <HAL_RCC_GetSysClockFreq+0x184>)
  7347. 8002dec: 689b ldr r3, [r3, #8]
  7348. 8002dee: f403 3380 and.w r3, r3, #65536 ; 0x10000
  7349. 8002df2: 2b00 cmp r3, #0
  7350. 8002df4: d041 beq.n 8002e7a <HAL_RCC_GetSysClockFreq+0xd6>
  7351. {
  7352. /* HSE used as PLL clock source */
  7353. pllvco = (uint32_t)(((uint64_t)HSE_VALUE * (uint64_t)pllm) / (uint64_t)plld);
  7354. 8002df6: 68bb ldr r3, [r7, #8]
  7355. 8002df8: 461d mov r5, r3
  7356. 8002dfa: f04f 0600 mov.w r6, #0
  7357. 8002dfe: 4629 mov r1, r5
  7358. 8002e00: 4632 mov r2, r6
  7359. 8002e02: f04f 0300 mov.w r3, #0
  7360. 8002e06: f04f 0400 mov.w r4, #0
  7361. 8002e0a: 0154 lsls r4, r2, #5
  7362. 8002e0c: ea44 64d1 orr.w r4, r4, r1, lsr #27
  7363. 8002e10: 014b lsls r3, r1, #5
  7364. 8002e12: 4619 mov r1, r3
  7365. 8002e14: 4622 mov r2, r4
  7366. 8002e16: 1b49 subs r1, r1, r5
  7367. 8002e18: eb62 0206 sbc.w r2, r2, r6
  7368. 8002e1c: f04f 0300 mov.w r3, #0
  7369. 8002e20: f04f 0400 mov.w r4, #0
  7370. 8002e24: 0194 lsls r4, r2, #6
  7371. 8002e26: ea44 6491 orr.w r4, r4, r1, lsr #26
  7372. 8002e2a: 018b lsls r3, r1, #6
  7373. 8002e2c: 1a5b subs r3, r3, r1
  7374. 8002e2e: eb64 0402 sbc.w r4, r4, r2
  7375. 8002e32: f04f 0100 mov.w r1, #0
  7376. 8002e36: f04f 0200 mov.w r2, #0
  7377. 8002e3a: 00e2 lsls r2, r4, #3
  7378. 8002e3c: ea42 7253 orr.w r2, r2, r3, lsr #29
  7379. 8002e40: 00d9 lsls r1, r3, #3
  7380. 8002e42: 460b mov r3, r1
  7381. 8002e44: 4614 mov r4, r2
  7382. 8002e46: 195b adds r3, r3, r5
  7383. 8002e48: eb44 0406 adc.w r4, r4, r6
  7384. 8002e4c: f04f 0100 mov.w r1, #0
  7385. 8002e50: f04f 0200 mov.w r2, #0
  7386. 8002e54: 0262 lsls r2, r4, #9
  7387. 8002e56: ea42 52d3 orr.w r2, r2, r3, lsr #23
  7388. 8002e5a: 0259 lsls r1, r3, #9
  7389. 8002e5c: 460b mov r3, r1
  7390. 8002e5e: 4614 mov r4, r2
  7391. 8002e60: 4618 mov r0, r3
  7392. 8002e62: 4621 mov r1, r4
  7393. 8002e64: 687b ldr r3, [r7, #4]
  7394. 8002e66: f04f 0400 mov.w r4, #0
  7395. 8002e6a: 461a mov r2, r3
  7396. 8002e6c: 4623 mov r3, r4
  7397. 8002e6e: f7fd f98d bl 800018c <__aeabi_uldivmod>
  7398. 8002e72: 4603 mov r3, r0
  7399. 8002e74: 460c mov r4, r1
  7400. 8002e76: 617b str r3, [r7, #20]
  7401. 8002e78: e040 b.n 8002efc <HAL_RCC_GetSysClockFreq+0x158>
  7402. }
  7403. else
  7404. {
  7405. /* HSI used as PLL clock source */
  7406. pllvco = (uint32_t)(((uint64_t)HSI_VALUE * (uint64_t)pllm) / (uint64_t)plld);
  7407. 8002e7a: 68bb ldr r3, [r7, #8]
  7408. 8002e7c: 461d mov r5, r3
  7409. 8002e7e: f04f 0600 mov.w r6, #0
  7410. 8002e82: 4629 mov r1, r5
  7411. 8002e84: 4632 mov r2, r6
  7412. 8002e86: f04f 0300 mov.w r3, #0
  7413. 8002e8a: f04f 0400 mov.w r4, #0
  7414. 8002e8e: 0154 lsls r4, r2, #5
  7415. 8002e90: ea44 64d1 orr.w r4, r4, r1, lsr #27
  7416. 8002e94: 014b lsls r3, r1, #5
  7417. 8002e96: 4619 mov r1, r3
  7418. 8002e98: 4622 mov r2, r4
  7419. 8002e9a: 1b49 subs r1, r1, r5
  7420. 8002e9c: eb62 0206 sbc.w r2, r2, r6
  7421. 8002ea0: f04f 0300 mov.w r3, #0
  7422. 8002ea4: f04f 0400 mov.w r4, #0
  7423. 8002ea8: 0194 lsls r4, r2, #6
  7424. 8002eaa: ea44 6491 orr.w r4, r4, r1, lsr #26
  7425. 8002eae: 018b lsls r3, r1, #6
  7426. 8002eb0: 1a5b subs r3, r3, r1
  7427. 8002eb2: eb64 0402 sbc.w r4, r4, r2
  7428. 8002eb6: f04f 0100 mov.w r1, #0
  7429. 8002eba: f04f 0200 mov.w r2, #0
  7430. 8002ebe: 00e2 lsls r2, r4, #3
  7431. 8002ec0: ea42 7253 orr.w r2, r2, r3, lsr #29
  7432. 8002ec4: 00d9 lsls r1, r3, #3
  7433. 8002ec6: 460b mov r3, r1
  7434. 8002ec8: 4614 mov r4, r2
  7435. 8002eca: 195b adds r3, r3, r5
  7436. 8002ecc: eb44 0406 adc.w r4, r4, r6
  7437. 8002ed0: f04f 0100 mov.w r1, #0
  7438. 8002ed4: f04f 0200 mov.w r2, #0
  7439. 8002ed8: 02a2 lsls r2, r4, #10
  7440. 8002eda: ea42 5293 orr.w r2, r2, r3, lsr #22
  7441. 8002ede: 0299 lsls r1, r3, #10
  7442. 8002ee0: 460b mov r3, r1
  7443. 8002ee2: 4614 mov r4, r2
  7444. 8002ee4: 4618 mov r0, r3
  7445. 8002ee6: 4621 mov r1, r4
  7446. 8002ee8: 687b ldr r3, [r7, #4]
  7447. 8002eea: f04f 0400 mov.w r4, #0
  7448. 8002eee: 461a mov r2, r3
  7449. 8002ef0: 4623 mov r3, r4
  7450. 8002ef2: f7fd f94b bl 800018c <__aeabi_uldivmod>
  7451. 8002ef6: 4603 mov r3, r0
  7452. 8002ef8: 460c mov r4, r1
  7453. 8002efa: 617b str r3, [r7, #20]
  7454. }
  7455. sysclockfreq = pllvco;
  7456. 8002efc: 697b ldr r3, [r7, #20]
  7457. 8002efe: 613b str r3, [r7, #16]
  7458. break;
  7459. 8002f00: e00d b.n 8002f1e <HAL_RCC_GetSysClockFreq+0x17a>
  7460. }
  7461. case RCC_SYSCLKSOURCE_STATUS_MSI: /* MSI used as system clock source */
  7462. default: /* MSI used as system clock */
  7463. {
  7464. msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> RCC_ICSCR_MSIRANGE_Pos;
  7465. 8002f02: 4b09 ldr r3, [pc, #36] ; (8002f28 <HAL_RCC_GetSysClockFreq+0x184>)
  7466. 8002f04: 685b ldr r3, [r3, #4]
  7467. 8002f06: 0b5b lsrs r3, r3, #13
  7468. 8002f08: f003 0307 and.w r3, r3, #7
  7469. 8002f0c: 603b str r3, [r7, #0]
  7470. sysclockfreq = (32768U * (1UL << (msiclkrange + 1U)));
  7471. 8002f0e: 683b ldr r3, [r7, #0]
  7472. 8002f10: 3301 adds r3, #1
  7473. 8002f12: f44f 4200 mov.w r2, #32768 ; 0x8000
  7474. 8002f16: fa02 f303 lsl.w r3, r2, r3
  7475. 8002f1a: 613b str r3, [r7, #16]
  7476. break;
  7477. 8002f1c: bf00 nop
  7478. }
  7479. }
  7480. return sysclockfreq;
  7481. 8002f1e: 693b ldr r3, [r7, #16]
  7482. }
  7483. 8002f20: 4618 mov r0, r3
  7484. 8002f22: 371c adds r7, #28
  7485. 8002f24: 46bd mov sp, r7
  7486. 8002f26: bdf0 pop {r4, r5, r6, r7, pc}
  7487. 8002f28: 40023800 .word 0x40023800
  7488. 8002f2c: 00f42400 .word 0x00f42400
  7489. 8002f30: 007a1200 .word 0x007a1200
  7490. 8002f34: 08007b60 .word 0x08007b60
  7491. 08002f38 <HAL_RCC_GetHCLKFreq>:
  7492. * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  7493. * and updated within this function
  7494. * @retval HCLK frequency
  7495. */
  7496. uint32_t HAL_RCC_GetHCLKFreq(void)
  7497. {
  7498. 8002f38: b480 push {r7}
  7499. 8002f3a: af00 add r7, sp, #0
  7500. return SystemCoreClock;
  7501. 8002f3c: 4b02 ldr r3, [pc, #8] ; (8002f48 <HAL_RCC_GetHCLKFreq+0x10>)
  7502. 8002f3e: 681b ldr r3, [r3, #0]
  7503. }
  7504. 8002f40: 4618 mov r0, r3
  7505. 8002f42: 46bd mov sp, r7
  7506. 8002f44: bc80 pop {r7}
  7507. 8002f46: 4770 bx lr
  7508. 8002f48: 20000004 .word 0x20000004
  7509. 08002f4c <HAL_RCC_GetPCLK1Freq>:
  7510. * @note Each time PCLK1 changes, this function must be called to update the
  7511. * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  7512. * @retval PCLK1 frequency
  7513. */
  7514. uint32_t HAL_RCC_GetPCLK1Freq(void)
  7515. {
  7516. 8002f4c: b580 push {r7, lr}
  7517. 8002f4e: af00 add r7, sp, #0
  7518. /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  7519. return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
  7520. 8002f50: f7ff fff2 bl 8002f38 <HAL_RCC_GetHCLKFreq>
  7521. 8002f54: 4601 mov r1, r0
  7522. 8002f56: 4b05 ldr r3, [pc, #20] ; (8002f6c <HAL_RCC_GetPCLK1Freq+0x20>)
  7523. 8002f58: 689b ldr r3, [r3, #8]
  7524. 8002f5a: 0a1b lsrs r3, r3, #8
  7525. 8002f5c: f003 0307 and.w r3, r3, #7
  7526. 8002f60: 4a03 ldr r2, [pc, #12] ; (8002f70 <HAL_RCC_GetPCLK1Freq+0x24>)
  7527. 8002f62: 5cd3 ldrb r3, [r2, r3]
  7528. 8002f64: fa21 f303 lsr.w r3, r1, r3
  7529. }
  7530. 8002f68: 4618 mov r0, r3
  7531. 8002f6a: bd80 pop {r7, pc}
  7532. 8002f6c: 40023800 .word 0x40023800
  7533. 8002f70: 08007b7c .word 0x08007b7c
  7534. 08002f74 <HAL_RCC_GetPCLK2Freq>:
  7535. * @note Each time PCLK2 changes, this function must be called to update the
  7536. * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  7537. * @retval PCLK2 frequency
  7538. */
  7539. uint32_t HAL_RCC_GetPCLK2Freq(void)
  7540. {
  7541. 8002f74: b580 push {r7, lr}
  7542. 8002f76: af00 add r7, sp, #0
  7543. /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  7544. return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]);
  7545. 8002f78: f7ff ffde bl 8002f38 <HAL_RCC_GetHCLKFreq>
  7546. 8002f7c: 4601 mov r1, r0
  7547. 8002f7e: 4b05 ldr r3, [pc, #20] ; (8002f94 <HAL_RCC_GetPCLK2Freq+0x20>)
  7548. 8002f80: 689b ldr r3, [r3, #8]
  7549. 8002f82: 0adb lsrs r3, r3, #11
  7550. 8002f84: f003 0307 and.w r3, r3, #7
  7551. 8002f88: 4a03 ldr r2, [pc, #12] ; (8002f98 <HAL_RCC_GetPCLK2Freq+0x24>)
  7552. 8002f8a: 5cd3 ldrb r3, [r2, r3]
  7553. 8002f8c: fa21 f303 lsr.w r3, r1, r3
  7554. }
  7555. 8002f90: 4618 mov r0, r3
  7556. 8002f92: bd80 pop {r7, pc}
  7557. 8002f94: 40023800 .word 0x40023800
  7558. 8002f98: 08007b7c .word 0x08007b7c
  7559. 08002f9c <RCC_SetFlashLatencyFromMSIRange>:
  7560. voltage range
  7561. * @param MSIrange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_6
  7562. * @retval HAL status
  7563. */
  7564. static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSIrange)
  7565. {
  7566. 8002f9c: b480 push {r7}
  7567. 8002f9e: b087 sub sp, #28
  7568. 8002fa0: af00 add r7, sp, #0
  7569. 8002fa2: 6078 str r0, [r7, #4]
  7570. uint32_t vos;
  7571. uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
  7572. 8002fa4: 2300 movs r3, #0
  7573. 8002fa6: 613b str r3, [r7, #16]
  7574. /* HCLK can reach 4 MHz only if AHB prescaler = 1 */
  7575. if (READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)
  7576. 8002fa8: 4b29 ldr r3, [pc, #164] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7577. 8002faa: 689b ldr r3, [r3, #8]
  7578. 8002fac: f003 03f0 and.w r3, r3, #240 ; 0xf0
  7579. 8002fb0: 2b00 cmp r3, #0
  7580. 8002fb2: d12c bne.n 800300e <RCC_SetFlashLatencyFromMSIRange+0x72>
  7581. {
  7582. if(__HAL_RCC_PWR_IS_CLK_ENABLED())
  7583. 8002fb4: 4b26 ldr r3, [pc, #152] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7584. 8002fb6: 6a5b ldr r3, [r3, #36] ; 0x24
  7585. 8002fb8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  7586. 8002fbc: 2b00 cmp r3, #0
  7587. 8002fbe: d005 beq.n 8002fcc <RCC_SetFlashLatencyFromMSIRange+0x30>
  7588. {
  7589. vos = READ_BIT(PWR->CR, PWR_CR_VOS);
  7590. 8002fc0: 4b24 ldr r3, [pc, #144] ; (8003054 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
  7591. 8002fc2: 681b ldr r3, [r3, #0]
  7592. 8002fc4: f403 53c0 and.w r3, r3, #6144 ; 0x1800
  7593. 8002fc8: 617b str r3, [r7, #20]
  7594. 8002fca: e016 b.n 8002ffa <RCC_SetFlashLatencyFromMSIRange+0x5e>
  7595. }
  7596. else
  7597. {
  7598. __HAL_RCC_PWR_CLK_ENABLE();
  7599. 8002fcc: 4b20 ldr r3, [pc, #128] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7600. 8002fce: 6a5b ldr r3, [r3, #36] ; 0x24
  7601. 8002fd0: 4a1f ldr r2, [pc, #124] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7602. 8002fd2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
  7603. 8002fd6: 6253 str r3, [r2, #36] ; 0x24
  7604. 8002fd8: 4b1d ldr r3, [pc, #116] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7605. 8002fda: 6a5b ldr r3, [r3, #36] ; 0x24
  7606. 8002fdc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
  7607. 8002fe0: 60fb str r3, [r7, #12]
  7608. 8002fe2: 68fb ldr r3, [r7, #12]
  7609. vos = READ_BIT(PWR->CR, PWR_CR_VOS);
  7610. 8002fe4: 4b1b ldr r3, [pc, #108] ; (8003054 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
  7611. 8002fe6: 681b ldr r3, [r3, #0]
  7612. 8002fe8: f403 53c0 and.w r3, r3, #6144 ; 0x1800
  7613. 8002fec: 617b str r3, [r7, #20]
  7614. __HAL_RCC_PWR_CLK_DISABLE();
  7615. 8002fee: 4b18 ldr r3, [pc, #96] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7616. 8002ff0: 6a5b ldr r3, [r3, #36] ; 0x24
  7617. 8002ff2: 4a17 ldr r2, [pc, #92] ; (8003050 <RCC_SetFlashLatencyFromMSIRange+0xb4>)
  7618. 8002ff4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
  7619. 8002ff8: 6253 str r3, [r2, #36] ; 0x24
  7620. }
  7621. /* Check if need to set latency 1 only for Range 3 & HCLK = 4MHz */
  7622. if((vos == PWR_REGULATOR_VOLTAGE_SCALE3) && (MSIrange == RCC_MSIRANGE_6))
  7623. 8002ffa: 697b ldr r3, [r7, #20]
  7624. 8002ffc: f5b3 5fc0 cmp.w r3, #6144 ; 0x1800
  7625. 8003000: d105 bne.n 800300e <RCC_SetFlashLatencyFromMSIRange+0x72>
  7626. 8003002: 687b ldr r3, [r7, #4]
  7627. 8003004: f5b3 4f40 cmp.w r3, #49152 ; 0xc000
  7628. 8003008: d101 bne.n 800300e <RCC_SetFlashLatencyFromMSIRange+0x72>
  7629. {
  7630. latency = FLASH_LATENCY_1; /* 1WS */
  7631. 800300a: 2301 movs r3, #1
  7632. 800300c: 613b str r3, [r7, #16]
  7633. }
  7634. }
  7635. __HAL_FLASH_SET_LATENCY(latency);
  7636. 800300e: 693b ldr r3, [r7, #16]
  7637. 8003010: 2b01 cmp r3, #1
  7638. 8003012: d105 bne.n 8003020 <RCC_SetFlashLatencyFromMSIRange+0x84>
  7639. 8003014: 4b10 ldr r3, [pc, #64] ; (8003058 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
  7640. 8003016: 681b ldr r3, [r3, #0]
  7641. 8003018: 4a0f ldr r2, [pc, #60] ; (8003058 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
  7642. 800301a: f043 0304 orr.w r3, r3, #4
  7643. 800301e: 6013 str r3, [r2, #0]
  7644. 8003020: 4b0d ldr r3, [pc, #52] ; (8003058 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
  7645. 8003022: 681b ldr r3, [r3, #0]
  7646. 8003024: f023 0201 bic.w r2, r3, #1
  7647. 8003028: 490b ldr r1, [pc, #44] ; (8003058 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
  7648. 800302a: 693b ldr r3, [r7, #16]
  7649. 800302c: 4313 orrs r3, r2
  7650. 800302e: 600b str r3, [r1, #0]
  7651. /* Check that the new number of wait states is taken into account to access the Flash
  7652. memory by reading the FLASH_ACR register */
  7653. if(__HAL_FLASH_GET_LATENCY() != latency)
  7654. 8003030: 4b09 ldr r3, [pc, #36] ; (8003058 <RCC_SetFlashLatencyFromMSIRange+0xbc>)
  7655. 8003032: 681b ldr r3, [r3, #0]
  7656. 8003034: f003 0301 and.w r3, r3, #1
  7657. 8003038: 693a ldr r2, [r7, #16]
  7658. 800303a: 429a cmp r2, r3
  7659. 800303c: d001 beq.n 8003042 <RCC_SetFlashLatencyFromMSIRange+0xa6>
  7660. {
  7661. return HAL_ERROR;
  7662. 800303e: 2301 movs r3, #1
  7663. 8003040: e000 b.n 8003044 <RCC_SetFlashLatencyFromMSIRange+0xa8>
  7664. }
  7665. return HAL_OK;
  7666. 8003042: 2300 movs r3, #0
  7667. }
  7668. 8003044: 4618 mov r0, r3
  7669. 8003046: 371c adds r7, #28
  7670. 8003048: 46bd mov sp, r7
  7671. 800304a: bc80 pop {r7}
  7672. 800304c: 4770 bx lr
  7673. 800304e: bf00 nop
  7674. 8003050: 40023800 .word 0x40023800
  7675. 8003054: 40007000 .word 0x40007000
  7676. 8003058: 40023c00 .word 0x40023c00
  7677. 0800305c <HAL_SPI_Init>:
  7678. * @param hspi pointer to a SPI_HandleTypeDef structure that contains
  7679. * the configuration information for SPI module.
  7680. * @retval HAL status
  7681. */
  7682. HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
  7683. {
  7684. 800305c: b580 push {r7, lr}
  7685. 800305e: b082 sub sp, #8
  7686. 8003060: af00 add r7, sp, #0
  7687. 8003062: 6078 str r0, [r7, #4]
  7688. /* Check the SPI handle allocation */
  7689. if (hspi == NULL)
  7690. 8003064: 687b ldr r3, [r7, #4]
  7691. 8003066: 2b00 cmp r3, #0
  7692. 8003068: d101 bne.n 800306e <HAL_SPI_Init+0x12>
  7693. {
  7694. return HAL_ERROR;
  7695. 800306a: 2301 movs r3, #1
  7696. 800306c: e07b b.n 8003166 <HAL_SPI_Init+0x10a>
  7697. assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  7698. assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  7699. /* TI mode is not supported on all devices in stm32l1xx serie.
  7700. TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
  7701. assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  7702. if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
  7703. 800306e: 687b ldr r3, [r7, #4]
  7704. 8003070: 6a5b ldr r3, [r3, #36] ; 0x24
  7705. 8003072: 2b00 cmp r3, #0
  7706. 8003074: d108 bne.n 8003088 <HAL_SPI_Init+0x2c>
  7707. {
  7708. assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
  7709. assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
  7710. if (hspi->Init.Mode == SPI_MODE_MASTER)
  7711. 8003076: 687b ldr r3, [r7, #4]
  7712. 8003078: 685b ldr r3, [r3, #4]
  7713. 800307a: f5b3 7f82 cmp.w r3, #260 ; 0x104
  7714. 800307e: d009 beq.n 8003094 <HAL_SPI_Init+0x38>
  7715. assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  7716. }
  7717. else
  7718. {
  7719. /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
  7720. hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
  7721. 8003080: 687b ldr r3, [r7, #4]
  7722. 8003082: 2200 movs r2, #0
  7723. 8003084: 61da str r2, [r3, #28]
  7724. 8003086: e005 b.n 8003094 <HAL_SPI_Init+0x38>
  7725. else
  7726. {
  7727. assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  7728. /* Force polarity and phase to TI protocaol requirements */
  7729. hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
  7730. 8003088: 687b ldr r3, [r7, #4]
  7731. 800308a: 2200 movs r2, #0
  7732. 800308c: 611a str r2, [r3, #16]
  7733. hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
  7734. 800308e: 687b ldr r3, [r7, #4]
  7735. 8003090: 2200 movs r2, #0
  7736. 8003092: 615a str r2, [r3, #20]
  7737. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  7738. {
  7739. assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
  7740. }
  7741. #else
  7742. hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
  7743. 8003094: 687b ldr r3, [r7, #4]
  7744. 8003096: 2200 movs r2, #0
  7745. 8003098: 629a str r2, [r3, #40] ; 0x28
  7746. #endif /* USE_SPI_CRC */
  7747. if (hspi->State == HAL_SPI_STATE_RESET)
  7748. 800309a: 687b ldr r3, [r7, #4]
  7749. 800309c: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
  7750. 80030a0: b2db uxtb r3, r3
  7751. 80030a2: 2b00 cmp r3, #0
  7752. 80030a4: d106 bne.n 80030b4 <HAL_SPI_Init+0x58>
  7753. {
  7754. /* Allocate lock resource and initialize it */
  7755. hspi->Lock = HAL_UNLOCKED;
  7756. 80030a6: 687b ldr r3, [r7, #4]
  7757. 80030a8: 2200 movs r2, #0
  7758. 80030aa: f883 2050 strb.w r2, [r3, #80] ; 0x50
  7759. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  7760. hspi->MspInitCallback(hspi);
  7761. #else
  7762. /* Init the low level hardware : GPIO, CLOCK, NVIC... */
  7763. HAL_SPI_MspInit(hspi);
  7764. 80030ae: 6878 ldr r0, [r7, #4]
  7765. 80030b0: f7fe f9bc bl 800142c <HAL_SPI_MspInit>
  7766. #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  7767. }
  7768. hspi->State = HAL_SPI_STATE_BUSY;
  7769. 80030b4: 687b ldr r3, [r7, #4]
  7770. 80030b6: 2202 movs r2, #2
  7771. 80030b8: f883 2051 strb.w r2, [r3, #81] ; 0x51
  7772. /* Disable the selected SPI peripheral */
  7773. __HAL_SPI_DISABLE(hspi);
  7774. 80030bc: 687b ldr r3, [r7, #4]
  7775. 80030be: 681b ldr r3, [r3, #0]
  7776. 80030c0: 681a ldr r2, [r3, #0]
  7777. 80030c2: 687b ldr r3, [r7, #4]
  7778. 80030c4: 681b ldr r3, [r3, #0]
  7779. 80030c6: f022 0240 bic.w r2, r2, #64 ; 0x40
  7780. 80030ca: 601a str r2, [r3, #0]
  7781. /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  7782. /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
  7783. Communication speed, First bit and CRC calculation state */
  7784. WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
  7785. 80030cc: 687b ldr r3, [r7, #4]
  7786. 80030ce: 685b ldr r3, [r3, #4]
  7787. 80030d0: f403 7282 and.w r2, r3, #260 ; 0x104
  7788. 80030d4: 687b ldr r3, [r7, #4]
  7789. 80030d6: 689b ldr r3, [r3, #8]
  7790. 80030d8: f403 4304 and.w r3, r3, #33792 ; 0x8400
  7791. 80030dc: 431a orrs r2, r3
  7792. 80030de: 687b ldr r3, [r7, #4]
  7793. 80030e0: 68db ldr r3, [r3, #12]
  7794. 80030e2: f403 6300 and.w r3, r3, #2048 ; 0x800
  7795. 80030e6: 431a orrs r2, r3
  7796. 80030e8: 687b ldr r3, [r7, #4]
  7797. 80030ea: 691b ldr r3, [r3, #16]
  7798. 80030ec: f003 0302 and.w r3, r3, #2
  7799. 80030f0: 431a orrs r2, r3
  7800. 80030f2: 687b ldr r3, [r7, #4]
  7801. 80030f4: 695b ldr r3, [r3, #20]
  7802. 80030f6: f003 0301 and.w r3, r3, #1
  7803. 80030fa: 431a orrs r2, r3
  7804. 80030fc: 687b ldr r3, [r7, #4]
  7805. 80030fe: 699b ldr r3, [r3, #24]
  7806. 8003100: f403 7300 and.w r3, r3, #512 ; 0x200
  7807. 8003104: 431a orrs r2, r3
  7808. 8003106: 687b ldr r3, [r7, #4]
  7809. 8003108: 69db ldr r3, [r3, #28]
  7810. 800310a: f003 0338 and.w r3, r3, #56 ; 0x38
  7811. 800310e: 431a orrs r2, r3
  7812. 8003110: 687b ldr r3, [r7, #4]
  7813. 8003112: 6a1b ldr r3, [r3, #32]
  7814. 8003114: f003 0380 and.w r3, r3, #128 ; 0x80
  7815. 8003118: ea42 0103 orr.w r1, r2, r3
  7816. 800311c: 687b ldr r3, [r7, #4]
  7817. 800311e: 6a9b ldr r3, [r3, #40] ; 0x28
  7818. 8003120: f403 5200 and.w r2, r3, #8192 ; 0x2000
  7819. 8003124: 687b ldr r3, [r7, #4]
  7820. 8003126: 681b ldr r3, [r3, #0]
  7821. 8003128: 430a orrs r2, r1
  7822. 800312a: 601a str r2, [r3, #0]
  7823. (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
  7824. (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
  7825. #if defined(SPI_CR2_FRF)
  7826. /* Configure : NSS management, TI Mode */
  7827. WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
  7828. 800312c: 687b ldr r3, [r7, #4]
  7829. 800312e: 699b ldr r3, [r3, #24]
  7830. 8003130: 0c1b lsrs r3, r3, #16
  7831. 8003132: f003 0104 and.w r1, r3, #4
  7832. 8003136: 687b ldr r3, [r7, #4]
  7833. 8003138: 6a5b ldr r3, [r3, #36] ; 0x24
  7834. 800313a: f003 0210 and.w r2, r3, #16
  7835. 800313e: 687b ldr r3, [r7, #4]
  7836. 8003140: 681b ldr r3, [r3, #0]
  7837. 8003142: 430a orrs r2, r1
  7838. 8003144: 605a str r2, [r3, #4]
  7839. }
  7840. #endif /* USE_SPI_CRC */
  7841. #if defined(SPI_I2SCFGR_I2SMOD)
  7842. /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  7843. CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
  7844. 8003146: 687b ldr r3, [r7, #4]
  7845. 8003148: 681b ldr r3, [r3, #0]
  7846. 800314a: 69da ldr r2, [r3, #28]
  7847. 800314c: 687b ldr r3, [r7, #4]
  7848. 800314e: 681b ldr r3, [r3, #0]
  7849. 8003150: f422 6200 bic.w r2, r2, #2048 ; 0x800
  7850. 8003154: 61da str r2, [r3, #28]
  7851. #endif /* SPI_I2SCFGR_I2SMOD */
  7852. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  7853. 8003156: 687b ldr r3, [r7, #4]
  7854. 8003158: 2200 movs r2, #0
  7855. 800315a: 655a str r2, [r3, #84] ; 0x54
  7856. hspi->State = HAL_SPI_STATE_READY;
  7857. 800315c: 687b ldr r3, [r7, #4]
  7858. 800315e: 2201 movs r2, #1
  7859. 8003160: f883 2051 strb.w r2, [r3, #81] ; 0x51
  7860. return HAL_OK;
  7861. 8003164: 2300 movs r3, #0
  7862. }
  7863. 8003166: 4618 mov r0, r3
  7864. 8003168: 3708 adds r7, #8
  7865. 800316a: 46bd mov sp, r7
  7866. 800316c: bd80 pop {r7, pc}
  7867. 0800316e <HAL_SPI_Transmit>:
  7868. * @param Size amount of data to be sent
  7869. * @param Timeout Timeout duration
  7870. * @retval HAL status
  7871. */
  7872. HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
  7873. {
  7874. 800316e: b580 push {r7, lr}
  7875. 8003170: b088 sub sp, #32
  7876. 8003172: af00 add r7, sp, #0
  7877. 8003174: 60f8 str r0, [r7, #12]
  7878. 8003176: 60b9 str r1, [r7, #8]
  7879. 8003178: 603b str r3, [r7, #0]
  7880. 800317a: 4613 mov r3, r2
  7881. 800317c: 80fb strh r3, [r7, #6]
  7882. uint32_t tickstart;
  7883. HAL_StatusTypeDef errorcode = HAL_OK;
  7884. 800317e: 2300 movs r3, #0
  7885. 8003180: 77fb strb r3, [r7, #31]
  7886. /* Check Direction parameter */
  7887. assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
  7888. /* Process Locked */
  7889. __HAL_LOCK(hspi);
  7890. 8003182: 68fb ldr r3, [r7, #12]
  7891. 8003184: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
  7892. 8003188: 2b01 cmp r3, #1
  7893. 800318a: d101 bne.n 8003190 <HAL_SPI_Transmit+0x22>
  7894. 800318c: 2302 movs r3, #2
  7895. 800318e: e126 b.n 80033de <HAL_SPI_Transmit+0x270>
  7896. 8003190: 68fb ldr r3, [r7, #12]
  7897. 8003192: 2201 movs r2, #1
  7898. 8003194: f883 2050 strb.w r2, [r3, #80] ; 0x50
  7899. /* Init tickstart for timeout management*/
  7900. tickstart = HAL_GetTick();
  7901. 8003198: f7fe fae0 bl 800175c <HAL_GetTick>
  7902. 800319c: 61b8 str r0, [r7, #24]
  7903. initial_TxXferCount = Size;
  7904. 800319e: 88fb ldrh r3, [r7, #6]
  7905. 80031a0: 82fb strh r3, [r7, #22]
  7906. if (hspi->State != HAL_SPI_STATE_READY)
  7907. 80031a2: 68fb ldr r3, [r7, #12]
  7908. 80031a4: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
  7909. 80031a8: b2db uxtb r3, r3
  7910. 80031aa: 2b01 cmp r3, #1
  7911. 80031ac: d002 beq.n 80031b4 <HAL_SPI_Transmit+0x46>
  7912. {
  7913. errorcode = HAL_BUSY;
  7914. 80031ae: 2302 movs r3, #2
  7915. 80031b0: 77fb strb r3, [r7, #31]
  7916. goto error;
  7917. 80031b2: e10b b.n 80033cc <HAL_SPI_Transmit+0x25e>
  7918. }
  7919. if ((pData == NULL) || (Size == 0U))
  7920. 80031b4: 68bb ldr r3, [r7, #8]
  7921. 80031b6: 2b00 cmp r3, #0
  7922. 80031b8: d002 beq.n 80031c0 <HAL_SPI_Transmit+0x52>
  7923. 80031ba: 88fb ldrh r3, [r7, #6]
  7924. 80031bc: 2b00 cmp r3, #0
  7925. 80031be: d102 bne.n 80031c6 <HAL_SPI_Transmit+0x58>
  7926. {
  7927. errorcode = HAL_ERROR;
  7928. 80031c0: 2301 movs r3, #1
  7929. 80031c2: 77fb strb r3, [r7, #31]
  7930. goto error;
  7931. 80031c4: e102 b.n 80033cc <HAL_SPI_Transmit+0x25e>
  7932. }
  7933. /* Set the transaction information */
  7934. hspi->State = HAL_SPI_STATE_BUSY_TX;
  7935. 80031c6: 68fb ldr r3, [r7, #12]
  7936. 80031c8: 2203 movs r2, #3
  7937. 80031ca: f883 2051 strb.w r2, [r3, #81] ; 0x51
  7938. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  7939. 80031ce: 68fb ldr r3, [r7, #12]
  7940. 80031d0: 2200 movs r2, #0
  7941. 80031d2: 655a str r2, [r3, #84] ; 0x54
  7942. hspi->pTxBuffPtr = (uint8_t *)pData;
  7943. 80031d4: 68fb ldr r3, [r7, #12]
  7944. 80031d6: 68ba ldr r2, [r7, #8]
  7945. 80031d8: 631a str r2, [r3, #48] ; 0x30
  7946. hspi->TxXferSize = Size;
  7947. 80031da: 68fb ldr r3, [r7, #12]
  7948. 80031dc: 88fa ldrh r2, [r7, #6]
  7949. 80031de: 869a strh r2, [r3, #52] ; 0x34
  7950. hspi->TxXferCount = Size;
  7951. 80031e0: 68fb ldr r3, [r7, #12]
  7952. 80031e2: 88fa ldrh r2, [r7, #6]
  7953. 80031e4: 86da strh r2, [r3, #54] ; 0x36
  7954. /*Init field not used in handle to zero */
  7955. hspi->pRxBuffPtr = (uint8_t *)NULL;
  7956. 80031e6: 68fb ldr r3, [r7, #12]
  7957. 80031e8: 2200 movs r2, #0
  7958. 80031ea: 639a str r2, [r3, #56] ; 0x38
  7959. hspi->RxXferSize = 0U;
  7960. 80031ec: 68fb ldr r3, [r7, #12]
  7961. 80031ee: 2200 movs r2, #0
  7962. 80031f0: 879a strh r2, [r3, #60] ; 0x3c
  7963. hspi->RxXferCount = 0U;
  7964. 80031f2: 68fb ldr r3, [r7, #12]
  7965. 80031f4: 2200 movs r2, #0
  7966. 80031f6: 87da strh r2, [r3, #62] ; 0x3e
  7967. hspi->TxISR = NULL;
  7968. 80031f8: 68fb ldr r3, [r7, #12]
  7969. 80031fa: 2200 movs r2, #0
  7970. 80031fc: 645a str r2, [r3, #68] ; 0x44
  7971. hspi->RxISR = NULL;
  7972. 80031fe: 68fb ldr r3, [r7, #12]
  7973. 8003200: 2200 movs r2, #0
  7974. 8003202: 641a str r2, [r3, #64] ; 0x40
  7975. /* Configure communication direction : 1Line */
  7976. if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
  7977. 8003204: 68fb ldr r3, [r7, #12]
  7978. 8003206: 689b ldr r3, [r3, #8]
  7979. 8003208: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
  7980. 800320c: d10f bne.n 800322e <HAL_SPI_Transmit+0xc0>
  7981. {
  7982. /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
  7983. __HAL_SPI_DISABLE(hspi);
  7984. 800320e: 68fb ldr r3, [r7, #12]
  7985. 8003210: 681b ldr r3, [r3, #0]
  7986. 8003212: 681a ldr r2, [r3, #0]
  7987. 8003214: 68fb ldr r3, [r7, #12]
  7988. 8003216: 681b ldr r3, [r3, #0]
  7989. 8003218: f022 0240 bic.w r2, r2, #64 ; 0x40
  7990. 800321c: 601a str r2, [r3, #0]
  7991. SPI_1LINE_TX(hspi);
  7992. 800321e: 68fb ldr r3, [r7, #12]
  7993. 8003220: 681b ldr r3, [r3, #0]
  7994. 8003222: 681a ldr r2, [r3, #0]
  7995. 8003224: 68fb ldr r3, [r7, #12]
  7996. 8003226: 681b ldr r3, [r3, #0]
  7997. 8003228: f442 4280 orr.w r2, r2, #16384 ; 0x4000
  7998. 800322c: 601a str r2, [r3, #0]
  7999. SPI_RESET_CRC(hspi);
  8000. }
  8001. #endif /* USE_SPI_CRC */
  8002. /* Check if the SPI is already enabled */
  8003. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  8004. 800322e: 68fb ldr r3, [r7, #12]
  8005. 8003230: 681b ldr r3, [r3, #0]
  8006. 8003232: 681b ldr r3, [r3, #0]
  8007. 8003234: f003 0340 and.w r3, r3, #64 ; 0x40
  8008. 8003238: 2b40 cmp r3, #64 ; 0x40
  8009. 800323a: d007 beq.n 800324c <HAL_SPI_Transmit+0xde>
  8010. {
  8011. /* Enable SPI peripheral */
  8012. __HAL_SPI_ENABLE(hspi);
  8013. 800323c: 68fb ldr r3, [r7, #12]
  8014. 800323e: 681b ldr r3, [r3, #0]
  8015. 8003240: 681a ldr r2, [r3, #0]
  8016. 8003242: 68fb ldr r3, [r7, #12]
  8017. 8003244: 681b ldr r3, [r3, #0]
  8018. 8003246: f042 0240 orr.w r2, r2, #64 ; 0x40
  8019. 800324a: 601a str r2, [r3, #0]
  8020. }
  8021. /* Transmit data in 16 Bit mode */
  8022. if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
  8023. 800324c: 68fb ldr r3, [r7, #12]
  8024. 800324e: 68db ldr r3, [r3, #12]
  8025. 8003250: f5b3 6f00 cmp.w r3, #2048 ; 0x800
  8026. 8003254: d14b bne.n 80032ee <HAL_SPI_Transmit+0x180>
  8027. {
  8028. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  8029. 8003256: 68fb ldr r3, [r7, #12]
  8030. 8003258: 685b ldr r3, [r3, #4]
  8031. 800325a: 2b00 cmp r3, #0
  8032. 800325c: d002 beq.n 8003264 <HAL_SPI_Transmit+0xf6>
  8033. 800325e: 8afb ldrh r3, [r7, #22]
  8034. 8003260: 2b01 cmp r3, #1
  8035. 8003262: d13e bne.n 80032e2 <HAL_SPI_Transmit+0x174>
  8036. {
  8037. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  8038. 8003264: 68fb ldr r3, [r7, #12]
  8039. 8003266: 6b1b ldr r3, [r3, #48] ; 0x30
  8040. 8003268: 881a ldrh r2, [r3, #0]
  8041. 800326a: 68fb ldr r3, [r7, #12]
  8042. 800326c: 681b ldr r3, [r3, #0]
  8043. 800326e: 60da str r2, [r3, #12]
  8044. hspi->pTxBuffPtr += sizeof(uint16_t);
  8045. 8003270: 68fb ldr r3, [r7, #12]
  8046. 8003272: 6b1b ldr r3, [r3, #48] ; 0x30
  8047. 8003274: 1c9a adds r2, r3, #2
  8048. 8003276: 68fb ldr r3, [r7, #12]
  8049. 8003278: 631a str r2, [r3, #48] ; 0x30
  8050. hspi->TxXferCount--;
  8051. 800327a: 68fb ldr r3, [r7, #12]
  8052. 800327c: 8edb ldrh r3, [r3, #54] ; 0x36
  8053. 800327e: b29b uxth r3, r3
  8054. 8003280: 3b01 subs r3, #1
  8055. 8003282: b29a uxth r2, r3
  8056. 8003284: 68fb ldr r3, [r7, #12]
  8057. 8003286: 86da strh r2, [r3, #54] ; 0x36
  8058. }
  8059. /* Transmit data in 16 Bit mode */
  8060. while (hspi->TxXferCount > 0U)
  8061. 8003288: e02b b.n 80032e2 <HAL_SPI_Transmit+0x174>
  8062. {
  8063. /* Wait until TXE flag is set to send data */
  8064. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
  8065. 800328a: 68fb ldr r3, [r7, #12]
  8066. 800328c: 681b ldr r3, [r3, #0]
  8067. 800328e: 689b ldr r3, [r3, #8]
  8068. 8003290: f003 0302 and.w r3, r3, #2
  8069. 8003294: 2b02 cmp r3, #2
  8070. 8003296: d112 bne.n 80032be <HAL_SPI_Transmit+0x150>
  8071. {
  8072. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  8073. 8003298: 68fb ldr r3, [r7, #12]
  8074. 800329a: 6b1b ldr r3, [r3, #48] ; 0x30
  8075. 800329c: 881a ldrh r2, [r3, #0]
  8076. 800329e: 68fb ldr r3, [r7, #12]
  8077. 80032a0: 681b ldr r3, [r3, #0]
  8078. 80032a2: 60da str r2, [r3, #12]
  8079. hspi->pTxBuffPtr += sizeof(uint16_t);
  8080. 80032a4: 68fb ldr r3, [r7, #12]
  8081. 80032a6: 6b1b ldr r3, [r3, #48] ; 0x30
  8082. 80032a8: 1c9a adds r2, r3, #2
  8083. 80032aa: 68fb ldr r3, [r7, #12]
  8084. 80032ac: 631a str r2, [r3, #48] ; 0x30
  8085. hspi->TxXferCount--;
  8086. 80032ae: 68fb ldr r3, [r7, #12]
  8087. 80032b0: 8edb ldrh r3, [r3, #54] ; 0x36
  8088. 80032b2: b29b uxth r3, r3
  8089. 80032b4: 3b01 subs r3, #1
  8090. 80032b6: b29a uxth r2, r3
  8091. 80032b8: 68fb ldr r3, [r7, #12]
  8092. 80032ba: 86da strh r2, [r3, #54] ; 0x36
  8093. 80032bc: e011 b.n 80032e2 <HAL_SPI_Transmit+0x174>
  8094. }
  8095. else
  8096. {
  8097. /* Timeout management */
  8098. if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
  8099. 80032be: f7fe fa4d bl 800175c <HAL_GetTick>
  8100. 80032c2: 4602 mov r2, r0
  8101. 80032c4: 69bb ldr r3, [r7, #24]
  8102. 80032c6: 1ad3 subs r3, r2, r3
  8103. 80032c8: 683a ldr r2, [r7, #0]
  8104. 80032ca: 429a cmp r2, r3
  8105. 80032cc: d803 bhi.n 80032d6 <HAL_SPI_Transmit+0x168>
  8106. 80032ce: 683b ldr r3, [r7, #0]
  8107. 80032d0: f1b3 3fff cmp.w r3, #4294967295
  8108. 80032d4: d102 bne.n 80032dc <HAL_SPI_Transmit+0x16e>
  8109. 80032d6: 683b ldr r3, [r7, #0]
  8110. 80032d8: 2b00 cmp r3, #0
  8111. 80032da: d102 bne.n 80032e2 <HAL_SPI_Transmit+0x174>
  8112. {
  8113. errorcode = HAL_TIMEOUT;
  8114. 80032dc: 2303 movs r3, #3
  8115. 80032de: 77fb strb r3, [r7, #31]
  8116. goto error;
  8117. 80032e0: e074 b.n 80033cc <HAL_SPI_Transmit+0x25e>
  8118. while (hspi->TxXferCount > 0U)
  8119. 80032e2: 68fb ldr r3, [r7, #12]
  8120. 80032e4: 8edb ldrh r3, [r3, #54] ; 0x36
  8121. 80032e6: b29b uxth r3, r3
  8122. 80032e8: 2b00 cmp r3, #0
  8123. 80032ea: d1ce bne.n 800328a <HAL_SPI_Transmit+0x11c>
  8124. 80032ec: e04c b.n 8003388 <HAL_SPI_Transmit+0x21a>
  8125. }
  8126. }
  8127. /* Transmit data in 8 Bit mode */
  8128. else
  8129. {
  8130. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  8131. 80032ee: 68fb ldr r3, [r7, #12]
  8132. 80032f0: 685b ldr r3, [r3, #4]
  8133. 80032f2: 2b00 cmp r3, #0
  8134. 80032f4: d002 beq.n 80032fc <HAL_SPI_Transmit+0x18e>
  8135. 80032f6: 8afb ldrh r3, [r7, #22]
  8136. 80032f8: 2b01 cmp r3, #1
  8137. 80032fa: d140 bne.n 800337e <HAL_SPI_Transmit+0x210>
  8138. {
  8139. *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
  8140. 80032fc: 68fb ldr r3, [r7, #12]
  8141. 80032fe: 6b1a ldr r2, [r3, #48] ; 0x30
  8142. 8003300: 68fb ldr r3, [r7, #12]
  8143. 8003302: 681b ldr r3, [r3, #0]
  8144. 8003304: 330c adds r3, #12
  8145. 8003306: 7812 ldrb r2, [r2, #0]
  8146. 8003308: 701a strb r2, [r3, #0]
  8147. hspi->pTxBuffPtr += sizeof(uint8_t);
  8148. 800330a: 68fb ldr r3, [r7, #12]
  8149. 800330c: 6b1b ldr r3, [r3, #48] ; 0x30
  8150. 800330e: 1c5a adds r2, r3, #1
  8151. 8003310: 68fb ldr r3, [r7, #12]
  8152. 8003312: 631a str r2, [r3, #48] ; 0x30
  8153. hspi->TxXferCount--;
  8154. 8003314: 68fb ldr r3, [r7, #12]
  8155. 8003316: 8edb ldrh r3, [r3, #54] ; 0x36
  8156. 8003318: b29b uxth r3, r3
  8157. 800331a: 3b01 subs r3, #1
  8158. 800331c: b29a uxth r2, r3
  8159. 800331e: 68fb ldr r3, [r7, #12]
  8160. 8003320: 86da strh r2, [r3, #54] ; 0x36
  8161. }
  8162. while (hspi->TxXferCount > 0U)
  8163. 8003322: e02c b.n 800337e <HAL_SPI_Transmit+0x210>
  8164. {
  8165. /* Wait until TXE flag is set to send data */
  8166. if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
  8167. 8003324: 68fb ldr r3, [r7, #12]
  8168. 8003326: 681b ldr r3, [r3, #0]
  8169. 8003328: 689b ldr r3, [r3, #8]
  8170. 800332a: f003 0302 and.w r3, r3, #2
  8171. 800332e: 2b02 cmp r3, #2
  8172. 8003330: d113 bne.n 800335a <HAL_SPI_Transmit+0x1ec>
  8173. {
  8174. *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
  8175. 8003332: 68fb ldr r3, [r7, #12]
  8176. 8003334: 6b1a ldr r2, [r3, #48] ; 0x30
  8177. 8003336: 68fb ldr r3, [r7, #12]
  8178. 8003338: 681b ldr r3, [r3, #0]
  8179. 800333a: 330c adds r3, #12
  8180. 800333c: 7812 ldrb r2, [r2, #0]
  8181. 800333e: 701a strb r2, [r3, #0]
  8182. hspi->pTxBuffPtr += sizeof(uint8_t);
  8183. 8003340: 68fb ldr r3, [r7, #12]
  8184. 8003342: 6b1b ldr r3, [r3, #48] ; 0x30
  8185. 8003344: 1c5a adds r2, r3, #1
  8186. 8003346: 68fb ldr r3, [r7, #12]
  8187. 8003348: 631a str r2, [r3, #48] ; 0x30
  8188. hspi->TxXferCount--;
  8189. 800334a: 68fb ldr r3, [r7, #12]
  8190. 800334c: 8edb ldrh r3, [r3, #54] ; 0x36
  8191. 800334e: b29b uxth r3, r3
  8192. 8003350: 3b01 subs r3, #1
  8193. 8003352: b29a uxth r2, r3
  8194. 8003354: 68fb ldr r3, [r7, #12]
  8195. 8003356: 86da strh r2, [r3, #54] ; 0x36
  8196. 8003358: e011 b.n 800337e <HAL_SPI_Transmit+0x210>
  8197. }
  8198. else
  8199. {
  8200. /* Timeout management */
  8201. if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
  8202. 800335a: f7fe f9ff bl 800175c <HAL_GetTick>
  8203. 800335e: 4602 mov r2, r0
  8204. 8003360: 69bb ldr r3, [r7, #24]
  8205. 8003362: 1ad3 subs r3, r2, r3
  8206. 8003364: 683a ldr r2, [r7, #0]
  8207. 8003366: 429a cmp r2, r3
  8208. 8003368: d803 bhi.n 8003372 <HAL_SPI_Transmit+0x204>
  8209. 800336a: 683b ldr r3, [r7, #0]
  8210. 800336c: f1b3 3fff cmp.w r3, #4294967295
  8211. 8003370: d102 bne.n 8003378 <HAL_SPI_Transmit+0x20a>
  8212. 8003372: 683b ldr r3, [r7, #0]
  8213. 8003374: 2b00 cmp r3, #0
  8214. 8003376: d102 bne.n 800337e <HAL_SPI_Transmit+0x210>
  8215. {
  8216. errorcode = HAL_TIMEOUT;
  8217. 8003378: 2303 movs r3, #3
  8218. 800337a: 77fb strb r3, [r7, #31]
  8219. goto error;
  8220. 800337c: e026 b.n 80033cc <HAL_SPI_Transmit+0x25e>
  8221. while (hspi->TxXferCount > 0U)
  8222. 800337e: 68fb ldr r3, [r7, #12]
  8223. 8003380: 8edb ldrh r3, [r3, #54] ; 0x36
  8224. 8003382: b29b uxth r3, r3
  8225. 8003384: 2b00 cmp r3, #0
  8226. 8003386: d1cd bne.n 8003324 <HAL_SPI_Transmit+0x1b6>
  8227. SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
  8228. }
  8229. #endif /* USE_SPI_CRC */
  8230. /* Check the end of the transaction */
  8231. if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  8232. 8003388: 69ba ldr r2, [r7, #24]
  8233. 800338a: 6839 ldr r1, [r7, #0]
  8234. 800338c: 68f8 ldr r0, [r7, #12]
  8235. 800338e: f000 fa55 bl 800383c <SPI_EndRxTxTransaction>
  8236. 8003392: 4603 mov r3, r0
  8237. 8003394: 2b00 cmp r3, #0
  8238. 8003396: d002 beq.n 800339e <HAL_SPI_Transmit+0x230>
  8239. {
  8240. hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  8241. 8003398: 68fb ldr r3, [r7, #12]
  8242. 800339a: 2220 movs r2, #32
  8243. 800339c: 655a str r2, [r3, #84] ; 0x54
  8244. }
  8245. /* Clear overrun flag in 2 Lines communication mode because received is not read */
  8246. if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  8247. 800339e: 68fb ldr r3, [r7, #12]
  8248. 80033a0: 689b ldr r3, [r3, #8]
  8249. 80033a2: 2b00 cmp r3, #0
  8250. 80033a4: d10a bne.n 80033bc <HAL_SPI_Transmit+0x24e>
  8251. {
  8252. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  8253. 80033a6: 2300 movs r3, #0
  8254. 80033a8: 613b str r3, [r7, #16]
  8255. 80033aa: 68fb ldr r3, [r7, #12]
  8256. 80033ac: 681b ldr r3, [r3, #0]
  8257. 80033ae: 68db ldr r3, [r3, #12]
  8258. 80033b0: 613b str r3, [r7, #16]
  8259. 80033b2: 68fb ldr r3, [r7, #12]
  8260. 80033b4: 681b ldr r3, [r3, #0]
  8261. 80033b6: 689b ldr r3, [r3, #8]
  8262. 80033b8: 613b str r3, [r7, #16]
  8263. 80033ba: 693b ldr r3, [r7, #16]
  8264. }
  8265. if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
  8266. 80033bc: 68fb ldr r3, [r7, #12]
  8267. 80033be: 6d5b ldr r3, [r3, #84] ; 0x54
  8268. 80033c0: 2b00 cmp r3, #0
  8269. 80033c2: d002 beq.n 80033ca <HAL_SPI_Transmit+0x25c>
  8270. {
  8271. errorcode = HAL_ERROR;
  8272. 80033c4: 2301 movs r3, #1
  8273. 80033c6: 77fb strb r3, [r7, #31]
  8274. 80033c8: e000 b.n 80033cc <HAL_SPI_Transmit+0x25e>
  8275. }
  8276. error:
  8277. 80033ca: bf00 nop
  8278. hspi->State = HAL_SPI_STATE_READY;
  8279. 80033cc: 68fb ldr r3, [r7, #12]
  8280. 80033ce: 2201 movs r2, #1
  8281. 80033d0: f883 2051 strb.w r2, [r3, #81] ; 0x51
  8282. /* Process Unlocked */
  8283. __HAL_UNLOCK(hspi);
  8284. 80033d4: 68fb ldr r3, [r7, #12]
  8285. 80033d6: 2200 movs r2, #0
  8286. 80033d8: f883 2050 strb.w r2, [r3, #80] ; 0x50
  8287. return errorcode;
  8288. 80033dc: 7ffb ldrb r3, [r7, #31]
  8289. }
  8290. 80033de: 4618 mov r0, r3
  8291. 80033e0: 3720 adds r7, #32
  8292. 80033e2: 46bd mov sp, r7
  8293. 80033e4: bd80 pop {r7, pc}
  8294. 080033e6 <HAL_SPI_TransmitReceive>:
  8295. * @param Timeout Timeout duration
  8296. * @retval HAL status
  8297. */
  8298. HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
  8299. uint32_t Timeout)
  8300. {
  8301. 80033e6: b580 push {r7, lr}
  8302. 80033e8: b08c sub sp, #48 ; 0x30
  8303. 80033ea: af00 add r7, sp, #0
  8304. 80033ec: 60f8 str r0, [r7, #12]
  8305. 80033ee: 60b9 str r1, [r7, #8]
  8306. 80033f0: 607a str r2, [r7, #4]
  8307. 80033f2: 807b strh r3, [r7, #2]
  8308. uint32_t tmp_mode;
  8309. HAL_SPI_StateTypeDef tmp_state;
  8310. uint32_t tickstart;
  8311. /* Variable used to alternate Rx and Tx during transfer */
  8312. uint32_t txallowed = 1U;
  8313. 80033f4: 2301 movs r3, #1
  8314. 80033f6: 62fb str r3, [r7, #44] ; 0x2c
  8315. HAL_StatusTypeDef errorcode = HAL_OK;
  8316. 80033f8: 2300 movs r3, #0
  8317. 80033fa: f887 302b strb.w r3, [r7, #43] ; 0x2b
  8318. /* Check Direction parameter */
  8319. assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
  8320. /* Process Locked */
  8321. __HAL_LOCK(hspi);
  8322. 80033fe: 68fb ldr r3, [r7, #12]
  8323. 8003400: f893 3050 ldrb.w r3, [r3, #80] ; 0x50
  8324. 8003404: 2b01 cmp r3, #1
  8325. 8003406: d101 bne.n 800340c <HAL_SPI_TransmitReceive+0x26>
  8326. 8003408: 2302 movs r3, #2
  8327. 800340a: e18a b.n 8003722 <HAL_SPI_TransmitReceive+0x33c>
  8328. 800340c: 68fb ldr r3, [r7, #12]
  8329. 800340e: 2201 movs r2, #1
  8330. 8003410: f883 2050 strb.w r2, [r3, #80] ; 0x50
  8331. /* Init tickstart for timeout management*/
  8332. tickstart = HAL_GetTick();
  8333. 8003414: f7fe f9a2 bl 800175c <HAL_GetTick>
  8334. 8003418: 6278 str r0, [r7, #36] ; 0x24
  8335. /* Init temporary variables */
  8336. tmp_state = hspi->State;
  8337. 800341a: 68fb ldr r3, [r7, #12]
  8338. 800341c: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
  8339. 8003420: f887 3023 strb.w r3, [r7, #35] ; 0x23
  8340. tmp_mode = hspi->Init.Mode;
  8341. 8003424: 68fb ldr r3, [r7, #12]
  8342. 8003426: 685b ldr r3, [r3, #4]
  8343. 8003428: 61fb str r3, [r7, #28]
  8344. initial_TxXferCount = Size;
  8345. 800342a: 887b ldrh r3, [r7, #2]
  8346. 800342c: 837b strh r3, [r7, #26]
  8347. if (!((tmp_state == HAL_SPI_STATE_READY) || \
  8348. 800342e: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
  8349. 8003432: 2b01 cmp r3, #1
  8350. 8003434: d00f beq.n 8003456 <HAL_SPI_TransmitReceive+0x70>
  8351. 8003436: 69fb ldr r3, [r7, #28]
  8352. 8003438: f5b3 7f82 cmp.w r3, #260 ; 0x104
  8353. 800343c: d107 bne.n 800344e <HAL_SPI_TransmitReceive+0x68>
  8354. ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
  8355. 800343e: 68fb ldr r3, [r7, #12]
  8356. 8003440: 689b ldr r3, [r3, #8]
  8357. 8003442: 2b00 cmp r3, #0
  8358. 8003444: d103 bne.n 800344e <HAL_SPI_TransmitReceive+0x68>
  8359. 8003446: f897 3023 ldrb.w r3, [r7, #35] ; 0x23
  8360. 800344a: 2b04 cmp r3, #4
  8361. 800344c: d003 beq.n 8003456 <HAL_SPI_TransmitReceive+0x70>
  8362. {
  8363. errorcode = HAL_BUSY;
  8364. 800344e: 2302 movs r3, #2
  8365. 8003450: f887 302b strb.w r3, [r7, #43] ; 0x2b
  8366. goto error;
  8367. 8003454: e15b b.n 800370e <HAL_SPI_TransmitReceive+0x328>
  8368. }
  8369. if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
  8370. 8003456: 68bb ldr r3, [r7, #8]
  8371. 8003458: 2b00 cmp r3, #0
  8372. 800345a: d005 beq.n 8003468 <HAL_SPI_TransmitReceive+0x82>
  8373. 800345c: 687b ldr r3, [r7, #4]
  8374. 800345e: 2b00 cmp r3, #0
  8375. 8003460: d002 beq.n 8003468 <HAL_SPI_TransmitReceive+0x82>
  8376. 8003462: 887b ldrh r3, [r7, #2]
  8377. 8003464: 2b00 cmp r3, #0
  8378. 8003466: d103 bne.n 8003470 <HAL_SPI_TransmitReceive+0x8a>
  8379. {
  8380. errorcode = HAL_ERROR;
  8381. 8003468: 2301 movs r3, #1
  8382. 800346a: f887 302b strb.w r3, [r7, #43] ; 0x2b
  8383. goto error;
  8384. 800346e: e14e b.n 800370e <HAL_SPI_TransmitReceive+0x328>
  8385. }
  8386. /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
  8387. if (hspi->State != HAL_SPI_STATE_BUSY_RX)
  8388. 8003470: 68fb ldr r3, [r7, #12]
  8389. 8003472: f893 3051 ldrb.w r3, [r3, #81] ; 0x51
  8390. 8003476: b2db uxtb r3, r3
  8391. 8003478: 2b04 cmp r3, #4
  8392. 800347a: d003 beq.n 8003484 <HAL_SPI_TransmitReceive+0x9e>
  8393. {
  8394. hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
  8395. 800347c: 68fb ldr r3, [r7, #12]
  8396. 800347e: 2205 movs r2, #5
  8397. 8003480: f883 2051 strb.w r2, [r3, #81] ; 0x51
  8398. }
  8399. /* Set the transaction information */
  8400. hspi->ErrorCode = HAL_SPI_ERROR_NONE;
  8401. 8003484: 68fb ldr r3, [r7, #12]
  8402. 8003486: 2200 movs r2, #0
  8403. 8003488: 655a str r2, [r3, #84] ; 0x54
  8404. hspi->pRxBuffPtr = (uint8_t *)pRxData;
  8405. 800348a: 68fb ldr r3, [r7, #12]
  8406. 800348c: 687a ldr r2, [r7, #4]
  8407. 800348e: 639a str r2, [r3, #56] ; 0x38
  8408. hspi->RxXferCount = Size;
  8409. 8003490: 68fb ldr r3, [r7, #12]
  8410. 8003492: 887a ldrh r2, [r7, #2]
  8411. 8003494: 87da strh r2, [r3, #62] ; 0x3e
  8412. hspi->RxXferSize = Size;
  8413. 8003496: 68fb ldr r3, [r7, #12]
  8414. 8003498: 887a ldrh r2, [r7, #2]
  8415. 800349a: 879a strh r2, [r3, #60] ; 0x3c
  8416. hspi->pTxBuffPtr = (uint8_t *)pTxData;
  8417. 800349c: 68fb ldr r3, [r7, #12]
  8418. 800349e: 68ba ldr r2, [r7, #8]
  8419. 80034a0: 631a str r2, [r3, #48] ; 0x30
  8420. hspi->TxXferCount = Size;
  8421. 80034a2: 68fb ldr r3, [r7, #12]
  8422. 80034a4: 887a ldrh r2, [r7, #2]
  8423. 80034a6: 86da strh r2, [r3, #54] ; 0x36
  8424. hspi->TxXferSize = Size;
  8425. 80034a8: 68fb ldr r3, [r7, #12]
  8426. 80034aa: 887a ldrh r2, [r7, #2]
  8427. 80034ac: 869a strh r2, [r3, #52] ; 0x34
  8428. /*Init field not used in handle to zero */
  8429. hspi->RxISR = NULL;
  8430. 80034ae: 68fb ldr r3, [r7, #12]
  8431. 80034b0: 2200 movs r2, #0
  8432. 80034b2: 641a str r2, [r3, #64] ; 0x40
  8433. hspi->TxISR = NULL;
  8434. 80034b4: 68fb ldr r3, [r7, #12]
  8435. 80034b6: 2200 movs r2, #0
  8436. 80034b8: 645a str r2, [r3, #68] ; 0x44
  8437. SPI_RESET_CRC(hspi);
  8438. }
  8439. #endif /* USE_SPI_CRC */
  8440. /* Check if the SPI is already enabled */
  8441. if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
  8442. 80034ba: 68fb ldr r3, [r7, #12]
  8443. 80034bc: 681b ldr r3, [r3, #0]
  8444. 80034be: 681b ldr r3, [r3, #0]
  8445. 80034c0: f003 0340 and.w r3, r3, #64 ; 0x40
  8446. 80034c4: 2b40 cmp r3, #64 ; 0x40
  8447. 80034c6: d007 beq.n 80034d8 <HAL_SPI_TransmitReceive+0xf2>
  8448. {
  8449. /* Enable SPI peripheral */
  8450. __HAL_SPI_ENABLE(hspi);
  8451. 80034c8: 68fb ldr r3, [r7, #12]
  8452. 80034ca: 681b ldr r3, [r3, #0]
  8453. 80034cc: 681a ldr r2, [r3, #0]
  8454. 80034ce: 68fb ldr r3, [r7, #12]
  8455. 80034d0: 681b ldr r3, [r3, #0]
  8456. 80034d2: f042 0240 orr.w r2, r2, #64 ; 0x40
  8457. 80034d6: 601a str r2, [r3, #0]
  8458. }
  8459. /* Transmit and Receive data in 16 Bit mode */
  8460. if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
  8461. 80034d8: 68fb ldr r3, [r7, #12]
  8462. 80034da: 68db ldr r3, [r3, #12]
  8463. 80034dc: f5b3 6f00 cmp.w r3, #2048 ; 0x800
  8464. 80034e0: d178 bne.n 80035d4 <HAL_SPI_TransmitReceive+0x1ee>
  8465. {
  8466. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  8467. 80034e2: 68fb ldr r3, [r7, #12]
  8468. 80034e4: 685b ldr r3, [r3, #4]
  8469. 80034e6: 2b00 cmp r3, #0
  8470. 80034e8: d002 beq.n 80034f0 <HAL_SPI_TransmitReceive+0x10a>
  8471. 80034ea: 8b7b ldrh r3, [r7, #26]
  8472. 80034ec: 2b01 cmp r3, #1
  8473. 80034ee: d166 bne.n 80035be <HAL_SPI_TransmitReceive+0x1d8>
  8474. {
  8475. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  8476. 80034f0: 68fb ldr r3, [r7, #12]
  8477. 80034f2: 6b1b ldr r3, [r3, #48] ; 0x30
  8478. 80034f4: 881a ldrh r2, [r3, #0]
  8479. 80034f6: 68fb ldr r3, [r7, #12]
  8480. 80034f8: 681b ldr r3, [r3, #0]
  8481. 80034fa: 60da str r2, [r3, #12]
  8482. hspi->pTxBuffPtr += sizeof(uint16_t);
  8483. 80034fc: 68fb ldr r3, [r7, #12]
  8484. 80034fe: 6b1b ldr r3, [r3, #48] ; 0x30
  8485. 8003500: 1c9a adds r2, r3, #2
  8486. 8003502: 68fb ldr r3, [r7, #12]
  8487. 8003504: 631a str r2, [r3, #48] ; 0x30
  8488. hspi->TxXferCount--;
  8489. 8003506: 68fb ldr r3, [r7, #12]
  8490. 8003508: 8edb ldrh r3, [r3, #54] ; 0x36
  8491. 800350a: b29b uxth r3, r3
  8492. 800350c: 3b01 subs r3, #1
  8493. 800350e: b29a uxth r2, r3
  8494. 8003510: 68fb ldr r3, [r7, #12]
  8495. 8003512: 86da strh r2, [r3, #54] ; 0x36
  8496. }
  8497. while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  8498. 8003514: e053 b.n 80035be <HAL_SPI_TransmitReceive+0x1d8>
  8499. {
  8500. /* Check TXE flag */
  8501. if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
  8502. 8003516: 68fb ldr r3, [r7, #12]
  8503. 8003518: 681b ldr r3, [r3, #0]
  8504. 800351a: 689b ldr r3, [r3, #8]
  8505. 800351c: f003 0302 and.w r3, r3, #2
  8506. 8003520: 2b02 cmp r3, #2
  8507. 8003522: d11b bne.n 800355c <HAL_SPI_TransmitReceive+0x176>
  8508. 8003524: 68fb ldr r3, [r7, #12]
  8509. 8003526: 8edb ldrh r3, [r3, #54] ; 0x36
  8510. 8003528: b29b uxth r3, r3
  8511. 800352a: 2b00 cmp r3, #0
  8512. 800352c: d016 beq.n 800355c <HAL_SPI_TransmitReceive+0x176>
  8513. 800352e: 6afb ldr r3, [r7, #44] ; 0x2c
  8514. 8003530: 2b01 cmp r3, #1
  8515. 8003532: d113 bne.n 800355c <HAL_SPI_TransmitReceive+0x176>
  8516. {
  8517. hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
  8518. 8003534: 68fb ldr r3, [r7, #12]
  8519. 8003536: 6b1b ldr r3, [r3, #48] ; 0x30
  8520. 8003538: 881a ldrh r2, [r3, #0]
  8521. 800353a: 68fb ldr r3, [r7, #12]
  8522. 800353c: 681b ldr r3, [r3, #0]
  8523. 800353e: 60da str r2, [r3, #12]
  8524. hspi->pTxBuffPtr += sizeof(uint16_t);
  8525. 8003540: 68fb ldr r3, [r7, #12]
  8526. 8003542: 6b1b ldr r3, [r3, #48] ; 0x30
  8527. 8003544: 1c9a adds r2, r3, #2
  8528. 8003546: 68fb ldr r3, [r7, #12]
  8529. 8003548: 631a str r2, [r3, #48] ; 0x30
  8530. hspi->TxXferCount--;
  8531. 800354a: 68fb ldr r3, [r7, #12]
  8532. 800354c: 8edb ldrh r3, [r3, #54] ; 0x36
  8533. 800354e: b29b uxth r3, r3
  8534. 8003550: 3b01 subs r3, #1
  8535. 8003552: b29a uxth r2, r3
  8536. 8003554: 68fb ldr r3, [r7, #12]
  8537. 8003556: 86da strh r2, [r3, #54] ; 0x36
  8538. /* Next Data is a reception (Rx). Tx not allowed */
  8539. txallowed = 0U;
  8540. 8003558: 2300 movs r3, #0
  8541. 800355a: 62fb str r3, [r7, #44] ; 0x2c
  8542. }
  8543. #endif /* USE_SPI_CRC */
  8544. }
  8545. /* Check RXNE flag */
  8546. if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
  8547. 800355c: 68fb ldr r3, [r7, #12]
  8548. 800355e: 681b ldr r3, [r3, #0]
  8549. 8003560: 689b ldr r3, [r3, #8]
  8550. 8003562: f003 0301 and.w r3, r3, #1
  8551. 8003566: 2b01 cmp r3, #1
  8552. 8003568: d119 bne.n 800359e <HAL_SPI_TransmitReceive+0x1b8>
  8553. 800356a: 68fb ldr r3, [r7, #12]
  8554. 800356c: 8fdb ldrh r3, [r3, #62] ; 0x3e
  8555. 800356e: b29b uxth r3, r3
  8556. 8003570: 2b00 cmp r3, #0
  8557. 8003572: d014 beq.n 800359e <HAL_SPI_TransmitReceive+0x1b8>
  8558. {
  8559. *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
  8560. 8003574: 68fb ldr r3, [r7, #12]
  8561. 8003576: 681b ldr r3, [r3, #0]
  8562. 8003578: 68da ldr r2, [r3, #12]
  8563. 800357a: 68fb ldr r3, [r7, #12]
  8564. 800357c: 6b9b ldr r3, [r3, #56] ; 0x38
  8565. 800357e: b292 uxth r2, r2
  8566. 8003580: 801a strh r2, [r3, #0]
  8567. hspi->pRxBuffPtr += sizeof(uint16_t);
  8568. 8003582: 68fb ldr r3, [r7, #12]
  8569. 8003584: 6b9b ldr r3, [r3, #56] ; 0x38
  8570. 8003586: 1c9a adds r2, r3, #2
  8571. 8003588: 68fb ldr r3, [r7, #12]
  8572. 800358a: 639a str r2, [r3, #56] ; 0x38
  8573. hspi->RxXferCount--;
  8574. 800358c: 68fb ldr r3, [r7, #12]
  8575. 800358e: 8fdb ldrh r3, [r3, #62] ; 0x3e
  8576. 8003590: b29b uxth r3, r3
  8577. 8003592: 3b01 subs r3, #1
  8578. 8003594: b29a uxth r2, r3
  8579. 8003596: 68fb ldr r3, [r7, #12]
  8580. 8003598: 87da strh r2, [r3, #62] ; 0x3e
  8581. /* Next Data is a Transmission (Tx). Tx is allowed */
  8582. txallowed = 1U;
  8583. 800359a: 2301 movs r3, #1
  8584. 800359c: 62fb str r3, [r7, #44] ; 0x2c
  8585. }
  8586. if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY))
  8587. 800359e: f7fe f8dd bl 800175c <HAL_GetTick>
  8588. 80035a2: 4602 mov r2, r0
  8589. 80035a4: 6a7b ldr r3, [r7, #36] ; 0x24
  8590. 80035a6: 1ad3 subs r3, r2, r3
  8591. 80035a8: 6bba ldr r2, [r7, #56] ; 0x38
  8592. 80035aa: 429a cmp r2, r3
  8593. 80035ac: d807 bhi.n 80035be <HAL_SPI_TransmitReceive+0x1d8>
  8594. 80035ae: 6bbb ldr r3, [r7, #56] ; 0x38
  8595. 80035b0: f1b3 3fff cmp.w r3, #4294967295
  8596. 80035b4: d003 beq.n 80035be <HAL_SPI_TransmitReceive+0x1d8>
  8597. {
  8598. errorcode = HAL_TIMEOUT;
  8599. 80035b6: 2303 movs r3, #3
  8600. 80035b8: f887 302b strb.w r3, [r7, #43] ; 0x2b
  8601. goto error;
  8602. 80035bc: e0a7 b.n 800370e <HAL_SPI_TransmitReceive+0x328>
  8603. while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  8604. 80035be: 68fb ldr r3, [r7, #12]
  8605. 80035c0: 8edb ldrh r3, [r3, #54] ; 0x36
  8606. 80035c2: b29b uxth r3, r3
  8607. 80035c4: 2b00 cmp r3, #0
  8608. 80035c6: d1a6 bne.n 8003516 <HAL_SPI_TransmitReceive+0x130>
  8609. 80035c8: 68fb ldr r3, [r7, #12]
  8610. 80035ca: 8fdb ldrh r3, [r3, #62] ; 0x3e
  8611. 80035cc: b29b uxth r3, r3
  8612. 80035ce: 2b00 cmp r3, #0
  8613. 80035d0: d1a1 bne.n 8003516 <HAL_SPI_TransmitReceive+0x130>
  8614. 80035d2: e07c b.n 80036ce <HAL_SPI_TransmitReceive+0x2e8>
  8615. }
  8616. }
  8617. /* Transmit and Receive data in 8 Bit mode */
  8618. else
  8619. {
  8620. if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
  8621. 80035d4: 68fb ldr r3, [r7, #12]
  8622. 80035d6: 685b ldr r3, [r3, #4]
  8623. 80035d8: 2b00 cmp r3, #0
  8624. 80035da: d002 beq.n 80035e2 <HAL_SPI_TransmitReceive+0x1fc>
  8625. 80035dc: 8b7b ldrh r3, [r7, #26]
  8626. 80035de: 2b01 cmp r3, #1
  8627. 80035e0: d16b bne.n 80036ba <HAL_SPI_TransmitReceive+0x2d4>
  8628. {
  8629. *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
  8630. 80035e2: 68fb ldr r3, [r7, #12]
  8631. 80035e4: 6b1a ldr r2, [r3, #48] ; 0x30
  8632. 80035e6: 68fb ldr r3, [r7, #12]
  8633. 80035e8: 681b ldr r3, [r3, #0]
  8634. 80035ea: 330c adds r3, #12
  8635. 80035ec: 7812 ldrb r2, [r2, #0]
  8636. 80035ee: 701a strb r2, [r3, #0]
  8637. hspi->pTxBuffPtr += sizeof(uint8_t);
  8638. 80035f0: 68fb ldr r3, [r7, #12]
  8639. 80035f2: 6b1b ldr r3, [r3, #48] ; 0x30
  8640. 80035f4: 1c5a adds r2, r3, #1
  8641. 80035f6: 68fb ldr r3, [r7, #12]
  8642. 80035f8: 631a str r2, [r3, #48] ; 0x30
  8643. hspi->TxXferCount--;
  8644. 80035fa: 68fb ldr r3, [r7, #12]
  8645. 80035fc: 8edb ldrh r3, [r3, #54] ; 0x36
  8646. 80035fe: b29b uxth r3, r3
  8647. 8003600: 3b01 subs r3, #1
  8648. 8003602: b29a uxth r2, r3
  8649. 8003604: 68fb ldr r3, [r7, #12]
  8650. 8003606: 86da strh r2, [r3, #54] ; 0x36
  8651. }
  8652. while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  8653. 8003608: e057 b.n 80036ba <HAL_SPI_TransmitReceive+0x2d4>
  8654. {
  8655. /* Check TXE flag */
  8656. if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
  8657. 800360a: 68fb ldr r3, [r7, #12]
  8658. 800360c: 681b ldr r3, [r3, #0]
  8659. 800360e: 689b ldr r3, [r3, #8]
  8660. 8003610: f003 0302 and.w r3, r3, #2
  8661. 8003614: 2b02 cmp r3, #2
  8662. 8003616: d11c bne.n 8003652 <HAL_SPI_TransmitReceive+0x26c>
  8663. 8003618: 68fb ldr r3, [r7, #12]
  8664. 800361a: 8edb ldrh r3, [r3, #54] ; 0x36
  8665. 800361c: b29b uxth r3, r3
  8666. 800361e: 2b00 cmp r3, #0
  8667. 8003620: d017 beq.n 8003652 <HAL_SPI_TransmitReceive+0x26c>
  8668. 8003622: 6afb ldr r3, [r7, #44] ; 0x2c
  8669. 8003624: 2b01 cmp r3, #1
  8670. 8003626: d114 bne.n 8003652 <HAL_SPI_TransmitReceive+0x26c>
  8671. {
  8672. *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
  8673. 8003628: 68fb ldr r3, [r7, #12]
  8674. 800362a: 6b1a ldr r2, [r3, #48] ; 0x30
  8675. 800362c: 68fb ldr r3, [r7, #12]
  8676. 800362e: 681b ldr r3, [r3, #0]
  8677. 8003630: 330c adds r3, #12
  8678. 8003632: 7812 ldrb r2, [r2, #0]
  8679. 8003634: 701a strb r2, [r3, #0]
  8680. hspi->pTxBuffPtr++;
  8681. 8003636: 68fb ldr r3, [r7, #12]
  8682. 8003638: 6b1b ldr r3, [r3, #48] ; 0x30
  8683. 800363a: 1c5a adds r2, r3, #1
  8684. 800363c: 68fb ldr r3, [r7, #12]
  8685. 800363e: 631a str r2, [r3, #48] ; 0x30
  8686. hspi->TxXferCount--;
  8687. 8003640: 68fb ldr r3, [r7, #12]
  8688. 8003642: 8edb ldrh r3, [r3, #54] ; 0x36
  8689. 8003644: b29b uxth r3, r3
  8690. 8003646: 3b01 subs r3, #1
  8691. 8003648: b29a uxth r2, r3
  8692. 800364a: 68fb ldr r3, [r7, #12]
  8693. 800364c: 86da strh r2, [r3, #54] ; 0x36
  8694. /* Next Data is a reception (Rx). Tx not allowed */
  8695. txallowed = 0U;
  8696. 800364e: 2300 movs r3, #0
  8697. 8003650: 62fb str r3, [r7, #44] ; 0x2c
  8698. }
  8699. #endif /* USE_SPI_CRC */
  8700. }
  8701. /* Wait until RXNE flag is reset */
  8702. if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
  8703. 8003652: 68fb ldr r3, [r7, #12]
  8704. 8003654: 681b ldr r3, [r3, #0]
  8705. 8003656: 689b ldr r3, [r3, #8]
  8706. 8003658: f003 0301 and.w r3, r3, #1
  8707. 800365c: 2b01 cmp r3, #1
  8708. 800365e: d119 bne.n 8003694 <HAL_SPI_TransmitReceive+0x2ae>
  8709. 8003660: 68fb ldr r3, [r7, #12]
  8710. 8003662: 8fdb ldrh r3, [r3, #62] ; 0x3e
  8711. 8003664: b29b uxth r3, r3
  8712. 8003666: 2b00 cmp r3, #0
  8713. 8003668: d014 beq.n 8003694 <HAL_SPI_TransmitReceive+0x2ae>
  8714. {
  8715. (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
  8716. 800366a: 68fb ldr r3, [r7, #12]
  8717. 800366c: 681b ldr r3, [r3, #0]
  8718. 800366e: 68da ldr r2, [r3, #12]
  8719. 8003670: 68fb ldr r3, [r7, #12]
  8720. 8003672: 6b9b ldr r3, [r3, #56] ; 0x38
  8721. 8003674: b2d2 uxtb r2, r2
  8722. 8003676: 701a strb r2, [r3, #0]
  8723. hspi->pRxBuffPtr++;
  8724. 8003678: 68fb ldr r3, [r7, #12]
  8725. 800367a: 6b9b ldr r3, [r3, #56] ; 0x38
  8726. 800367c: 1c5a adds r2, r3, #1
  8727. 800367e: 68fb ldr r3, [r7, #12]
  8728. 8003680: 639a str r2, [r3, #56] ; 0x38
  8729. hspi->RxXferCount--;
  8730. 8003682: 68fb ldr r3, [r7, #12]
  8731. 8003684: 8fdb ldrh r3, [r3, #62] ; 0x3e
  8732. 8003686: b29b uxth r3, r3
  8733. 8003688: 3b01 subs r3, #1
  8734. 800368a: b29a uxth r2, r3
  8735. 800368c: 68fb ldr r3, [r7, #12]
  8736. 800368e: 87da strh r2, [r3, #62] ; 0x3e
  8737. /* Next Data is a Transmission (Tx). Tx is allowed */
  8738. txallowed = 1U;
  8739. 8003690: 2301 movs r3, #1
  8740. 8003692: 62fb str r3, [r7, #44] ; 0x2c
  8741. }
  8742. if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
  8743. 8003694: f7fe f862 bl 800175c <HAL_GetTick>
  8744. 8003698: 4602 mov r2, r0
  8745. 800369a: 6a7b ldr r3, [r7, #36] ; 0x24
  8746. 800369c: 1ad3 subs r3, r2, r3
  8747. 800369e: 6bba ldr r2, [r7, #56] ; 0x38
  8748. 80036a0: 429a cmp r2, r3
  8749. 80036a2: d803 bhi.n 80036ac <HAL_SPI_TransmitReceive+0x2c6>
  8750. 80036a4: 6bbb ldr r3, [r7, #56] ; 0x38
  8751. 80036a6: f1b3 3fff cmp.w r3, #4294967295
  8752. 80036aa: d102 bne.n 80036b2 <HAL_SPI_TransmitReceive+0x2cc>
  8753. 80036ac: 6bbb ldr r3, [r7, #56] ; 0x38
  8754. 80036ae: 2b00 cmp r3, #0
  8755. 80036b0: d103 bne.n 80036ba <HAL_SPI_TransmitReceive+0x2d4>
  8756. {
  8757. errorcode = HAL_TIMEOUT;
  8758. 80036b2: 2303 movs r3, #3
  8759. 80036b4: f887 302b strb.w r3, [r7, #43] ; 0x2b
  8760. goto error;
  8761. 80036b8: e029 b.n 800370e <HAL_SPI_TransmitReceive+0x328>
  8762. while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
  8763. 80036ba: 68fb ldr r3, [r7, #12]
  8764. 80036bc: 8edb ldrh r3, [r3, #54] ; 0x36
  8765. 80036be: b29b uxth r3, r3
  8766. 80036c0: 2b00 cmp r3, #0
  8767. 80036c2: d1a2 bne.n 800360a <HAL_SPI_TransmitReceive+0x224>
  8768. 80036c4: 68fb ldr r3, [r7, #12]
  8769. 80036c6: 8fdb ldrh r3, [r3, #62] ; 0x3e
  8770. 80036c8: b29b uxth r3, r3
  8771. 80036ca: 2b00 cmp r3, #0
  8772. 80036cc: d19d bne.n 800360a <HAL_SPI_TransmitReceive+0x224>
  8773. errorcode = HAL_ERROR;
  8774. }
  8775. #endif /* USE_SPI_CRC */
  8776. /* Check the end of the transaction */
  8777. if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
  8778. 80036ce: 6a7a ldr r2, [r7, #36] ; 0x24
  8779. 80036d0: 6bb9 ldr r1, [r7, #56] ; 0x38
  8780. 80036d2: 68f8 ldr r0, [r7, #12]
  8781. 80036d4: f000 f8b2 bl 800383c <SPI_EndRxTxTransaction>
  8782. 80036d8: 4603 mov r3, r0
  8783. 80036da: 2b00 cmp r3, #0
  8784. 80036dc: d006 beq.n 80036ec <HAL_SPI_TransmitReceive+0x306>
  8785. {
  8786. errorcode = HAL_ERROR;
  8787. 80036de: 2301 movs r3, #1
  8788. 80036e0: f887 302b strb.w r3, [r7, #43] ; 0x2b
  8789. hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
  8790. 80036e4: 68fb ldr r3, [r7, #12]
  8791. 80036e6: 2220 movs r2, #32
  8792. 80036e8: 655a str r2, [r3, #84] ; 0x54
  8793. goto error;
  8794. 80036ea: e010 b.n 800370e <HAL_SPI_TransmitReceive+0x328>
  8795. }
  8796. /* Clear overrun flag in 2 Lines communication mode because received is not read */
  8797. if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
  8798. 80036ec: 68fb ldr r3, [r7, #12]
  8799. 80036ee: 689b ldr r3, [r3, #8]
  8800. 80036f0: 2b00 cmp r3, #0
  8801. 80036f2: d10b bne.n 800370c <HAL_SPI_TransmitReceive+0x326>
  8802. {
  8803. __HAL_SPI_CLEAR_OVRFLAG(hspi);
  8804. 80036f4: 2300 movs r3, #0
  8805. 80036f6: 617b str r3, [r7, #20]
  8806. 80036f8: 68fb ldr r3, [r7, #12]
  8807. 80036fa: 681b ldr r3, [r3, #0]
  8808. 80036fc: 68db ldr r3, [r3, #12]
  8809. 80036fe: 617b str r3, [r7, #20]
  8810. 8003700: 68fb ldr r3, [r7, #12]
  8811. 8003702: 681b ldr r3, [r3, #0]
  8812. 8003704: 689b ldr r3, [r3, #8]
  8813. 8003706: 617b str r3, [r7, #20]
  8814. 8003708: 697b ldr r3, [r7, #20]
  8815. 800370a: e000 b.n 800370e <HAL_SPI_TransmitReceive+0x328>
  8816. }
  8817. error :
  8818. 800370c: bf00 nop
  8819. hspi->State = HAL_SPI_STATE_READY;
  8820. 800370e: 68fb ldr r3, [r7, #12]
  8821. 8003710: 2201 movs r2, #1
  8822. 8003712: f883 2051 strb.w r2, [r3, #81] ; 0x51
  8823. __HAL_UNLOCK(hspi);
  8824. 8003716: 68fb ldr r3, [r7, #12]
  8825. 8003718: 2200 movs r2, #0
  8826. 800371a: f883 2050 strb.w r2, [r3, #80] ; 0x50
  8827. return errorcode;
  8828. 800371e: f897 302b ldrb.w r3, [r7, #43] ; 0x2b
  8829. }
  8830. 8003722: 4618 mov r0, r3
  8831. 8003724: 3730 adds r7, #48 ; 0x30
  8832. 8003726: 46bd mov sp, r7
  8833. 8003728: bd80 pop {r7, pc}
  8834. ...
  8835. 0800372c <SPI_WaitFlagStateUntilTimeout>:
  8836. * @param Tickstart tick start value
  8837. * @retval HAL status
  8838. */
  8839. static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
  8840. uint32_t Timeout, uint32_t Tickstart)
  8841. {
  8842. 800372c: b580 push {r7, lr}
  8843. 800372e: b088 sub sp, #32
  8844. 8003730: af00 add r7, sp, #0
  8845. 8003732: 60f8 str r0, [r7, #12]
  8846. 8003734: 60b9 str r1, [r7, #8]
  8847. 8003736: 603b str r3, [r7, #0]
  8848. 8003738: 4613 mov r3, r2
  8849. 800373a: 71fb strb r3, [r7, #7]
  8850. __IO uint32_t count;
  8851. uint32_t tmp_timeout;
  8852. uint32_t tmp_tickstart;
  8853. /* Adjust Timeout value in case of end of transfer */
  8854. tmp_timeout = Timeout - (HAL_GetTick() - Tickstart);
  8855. 800373c: f7fe f80e bl 800175c <HAL_GetTick>
  8856. 8003740: 4602 mov r2, r0
  8857. 8003742: 6abb ldr r3, [r7, #40] ; 0x28
  8858. 8003744: 1a9b subs r3, r3, r2
  8859. 8003746: 683a ldr r2, [r7, #0]
  8860. 8003748: 4413 add r3, r2
  8861. 800374a: 61fb str r3, [r7, #28]
  8862. tmp_tickstart = HAL_GetTick();
  8863. 800374c: f7fe f806 bl 800175c <HAL_GetTick>
  8864. 8003750: 61b8 str r0, [r7, #24]
  8865. /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
  8866. count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
  8867. 8003752: 4b39 ldr r3, [pc, #228] ; (8003838 <SPI_WaitFlagStateUntilTimeout+0x10c>)
  8868. 8003754: 681b ldr r3, [r3, #0]
  8869. 8003756: 015b lsls r3, r3, #5
  8870. 8003758: 0d1b lsrs r3, r3, #20
  8871. 800375a: 69fa ldr r2, [r7, #28]
  8872. 800375c: fb02 f303 mul.w r3, r2, r3
  8873. 8003760: 617b str r3, [r7, #20]
  8874. while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
  8875. 8003762: e054 b.n 800380e <SPI_WaitFlagStateUntilTimeout+0xe2>
  8876. {
  8877. if (Timeout != HAL_MAX_DELAY)
  8878. 8003764: 683b ldr r3, [r7, #0]
  8879. 8003766: f1b3 3fff cmp.w r3, #4294967295
  8880. 800376a: d050 beq.n 800380e <SPI_WaitFlagStateUntilTimeout+0xe2>
  8881. {
  8882. if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
  8883. 800376c: f7fd fff6 bl 800175c <HAL_GetTick>
  8884. 8003770: 4602 mov r2, r0
  8885. 8003772: 69bb ldr r3, [r7, #24]
  8886. 8003774: 1ad3 subs r3, r2, r3
  8887. 8003776: 69fa ldr r2, [r7, #28]
  8888. 8003778: 429a cmp r2, r3
  8889. 800377a: d902 bls.n 8003782 <SPI_WaitFlagStateUntilTimeout+0x56>
  8890. 800377c: 69fb ldr r3, [r7, #28]
  8891. 800377e: 2b00 cmp r3, #0
  8892. 8003780: d13d bne.n 80037fe <SPI_WaitFlagStateUntilTimeout+0xd2>
  8893. /* Disable the SPI and reset the CRC: the CRC value should be cleared
  8894. on both master and slave sides in order to resynchronize the master
  8895. and slave for their respective CRC calculation */
  8896. /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
  8897. __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
  8898. 8003782: 68fb ldr r3, [r7, #12]
  8899. 8003784: 681b ldr r3, [r3, #0]
  8900. 8003786: 685a ldr r2, [r3, #4]
  8901. 8003788: 68fb ldr r3, [r7, #12]
  8902. 800378a: 681b ldr r3, [r3, #0]
  8903. 800378c: f022 02e0 bic.w r2, r2, #224 ; 0xe0
  8904. 8003790: 605a str r2, [r3, #4]
  8905. if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
  8906. 8003792: 68fb ldr r3, [r7, #12]
  8907. 8003794: 685b ldr r3, [r3, #4]
  8908. 8003796: f5b3 7f82 cmp.w r3, #260 ; 0x104
  8909. 800379a: d111 bne.n 80037c0 <SPI_WaitFlagStateUntilTimeout+0x94>
  8910. 800379c: 68fb ldr r3, [r7, #12]
  8911. 800379e: 689b ldr r3, [r3, #8]
  8912. 80037a0: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
  8913. 80037a4: d004 beq.n 80037b0 <SPI_WaitFlagStateUntilTimeout+0x84>
  8914. || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
  8915. 80037a6: 68fb ldr r3, [r7, #12]
  8916. 80037a8: 689b ldr r3, [r3, #8]
  8917. 80037aa: f5b3 6f80 cmp.w r3, #1024 ; 0x400
  8918. 80037ae: d107 bne.n 80037c0 <SPI_WaitFlagStateUntilTimeout+0x94>
  8919. {
  8920. /* Disable SPI peripheral */
  8921. __HAL_SPI_DISABLE(hspi);
  8922. 80037b0: 68fb ldr r3, [r7, #12]
  8923. 80037b2: 681b ldr r3, [r3, #0]
  8924. 80037b4: 681a ldr r2, [r3, #0]
  8925. 80037b6: 68fb ldr r3, [r7, #12]
  8926. 80037b8: 681b ldr r3, [r3, #0]
  8927. 80037ba: f022 0240 bic.w r2, r2, #64 ; 0x40
  8928. 80037be: 601a str r2, [r3, #0]
  8929. }
  8930. /* Reset CRC Calculation */
  8931. if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
  8932. 80037c0: 68fb ldr r3, [r7, #12]
  8933. 80037c2: 6a9b ldr r3, [r3, #40] ; 0x28
  8934. 80037c4: f5b3 5f00 cmp.w r3, #8192 ; 0x2000
  8935. 80037c8: d10f bne.n 80037ea <SPI_WaitFlagStateUntilTimeout+0xbe>
  8936. {
  8937. SPI_RESET_CRC(hspi);
  8938. 80037ca: 68fb ldr r3, [r7, #12]
  8939. 80037cc: 681b ldr r3, [r3, #0]
  8940. 80037ce: 681a ldr r2, [r3, #0]
  8941. 80037d0: 68fb ldr r3, [r7, #12]
  8942. 80037d2: 681b ldr r3, [r3, #0]
  8943. 80037d4: f422 5200 bic.w r2, r2, #8192 ; 0x2000
  8944. 80037d8: 601a str r2, [r3, #0]
  8945. 80037da: 68fb ldr r3, [r7, #12]
  8946. 80037dc: 681b ldr r3, [r3, #0]
  8947. 80037de: 681a ldr r2, [r3, #0]
  8948. 80037e0: 68fb ldr r3, [r7, #12]
  8949. 80037e2: 681b ldr r3, [r3, #0]
  8950. 80037e4: f442 5200 orr.w r2, r2, #8192 ; 0x2000
  8951. 80037e8: 601a str r2, [r3, #0]
  8952. }
  8953. hspi->State = HAL_SPI_STATE_READY;
  8954. 80037ea: 68fb ldr r3, [r7, #12]
  8955. 80037ec: 2201 movs r2, #1
  8956. 80037ee: f883 2051 strb.w r2, [r3, #81] ; 0x51
  8957. /* Process Unlocked */
  8958. __HAL_UNLOCK(hspi);
  8959. 80037f2: 68fb ldr r3, [r7, #12]
  8960. 80037f4: 2200 movs r2, #0
  8961. 80037f6: f883 2050 strb.w r2, [r3, #80] ; 0x50
  8962. return HAL_TIMEOUT;
  8963. 80037fa: 2303 movs r3, #3
  8964. 80037fc: e017 b.n 800382e <SPI_WaitFlagStateUntilTimeout+0x102>
  8965. }
  8966. /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
  8967. if(count == 0U)
  8968. 80037fe: 697b ldr r3, [r7, #20]
  8969. 8003800: 2b00 cmp r3, #0
  8970. 8003802: d101 bne.n 8003808 <SPI_WaitFlagStateUntilTimeout+0xdc>
  8971. {
  8972. tmp_timeout = 0U;
  8973. 8003804: 2300 movs r3, #0
  8974. 8003806: 61fb str r3, [r7, #28]
  8975. }
  8976. count--;
  8977. 8003808: 697b ldr r3, [r7, #20]
  8978. 800380a: 3b01 subs r3, #1
  8979. 800380c: 617b str r3, [r7, #20]
  8980. while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
  8981. 800380e: 68fb ldr r3, [r7, #12]
  8982. 8003810: 681b ldr r3, [r3, #0]
  8983. 8003812: 689a ldr r2, [r3, #8]
  8984. 8003814: 68bb ldr r3, [r7, #8]
  8985. 8003816: 4013 ands r3, r2
  8986. 8003818: 68ba ldr r2, [r7, #8]
  8987. 800381a: 429a cmp r2, r3
  8988. 800381c: bf0c ite eq
  8989. 800381e: 2301 moveq r3, #1
  8990. 8003820: 2300 movne r3, #0
  8991. 8003822: b2db uxtb r3, r3
  8992. 8003824: 461a mov r2, r3
  8993. 8003826: 79fb ldrb r3, [r7, #7]
  8994. 8003828: 429a cmp r2, r3
  8995. 800382a: d19b bne.n 8003764 <SPI_WaitFlagStateUntilTimeout+0x38>
  8996. }
  8997. }
  8998. return HAL_OK;
  8999. 800382c: 2300 movs r3, #0
  9000. }
  9001. 800382e: 4618 mov r0, r3
  9002. 8003830: 3720 adds r7, #32
  9003. 8003832: 46bd mov sp, r7
  9004. 8003834: bd80 pop {r7, pc}
  9005. 8003836: bf00 nop
  9006. 8003838: 20000004 .word 0x20000004
  9007. 0800383c <SPI_EndRxTxTransaction>:
  9008. * @param Timeout Timeout duration
  9009. * @param Tickstart tick start value
  9010. * @retval HAL status
  9011. */
  9012. static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
  9013. {
  9014. 800383c: b580 push {r7, lr}
  9015. 800383e: b088 sub sp, #32
  9016. 8003840: af02 add r7, sp, #8
  9017. 8003842: 60f8 str r0, [r7, #12]
  9018. 8003844: 60b9 str r1, [r7, #8]
  9019. 8003846: 607a str r2, [r7, #4]
  9020. /* Timeout in µs */
  9021. __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
  9022. 8003848: 4b1b ldr r3, [pc, #108] ; (80038b8 <SPI_EndRxTxTransaction+0x7c>)
  9023. 800384a: 681b ldr r3, [r3, #0]
  9024. 800384c: 4a1b ldr r2, [pc, #108] ; (80038bc <SPI_EndRxTxTransaction+0x80>)
  9025. 800384e: fba2 2303 umull r2, r3, r2, r3
  9026. 8003852: 0d5b lsrs r3, r3, #21
  9027. 8003854: f44f 727a mov.w r2, #1000 ; 0x3e8
  9028. 8003858: fb02 f303 mul.w r3, r2, r3
  9029. 800385c: 617b str r3, [r7, #20]
  9030. /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
  9031. if (hspi->Init.Mode == SPI_MODE_MASTER)
  9032. 800385e: 68fb ldr r3, [r7, #12]
  9033. 8003860: 685b ldr r3, [r3, #4]
  9034. 8003862: f5b3 7f82 cmp.w r3, #260 ; 0x104
  9035. 8003866: d112 bne.n 800388e <SPI_EndRxTxTransaction+0x52>
  9036. {
  9037. /* Control the BSY flag */
  9038. if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
  9039. 8003868: 687b ldr r3, [r7, #4]
  9040. 800386a: 9300 str r3, [sp, #0]
  9041. 800386c: 68bb ldr r3, [r7, #8]
  9042. 800386e: 2200 movs r2, #0
  9043. 8003870: 2180 movs r1, #128 ; 0x80
  9044. 8003872: 68f8 ldr r0, [r7, #12]
  9045. 8003874: f7ff ff5a bl 800372c <SPI_WaitFlagStateUntilTimeout>
  9046. 8003878: 4603 mov r3, r0
  9047. 800387a: 2b00 cmp r3, #0
  9048. 800387c: d016 beq.n 80038ac <SPI_EndRxTxTransaction+0x70>
  9049. {
  9050. SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
  9051. 800387e: 68fb ldr r3, [r7, #12]
  9052. 8003880: 6d5b ldr r3, [r3, #84] ; 0x54
  9053. 8003882: f043 0220 orr.w r2, r3, #32
  9054. 8003886: 68fb ldr r3, [r7, #12]
  9055. 8003888: 655a str r2, [r3, #84] ; 0x54
  9056. return HAL_TIMEOUT;
  9057. 800388a: 2303 movs r3, #3
  9058. 800388c: e00f b.n 80038ae <SPI_EndRxTxTransaction+0x72>
  9059. * User have to calculate the timeout value to fit with the time of 1 byte transfer.
  9060. * This time is directly link with the SPI clock from Master device.
  9061. */
  9062. do
  9063. {
  9064. if (count == 0U)
  9065. 800388e: 697b ldr r3, [r7, #20]
  9066. 8003890: 2b00 cmp r3, #0
  9067. 8003892: d00a beq.n 80038aa <SPI_EndRxTxTransaction+0x6e>
  9068. {
  9069. break;
  9070. }
  9071. count--;
  9072. 8003894: 697b ldr r3, [r7, #20]
  9073. 8003896: 3b01 subs r3, #1
  9074. 8003898: 617b str r3, [r7, #20]
  9075. } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
  9076. 800389a: 68fb ldr r3, [r7, #12]
  9077. 800389c: 681b ldr r3, [r3, #0]
  9078. 800389e: 689b ldr r3, [r3, #8]
  9079. 80038a0: f003 0380 and.w r3, r3, #128 ; 0x80
  9080. 80038a4: 2b80 cmp r3, #128 ; 0x80
  9081. 80038a6: d0f2 beq.n 800388e <SPI_EndRxTxTransaction+0x52>
  9082. 80038a8: e000 b.n 80038ac <SPI_EndRxTxTransaction+0x70>
  9083. break;
  9084. 80038aa: bf00 nop
  9085. }
  9086. return HAL_OK;
  9087. 80038ac: 2300 movs r3, #0
  9088. }
  9089. 80038ae: 4618 mov r0, r3
  9090. 80038b0: 3718 adds r7, #24
  9091. 80038b2: 46bd mov sp, r7
  9092. 80038b4: bd80 pop {r7, pc}
  9093. 80038b6: bf00 nop
  9094. 80038b8: 20000004 .word 0x20000004
  9095. 80038bc: 165e9f81 .word 0x165e9f81
  9096. 080038c0 <HAL_UART_Init>:
  9097. * @param huart Pointer to a UART_HandleTypeDef structure that contains
  9098. * the configuration information for the specified UART module.
  9099. * @retval HAL status
  9100. */
  9101. HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
  9102. {
  9103. 80038c0: b580 push {r7, lr}
  9104. 80038c2: b082 sub sp, #8
  9105. 80038c4: af00 add r7, sp, #0
  9106. 80038c6: 6078 str r0, [r7, #4]
  9107. /* Check the UART handle allocation */
  9108. if (huart == NULL)
  9109. 80038c8: 687b ldr r3, [r7, #4]
  9110. 80038ca: 2b00 cmp r3, #0
  9111. 80038cc: d101 bne.n 80038d2 <HAL_UART_Init+0x12>
  9112. {
  9113. return HAL_ERROR;
  9114. 80038ce: 2301 movs r3, #1
  9115. 80038d0: e03f b.n 8003952 <HAL_UART_Init+0x92>
  9116. assert_param(IS_UART_INSTANCE(huart->Instance));
  9117. }
  9118. assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
  9119. assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
  9120. if (huart->gState == HAL_UART_STATE_RESET)
  9121. 80038d2: 687b ldr r3, [r7, #4]
  9122. 80038d4: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
  9123. 80038d8: b2db uxtb r3, r3
  9124. 80038da: 2b00 cmp r3, #0
  9125. 80038dc: d106 bne.n 80038ec <HAL_UART_Init+0x2c>
  9126. {
  9127. /* Allocate lock resource and initialize it */
  9128. huart->Lock = HAL_UNLOCKED;
  9129. 80038de: 687b ldr r3, [r7, #4]
  9130. 80038e0: 2200 movs r2, #0
  9131. 80038e2: f883 2038 strb.w r2, [r3, #56] ; 0x38
  9132. /* Init the low level hardware */
  9133. huart->MspInitCallback(huart);
  9134. #else
  9135. /* Init the low level hardware : GPIO, CLOCK */
  9136. HAL_UART_MspInit(huart);
  9137. 80038e6: 6878 ldr r0, [r7, #4]
  9138. 80038e8: f7fd fde4 bl 80014b4 <HAL_UART_MspInit>
  9139. #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  9140. }
  9141. huart->gState = HAL_UART_STATE_BUSY;
  9142. 80038ec: 687b ldr r3, [r7, #4]
  9143. 80038ee: 2224 movs r2, #36 ; 0x24
  9144. 80038f0: f883 2039 strb.w r2, [r3, #57] ; 0x39
  9145. /* Disable the peripheral */
  9146. __HAL_UART_DISABLE(huart);
  9147. 80038f4: 687b ldr r3, [r7, #4]
  9148. 80038f6: 681b ldr r3, [r3, #0]
  9149. 80038f8: 68da ldr r2, [r3, #12]
  9150. 80038fa: 687b ldr r3, [r7, #4]
  9151. 80038fc: 681b ldr r3, [r3, #0]
  9152. 80038fe: f422 5200 bic.w r2, r2, #8192 ; 0x2000
  9153. 8003902: 60da str r2, [r3, #12]
  9154. /* Set the UART Communication parameters */
  9155. UART_SetConfig(huart);
  9156. 8003904: 6878 ldr r0, [r7, #4]
  9157. 8003906: f000 f90b bl 8003b20 <UART_SetConfig>
  9158. /* In asynchronous mode, the following bits must be kept cleared:
  9159. - LINEN and CLKEN bits in the USART_CR2 register,
  9160. - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
  9161. CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
  9162. 800390a: 687b ldr r3, [r7, #4]
  9163. 800390c: 681b ldr r3, [r3, #0]
  9164. 800390e: 691a ldr r2, [r3, #16]
  9165. 8003910: 687b ldr r3, [r7, #4]
  9166. 8003912: 681b ldr r3, [r3, #0]
  9167. 8003914: f422 4290 bic.w r2, r2, #18432 ; 0x4800
  9168. 8003918: 611a str r2, [r3, #16]
  9169. CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
  9170. 800391a: 687b ldr r3, [r7, #4]
  9171. 800391c: 681b ldr r3, [r3, #0]
  9172. 800391e: 695a ldr r2, [r3, #20]
  9173. 8003920: 687b ldr r3, [r7, #4]
  9174. 8003922: 681b ldr r3, [r3, #0]
  9175. 8003924: f022 022a bic.w r2, r2, #42 ; 0x2a
  9176. 8003928: 615a str r2, [r3, #20]
  9177. /* Enable the peripheral */
  9178. __HAL_UART_ENABLE(huart);
  9179. 800392a: 687b ldr r3, [r7, #4]
  9180. 800392c: 681b ldr r3, [r3, #0]
  9181. 800392e: 68da ldr r2, [r3, #12]
  9182. 8003930: 687b ldr r3, [r7, #4]
  9183. 8003932: 681b ldr r3, [r3, #0]
  9184. 8003934: f442 5200 orr.w r2, r2, #8192 ; 0x2000
  9185. 8003938: 60da str r2, [r3, #12]
  9186. /* Initialize the UART state */
  9187. huart->ErrorCode = HAL_UART_ERROR_NONE;
  9188. 800393a: 687b ldr r3, [r7, #4]
  9189. 800393c: 2200 movs r2, #0
  9190. 800393e: 63da str r2, [r3, #60] ; 0x3c
  9191. huart->gState = HAL_UART_STATE_READY;
  9192. 8003940: 687b ldr r3, [r7, #4]
  9193. 8003942: 2220 movs r2, #32
  9194. 8003944: f883 2039 strb.w r2, [r3, #57] ; 0x39
  9195. huart->RxState = HAL_UART_STATE_READY;
  9196. 8003948: 687b ldr r3, [r7, #4]
  9197. 800394a: 2220 movs r2, #32
  9198. 800394c: f883 203a strb.w r2, [r3, #58] ; 0x3a
  9199. return HAL_OK;
  9200. 8003950: 2300 movs r3, #0
  9201. }
  9202. 8003952: 4618 mov r0, r3
  9203. 8003954: 3708 adds r7, #8
  9204. 8003956: 46bd mov sp, r7
  9205. 8003958: bd80 pop {r7, pc}
  9206. 0800395a <HAL_UART_Transmit>:
  9207. * @param Size Amount of data elements (u8 or u16) to be sent
  9208. * @param Timeout Timeout duration
  9209. * @retval HAL status
  9210. */
  9211. HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
  9212. {
  9213. 800395a: b580 push {r7, lr}
  9214. 800395c: b088 sub sp, #32
  9215. 800395e: af02 add r7, sp, #8
  9216. 8003960: 60f8 str r0, [r7, #12]
  9217. 8003962: 60b9 str r1, [r7, #8]
  9218. 8003964: 603b str r3, [r7, #0]
  9219. 8003966: 4613 mov r3, r2
  9220. 8003968: 80fb strh r3, [r7, #6]
  9221. uint16_t *tmp;
  9222. uint32_t tickstart = 0U;
  9223. 800396a: 2300 movs r3, #0
  9224. 800396c: 617b str r3, [r7, #20]
  9225. /* Check that a Tx process is not already ongoing */
  9226. if (huart->gState == HAL_UART_STATE_READY)
  9227. 800396e: 68fb ldr r3, [r7, #12]
  9228. 8003970: f893 3039 ldrb.w r3, [r3, #57] ; 0x39
  9229. 8003974: b2db uxtb r3, r3
  9230. 8003976: 2b20 cmp r3, #32
  9231. 8003978: f040 8083 bne.w 8003a82 <HAL_UART_Transmit+0x128>
  9232. {
  9233. if ((pData == NULL) || (Size == 0U))
  9234. 800397c: 68bb ldr r3, [r7, #8]
  9235. 800397e: 2b00 cmp r3, #0
  9236. 8003980: d002 beq.n 8003988 <HAL_UART_Transmit+0x2e>
  9237. 8003982: 88fb ldrh r3, [r7, #6]
  9238. 8003984: 2b00 cmp r3, #0
  9239. 8003986: d101 bne.n 800398c <HAL_UART_Transmit+0x32>
  9240. {
  9241. return HAL_ERROR;
  9242. 8003988: 2301 movs r3, #1
  9243. 800398a: e07b b.n 8003a84 <HAL_UART_Transmit+0x12a>
  9244. }
  9245. /* Process Locked */
  9246. __HAL_LOCK(huart);
  9247. 800398c: 68fb ldr r3, [r7, #12]
  9248. 800398e: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
  9249. 8003992: 2b01 cmp r3, #1
  9250. 8003994: d101 bne.n 800399a <HAL_UART_Transmit+0x40>
  9251. 8003996: 2302 movs r3, #2
  9252. 8003998: e074 b.n 8003a84 <HAL_UART_Transmit+0x12a>
  9253. 800399a: 68fb ldr r3, [r7, #12]
  9254. 800399c: 2201 movs r2, #1
  9255. 800399e: f883 2038 strb.w r2, [r3, #56] ; 0x38
  9256. huart->ErrorCode = HAL_UART_ERROR_NONE;
  9257. 80039a2: 68fb ldr r3, [r7, #12]
  9258. 80039a4: 2200 movs r2, #0
  9259. 80039a6: 63da str r2, [r3, #60] ; 0x3c
  9260. huart->gState = HAL_UART_STATE_BUSY_TX;
  9261. 80039a8: 68fb ldr r3, [r7, #12]
  9262. 80039aa: 2221 movs r2, #33 ; 0x21
  9263. 80039ac: f883 2039 strb.w r2, [r3, #57] ; 0x39
  9264. /* Init tickstart for timeout managment */
  9265. tickstart = HAL_GetTick();
  9266. 80039b0: f7fd fed4 bl 800175c <HAL_GetTick>
  9267. 80039b4: 6178 str r0, [r7, #20]
  9268. huart->TxXferSize = Size;
  9269. 80039b6: 68fb ldr r3, [r7, #12]
  9270. 80039b8: 88fa ldrh r2, [r7, #6]
  9271. 80039ba: 849a strh r2, [r3, #36] ; 0x24
  9272. huart->TxXferCount = Size;
  9273. 80039bc: 68fb ldr r3, [r7, #12]
  9274. 80039be: 88fa ldrh r2, [r7, #6]
  9275. 80039c0: 84da strh r2, [r3, #38] ; 0x26
  9276. /* Process Unlocked */
  9277. __HAL_UNLOCK(huart);
  9278. 80039c2: 68fb ldr r3, [r7, #12]
  9279. 80039c4: 2200 movs r2, #0
  9280. 80039c6: f883 2038 strb.w r2, [r3, #56] ; 0x38
  9281. while (huart->TxXferCount > 0U)
  9282. 80039ca: e042 b.n 8003a52 <HAL_UART_Transmit+0xf8>
  9283. {
  9284. huart->TxXferCount--;
  9285. 80039cc: 68fb ldr r3, [r7, #12]
  9286. 80039ce: 8cdb ldrh r3, [r3, #38] ; 0x26
  9287. 80039d0: b29b uxth r3, r3
  9288. 80039d2: 3b01 subs r3, #1
  9289. 80039d4: b29a uxth r2, r3
  9290. 80039d6: 68fb ldr r3, [r7, #12]
  9291. 80039d8: 84da strh r2, [r3, #38] ; 0x26
  9292. if (huart->Init.WordLength == UART_WORDLENGTH_9B)
  9293. 80039da: 68fb ldr r3, [r7, #12]
  9294. 80039dc: 689b ldr r3, [r3, #8]
  9295. 80039de: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  9296. 80039e2: d122 bne.n 8003a2a <HAL_UART_Transmit+0xd0>
  9297. {
  9298. if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  9299. 80039e4: 683b ldr r3, [r7, #0]
  9300. 80039e6: 9300 str r3, [sp, #0]
  9301. 80039e8: 697b ldr r3, [r7, #20]
  9302. 80039ea: 2200 movs r2, #0
  9303. 80039ec: 2180 movs r1, #128 ; 0x80
  9304. 80039ee: 68f8 ldr r0, [r7, #12]
  9305. 80039f0: f000 f84c bl 8003a8c <UART_WaitOnFlagUntilTimeout>
  9306. 80039f4: 4603 mov r3, r0
  9307. 80039f6: 2b00 cmp r3, #0
  9308. 80039f8: d001 beq.n 80039fe <HAL_UART_Transmit+0xa4>
  9309. {
  9310. return HAL_TIMEOUT;
  9311. 80039fa: 2303 movs r3, #3
  9312. 80039fc: e042 b.n 8003a84 <HAL_UART_Transmit+0x12a>
  9313. }
  9314. tmp = (uint16_t *) pData;
  9315. 80039fe: 68bb ldr r3, [r7, #8]
  9316. 8003a00: 613b str r3, [r7, #16]
  9317. huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
  9318. 8003a02: 693b ldr r3, [r7, #16]
  9319. 8003a04: 881b ldrh r3, [r3, #0]
  9320. 8003a06: 461a mov r2, r3
  9321. 8003a08: 68fb ldr r3, [r7, #12]
  9322. 8003a0a: 681b ldr r3, [r3, #0]
  9323. 8003a0c: f3c2 0208 ubfx r2, r2, #0, #9
  9324. 8003a10: 605a str r2, [r3, #4]
  9325. if (huart->Init.Parity == UART_PARITY_NONE)
  9326. 8003a12: 68fb ldr r3, [r7, #12]
  9327. 8003a14: 691b ldr r3, [r3, #16]
  9328. 8003a16: 2b00 cmp r3, #0
  9329. 8003a18: d103 bne.n 8003a22 <HAL_UART_Transmit+0xc8>
  9330. {
  9331. pData += 2U;
  9332. 8003a1a: 68bb ldr r3, [r7, #8]
  9333. 8003a1c: 3302 adds r3, #2
  9334. 8003a1e: 60bb str r3, [r7, #8]
  9335. 8003a20: e017 b.n 8003a52 <HAL_UART_Transmit+0xf8>
  9336. }
  9337. else
  9338. {
  9339. pData += 1U;
  9340. 8003a22: 68bb ldr r3, [r7, #8]
  9341. 8003a24: 3301 adds r3, #1
  9342. 8003a26: 60bb str r3, [r7, #8]
  9343. 8003a28: e013 b.n 8003a52 <HAL_UART_Transmit+0xf8>
  9344. }
  9345. }
  9346. else
  9347. {
  9348. if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
  9349. 8003a2a: 683b ldr r3, [r7, #0]
  9350. 8003a2c: 9300 str r3, [sp, #0]
  9351. 8003a2e: 697b ldr r3, [r7, #20]
  9352. 8003a30: 2200 movs r2, #0
  9353. 8003a32: 2180 movs r1, #128 ; 0x80
  9354. 8003a34: 68f8 ldr r0, [r7, #12]
  9355. 8003a36: f000 f829 bl 8003a8c <UART_WaitOnFlagUntilTimeout>
  9356. 8003a3a: 4603 mov r3, r0
  9357. 8003a3c: 2b00 cmp r3, #0
  9358. 8003a3e: d001 beq.n 8003a44 <HAL_UART_Transmit+0xea>
  9359. {
  9360. return HAL_TIMEOUT;
  9361. 8003a40: 2303 movs r3, #3
  9362. 8003a42: e01f b.n 8003a84 <HAL_UART_Transmit+0x12a>
  9363. }
  9364. huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
  9365. 8003a44: 68bb ldr r3, [r7, #8]
  9366. 8003a46: 1c5a adds r2, r3, #1
  9367. 8003a48: 60ba str r2, [r7, #8]
  9368. 8003a4a: 781a ldrb r2, [r3, #0]
  9369. 8003a4c: 68fb ldr r3, [r7, #12]
  9370. 8003a4e: 681b ldr r3, [r3, #0]
  9371. 8003a50: 605a str r2, [r3, #4]
  9372. while (huart->TxXferCount > 0U)
  9373. 8003a52: 68fb ldr r3, [r7, #12]
  9374. 8003a54: 8cdb ldrh r3, [r3, #38] ; 0x26
  9375. 8003a56: b29b uxth r3, r3
  9376. 8003a58: 2b00 cmp r3, #0
  9377. 8003a5a: d1b7 bne.n 80039cc <HAL_UART_Transmit+0x72>
  9378. }
  9379. }
  9380. if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
  9381. 8003a5c: 683b ldr r3, [r7, #0]
  9382. 8003a5e: 9300 str r3, [sp, #0]
  9383. 8003a60: 697b ldr r3, [r7, #20]
  9384. 8003a62: 2200 movs r2, #0
  9385. 8003a64: 2140 movs r1, #64 ; 0x40
  9386. 8003a66: 68f8 ldr r0, [r7, #12]
  9387. 8003a68: f000 f810 bl 8003a8c <UART_WaitOnFlagUntilTimeout>
  9388. 8003a6c: 4603 mov r3, r0
  9389. 8003a6e: 2b00 cmp r3, #0
  9390. 8003a70: d001 beq.n 8003a76 <HAL_UART_Transmit+0x11c>
  9391. {
  9392. return HAL_TIMEOUT;
  9393. 8003a72: 2303 movs r3, #3
  9394. 8003a74: e006 b.n 8003a84 <HAL_UART_Transmit+0x12a>
  9395. }
  9396. /* At end of Tx process, restore huart->gState to Ready */
  9397. huart->gState = HAL_UART_STATE_READY;
  9398. 8003a76: 68fb ldr r3, [r7, #12]
  9399. 8003a78: 2220 movs r2, #32
  9400. 8003a7a: f883 2039 strb.w r2, [r3, #57] ; 0x39
  9401. return HAL_OK;
  9402. 8003a7e: 2300 movs r3, #0
  9403. 8003a80: e000 b.n 8003a84 <HAL_UART_Transmit+0x12a>
  9404. }
  9405. else
  9406. {
  9407. return HAL_BUSY;
  9408. 8003a82: 2302 movs r3, #2
  9409. }
  9410. }
  9411. 8003a84: 4618 mov r0, r3
  9412. 8003a86: 3718 adds r7, #24
  9413. 8003a88: 46bd mov sp, r7
  9414. 8003a8a: bd80 pop {r7, pc}
  9415. 08003a8c <UART_WaitOnFlagUntilTimeout>:
  9416. * @param Tickstart Tick start value
  9417. * @param Timeout Timeout duration
  9418. * @retval HAL status
  9419. */
  9420. static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
  9421. {
  9422. 8003a8c: b580 push {r7, lr}
  9423. 8003a8e: b084 sub sp, #16
  9424. 8003a90: af00 add r7, sp, #0
  9425. 8003a92: 60f8 str r0, [r7, #12]
  9426. 8003a94: 60b9 str r1, [r7, #8]
  9427. 8003a96: 603b str r3, [r7, #0]
  9428. 8003a98: 4613 mov r3, r2
  9429. 8003a9a: 71fb strb r3, [r7, #7]
  9430. /* Wait until flag is set */
  9431. while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  9432. 8003a9c: e02c b.n 8003af8 <UART_WaitOnFlagUntilTimeout+0x6c>
  9433. {
  9434. /* Check for the Timeout */
  9435. if (Timeout != HAL_MAX_DELAY)
  9436. 8003a9e: 69bb ldr r3, [r7, #24]
  9437. 8003aa0: f1b3 3fff cmp.w r3, #4294967295
  9438. 8003aa4: d028 beq.n 8003af8 <UART_WaitOnFlagUntilTimeout+0x6c>
  9439. {
  9440. if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
  9441. 8003aa6: 69bb ldr r3, [r7, #24]
  9442. 8003aa8: 2b00 cmp r3, #0
  9443. 8003aaa: d007 beq.n 8003abc <UART_WaitOnFlagUntilTimeout+0x30>
  9444. 8003aac: f7fd fe56 bl 800175c <HAL_GetTick>
  9445. 8003ab0: 4602 mov r2, r0
  9446. 8003ab2: 683b ldr r3, [r7, #0]
  9447. 8003ab4: 1ad3 subs r3, r2, r3
  9448. 8003ab6: 69ba ldr r2, [r7, #24]
  9449. 8003ab8: 429a cmp r2, r3
  9450. 8003aba: d21d bcs.n 8003af8 <UART_WaitOnFlagUntilTimeout+0x6c>
  9451. {
  9452. /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
  9453. CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
  9454. 8003abc: 68fb ldr r3, [r7, #12]
  9455. 8003abe: 681b ldr r3, [r3, #0]
  9456. 8003ac0: 68da ldr r2, [r3, #12]
  9457. 8003ac2: 68fb ldr r3, [r7, #12]
  9458. 8003ac4: 681b ldr r3, [r3, #0]
  9459. 8003ac6: f422 72d0 bic.w r2, r2, #416 ; 0x1a0
  9460. 8003aca: 60da str r2, [r3, #12]
  9461. CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
  9462. 8003acc: 68fb ldr r3, [r7, #12]
  9463. 8003ace: 681b ldr r3, [r3, #0]
  9464. 8003ad0: 695a ldr r2, [r3, #20]
  9465. 8003ad2: 68fb ldr r3, [r7, #12]
  9466. 8003ad4: 681b ldr r3, [r3, #0]
  9467. 8003ad6: f022 0201 bic.w r2, r2, #1
  9468. 8003ada: 615a str r2, [r3, #20]
  9469. huart->gState = HAL_UART_STATE_READY;
  9470. 8003adc: 68fb ldr r3, [r7, #12]
  9471. 8003ade: 2220 movs r2, #32
  9472. 8003ae0: f883 2039 strb.w r2, [r3, #57] ; 0x39
  9473. huart->RxState = HAL_UART_STATE_READY;
  9474. 8003ae4: 68fb ldr r3, [r7, #12]
  9475. 8003ae6: 2220 movs r2, #32
  9476. 8003ae8: f883 203a strb.w r2, [r3, #58] ; 0x3a
  9477. /* Process Unlocked */
  9478. __HAL_UNLOCK(huart);
  9479. 8003aec: 68fb ldr r3, [r7, #12]
  9480. 8003aee: 2200 movs r2, #0
  9481. 8003af0: f883 2038 strb.w r2, [r3, #56] ; 0x38
  9482. return HAL_TIMEOUT;
  9483. 8003af4: 2303 movs r3, #3
  9484. 8003af6: e00f b.n 8003b18 <UART_WaitOnFlagUntilTimeout+0x8c>
  9485. while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
  9486. 8003af8: 68fb ldr r3, [r7, #12]
  9487. 8003afa: 681b ldr r3, [r3, #0]
  9488. 8003afc: 681a ldr r2, [r3, #0]
  9489. 8003afe: 68bb ldr r3, [r7, #8]
  9490. 8003b00: 4013 ands r3, r2
  9491. 8003b02: 68ba ldr r2, [r7, #8]
  9492. 8003b04: 429a cmp r2, r3
  9493. 8003b06: bf0c ite eq
  9494. 8003b08: 2301 moveq r3, #1
  9495. 8003b0a: 2300 movne r3, #0
  9496. 8003b0c: b2db uxtb r3, r3
  9497. 8003b0e: 461a mov r2, r3
  9498. 8003b10: 79fb ldrb r3, [r7, #7]
  9499. 8003b12: 429a cmp r2, r3
  9500. 8003b14: d0c3 beq.n 8003a9e <UART_WaitOnFlagUntilTimeout+0x12>
  9501. }
  9502. }
  9503. }
  9504. return HAL_OK;
  9505. 8003b16: 2300 movs r3, #0
  9506. }
  9507. 8003b18: 4618 mov r0, r3
  9508. 8003b1a: 3710 adds r7, #16
  9509. 8003b1c: 46bd mov sp, r7
  9510. 8003b1e: bd80 pop {r7, pc}
  9511. 08003b20 <UART_SetConfig>:
  9512. * @param huart Pointer to a UART_HandleTypeDef structure that contains
  9513. * the configuration information for the specified UART module.
  9514. * @retval None
  9515. */
  9516. static void UART_SetConfig(UART_HandleTypeDef *huart)
  9517. {
  9518. 8003b20: b580 push {r7, lr}
  9519. 8003b22: b084 sub sp, #16
  9520. 8003b24: af00 add r7, sp, #0
  9521. 8003b26: 6078 str r0, [r7, #4]
  9522. assert_param(IS_UART_MODE(huart->Init.Mode));
  9523. /*-------------------------- USART CR2 Configuration -----------------------*/
  9524. /* Configure the UART Stop Bits: Set STOP[13:12] bits
  9525. according to huart->Init.StopBits value */
  9526. MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
  9527. 8003b28: 687b ldr r3, [r7, #4]
  9528. 8003b2a: 681b ldr r3, [r3, #0]
  9529. 8003b2c: 691b ldr r3, [r3, #16]
  9530. 8003b2e: f423 5140 bic.w r1, r3, #12288 ; 0x3000
  9531. 8003b32: 687b ldr r3, [r7, #4]
  9532. 8003b34: 68da ldr r2, [r3, #12]
  9533. 8003b36: 687b ldr r3, [r7, #4]
  9534. 8003b38: 681b ldr r3, [r3, #0]
  9535. 8003b3a: 430a orrs r2, r1
  9536. 8003b3c: 611a str r2, [r3, #16]
  9537. Set the M bits according to huart->Init.WordLength value
  9538. Set PCE and PS bits according to huart->Init.Parity value
  9539. Set TE and RE bits according to huart->Init.Mode value
  9540. Set OVER8 bit according to huart->Init.OverSampling value */
  9541. tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
  9542. 8003b3e: 687b ldr r3, [r7, #4]
  9543. 8003b40: 689a ldr r2, [r3, #8]
  9544. 8003b42: 687b ldr r3, [r7, #4]
  9545. 8003b44: 691b ldr r3, [r3, #16]
  9546. 8003b46: 431a orrs r2, r3
  9547. 8003b48: 687b ldr r3, [r7, #4]
  9548. 8003b4a: 695b ldr r3, [r3, #20]
  9549. 8003b4c: 431a orrs r2, r3
  9550. 8003b4e: 687b ldr r3, [r7, #4]
  9551. 8003b50: 69db ldr r3, [r3, #28]
  9552. 8003b52: 4313 orrs r3, r2
  9553. 8003b54: 60bb str r3, [r7, #8]
  9554. MODIFY_REG(huart->Instance->CR1,
  9555. 8003b56: 687b ldr r3, [r7, #4]
  9556. 8003b58: 681b ldr r3, [r3, #0]
  9557. 8003b5a: 68db ldr r3, [r3, #12]
  9558. 8003b5c: f423 4316 bic.w r3, r3, #38400 ; 0x9600
  9559. 8003b60: f023 030c bic.w r3, r3, #12
  9560. 8003b64: 687a ldr r2, [r7, #4]
  9561. 8003b66: 6812 ldr r2, [r2, #0]
  9562. 8003b68: 68b9 ldr r1, [r7, #8]
  9563. 8003b6a: 430b orrs r3, r1
  9564. 8003b6c: 60d3 str r3, [r2, #12]
  9565. (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
  9566. tmpreg);
  9567. /*-------------------------- USART CR3 Configuration -----------------------*/
  9568. /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  9569. MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
  9570. 8003b6e: 687b ldr r3, [r7, #4]
  9571. 8003b70: 681b ldr r3, [r3, #0]
  9572. 8003b72: 695b ldr r3, [r3, #20]
  9573. 8003b74: f423 7140 bic.w r1, r3, #768 ; 0x300
  9574. 8003b78: 687b ldr r3, [r7, #4]
  9575. 8003b7a: 699a ldr r2, [r3, #24]
  9576. 8003b7c: 687b ldr r3, [r7, #4]
  9577. 8003b7e: 681b ldr r3, [r3, #0]
  9578. 8003b80: 430a orrs r2, r1
  9579. 8003b82: 615a str r2, [r3, #20]
  9580. if((huart->Instance == USART1))
  9581. 8003b84: 687b ldr r3, [r7, #4]
  9582. 8003b86: 681b ldr r3, [r3, #0]
  9583. 8003b88: 4a55 ldr r2, [pc, #340] ; (8003ce0 <UART_SetConfig+0x1c0>)
  9584. 8003b8a: 4293 cmp r3, r2
  9585. 8003b8c: d103 bne.n 8003b96 <UART_SetConfig+0x76>
  9586. {
  9587. pclk = HAL_RCC_GetPCLK2Freq();
  9588. 8003b8e: f7ff f9f1 bl 8002f74 <HAL_RCC_GetPCLK2Freq>
  9589. 8003b92: 60f8 str r0, [r7, #12]
  9590. 8003b94: e002 b.n 8003b9c <UART_SetConfig+0x7c>
  9591. }
  9592. else
  9593. {
  9594. pclk = HAL_RCC_GetPCLK1Freq();
  9595. 8003b96: f7ff f9d9 bl 8002f4c <HAL_RCC_GetPCLK1Freq>
  9596. 8003b9a: 60f8 str r0, [r7, #12]
  9597. }
  9598. /*-------------------------- USART BRR Configuration ---------------------*/
  9599. if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
  9600. 8003b9c: 687b ldr r3, [r7, #4]
  9601. 8003b9e: 69db ldr r3, [r3, #28]
  9602. 8003ba0: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
  9603. 8003ba4: d14c bne.n 8003c40 <UART_SetConfig+0x120>
  9604. {
  9605. huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
  9606. 8003ba6: 68fa ldr r2, [r7, #12]
  9607. 8003ba8: 4613 mov r3, r2
  9608. 8003baa: 009b lsls r3, r3, #2
  9609. 8003bac: 4413 add r3, r2
  9610. 8003bae: 009a lsls r2, r3, #2
  9611. 8003bb0: 441a add r2, r3
  9612. 8003bb2: 687b ldr r3, [r7, #4]
  9613. 8003bb4: 685b ldr r3, [r3, #4]
  9614. 8003bb6: 005b lsls r3, r3, #1
  9615. 8003bb8: fbb2 f3f3 udiv r3, r2, r3
  9616. 8003bbc: 4a49 ldr r2, [pc, #292] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9617. 8003bbe: fba2 2303 umull r2, r3, r2, r3
  9618. 8003bc2: 095b lsrs r3, r3, #5
  9619. 8003bc4: 0119 lsls r1, r3, #4
  9620. 8003bc6: 68fa ldr r2, [r7, #12]
  9621. 8003bc8: 4613 mov r3, r2
  9622. 8003bca: 009b lsls r3, r3, #2
  9623. 8003bcc: 4413 add r3, r2
  9624. 8003bce: 009a lsls r2, r3, #2
  9625. 8003bd0: 441a add r2, r3
  9626. 8003bd2: 687b ldr r3, [r7, #4]
  9627. 8003bd4: 685b ldr r3, [r3, #4]
  9628. 8003bd6: 005b lsls r3, r3, #1
  9629. 8003bd8: fbb2 f2f3 udiv r2, r2, r3
  9630. 8003bdc: 4b41 ldr r3, [pc, #260] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9631. 8003bde: fba3 0302 umull r0, r3, r3, r2
  9632. 8003be2: 095b lsrs r3, r3, #5
  9633. 8003be4: 2064 movs r0, #100 ; 0x64
  9634. 8003be6: fb00 f303 mul.w r3, r0, r3
  9635. 8003bea: 1ad3 subs r3, r2, r3
  9636. 8003bec: 00db lsls r3, r3, #3
  9637. 8003bee: 3332 adds r3, #50 ; 0x32
  9638. 8003bf0: 4a3c ldr r2, [pc, #240] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9639. 8003bf2: fba2 2303 umull r2, r3, r2, r3
  9640. 8003bf6: 095b lsrs r3, r3, #5
  9641. 8003bf8: 005b lsls r3, r3, #1
  9642. 8003bfa: f403 73f8 and.w r3, r3, #496 ; 0x1f0
  9643. 8003bfe: 4419 add r1, r3
  9644. 8003c00: 68fa ldr r2, [r7, #12]
  9645. 8003c02: 4613 mov r3, r2
  9646. 8003c04: 009b lsls r3, r3, #2
  9647. 8003c06: 4413 add r3, r2
  9648. 8003c08: 009a lsls r2, r3, #2
  9649. 8003c0a: 441a add r2, r3
  9650. 8003c0c: 687b ldr r3, [r7, #4]
  9651. 8003c0e: 685b ldr r3, [r3, #4]
  9652. 8003c10: 005b lsls r3, r3, #1
  9653. 8003c12: fbb2 f2f3 udiv r2, r2, r3
  9654. 8003c16: 4b33 ldr r3, [pc, #204] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9655. 8003c18: fba3 0302 umull r0, r3, r3, r2
  9656. 8003c1c: 095b lsrs r3, r3, #5
  9657. 8003c1e: 2064 movs r0, #100 ; 0x64
  9658. 8003c20: fb00 f303 mul.w r3, r0, r3
  9659. 8003c24: 1ad3 subs r3, r2, r3
  9660. 8003c26: 00db lsls r3, r3, #3
  9661. 8003c28: 3332 adds r3, #50 ; 0x32
  9662. 8003c2a: 4a2e ldr r2, [pc, #184] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9663. 8003c2c: fba2 2303 umull r2, r3, r2, r3
  9664. 8003c30: 095b lsrs r3, r3, #5
  9665. 8003c32: f003 0207 and.w r2, r3, #7
  9666. 8003c36: 687b ldr r3, [r7, #4]
  9667. 8003c38: 681b ldr r3, [r3, #0]
  9668. 8003c3a: 440a add r2, r1
  9669. 8003c3c: 609a str r2, [r3, #8]
  9670. }
  9671. else
  9672. {
  9673. huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  9674. }
  9675. }
  9676. 8003c3e: e04a b.n 8003cd6 <UART_SetConfig+0x1b6>
  9677. huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  9678. 8003c40: 68fa ldr r2, [r7, #12]
  9679. 8003c42: 4613 mov r3, r2
  9680. 8003c44: 009b lsls r3, r3, #2
  9681. 8003c46: 4413 add r3, r2
  9682. 8003c48: 009a lsls r2, r3, #2
  9683. 8003c4a: 441a add r2, r3
  9684. 8003c4c: 687b ldr r3, [r7, #4]
  9685. 8003c4e: 685b ldr r3, [r3, #4]
  9686. 8003c50: 009b lsls r3, r3, #2
  9687. 8003c52: fbb2 f3f3 udiv r3, r2, r3
  9688. 8003c56: 4a23 ldr r2, [pc, #140] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9689. 8003c58: fba2 2303 umull r2, r3, r2, r3
  9690. 8003c5c: 095b lsrs r3, r3, #5
  9691. 8003c5e: 0119 lsls r1, r3, #4
  9692. 8003c60: 68fa ldr r2, [r7, #12]
  9693. 8003c62: 4613 mov r3, r2
  9694. 8003c64: 009b lsls r3, r3, #2
  9695. 8003c66: 4413 add r3, r2
  9696. 8003c68: 009a lsls r2, r3, #2
  9697. 8003c6a: 441a add r2, r3
  9698. 8003c6c: 687b ldr r3, [r7, #4]
  9699. 8003c6e: 685b ldr r3, [r3, #4]
  9700. 8003c70: 009b lsls r3, r3, #2
  9701. 8003c72: fbb2 f2f3 udiv r2, r2, r3
  9702. 8003c76: 4b1b ldr r3, [pc, #108] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9703. 8003c78: fba3 0302 umull r0, r3, r3, r2
  9704. 8003c7c: 095b lsrs r3, r3, #5
  9705. 8003c7e: 2064 movs r0, #100 ; 0x64
  9706. 8003c80: fb00 f303 mul.w r3, r0, r3
  9707. 8003c84: 1ad3 subs r3, r2, r3
  9708. 8003c86: 011b lsls r3, r3, #4
  9709. 8003c88: 3332 adds r3, #50 ; 0x32
  9710. 8003c8a: 4a16 ldr r2, [pc, #88] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9711. 8003c8c: fba2 2303 umull r2, r3, r2, r3
  9712. 8003c90: 095b lsrs r3, r3, #5
  9713. 8003c92: f003 03f0 and.w r3, r3, #240 ; 0xf0
  9714. 8003c96: 4419 add r1, r3
  9715. 8003c98: 68fa ldr r2, [r7, #12]
  9716. 8003c9a: 4613 mov r3, r2
  9717. 8003c9c: 009b lsls r3, r3, #2
  9718. 8003c9e: 4413 add r3, r2
  9719. 8003ca0: 009a lsls r2, r3, #2
  9720. 8003ca2: 441a add r2, r3
  9721. 8003ca4: 687b ldr r3, [r7, #4]
  9722. 8003ca6: 685b ldr r3, [r3, #4]
  9723. 8003ca8: 009b lsls r3, r3, #2
  9724. 8003caa: fbb2 f2f3 udiv r2, r2, r3
  9725. 8003cae: 4b0d ldr r3, [pc, #52] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9726. 8003cb0: fba3 0302 umull r0, r3, r3, r2
  9727. 8003cb4: 095b lsrs r3, r3, #5
  9728. 8003cb6: 2064 movs r0, #100 ; 0x64
  9729. 8003cb8: fb00 f303 mul.w r3, r0, r3
  9730. 8003cbc: 1ad3 subs r3, r2, r3
  9731. 8003cbe: 011b lsls r3, r3, #4
  9732. 8003cc0: 3332 adds r3, #50 ; 0x32
  9733. 8003cc2: 4a08 ldr r2, [pc, #32] ; (8003ce4 <UART_SetConfig+0x1c4>)
  9734. 8003cc4: fba2 2303 umull r2, r3, r2, r3
  9735. 8003cc8: 095b lsrs r3, r3, #5
  9736. 8003cca: f003 020f and.w r2, r3, #15
  9737. 8003cce: 687b ldr r3, [r7, #4]
  9738. 8003cd0: 681b ldr r3, [r3, #0]
  9739. 8003cd2: 440a add r2, r1
  9740. 8003cd4: 609a str r2, [r3, #8]
  9741. }
  9742. 8003cd6: bf00 nop
  9743. 8003cd8: 3710 adds r7, #16
  9744. 8003cda: 46bd mov sp, r7
  9745. 8003cdc: bd80 pop {r7, pc}
  9746. 8003cde: bf00 nop
  9747. 8003ce0: 40013800 .word 0x40013800
  9748. 8003ce4: 51eb851f .word 0x51eb851f
  9749. 08003ce8 <MX_FATFS_Init>:
  9750. /* USER CODE BEGIN Variables */
  9751. /* USER CODE END Variables */
  9752. void MX_FATFS_Init(void)
  9753. {
  9754. 8003ce8: b580 push {r7, lr}
  9755. 8003cea: af00 add r7, sp, #0
  9756. /*## FatFS: Link the USER driver ###########################*/
  9757. retUSER = FATFS_LinkDriver(&USER_Driver, USERPath);
  9758. 8003cec: 4904 ldr r1, [pc, #16] ; (8003d00 <MX_FATFS_Init+0x18>)
  9759. 8003cee: 4805 ldr r0, [pc, #20] ; (8003d04 <MX_FATFS_Init+0x1c>)
  9760. 8003cf0: f003 f97c bl 8006fec <FATFS_LinkDriver>
  9761. 8003cf4: 4603 mov r3, r0
  9762. 8003cf6: 461a mov r2, r3
  9763. 8003cf8: 4b03 ldr r3, [pc, #12] ; (8003d08 <MX_FATFS_Init+0x20>)
  9764. 8003cfa: 701a strb r2, [r3, #0]
  9765. /* USER CODE BEGIN Init */
  9766. /* additional user code for init */
  9767. /* USER CODE END Init */
  9768. }
  9769. 8003cfc: bf00 nop
  9770. 8003cfe: bd80 pop {r7, pc}
  9771. 8003d00: 200024e0 .word 0x200024e0
  9772. 8003d04: 20000010 .word 0x20000010
  9773. 8003d08: 200024e4 .word 0x200024e4
  9774. 08003d0c <get_fattime>:
  9775. * @brief Gets Time from RTC
  9776. * @param None
  9777. * @retval Time in DWORD
  9778. */
  9779. DWORD get_fattime(void)
  9780. {
  9781. 8003d0c: b480 push {r7}
  9782. 8003d0e: af00 add r7, sp, #0
  9783. /* USER CODE BEGIN get_fattime */
  9784. return 0;
  9785. 8003d10: 2300 movs r3, #0
  9786. /* USER CODE END get_fattime */
  9787. }
  9788. 8003d12: 4618 mov r0, r3
  9789. 8003d14: 46bd mov sp, r7
  9790. 8003d16: bc80 pop {r7}
  9791. 8003d18: 4770 bx lr
  9792. 08003d1a <USER_initialize>:
  9793. * @retval DSTATUS: Operation status
  9794. */
  9795. DSTATUS USER_initialize (
  9796. BYTE pdrv /* Physical drive nmuber to identify the drive */
  9797. )
  9798. {
  9799. 8003d1a: b580 push {r7, lr}
  9800. 8003d1c: b082 sub sp, #8
  9801. 8003d1e: af00 add r7, sp, #0
  9802. 8003d20: 4603 mov r3, r0
  9803. 8003d22: 71fb strb r3, [r7, #7]
  9804. /* USER CODE BEGIN INIT */
  9805. //Stat = STA_NOINIT;
  9806. //return Stat;
  9807. SD_disk_initialize (pdrv);
  9808. 8003d24: 79fb ldrb r3, [r7, #7]
  9809. 8003d26: 4618 mov r0, r3
  9810. 8003d28: f7fc fd64 bl 80007f4 <SD_disk_initialize>
  9811. /* USER CODE END INIT */
  9812. }
  9813. 8003d2c: bf00 nop
  9814. 8003d2e: 4618 mov r0, r3
  9815. 8003d30: 3708 adds r7, #8
  9816. 8003d32: 46bd mov sp, r7
  9817. 8003d34: bd80 pop {r7, pc}
  9818. 08003d36 <USER_status>:
  9819. * @retval DSTATUS: Operation status
  9820. */
  9821. DSTATUS USER_status (
  9822. BYTE pdrv /* Physical drive number to identify the drive */
  9823. )
  9824. {
  9825. 8003d36: b580 push {r7, lr}
  9826. 8003d38: b082 sub sp, #8
  9827. 8003d3a: af00 add r7, sp, #0
  9828. 8003d3c: 4603 mov r3, r0
  9829. 8003d3e: 71fb strb r3, [r7, #7]
  9830. /* USER CODE BEGIN STATUS */
  9831. //Stat = STA_NOINIT;
  9832. //return Stat;
  9833. SD_disk_status (pdrv);
  9834. 8003d40: 79fb ldrb r3, [r7, #7]
  9835. 8003d42: 4618 mov r0, r3
  9836. 8003d44: f7fc fe3c bl 80009c0 <SD_disk_status>
  9837. /* USER CODE END STATUS */
  9838. }
  9839. 8003d48: bf00 nop
  9840. 8003d4a: 4618 mov r0, r3
  9841. 8003d4c: 3708 adds r7, #8
  9842. 8003d4e: 46bd mov sp, r7
  9843. 8003d50: bd80 pop {r7, pc}
  9844. 08003d52 <USER_read>:
  9845. BYTE pdrv, /* Physical drive nmuber to identify the drive */
  9846. BYTE *buff, /* Data buffer to store read data */
  9847. DWORD sector, /* Sector address in LBA */
  9848. UINT count /* Number of sectors to read */
  9849. )
  9850. {
  9851. 8003d52: b580 push {r7, lr}
  9852. 8003d54: b084 sub sp, #16
  9853. 8003d56: af00 add r7, sp, #0
  9854. 8003d58: 60b9 str r1, [r7, #8]
  9855. 8003d5a: 607a str r2, [r7, #4]
  9856. 8003d5c: 603b str r3, [r7, #0]
  9857. 8003d5e: 4603 mov r3, r0
  9858. 8003d60: 73fb strb r3, [r7, #15]
  9859. /* USER CODE BEGIN READ */
  9860. //return RES_OK;
  9861. SD_disk_read (pdrv, buff, sector, count);
  9862. 8003d62: 7bf8 ldrb r0, [r7, #15]
  9863. 8003d64: 683b ldr r3, [r7, #0]
  9864. 8003d66: 687a ldr r2, [r7, #4]
  9865. 8003d68: 68b9 ldr r1, [r7, #8]
  9866. 8003d6a: f7fc fe3d bl 80009e8 <SD_disk_read>
  9867. /* USER CODE END READ */
  9868. }
  9869. 8003d6e: bf00 nop
  9870. 8003d70: 4618 mov r0, r3
  9871. 8003d72: 3710 adds r7, #16
  9872. 8003d74: 46bd mov sp, r7
  9873. 8003d76: bd80 pop {r7, pc}
  9874. 08003d78 <USER_write>:
  9875. BYTE pdrv, /* Physical drive nmuber to identify the drive */
  9876. const BYTE *buff, /* Data to be written */
  9877. DWORD sector, /* Sector address in LBA */
  9878. UINT count /* Number of sectors to write */
  9879. )
  9880. {
  9881. 8003d78: b580 push {r7, lr}
  9882. 8003d7a: b084 sub sp, #16
  9883. 8003d7c: af00 add r7, sp, #0
  9884. 8003d7e: 60b9 str r1, [r7, #8]
  9885. 8003d80: 607a str r2, [r7, #4]
  9886. 8003d82: 603b str r3, [r7, #0]
  9887. 8003d84: 4603 mov r3, r0
  9888. 8003d86: 73fb strb r3, [r7, #15]
  9889. /* USER CODE BEGIN WRITE */
  9890. /* USER CODE HERE */
  9891. //return RES_OK;
  9892. SD_disk_write (pdrv, buff, sector, count);
  9893. 8003d88: 7bf8 ldrb r0, [r7, #15]
  9894. 8003d8a: 683b ldr r3, [r7, #0]
  9895. 8003d8c: 687a ldr r2, [r7, #4]
  9896. 8003d8e: 68b9 ldr r1, [r7, #8]
  9897. 8003d90: f7fc fe94 bl 8000abc <SD_disk_write>
  9898. /* USER CODE END WRITE */
  9899. }
  9900. 8003d94: bf00 nop
  9901. 8003d96: 4618 mov r0, r3
  9902. 8003d98: 3710 adds r7, #16
  9903. 8003d9a: 46bd mov sp, r7
  9904. 8003d9c: bd80 pop {r7, pc}
  9905. 08003d9e <USER_ioctl>:
  9906. DRESULT USER_ioctl (
  9907. BYTE pdrv, /* Physical drive nmuber (0..) */
  9908. BYTE cmd, /* Control code */
  9909. void *buff /* Buffer to send/receive control data */
  9910. )
  9911. {
  9912. 8003d9e: b580 push {r7, lr}
  9913. 8003da0: b082 sub sp, #8
  9914. 8003da2: af00 add r7, sp, #0
  9915. 8003da4: 4603 mov r3, r0
  9916. 8003da6: 603a str r2, [r7, #0]
  9917. 8003da8: 71fb strb r3, [r7, #7]
  9918. 8003daa: 460b mov r3, r1
  9919. 8003dac: 71bb strb r3, [r7, #6]
  9920. /* USER CODE BEGIN IOCTL */
  9921. //DRESULT res = RES_ERROR;
  9922. //return res;
  9923. SD_disk_ioctl (pdrv, cmd, buff);
  9924. 8003dae: 79fb ldrb r3, [r7, #7]
  9925. 8003db0: 79b9 ldrb r1, [r7, #6]
  9926. 8003db2: 683a ldr r2, [r7, #0]
  9927. 8003db4: 4618 mov r0, r3
  9928. 8003db6: f7fc ff05 bl 8000bc4 <SD_disk_ioctl>
  9929. /* USER CODE END IOCTL */
  9930. }
  9931. 8003dba: bf00 nop
  9932. 8003dbc: 4618 mov r0, r3
  9933. 8003dbe: 3708 adds r7, #8
  9934. 8003dc0: 46bd mov sp, r7
  9935. 8003dc2: bd80 pop {r7, pc}
  9936. 08003dc4 <disk_status>:
  9937. * @retval DSTATUS: Operation status
  9938. */
  9939. DSTATUS disk_status (
  9940. BYTE pdrv /* Physical drive number to identify the drive */
  9941. )
  9942. {
  9943. 8003dc4: b580 push {r7, lr}
  9944. 8003dc6: b084 sub sp, #16
  9945. 8003dc8: af00 add r7, sp, #0
  9946. 8003dca: 4603 mov r3, r0
  9947. 8003dcc: 71fb strb r3, [r7, #7]
  9948. DSTATUS stat;
  9949. stat = disk.drv[pdrv]->disk_status(disk.lun[pdrv]);
  9950. 8003dce: 79fb ldrb r3, [r7, #7]
  9951. 8003dd0: 4a08 ldr r2, [pc, #32] ; (8003df4 <disk_status+0x30>)
  9952. 8003dd2: 009b lsls r3, r3, #2
  9953. 8003dd4: 4413 add r3, r2
  9954. 8003dd6: 685b ldr r3, [r3, #4]
  9955. 8003dd8: 685b ldr r3, [r3, #4]
  9956. 8003dda: 79fa ldrb r2, [r7, #7]
  9957. 8003ddc: 4905 ldr r1, [pc, #20] ; (8003df4 <disk_status+0x30>)
  9958. 8003dde: 440a add r2, r1
  9959. 8003de0: 7a12 ldrb r2, [r2, #8]
  9960. 8003de2: 4610 mov r0, r2
  9961. 8003de4: 4798 blx r3
  9962. 8003de6: 4603 mov r3, r0
  9963. 8003de8: 73fb strb r3, [r7, #15]
  9964. return stat;
  9965. 8003dea: 7bfb ldrb r3, [r7, #15]
  9966. }
  9967. 8003dec: 4618 mov r0, r3
  9968. 8003dee: 3710 adds r7, #16
  9969. 8003df0: 46bd mov sp, r7
  9970. 8003df2: bd80 pop {r7, pc}
  9971. 8003df4: 200002d4 .word 0x200002d4
  9972. 08003df8 <disk_initialize>:
  9973. * @retval DSTATUS: Operation status
  9974. */
  9975. DSTATUS disk_initialize (
  9976. BYTE pdrv /* Physical drive nmuber to identify the drive */
  9977. )
  9978. {
  9979. 8003df8: b580 push {r7, lr}
  9980. 8003dfa: b084 sub sp, #16
  9981. 8003dfc: af00 add r7, sp, #0
  9982. 8003dfe: 4603 mov r3, r0
  9983. 8003e00: 71fb strb r3, [r7, #7]
  9984. DSTATUS stat = RES_OK;
  9985. 8003e02: 2300 movs r3, #0
  9986. 8003e04: 73fb strb r3, [r7, #15]
  9987. if(disk.is_initialized[pdrv] == 0)
  9988. 8003e06: 79fb ldrb r3, [r7, #7]
  9989. 8003e08: 4a0d ldr r2, [pc, #52] ; (8003e40 <disk_initialize+0x48>)
  9990. 8003e0a: 5cd3 ldrb r3, [r2, r3]
  9991. 8003e0c: 2b00 cmp r3, #0
  9992. 8003e0e: d111 bne.n 8003e34 <disk_initialize+0x3c>
  9993. {
  9994. disk.is_initialized[pdrv] = 1;
  9995. 8003e10: 79fb ldrb r3, [r7, #7]
  9996. 8003e12: 4a0b ldr r2, [pc, #44] ; (8003e40 <disk_initialize+0x48>)
  9997. 8003e14: 2101 movs r1, #1
  9998. 8003e16: 54d1 strb r1, [r2, r3]
  9999. stat = disk.drv[pdrv]->disk_initialize(disk.lun[pdrv]);
  10000. 8003e18: 79fb ldrb r3, [r7, #7]
  10001. 8003e1a: 4a09 ldr r2, [pc, #36] ; (8003e40 <disk_initialize+0x48>)
  10002. 8003e1c: 009b lsls r3, r3, #2
  10003. 8003e1e: 4413 add r3, r2
  10004. 8003e20: 685b ldr r3, [r3, #4]
  10005. 8003e22: 681b ldr r3, [r3, #0]
  10006. 8003e24: 79fa ldrb r2, [r7, #7]
  10007. 8003e26: 4906 ldr r1, [pc, #24] ; (8003e40 <disk_initialize+0x48>)
  10008. 8003e28: 440a add r2, r1
  10009. 8003e2a: 7a12 ldrb r2, [r2, #8]
  10010. 8003e2c: 4610 mov r0, r2
  10011. 8003e2e: 4798 blx r3
  10012. 8003e30: 4603 mov r3, r0
  10013. 8003e32: 73fb strb r3, [r7, #15]
  10014. }
  10015. return stat;
  10016. 8003e34: 7bfb ldrb r3, [r7, #15]
  10017. }
  10018. 8003e36: 4618 mov r0, r3
  10019. 8003e38: 3710 adds r7, #16
  10020. 8003e3a: 46bd mov sp, r7
  10021. 8003e3c: bd80 pop {r7, pc}
  10022. 8003e3e: bf00 nop
  10023. 8003e40: 200002d4 .word 0x200002d4
  10024. 08003e44 <disk_read>:
  10025. BYTE pdrv, /* Physical drive nmuber to identify the drive */
  10026. BYTE *buff, /* Data buffer to store read data */
  10027. DWORD sector, /* Sector address in LBA */
  10028. UINT count /* Number of sectors to read */
  10029. )
  10030. {
  10031. 8003e44: b590 push {r4, r7, lr}
  10032. 8003e46: b087 sub sp, #28
  10033. 8003e48: af00 add r7, sp, #0
  10034. 8003e4a: 60b9 str r1, [r7, #8]
  10035. 8003e4c: 607a str r2, [r7, #4]
  10036. 8003e4e: 603b str r3, [r7, #0]
  10037. 8003e50: 4603 mov r3, r0
  10038. 8003e52: 73fb strb r3, [r7, #15]
  10039. DRESULT res;
  10040. res = disk.drv[pdrv]->disk_read(disk.lun[pdrv], buff, sector, count);
  10041. 8003e54: 7bfb ldrb r3, [r7, #15]
  10042. 8003e56: 4a0a ldr r2, [pc, #40] ; (8003e80 <disk_read+0x3c>)
  10043. 8003e58: 009b lsls r3, r3, #2
  10044. 8003e5a: 4413 add r3, r2
  10045. 8003e5c: 685b ldr r3, [r3, #4]
  10046. 8003e5e: 689c ldr r4, [r3, #8]
  10047. 8003e60: 7bfb ldrb r3, [r7, #15]
  10048. 8003e62: 4a07 ldr r2, [pc, #28] ; (8003e80 <disk_read+0x3c>)
  10049. 8003e64: 4413 add r3, r2
  10050. 8003e66: 7a18 ldrb r0, [r3, #8]
  10051. 8003e68: 683b ldr r3, [r7, #0]
  10052. 8003e6a: 687a ldr r2, [r7, #4]
  10053. 8003e6c: 68b9 ldr r1, [r7, #8]
  10054. 8003e6e: 47a0 blx r4
  10055. 8003e70: 4603 mov r3, r0
  10056. 8003e72: 75fb strb r3, [r7, #23]
  10057. return res;
  10058. 8003e74: 7dfb ldrb r3, [r7, #23]
  10059. }
  10060. 8003e76: 4618 mov r0, r3
  10061. 8003e78: 371c adds r7, #28
  10062. 8003e7a: 46bd mov sp, r7
  10063. 8003e7c: bd90 pop {r4, r7, pc}
  10064. 8003e7e: bf00 nop
  10065. 8003e80: 200002d4 .word 0x200002d4
  10066. 08003e84 <disk_write>:
  10067. BYTE pdrv, /* Physical drive nmuber to identify the drive */
  10068. const BYTE *buff, /* Data to be written */
  10069. DWORD sector, /* Sector address in LBA */
  10070. UINT count /* Number of sectors to write */
  10071. )
  10072. {
  10073. 8003e84: b590 push {r4, r7, lr}
  10074. 8003e86: b087 sub sp, #28
  10075. 8003e88: af00 add r7, sp, #0
  10076. 8003e8a: 60b9 str r1, [r7, #8]
  10077. 8003e8c: 607a str r2, [r7, #4]
  10078. 8003e8e: 603b str r3, [r7, #0]
  10079. 8003e90: 4603 mov r3, r0
  10080. 8003e92: 73fb strb r3, [r7, #15]
  10081. DRESULT res;
  10082. res = disk.drv[pdrv]->disk_write(disk.lun[pdrv], buff, sector, count);
  10083. 8003e94: 7bfb ldrb r3, [r7, #15]
  10084. 8003e96: 4a0a ldr r2, [pc, #40] ; (8003ec0 <disk_write+0x3c>)
  10085. 8003e98: 009b lsls r3, r3, #2
  10086. 8003e9a: 4413 add r3, r2
  10087. 8003e9c: 685b ldr r3, [r3, #4]
  10088. 8003e9e: 68dc ldr r4, [r3, #12]
  10089. 8003ea0: 7bfb ldrb r3, [r7, #15]
  10090. 8003ea2: 4a07 ldr r2, [pc, #28] ; (8003ec0 <disk_write+0x3c>)
  10091. 8003ea4: 4413 add r3, r2
  10092. 8003ea6: 7a18 ldrb r0, [r3, #8]
  10093. 8003ea8: 683b ldr r3, [r7, #0]
  10094. 8003eaa: 687a ldr r2, [r7, #4]
  10095. 8003eac: 68b9 ldr r1, [r7, #8]
  10096. 8003eae: 47a0 blx r4
  10097. 8003eb0: 4603 mov r3, r0
  10098. 8003eb2: 75fb strb r3, [r7, #23]
  10099. return res;
  10100. 8003eb4: 7dfb ldrb r3, [r7, #23]
  10101. }
  10102. 8003eb6: 4618 mov r0, r3
  10103. 8003eb8: 371c adds r7, #28
  10104. 8003eba: 46bd mov sp, r7
  10105. 8003ebc: bd90 pop {r4, r7, pc}
  10106. 8003ebe: bf00 nop
  10107. 8003ec0: 200002d4 .word 0x200002d4
  10108. 08003ec4 <disk_ioctl>:
  10109. DRESULT disk_ioctl (
  10110. BYTE pdrv, /* Physical drive nmuber (0..) */
  10111. BYTE cmd, /* Control code */
  10112. void *buff /* Buffer to send/receive control data */
  10113. )
  10114. {
  10115. 8003ec4: b580 push {r7, lr}
  10116. 8003ec6: b084 sub sp, #16
  10117. 8003ec8: af00 add r7, sp, #0
  10118. 8003eca: 4603 mov r3, r0
  10119. 8003ecc: 603a str r2, [r7, #0]
  10120. 8003ece: 71fb strb r3, [r7, #7]
  10121. 8003ed0: 460b mov r3, r1
  10122. 8003ed2: 71bb strb r3, [r7, #6]
  10123. DRESULT res;
  10124. res = disk.drv[pdrv]->disk_ioctl(disk.lun[pdrv], cmd, buff);
  10125. 8003ed4: 79fb ldrb r3, [r7, #7]
  10126. 8003ed6: 4a09 ldr r2, [pc, #36] ; (8003efc <disk_ioctl+0x38>)
  10127. 8003ed8: 009b lsls r3, r3, #2
  10128. 8003eda: 4413 add r3, r2
  10129. 8003edc: 685b ldr r3, [r3, #4]
  10130. 8003ede: 691b ldr r3, [r3, #16]
  10131. 8003ee0: 79fa ldrb r2, [r7, #7]
  10132. 8003ee2: 4906 ldr r1, [pc, #24] ; (8003efc <disk_ioctl+0x38>)
  10133. 8003ee4: 440a add r2, r1
  10134. 8003ee6: 7a10 ldrb r0, [r2, #8]
  10135. 8003ee8: 79b9 ldrb r1, [r7, #6]
  10136. 8003eea: 683a ldr r2, [r7, #0]
  10137. 8003eec: 4798 blx r3
  10138. 8003eee: 4603 mov r3, r0
  10139. 8003ef0: 73fb strb r3, [r7, #15]
  10140. return res;
  10141. 8003ef2: 7bfb ldrb r3, [r7, #15]
  10142. }
  10143. 8003ef4: 4618 mov r0, r3
  10144. 8003ef6: 3710 adds r7, #16
  10145. 8003ef8: 46bd mov sp, r7
  10146. 8003efa: bd80 pop {r7, pc}
  10147. 8003efc: 200002d4 .word 0x200002d4
  10148. 08003f00 <ld_word>:
  10149. /* Load/Store multi-byte word in the FAT structure */
  10150. /*-----------------------------------------------------------------------*/
  10151. static
  10152. WORD ld_word (const BYTE* ptr) /* Load a 2-byte little-endian word */
  10153. {
  10154. 8003f00: b480 push {r7}
  10155. 8003f02: b085 sub sp, #20
  10156. 8003f04: af00 add r7, sp, #0
  10157. 8003f06: 6078 str r0, [r7, #4]
  10158. WORD rv;
  10159. rv = ptr[1];
  10160. 8003f08: 687b ldr r3, [r7, #4]
  10161. 8003f0a: 3301 adds r3, #1
  10162. 8003f0c: 781b ldrb r3, [r3, #0]
  10163. 8003f0e: 81fb strh r3, [r7, #14]
  10164. rv = rv << 8 | ptr[0];
  10165. 8003f10: 89fb ldrh r3, [r7, #14]
  10166. 8003f12: 021b lsls r3, r3, #8
  10167. 8003f14: b21a sxth r2, r3
  10168. 8003f16: 687b ldr r3, [r7, #4]
  10169. 8003f18: 781b ldrb r3, [r3, #0]
  10170. 8003f1a: b21b sxth r3, r3
  10171. 8003f1c: 4313 orrs r3, r2
  10172. 8003f1e: b21b sxth r3, r3
  10173. 8003f20: 81fb strh r3, [r7, #14]
  10174. return rv;
  10175. 8003f22: 89fb ldrh r3, [r7, #14]
  10176. }
  10177. 8003f24: 4618 mov r0, r3
  10178. 8003f26: 3714 adds r7, #20
  10179. 8003f28: 46bd mov sp, r7
  10180. 8003f2a: bc80 pop {r7}
  10181. 8003f2c: 4770 bx lr
  10182. 08003f2e <ld_dword>:
  10183. static
  10184. DWORD ld_dword (const BYTE* ptr) /* Load a 4-byte little-endian word */
  10185. {
  10186. 8003f2e: b480 push {r7}
  10187. 8003f30: b085 sub sp, #20
  10188. 8003f32: af00 add r7, sp, #0
  10189. 8003f34: 6078 str r0, [r7, #4]
  10190. DWORD rv;
  10191. rv = ptr[3];
  10192. 8003f36: 687b ldr r3, [r7, #4]
  10193. 8003f38: 3303 adds r3, #3
  10194. 8003f3a: 781b ldrb r3, [r3, #0]
  10195. 8003f3c: 60fb str r3, [r7, #12]
  10196. rv = rv << 8 | ptr[2];
  10197. 8003f3e: 68fb ldr r3, [r7, #12]
  10198. 8003f40: 021b lsls r3, r3, #8
  10199. 8003f42: 687a ldr r2, [r7, #4]
  10200. 8003f44: 3202 adds r2, #2
  10201. 8003f46: 7812 ldrb r2, [r2, #0]
  10202. 8003f48: 4313 orrs r3, r2
  10203. 8003f4a: 60fb str r3, [r7, #12]
  10204. rv = rv << 8 | ptr[1];
  10205. 8003f4c: 68fb ldr r3, [r7, #12]
  10206. 8003f4e: 021b lsls r3, r3, #8
  10207. 8003f50: 687a ldr r2, [r7, #4]
  10208. 8003f52: 3201 adds r2, #1
  10209. 8003f54: 7812 ldrb r2, [r2, #0]
  10210. 8003f56: 4313 orrs r3, r2
  10211. 8003f58: 60fb str r3, [r7, #12]
  10212. rv = rv << 8 | ptr[0];
  10213. 8003f5a: 68fb ldr r3, [r7, #12]
  10214. 8003f5c: 021b lsls r3, r3, #8
  10215. 8003f5e: 687a ldr r2, [r7, #4]
  10216. 8003f60: 7812 ldrb r2, [r2, #0]
  10217. 8003f62: 4313 orrs r3, r2
  10218. 8003f64: 60fb str r3, [r7, #12]
  10219. return rv;
  10220. 8003f66: 68fb ldr r3, [r7, #12]
  10221. }
  10222. 8003f68: 4618 mov r0, r3
  10223. 8003f6a: 3714 adds r7, #20
  10224. 8003f6c: 46bd mov sp, r7
  10225. 8003f6e: bc80 pop {r7}
  10226. 8003f70: 4770 bx lr
  10227. 08003f72 <st_word>:
  10228. #endif
  10229. #if !_FS_READONLY
  10230. static
  10231. void st_word (BYTE* ptr, WORD val) /* Store a 2-byte word in little-endian */
  10232. {
  10233. 8003f72: b480 push {r7}
  10234. 8003f74: b083 sub sp, #12
  10235. 8003f76: af00 add r7, sp, #0
  10236. 8003f78: 6078 str r0, [r7, #4]
  10237. 8003f7a: 460b mov r3, r1
  10238. 8003f7c: 807b strh r3, [r7, #2]
  10239. *ptr++ = (BYTE)val; val >>= 8;
  10240. 8003f7e: 687b ldr r3, [r7, #4]
  10241. 8003f80: 1c5a adds r2, r3, #1
  10242. 8003f82: 607a str r2, [r7, #4]
  10243. 8003f84: 887a ldrh r2, [r7, #2]
  10244. 8003f86: b2d2 uxtb r2, r2
  10245. 8003f88: 701a strb r2, [r3, #0]
  10246. 8003f8a: 887b ldrh r3, [r7, #2]
  10247. 8003f8c: 0a1b lsrs r3, r3, #8
  10248. 8003f8e: 807b strh r3, [r7, #2]
  10249. *ptr++ = (BYTE)val;
  10250. 8003f90: 687b ldr r3, [r7, #4]
  10251. 8003f92: 1c5a adds r2, r3, #1
  10252. 8003f94: 607a str r2, [r7, #4]
  10253. 8003f96: 887a ldrh r2, [r7, #2]
  10254. 8003f98: b2d2 uxtb r2, r2
  10255. 8003f9a: 701a strb r2, [r3, #0]
  10256. }
  10257. 8003f9c: bf00 nop
  10258. 8003f9e: 370c adds r7, #12
  10259. 8003fa0: 46bd mov sp, r7
  10260. 8003fa2: bc80 pop {r7}
  10261. 8003fa4: 4770 bx lr
  10262. 08003fa6 <st_dword>:
  10263. static
  10264. void st_dword (BYTE* ptr, DWORD val) /* Store a 4-byte word in little-endian */
  10265. {
  10266. 8003fa6: b480 push {r7}
  10267. 8003fa8: b083 sub sp, #12
  10268. 8003faa: af00 add r7, sp, #0
  10269. 8003fac: 6078 str r0, [r7, #4]
  10270. 8003fae: 6039 str r1, [r7, #0]
  10271. *ptr++ = (BYTE)val; val >>= 8;
  10272. 8003fb0: 687b ldr r3, [r7, #4]
  10273. 8003fb2: 1c5a adds r2, r3, #1
  10274. 8003fb4: 607a str r2, [r7, #4]
  10275. 8003fb6: 683a ldr r2, [r7, #0]
  10276. 8003fb8: b2d2 uxtb r2, r2
  10277. 8003fba: 701a strb r2, [r3, #0]
  10278. 8003fbc: 683b ldr r3, [r7, #0]
  10279. 8003fbe: 0a1b lsrs r3, r3, #8
  10280. 8003fc0: 603b str r3, [r7, #0]
  10281. *ptr++ = (BYTE)val; val >>= 8;
  10282. 8003fc2: 687b ldr r3, [r7, #4]
  10283. 8003fc4: 1c5a adds r2, r3, #1
  10284. 8003fc6: 607a str r2, [r7, #4]
  10285. 8003fc8: 683a ldr r2, [r7, #0]
  10286. 8003fca: b2d2 uxtb r2, r2
  10287. 8003fcc: 701a strb r2, [r3, #0]
  10288. 8003fce: 683b ldr r3, [r7, #0]
  10289. 8003fd0: 0a1b lsrs r3, r3, #8
  10290. 8003fd2: 603b str r3, [r7, #0]
  10291. *ptr++ = (BYTE)val; val >>= 8;
  10292. 8003fd4: 687b ldr r3, [r7, #4]
  10293. 8003fd6: 1c5a adds r2, r3, #1
  10294. 8003fd8: 607a str r2, [r7, #4]
  10295. 8003fda: 683a ldr r2, [r7, #0]
  10296. 8003fdc: b2d2 uxtb r2, r2
  10297. 8003fde: 701a strb r2, [r3, #0]
  10298. 8003fe0: 683b ldr r3, [r7, #0]
  10299. 8003fe2: 0a1b lsrs r3, r3, #8
  10300. 8003fe4: 603b str r3, [r7, #0]
  10301. *ptr++ = (BYTE)val;
  10302. 8003fe6: 687b ldr r3, [r7, #4]
  10303. 8003fe8: 1c5a adds r2, r3, #1
  10304. 8003fea: 607a str r2, [r7, #4]
  10305. 8003fec: 683a ldr r2, [r7, #0]
  10306. 8003fee: b2d2 uxtb r2, r2
  10307. 8003ff0: 701a strb r2, [r3, #0]
  10308. }
  10309. 8003ff2: bf00 nop
  10310. 8003ff4: 370c adds r7, #12
  10311. 8003ff6: 46bd mov sp, r7
  10312. 8003ff8: bc80 pop {r7}
  10313. 8003ffa: 4770 bx lr
  10314. 08003ffc <mem_cpy>:
  10315. /* String functions */
  10316. /*-----------------------------------------------------------------------*/
  10317. /* Copy memory to memory */
  10318. static
  10319. void mem_cpy (void* dst, const void* src, UINT cnt) {
  10320. 8003ffc: b480 push {r7}
  10321. 8003ffe: b087 sub sp, #28
  10322. 8004000: af00 add r7, sp, #0
  10323. 8004002: 60f8 str r0, [r7, #12]
  10324. 8004004: 60b9 str r1, [r7, #8]
  10325. 8004006: 607a str r2, [r7, #4]
  10326. BYTE *d = (BYTE*)dst;
  10327. 8004008: 68fb ldr r3, [r7, #12]
  10328. 800400a: 617b str r3, [r7, #20]
  10329. const BYTE *s = (const BYTE*)src;
  10330. 800400c: 68bb ldr r3, [r7, #8]
  10331. 800400e: 613b str r3, [r7, #16]
  10332. if (cnt) {
  10333. 8004010: 687b ldr r3, [r7, #4]
  10334. 8004012: 2b00 cmp r3, #0
  10335. 8004014: d00d beq.n 8004032 <mem_cpy+0x36>
  10336. do {
  10337. *d++ = *s++;
  10338. 8004016: 693a ldr r2, [r7, #16]
  10339. 8004018: 1c53 adds r3, r2, #1
  10340. 800401a: 613b str r3, [r7, #16]
  10341. 800401c: 697b ldr r3, [r7, #20]
  10342. 800401e: 1c59 adds r1, r3, #1
  10343. 8004020: 6179 str r1, [r7, #20]
  10344. 8004022: 7812 ldrb r2, [r2, #0]
  10345. 8004024: 701a strb r2, [r3, #0]
  10346. } while (--cnt);
  10347. 8004026: 687b ldr r3, [r7, #4]
  10348. 8004028: 3b01 subs r3, #1
  10349. 800402a: 607b str r3, [r7, #4]
  10350. 800402c: 687b ldr r3, [r7, #4]
  10351. 800402e: 2b00 cmp r3, #0
  10352. 8004030: d1f1 bne.n 8004016 <mem_cpy+0x1a>
  10353. }
  10354. }
  10355. 8004032: bf00 nop
  10356. 8004034: 371c adds r7, #28
  10357. 8004036: 46bd mov sp, r7
  10358. 8004038: bc80 pop {r7}
  10359. 800403a: 4770 bx lr
  10360. 0800403c <mem_set>:
  10361. /* Fill memory block */
  10362. static
  10363. void mem_set (void* dst, int val, UINT cnt) {
  10364. 800403c: b480 push {r7}
  10365. 800403e: b087 sub sp, #28
  10366. 8004040: af00 add r7, sp, #0
  10367. 8004042: 60f8 str r0, [r7, #12]
  10368. 8004044: 60b9 str r1, [r7, #8]
  10369. 8004046: 607a str r2, [r7, #4]
  10370. BYTE *d = (BYTE*)dst;
  10371. 8004048: 68fb ldr r3, [r7, #12]
  10372. 800404a: 617b str r3, [r7, #20]
  10373. do {
  10374. *d++ = (BYTE)val;
  10375. 800404c: 697b ldr r3, [r7, #20]
  10376. 800404e: 1c5a adds r2, r3, #1
  10377. 8004050: 617a str r2, [r7, #20]
  10378. 8004052: 68ba ldr r2, [r7, #8]
  10379. 8004054: b2d2 uxtb r2, r2
  10380. 8004056: 701a strb r2, [r3, #0]
  10381. } while (--cnt);
  10382. 8004058: 687b ldr r3, [r7, #4]
  10383. 800405a: 3b01 subs r3, #1
  10384. 800405c: 607b str r3, [r7, #4]
  10385. 800405e: 687b ldr r3, [r7, #4]
  10386. 8004060: 2b00 cmp r3, #0
  10387. 8004062: d1f3 bne.n 800404c <mem_set+0x10>
  10388. }
  10389. 8004064: bf00 nop
  10390. 8004066: 371c adds r7, #28
  10391. 8004068: 46bd mov sp, r7
  10392. 800406a: bc80 pop {r7}
  10393. 800406c: 4770 bx lr
  10394. 0800406e <mem_cmp>:
  10395. /* Compare memory block */
  10396. static
  10397. int mem_cmp (const void* dst, const void* src, UINT cnt) { /* ZR:same, NZ:different */
  10398. 800406e: b480 push {r7}
  10399. 8004070: b089 sub sp, #36 ; 0x24
  10400. 8004072: af00 add r7, sp, #0
  10401. 8004074: 60f8 str r0, [r7, #12]
  10402. 8004076: 60b9 str r1, [r7, #8]
  10403. 8004078: 607a str r2, [r7, #4]
  10404. const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
  10405. 800407a: 68fb ldr r3, [r7, #12]
  10406. 800407c: 61fb str r3, [r7, #28]
  10407. 800407e: 68bb ldr r3, [r7, #8]
  10408. 8004080: 61bb str r3, [r7, #24]
  10409. int r = 0;
  10410. 8004082: 2300 movs r3, #0
  10411. 8004084: 617b str r3, [r7, #20]
  10412. do {
  10413. r = *d++ - *s++;
  10414. 8004086: 69fb ldr r3, [r7, #28]
  10415. 8004088: 1c5a adds r2, r3, #1
  10416. 800408a: 61fa str r2, [r7, #28]
  10417. 800408c: 781b ldrb r3, [r3, #0]
  10418. 800408e: 4619 mov r1, r3
  10419. 8004090: 69bb ldr r3, [r7, #24]
  10420. 8004092: 1c5a adds r2, r3, #1
  10421. 8004094: 61ba str r2, [r7, #24]
  10422. 8004096: 781b ldrb r3, [r3, #0]
  10423. 8004098: 1acb subs r3, r1, r3
  10424. 800409a: 617b str r3, [r7, #20]
  10425. } while (--cnt && r == 0);
  10426. 800409c: 687b ldr r3, [r7, #4]
  10427. 800409e: 3b01 subs r3, #1
  10428. 80040a0: 607b str r3, [r7, #4]
  10429. 80040a2: 687b ldr r3, [r7, #4]
  10430. 80040a4: 2b00 cmp r3, #0
  10431. 80040a6: d002 beq.n 80040ae <mem_cmp+0x40>
  10432. 80040a8: 697b ldr r3, [r7, #20]
  10433. 80040aa: 2b00 cmp r3, #0
  10434. 80040ac: d0eb beq.n 8004086 <mem_cmp+0x18>
  10435. return r;
  10436. 80040ae: 697b ldr r3, [r7, #20]
  10437. }
  10438. 80040b0: 4618 mov r0, r3
  10439. 80040b2: 3724 adds r7, #36 ; 0x24
  10440. 80040b4: 46bd mov sp, r7
  10441. 80040b6: bc80 pop {r7}
  10442. 80040b8: 4770 bx lr
  10443. 080040ba <chk_chr>:
  10444. /* Check if chr is contained in the string */
  10445. static
  10446. int chk_chr (const char* str, int chr) { /* NZ:contained, ZR:not contained */
  10447. 80040ba: b480 push {r7}
  10448. 80040bc: b083 sub sp, #12
  10449. 80040be: af00 add r7, sp, #0
  10450. 80040c0: 6078 str r0, [r7, #4]
  10451. 80040c2: 6039 str r1, [r7, #0]
  10452. while (*str && *str != chr) str++;
  10453. 80040c4: e002 b.n 80040cc <chk_chr+0x12>
  10454. 80040c6: 687b ldr r3, [r7, #4]
  10455. 80040c8: 3301 adds r3, #1
  10456. 80040ca: 607b str r3, [r7, #4]
  10457. 80040cc: 687b ldr r3, [r7, #4]
  10458. 80040ce: 781b ldrb r3, [r3, #0]
  10459. 80040d0: 2b00 cmp r3, #0
  10460. 80040d2: d005 beq.n 80040e0 <chk_chr+0x26>
  10461. 80040d4: 687b ldr r3, [r7, #4]
  10462. 80040d6: 781b ldrb r3, [r3, #0]
  10463. 80040d8: 461a mov r2, r3
  10464. 80040da: 683b ldr r3, [r7, #0]
  10465. 80040dc: 4293 cmp r3, r2
  10466. 80040de: d1f2 bne.n 80040c6 <chk_chr+0xc>
  10467. return *str;
  10468. 80040e0: 687b ldr r3, [r7, #4]
  10469. 80040e2: 781b ldrb r3, [r3, #0]
  10470. }
  10471. 80040e4: 4618 mov r0, r3
  10472. 80040e6: 370c adds r7, #12
  10473. 80040e8: 46bd mov sp, r7
  10474. 80040ea: bc80 pop {r7}
  10475. 80040ec: 4770 bx lr
  10476. ...
  10477. 080040f0 <chk_lock>:
  10478. static
  10479. FRESULT chk_lock ( /* Check if the file can be accessed */
  10480. DIR* dp, /* Directory object pointing the file to be checked */
  10481. int acc /* Desired access type (0:Read, 1:Write, 2:Delete/Rename) */
  10482. )
  10483. {
  10484. 80040f0: b480 push {r7}
  10485. 80040f2: b085 sub sp, #20
  10486. 80040f4: af00 add r7, sp, #0
  10487. 80040f6: 6078 str r0, [r7, #4]
  10488. 80040f8: 6039 str r1, [r7, #0]
  10489. UINT i, be;
  10490. /* Search file semaphore table */
  10491. for (i = be = 0; i < _FS_LOCK; i++) {
  10492. 80040fa: 2300 movs r3, #0
  10493. 80040fc: 60bb str r3, [r7, #8]
  10494. 80040fe: 68bb ldr r3, [r7, #8]
  10495. 8004100: 60fb str r3, [r7, #12]
  10496. 8004102: e029 b.n 8004158 <chk_lock+0x68>
  10497. if (Files[i].fs) { /* Existing entry */
  10498. 8004104: 4a26 ldr r2, [pc, #152] ; (80041a0 <chk_lock+0xb0>)
  10499. 8004106: 68fb ldr r3, [r7, #12]
  10500. 8004108: 011b lsls r3, r3, #4
  10501. 800410a: 4413 add r3, r2
  10502. 800410c: 681b ldr r3, [r3, #0]
  10503. 800410e: 2b00 cmp r3, #0
  10504. 8004110: d01d beq.n 800414e <chk_lock+0x5e>
  10505. if (Files[i].fs == dp->obj.fs && /* Check if the object matched with an open object */
  10506. 8004112: 4a23 ldr r2, [pc, #140] ; (80041a0 <chk_lock+0xb0>)
  10507. 8004114: 68fb ldr r3, [r7, #12]
  10508. 8004116: 011b lsls r3, r3, #4
  10509. 8004118: 4413 add r3, r2
  10510. 800411a: 681a ldr r2, [r3, #0]
  10511. 800411c: 687b ldr r3, [r7, #4]
  10512. 800411e: 681b ldr r3, [r3, #0]
  10513. 8004120: 429a cmp r2, r3
  10514. 8004122: d116 bne.n 8004152 <chk_lock+0x62>
  10515. Files[i].clu == dp->obj.sclust &&
  10516. 8004124: 4a1e ldr r2, [pc, #120] ; (80041a0 <chk_lock+0xb0>)
  10517. 8004126: 68fb ldr r3, [r7, #12]
  10518. 8004128: 011b lsls r3, r3, #4
  10519. 800412a: 4413 add r3, r2
  10520. 800412c: 3304 adds r3, #4
  10521. 800412e: 681a ldr r2, [r3, #0]
  10522. 8004130: 687b ldr r3, [r7, #4]
  10523. 8004132: 689b ldr r3, [r3, #8]
  10524. if (Files[i].fs == dp->obj.fs && /* Check if the object matched with an open object */
  10525. 8004134: 429a cmp r2, r3
  10526. 8004136: d10c bne.n 8004152 <chk_lock+0x62>
  10527. Files[i].ofs == dp->dptr) break;
  10528. 8004138: 4a19 ldr r2, [pc, #100] ; (80041a0 <chk_lock+0xb0>)
  10529. 800413a: 68fb ldr r3, [r7, #12]
  10530. 800413c: 011b lsls r3, r3, #4
  10531. 800413e: 4413 add r3, r2
  10532. 8004140: 3308 adds r3, #8
  10533. 8004142: 681a ldr r2, [r3, #0]
  10534. 8004144: 687b ldr r3, [r7, #4]
  10535. 8004146: 695b ldr r3, [r3, #20]
  10536. Files[i].clu == dp->obj.sclust &&
  10537. 8004148: 429a cmp r2, r3
  10538. 800414a: d102 bne.n 8004152 <chk_lock+0x62>
  10539. Files[i].ofs == dp->dptr) break;
  10540. 800414c: e007 b.n 800415e <chk_lock+0x6e>
  10541. } else { /* Blank entry */
  10542. be = 1;
  10543. 800414e: 2301 movs r3, #1
  10544. 8004150: 60bb str r3, [r7, #8]
  10545. for (i = be = 0; i < _FS_LOCK; i++) {
  10546. 8004152: 68fb ldr r3, [r7, #12]
  10547. 8004154: 3301 adds r3, #1
  10548. 8004156: 60fb str r3, [r7, #12]
  10549. 8004158: 68fb ldr r3, [r7, #12]
  10550. 800415a: 2b01 cmp r3, #1
  10551. 800415c: d9d2 bls.n 8004104 <chk_lock+0x14>
  10552. }
  10553. }
  10554. if (i == _FS_LOCK) { /* The object is not opened */
  10555. 800415e: 68fb ldr r3, [r7, #12]
  10556. 8004160: 2b02 cmp r3, #2
  10557. 8004162: d109 bne.n 8004178 <chk_lock+0x88>
  10558. return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */
  10559. 8004164: 68bb ldr r3, [r7, #8]
  10560. 8004166: 2b00 cmp r3, #0
  10561. 8004168: d102 bne.n 8004170 <chk_lock+0x80>
  10562. 800416a: 683b ldr r3, [r7, #0]
  10563. 800416c: 2b02 cmp r3, #2
  10564. 800416e: d101 bne.n 8004174 <chk_lock+0x84>
  10565. 8004170: 2300 movs r3, #0
  10566. 8004172: e010 b.n 8004196 <chk_lock+0xa6>
  10567. 8004174: 2312 movs r3, #18
  10568. 8004176: e00e b.n 8004196 <chk_lock+0xa6>
  10569. }
  10570. /* The object has been opened. Reject any open against writing file and all write mode open */
  10571. return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
  10572. 8004178: 683b ldr r3, [r7, #0]
  10573. 800417a: 2b00 cmp r3, #0
  10574. 800417c: d108 bne.n 8004190 <chk_lock+0xa0>
  10575. 800417e: 4a08 ldr r2, [pc, #32] ; (80041a0 <chk_lock+0xb0>)
  10576. 8004180: 68fb ldr r3, [r7, #12]
  10577. 8004182: 011b lsls r3, r3, #4
  10578. 8004184: 4413 add r3, r2
  10579. 8004186: 330c adds r3, #12
  10580. 8004188: 881b ldrh r3, [r3, #0]
  10581. 800418a: f5b3 7f80 cmp.w r3, #256 ; 0x100
  10582. 800418e: d101 bne.n 8004194 <chk_lock+0xa4>
  10583. 8004190: 2310 movs r3, #16
  10584. 8004192: e000 b.n 8004196 <chk_lock+0xa6>
  10585. 8004194: 2300 movs r3, #0
  10586. }
  10587. 8004196: 4618 mov r0, r3
  10588. 8004198: 3714 adds r7, #20
  10589. 800419a: 46bd mov sp, r7
  10590. 800419c: bc80 pop {r7}
  10591. 800419e: 4770 bx lr
  10592. 80041a0: 200000b4 .word 0x200000b4
  10593. 080041a4 <enq_lock>:
  10594. static
  10595. int enq_lock (void) /* Check if an entry is available for a new object */
  10596. {
  10597. 80041a4: b480 push {r7}
  10598. 80041a6: b083 sub sp, #12
  10599. 80041a8: af00 add r7, sp, #0
  10600. UINT i;
  10601. for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
  10602. 80041aa: 2300 movs r3, #0
  10603. 80041ac: 607b str r3, [r7, #4]
  10604. 80041ae: e002 b.n 80041b6 <enq_lock+0x12>
  10605. 80041b0: 687b ldr r3, [r7, #4]
  10606. 80041b2: 3301 adds r3, #1
  10607. 80041b4: 607b str r3, [r7, #4]
  10608. 80041b6: 687b ldr r3, [r7, #4]
  10609. 80041b8: 2b01 cmp r3, #1
  10610. 80041ba: d806 bhi.n 80041ca <enq_lock+0x26>
  10611. 80041bc: 4a08 ldr r2, [pc, #32] ; (80041e0 <enq_lock+0x3c>)
  10612. 80041be: 687b ldr r3, [r7, #4]
  10613. 80041c0: 011b lsls r3, r3, #4
  10614. 80041c2: 4413 add r3, r2
  10615. 80041c4: 681b ldr r3, [r3, #0]
  10616. 80041c6: 2b00 cmp r3, #0
  10617. 80041c8: d1f2 bne.n 80041b0 <enq_lock+0xc>
  10618. return (i == _FS_LOCK) ? 0 : 1;
  10619. 80041ca: 687b ldr r3, [r7, #4]
  10620. 80041cc: 2b02 cmp r3, #2
  10621. 80041ce: bf14 ite ne
  10622. 80041d0: 2301 movne r3, #1
  10623. 80041d2: 2300 moveq r3, #0
  10624. 80041d4: b2db uxtb r3, r3
  10625. }
  10626. 80041d6: 4618 mov r0, r3
  10627. 80041d8: 370c adds r7, #12
  10628. 80041da: 46bd mov sp, r7
  10629. 80041dc: bc80 pop {r7}
  10630. 80041de: 4770 bx lr
  10631. 80041e0: 200000b4 .word 0x200000b4
  10632. 080041e4 <inc_lock>:
  10633. static
  10634. UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */
  10635. DIR* dp, /* Directory object pointing the file to register or increment */
  10636. int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
  10637. )
  10638. {
  10639. 80041e4: b480 push {r7}
  10640. 80041e6: b085 sub sp, #20
  10641. 80041e8: af00 add r7, sp, #0
  10642. 80041ea: 6078 str r0, [r7, #4]
  10643. 80041ec: 6039 str r1, [r7, #0]
  10644. UINT i;
  10645. for (i = 0; i < _FS_LOCK; i++) { /* Find the object */
  10646. 80041ee: 2300 movs r3, #0
  10647. 80041f0: 60fb str r3, [r7, #12]
  10648. 80041f2: e01f b.n 8004234 <inc_lock+0x50>
  10649. if (Files[i].fs == dp->obj.fs &&
  10650. 80041f4: 4a41 ldr r2, [pc, #260] ; (80042fc <inc_lock+0x118>)
  10651. 80041f6: 68fb ldr r3, [r7, #12]
  10652. 80041f8: 011b lsls r3, r3, #4
  10653. 80041fa: 4413 add r3, r2
  10654. 80041fc: 681a ldr r2, [r3, #0]
  10655. 80041fe: 687b ldr r3, [r7, #4]
  10656. 8004200: 681b ldr r3, [r3, #0]
  10657. 8004202: 429a cmp r2, r3
  10658. 8004204: d113 bne.n 800422e <inc_lock+0x4a>
  10659. Files[i].clu == dp->obj.sclust &&
  10660. 8004206: 4a3d ldr r2, [pc, #244] ; (80042fc <inc_lock+0x118>)
  10661. 8004208: 68fb ldr r3, [r7, #12]
  10662. 800420a: 011b lsls r3, r3, #4
  10663. 800420c: 4413 add r3, r2
  10664. 800420e: 3304 adds r3, #4
  10665. 8004210: 681a ldr r2, [r3, #0]
  10666. 8004212: 687b ldr r3, [r7, #4]
  10667. 8004214: 689b ldr r3, [r3, #8]
  10668. if (Files[i].fs == dp->obj.fs &&
  10669. 8004216: 429a cmp r2, r3
  10670. 8004218: d109 bne.n 800422e <inc_lock+0x4a>
  10671. Files[i].ofs == dp->dptr) break;
  10672. 800421a: 4a38 ldr r2, [pc, #224] ; (80042fc <inc_lock+0x118>)
  10673. 800421c: 68fb ldr r3, [r7, #12]
  10674. 800421e: 011b lsls r3, r3, #4
  10675. 8004220: 4413 add r3, r2
  10676. 8004222: 3308 adds r3, #8
  10677. 8004224: 681a ldr r2, [r3, #0]
  10678. 8004226: 687b ldr r3, [r7, #4]
  10679. 8004228: 695b ldr r3, [r3, #20]
  10680. Files[i].clu == dp->obj.sclust &&
  10681. 800422a: 429a cmp r2, r3
  10682. 800422c: d006 beq.n 800423c <inc_lock+0x58>
  10683. for (i = 0; i < _FS_LOCK; i++) { /* Find the object */
  10684. 800422e: 68fb ldr r3, [r7, #12]
  10685. 8004230: 3301 adds r3, #1
  10686. 8004232: 60fb str r3, [r7, #12]
  10687. 8004234: 68fb ldr r3, [r7, #12]
  10688. 8004236: 2b01 cmp r3, #1
  10689. 8004238: d9dc bls.n 80041f4 <inc_lock+0x10>
  10690. 800423a: e000 b.n 800423e <inc_lock+0x5a>
  10691. Files[i].ofs == dp->dptr) break;
  10692. 800423c: bf00 nop
  10693. }
  10694. if (i == _FS_LOCK) { /* Not opened. Register it as new. */
  10695. 800423e: 68fb ldr r3, [r7, #12]
  10696. 8004240: 2b02 cmp r3, #2
  10697. 8004242: d132 bne.n 80042aa <inc_lock+0xc6>
  10698. for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
  10699. 8004244: 2300 movs r3, #0
  10700. 8004246: 60fb str r3, [r7, #12]
  10701. 8004248: e002 b.n 8004250 <inc_lock+0x6c>
  10702. 800424a: 68fb ldr r3, [r7, #12]
  10703. 800424c: 3301 adds r3, #1
  10704. 800424e: 60fb str r3, [r7, #12]
  10705. 8004250: 68fb ldr r3, [r7, #12]
  10706. 8004252: 2b01 cmp r3, #1
  10707. 8004254: d806 bhi.n 8004264 <inc_lock+0x80>
  10708. 8004256: 4a29 ldr r2, [pc, #164] ; (80042fc <inc_lock+0x118>)
  10709. 8004258: 68fb ldr r3, [r7, #12]
  10710. 800425a: 011b lsls r3, r3, #4
  10711. 800425c: 4413 add r3, r2
  10712. 800425e: 681b ldr r3, [r3, #0]
  10713. 8004260: 2b00 cmp r3, #0
  10714. 8004262: d1f2 bne.n 800424a <inc_lock+0x66>
  10715. if (i == _FS_LOCK) return 0; /* No free entry to register (int err) */
  10716. 8004264: 68fb ldr r3, [r7, #12]
  10717. 8004266: 2b02 cmp r3, #2
  10718. 8004268: d101 bne.n 800426e <inc_lock+0x8a>
  10719. 800426a: 2300 movs r3, #0
  10720. 800426c: e040 b.n 80042f0 <inc_lock+0x10c>
  10721. Files[i].fs = dp->obj.fs;
  10722. 800426e: 687b ldr r3, [r7, #4]
  10723. 8004270: 681a ldr r2, [r3, #0]
  10724. 8004272: 4922 ldr r1, [pc, #136] ; (80042fc <inc_lock+0x118>)
  10725. 8004274: 68fb ldr r3, [r7, #12]
  10726. 8004276: 011b lsls r3, r3, #4
  10727. 8004278: 440b add r3, r1
  10728. 800427a: 601a str r2, [r3, #0]
  10729. Files[i].clu = dp->obj.sclust;
  10730. 800427c: 687b ldr r3, [r7, #4]
  10731. 800427e: 689a ldr r2, [r3, #8]
  10732. 8004280: 491e ldr r1, [pc, #120] ; (80042fc <inc_lock+0x118>)
  10733. 8004282: 68fb ldr r3, [r7, #12]
  10734. 8004284: 011b lsls r3, r3, #4
  10735. 8004286: 440b add r3, r1
  10736. 8004288: 3304 adds r3, #4
  10737. 800428a: 601a str r2, [r3, #0]
  10738. Files[i].ofs = dp->dptr;
  10739. 800428c: 687b ldr r3, [r7, #4]
  10740. 800428e: 695a ldr r2, [r3, #20]
  10741. 8004290: 491a ldr r1, [pc, #104] ; (80042fc <inc_lock+0x118>)
  10742. 8004292: 68fb ldr r3, [r7, #12]
  10743. 8004294: 011b lsls r3, r3, #4
  10744. 8004296: 440b add r3, r1
  10745. 8004298: 3308 adds r3, #8
  10746. 800429a: 601a str r2, [r3, #0]
  10747. Files[i].ctr = 0;
  10748. 800429c: 4a17 ldr r2, [pc, #92] ; (80042fc <inc_lock+0x118>)
  10749. 800429e: 68fb ldr r3, [r7, #12]
  10750. 80042a0: 011b lsls r3, r3, #4
  10751. 80042a2: 4413 add r3, r2
  10752. 80042a4: 330c adds r3, #12
  10753. 80042a6: 2200 movs r2, #0
  10754. 80042a8: 801a strh r2, [r3, #0]
  10755. }
  10756. if (acc && Files[i].ctr) return 0; /* Access violation (int err) */
  10757. 80042aa: 683b ldr r3, [r7, #0]
  10758. 80042ac: 2b00 cmp r3, #0
  10759. 80042ae: d009 beq.n 80042c4 <inc_lock+0xe0>
  10760. 80042b0: 4a12 ldr r2, [pc, #72] ; (80042fc <inc_lock+0x118>)
  10761. 80042b2: 68fb ldr r3, [r7, #12]
  10762. 80042b4: 011b lsls r3, r3, #4
  10763. 80042b6: 4413 add r3, r2
  10764. 80042b8: 330c adds r3, #12
  10765. 80042ba: 881b ldrh r3, [r3, #0]
  10766. 80042bc: 2b00 cmp r3, #0
  10767. 80042be: d001 beq.n 80042c4 <inc_lock+0xe0>
  10768. 80042c0: 2300 movs r3, #0
  10769. 80042c2: e015 b.n 80042f0 <inc_lock+0x10c>
  10770. Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
  10771. 80042c4: 683b ldr r3, [r7, #0]
  10772. 80042c6: 2b00 cmp r3, #0
  10773. 80042c8: d108 bne.n 80042dc <inc_lock+0xf8>
  10774. 80042ca: 4a0c ldr r2, [pc, #48] ; (80042fc <inc_lock+0x118>)
  10775. 80042cc: 68fb ldr r3, [r7, #12]
  10776. 80042ce: 011b lsls r3, r3, #4
  10777. 80042d0: 4413 add r3, r2
  10778. 80042d2: 330c adds r3, #12
  10779. 80042d4: 881b ldrh r3, [r3, #0]
  10780. 80042d6: 3301 adds r3, #1
  10781. 80042d8: b29a uxth r2, r3
  10782. 80042da: e001 b.n 80042e0 <inc_lock+0xfc>
  10783. 80042dc: f44f 7280 mov.w r2, #256 ; 0x100
  10784. 80042e0: 4906 ldr r1, [pc, #24] ; (80042fc <inc_lock+0x118>)
  10785. 80042e2: 68fb ldr r3, [r7, #12]
  10786. 80042e4: 011b lsls r3, r3, #4
  10787. 80042e6: 440b add r3, r1
  10788. 80042e8: 330c adds r3, #12
  10789. 80042ea: 801a strh r2, [r3, #0]
  10790. return i + 1;
  10791. 80042ec: 68fb ldr r3, [r7, #12]
  10792. 80042ee: 3301 adds r3, #1
  10793. }
  10794. 80042f0: 4618 mov r0, r3
  10795. 80042f2: 3714 adds r7, #20
  10796. 80042f4: 46bd mov sp, r7
  10797. 80042f6: bc80 pop {r7}
  10798. 80042f8: 4770 bx lr
  10799. 80042fa: bf00 nop
  10800. 80042fc: 200000b4 .word 0x200000b4
  10801. 08004300 <dec_lock>:
  10802. static
  10803. FRESULT dec_lock ( /* Decrement object open counter */
  10804. UINT i /* Semaphore index (1..) */
  10805. )
  10806. {
  10807. 8004300: b480 push {r7}
  10808. 8004302: b085 sub sp, #20
  10809. 8004304: af00 add r7, sp, #0
  10810. 8004306: 6078 str r0, [r7, #4]
  10811. WORD n;
  10812. FRESULT res;
  10813. if (--i < _FS_LOCK) { /* Shift index number origin from 0 */
  10814. 8004308: 687b ldr r3, [r7, #4]
  10815. 800430a: 3b01 subs r3, #1
  10816. 800430c: 607b str r3, [r7, #4]
  10817. 800430e: 687b ldr r3, [r7, #4]
  10818. 8004310: 2b01 cmp r3, #1
  10819. 8004312: d825 bhi.n 8004360 <dec_lock+0x60>
  10820. n = Files[i].ctr;
  10821. 8004314: 4a16 ldr r2, [pc, #88] ; (8004370 <dec_lock+0x70>)
  10822. 8004316: 687b ldr r3, [r7, #4]
  10823. 8004318: 011b lsls r3, r3, #4
  10824. 800431a: 4413 add r3, r2
  10825. 800431c: 330c adds r3, #12
  10826. 800431e: 881b ldrh r3, [r3, #0]
  10827. 8004320: 81fb strh r3, [r7, #14]
  10828. if (n == 0x100) n = 0; /* If write mode open, delete the entry */
  10829. 8004322: 89fb ldrh r3, [r7, #14]
  10830. 8004324: f5b3 7f80 cmp.w r3, #256 ; 0x100
  10831. 8004328: d101 bne.n 800432e <dec_lock+0x2e>
  10832. 800432a: 2300 movs r3, #0
  10833. 800432c: 81fb strh r3, [r7, #14]
  10834. if (n > 0) n--; /* Decrement read mode open count */
  10835. 800432e: 89fb ldrh r3, [r7, #14]
  10836. 8004330: 2b00 cmp r3, #0
  10837. 8004332: d002 beq.n 800433a <dec_lock+0x3a>
  10838. 8004334: 89fb ldrh r3, [r7, #14]
  10839. 8004336: 3b01 subs r3, #1
  10840. 8004338: 81fb strh r3, [r7, #14]
  10841. Files[i].ctr = n;
  10842. 800433a: 4a0d ldr r2, [pc, #52] ; (8004370 <dec_lock+0x70>)
  10843. 800433c: 687b ldr r3, [r7, #4]
  10844. 800433e: 011b lsls r3, r3, #4
  10845. 8004340: 4413 add r3, r2
  10846. 8004342: 330c adds r3, #12
  10847. 8004344: 89fa ldrh r2, [r7, #14]
  10848. 8004346: 801a strh r2, [r3, #0]
  10849. if (n == 0) Files[i].fs = 0; /* Delete the entry if open count gets zero */
  10850. 8004348: 89fb ldrh r3, [r7, #14]
  10851. 800434a: 2b00 cmp r3, #0
  10852. 800434c: d105 bne.n 800435a <dec_lock+0x5a>
  10853. 800434e: 4a08 ldr r2, [pc, #32] ; (8004370 <dec_lock+0x70>)
  10854. 8004350: 687b ldr r3, [r7, #4]
  10855. 8004352: 011b lsls r3, r3, #4
  10856. 8004354: 4413 add r3, r2
  10857. 8004356: 2200 movs r2, #0
  10858. 8004358: 601a str r2, [r3, #0]
  10859. res = FR_OK;
  10860. 800435a: 2300 movs r3, #0
  10861. 800435c: 737b strb r3, [r7, #13]
  10862. 800435e: e001 b.n 8004364 <dec_lock+0x64>
  10863. } else {
  10864. res = FR_INT_ERR; /* Invalid index nunber */
  10865. 8004360: 2302 movs r3, #2
  10866. 8004362: 737b strb r3, [r7, #13]
  10867. }
  10868. return res;
  10869. 8004364: 7b7b ldrb r3, [r7, #13]
  10870. }
  10871. 8004366: 4618 mov r0, r3
  10872. 8004368: 3714 adds r7, #20
  10873. 800436a: 46bd mov sp, r7
  10874. 800436c: bc80 pop {r7}
  10875. 800436e: 4770 bx lr
  10876. 8004370: 200000b4 .word 0x200000b4
  10877. 08004374 <clear_lock>:
  10878. static
  10879. void clear_lock ( /* Clear lock entries of the volume */
  10880. FATFS *fs
  10881. )
  10882. {
  10883. 8004374: b480 push {r7}
  10884. 8004376: b085 sub sp, #20
  10885. 8004378: af00 add r7, sp, #0
  10886. 800437a: 6078 str r0, [r7, #4]
  10887. UINT i;
  10888. for (i = 0; i < _FS_LOCK; i++) {
  10889. 800437c: 2300 movs r3, #0
  10890. 800437e: 60fb str r3, [r7, #12]
  10891. 8004380: e010 b.n 80043a4 <clear_lock+0x30>
  10892. if (Files[i].fs == fs) Files[i].fs = 0;
  10893. 8004382: 4a0c ldr r2, [pc, #48] ; (80043b4 <clear_lock+0x40>)
  10894. 8004384: 68fb ldr r3, [r7, #12]
  10895. 8004386: 011b lsls r3, r3, #4
  10896. 8004388: 4413 add r3, r2
  10897. 800438a: 681b ldr r3, [r3, #0]
  10898. 800438c: 687a ldr r2, [r7, #4]
  10899. 800438e: 429a cmp r2, r3
  10900. 8004390: d105 bne.n 800439e <clear_lock+0x2a>
  10901. 8004392: 4a08 ldr r2, [pc, #32] ; (80043b4 <clear_lock+0x40>)
  10902. 8004394: 68fb ldr r3, [r7, #12]
  10903. 8004396: 011b lsls r3, r3, #4
  10904. 8004398: 4413 add r3, r2
  10905. 800439a: 2200 movs r2, #0
  10906. 800439c: 601a str r2, [r3, #0]
  10907. for (i = 0; i < _FS_LOCK; i++) {
  10908. 800439e: 68fb ldr r3, [r7, #12]
  10909. 80043a0: 3301 adds r3, #1
  10910. 80043a2: 60fb str r3, [r7, #12]
  10911. 80043a4: 68fb ldr r3, [r7, #12]
  10912. 80043a6: 2b01 cmp r3, #1
  10913. 80043a8: d9eb bls.n 8004382 <clear_lock+0xe>
  10914. }
  10915. }
  10916. 80043aa: bf00 nop
  10917. 80043ac: 3714 adds r7, #20
  10918. 80043ae: 46bd mov sp, r7
  10919. 80043b0: bc80 pop {r7}
  10920. 80043b2: 4770 bx lr
  10921. 80043b4: 200000b4 .word 0x200000b4
  10922. 080043b8 <sync_window>:
  10923. #if !_FS_READONLY
  10924. static
  10925. FRESULT sync_window ( /* Returns FR_OK or FR_DISK_ERROR */
  10926. FATFS* fs /* File system object */
  10927. )
  10928. {
  10929. 80043b8: b580 push {r7, lr}
  10930. 80043ba: b086 sub sp, #24
  10931. 80043bc: af00 add r7, sp, #0
  10932. 80043be: 6078 str r0, [r7, #4]
  10933. DWORD wsect;
  10934. UINT nf;
  10935. FRESULT res = FR_OK;
  10936. 80043c0: 2300 movs r3, #0
  10937. 80043c2: 73fb strb r3, [r7, #15]
  10938. if (fs->wflag) { /* Write back the sector if it is dirty */
  10939. 80043c4: 687b ldr r3, [r7, #4]
  10940. 80043c6: 78db ldrb r3, [r3, #3]
  10941. 80043c8: 2b00 cmp r3, #0
  10942. 80043ca: d034 beq.n 8004436 <sync_window+0x7e>
  10943. wsect = fs->winsect; /* Current sector number */
  10944. 80043cc: 687b ldr r3, [r7, #4]
  10945. 80043ce: 6b5b ldr r3, [r3, #52] ; 0x34
  10946. 80043d0: 617b str r3, [r7, #20]
  10947. if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK) {
  10948. 80043d2: 687b ldr r3, [r7, #4]
  10949. 80043d4: 7858 ldrb r0, [r3, #1]
  10950. 80043d6: 687b ldr r3, [r7, #4]
  10951. 80043d8: f103 0138 add.w r1, r3, #56 ; 0x38
  10952. 80043dc: 2301 movs r3, #1
  10953. 80043de: 697a ldr r2, [r7, #20]
  10954. 80043e0: f7ff fd50 bl 8003e84 <disk_write>
  10955. 80043e4: 4603 mov r3, r0
  10956. 80043e6: 2b00 cmp r3, #0
  10957. 80043e8: d002 beq.n 80043f0 <sync_window+0x38>
  10958. res = FR_DISK_ERR;
  10959. 80043ea: 2301 movs r3, #1
  10960. 80043ec: 73fb strb r3, [r7, #15]
  10961. 80043ee: e022 b.n 8004436 <sync_window+0x7e>
  10962. } else {
  10963. fs->wflag = 0;
  10964. 80043f0: 687b ldr r3, [r7, #4]
  10965. 80043f2: 2200 movs r2, #0
  10966. 80043f4: 70da strb r2, [r3, #3]
  10967. if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */
  10968. 80043f6: 687b ldr r3, [r7, #4]
  10969. 80043f8: 6a9b ldr r3, [r3, #40] ; 0x28
  10970. 80043fa: 697a ldr r2, [r7, #20]
  10971. 80043fc: 1ad2 subs r2, r2, r3
  10972. 80043fe: 687b ldr r3, [r7, #4]
  10973. 8004400: 6a1b ldr r3, [r3, #32]
  10974. 8004402: 429a cmp r2, r3
  10975. 8004404: d217 bcs.n 8004436 <sync_window+0x7e>
  10976. for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */
  10977. 8004406: 687b ldr r3, [r7, #4]
  10978. 8004408: 789b ldrb r3, [r3, #2]
  10979. 800440a: 613b str r3, [r7, #16]
  10980. 800440c: e010 b.n 8004430 <sync_window+0x78>
  10981. wsect += fs->fsize;
  10982. 800440e: 687b ldr r3, [r7, #4]
  10983. 8004410: 6a1b ldr r3, [r3, #32]
  10984. 8004412: 697a ldr r2, [r7, #20]
  10985. 8004414: 4413 add r3, r2
  10986. 8004416: 617b str r3, [r7, #20]
  10987. disk_write(fs->drv, fs->win, wsect, 1);
  10988. 8004418: 687b ldr r3, [r7, #4]
  10989. 800441a: 7858 ldrb r0, [r3, #1]
  10990. 800441c: 687b ldr r3, [r7, #4]
  10991. 800441e: f103 0138 add.w r1, r3, #56 ; 0x38
  10992. 8004422: 2301 movs r3, #1
  10993. 8004424: 697a ldr r2, [r7, #20]
  10994. 8004426: f7ff fd2d bl 8003e84 <disk_write>
  10995. for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */
  10996. 800442a: 693b ldr r3, [r7, #16]
  10997. 800442c: 3b01 subs r3, #1
  10998. 800442e: 613b str r3, [r7, #16]
  10999. 8004430: 693b ldr r3, [r7, #16]
  11000. 8004432: 2b01 cmp r3, #1
  11001. 8004434: d8eb bhi.n 800440e <sync_window+0x56>
  11002. }
  11003. }
  11004. }
  11005. }
  11006. return res;
  11007. 8004436: 7bfb ldrb r3, [r7, #15]
  11008. }
  11009. 8004438: 4618 mov r0, r3
  11010. 800443a: 3718 adds r7, #24
  11011. 800443c: 46bd mov sp, r7
  11012. 800443e: bd80 pop {r7, pc}
  11013. 08004440 <move_window>:
  11014. static
  11015. FRESULT move_window ( /* Returns FR_OK or FR_DISK_ERROR */
  11016. FATFS* fs, /* File system object */
  11017. DWORD sector /* Sector number to make appearance in the fs->win[] */
  11018. )
  11019. {
  11020. 8004440: b580 push {r7, lr}
  11021. 8004442: b084 sub sp, #16
  11022. 8004444: af00 add r7, sp, #0
  11023. 8004446: 6078 str r0, [r7, #4]
  11024. 8004448: 6039 str r1, [r7, #0]
  11025. FRESULT res = FR_OK;
  11026. 800444a: 2300 movs r3, #0
  11027. 800444c: 73fb strb r3, [r7, #15]
  11028. if (sector != fs->winsect) { /* Window offset changed? */
  11029. 800444e: 687b ldr r3, [r7, #4]
  11030. 8004450: 6b5b ldr r3, [r3, #52] ; 0x34
  11031. 8004452: 683a ldr r2, [r7, #0]
  11032. 8004454: 429a cmp r2, r3
  11033. 8004456: d01b beq.n 8004490 <move_window+0x50>
  11034. #if !_FS_READONLY
  11035. res = sync_window(fs); /* Write-back changes */
  11036. 8004458: 6878 ldr r0, [r7, #4]
  11037. 800445a: f7ff ffad bl 80043b8 <sync_window>
  11038. 800445e: 4603 mov r3, r0
  11039. 8004460: 73fb strb r3, [r7, #15]
  11040. #endif
  11041. if (res == FR_OK) { /* Fill sector window with new data */
  11042. 8004462: 7bfb ldrb r3, [r7, #15]
  11043. 8004464: 2b00 cmp r3, #0
  11044. 8004466: d113 bne.n 8004490 <move_window+0x50>
  11045. if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK) {
  11046. 8004468: 687b ldr r3, [r7, #4]
  11047. 800446a: 7858 ldrb r0, [r3, #1]
  11048. 800446c: 687b ldr r3, [r7, #4]
  11049. 800446e: f103 0138 add.w r1, r3, #56 ; 0x38
  11050. 8004472: 2301 movs r3, #1
  11051. 8004474: 683a ldr r2, [r7, #0]
  11052. 8004476: f7ff fce5 bl 8003e44 <disk_read>
  11053. 800447a: 4603 mov r3, r0
  11054. 800447c: 2b00 cmp r3, #0
  11055. 800447e: d004 beq.n 800448a <move_window+0x4a>
  11056. sector = 0xFFFFFFFF; /* Invalidate window if data is not reliable */
  11057. 8004480: f04f 33ff mov.w r3, #4294967295
  11058. 8004484: 603b str r3, [r7, #0]
  11059. res = FR_DISK_ERR;
  11060. 8004486: 2301 movs r3, #1
  11061. 8004488: 73fb strb r3, [r7, #15]
  11062. }
  11063. fs->winsect = sector;
  11064. 800448a: 687b ldr r3, [r7, #4]
  11065. 800448c: 683a ldr r2, [r7, #0]
  11066. 800448e: 635a str r2, [r3, #52] ; 0x34
  11067. }
  11068. }
  11069. return res;
  11070. 8004490: 7bfb ldrb r3, [r7, #15]
  11071. }
  11072. 8004492: 4618 mov r0, r3
  11073. 8004494: 3710 adds r7, #16
  11074. 8004496: 46bd mov sp, r7
  11075. 8004498: bd80 pop {r7, pc}
  11076. ...
  11077. 0800449c <sync_fs>:
  11078. static
  11079. FRESULT sync_fs ( /* FR_OK:succeeded, !=0:error */
  11080. FATFS* fs /* File system object */
  11081. )
  11082. {
  11083. 800449c: b580 push {r7, lr}
  11084. 800449e: b084 sub sp, #16
  11085. 80044a0: af00 add r7, sp, #0
  11086. 80044a2: 6078 str r0, [r7, #4]
  11087. FRESULT res;
  11088. res = sync_window(fs);
  11089. 80044a4: 6878 ldr r0, [r7, #4]
  11090. 80044a6: f7ff ff87 bl 80043b8 <sync_window>
  11091. 80044aa: 4603 mov r3, r0
  11092. 80044ac: 73fb strb r3, [r7, #15]
  11093. if (res == FR_OK) {
  11094. 80044ae: 7bfb ldrb r3, [r7, #15]
  11095. 80044b0: 2b00 cmp r3, #0
  11096. 80044b2: d159 bne.n 8004568 <sync_fs+0xcc>
  11097. /* Update FSInfo sector if needed */
  11098. if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) {
  11099. 80044b4: 687b ldr r3, [r7, #4]
  11100. 80044b6: 781b ldrb r3, [r3, #0]
  11101. 80044b8: 2b03 cmp r3, #3
  11102. 80044ba: d149 bne.n 8004550 <sync_fs+0xb4>
  11103. 80044bc: 687b ldr r3, [r7, #4]
  11104. 80044be: 791b ldrb r3, [r3, #4]
  11105. 80044c0: 2b01 cmp r3, #1
  11106. 80044c2: d145 bne.n 8004550 <sync_fs+0xb4>
  11107. /* Create FSInfo structure */
  11108. mem_set(fs->win, 0, SS(fs));
  11109. 80044c4: 687b ldr r3, [r7, #4]
  11110. 80044c6: f103 0038 add.w r0, r3, #56 ; 0x38
  11111. 80044ca: 687b ldr r3, [r7, #4]
  11112. 80044cc: 899b ldrh r3, [r3, #12]
  11113. 80044ce: 461a mov r2, r3
  11114. 80044d0: 2100 movs r1, #0
  11115. 80044d2: f7ff fdb3 bl 800403c <mem_set>
  11116. st_word(fs->win + BS_55AA, 0xAA55);
  11117. 80044d6: 687b ldr r3, [r7, #4]
  11118. 80044d8: 3338 adds r3, #56 ; 0x38
  11119. 80044da: f503 73ff add.w r3, r3, #510 ; 0x1fe
  11120. 80044de: f64a 2155 movw r1, #43605 ; 0xaa55
  11121. 80044e2: 4618 mov r0, r3
  11122. 80044e4: f7ff fd45 bl 8003f72 <st_word>
  11123. st_dword(fs->win + FSI_LeadSig, 0x41615252);
  11124. 80044e8: 687b ldr r3, [r7, #4]
  11125. 80044ea: 3338 adds r3, #56 ; 0x38
  11126. 80044ec: 4921 ldr r1, [pc, #132] ; (8004574 <sync_fs+0xd8>)
  11127. 80044ee: 4618 mov r0, r3
  11128. 80044f0: f7ff fd59 bl 8003fa6 <st_dword>
  11129. st_dword(fs->win + FSI_StrucSig, 0x61417272);
  11130. 80044f4: 687b ldr r3, [r7, #4]
  11131. 80044f6: 3338 adds r3, #56 ; 0x38
  11132. 80044f8: f503 73f2 add.w r3, r3, #484 ; 0x1e4
  11133. 80044fc: 491e ldr r1, [pc, #120] ; (8004578 <sync_fs+0xdc>)
  11134. 80044fe: 4618 mov r0, r3
  11135. 8004500: f7ff fd51 bl 8003fa6 <st_dword>
  11136. st_dword(fs->win + FSI_Free_Count, fs->free_clst);
  11137. 8004504: 687b ldr r3, [r7, #4]
  11138. 8004506: 3338 adds r3, #56 ; 0x38
  11139. 8004508: f503 72f4 add.w r2, r3, #488 ; 0x1e8
  11140. 800450c: 687b ldr r3, [r7, #4]
  11141. 800450e: 699b ldr r3, [r3, #24]
  11142. 8004510: 4619 mov r1, r3
  11143. 8004512: 4610 mov r0, r2
  11144. 8004514: f7ff fd47 bl 8003fa6 <st_dword>
  11145. st_dword(fs->win + FSI_Nxt_Free, fs->last_clst);
  11146. 8004518: 687b ldr r3, [r7, #4]
  11147. 800451a: 3338 adds r3, #56 ; 0x38
  11148. 800451c: f503 72f6 add.w r2, r3, #492 ; 0x1ec
  11149. 8004520: 687b ldr r3, [r7, #4]
  11150. 8004522: 695b ldr r3, [r3, #20]
  11151. 8004524: 4619 mov r1, r3
  11152. 8004526: 4610 mov r0, r2
  11153. 8004528: f7ff fd3d bl 8003fa6 <st_dword>
  11154. /* Write it into the FSInfo sector */
  11155. fs->winsect = fs->volbase + 1;
  11156. 800452c: 687b ldr r3, [r7, #4]
  11157. 800452e: 6a5b ldr r3, [r3, #36] ; 0x24
  11158. 8004530: 1c5a adds r2, r3, #1
  11159. 8004532: 687b ldr r3, [r7, #4]
  11160. 8004534: 635a str r2, [r3, #52] ; 0x34
  11161. disk_write(fs->drv, fs->win, fs->winsect, 1);
  11162. 8004536: 687b ldr r3, [r7, #4]
  11163. 8004538: 7858 ldrb r0, [r3, #1]
  11164. 800453a: 687b ldr r3, [r7, #4]
  11165. 800453c: f103 0138 add.w r1, r3, #56 ; 0x38
  11166. 8004540: 687b ldr r3, [r7, #4]
  11167. 8004542: 6b5a ldr r2, [r3, #52] ; 0x34
  11168. 8004544: 2301 movs r3, #1
  11169. 8004546: f7ff fc9d bl 8003e84 <disk_write>
  11170. fs->fsi_flag = 0;
  11171. 800454a: 687b ldr r3, [r7, #4]
  11172. 800454c: 2200 movs r2, #0
  11173. 800454e: 711a strb r2, [r3, #4]
  11174. }
  11175. /* Make sure that no pending write process in the physical drive */
  11176. if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) res = FR_DISK_ERR;
  11177. 8004550: 687b ldr r3, [r7, #4]
  11178. 8004552: 785b ldrb r3, [r3, #1]
  11179. 8004554: 2200 movs r2, #0
  11180. 8004556: 2100 movs r1, #0
  11181. 8004558: 4618 mov r0, r3
  11182. 800455a: f7ff fcb3 bl 8003ec4 <disk_ioctl>
  11183. 800455e: 4603 mov r3, r0
  11184. 8004560: 2b00 cmp r3, #0
  11185. 8004562: d001 beq.n 8004568 <sync_fs+0xcc>
  11186. 8004564: 2301 movs r3, #1
  11187. 8004566: 73fb strb r3, [r7, #15]
  11188. }
  11189. return res;
  11190. 8004568: 7bfb ldrb r3, [r7, #15]
  11191. }
  11192. 800456a: 4618 mov r0, r3
  11193. 800456c: 3710 adds r7, #16
  11194. 800456e: 46bd mov sp, r7
  11195. 8004570: bd80 pop {r7, pc}
  11196. 8004572: bf00 nop
  11197. 8004574: 41615252 .word 0x41615252
  11198. 8004578: 61417272 .word 0x61417272
  11199. 0800457c <clust2sect>:
  11200. static
  11201. DWORD clust2sect ( /* !=0:Sector number, 0:Failed (invalid cluster#) */
  11202. FATFS* fs, /* File system object */
  11203. DWORD clst /* Cluster# to be converted */
  11204. )
  11205. {
  11206. 800457c: b480 push {r7}
  11207. 800457e: b083 sub sp, #12
  11208. 8004580: af00 add r7, sp, #0
  11209. 8004582: 6078 str r0, [r7, #4]
  11210. 8004584: 6039 str r1, [r7, #0]
  11211. clst -= 2;
  11212. 8004586: 683b ldr r3, [r7, #0]
  11213. 8004588: 3b02 subs r3, #2
  11214. 800458a: 603b str r3, [r7, #0]
  11215. if (clst >= fs->n_fatent - 2) return 0; /* Invalid cluster# */
  11216. 800458c: 687b ldr r3, [r7, #4]
  11217. 800458e: 69db ldr r3, [r3, #28]
  11218. 8004590: 3b02 subs r3, #2
  11219. 8004592: 683a ldr r2, [r7, #0]
  11220. 8004594: 429a cmp r2, r3
  11221. 8004596: d301 bcc.n 800459c <clust2sect+0x20>
  11222. 8004598: 2300 movs r3, #0
  11223. 800459a: e008 b.n 80045ae <clust2sect+0x32>
  11224. return clst * fs->csize + fs->database;
  11225. 800459c: 687b ldr r3, [r7, #4]
  11226. 800459e: 895b ldrh r3, [r3, #10]
  11227. 80045a0: 461a mov r2, r3
  11228. 80045a2: 683b ldr r3, [r7, #0]
  11229. 80045a4: fb03 f202 mul.w r2, r3, r2
  11230. 80045a8: 687b ldr r3, [r7, #4]
  11231. 80045aa: 6b1b ldr r3, [r3, #48] ; 0x30
  11232. 80045ac: 4413 add r3, r2
  11233. }
  11234. 80045ae: 4618 mov r0, r3
  11235. 80045b0: 370c adds r7, #12
  11236. 80045b2: 46bd mov sp, r7
  11237. 80045b4: bc80 pop {r7}
  11238. 80045b6: 4770 bx lr
  11239. 080045b8 <get_fat>:
  11240. static
  11241. DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, 2..0x7FFFFFFF:Cluster status */
  11242. _FDID* obj, /* Corresponding object */
  11243. DWORD clst /* Cluster number to get the value */
  11244. )
  11245. {
  11246. 80045b8: b580 push {r7, lr}
  11247. 80045ba: b086 sub sp, #24
  11248. 80045bc: af00 add r7, sp, #0
  11249. 80045be: 6078 str r0, [r7, #4]
  11250. 80045c0: 6039 str r1, [r7, #0]
  11251. UINT wc, bc;
  11252. DWORD val;
  11253. FATFS *fs = obj->fs;
  11254. 80045c2: 687b ldr r3, [r7, #4]
  11255. 80045c4: 681b ldr r3, [r3, #0]
  11256. 80045c6: 613b str r3, [r7, #16]
  11257. if (clst < 2 || clst >= fs->n_fatent) { /* Check if in valid range */
  11258. 80045c8: 683b ldr r3, [r7, #0]
  11259. 80045ca: 2b01 cmp r3, #1
  11260. 80045cc: d904 bls.n 80045d8 <get_fat+0x20>
  11261. 80045ce: 693b ldr r3, [r7, #16]
  11262. 80045d0: 69db ldr r3, [r3, #28]
  11263. 80045d2: 683a ldr r2, [r7, #0]
  11264. 80045d4: 429a cmp r2, r3
  11265. 80045d6: d302 bcc.n 80045de <get_fat+0x26>
  11266. val = 1; /* Internal error */
  11267. 80045d8: 2301 movs r3, #1
  11268. 80045da: 617b str r3, [r7, #20]
  11269. 80045dc: e0b7 b.n 800474e <get_fat+0x196>
  11270. } else {
  11271. val = 0xFFFFFFFF; /* Default value falls on disk error */
  11272. 80045de: f04f 33ff mov.w r3, #4294967295
  11273. 80045e2: 617b str r3, [r7, #20]
  11274. switch (fs->fs_type) {
  11275. 80045e4: 693b ldr r3, [r7, #16]
  11276. 80045e6: 781b ldrb r3, [r3, #0]
  11277. 80045e8: 2b02 cmp r3, #2
  11278. 80045ea: d05a beq.n 80046a2 <get_fat+0xea>
  11279. 80045ec: 2b03 cmp r3, #3
  11280. 80045ee: d07d beq.n 80046ec <get_fat+0x134>
  11281. 80045f0: 2b01 cmp r3, #1
  11282. 80045f2: f040 80a2 bne.w 800473a <get_fat+0x182>
  11283. case FS_FAT12 :
  11284. bc = (UINT)clst; bc += bc / 2;
  11285. 80045f6: 683b ldr r3, [r7, #0]
  11286. 80045f8: 60fb str r3, [r7, #12]
  11287. 80045fa: 68fb ldr r3, [r7, #12]
  11288. 80045fc: 085b lsrs r3, r3, #1
  11289. 80045fe: 68fa ldr r2, [r7, #12]
  11290. 8004600: 4413 add r3, r2
  11291. 8004602: 60fb str r3, [r7, #12]
  11292. if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
  11293. 8004604: 693b ldr r3, [r7, #16]
  11294. 8004606: 6a9a ldr r2, [r3, #40] ; 0x28
  11295. 8004608: 693b ldr r3, [r7, #16]
  11296. 800460a: 899b ldrh r3, [r3, #12]
  11297. 800460c: 4619 mov r1, r3
  11298. 800460e: 68fb ldr r3, [r7, #12]
  11299. 8004610: fbb3 f3f1 udiv r3, r3, r1
  11300. 8004614: 4413 add r3, r2
  11301. 8004616: 4619 mov r1, r3
  11302. 8004618: 6938 ldr r0, [r7, #16]
  11303. 800461a: f7ff ff11 bl 8004440 <move_window>
  11304. 800461e: 4603 mov r3, r0
  11305. 8004620: 2b00 cmp r3, #0
  11306. 8004622: f040 808d bne.w 8004740 <get_fat+0x188>
  11307. wc = fs->win[bc++ % SS(fs)];
  11308. 8004626: 68fb ldr r3, [r7, #12]
  11309. 8004628: 1c5a adds r2, r3, #1
  11310. 800462a: 60fa str r2, [r7, #12]
  11311. 800462c: 693a ldr r2, [r7, #16]
  11312. 800462e: 8992 ldrh r2, [r2, #12]
  11313. 8004630: fbb3 f1f2 udiv r1, r3, r2
  11314. 8004634: fb02 f201 mul.w r2, r2, r1
  11315. 8004638: 1a9b subs r3, r3, r2
  11316. 800463a: 693a ldr r2, [r7, #16]
  11317. 800463c: 4413 add r3, r2
  11318. 800463e: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
  11319. 8004642: 60bb str r3, [r7, #8]
  11320. if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
  11321. 8004644: 693b ldr r3, [r7, #16]
  11322. 8004646: 6a9a ldr r2, [r3, #40] ; 0x28
  11323. 8004648: 693b ldr r3, [r7, #16]
  11324. 800464a: 899b ldrh r3, [r3, #12]
  11325. 800464c: 4619 mov r1, r3
  11326. 800464e: 68fb ldr r3, [r7, #12]
  11327. 8004650: fbb3 f3f1 udiv r3, r3, r1
  11328. 8004654: 4413 add r3, r2
  11329. 8004656: 4619 mov r1, r3
  11330. 8004658: 6938 ldr r0, [r7, #16]
  11331. 800465a: f7ff fef1 bl 8004440 <move_window>
  11332. 800465e: 4603 mov r3, r0
  11333. 8004660: 2b00 cmp r3, #0
  11334. 8004662: d16f bne.n 8004744 <get_fat+0x18c>
  11335. wc |= fs->win[bc % SS(fs)] << 8;
  11336. 8004664: 693b ldr r3, [r7, #16]
  11337. 8004666: 899b ldrh r3, [r3, #12]
  11338. 8004668: 461a mov r2, r3
  11339. 800466a: 68fb ldr r3, [r7, #12]
  11340. 800466c: fbb3 f1f2 udiv r1, r3, r2
  11341. 8004670: fb02 f201 mul.w r2, r2, r1
  11342. 8004674: 1a9b subs r3, r3, r2
  11343. 8004676: 693a ldr r2, [r7, #16]
  11344. 8004678: 4413 add r3, r2
  11345. 800467a: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
  11346. 800467e: 021b lsls r3, r3, #8
  11347. 8004680: 461a mov r2, r3
  11348. 8004682: 68bb ldr r3, [r7, #8]
  11349. 8004684: 4313 orrs r3, r2
  11350. 8004686: 60bb str r3, [r7, #8]
  11351. val = (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
  11352. 8004688: 683b ldr r3, [r7, #0]
  11353. 800468a: f003 0301 and.w r3, r3, #1
  11354. 800468e: 2b00 cmp r3, #0
  11355. 8004690: d002 beq.n 8004698 <get_fat+0xe0>
  11356. 8004692: 68bb ldr r3, [r7, #8]
  11357. 8004694: 091b lsrs r3, r3, #4
  11358. 8004696: e002 b.n 800469e <get_fat+0xe6>
  11359. 8004698: 68bb ldr r3, [r7, #8]
  11360. 800469a: f3c3 030b ubfx r3, r3, #0, #12
  11361. 800469e: 617b str r3, [r7, #20]
  11362. break;
  11363. 80046a0: e055 b.n 800474e <get_fat+0x196>
  11364. case FS_FAT16 :
  11365. if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
  11366. 80046a2: 693b ldr r3, [r7, #16]
  11367. 80046a4: 6a9a ldr r2, [r3, #40] ; 0x28
  11368. 80046a6: 693b ldr r3, [r7, #16]
  11369. 80046a8: 899b ldrh r3, [r3, #12]
  11370. 80046aa: 085b lsrs r3, r3, #1
  11371. 80046ac: b29b uxth r3, r3
  11372. 80046ae: 4619 mov r1, r3
  11373. 80046b0: 683b ldr r3, [r7, #0]
  11374. 80046b2: fbb3 f3f1 udiv r3, r3, r1
  11375. 80046b6: 4413 add r3, r2
  11376. 80046b8: 4619 mov r1, r3
  11377. 80046ba: 6938 ldr r0, [r7, #16]
  11378. 80046bc: f7ff fec0 bl 8004440 <move_window>
  11379. 80046c0: 4603 mov r3, r0
  11380. 80046c2: 2b00 cmp r3, #0
  11381. 80046c4: d140 bne.n 8004748 <get_fat+0x190>
  11382. val = ld_word(fs->win + clst * 2 % SS(fs));
  11383. 80046c6: 693b ldr r3, [r7, #16]
  11384. 80046c8: f103 0138 add.w r1, r3, #56 ; 0x38
  11385. 80046cc: 683b ldr r3, [r7, #0]
  11386. 80046ce: 005b lsls r3, r3, #1
  11387. 80046d0: 693a ldr r2, [r7, #16]
  11388. 80046d2: 8992 ldrh r2, [r2, #12]
  11389. 80046d4: fbb3 f0f2 udiv r0, r3, r2
  11390. 80046d8: fb02 f200 mul.w r2, r2, r0
  11391. 80046dc: 1a9b subs r3, r3, r2
  11392. 80046de: 440b add r3, r1
  11393. 80046e0: 4618 mov r0, r3
  11394. 80046e2: f7ff fc0d bl 8003f00 <ld_word>
  11395. 80046e6: 4603 mov r3, r0
  11396. 80046e8: 617b str r3, [r7, #20]
  11397. break;
  11398. 80046ea: e030 b.n 800474e <get_fat+0x196>
  11399. case FS_FAT32 :
  11400. if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
  11401. 80046ec: 693b ldr r3, [r7, #16]
  11402. 80046ee: 6a9a ldr r2, [r3, #40] ; 0x28
  11403. 80046f0: 693b ldr r3, [r7, #16]
  11404. 80046f2: 899b ldrh r3, [r3, #12]
  11405. 80046f4: 089b lsrs r3, r3, #2
  11406. 80046f6: b29b uxth r3, r3
  11407. 80046f8: 4619 mov r1, r3
  11408. 80046fa: 683b ldr r3, [r7, #0]
  11409. 80046fc: fbb3 f3f1 udiv r3, r3, r1
  11410. 8004700: 4413 add r3, r2
  11411. 8004702: 4619 mov r1, r3
  11412. 8004704: 6938 ldr r0, [r7, #16]
  11413. 8004706: f7ff fe9b bl 8004440 <move_window>
  11414. 800470a: 4603 mov r3, r0
  11415. 800470c: 2b00 cmp r3, #0
  11416. 800470e: d11d bne.n 800474c <get_fat+0x194>
  11417. val = ld_dword(fs->win + clst * 4 % SS(fs)) & 0x0FFFFFFF;
  11418. 8004710: 693b ldr r3, [r7, #16]
  11419. 8004712: f103 0138 add.w r1, r3, #56 ; 0x38
  11420. 8004716: 683b ldr r3, [r7, #0]
  11421. 8004718: 009b lsls r3, r3, #2
  11422. 800471a: 693a ldr r2, [r7, #16]
  11423. 800471c: 8992 ldrh r2, [r2, #12]
  11424. 800471e: fbb3 f0f2 udiv r0, r3, r2
  11425. 8004722: fb02 f200 mul.w r2, r2, r0
  11426. 8004726: 1a9b subs r3, r3, r2
  11427. 8004728: 440b add r3, r1
  11428. 800472a: 4618 mov r0, r3
  11429. 800472c: f7ff fbff bl 8003f2e <ld_dword>
  11430. 8004730: 4603 mov r3, r0
  11431. 8004732: f023 4370 bic.w r3, r3, #4026531840 ; 0xf0000000
  11432. 8004736: 617b str r3, [r7, #20]
  11433. break;
  11434. 8004738: e009 b.n 800474e <get_fat+0x196>
  11435. }
  11436. }
  11437. /* go to default */
  11438. #endif
  11439. default:
  11440. val = 1; /* Internal error */
  11441. 800473a: 2301 movs r3, #1
  11442. 800473c: 617b str r3, [r7, #20]
  11443. 800473e: e006 b.n 800474e <get_fat+0x196>
  11444. if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
  11445. 8004740: bf00 nop
  11446. 8004742: e004 b.n 800474e <get_fat+0x196>
  11447. if (move_window(fs, fs->fatbase + (bc / SS(fs))) != FR_OK) break;
  11448. 8004744: bf00 nop
  11449. 8004746: e002 b.n 800474e <get_fat+0x196>
  11450. if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))) != FR_OK) break;
  11451. 8004748: bf00 nop
  11452. 800474a: e000 b.n 800474e <get_fat+0x196>
  11453. if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))) != FR_OK) break;
  11454. 800474c: bf00 nop
  11455. }
  11456. }
  11457. return val;
  11458. 800474e: 697b ldr r3, [r7, #20]
  11459. }
  11460. 8004750: 4618 mov r0, r3
  11461. 8004752: 3718 adds r7, #24
  11462. 8004754: 46bd mov sp, r7
  11463. 8004756: bd80 pop {r7, pc}
  11464. 08004758 <put_fat>:
  11465. FRESULT put_fat ( /* FR_OK(0):succeeded, !=0:error */
  11466. FATFS* fs, /* Corresponding file system object */
  11467. DWORD clst, /* FAT index number (cluster number) to be changed */
  11468. DWORD val /* New value to be set to the entry */
  11469. )
  11470. {
  11471. 8004758: b590 push {r4, r7, lr}
  11472. 800475a: b089 sub sp, #36 ; 0x24
  11473. 800475c: af00 add r7, sp, #0
  11474. 800475e: 60f8 str r0, [r7, #12]
  11475. 8004760: 60b9 str r1, [r7, #8]
  11476. 8004762: 607a str r2, [r7, #4]
  11477. UINT bc;
  11478. BYTE *p;
  11479. FRESULT res = FR_INT_ERR;
  11480. 8004764: 2302 movs r3, #2
  11481. 8004766: 77fb strb r3, [r7, #31]
  11482. if (clst >= 2 && clst < fs->n_fatent) { /* Check if in valid range */
  11483. 8004768: 68bb ldr r3, [r7, #8]
  11484. 800476a: 2b01 cmp r3, #1
  11485. 800476c: f240 8106 bls.w 800497c <put_fat+0x224>
  11486. 8004770: 68fb ldr r3, [r7, #12]
  11487. 8004772: 69db ldr r3, [r3, #28]
  11488. 8004774: 68ba ldr r2, [r7, #8]
  11489. 8004776: 429a cmp r2, r3
  11490. 8004778: f080 8100 bcs.w 800497c <put_fat+0x224>
  11491. switch (fs->fs_type) {
  11492. 800477c: 68fb ldr r3, [r7, #12]
  11493. 800477e: 781b ldrb r3, [r3, #0]
  11494. 8004780: 2b02 cmp r3, #2
  11495. 8004782: f000 8088 beq.w 8004896 <put_fat+0x13e>
  11496. 8004786: 2b03 cmp r3, #3
  11497. 8004788: f000 80b0 beq.w 80048ec <put_fat+0x194>
  11498. 800478c: 2b01 cmp r3, #1
  11499. 800478e: f040 80f5 bne.w 800497c <put_fat+0x224>
  11500. case FS_FAT12 : /* Bitfield items */
  11501. bc = (UINT)clst; bc += bc / 2;
  11502. 8004792: 68bb ldr r3, [r7, #8]
  11503. 8004794: 61bb str r3, [r7, #24]
  11504. 8004796: 69bb ldr r3, [r7, #24]
  11505. 8004798: 085b lsrs r3, r3, #1
  11506. 800479a: 69ba ldr r2, [r7, #24]
  11507. 800479c: 4413 add r3, r2
  11508. 800479e: 61bb str r3, [r7, #24]
  11509. res = move_window(fs, fs->fatbase + (bc / SS(fs)));
  11510. 80047a0: 68fb ldr r3, [r7, #12]
  11511. 80047a2: 6a9a ldr r2, [r3, #40] ; 0x28
  11512. 80047a4: 68fb ldr r3, [r7, #12]
  11513. 80047a6: 899b ldrh r3, [r3, #12]
  11514. 80047a8: 4619 mov r1, r3
  11515. 80047aa: 69bb ldr r3, [r7, #24]
  11516. 80047ac: fbb3 f3f1 udiv r3, r3, r1
  11517. 80047b0: 4413 add r3, r2
  11518. 80047b2: 4619 mov r1, r3
  11519. 80047b4: 68f8 ldr r0, [r7, #12]
  11520. 80047b6: f7ff fe43 bl 8004440 <move_window>
  11521. 80047ba: 4603 mov r3, r0
  11522. 80047bc: 77fb strb r3, [r7, #31]
  11523. if (res != FR_OK) break;
  11524. 80047be: 7ffb ldrb r3, [r7, #31]
  11525. 80047c0: 2b00 cmp r3, #0
  11526. 80047c2: f040 80d4 bne.w 800496e <put_fat+0x216>
  11527. p = fs->win + bc++ % SS(fs);
  11528. 80047c6: 68fb ldr r3, [r7, #12]
  11529. 80047c8: f103 0138 add.w r1, r3, #56 ; 0x38
  11530. 80047cc: 69bb ldr r3, [r7, #24]
  11531. 80047ce: 1c5a adds r2, r3, #1
  11532. 80047d0: 61ba str r2, [r7, #24]
  11533. 80047d2: 68fa ldr r2, [r7, #12]
  11534. 80047d4: 8992 ldrh r2, [r2, #12]
  11535. 80047d6: fbb3 f0f2 udiv r0, r3, r2
  11536. 80047da: fb02 f200 mul.w r2, r2, r0
  11537. 80047de: 1a9b subs r3, r3, r2
  11538. 80047e0: 440b add r3, r1
  11539. 80047e2: 617b str r3, [r7, #20]
  11540. *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
  11541. 80047e4: 68bb ldr r3, [r7, #8]
  11542. 80047e6: f003 0301 and.w r3, r3, #1
  11543. 80047ea: 2b00 cmp r3, #0
  11544. 80047ec: d00d beq.n 800480a <put_fat+0xb2>
  11545. 80047ee: 697b ldr r3, [r7, #20]
  11546. 80047f0: 781b ldrb r3, [r3, #0]
  11547. 80047f2: b25b sxtb r3, r3
  11548. 80047f4: f003 030f and.w r3, r3, #15
  11549. 80047f8: b25a sxtb r2, r3
  11550. 80047fa: 687b ldr r3, [r7, #4]
  11551. 80047fc: b2db uxtb r3, r3
  11552. 80047fe: 011b lsls r3, r3, #4
  11553. 8004800: b25b sxtb r3, r3
  11554. 8004802: 4313 orrs r3, r2
  11555. 8004804: b25b sxtb r3, r3
  11556. 8004806: b2db uxtb r3, r3
  11557. 8004808: e001 b.n 800480e <put_fat+0xb6>
  11558. 800480a: 687b ldr r3, [r7, #4]
  11559. 800480c: b2db uxtb r3, r3
  11560. 800480e: 697a ldr r2, [r7, #20]
  11561. 8004810: 7013 strb r3, [r2, #0]
  11562. fs->wflag = 1;
  11563. 8004812: 68fb ldr r3, [r7, #12]
  11564. 8004814: 2201 movs r2, #1
  11565. 8004816: 70da strb r2, [r3, #3]
  11566. res = move_window(fs, fs->fatbase + (bc / SS(fs)));
  11567. 8004818: 68fb ldr r3, [r7, #12]
  11568. 800481a: 6a9a ldr r2, [r3, #40] ; 0x28
  11569. 800481c: 68fb ldr r3, [r7, #12]
  11570. 800481e: 899b ldrh r3, [r3, #12]
  11571. 8004820: 4619 mov r1, r3
  11572. 8004822: 69bb ldr r3, [r7, #24]
  11573. 8004824: fbb3 f3f1 udiv r3, r3, r1
  11574. 8004828: 4413 add r3, r2
  11575. 800482a: 4619 mov r1, r3
  11576. 800482c: 68f8 ldr r0, [r7, #12]
  11577. 800482e: f7ff fe07 bl 8004440 <move_window>
  11578. 8004832: 4603 mov r3, r0
  11579. 8004834: 77fb strb r3, [r7, #31]
  11580. if (res != FR_OK) break;
  11581. 8004836: 7ffb ldrb r3, [r7, #31]
  11582. 8004838: 2b00 cmp r3, #0
  11583. 800483a: f040 809a bne.w 8004972 <put_fat+0x21a>
  11584. p = fs->win + bc % SS(fs);
  11585. 800483e: 68fb ldr r3, [r7, #12]
  11586. 8004840: f103 0138 add.w r1, r3, #56 ; 0x38
  11587. 8004844: 68fb ldr r3, [r7, #12]
  11588. 8004846: 899b ldrh r3, [r3, #12]
  11589. 8004848: 461a mov r2, r3
  11590. 800484a: 69bb ldr r3, [r7, #24]
  11591. 800484c: fbb3 f0f2 udiv r0, r3, r2
  11592. 8004850: fb02 f200 mul.w r2, r2, r0
  11593. 8004854: 1a9b subs r3, r3, r2
  11594. 8004856: 440b add r3, r1
  11595. 8004858: 617b str r3, [r7, #20]
  11596. *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
  11597. 800485a: 68bb ldr r3, [r7, #8]
  11598. 800485c: f003 0301 and.w r3, r3, #1
  11599. 8004860: 2b00 cmp r3, #0
  11600. 8004862: d003 beq.n 800486c <put_fat+0x114>
  11601. 8004864: 687b ldr r3, [r7, #4]
  11602. 8004866: 091b lsrs r3, r3, #4
  11603. 8004868: b2db uxtb r3, r3
  11604. 800486a: e00e b.n 800488a <put_fat+0x132>
  11605. 800486c: 697b ldr r3, [r7, #20]
  11606. 800486e: 781b ldrb r3, [r3, #0]
  11607. 8004870: b25b sxtb r3, r3
  11608. 8004872: f023 030f bic.w r3, r3, #15
  11609. 8004876: b25a sxtb r2, r3
  11610. 8004878: 687b ldr r3, [r7, #4]
  11611. 800487a: 0a1b lsrs r3, r3, #8
  11612. 800487c: b25b sxtb r3, r3
  11613. 800487e: f003 030f and.w r3, r3, #15
  11614. 8004882: b25b sxtb r3, r3
  11615. 8004884: 4313 orrs r3, r2
  11616. 8004886: b25b sxtb r3, r3
  11617. 8004888: b2db uxtb r3, r3
  11618. 800488a: 697a ldr r2, [r7, #20]
  11619. 800488c: 7013 strb r3, [r2, #0]
  11620. fs->wflag = 1;
  11621. 800488e: 68fb ldr r3, [r7, #12]
  11622. 8004890: 2201 movs r2, #1
  11623. 8004892: 70da strb r2, [r3, #3]
  11624. break;
  11625. 8004894: e072 b.n 800497c <put_fat+0x224>
  11626. case FS_FAT16 : /* WORD aligned items */
  11627. res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
  11628. 8004896: 68fb ldr r3, [r7, #12]
  11629. 8004898: 6a9a ldr r2, [r3, #40] ; 0x28
  11630. 800489a: 68fb ldr r3, [r7, #12]
  11631. 800489c: 899b ldrh r3, [r3, #12]
  11632. 800489e: 085b lsrs r3, r3, #1
  11633. 80048a0: b29b uxth r3, r3
  11634. 80048a2: 4619 mov r1, r3
  11635. 80048a4: 68bb ldr r3, [r7, #8]
  11636. 80048a6: fbb3 f3f1 udiv r3, r3, r1
  11637. 80048aa: 4413 add r3, r2
  11638. 80048ac: 4619 mov r1, r3
  11639. 80048ae: 68f8 ldr r0, [r7, #12]
  11640. 80048b0: f7ff fdc6 bl 8004440 <move_window>
  11641. 80048b4: 4603 mov r3, r0
  11642. 80048b6: 77fb strb r3, [r7, #31]
  11643. if (res != FR_OK) break;
  11644. 80048b8: 7ffb ldrb r3, [r7, #31]
  11645. 80048ba: 2b00 cmp r3, #0
  11646. 80048bc: d15b bne.n 8004976 <put_fat+0x21e>
  11647. st_word(fs->win + clst * 2 % SS(fs), (WORD)val);
  11648. 80048be: 68fb ldr r3, [r7, #12]
  11649. 80048c0: f103 0138 add.w r1, r3, #56 ; 0x38
  11650. 80048c4: 68bb ldr r3, [r7, #8]
  11651. 80048c6: 005b lsls r3, r3, #1
  11652. 80048c8: 68fa ldr r2, [r7, #12]
  11653. 80048ca: 8992 ldrh r2, [r2, #12]
  11654. 80048cc: fbb3 f0f2 udiv r0, r3, r2
  11655. 80048d0: fb02 f200 mul.w r2, r2, r0
  11656. 80048d4: 1a9b subs r3, r3, r2
  11657. 80048d6: 440b add r3, r1
  11658. 80048d8: 687a ldr r2, [r7, #4]
  11659. 80048da: b292 uxth r2, r2
  11660. 80048dc: 4611 mov r1, r2
  11661. 80048de: 4618 mov r0, r3
  11662. 80048e0: f7ff fb47 bl 8003f72 <st_word>
  11663. fs->wflag = 1;
  11664. 80048e4: 68fb ldr r3, [r7, #12]
  11665. 80048e6: 2201 movs r2, #1
  11666. 80048e8: 70da strb r2, [r3, #3]
  11667. break;
  11668. 80048ea: e047 b.n 800497c <put_fat+0x224>
  11669. case FS_FAT32 : /* DWORD aligned items */
  11670. #if _FS_EXFAT
  11671. case FS_EXFAT :
  11672. #endif
  11673. res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
  11674. 80048ec: 68fb ldr r3, [r7, #12]
  11675. 80048ee: 6a9a ldr r2, [r3, #40] ; 0x28
  11676. 80048f0: 68fb ldr r3, [r7, #12]
  11677. 80048f2: 899b ldrh r3, [r3, #12]
  11678. 80048f4: 089b lsrs r3, r3, #2
  11679. 80048f6: b29b uxth r3, r3
  11680. 80048f8: 4619 mov r1, r3
  11681. 80048fa: 68bb ldr r3, [r7, #8]
  11682. 80048fc: fbb3 f3f1 udiv r3, r3, r1
  11683. 8004900: 4413 add r3, r2
  11684. 8004902: 4619 mov r1, r3
  11685. 8004904: 68f8 ldr r0, [r7, #12]
  11686. 8004906: f7ff fd9b bl 8004440 <move_window>
  11687. 800490a: 4603 mov r3, r0
  11688. 800490c: 77fb strb r3, [r7, #31]
  11689. if (res != FR_OK) break;
  11690. 800490e: 7ffb ldrb r3, [r7, #31]
  11691. 8004910: 2b00 cmp r3, #0
  11692. 8004912: d132 bne.n 800497a <put_fat+0x222>
  11693. if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
  11694. val = (val & 0x0FFFFFFF) | (ld_dword(fs->win + clst * 4 % SS(fs)) & 0xF0000000);
  11695. 8004914: 687b ldr r3, [r7, #4]
  11696. 8004916: f023 4470 bic.w r4, r3, #4026531840 ; 0xf0000000
  11697. 800491a: 68fb ldr r3, [r7, #12]
  11698. 800491c: f103 0138 add.w r1, r3, #56 ; 0x38
  11699. 8004920: 68bb ldr r3, [r7, #8]
  11700. 8004922: 009b lsls r3, r3, #2
  11701. 8004924: 68fa ldr r2, [r7, #12]
  11702. 8004926: 8992 ldrh r2, [r2, #12]
  11703. 8004928: fbb3 f0f2 udiv r0, r3, r2
  11704. 800492c: fb02 f200 mul.w r2, r2, r0
  11705. 8004930: 1a9b subs r3, r3, r2
  11706. 8004932: 440b add r3, r1
  11707. 8004934: 4618 mov r0, r3
  11708. 8004936: f7ff fafa bl 8003f2e <ld_dword>
  11709. 800493a: 4603 mov r3, r0
  11710. 800493c: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000
  11711. 8004940: 4323 orrs r3, r4
  11712. 8004942: 607b str r3, [r7, #4]
  11713. }
  11714. st_dword(fs->win + clst * 4 % SS(fs), val);
  11715. 8004944: 68fb ldr r3, [r7, #12]
  11716. 8004946: f103 0138 add.w r1, r3, #56 ; 0x38
  11717. 800494a: 68bb ldr r3, [r7, #8]
  11718. 800494c: 009b lsls r3, r3, #2
  11719. 800494e: 68fa ldr r2, [r7, #12]
  11720. 8004950: 8992 ldrh r2, [r2, #12]
  11721. 8004952: fbb3 f0f2 udiv r0, r3, r2
  11722. 8004956: fb02 f200 mul.w r2, r2, r0
  11723. 800495a: 1a9b subs r3, r3, r2
  11724. 800495c: 440b add r3, r1
  11725. 800495e: 6879 ldr r1, [r7, #4]
  11726. 8004960: 4618 mov r0, r3
  11727. 8004962: f7ff fb20 bl 8003fa6 <st_dword>
  11728. fs->wflag = 1;
  11729. 8004966: 68fb ldr r3, [r7, #12]
  11730. 8004968: 2201 movs r2, #1
  11731. 800496a: 70da strb r2, [r3, #3]
  11732. break;
  11733. 800496c: e006 b.n 800497c <put_fat+0x224>
  11734. if (res != FR_OK) break;
  11735. 800496e: bf00 nop
  11736. 8004970: e004 b.n 800497c <put_fat+0x224>
  11737. if (res != FR_OK) break;
  11738. 8004972: bf00 nop
  11739. 8004974: e002 b.n 800497c <put_fat+0x224>
  11740. if (res != FR_OK) break;
  11741. 8004976: bf00 nop
  11742. 8004978: e000 b.n 800497c <put_fat+0x224>
  11743. if (res != FR_OK) break;
  11744. 800497a: bf00 nop
  11745. }
  11746. }
  11747. return res;
  11748. 800497c: 7ffb ldrb r3, [r7, #31]
  11749. }
  11750. 800497e: 4618 mov r0, r3
  11751. 8004980: 3724 adds r7, #36 ; 0x24
  11752. 8004982: 46bd mov sp, r7
  11753. 8004984: bd90 pop {r4, r7, pc}
  11754. 08004986 <remove_chain>:
  11755. FRESULT remove_chain ( /* FR_OK(0):succeeded, !=0:error */
  11756. _FDID* obj, /* Corresponding object */
  11757. DWORD clst, /* Cluster to remove a chain from */
  11758. DWORD pclst /* Previous cluster of clst (0:an entire chain) */
  11759. )
  11760. {
  11761. 8004986: b580 push {r7, lr}
  11762. 8004988: b088 sub sp, #32
  11763. 800498a: af00 add r7, sp, #0
  11764. 800498c: 60f8 str r0, [r7, #12]
  11765. 800498e: 60b9 str r1, [r7, #8]
  11766. 8004990: 607a str r2, [r7, #4]
  11767. FRESULT res = FR_OK;
  11768. 8004992: 2300 movs r3, #0
  11769. 8004994: 77fb strb r3, [r7, #31]
  11770. DWORD nxt;
  11771. FATFS *fs = obj->fs;
  11772. 8004996: 68fb ldr r3, [r7, #12]
  11773. 8004998: 681b ldr r3, [r3, #0]
  11774. 800499a: 61bb str r3, [r7, #24]
  11775. #endif
  11776. #if _USE_TRIM
  11777. DWORD rt[2];
  11778. #endif
  11779. if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Check if in valid range */
  11780. 800499c: 68bb ldr r3, [r7, #8]
  11781. 800499e: 2b01 cmp r3, #1
  11782. 80049a0: d904 bls.n 80049ac <remove_chain+0x26>
  11783. 80049a2: 69bb ldr r3, [r7, #24]
  11784. 80049a4: 69db ldr r3, [r3, #28]
  11785. 80049a6: 68ba ldr r2, [r7, #8]
  11786. 80049a8: 429a cmp r2, r3
  11787. 80049aa: d301 bcc.n 80049b0 <remove_chain+0x2a>
  11788. 80049ac: 2302 movs r3, #2
  11789. 80049ae: e04b b.n 8004a48 <remove_chain+0xc2>
  11790. /* Mark the previous cluster 'EOC' on the FAT if it exists */
  11791. if (pclst && (!_FS_EXFAT || fs->fs_type != FS_EXFAT || obj->stat != 2)) {
  11792. 80049b0: 687b ldr r3, [r7, #4]
  11793. 80049b2: 2b00 cmp r3, #0
  11794. 80049b4: d00c beq.n 80049d0 <remove_chain+0x4a>
  11795. res = put_fat(fs, pclst, 0xFFFFFFFF);
  11796. 80049b6: f04f 32ff mov.w r2, #4294967295
  11797. 80049ba: 6879 ldr r1, [r7, #4]
  11798. 80049bc: 69b8 ldr r0, [r7, #24]
  11799. 80049be: f7ff fecb bl 8004758 <put_fat>
  11800. 80049c2: 4603 mov r3, r0
  11801. 80049c4: 77fb strb r3, [r7, #31]
  11802. if (res != FR_OK) return res;
  11803. 80049c6: 7ffb ldrb r3, [r7, #31]
  11804. 80049c8: 2b00 cmp r3, #0
  11805. 80049ca: d001 beq.n 80049d0 <remove_chain+0x4a>
  11806. 80049cc: 7ffb ldrb r3, [r7, #31]
  11807. 80049ce: e03b b.n 8004a48 <remove_chain+0xc2>
  11808. }
  11809. /* Remove the chain */
  11810. do {
  11811. nxt = get_fat(obj, clst); /* Get cluster status */
  11812. 80049d0: 68b9 ldr r1, [r7, #8]
  11813. 80049d2: 68f8 ldr r0, [r7, #12]
  11814. 80049d4: f7ff fdf0 bl 80045b8 <get_fat>
  11815. 80049d8: 6178 str r0, [r7, #20]
  11816. if (nxt == 0) break; /* Empty cluster? */
  11817. 80049da: 697b ldr r3, [r7, #20]
  11818. 80049dc: 2b00 cmp r3, #0
  11819. 80049de: d031 beq.n 8004a44 <remove_chain+0xbe>
  11820. if (nxt == 1) return FR_INT_ERR; /* Internal error? */
  11821. 80049e0: 697b ldr r3, [r7, #20]
  11822. 80049e2: 2b01 cmp r3, #1
  11823. 80049e4: d101 bne.n 80049ea <remove_chain+0x64>
  11824. 80049e6: 2302 movs r3, #2
  11825. 80049e8: e02e b.n 8004a48 <remove_chain+0xc2>
  11826. if (nxt == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error? */
  11827. 80049ea: 697b ldr r3, [r7, #20]
  11828. 80049ec: f1b3 3fff cmp.w r3, #4294967295
  11829. 80049f0: d101 bne.n 80049f6 <remove_chain+0x70>
  11830. 80049f2: 2301 movs r3, #1
  11831. 80049f4: e028 b.n 8004a48 <remove_chain+0xc2>
  11832. if (!_FS_EXFAT || fs->fs_type != FS_EXFAT) {
  11833. res = put_fat(fs, clst, 0); /* Mark the cluster 'free' on the FAT */
  11834. 80049f6: 2200 movs r2, #0
  11835. 80049f8: 68b9 ldr r1, [r7, #8]
  11836. 80049fa: 69b8 ldr r0, [r7, #24]
  11837. 80049fc: f7ff feac bl 8004758 <put_fat>
  11838. 8004a00: 4603 mov r3, r0
  11839. 8004a02: 77fb strb r3, [r7, #31]
  11840. if (res != FR_OK) return res;
  11841. 8004a04: 7ffb ldrb r3, [r7, #31]
  11842. 8004a06: 2b00 cmp r3, #0
  11843. 8004a08: d001 beq.n 8004a0e <remove_chain+0x88>
  11844. 8004a0a: 7ffb ldrb r3, [r7, #31]
  11845. 8004a0c: e01c b.n 8004a48 <remove_chain+0xc2>
  11846. }
  11847. if (fs->free_clst < fs->n_fatent - 2) { /* Update FSINFO */
  11848. 8004a0e: 69bb ldr r3, [r7, #24]
  11849. 8004a10: 699a ldr r2, [r3, #24]
  11850. 8004a12: 69bb ldr r3, [r7, #24]
  11851. 8004a14: 69db ldr r3, [r3, #28]
  11852. 8004a16: 3b02 subs r3, #2
  11853. 8004a18: 429a cmp r2, r3
  11854. 8004a1a: d20b bcs.n 8004a34 <remove_chain+0xae>
  11855. fs->free_clst++;
  11856. 8004a1c: 69bb ldr r3, [r7, #24]
  11857. 8004a1e: 699b ldr r3, [r3, #24]
  11858. 8004a20: 1c5a adds r2, r3, #1
  11859. 8004a22: 69bb ldr r3, [r7, #24]
  11860. 8004a24: 619a str r2, [r3, #24]
  11861. fs->fsi_flag |= 1;
  11862. 8004a26: 69bb ldr r3, [r7, #24]
  11863. 8004a28: 791b ldrb r3, [r3, #4]
  11864. 8004a2a: f043 0301 orr.w r3, r3, #1
  11865. 8004a2e: b2da uxtb r2, r3
  11866. 8004a30: 69bb ldr r3, [r7, #24]
  11867. 8004a32: 711a strb r2, [r3, #4]
  11868. disk_ioctl(fs->drv, CTRL_TRIM, rt); /* Inform device the block can be erased */
  11869. #endif
  11870. scl = ecl = nxt;
  11871. }
  11872. #endif
  11873. clst = nxt; /* Next cluster */
  11874. 8004a34: 697b ldr r3, [r7, #20]
  11875. 8004a36: 60bb str r3, [r7, #8]
  11876. } while (clst < fs->n_fatent); /* Repeat while not the last link */
  11877. 8004a38: 69bb ldr r3, [r7, #24]
  11878. 8004a3a: 69db ldr r3, [r3, #28]
  11879. 8004a3c: 68ba ldr r2, [r7, #8]
  11880. 8004a3e: 429a cmp r2, r3
  11881. 8004a40: d3c6 bcc.n 80049d0 <remove_chain+0x4a>
  11882. 8004a42: e000 b.n 8004a46 <remove_chain+0xc0>
  11883. if (nxt == 0) break; /* Empty cluster? */
  11884. 8004a44: bf00 nop
  11885. obj->stat = 2; /* Change the object status 'contiguous' */
  11886. }
  11887. }
  11888. }
  11889. #endif
  11890. return FR_OK;
  11891. 8004a46: 2300 movs r3, #0
  11892. }
  11893. 8004a48: 4618 mov r0, r3
  11894. 8004a4a: 3720 adds r7, #32
  11895. 8004a4c: 46bd mov sp, r7
  11896. 8004a4e: bd80 pop {r7, pc}
  11897. 08004a50 <create_chain>:
  11898. static
  11899. DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
  11900. _FDID* obj, /* Corresponding object */
  11901. DWORD clst /* Cluster# to stretch, 0:Create a new chain */
  11902. )
  11903. {
  11904. 8004a50: b580 push {r7, lr}
  11905. 8004a52: b088 sub sp, #32
  11906. 8004a54: af00 add r7, sp, #0
  11907. 8004a56: 6078 str r0, [r7, #4]
  11908. 8004a58: 6039 str r1, [r7, #0]
  11909. DWORD cs, ncl, scl;
  11910. FRESULT res;
  11911. FATFS *fs = obj->fs;
  11912. 8004a5a: 687b ldr r3, [r7, #4]
  11913. 8004a5c: 681b ldr r3, [r3, #0]
  11914. 8004a5e: 613b str r3, [r7, #16]
  11915. if (clst == 0) { /* Create a new chain */
  11916. 8004a60: 683b ldr r3, [r7, #0]
  11917. 8004a62: 2b00 cmp r3, #0
  11918. 8004a64: d10d bne.n 8004a82 <create_chain+0x32>
  11919. scl = fs->last_clst; /* Get suggested cluster to start from */
  11920. 8004a66: 693b ldr r3, [r7, #16]
  11921. 8004a68: 695b ldr r3, [r3, #20]
  11922. 8004a6a: 61bb str r3, [r7, #24]
  11923. if (scl == 0 || scl >= fs->n_fatent) scl = 1;
  11924. 8004a6c: 69bb ldr r3, [r7, #24]
  11925. 8004a6e: 2b00 cmp r3, #0
  11926. 8004a70: d004 beq.n 8004a7c <create_chain+0x2c>
  11927. 8004a72: 693b ldr r3, [r7, #16]
  11928. 8004a74: 69db ldr r3, [r3, #28]
  11929. 8004a76: 69ba ldr r2, [r7, #24]
  11930. 8004a78: 429a cmp r2, r3
  11931. 8004a7a: d31b bcc.n 8004ab4 <create_chain+0x64>
  11932. 8004a7c: 2301 movs r3, #1
  11933. 8004a7e: 61bb str r3, [r7, #24]
  11934. 8004a80: e018 b.n 8004ab4 <create_chain+0x64>
  11935. }
  11936. else { /* Stretch current chain */
  11937. cs = get_fat(obj, clst); /* Check the cluster status */
  11938. 8004a82: 6839 ldr r1, [r7, #0]
  11939. 8004a84: 6878 ldr r0, [r7, #4]
  11940. 8004a86: f7ff fd97 bl 80045b8 <get_fat>
  11941. 8004a8a: 60f8 str r0, [r7, #12]
  11942. if (cs < 2) return 1; /* Invalid FAT value */
  11943. 8004a8c: 68fb ldr r3, [r7, #12]
  11944. 8004a8e: 2b01 cmp r3, #1
  11945. 8004a90: d801 bhi.n 8004a96 <create_chain+0x46>
  11946. 8004a92: 2301 movs r3, #1
  11947. 8004a94: e070 b.n 8004b78 <create_chain+0x128>
  11948. if (cs == 0xFFFFFFFF) return cs; /* A disk error occurred */
  11949. 8004a96: 68fb ldr r3, [r7, #12]
  11950. 8004a98: f1b3 3fff cmp.w r3, #4294967295
  11951. 8004a9c: d101 bne.n 8004aa2 <create_chain+0x52>
  11952. 8004a9e: 68fb ldr r3, [r7, #12]
  11953. 8004aa0: e06a b.n 8004b78 <create_chain+0x128>
  11954. if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
  11955. 8004aa2: 693b ldr r3, [r7, #16]
  11956. 8004aa4: 69db ldr r3, [r3, #28]
  11957. 8004aa6: 68fa ldr r2, [r7, #12]
  11958. 8004aa8: 429a cmp r2, r3
  11959. 8004aaa: d201 bcs.n 8004ab0 <create_chain+0x60>
  11960. 8004aac: 68fb ldr r3, [r7, #12]
  11961. 8004aae: e063 b.n 8004b78 <create_chain+0x128>
  11962. scl = clst;
  11963. 8004ab0: 683b ldr r3, [r7, #0]
  11964. 8004ab2: 61bb str r3, [r7, #24]
  11965. }
  11966. }
  11967. } else
  11968. #endif
  11969. { /* On the FAT12/16/32 volume */
  11970. ncl = scl; /* Start cluster */
  11971. 8004ab4: 69bb ldr r3, [r7, #24]
  11972. 8004ab6: 61fb str r3, [r7, #28]
  11973. for (;;) {
  11974. ncl++; /* Next cluster */
  11975. 8004ab8: 69fb ldr r3, [r7, #28]
  11976. 8004aba: 3301 adds r3, #1
  11977. 8004abc: 61fb str r3, [r7, #28]
  11978. if (ncl >= fs->n_fatent) { /* Check wrap-around */
  11979. 8004abe: 693b ldr r3, [r7, #16]
  11980. 8004ac0: 69db ldr r3, [r3, #28]
  11981. 8004ac2: 69fa ldr r2, [r7, #28]
  11982. 8004ac4: 429a cmp r2, r3
  11983. 8004ac6: d307 bcc.n 8004ad8 <create_chain+0x88>
  11984. ncl = 2;
  11985. 8004ac8: 2302 movs r3, #2
  11986. 8004aca: 61fb str r3, [r7, #28]
  11987. if (ncl > scl) return 0; /* No free cluster */
  11988. 8004acc: 69fa ldr r2, [r7, #28]
  11989. 8004ace: 69bb ldr r3, [r7, #24]
  11990. 8004ad0: 429a cmp r2, r3
  11991. 8004ad2: d901 bls.n 8004ad8 <create_chain+0x88>
  11992. 8004ad4: 2300 movs r3, #0
  11993. 8004ad6: e04f b.n 8004b78 <create_chain+0x128>
  11994. }
  11995. cs = get_fat(obj, ncl); /* Get the cluster status */
  11996. 8004ad8: 69f9 ldr r1, [r7, #28]
  11997. 8004ada: 6878 ldr r0, [r7, #4]
  11998. 8004adc: f7ff fd6c bl 80045b8 <get_fat>
  11999. 8004ae0: 60f8 str r0, [r7, #12]
  12000. if (cs == 0) break; /* Found a free cluster */
  12001. 8004ae2: 68fb ldr r3, [r7, #12]
  12002. 8004ae4: 2b00 cmp r3, #0
  12003. 8004ae6: d00e beq.n 8004b06 <create_chain+0xb6>
  12004. if (cs == 1 || cs == 0xFFFFFFFF) return cs; /* An error occurred */
  12005. 8004ae8: 68fb ldr r3, [r7, #12]
  12006. 8004aea: 2b01 cmp r3, #1
  12007. 8004aec: d003 beq.n 8004af6 <create_chain+0xa6>
  12008. 8004aee: 68fb ldr r3, [r7, #12]
  12009. 8004af0: f1b3 3fff cmp.w r3, #4294967295
  12010. 8004af4: d101 bne.n 8004afa <create_chain+0xaa>
  12011. 8004af6: 68fb ldr r3, [r7, #12]
  12012. 8004af8: e03e b.n 8004b78 <create_chain+0x128>
  12013. if (ncl == scl) return 0; /* No free cluster */
  12014. 8004afa: 69fa ldr r2, [r7, #28]
  12015. 8004afc: 69bb ldr r3, [r7, #24]
  12016. 8004afe: 429a cmp r2, r3
  12017. 8004b00: d1da bne.n 8004ab8 <create_chain+0x68>
  12018. 8004b02: 2300 movs r3, #0
  12019. 8004b04: e038 b.n 8004b78 <create_chain+0x128>
  12020. if (cs == 0) break; /* Found a free cluster */
  12021. 8004b06: bf00 nop
  12022. }
  12023. res = put_fat(fs, ncl, 0xFFFFFFFF); /* Mark the new cluster 'EOC' */
  12024. 8004b08: f04f 32ff mov.w r2, #4294967295
  12025. 8004b0c: 69f9 ldr r1, [r7, #28]
  12026. 8004b0e: 6938 ldr r0, [r7, #16]
  12027. 8004b10: f7ff fe22 bl 8004758 <put_fat>
  12028. 8004b14: 4603 mov r3, r0
  12029. 8004b16: 75fb strb r3, [r7, #23]
  12030. if (res == FR_OK && clst != 0) {
  12031. 8004b18: 7dfb ldrb r3, [r7, #23]
  12032. 8004b1a: 2b00 cmp r3, #0
  12033. 8004b1c: d109 bne.n 8004b32 <create_chain+0xe2>
  12034. 8004b1e: 683b ldr r3, [r7, #0]
  12035. 8004b20: 2b00 cmp r3, #0
  12036. 8004b22: d006 beq.n 8004b32 <create_chain+0xe2>
  12037. res = put_fat(fs, clst, ncl); /* Link it from the previous one if needed */
  12038. 8004b24: 69fa ldr r2, [r7, #28]
  12039. 8004b26: 6839 ldr r1, [r7, #0]
  12040. 8004b28: 6938 ldr r0, [r7, #16]
  12041. 8004b2a: f7ff fe15 bl 8004758 <put_fat>
  12042. 8004b2e: 4603 mov r3, r0
  12043. 8004b30: 75fb strb r3, [r7, #23]
  12044. }
  12045. }
  12046. if (res == FR_OK) { /* Update FSINFO if function succeeded. */
  12047. 8004b32: 7dfb ldrb r3, [r7, #23]
  12048. 8004b34: 2b00 cmp r3, #0
  12049. 8004b36: d116 bne.n 8004b66 <create_chain+0x116>
  12050. fs->last_clst = ncl;
  12051. 8004b38: 693b ldr r3, [r7, #16]
  12052. 8004b3a: 69fa ldr r2, [r7, #28]
  12053. 8004b3c: 615a str r2, [r3, #20]
  12054. if (fs->free_clst <= fs->n_fatent - 2) fs->free_clst--;
  12055. 8004b3e: 693b ldr r3, [r7, #16]
  12056. 8004b40: 699a ldr r2, [r3, #24]
  12057. 8004b42: 693b ldr r3, [r7, #16]
  12058. 8004b44: 69db ldr r3, [r3, #28]
  12059. 8004b46: 3b02 subs r3, #2
  12060. 8004b48: 429a cmp r2, r3
  12061. 8004b4a: d804 bhi.n 8004b56 <create_chain+0x106>
  12062. 8004b4c: 693b ldr r3, [r7, #16]
  12063. 8004b4e: 699b ldr r3, [r3, #24]
  12064. 8004b50: 1e5a subs r2, r3, #1
  12065. 8004b52: 693b ldr r3, [r7, #16]
  12066. 8004b54: 619a str r2, [r3, #24]
  12067. fs->fsi_flag |= 1;
  12068. 8004b56: 693b ldr r3, [r7, #16]
  12069. 8004b58: 791b ldrb r3, [r3, #4]
  12070. 8004b5a: f043 0301 orr.w r3, r3, #1
  12071. 8004b5e: b2da uxtb r2, r3
  12072. 8004b60: 693b ldr r3, [r7, #16]
  12073. 8004b62: 711a strb r2, [r3, #4]
  12074. 8004b64: e007 b.n 8004b76 <create_chain+0x126>
  12075. } else {
  12076. ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; /* Failed. Generate error status */
  12077. 8004b66: 7dfb ldrb r3, [r7, #23]
  12078. 8004b68: 2b01 cmp r3, #1
  12079. 8004b6a: d102 bne.n 8004b72 <create_chain+0x122>
  12080. 8004b6c: f04f 33ff mov.w r3, #4294967295
  12081. 8004b70: e000 b.n 8004b74 <create_chain+0x124>
  12082. 8004b72: 2301 movs r3, #1
  12083. 8004b74: 61fb str r3, [r7, #28]
  12084. }
  12085. return ncl; /* Return new cluster number or error status */
  12086. 8004b76: 69fb ldr r3, [r7, #28]
  12087. }
  12088. 8004b78: 4618 mov r0, r3
  12089. 8004b7a: 3720 adds r7, #32
  12090. 8004b7c: 46bd mov sp, r7
  12091. 8004b7e: bd80 pop {r7, pc}
  12092. 08004b80 <clmt_clust>:
  12093. static
  12094. DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */
  12095. FIL* fp, /* Pointer to the file object */
  12096. FSIZE_t ofs /* File offset to be converted to cluster# */
  12097. )
  12098. {
  12099. 8004b80: b480 push {r7}
  12100. 8004b82: b087 sub sp, #28
  12101. 8004b84: af00 add r7, sp, #0
  12102. 8004b86: 6078 str r0, [r7, #4]
  12103. 8004b88: 6039 str r1, [r7, #0]
  12104. DWORD cl, ncl, *tbl;
  12105. FATFS *fs = fp->obj.fs;
  12106. 8004b8a: 687b ldr r3, [r7, #4]
  12107. 8004b8c: 681b ldr r3, [r3, #0]
  12108. 8004b8e: 60fb str r3, [r7, #12]
  12109. tbl = fp->cltbl + 1; /* Top of CLMT */
  12110. 8004b90: 687b ldr r3, [r7, #4]
  12111. 8004b92: 6adb ldr r3, [r3, #44] ; 0x2c
  12112. 8004b94: 3304 adds r3, #4
  12113. 8004b96: 613b str r3, [r7, #16]
  12114. cl = (DWORD)(ofs / SS(fs) / fs->csize); /* Cluster order from top of the file */
  12115. 8004b98: 68fb ldr r3, [r7, #12]
  12116. 8004b9a: 899b ldrh r3, [r3, #12]
  12117. 8004b9c: 461a mov r2, r3
  12118. 8004b9e: 683b ldr r3, [r7, #0]
  12119. 8004ba0: fbb3 f3f2 udiv r3, r3, r2
  12120. 8004ba4: 68fa ldr r2, [r7, #12]
  12121. 8004ba6: 8952 ldrh r2, [r2, #10]
  12122. 8004ba8: fbb3 f3f2 udiv r3, r3, r2
  12123. 8004bac: 617b str r3, [r7, #20]
  12124. for (;;) {
  12125. ncl = *tbl++; /* Number of cluters in the fragment */
  12126. 8004bae: 693b ldr r3, [r7, #16]
  12127. 8004bb0: 1d1a adds r2, r3, #4
  12128. 8004bb2: 613a str r2, [r7, #16]
  12129. 8004bb4: 681b ldr r3, [r3, #0]
  12130. 8004bb6: 60bb str r3, [r7, #8]
  12131. if (ncl == 0) return 0; /* End of table? (error) */
  12132. 8004bb8: 68bb ldr r3, [r7, #8]
  12133. 8004bba: 2b00 cmp r3, #0
  12134. 8004bbc: d101 bne.n 8004bc2 <clmt_clust+0x42>
  12135. 8004bbe: 2300 movs r3, #0
  12136. 8004bc0: e010 b.n 8004be4 <clmt_clust+0x64>
  12137. if (cl < ncl) break; /* In this fragment? */
  12138. 8004bc2: 697a ldr r2, [r7, #20]
  12139. 8004bc4: 68bb ldr r3, [r7, #8]
  12140. 8004bc6: 429a cmp r2, r3
  12141. 8004bc8: d307 bcc.n 8004bda <clmt_clust+0x5a>
  12142. cl -= ncl; tbl++; /* Next fragment */
  12143. 8004bca: 697a ldr r2, [r7, #20]
  12144. 8004bcc: 68bb ldr r3, [r7, #8]
  12145. 8004bce: 1ad3 subs r3, r2, r3
  12146. 8004bd0: 617b str r3, [r7, #20]
  12147. 8004bd2: 693b ldr r3, [r7, #16]
  12148. 8004bd4: 3304 adds r3, #4
  12149. 8004bd6: 613b str r3, [r7, #16]
  12150. ncl = *tbl++; /* Number of cluters in the fragment */
  12151. 8004bd8: e7e9 b.n 8004bae <clmt_clust+0x2e>
  12152. if (cl < ncl) break; /* In this fragment? */
  12153. 8004bda: bf00 nop
  12154. }
  12155. return cl + *tbl; /* Return the cluster number */
  12156. 8004bdc: 693b ldr r3, [r7, #16]
  12157. 8004bde: 681a ldr r2, [r3, #0]
  12158. 8004be0: 697b ldr r3, [r7, #20]
  12159. 8004be2: 4413 add r3, r2
  12160. }
  12161. 8004be4: 4618 mov r0, r3
  12162. 8004be6: 371c adds r7, #28
  12163. 8004be8: 46bd mov sp, r7
  12164. 8004bea: bc80 pop {r7}
  12165. 8004bec: 4770 bx lr
  12166. 08004bee <dir_sdi>:
  12167. static
  12168. FRESULT dir_sdi ( /* FR_OK(0):succeeded, !=0:error */
  12169. DIR* dp, /* Pointer to directory object */
  12170. DWORD ofs /* Offset of directory table */
  12171. )
  12172. {
  12173. 8004bee: b580 push {r7, lr}
  12174. 8004bf0: b086 sub sp, #24
  12175. 8004bf2: af00 add r7, sp, #0
  12176. 8004bf4: 6078 str r0, [r7, #4]
  12177. 8004bf6: 6039 str r1, [r7, #0]
  12178. DWORD csz, clst;
  12179. FATFS *fs = dp->obj.fs;
  12180. 8004bf8: 687b ldr r3, [r7, #4]
  12181. 8004bfa: 681b ldr r3, [r3, #0]
  12182. 8004bfc: 613b str r3, [r7, #16]
  12183. if (ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR) || ofs % SZDIRE) { /* Check range of offset and alignment */
  12184. 8004bfe: 683b ldr r3, [r7, #0]
  12185. 8004c00: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  12186. 8004c04: d204 bcs.n 8004c10 <dir_sdi+0x22>
  12187. 8004c06: 683b ldr r3, [r7, #0]
  12188. 8004c08: f003 031f and.w r3, r3, #31
  12189. 8004c0c: 2b00 cmp r3, #0
  12190. 8004c0e: d001 beq.n 8004c14 <dir_sdi+0x26>
  12191. return FR_INT_ERR;
  12192. 8004c10: 2302 movs r3, #2
  12193. 8004c12: e071 b.n 8004cf8 <dir_sdi+0x10a>
  12194. }
  12195. dp->dptr = ofs; /* Set current offset */
  12196. 8004c14: 687b ldr r3, [r7, #4]
  12197. 8004c16: 683a ldr r2, [r7, #0]
  12198. 8004c18: 615a str r2, [r3, #20]
  12199. clst = dp->obj.sclust; /* Table start cluster (0:root) */
  12200. 8004c1a: 687b ldr r3, [r7, #4]
  12201. 8004c1c: 689b ldr r3, [r3, #8]
  12202. 8004c1e: 617b str r3, [r7, #20]
  12203. if (clst == 0 && fs->fs_type >= FS_FAT32) { /* Replace cluster# 0 with root cluster# */
  12204. 8004c20: 697b ldr r3, [r7, #20]
  12205. 8004c22: 2b00 cmp r3, #0
  12206. 8004c24: d106 bne.n 8004c34 <dir_sdi+0x46>
  12207. 8004c26: 693b ldr r3, [r7, #16]
  12208. 8004c28: 781b ldrb r3, [r3, #0]
  12209. 8004c2a: 2b02 cmp r3, #2
  12210. 8004c2c: d902 bls.n 8004c34 <dir_sdi+0x46>
  12211. clst = fs->dirbase;
  12212. 8004c2e: 693b ldr r3, [r7, #16]
  12213. 8004c30: 6adb ldr r3, [r3, #44] ; 0x2c
  12214. 8004c32: 617b str r3, [r7, #20]
  12215. if (_FS_EXFAT) dp->obj.stat = 0; /* exFAT: Root dir has an FAT chain */
  12216. }
  12217. if (clst == 0) { /* Static table (root-directory in FAT12/16) */
  12218. 8004c34: 697b ldr r3, [r7, #20]
  12219. 8004c36: 2b00 cmp r3, #0
  12220. 8004c38: d10c bne.n 8004c54 <dir_sdi+0x66>
  12221. if (ofs / SZDIRE >= fs->n_rootdir) return FR_INT_ERR; /* Is index out of range? */
  12222. 8004c3a: 683b ldr r3, [r7, #0]
  12223. 8004c3c: 095b lsrs r3, r3, #5
  12224. 8004c3e: 693a ldr r2, [r7, #16]
  12225. 8004c40: 8912 ldrh r2, [r2, #8]
  12226. 8004c42: 4293 cmp r3, r2
  12227. 8004c44: d301 bcc.n 8004c4a <dir_sdi+0x5c>
  12228. 8004c46: 2302 movs r3, #2
  12229. 8004c48: e056 b.n 8004cf8 <dir_sdi+0x10a>
  12230. dp->sect = fs->dirbase;
  12231. 8004c4a: 693b ldr r3, [r7, #16]
  12232. 8004c4c: 6ada ldr r2, [r3, #44] ; 0x2c
  12233. 8004c4e: 687b ldr r3, [r7, #4]
  12234. 8004c50: 61da str r2, [r3, #28]
  12235. 8004c52: e02d b.n 8004cb0 <dir_sdi+0xc2>
  12236. } else { /* Dynamic table (sub-directory or root-directory in FAT32+) */
  12237. csz = (DWORD)fs->csize * SS(fs); /* Bytes per cluster */
  12238. 8004c54: 693b ldr r3, [r7, #16]
  12239. 8004c56: 895b ldrh r3, [r3, #10]
  12240. 8004c58: 461a mov r2, r3
  12241. 8004c5a: 693b ldr r3, [r7, #16]
  12242. 8004c5c: 899b ldrh r3, [r3, #12]
  12243. 8004c5e: fb03 f302 mul.w r3, r3, r2
  12244. 8004c62: 60fb str r3, [r7, #12]
  12245. while (ofs >= csz) { /* Follow cluster chain */
  12246. 8004c64: e019 b.n 8004c9a <dir_sdi+0xac>
  12247. clst = get_fat(&dp->obj, clst); /* Get next cluster */
  12248. 8004c66: 687b ldr r3, [r7, #4]
  12249. 8004c68: 6979 ldr r1, [r7, #20]
  12250. 8004c6a: 4618 mov r0, r3
  12251. 8004c6c: f7ff fca4 bl 80045b8 <get_fat>
  12252. 8004c70: 6178 str r0, [r7, #20]
  12253. if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
  12254. 8004c72: 697b ldr r3, [r7, #20]
  12255. 8004c74: f1b3 3fff cmp.w r3, #4294967295
  12256. 8004c78: d101 bne.n 8004c7e <dir_sdi+0x90>
  12257. 8004c7a: 2301 movs r3, #1
  12258. 8004c7c: e03c b.n 8004cf8 <dir_sdi+0x10a>
  12259. if (clst < 2 || clst >= fs->n_fatent) return FR_INT_ERR; /* Reached to end of table or internal error */
  12260. 8004c7e: 697b ldr r3, [r7, #20]
  12261. 8004c80: 2b01 cmp r3, #1
  12262. 8004c82: d904 bls.n 8004c8e <dir_sdi+0xa0>
  12263. 8004c84: 693b ldr r3, [r7, #16]
  12264. 8004c86: 69db ldr r3, [r3, #28]
  12265. 8004c88: 697a ldr r2, [r7, #20]
  12266. 8004c8a: 429a cmp r2, r3
  12267. 8004c8c: d301 bcc.n 8004c92 <dir_sdi+0xa4>
  12268. 8004c8e: 2302 movs r3, #2
  12269. 8004c90: e032 b.n 8004cf8 <dir_sdi+0x10a>
  12270. ofs -= csz;
  12271. 8004c92: 683a ldr r2, [r7, #0]
  12272. 8004c94: 68fb ldr r3, [r7, #12]
  12273. 8004c96: 1ad3 subs r3, r2, r3
  12274. 8004c98: 603b str r3, [r7, #0]
  12275. while (ofs >= csz) { /* Follow cluster chain */
  12276. 8004c9a: 683a ldr r2, [r7, #0]
  12277. 8004c9c: 68fb ldr r3, [r7, #12]
  12278. 8004c9e: 429a cmp r2, r3
  12279. 8004ca0: d2e1 bcs.n 8004c66 <dir_sdi+0x78>
  12280. }
  12281. dp->sect = clust2sect(fs, clst);
  12282. 8004ca2: 6979 ldr r1, [r7, #20]
  12283. 8004ca4: 6938 ldr r0, [r7, #16]
  12284. 8004ca6: f7ff fc69 bl 800457c <clust2sect>
  12285. 8004caa: 4602 mov r2, r0
  12286. 8004cac: 687b ldr r3, [r7, #4]
  12287. 8004cae: 61da str r2, [r3, #28]
  12288. }
  12289. dp->clust = clst; /* Current cluster# */
  12290. 8004cb0: 687b ldr r3, [r7, #4]
  12291. 8004cb2: 697a ldr r2, [r7, #20]
  12292. 8004cb4: 619a str r2, [r3, #24]
  12293. if (!dp->sect) return FR_INT_ERR;
  12294. 8004cb6: 687b ldr r3, [r7, #4]
  12295. 8004cb8: 69db ldr r3, [r3, #28]
  12296. 8004cba: 2b00 cmp r3, #0
  12297. 8004cbc: d101 bne.n 8004cc2 <dir_sdi+0xd4>
  12298. 8004cbe: 2302 movs r3, #2
  12299. 8004cc0: e01a b.n 8004cf8 <dir_sdi+0x10a>
  12300. dp->sect += ofs / SS(fs); /* Sector# of the directory entry */
  12301. 8004cc2: 687b ldr r3, [r7, #4]
  12302. 8004cc4: 69da ldr r2, [r3, #28]
  12303. 8004cc6: 693b ldr r3, [r7, #16]
  12304. 8004cc8: 899b ldrh r3, [r3, #12]
  12305. 8004cca: 4619 mov r1, r3
  12306. 8004ccc: 683b ldr r3, [r7, #0]
  12307. 8004cce: fbb3 f3f1 udiv r3, r3, r1
  12308. 8004cd2: 441a add r2, r3
  12309. 8004cd4: 687b ldr r3, [r7, #4]
  12310. 8004cd6: 61da str r2, [r3, #28]
  12311. dp->dir = fs->win + (ofs % SS(fs)); /* Pointer to the entry in the win[] */
  12312. 8004cd8: 693b ldr r3, [r7, #16]
  12313. 8004cda: f103 0138 add.w r1, r3, #56 ; 0x38
  12314. 8004cde: 693b ldr r3, [r7, #16]
  12315. 8004ce0: 899b ldrh r3, [r3, #12]
  12316. 8004ce2: 461a mov r2, r3
  12317. 8004ce4: 683b ldr r3, [r7, #0]
  12318. 8004ce6: fbb3 f0f2 udiv r0, r3, r2
  12319. 8004cea: fb02 f200 mul.w r2, r2, r0
  12320. 8004cee: 1a9b subs r3, r3, r2
  12321. 8004cf0: 18ca adds r2, r1, r3
  12322. 8004cf2: 687b ldr r3, [r7, #4]
  12323. 8004cf4: 621a str r2, [r3, #32]
  12324. return FR_OK;
  12325. 8004cf6: 2300 movs r3, #0
  12326. }
  12327. 8004cf8: 4618 mov r0, r3
  12328. 8004cfa: 3718 adds r7, #24
  12329. 8004cfc: 46bd mov sp, r7
  12330. 8004cfe: bd80 pop {r7, pc}
  12331. 08004d00 <dir_next>:
  12332. static
  12333. FRESULT dir_next ( /* FR_OK(0):succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */
  12334. DIR* dp, /* Pointer to the directory object */
  12335. int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
  12336. )
  12337. {
  12338. 8004d00: b580 push {r7, lr}
  12339. 8004d02: b086 sub sp, #24
  12340. 8004d04: af00 add r7, sp, #0
  12341. 8004d06: 6078 str r0, [r7, #4]
  12342. 8004d08: 6039 str r1, [r7, #0]
  12343. DWORD ofs, clst;
  12344. FATFS *fs = dp->obj.fs;
  12345. 8004d0a: 687b ldr r3, [r7, #4]
  12346. 8004d0c: 681b ldr r3, [r3, #0]
  12347. 8004d0e: 60fb str r3, [r7, #12]
  12348. #if !_FS_READONLY
  12349. UINT n;
  12350. #endif
  12351. ofs = dp->dptr + SZDIRE; /* Next entry */
  12352. 8004d10: 687b ldr r3, [r7, #4]
  12353. 8004d12: 695b ldr r3, [r3, #20]
  12354. 8004d14: 3320 adds r3, #32
  12355. 8004d16: 60bb str r3, [r7, #8]
  12356. if (!dp->sect || ofs >= (DWORD)((_FS_EXFAT && fs->fs_type == FS_EXFAT) ? MAX_DIR_EX : MAX_DIR)) return FR_NO_FILE; /* Report EOT when offset has reached max value */
  12357. 8004d18: 687b ldr r3, [r7, #4]
  12358. 8004d1a: 69db ldr r3, [r3, #28]
  12359. 8004d1c: 2b00 cmp r3, #0
  12360. 8004d1e: d003 beq.n 8004d28 <dir_next+0x28>
  12361. 8004d20: 68bb ldr r3, [r7, #8]
  12362. 8004d22: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000
  12363. 8004d26: d301 bcc.n 8004d2c <dir_next+0x2c>
  12364. 8004d28: 2304 movs r3, #4
  12365. 8004d2a: e0bb b.n 8004ea4 <dir_next+0x1a4>
  12366. if (ofs % SS(fs) == 0) { /* Sector changed? */
  12367. 8004d2c: 68fb ldr r3, [r7, #12]
  12368. 8004d2e: 899b ldrh r3, [r3, #12]
  12369. 8004d30: 461a mov r2, r3
  12370. 8004d32: 68bb ldr r3, [r7, #8]
  12371. 8004d34: fbb3 f1f2 udiv r1, r3, r2
  12372. 8004d38: fb02 f201 mul.w r2, r2, r1
  12373. 8004d3c: 1a9b subs r3, r3, r2
  12374. 8004d3e: 2b00 cmp r3, #0
  12375. 8004d40: f040 809d bne.w 8004e7e <dir_next+0x17e>
  12376. dp->sect++; /* Next sector */
  12377. 8004d44: 687b ldr r3, [r7, #4]
  12378. 8004d46: 69db ldr r3, [r3, #28]
  12379. 8004d48: 1c5a adds r2, r3, #1
  12380. 8004d4a: 687b ldr r3, [r7, #4]
  12381. 8004d4c: 61da str r2, [r3, #28]
  12382. if (!dp->clust) { /* Static table */
  12383. 8004d4e: 687b ldr r3, [r7, #4]
  12384. 8004d50: 699b ldr r3, [r3, #24]
  12385. 8004d52: 2b00 cmp r3, #0
  12386. 8004d54: d10b bne.n 8004d6e <dir_next+0x6e>
  12387. if (ofs / SZDIRE >= fs->n_rootdir) { /* Report EOT if it reached end of static table */
  12388. 8004d56: 68bb ldr r3, [r7, #8]
  12389. 8004d58: 095b lsrs r3, r3, #5
  12390. 8004d5a: 68fa ldr r2, [r7, #12]
  12391. 8004d5c: 8912 ldrh r2, [r2, #8]
  12392. 8004d5e: 4293 cmp r3, r2
  12393. 8004d60: f0c0 808d bcc.w 8004e7e <dir_next+0x17e>
  12394. dp->sect = 0; return FR_NO_FILE;
  12395. 8004d64: 687b ldr r3, [r7, #4]
  12396. 8004d66: 2200 movs r2, #0
  12397. 8004d68: 61da str r2, [r3, #28]
  12398. 8004d6a: 2304 movs r3, #4
  12399. 8004d6c: e09a b.n 8004ea4 <dir_next+0x1a4>
  12400. }
  12401. }
  12402. else { /* Dynamic table */
  12403. if ((ofs / SS(fs) & (fs->csize - 1)) == 0) { /* Cluster changed? */
  12404. 8004d6e: 68fb ldr r3, [r7, #12]
  12405. 8004d70: 899b ldrh r3, [r3, #12]
  12406. 8004d72: 461a mov r2, r3
  12407. 8004d74: 68bb ldr r3, [r7, #8]
  12408. 8004d76: fbb3 f3f2 udiv r3, r3, r2
  12409. 8004d7a: 68fa ldr r2, [r7, #12]
  12410. 8004d7c: 8952 ldrh r2, [r2, #10]
  12411. 8004d7e: 3a01 subs r2, #1
  12412. 8004d80: 4013 ands r3, r2
  12413. 8004d82: 2b00 cmp r3, #0
  12414. 8004d84: d17b bne.n 8004e7e <dir_next+0x17e>
  12415. clst = get_fat(&dp->obj, dp->clust); /* Get next cluster */
  12416. 8004d86: 687a ldr r2, [r7, #4]
  12417. 8004d88: 687b ldr r3, [r7, #4]
  12418. 8004d8a: 699b ldr r3, [r3, #24]
  12419. 8004d8c: 4619 mov r1, r3
  12420. 8004d8e: 4610 mov r0, r2
  12421. 8004d90: f7ff fc12 bl 80045b8 <get_fat>
  12422. 8004d94: 6178 str r0, [r7, #20]
  12423. if (clst <= 1) return FR_INT_ERR; /* Internal error */
  12424. 8004d96: 697b ldr r3, [r7, #20]
  12425. 8004d98: 2b01 cmp r3, #1
  12426. 8004d9a: d801 bhi.n 8004da0 <dir_next+0xa0>
  12427. 8004d9c: 2302 movs r3, #2
  12428. 8004d9e: e081 b.n 8004ea4 <dir_next+0x1a4>
  12429. if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
  12430. 8004da0: 697b ldr r3, [r7, #20]
  12431. 8004da2: f1b3 3fff cmp.w r3, #4294967295
  12432. 8004da6: d101 bne.n 8004dac <dir_next+0xac>
  12433. 8004da8: 2301 movs r3, #1
  12434. 8004daa: e07b b.n 8004ea4 <dir_next+0x1a4>
  12435. if (clst >= fs->n_fatent) { /* Reached end of dynamic table */
  12436. 8004dac: 68fb ldr r3, [r7, #12]
  12437. 8004dae: 69db ldr r3, [r3, #28]
  12438. 8004db0: 697a ldr r2, [r7, #20]
  12439. 8004db2: 429a cmp r2, r3
  12440. 8004db4: d359 bcc.n 8004e6a <dir_next+0x16a>
  12441. #if !_FS_READONLY
  12442. if (!stretch) { /* If no stretch, report EOT */
  12443. 8004db6: 683b ldr r3, [r7, #0]
  12444. 8004db8: 2b00 cmp r3, #0
  12445. 8004dba: d104 bne.n 8004dc6 <dir_next+0xc6>
  12446. dp->sect = 0; return FR_NO_FILE;
  12447. 8004dbc: 687b ldr r3, [r7, #4]
  12448. 8004dbe: 2200 movs r2, #0
  12449. 8004dc0: 61da str r2, [r3, #28]
  12450. 8004dc2: 2304 movs r3, #4
  12451. 8004dc4: e06e b.n 8004ea4 <dir_next+0x1a4>
  12452. }
  12453. clst = create_chain(&dp->obj, dp->clust); /* Allocate a cluster */
  12454. 8004dc6: 687a ldr r2, [r7, #4]
  12455. 8004dc8: 687b ldr r3, [r7, #4]
  12456. 8004dca: 699b ldr r3, [r3, #24]
  12457. 8004dcc: 4619 mov r1, r3
  12458. 8004dce: 4610 mov r0, r2
  12459. 8004dd0: f7ff fe3e bl 8004a50 <create_chain>
  12460. 8004dd4: 6178 str r0, [r7, #20]
  12461. if (clst == 0) return FR_DENIED; /* No free cluster */
  12462. 8004dd6: 697b ldr r3, [r7, #20]
  12463. 8004dd8: 2b00 cmp r3, #0
  12464. 8004dda: d101 bne.n 8004de0 <dir_next+0xe0>
  12465. 8004ddc: 2307 movs r3, #7
  12466. 8004dde: e061 b.n 8004ea4 <dir_next+0x1a4>
  12467. if (clst == 1) return FR_INT_ERR; /* Internal error */
  12468. 8004de0: 697b ldr r3, [r7, #20]
  12469. 8004de2: 2b01 cmp r3, #1
  12470. 8004de4: d101 bne.n 8004dea <dir_next+0xea>
  12471. 8004de6: 2302 movs r3, #2
  12472. 8004de8: e05c b.n 8004ea4 <dir_next+0x1a4>
  12473. if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
  12474. 8004dea: 697b ldr r3, [r7, #20]
  12475. 8004dec: f1b3 3fff cmp.w r3, #4294967295
  12476. 8004df0: d101 bne.n 8004df6 <dir_next+0xf6>
  12477. 8004df2: 2301 movs r3, #1
  12478. 8004df4: e056 b.n 8004ea4 <dir_next+0x1a4>
  12479. /* Clean-up the stretched table */
  12480. if (_FS_EXFAT) dp->obj.stat |= 4; /* The directory needs to be updated */
  12481. if (sync_window(fs) != FR_OK) return FR_DISK_ERR; /* Flush disk access window */
  12482. 8004df6: 68f8 ldr r0, [r7, #12]
  12483. 8004df8: f7ff fade bl 80043b8 <sync_window>
  12484. 8004dfc: 4603 mov r3, r0
  12485. 8004dfe: 2b00 cmp r3, #0
  12486. 8004e00: d001 beq.n 8004e06 <dir_next+0x106>
  12487. 8004e02: 2301 movs r3, #1
  12488. 8004e04: e04e b.n 8004ea4 <dir_next+0x1a4>
  12489. mem_set(fs->win, 0, SS(fs)); /* Clear window buffer */
  12490. 8004e06: 68fb ldr r3, [r7, #12]
  12491. 8004e08: f103 0038 add.w r0, r3, #56 ; 0x38
  12492. 8004e0c: 68fb ldr r3, [r7, #12]
  12493. 8004e0e: 899b ldrh r3, [r3, #12]
  12494. 8004e10: 461a mov r2, r3
  12495. 8004e12: 2100 movs r1, #0
  12496. 8004e14: f7ff f912 bl 800403c <mem_set>
  12497. for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) { /* Fill the new cluster with 0 */
  12498. 8004e18: 2300 movs r3, #0
  12499. 8004e1a: 613b str r3, [r7, #16]
  12500. 8004e1c: 6979 ldr r1, [r7, #20]
  12501. 8004e1e: 68f8 ldr r0, [r7, #12]
  12502. 8004e20: f7ff fbac bl 800457c <clust2sect>
  12503. 8004e24: 4602 mov r2, r0
  12504. 8004e26: 68fb ldr r3, [r7, #12]
  12505. 8004e28: 635a str r2, [r3, #52] ; 0x34
  12506. 8004e2a: e012 b.n 8004e52 <dir_next+0x152>
  12507. fs->wflag = 1;
  12508. 8004e2c: 68fb ldr r3, [r7, #12]
  12509. 8004e2e: 2201 movs r2, #1
  12510. 8004e30: 70da strb r2, [r3, #3]
  12511. if (sync_window(fs) != FR_OK) return FR_DISK_ERR;
  12512. 8004e32: 68f8 ldr r0, [r7, #12]
  12513. 8004e34: f7ff fac0 bl 80043b8 <sync_window>
  12514. 8004e38: 4603 mov r3, r0
  12515. 8004e3a: 2b00 cmp r3, #0
  12516. 8004e3c: d001 beq.n 8004e42 <dir_next+0x142>
  12517. 8004e3e: 2301 movs r3, #1
  12518. 8004e40: e030 b.n 8004ea4 <dir_next+0x1a4>
  12519. for (n = 0, fs->winsect = clust2sect(fs, clst); n < fs->csize; n++, fs->winsect++) { /* Fill the new cluster with 0 */
  12520. 8004e42: 693b ldr r3, [r7, #16]
  12521. 8004e44: 3301 adds r3, #1
  12522. 8004e46: 613b str r3, [r7, #16]
  12523. 8004e48: 68fb ldr r3, [r7, #12]
  12524. 8004e4a: 6b5b ldr r3, [r3, #52] ; 0x34
  12525. 8004e4c: 1c5a adds r2, r3, #1
  12526. 8004e4e: 68fb ldr r3, [r7, #12]
  12527. 8004e50: 635a str r2, [r3, #52] ; 0x34
  12528. 8004e52: 68fb ldr r3, [r7, #12]
  12529. 8004e54: 895b ldrh r3, [r3, #10]
  12530. 8004e56: 461a mov r2, r3
  12531. 8004e58: 693b ldr r3, [r7, #16]
  12532. 8004e5a: 4293 cmp r3, r2
  12533. 8004e5c: d3e6 bcc.n 8004e2c <dir_next+0x12c>
  12534. }
  12535. fs->winsect -= n; /* Restore window offset */
  12536. 8004e5e: 68fb ldr r3, [r7, #12]
  12537. 8004e60: 6b5a ldr r2, [r3, #52] ; 0x34
  12538. 8004e62: 693b ldr r3, [r7, #16]
  12539. 8004e64: 1ad2 subs r2, r2, r3
  12540. 8004e66: 68fb ldr r3, [r7, #12]
  12541. 8004e68: 635a str r2, [r3, #52] ; 0x34
  12542. #else
  12543. if (!stretch) dp->sect = 0; /* (this line is to suppress compiler warning) */
  12544. dp->sect = 0; return FR_NO_FILE; /* Report EOT */
  12545. #endif
  12546. }
  12547. dp->clust = clst; /* Initialize data for new cluster */
  12548. 8004e6a: 687b ldr r3, [r7, #4]
  12549. 8004e6c: 697a ldr r2, [r7, #20]
  12550. 8004e6e: 619a str r2, [r3, #24]
  12551. dp->sect = clust2sect(fs, clst);
  12552. 8004e70: 6979 ldr r1, [r7, #20]
  12553. 8004e72: 68f8 ldr r0, [r7, #12]
  12554. 8004e74: f7ff fb82 bl 800457c <clust2sect>
  12555. 8004e78: 4602 mov r2, r0
  12556. 8004e7a: 687b ldr r3, [r7, #4]
  12557. 8004e7c: 61da str r2, [r3, #28]
  12558. }
  12559. }
  12560. }
  12561. dp->dptr = ofs; /* Current entry */
  12562. 8004e7e: 687b ldr r3, [r7, #4]
  12563. 8004e80: 68ba ldr r2, [r7, #8]
  12564. 8004e82: 615a str r2, [r3, #20]
  12565. dp->dir = fs->win + ofs % SS(fs); /* Pointer to the entry in the win[] */
  12566. 8004e84: 68fb ldr r3, [r7, #12]
  12567. 8004e86: f103 0138 add.w r1, r3, #56 ; 0x38
  12568. 8004e8a: 68fb ldr r3, [r7, #12]
  12569. 8004e8c: 899b ldrh r3, [r3, #12]
  12570. 8004e8e: 461a mov r2, r3
  12571. 8004e90: 68bb ldr r3, [r7, #8]
  12572. 8004e92: fbb3 f0f2 udiv r0, r3, r2
  12573. 8004e96: fb02 f200 mul.w r2, r2, r0
  12574. 8004e9a: 1a9b subs r3, r3, r2
  12575. 8004e9c: 18ca adds r2, r1, r3
  12576. 8004e9e: 687b ldr r3, [r7, #4]
  12577. 8004ea0: 621a str r2, [r3, #32]
  12578. return FR_OK;
  12579. 8004ea2: 2300 movs r3, #0
  12580. }
  12581. 8004ea4: 4618 mov r0, r3
  12582. 8004ea6: 3718 adds r7, #24
  12583. 8004ea8: 46bd mov sp, r7
  12584. 8004eaa: bd80 pop {r7, pc}
  12585. 08004eac <dir_alloc>:
  12586. static
  12587. FRESULT dir_alloc ( /* FR_OK(0):succeeded, !=0:error */
  12588. DIR* dp, /* Pointer to the directory object */
  12589. UINT nent /* Number of contiguous entries to allocate */
  12590. )
  12591. {
  12592. 8004eac: b580 push {r7, lr}
  12593. 8004eae: b086 sub sp, #24
  12594. 8004eb0: af00 add r7, sp, #0
  12595. 8004eb2: 6078 str r0, [r7, #4]
  12596. 8004eb4: 6039 str r1, [r7, #0]
  12597. FRESULT res;
  12598. UINT n;
  12599. FATFS *fs = dp->obj.fs;
  12600. 8004eb6: 687b ldr r3, [r7, #4]
  12601. 8004eb8: 681b ldr r3, [r3, #0]
  12602. 8004eba: 60fb str r3, [r7, #12]
  12603. res = dir_sdi(dp, 0);
  12604. 8004ebc: 2100 movs r1, #0
  12605. 8004ebe: 6878 ldr r0, [r7, #4]
  12606. 8004ec0: f7ff fe95 bl 8004bee <dir_sdi>
  12607. 8004ec4: 4603 mov r3, r0
  12608. 8004ec6: 75fb strb r3, [r7, #23]
  12609. if (res == FR_OK) {
  12610. 8004ec8: 7dfb ldrb r3, [r7, #23]
  12611. 8004eca: 2b00 cmp r3, #0
  12612. 8004ecc: d12b bne.n 8004f26 <dir_alloc+0x7a>
  12613. n = 0;
  12614. 8004ece: 2300 movs r3, #0
  12615. 8004ed0: 613b str r3, [r7, #16]
  12616. do {
  12617. res = move_window(fs, dp->sect);
  12618. 8004ed2: 687b ldr r3, [r7, #4]
  12619. 8004ed4: 69db ldr r3, [r3, #28]
  12620. 8004ed6: 4619 mov r1, r3
  12621. 8004ed8: 68f8 ldr r0, [r7, #12]
  12622. 8004eda: f7ff fab1 bl 8004440 <move_window>
  12623. 8004ede: 4603 mov r3, r0
  12624. 8004ee0: 75fb strb r3, [r7, #23]
  12625. if (res != FR_OK) break;
  12626. 8004ee2: 7dfb ldrb r3, [r7, #23]
  12627. 8004ee4: 2b00 cmp r3, #0
  12628. 8004ee6: d11d bne.n 8004f24 <dir_alloc+0x78>
  12629. #if _FS_EXFAT
  12630. if ((fs->fs_type == FS_EXFAT) ? (int)((dp->dir[XDIR_Type] & 0x80) == 0) : (int)(dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0)) {
  12631. #else
  12632. if (dp->dir[DIR_Name] == DDEM || dp->dir[DIR_Name] == 0) {
  12633. 8004ee8: 687b ldr r3, [r7, #4]
  12634. 8004eea: 6a1b ldr r3, [r3, #32]
  12635. 8004eec: 781b ldrb r3, [r3, #0]
  12636. 8004eee: 2be5 cmp r3, #229 ; 0xe5
  12637. 8004ef0: d004 beq.n 8004efc <dir_alloc+0x50>
  12638. 8004ef2: 687b ldr r3, [r7, #4]
  12639. 8004ef4: 6a1b ldr r3, [r3, #32]
  12640. 8004ef6: 781b ldrb r3, [r3, #0]
  12641. 8004ef8: 2b00 cmp r3, #0
  12642. 8004efa: d107 bne.n 8004f0c <dir_alloc+0x60>
  12643. #endif
  12644. if (++n == nent) break; /* A block of contiguous free entries is found */
  12645. 8004efc: 693b ldr r3, [r7, #16]
  12646. 8004efe: 3301 adds r3, #1
  12647. 8004f00: 613b str r3, [r7, #16]
  12648. 8004f02: 693a ldr r2, [r7, #16]
  12649. 8004f04: 683b ldr r3, [r7, #0]
  12650. 8004f06: 429a cmp r2, r3
  12651. 8004f08: d102 bne.n 8004f10 <dir_alloc+0x64>
  12652. 8004f0a: e00c b.n 8004f26 <dir_alloc+0x7a>
  12653. } else {
  12654. n = 0; /* Not a blank entry. Restart to search */
  12655. 8004f0c: 2300 movs r3, #0
  12656. 8004f0e: 613b str r3, [r7, #16]
  12657. }
  12658. res = dir_next(dp, 1);
  12659. 8004f10: 2101 movs r1, #1
  12660. 8004f12: 6878 ldr r0, [r7, #4]
  12661. 8004f14: f7ff fef4 bl 8004d00 <dir_next>
  12662. 8004f18: 4603 mov r3, r0
  12663. 8004f1a: 75fb strb r3, [r7, #23]
  12664. } while (res == FR_OK); /* Next entry with table stretch enabled */
  12665. 8004f1c: 7dfb ldrb r3, [r7, #23]
  12666. 8004f1e: 2b00 cmp r3, #0
  12667. 8004f20: d0d7 beq.n 8004ed2 <dir_alloc+0x26>
  12668. 8004f22: e000 b.n 8004f26 <dir_alloc+0x7a>
  12669. if (res != FR_OK) break;
  12670. 8004f24: bf00 nop
  12671. }
  12672. if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */
  12673. 8004f26: 7dfb ldrb r3, [r7, #23]
  12674. 8004f28: 2b04 cmp r3, #4
  12675. 8004f2a: d101 bne.n 8004f30 <dir_alloc+0x84>
  12676. 8004f2c: 2307 movs r3, #7
  12677. 8004f2e: 75fb strb r3, [r7, #23]
  12678. return res;
  12679. 8004f30: 7dfb ldrb r3, [r7, #23]
  12680. }
  12681. 8004f32: 4618 mov r0, r3
  12682. 8004f34: 3718 adds r7, #24
  12683. 8004f36: 46bd mov sp, r7
  12684. 8004f38: bd80 pop {r7, pc}
  12685. 08004f3a <ld_clust>:
  12686. static
  12687. DWORD ld_clust ( /* Returns the top cluster value of the SFN entry */
  12688. FATFS* fs, /* Pointer to the fs object */
  12689. const BYTE* dir /* Pointer to the key entry */
  12690. )
  12691. {
  12692. 8004f3a: b580 push {r7, lr}
  12693. 8004f3c: b084 sub sp, #16
  12694. 8004f3e: af00 add r7, sp, #0
  12695. 8004f40: 6078 str r0, [r7, #4]
  12696. 8004f42: 6039 str r1, [r7, #0]
  12697. DWORD cl;
  12698. cl = ld_word(dir + DIR_FstClusLO);
  12699. 8004f44: 683b ldr r3, [r7, #0]
  12700. 8004f46: 331a adds r3, #26
  12701. 8004f48: 4618 mov r0, r3
  12702. 8004f4a: f7fe ffd9 bl 8003f00 <ld_word>
  12703. 8004f4e: 4603 mov r3, r0
  12704. 8004f50: 60fb str r3, [r7, #12]
  12705. if (fs->fs_type == FS_FAT32) {
  12706. 8004f52: 687b ldr r3, [r7, #4]
  12707. 8004f54: 781b ldrb r3, [r3, #0]
  12708. 8004f56: 2b03 cmp r3, #3
  12709. 8004f58: d109 bne.n 8004f6e <ld_clust+0x34>
  12710. cl |= (DWORD)ld_word(dir + DIR_FstClusHI) << 16;
  12711. 8004f5a: 683b ldr r3, [r7, #0]
  12712. 8004f5c: 3314 adds r3, #20
  12713. 8004f5e: 4618 mov r0, r3
  12714. 8004f60: f7fe ffce bl 8003f00 <ld_word>
  12715. 8004f64: 4603 mov r3, r0
  12716. 8004f66: 041b lsls r3, r3, #16
  12717. 8004f68: 68fa ldr r2, [r7, #12]
  12718. 8004f6a: 4313 orrs r3, r2
  12719. 8004f6c: 60fb str r3, [r7, #12]
  12720. }
  12721. return cl;
  12722. 8004f6e: 68fb ldr r3, [r7, #12]
  12723. }
  12724. 8004f70: 4618 mov r0, r3
  12725. 8004f72: 3710 adds r7, #16
  12726. 8004f74: 46bd mov sp, r7
  12727. 8004f76: bd80 pop {r7, pc}
  12728. 08004f78 <st_clust>:
  12729. void st_clust (
  12730. FATFS* fs, /* Pointer to the fs object */
  12731. BYTE* dir, /* Pointer to the key entry */
  12732. DWORD cl /* Value to be set */
  12733. )
  12734. {
  12735. 8004f78: b580 push {r7, lr}
  12736. 8004f7a: b084 sub sp, #16
  12737. 8004f7c: af00 add r7, sp, #0
  12738. 8004f7e: 60f8 str r0, [r7, #12]
  12739. 8004f80: 60b9 str r1, [r7, #8]
  12740. 8004f82: 607a str r2, [r7, #4]
  12741. st_word(dir + DIR_FstClusLO, (WORD)cl);
  12742. 8004f84: 68bb ldr r3, [r7, #8]
  12743. 8004f86: 331a adds r3, #26
  12744. 8004f88: 687a ldr r2, [r7, #4]
  12745. 8004f8a: b292 uxth r2, r2
  12746. 8004f8c: 4611 mov r1, r2
  12747. 8004f8e: 4618 mov r0, r3
  12748. 8004f90: f7fe ffef bl 8003f72 <st_word>
  12749. if (fs->fs_type == FS_FAT32) {
  12750. 8004f94: 68fb ldr r3, [r7, #12]
  12751. 8004f96: 781b ldrb r3, [r3, #0]
  12752. 8004f98: 2b03 cmp r3, #3
  12753. 8004f9a: d109 bne.n 8004fb0 <st_clust+0x38>
  12754. st_word(dir + DIR_FstClusHI, (WORD)(cl >> 16));
  12755. 8004f9c: 68bb ldr r3, [r7, #8]
  12756. 8004f9e: f103 0214 add.w r2, r3, #20
  12757. 8004fa2: 687b ldr r3, [r7, #4]
  12758. 8004fa4: 0c1b lsrs r3, r3, #16
  12759. 8004fa6: b29b uxth r3, r3
  12760. 8004fa8: 4619 mov r1, r3
  12761. 8004faa: 4610 mov r0, r2
  12762. 8004fac: f7fe ffe1 bl 8003f72 <st_word>
  12763. }
  12764. }
  12765. 8004fb0: bf00 nop
  12766. 8004fb2: 3710 adds r7, #16
  12767. 8004fb4: 46bd mov sp, r7
  12768. 8004fb6: bd80 pop {r7, pc}
  12769. 08004fb8 <cmp_lfn>:
  12770. static
  12771. int cmp_lfn ( /* 1:matched, 0:not matched */
  12772. const WCHAR* lfnbuf, /* Pointer to the LFN working buffer to be compared */
  12773. BYTE* dir /* Pointer to the directory entry containing the part of LFN */
  12774. )
  12775. {
  12776. 8004fb8: b590 push {r4, r7, lr}
  12777. 8004fba: b087 sub sp, #28
  12778. 8004fbc: af00 add r7, sp, #0
  12779. 8004fbe: 6078 str r0, [r7, #4]
  12780. 8004fc0: 6039 str r1, [r7, #0]
  12781. UINT i, s;
  12782. WCHAR wc, uc;
  12783. if (ld_word(dir + LDIR_FstClusLO) != 0) return 0; /* Check LDIR_FstClusLO */
  12784. 8004fc2: 683b ldr r3, [r7, #0]
  12785. 8004fc4: 331a adds r3, #26
  12786. 8004fc6: 4618 mov r0, r3
  12787. 8004fc8: f7fe ff9a bl 8003f00 <ld_word>
  12788. 8004fcc: 4603 mov r3, r0
  12789. 8004fce: 2b00 cmp r3, #0
  12790. 8004fd0: d001 beq.n 8004fd6 <cmp_lfn+0x1e>
  12791. 8004fd2: 2300 movs r3, #0
  12792. 8004fd4: e059 b.n 800508a <cmp_lfn+0xd2>
  12793. i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
  12794. 8004fd6: 683b ldr r3, [r7, #0]
  12795. 8004fd8: 781b ldrb r3, [r3, #0]
  12796. 8004fda: f003 033f and.w r3, r3, #63 ; 0x3f
  12797. 8004fde: 1e5a subs r2, r3, #1
  12798. 8004fe0: 4613 mov r3, r2
  12799. 8004fe2: 005b lsls r3, r3, #1
  12800. 8004fe4: 4413 add r3, r2
  12801. 8004fe6: 009b lsls r3, r3, #2
  12802. 8004fe8: 4413 add r3, r2
  12803. 8004fea: 617b str r3, [r7, #20]
  12804. for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */
  12805. 8004fec: 2301 movs r3, #1
  12806. 8004fee: 81fb strh r3, [r7, #14]
  12807. 8004ff0: 2300 movs r3, #0
  12808. 8004ff2: 613b str r3, [r7, #16]
  12809. 8004ff4: e033 b.n 800505e <cmp_lfn+0xa6>
  12810. uc = ld_word(dir + LfnOfs[s]); /* Pick an LFN character */
  12811. 8004ff6: 4a27 ldr r2, [pc, #156] ; (8005094 <cmp_lfn+0xdc>)
  12812. 8004ff8: 693b ldr r3, [r7, #16]
  12813. 8004ffa: 4413 add r3, r2
  12814. 8004ffc: 781b ldrb r3, [r3, #0]
  12815. 8004ffe: 461a mov r2, r3
  12816. 8005000: 683b ldr r3, [r7, #0]
  12817. 8005002: 4413 add r3, r2
  12818. 8005004: 4618 mov r0, r3
  12819. 8005006: f7fe ff7b bl 8003f00 <ld_word>
  12820. 800500a: 4603 mov r3, r0
  12821. 800500c: 81bb strh r3, [r7, #12]
  12822. if (wc) {
  12823. 800500e: 89fb ldrh r3, [r7, #14]
  12824. 8005010: 2b00 cmp r3, #0
  12825. 8005012: d01a beq.n 800504a <cmp_lfn+0x92>
  12826. if (i >= _MAX_LFN || ff_wtoupper(uc) != ff_wtoupper(lfnbuf[i++])) { /* Compare it */
  12827. 8005014: 697b ldr r3, [r7, #20]
  12828. 8005016: 2bfe cmp r3, #254 ; 0xfe
  12829. 8005018: d812 bhi.n 8005040 <cmp_lfn+0x88>
  12830. 800501a: 89bb ldrh r3, [r7, #12]
  12831. 800501c: 4618 mov r0, r3
  12832. 800501e: f002 f82f bl 8007080 <ff_wtoupper>
  12833. 8005022: 4603 mov r3, r0
  12834. 8005024: 461c mov r4, r3
  12835. 8005026: 697b ldr r3, [r7, #20]
  12836. 8005028: 1c5a adds r2, r3, #1
  12837. 800502a: 617a str r2, [r7, #20]
  12838. 800502c: 005b lsls r3, r3, #1
  12839. 800502e: 687a ldr r2, [r7, #4]
  12840. 8005030: 4413 add r3, r2
  12841. 8005032: 881b ldrh r3, [r3, #0]
  12842. 8005034: 4618 mov r0, r3
  12843. 8005036: f002 f823 bl 8007080 <ff_wtoupper>
  12844. 800503a: 4603 mov r3, r0
  12845. 800503c: 429c cmp r4, r3
  12846. 800503e: d001 beq.n 8005044 <cmp_lfn+0x8c>
  12847. return 0; /* Not matched */
  12848. 8005040: 2300 movs r3, #0
  12849. 8005042: e022 b.n 800508a <cmp_lfn+0xd2>
  12850. }
  12851. wc = uc;
  12852. 8005044: 89bb ldrh r3, [r7, #12]
  12853. 8005046: 81fb strh r3, [r7, #14]
  12854. 8005048: e006 b.n 8005058 <cmp_lfn+0xa0>
  12855. } else {
  12856. if (uc != 0xFFFF) return 0; /* Check filler */
  12857. 800504a: 89bb ldrh r3, [r7, #12]
  12858. 800504c: f64f 72ff movw r2, #65535 ; 0xffff
  12859. 8005050: 4293 cmp r3, r2
  12860. 8005052: d001 beq.n 8005058 <cmp_lfn+0xa0>
  12861. 8005054: 2300 movs r3, #0
  12862. 8005056: e018 b.n 800508a <cmp_lfn+0xd2>
  12863. for (wc = 1, s = 0; s < 13; s++) { /* Process all characters in the entry */
  12864. 8005058: 693b ldr r3, [r7, #16]
  12865. 800505a: 3301 adds r3, #1
  12866. 800505c: 613b str r3, [r7, #16]
  12867. 800505e: 693b ldr r3, [r7, #16]
  12868. 8005060: 2b0c cmp r3, #12
  12869. 8005062: d9c8 bls.n 8004ff6 <cmp_lfn+0x3e>
  12870. }
  12871. }
  12872. if ((dir[LDIR_Ord] & LLEF) && wc && lfnbuf[i]) return 0; /* Last segment matched but different length */
  12873. 8005064: 683b ldr r3, [r7, #0]
  12874. 8005066: 781b ldrb r3, [r3, #0]
  12875. 8005068: f003 0340 and.w r3, r3, #64 ; 0x40
  12876. 800506c: 2b00 cmp r3, #0
  12877. 800506e: d00b beq.n 8005088 <cmp_lfn+0xd0>
  12878. 8005070: 89fb ldrh r3, [r7, #14]
  12879. 8005072: 2b00 cmp r3, #0
  12880. 8005074: d008 beq.n 8005088 <cmp_lfn+0xd0>
  12881. 8005076: 697b ldr r3, [r7, #20]
  12882. 8005078: 005b lsls r3, r3, #1
  12883. 800507a: 687a ldr r2, [r7, #4]
  12884. 800507c: 4413 add r3, r2
  12885. 800507e: 881b ldrh r3, [r3, #0]
  12886. 8005080: 2b00 cmp r3, #0
  12887. 8005082: d001 beq.n 8005088 <cmp_lfn+0xd0>
  12888. 8005084: 2300 movs r3, #0
  12889. 8005086: e000 b.n 800508a <cmp_lfn+0xd2>
  12890. return 1; /* The part of LFN matched */
  12891. 8005088: 2301 movs r3, #1
  12892. }
  12893. 800508a: 4618 mov r0, r3
  12894. 800508c: 371c adds r7, #28
  12895. 800508e: 46bd mov sp, r7
  12896. 8005090: bd90 pop {r4, r7, pc}
  12897. 8005092: bf00 nop
  12898. 8005094: 08007c04 .word 0x08007c04
  12899. 08005098 <put_lfn>:
  12900. const WCHAR* lfn, /* Pointer to the LFN */
  12901. BYTE* dir, /* Pointer to the LFN entry to be created */
  12902. BYTE ord, /* LFN order (1-20) */
  12903. BYTE sum /* Checksum of the corresponding SFN */
  12904. )
  12905. {
  12906. 8005098: b580 push {r7, lr}
  12907. 800509a: b088 sub sp, #32
  12908. 800509c: af00 add r7, sp, #0
  12909. 800509e: 60f8 str r0, [r7, #12]
  12910. 80050a0: 60b9 str r1, [r7, #8]
  12911. 80050a2: 4611 mov r1, r2
  12912. 80050a4: 461a mov r2, r3
  12913. 80050a6: 460b mov r3, r1
  12914. 80050a8: 71fb strb r3, [r7, #7]
  12915. 80050aa: 4613 mov r3, r2
  12916. 80050ac: 71bb strb r3, [r7, #6]
  12917. UINT i, s;
  12918. WCHAR wc;
  12919. dir[LDIR_Chksum] = sum; /* Set checksum */
  12920. 80050ae: 68bb ldr r3, [r7, #8]
  12921. 80050b0: 330d adds r3, #13
  12922. 80050b2: 79ba ldrb r2, [r7, #6]
  12923. 80050b4: 701a strb r2, [r3, #0]
  12924. dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
  12925. 80050b6: 68bb ldr r3, [r7, #8]
  12926. 80050b8: 330b adds r3, #11
  12927. 80050ba: 220f movs r2, #15
  12928. 80050bc: 701a strb r2, [r3, #0]
  12929. dir[LDIR_Type] = 0;
  12930. 80050be: 68bb ldr r3, [r7, #8]
  12931. 80050c0: 330c adds r3, #12
  12932. 80050c2: 2200 movs r2, #0
  12933. 80050c4: 701a strb r2, [r3, #0]
  12934. st_word(dir + LDIR_FstClusLO, 0);
  12935. 80050c6: 68bb ldr r3, [r7, #8]
  12936. 80050c8: 331a adds r3, #26
  12937. 80050ca: 2100 movs r1, #0
  12938. 80050cc: 4618 mov r0, r3
  12939. 80050ce: f7fe ff50 bl 8003f72 <st_word>
  12940. i = (ord - 1) * 13; /* Get offset in the LFN working buffer */
  12941. 80050d2: 79fb ldrb r3, [r7, #7]
  12942. 80050d4: 1e5a subs r2, r3, #1
  12943. 80050d6: 4613 mov r3, r2
  12944. 80050d8: 005b lsls r3, r3, #1
  12945. 80050da: 4413 add r3, r2
  12946. 80050dc: 009b lsls r3, r3, #2
  12947. 80050de: 4413 add r3, r2
  12948. 80050e0: 61fb str r3, [r7, #28]
  12949. s = wc = 0;
  12950. 80050e2: 2300 movs r3, #0
  12951. 80050e4: 82fb strh r3, [r7, #22]
  12952. 80050e6: 2300 movs r3, #0
  12953. 80050e8: 61bb str r3, [r7, #24]
  12954. do {
  12955. if (wc != 0xFFFF) wc = lfn[i++]; /* Get an effective character */
  12956. 80050ea: 8afb ldrh r3, [r7, #22]
  12957. 80050ec: f64f 72ff movw r2, #65535 ; 0xffff
  12958. 80050f0: 4293 cmp r3, r2
  12959. 80050f2: d007 beq.n 8005104 <put_lfn+0x6c>
  12960. 80050f4: 69fb ldr r3, [r7, #28]
  12961. 80050f6: 1c5a adds r2, r3, #1
  12962. 80050f8: 61fa str r2, [r7, #28]
  12963. 80050fa: 005b lsls r3, r3, #1
  12964. 80050fc: 68fa ldr r2, [r7, #12]
  12965. 80050fe: 4413 add r3, r2
  12966. 8005100: 881b ldrh r3, [r3, #0]
  12967. 8005102: 82fb strh r3, [r7, #22]
  12968. st_word(dir + LfnOfs[s], wc); /* Put it */
  12969. 8005104: 4a17 ldr r2, [pc, #92] ; (8005164 <put_lfn+0xcc>)
  12970. 8005106: 69bb ldr r3, [r7, #24]
  12971. 8005108: 4413 add r3, r2
  12972. 800510a: 781b ldrb r3, [r3, #0]
  12973. 800510c: 461a mov r2, r3
  12974. 800510e: 68bb ldr r3, [r7, #8]
  12975. 8005110: 4413 add r3, r2
  12976. 8005112: 8afa ldrh r2, [r7, #22]
  12977. 8005114: 4611 mov r1, r2
  12978. 8005116: 4618 mov r0, r3
  12979. 8005118: f7fe ff2b bl 8003f72 <st_word>
  12980. if (wc == 0) wc = 0xFFFF; /* Padding characters for left locations */
  12981. 800511c: 8afb ldrh r3, [r7, #22]
  12982. 800511e: 2b00 cmp r3, #0
  12983. 8005120: d102 bne.n 8005128 <put_lfn+0x90>
  12984. 8005122: f64f 73ff movw r3, #65535 ; 0xffff
  12985. 8005126: 82fb strh r3, [r7, #22]
  12986. } while (++s < 13);
  12987. 8005128: 69bb ldr r3, [r7, #24]
  12988. 800512a: 3301 adds r3, #1
  12989. 800512c: 61bb str r3, [r7, #24]
  12990. 800512e: 69bb ldr r3, [r7, #24]
  12991. 8005130: 2b0c cmp r3, #12
  12992. 8005132: d9da bls.n 80050ea <put_lfn+0x52>
  12993. if (wc == 0xFFFF || !lfn[i]) ord |= LLEF; /* Last LFN part is the start of LFN sequence */
  12994. 8005134: 8afb ldrh r3, [r7, #22]
  12995. 8005136: f64f 72ff movw r2, #65535 ; 0xffff
  12996. 800513a: 4293 cmp r3, r2
  12997. 800513c: d006 beq.n 800514c <put_lfn+0xb4>
  12998. 800513e: 69fb ldr r3, [r7, #28]
  12999. 8005140: 005b lsls r3, r3, #1
  13000. 8005142: 68fa ldr r2, [r7, #12]
  13001. 8005144: 4413 add r3, r2
  13002. 8005146: 881b ldrh r3, [r3, #0]
  13003. 8005148: 2b00 cmp r3, #0
  13004. 800514a: d103 bne.n 8005154 <put_lfn+0xbc>
  13005. 800514c: 79fb ldrb r3, [r7, #7]
  13006. 800514e: f043 0340 orr.w r3, r3, #64 ; 0x40
  13007. 8005152: 71fb strb r3, [r7, #7]
  13008. dir[LDIR_Ord] = ord; /* Set the LFN order */
  13009. 8005154: 68bb ldr r3, [r7, #8]
  13010. 8005156: 79fa ldrb r2, [r7, #7]
  13011. 8005158: 701a strb r2, [r3, #0]
  13012. }
  13013. 800515a: bf00 nop
  13014. 800515c: 3720 adds r7, #32
  13015. 800515e: 46bd mov sp, r7
  13016. 8005160: bd80 pop {r7, pc}
  13017. 8005162: bf00 nop
  13018. 8005164: 08007c04 .word 0x08007c04
  13019. 08005168 <gen_numname>:
  13020. BYTE* dst, /* Pointer to the buffer to store numbered SFN */
  13021. const BYTE* src, /* Pointer to SFN */
  13022. const WCHAR* lfn, /* Pointer to LFN */
  13023. UINT seq /* Sequence number */
  13024. )
  13025. {
  13026. 8005168: b580 push {r7, lr}
  13027. 800516a: b08c sub sp, #48 ; 0x30
  13028. 800516c: af00 add r7, sp, #0
  13029. 800516e: 60f8 str r0, [r7, #12]
  13030. 8005170: 60b9 str r1, [r7, #8]
  13031. 8005172: 607a str r2, [r7, #4]
  13032. 8005174: 603b str r3, [r7, #0]
  13033. UINT i, j;
  13034. WCHAR wc;
  13035. DWORD sr;
  13036. mem_cpy(dst, src, 11);
  13037. 8005176: 220b movs r2, #11
  13038. 8005178: 68b9 ldr r1, [r7, #8]
  13039. 800517a: 68f8 ldr r0, [r7, #12]
  13040. 800517c: f7fe ff3e bl 8003ffc <mem_cpy>
  13041. if (seq > 5) { /* In case of many collisions, generate a hash number instead of sequential number */
  13042. 8005180: 683b ldr r3, [r7, #0]
  13043. 8005182: 2b05 cmp r3, #5
  13044. 8005184: d92b bls.n 80051de <gen_numname+0x76>
  13045. sr = seq;
  13046. 8005186: 683b ldr r3, [r7, #0]
  13047. 8005188: 61fb str r3, [r7, #28]
  13048. while (*lfn) { /* Create a CRC */
  13049. 800518a: e022 b.n 80051d2 <gen_numname+0x6a>
  13050. wc = *lfn++;
  13051. 800518c: 687b ldr r3, [r7, #4]
  13052. 800518e: 1c9a adds r2, r3, #2
  13053. 8005190: 607a str r2, [r7, #4]
  13054. 8005192: 881b ldrh r3, [r3, #0]
  13055. 8005194: 847b strh r3, [r7, #34] ; 0x22
  13056. for (i = 0; i < 16; i++) {
  13057. 8005196: 2300 movs r3, #0
  13058. 8005198: 62bb str r3, [r7, #40] ; 0x28
  13059. 800519a: e017 b.n 80051cc <gen_numname+0x64>
  13060. sr = (sr << 1) + (wc & 1);
  13061. 800519c: 69fb ldr r3, [r7, #28]
  13062. 800519e: 005a lsls r2, r3, #1
  13063. 80051a0: 8c7b ldrh r3, [r7, #34] ; 0x22
  13064. 80051a2: f003 0301 and.w r3, r3, #1
  13065. 80051a6: 4413 add r3, r2
  13066. 80051a8: 61fb str r3, [r7, #28]
  13067. wc >>= 1;
  13068. 80051aa: 8c7b ldrh r3, [r7, #34] ; 0x22
  13069. 80051ac: 085b lsrs r3, r3, #1
  13070. 80051ae: 847b strh r3, [r7, #34] ; 0x22
  13071. if (sr & 0x10000) sr ^= 0x11021;
  13072. 80051b0: 69fb ldr r3, [r7, #28]
  13073. 80051b2: f403 3380 and.w r3, r3, #65536 ; 0x10000
  13074. 80051b6: 2b00 cmp r3, #0
  13075. 80051b8: d005 beq.n 80051c6 <gen_numname+0x5e>
  13076. 80051ba: 69fb ldr r3, [r7, #28]
  13077. 80051bc: f483 3388 eor.w r3, r3, #69632 ; 0x11000
  13078. 80051c0: f083 0321 eor.w r3, r3, #33 ; 0x21
  13079. 80051c4: 61fb str r3, [r7, #28]
  13080. for (i = 0; i < 16; i++) {
  13081. 80051c6: 6abb ldr r3, [r7, #40] ; 0x28
  13082. 80051c8: 3301 adds r3, #1
  13083. 80051ca: 62bb str r3, [r7, #40] ; 0x28
  13084. 80051cc: 6abb ldr r3, [r7, #40] ; 0x28
  13085. 80051ce: 2b0f cmp r3, #15
  13086. 80051d0: d9e4 bls.n 800519c <gen_numname+0x34>
  13087. while (*lfn) { /* Create a CRC */
  13088. 80051d2: 687b ldr r3, [r7, #4]
  13089. 80051d4: 881b ldrh r3, [r3, #0]
  13090. 80051d6: 2b00 cmp r3, #0
  13091. 80051d8: d1d8 bne.n 800518c <gen_numname+0x24>
  13092. }
  13093. }
  13094. seq = (UINT)sr;
  13095. 80051da: 69fb ldr r3, [r7, #28]
  13096. 80051dc: 603b str r3, [r7, #0]
  13097. }
  13098. /* itoa (hexdecimal) */
  13099. i = 7;
  13100. 80051de: 2307 movs r3, #7
  13101. 80051e0: 62bb str r3, [r7, #40] ; 0x28
  13102. do {
  13103. c = (BYTE)((seq % 16) + '0');
  13104. 80051e2: 683b ldr r3, [r7, #0]
  13105. 80051e4: b2db uxtb r3, r3
  13106. 80051e6: f003 030f and.w r3, r3, #15
  13107. 80051ea: b2db uxtb r3, r3
  13108. 80051ec: 3330 adds r3, #48 ; 0x30
  13109. 80051ee: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13110. if (c > '9') c += 7;
  13111. 80051f2: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13112. 80051f6: 2b39 cmp r3, #57 ; 0x39
  13113. 80051f8: d904 bls.n 8005204 <gen_numname+0x9c>
  13114. 80051fa: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13115. 80051fe: 3307 adds r3, #7
  13116. 8005200: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13117. ns[i--] = c;
  13118. 8005204: 6abb ldr r3, [r7, #40] ; 0x28
  13119. 8005206: 1e5a subs r2, r3, #1
  13120. 8005208: 62ba str r2, [r7, #40] ; 0x28
  13121. 800520a: f107 0230 add.w r2, r7, #48 ; 0x30
  13122. 800520e: 4413 add r3, r2
  13123. 8005210: f897 202f ldrb.w r2, [r7, #47] ; 0x2f
  13124. 8005214: f803 2c1c strb.w r2, [r3, #-28]
  13125. seq /= 16;
  13126. 8005218: 683b ldr r3, [r7, #0]
  13127. 800521a: 091b lsrs r3, r3, #4
  13128. 800521c: 603b str r3, [r7, #0]
  13129. } while (seq);
  13130. 800521e: 683b ldr r3, [r7, #0]
  13131. 8005220: 2b00 cmp r3, #0
  13132. 8005222: d1de bne.n 80051e2 <gen_numname+0x7a>
  13133. ns[i] = '~';
  13134. 8005224: f107 0214 add.w r2, r7, #20
  13135. 8005228: 6abb ldr r3, [r7, #40] ; 0x28
  13136. 800522a: 4413 add r3, r2
  13137. 800522c: 227e movs r2, #126 ; 0x7e
  13138. 800522e: 701a strb r2, [r3, #0]
  13139. /* Append the number */
  13140. for (j = 0; j < i && dst[j] != ' '; j++) {
  13141. 8005230: 2300 movs r3, #0
  13142. 8005232: 627b str r3, [r7, #36] ; 0x24
  13143. 8005234: e002 b.n 800523c <gen_numname+0xd4>
  13144. 8005236: 6a7b ldr r3, [r7, #36] ; 0x24
  13145. 8005238: 3301 adds r3, #1
  13146. 800523a: 627b str r3, [r7, #36] ; 0x24
  13147. 800523c: 6a7a ldr r2, [r7, #36] ; 0x24
  13148. 800523e: 6abb ldr r3, [r7, #40] ; 0x28
  13149. 8005240: 429a cmp r2, r3
  13150. 8005242: d205 bcs.n 8005250 <gen_numname+0xe8>
  13151. 8005244: 68fa ldr r2, [r7, #12]
  13152. 8005246: 6a7b ldr r3, [r7, #36] ; 0x24
  13153. 8005248: 4413 add r3, r2
  13154. 800524a: 781b ldrb r3, [r3, #0]
  13155. 800524c: 2b20 cmp r3, #32
  13156. 800524e: d1f2 bne.n 8005236 <gen_numname+0xce>
  13157. if (j == i - 1) break;
  13158. j++;
  13159. }
  13160. }
  13161. do {
  13162. dst[j++] = (i < 8) ? ns[i++] : ' ';
  13163. 8005250: 6abb ldr r3, [r7, #40] ; 0x28
  13164. 8005252: 2b07 cmp r3, #7
  13165. 8005254: d808 bhi.n 8005268 <gen_numname+0x100>
  13166. 8005256: 6abb ldr r3, [r7, #40] ; 0x28
  13167. 8005258: 1c5a adds r2, r3, #1
  13168. 800525a: 62ba str r2, [r7, #40] ; 0x28
  13169. 800525c: f107 0230 add.w r2, r7, #48 ; 0x30
  13170. 8005260: 4413 add r3, r2
  13171. 8005262: f813 1c1c ldrb.w r1, [r3, #-28]
  13172. 8005266: e000 b.n 800526a <gen_numname+0x102>
  13173. 8005268: 2120 movs r1, #32
  13174. 800526a: 6a7b ldr r3, [r7, #36] ; 0x24
  13175. 800526c: 1c5a adds r2, r3, #1
  13176. 800526e: 627a str r2, [r7, #36] ; 0x24
  13177. 8005270: 68fa ldr r2, [r7, #12]
  13178. 8005272: 4413 add r3, r2
  13179. 8005274: 460a mov r2, r1
  13180. 8005276: 701a strb r2, [r3, #0]
  13181. } while (j < 8);
  13182. 8005278: 6a7b ldr r3, [r7, #36] ; 0x24
  13183. 800527a: 2b07 cmp r3, #7
  13184. 800527c: d9e8 bls.n 8005250 <gen_numname+0xe8>
  13185. }
  13186. 800527e: bf00 nop
  13187. 8005280: 3730 adds r7, #48 ; 0x30
  13188. 8005282: 46bd mov sp, r7
  13189. 8005284: bd80 pop {r7, pc}
  13190. 08005286 <sum_sfn>:
  13191. static
  13192. BYTE sum_sfn (
  13193. const BYTE* dir /* Pointer to the SFN entry */
  13194. )
  13195. {
  13196. 8005286: b480 push {r7}
  13197. 8005288: b085 sub sp, #20
  13198. 800528a: af00 add r7, sp, #0
  13199. 800528c: 6078 str r0, [r7, #4]
  13200. BYTE sum = 0;
  13201. 800528e: 2300 movs r3, #0
  13202. 8005290: 73fb strb r3, [r7, #15]
  13203. UINT n = 11;
  13204. 8005292: 230b movs r3, #11
  13205. 8005294: 60bb str r3, [r7, #8]
  13206. do {
  13207. sum = (sum >> 1) + (sum << 7) + *dir++;
  13208. 8005296: 7bfb ldrb r3, [r7, #15]
  13209. 8005298: b2da uxtb r2, r3
  13210. 800529a: 0852 lsrs r2, r2, #1
  13211. 800529c: 01db lsls r3, r3, #7
  13212. 800529e: 4313 orrs r3, r2
  13213. 80052a0: b2da uxtb r2, r3
  13214. 80052a2: 687b ldr r3, [r7, #4]
  13215. 80052a4: 1c59 adds r1, r3, #1
  13216. 80052a6: 6079 str r1, [r7, #4]
  13217. 80052a8: 781b ldrb r3, [r3, #0]
  13218. 80052aa: 4413 add r3, r2
  13219. 80052ac: 73fb strb r3, [r7, #15]
  13220. } while (--n);
  13221. 80052ae: 68bb ldr r3, [r7, #8]
  13222. 80052b0: 3b01 subs r3, #1
  13223. 80052b2: 60bb str r3, [r7, #8]
  13224. 80052b4: 68bb ldr r3, [r7, #8]
  13225. 80052b6: 2b00 cmp r3, #0
  13226. 80052b8: d1ed bne.n 8005296 <sum_sfn+0x10>
  13227. return sum;
  13228. 80052ba: 7bfb ldrb r3, [r7, #15]
  13229. }
  13230. 80052bc: 4618 mov r0, r3
  13231. 80052be: 3714 adds r7, #20
  13232. 80052c0: 46bd mov sp, r7
  13233. 80052c2: bc80 pop {r7}
  13234. 80052c4: 4770 bx lr
  13235. 080052c6 <dir_find>:
  13236. static
  13237. FRESULT dir_find ( /* FR_OK(0):succeeded, !=0:error */
  13238. DIR* dp /* Pointer to the directory object with the file name */
  13239. )
  13240. {
  13241. 80052c6: b580 push {r7, lr}
  13242. 80052c8: b086 sub sp, #24
  13243. 80052ca: af00 add r7, sp, #0
  13244. 80052cc: 6078 str r0, [r7, #4]
  13245. FRESULT res;
  13246. FATFS *fs = dp->obj.fs;
  13247. 80052ce: 687b ldr r3, [r7, #4]
  13248. 80052d0: 681b ldr r3, [r3, #0]
  13249. 80052d2: 613b str r3, [r7, #16]
  13250. BYTE c;
  13251. #if _USE_LFN != 0
  13252. BYTE a, ord, sum;
  13253. #endif
  13254. res = dir_sdi(dp, 0); /* Rewind directory object */
  13255. 80052d4: 2100 movs r1, #0
  13256. 80052d6: 6878 ldr r0, [r7, #4]
  13257. 80052d8: f7ff fc89 bl 8004bee <dir_sdi>
  13258. 80052dc: 4603 mov r3, r0
  13259. 80052de: 75fb strb r3, [r7, #23]
  13260. if (res != FR_OK) return res;
  13261. 80052e0: 7dfb ldrb r3, [r7, #23]
  13262. 80052e2: 2b00 cmp r3, #0
  13263. 80052e4: d001 beq.n 80052ea <dir_find+0x24>
  13264. 80052e6: 7dfb ldrb r3, [r7, #23]
  13265. 80052e8: e0a9 b.n 800543e <dir_find+0x178>
  13266. return res;
  13267. }
  13268. #endif
  13269. /* On the FAT12/16/32 volume */
  13270. #if _USE_LFN != 0
  13271. ord = sum = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
  13272. 80052ea: 23ff movs r3, #255 ; 0xff
  13273. 80052ec: 753b strb r3, [r7, #20]
  13274. 80052ee: 7d3b ldrb r3, [r7, #20]
  13275. 80052f0: 757b strb r3, [r7, #21]
  13276. 80052f2: 687b ldr r3, [r7, #4]
  13277. 80052f4: f04f 32ff mov.w r2, #4294967295
  13278. 80052f8: 631a str r2, [r3, #48] ; 0x30
  13279. #endif
  13280. do {
  13281. res = move_window(fs, dp->sect);
  13282. 80052fa: 687b ldr r3, [r7, #4]
  13283. 80052fc: 69db ldr r3, [r3, #28]
  13284. 80052fe: 4619 mov r1, r3
  13285. 8005300: 6938 ldr r0, [r7, #16]
  13286. 8005302: f7ff f89d bl 8004440 <move_window>
  13287. 8005306: 4603 mov r3, r0
  13288. 8005308: 75fb strb r3, [r7, #23]
  13289. if (res != FR_OK) break;
  13290. 800530a: 7dfb ldrb r3, [r7, #23]
  13291. 800530c: 2b00 cmp r3, #0
  13292. 800530e: f040 8090 bne.w 8005432 <dir_find+0x16c>
  13293. c = dp->dir[DIR_Name];
  13294. 8005312: 687b ldr r3, [r7, #4]
  13295. 8005314: 6a1b ldr r3, [r3, #32]
  13296. 8005316: 781b ldrb r3, [r3, #0]
  13297. 8005318: 75bb strb r3, [r7, #22]
  13298. if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
  13299. 800531a: 7dbb ldrb r3, [r7, #22]
  13300. 800531c: 2b00 cmp r3, #0
  13301. 800531e: d102 bne.n 8005326 <dir_find+0x60>
  13302. 8005320: 2304 movs r3, #4
  13303. 8005322: 75fb strb r3, [r7, #23]
  13304. 8005324: e08a b.n 800543c <dir_find+0x176>
  13305. #if _USE_LFN != 0 /* LFN configuration */
  13306. dp->obj.attr = a = dp->dir[DIR_Attr] & AM_MASK;
  13307. 8005326: 687b ldr r3, [r7, #4]
  13308. 8005328: 6a1b ldr r3, [r3, #32]
  13309. 800532a: 330b adds r3, #11
  13310. 800532c: 781b ldrb r3, [r3, #0]
  13311. 800532e: f003 033f and.w r3, r3, #63 ; 0x3f
  13312. 8005332: 73fb strb r3, [r7, #15]
  13313. 8005334: 687b ldr r3, [r7, #4]
  13314. 8005336: 7bfa ldrb r2, [r7, #15]
  13315. 8005338: 719a strb r2, [r3, #6]
  13316. if (c == DDEM || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
  13317. 800533a: 7dbb ldrb r3, [r7, #22]
  13318. 800533c: 2be5 cmp r3, #229 ; 0xe5
  13319. 800533e: d007 beq.n 8005350 <dir_find+0x8a>
  13320. 8005340: 7bfb ldrb r3, [r7, #15]
  13321. 8005342: f003 0308 and.w r3, r3, #8
  13322. 8005346: 2b00 cmp r3, #0
  13323. 8005348: d009 beq.n 800535e <dir_find+0x98>
  13324. 800534a: 7bfb ldrb r3, [r7, #15]
  13325. 800534c: 2b0f cmp r3, #15
  13326. 800534e: d006 beq.n 800535e <dir_find+0x98>
  13327. ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
  13328. 8005350: 23ff movs r3, #255 ; 0xff
  13329. 8005352: 757b strb r3, [r7, #21]
  13330. 8005354: 687b ldr r3, [r7, #4]
  13331. 8005356: f04f 32ff mov.w r2, #4294967295
  13332. 800535a: 631a str r2, [r3, #48] ; 0x30
  13333. 800535c: e05e b.n 800541c <dir_find+0x156>
  13334. } else {
  13335. if (a == AM_LFN) { /* An LFN entry is found */
  13336. 800535e: 7bfb ldrb r3, [r7, #15]
  13337. 8005360: 2b0f cmp r3, #15
  13338. 8005362: d136 bne.n 80053d2 <dir_find+0x10c>
  13339. if (!(dp->fn[NSFLAG] & NS_NOLFN)) {
  13340. 8005364: 687b ldr r3, [r7, #4]
  13341. 8005366: f893 302f ldrb.w r3, [r3, #47] ; 0x2f
  13342. 800536a: f003 0340 and.w r3, r3, #64 ; 0x40
  13343. 800536e: 2b00 cmp r3, #0
  13344. 8005370: d154 bne.n 800541c <dir_find+0x156>
  13345. if (c & LLEF) { /* Is it start of LFN sequence? */
  13346. 8005372: 7dbb ldrb r3, [r7, #22]
  13347. 8005374: f003 0340 and.w r3, r3, #64 ; 0x40
  13348. 8005378: 2b00 cmp r3, #0
  13349. 800537a: d00d beq.n 8005398 <dir_find+0xd2>
  13350. sum = dp->dir[LDIR_Chksum];
  13351. 800537c: 687b ldr r3, [r7, #4]
  13352. 800537e: 6a1b ldr r3, [r3, #32]
  13353. 8005380: 7b5b ldrb r3, [r3, #13]
  13354. 8005382: 753b strb r3, [r7, #20]
  13355. c &= (BYTE)~LLEF; ord = c; /* LFN start order */
  13356. 8005384: 7dbb ldrb r3, [r7, #22]
  13357. 8005386: f023 0340 bic.w r3, r3, #64 ; 0x40
  13358. 800538a: 75bb strb r3, [r7, #22]
  13359. 800538c: 7dbb ldrb r3, [r7, #22]
  13360. 800538e: 757b strb r3, [r7, #21]
  13361. dp->blk_ofs = dp->dptr; /* Start offset of LFN */
  13362. 8005390: 687b ldr r3, [r7, #4]
  13363. 8005392: 695a ldr r2, [r3, #20]
  13364. 8005394: 687b ldr r3, [r7, #4]
  13365. 8005396: 631a str r2, [r3, #48] ; 0x30
  13366. }
  13367. /* Check validity of the LFN entry and compare it with given name */
  13368. ord = (c == ord && sum == dp->dir[LDIR_Chksum] && cmp_lfn(fs->lfnbuf, dp->dir)) ? ord - 1 : 0xFF;
  13369. 8005398: 7dba ldrb r2, [r7, #22]
  13370. 800539a: 7d7b ldrb r3, [r7, #21]
  13371. 800539c: 429a cmp r2, r3
  13372. 800539e: d115 bne.n 80053cc <dir_find+0x106>
  13373. 80053a0: 687b ldr r3, [r7, #4]
  13374. 80053a2: 6a1b ldr r3, [r3, #32]
  13375. 80053a4: 330d adds r3, #13
  13376. 80053a6: 781b ldrb r3, [r3, #0]
  13377. 80053a8: 7d3a ldrb r2, [r7, #20]
  13378. 80053aa: 429a cmp r2, r3
  13379. 80053ac: d10e bne.n 80053cc <dir_find+0x106>
  13380. 80053ae: 693b ldr r3, [r7, #16]
  13381. 80053b0: 691a ldr r2, [r3, #16]
  13382. 80053b2: 687b ldr r3, [r7, #4]
  13383. 80053b4: 6a1b ldr r3, [r3, #32]
  13384. 80053b6: 4619 mov r1, r3
  13385. 80053b8: 4610 mov r0, r2
  13386. 80053ba: f7ff fdfd bl 8004fb8 <cmp_lfn>
  13387. 80053be: 4603 mov r3, r0
  13388. 80053c0: 2b00 cmp r3, #0
  13389. 80053c2: d003 beq.n 80053cc <dir_find+0x106>
  13390. 80053c4: 7d7b ldrb r3, [r7, #21]
  13391. 80053c6: 3b01 subs r3, #1
  13392. 80053c8: b2db uxtb r3, r3
  13393. 80053ca: e000 b.n 80053ce <dir_find+0x108>
  13394. 80053cc: 23ff movs r3, #255 ; 0xff
  13395. 80053ce: 757b strb r3, [r7, #21]
  13396. 80053d0: e024 b.n 800541c <dir_find+0x156>
  13397. }
  13398. } else { /* An SFN entry is found */
  13399. if (!ord && sum == sum_sfn(dp->dir)) break; /* LFN matched? */
  13400. 80053d2: 7d7b ldrb r3, [r7, #21]
  13401. 80053d4: 2b00 cmp r3, #0
  13402. 80053d6: d109 bne.n 80053ec <dir_find+0x126>
  13403. 80053d8: 687b ldr r3, [r7, #4]
  13404. 80053da: 6a1b ldr r3, [r3, #32]
  13405. 80053dc: 4618 mov r0, r3
  13406. 80053de: f7ff ff52 bl 8005286 <sum_sfn>
  13407. 80053e2: 4603 mov r3, r0
  13408. 80053e4: 461a mov r2, r3
  13409. 80053e6: 7d3b ldrb r3, [r7, #20]
  13410. 80053e8: 4293 cmp r3, r2
  13411. 80053ea: d024 beq.n 8005436 <dir_find+0x170>
  13412. if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */
  13413. 80053ec: 687b ldr r3, [r7, #4]
  13414. 80053ee: f893 302f ldrb.w r3, [r3, #47] ; 0x2f
  13415. 80053f2: f003 0301 and.w r3, r3, #1
  13416. 80053f6: 2b00 cmp r3, #0
  13417. 80053f8: d10a bne.n 8005410 <dir_find+0x14a>
  13418. 80053fa: 687b ldr r3, [r7, #4]
  13419. 80053fc: 6a18 ldr r0, [r3, #32]
  13420. 80053fe: 687b ldr r3, [r7, #4]
  13421. 8005400: 3324 adds r3, #36 ; 0x24
  13422. 8005402: 220b movs r2, #11
  13423. 8005404: 4619 mov r1, r3
  13424. 8005406: f7fe fe32 bl 800406e <mem_cmp>
  13425. 800540a: 4603 mov r3, r0
  13426. 800540c: 2b00 cmp r3, #0
  13427. 800540e: d014 beq.n 800543a <dir_find+0x174>
  13428. ord = 0xFF; dp->blk_ofs = 0xFFFFFFFF; /* Reset LFN sequence */
  13429. 8005410: 23ff movs r3, #255 ; 0xff
  13430. 8005412: 757b strb r3, [r7, #21]
  13431. 8005414: 687b ldr r3, [r7, #4]
  13432. 8005416: f04f 32ff mov.w r2, #4294967295
  13433. 800541a: 631a str r2, [r3, #48] ; 0x30
  13434. }
  13435. #else /* Non LFN configuration */
  13436. dp->obj.attr = dp->dir[DIR_Attr] & AM_MASK;
  13437. if (!(dp->dir[DIR_Attr] & AM_VOL) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* Is it a valid entry? */
  13438. #endif
  13439. res = dir_next(dp, 0); /* Next entry */
  13440. 800541c: 2100 movs r1, #0
  13441. 800541e: 6878 ldr r0, [r7, #4]
  13442. 8005420: f7ff fc6e bl 8004d00 <dir_next>
  13443. 8005424: 4603 mov r3, r0
  13444. 8005426: 75fb strb r3, [r7, #23]
  13445. } while (res == FR_OK);
  13446. 8005428: 7dfb ldrb r3, [r7, #23]
  13447. 800542a: 2b00 cmp r3, #0
  13448. 800542c: f43f af65 beq.w 80052fa <dir_find+0x34>
  13449. 8005430: e004 b.n 800543c <dir_find+0x176>
  13450. if (res != FR_OK) break;
  13451. 8005432: bf00 nop
  13452. 8005434: e002 b.n 800543c <dir_find+0x176>
  13453. if (!ord && sum == sum_sfn(dp->dir)) break; /* LFN matched? */
  13454. 8005436: bf00 nop
  13455. 8005438: e000 b.n 800543c <dir_find+0x176>
  13456. if (!(dp->fn[NSFLAG] & NS_LOSS) && !mem_cmp(dp->dir, dp->fn, 11)) break; /* SFN matched? */
  13457. 800543a: bf00 nop
  13458. return res;
  13459. 800543c: 7dfb ldrb r3, [r7, #23]
  13460. }
  13461. 800543e: 4618 mov r0, r3
  13462. 8005440: 3718 adds r7, #24
  13463. 8005442: 46bd mov sp, r7
  13464. 8005444: bd80 pop {r7, pc}
  13465. ...
  13466. 08005448 <dir_register>:
  13467. static
  13468. FRESULT dir_register ( /* FR_OK:succeeded, FR_DENIED:no free entry or too many SFN collision, FR_DISK_ERR:disk error */
  13469. DIR* dp /* Target directory with object name to be created */
  13470. )
  13471. {
  13472. 8005448: b580 push {r7, lr}
  13473. 800544a: b08c sub sp, #48 ; 0x30
  13474. 800544c: af00 add r7, sp, #0
  13475. 800544e: 6078 str r0, [r7, #4]
  13476. FRESULT res;
  13477. FATFS *fs = dp->obj.fs;
  13478. 8005450: 687b ldr r3, [r7, #4]
  13479. 8005452: 681b ldr r3, [r3, #0]
  13480. 8005454: 61fb str r3, [r7, #28]
  13481. #if _USE_LFN != 0 /* LFN configuration */
  13482. UINT n, nlen, nent;
  13483. BYTE sn[12], sum;
  13484. if (dp->fn[NSFLAG] & (NS_DOT | NS_NONAME)) return FR_INVALID_NAME; /* Check name validity */
  13485. 8005456: 687b ldr r3, [r7, #4]
  13486. 8005458: f893 302f ldrb.w r3, [r3, #47] ; 0x2f
  13487. 800545c: f003 03a0 and.w r3, r3, #160 ; 0xa0
  13488. 8005460: 2b00 cmp r3, #0
  13489. 8005462: d001 beq.n 8005468 <dir_register+0x20>
  13490. 8005464: 2306 movs r3, #6
  13491. 8005466: e0e0 b.n 800562a <dir_register+0x1e2>
  13492. for (nlen = 0; fs->lfnbuf[nlen]; nlen++) ; /* Get lfn length */
  13493. 8005468: 2300 movs r3, #0
  13494. 800546a: 627b str r3, [r7, #36] ; 0x24
  13495. 800546c: e002 b.n 8005474 <dir_register+0x2c>
  13496. 800546e: 6a7b ldr r3, [r7, #36] ; 0x24
  13497. 8005470: 3301 adds r3, #1
  13498. 8005472: 627b str r3, [r7, #36] ; 0x24
  13499. 8005474: 69fb ldr r3, [r7, #28]
  13500. 8005476: 691a ldr r2, [r3, #16]
  13501. 8005478: 6a7b ldr r3, [r7, #36] ; 0x24
  13502. 800547a: 005b lsls r3, r3, #1
  13503. 800547c: 4413 add r3, r2
  13504. 800547e: 881b ldrh r3, [r3, #0]
  13505. 8005480: 2b00 cmp r3, #0
  13506. 8005482: d1f4 bne.n 800546e <dir_register+0x26>
  13507. create_xdir(fs->dirbuf, fs->lfnbuf); /* Create on-memory directory block to be written later */
  13508. return FR_OK;
  13509. }
  13510. #endif
  13511. /* On the FAT12/16/32 volume */
  13512. mem_cpy(sn, dp->fn, 12);
  13513. 8005484: 687b ldr r3, [r7, #4]
  13514. 8005486: f103 0124 add.w r1, r3, #36 ; 0x24
  13515. 800548a: f107 030c add.w r3, r7, #12
  13516. 800548e: 220c movs r2, #12
  13517. 8005490: 4618 mov r0, r3
  13518. 8005492: f7fe fdb3 bl 8003ffc <mem_cpy>
  13519. if (sn[NSFLAG] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
  13520. 8005496: 7dfb ldrb r3, [r7, #23]
  13521. 8005498: f003 0301 and.w r3, r3, #1
  13522. 800549c: 2b00 cmp r3, #0
  13523. 800549e: d032 beq.n 8005506 <dir_register+0xbe>
  13524. dp->fn[NSFLAG] = NS_NOLFN; /* Find only SFN */
  13525. 80054a0: 687b ldr r3, [r7, #4]
  13526. 80054a2: 2240 movs r2, #64 ; 0x40
  13527. 80054a4: f883 202f strb.w r2, [r3, #47] ; 0x2f
  13528. for (n = 1; n < 100; n++) {
  13529. 80054a8: 2301 movs r3, #1
  13530. 80054aa: 62bb str r3, [r7, #40] ; 0x28
  13531. 80054ac: e016 b.n 80054dc <dir_register+0x94>
  13532. gen_numname(dp->fn, sn, fs->lfnbuf, n); /* Generate a numbered name */
  13533. 80054ae: 687b ldr r3, [r7, #4]
  13534. 80054b0: f103 0024 add.w r0, r3, #36 ; 0x24
  13535. 80054b4: 69fb ldr r3, [r7, #28]
  13536. 80054b6: 691a ldr r2, [r3, #16]
  13537. 80054b8: f107 010c add.w r1, r7, #12
  13538. 80054bc: 6abb ldr r3, [r7, #40] ; 0x28
  13539. 80054be: f7ff fe53 bl 8005168 <gen_numname>
  13540. res = dir_find(dp); /* Check if the name collides with existing SFN */
  13541. 80054c2: 6878 ldr r0, [r7, #4]
  13542. 80054c4: f7ff feff bl 80052c6 <dir_find>
  13543. 80054c8: 4603 mov r3, r0
  13544. 80054ca: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13545. if (res != FR_OK) break;
  13546. 80054ce: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13547. 80054d2: 2b00 cmp r3, #0
  13548. 80054d4: d106 bne.n 80054e4 <dir_register+0x9c>
  13549. for (n = 1; n < 100; n++) {
  13550. 80054d6: 6abb ldr r3, [r7, #40] ; 0x28
  13551. 80054d8: 3301 adds r3, #1
  13552. 80054da: 62bb str r3, [r7, #40] ; 0x28
  13553. 80054dc: 6abb ldr r3, [r7, #40] ; 0x28
  13554. 80054de: 2b63 cmp r3, #99 ; 0x63
  13555. 80054e0: d9e5 bls.n 80054ae <dir_register+0x66>
  13556. 80054e2: e000 b.n 80054e6 <dir_register+0x9e>
  13557. if (res != FR_OK) break;
  13558. 80054e4: bf00 nop
  13559. }
  13560. if (n == 100) return FR_DENIED; /* Abort if too many collisions */
  13561. 80054e6: 6abb ldr r3, [r7, #40] ; 0x28
  13562. 80054e8: 2b64 cmp r3, #100 ; 0x64
  13563. 80054ea: d101 bne.n 80054f0 <dir_register+0xa8>
  13564. 80054ec: 2307 movs r3, #7
  13565. 80054ee: e09c b.n 800562a <dir_register+0x1e2>
  13566. if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
  13567. 80054f0: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13568. 80054f4: 2b04 cmp r3, #4
  13569. 80054f6: d002 beq.n 80054fe <dir_register+0xb6>
  13570. 80054f8: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13571. 80054fc: e095 b.n 800562a <dir_register+0x1e2>
  13572. dp->fn[NSFLAG] = sn[NSFLAG];
  13573. 80054fe: 7dfa ldrb r2, [r7, #23]
  13574. 8005500: 687b ldr r3, [r7, #4]
  13575. 8005502: f883 202f strb.w r2, [r3, #47] ; 0x2f
  13576. }
  13577. /* Create an SFN with/without LFNs. */
  13578. nent = (sn[NSFLAG] & NS_LFN) ? (nlen + 12) / 13 + 1 : 1; /* Number of entries to allocate */
  13579. 8005506: 7dfb ldrb r3, [r7, #23]
  13580. 8005508: f003 0302 and.w r3, r3, #2
  13581. 800550c: 2b00 cmp r3, #0
  13582. 800550e: d007 beq.n 8005520 <dir_register+0xd8>
  13583. 8005510: 6a7b ldr r3, [r7, #36] ; 0x24
  13584. 8005512: 330c adds r3, #12
  13585. 8005514: 4a47 ldr r2, [pc, #284] ; (8005634 <dir_register+0x1ec>)
  13586. 8005516: fba2 2303 umull r2, r3, r2, r3
  13587. 800551a: 089b lsrs r3, r3, #2
  13588. 800551c: 3301 adds r3, #1
  13589. 800551e: e000 b.n 8005522 <dir_register+0xda>
  13590. 8005520: 2301 movs r3, #1
  13591. 8005522: 623b str r3, [r7, #32]
  13592. res = dir_alloc(dp, nent); /* Allocate entries */
  13593. 8005524: 6a39 ldr r1, [r7, #32]
  13594. 8005526: 6878 ldr r0, [r7, #4]
  13595. 8005528: f7ff fcc0 bl 8004eac <dir_alloc>
  13596. 800552c: 4603 mov r3, r0
  13597. 800552e: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13598. if (res == FR_OK && --nent) { /* Set LFN entry if needed */
  13599. 8005532: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13600. 8005536: 2b00 cmp r3, #0
  13601. 8005538: d148 bne.n 80055cc <dir_register+0x184>
  13602. 800553a: 6a3b ldr r3, [r7, #32]
  13603. 800553c: 3b01 subs r3, #1
  13604. 800553e: 623b str r3, [r7, #32]
  13605. 8005540: 6a3b ldr r3, [r7, #32]
  13606. 8005542: 2b00 cmp r3, #0
  13607. 8005544: d042 beq.n 80055cc <dir_register+0x184>
  13608. res = dir_sdi(dp, dp->dptr - nent * SZDIRE);
  13609. 8005546: 687b ldr r3, [r7, #4]
  13610. 8005548: 695a ldr r2, [r3, #20]
  13611. 800554a: 6a3b ldr r3, [r7, #32]
  13612. 800554c: 015b lsls r3, r3, #5
  13613. 800554e: 1ad3 subs r3, r2, r3
  13614. 8005550: 4619 mov r1, r3
  13615. 8005552: 6878 ldr r0, [r7, #4]
  13616. 8005554: f7ff fb4b bl 8004bee <dir_sdi>
  13617. 8005558: 4603 mov r3, r0
  13618. 800555a: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13619. if (res == FR_OK) {
  13620. 800555e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13621. 8005562: 2b00 cmp r3, #0
  13622. 8005564: d132 bne.n 80055cc <dir_register+0x184>
  13623. sum = sum_sfn(dp->fn); /* Checksum value of the SFN tied to the LFN */
  13624. 8005566: 687b ldr r3, [r7, #4]
  13625. 8005568: 3324 adds r3, #36 ; 0x24
  13626. 800556a: 4618 mov r0, r3
  13627. 800556c: f7ff fe8b bl 8005286 <sum_sfn>
  13628. 8005570: 4603 mov r3, r0
  13629. 8005572: 76fb strb r3, [r7, #27]
  13630. do { /* Store LFN entries in bottom first */
  13631. res = move_window(fs, dp->sect);
  13632. 8005574: 687b ldr r3, [r7, #4]
  13633. 8005576: 69db ldr r3, [r3, #28]
  13634. 8005578: 4619 mov r1, r3
  13635. 800557a: 69f8 ldr r0, [r7, #28]
  13636. 800557c: f7fe ff60 bl 8004440 <move_window>
  13637. 8005580: 4603 mov r3, r0
  13638. 8005582: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13639. if (res != FR_OK) break;
  13640. 8005586: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13641. 800558a: 2b00 cmp r3, #0
  13642. 800558c: d11d bne.n 80055ca <dir_register+0x182>
  13643. put_lfn(fs->lfnbuf, dp->dir, (BYTE)nent, sum);
  13644. 800558e: 69fb ldr r3, [r7, #28]
  13645. 8005590: 6918 ldr r0, [r3, #16]
  13646. 8005592: 687b ldr r3, [r7, #4]
  13647. 8005594: 6a19 ldr r1, [r3, #32]
  13648. 8005596: 6a3b ldr r3, [r7, #32]
  13649. 8005598: b2da uxtb r2, r3
  13650. 800559a: 7efb ldrb r3, [r7, #27]
  13651. 800559c: f7ff fd7c bl 8005098 <put_lfn>
  13652. fs->wflag = 1;
  13653. 80055a0: 69fb ldr r3, [r7, #28]
  13654. 80055a2: 2201 movs r2, #1
  13655. 80055a4: 70da strb r2, [r3, #3]
  13656. res = dir_next(dp, 0); /* Next entry */
  13657. 80055a6: 2100 movs r1, #0
  13658. 80055a8: 6878 ldr r0, [r7, #4]
  13659. 80055aa: f7ff fba9 bl 8004d00 <dir_next>
  13660. 80055ae: 4603 mov r3, r0
  13661. 80055b0: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13662. } while (res == FR_OK && --nent);
  13663. 80055b4: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13664. 80055b8: 2b00 cmp r3, #0
  13665. 80055ba: d107 bne.n 80055cc <dir_register+0x184>
  13666. 80055bc: 6a3b ldr r3, [r7, #32]
  13667. 80055be: 3b01 subs r3, #1
  13668. 80055c0: 623b str r3, [r7, #32]
  13669. 80055c2: 6a3b ldr r3, [r7, #32]
  13670. 80055c4: 2b00 cmp r3, #0
  13671. 80055c6: d1d5 bne.n 8005574 <dir_register+0x12c>
  13672. 80055c8: e000 b.n 80055cc <dir_register+0x184>
  13673. if (res != FR_OK) break;
  13674. 80055ca: bf00 nop
  13675. res = dir_alloc(dp, 1); /* Allocate an entry for SFN */
  13676. #endif
  13677. /* Set SFN entry */
  13678. if (res == FR_OK) {
  13679. 80055cc: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13680. 80055d0: 2b00 cmp r3, #0
  13681. 80055d2: d128 bne.n 8005626 <dir_register+0x1de>
  13682. res = move_window(fs, dp->sect);
  13683. 80055d4: 687b ldr r3, [r7, #4]
  13684. 80055d6: 69db ldr r3, [r3, #28]
  13685. 80055d8: 4619 mov r1, r3
  13686. 80055da: 69f8 ldr r0, [r7, #28]
  13687. 80055dc: f7fe ff30 bl 8004440 <move_window>
  13688. 80055e0: 4603 mov r3, r0
  13689. 80055e2: f887 302f strb.w r3, [r7, #47] ; 0x2f
  13690. if (res == FR_OK) {
  13691. 80055e6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13692. 80055ea: 2b00 cmp r3, #0
  13693. 80055ec: d11b bne.n 8005626 <dir_register+0x1de>
  13694. mem_set(dp->dir, 0, SZDIRE); /* Clean the entry */
  13695. 80055ee: 687b ldr r3, [r7, #4]
  13696. 80055f0: 6a1b ldr r3, [r3, #32]
  13697. 80055f2: 2220 movs r2, #32
  13698. 80055f4: 2100 movs r1, #0
  13699. 80055f6: 4618 mov r0, r3
  13700. 80055f8: f7fe fd20 bl 800403c <mem_set>
  13701. mem_cpy(dp->dir + DIR_Name, dp->fn, 11); /* Put SFN */
  13702. 80055fc: 687b ldr r3, [r7, #4]
  13703. 80055fe: 6a18 ldr r0, [r3, #32]
  13704. 8005600: 687b ldr r3, [r7, #4]
  13705. 8005602: 3324 adds r3, #36 ; 0x24
  13706. 8005604: 220b movs r2, #11
  13707. 8005606: 4619 mov r1, r3
  13708. 8005608: f7fe fcf8 bl 8003ffc <mem_cpy>
  13709. #if _USE_LFN != 0
  13710. dp->dir[DIR_NTres] = dp->fn[NSFLAG] & (NS_BODY | NS_EXT); /* Put NT flag */
  13711. 800560c: 687b ldr r3, [r7, #4]
  13712. 800560e: f893 202f ldrb.w r2, [r3, #47] ; 0x2f
  13713. 8005612: 687b ldr r3, [r7, #4]
  13714. 8005614: 6a1b ldr r3, [r3, #32]
  13715. 8005616: 330c adds r3, #12
  13716. 8005618: f002 0218 and.w r2, r2, #24
  13717. 800561c: b2d2 uxtb r2, r2
  13718. 800561e: 701a strb r2, [r3, #0]
  13719. #endif
  13720. fs->wflag = 1;
  13721. 8005620: 69fb ldr r3, [r7, #28]
  13722. 8005622: 2201 movs r2, #1
  13723. 8005624: 70da strb r2, [r3, #3]
  13724. }
  13725. }
  13726. return res;
  13727. 8005626: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  13728. }
  13729. 800562a: 4618 mov r0, r3
  13730. 800562c: 3730 adds r7, #48 ; 0x30
  13731. 800562e: 46bd mov sp, r7
  13732. 8005630: bd80 pop {r7, pc}
  13733. 8005632: bf00 nop
  13734. 8005634: 4ec4ec4f .word 0x4ec4ec4f
  13735. 08005638 <create_name>:
  13736. static
  13737. FRESULT create_name ( /* FR_OK: successful, FR_INVALID_NAME: could not create */
  13738. DIR* dp, /* Pointer to the directory object */
  13739. const TCHAR** path /* Pointer to pointer to the segment in the path string */
  13740. )
  13741. {
  13742. 8005638: b580 push {r7, lr}
  13743. 800563a: b08a sub sp, #40 ; 0x28
  13744. 800563c: af00 add r7, sp, #0
  13745. 800563e: 6078 str r0, [r7, #4]
  13746. 8005640: 6039 str r1, [r7, #0]
  13747. WCHAR w, *lfn;
  13748. UINT i, ni, si, di;
  13749. const TCHAR *p;
  13750. /* Create LFN in Unicode */
  13751. p = *path; lfn = dp->obj.fs->lfnbuf; si = di = 0;
  13752. 8005642: 683b ldr r3, [r7, #0]
  13753. 8005644: 681b ldr r3, [r3, #0]
  13754. 8005646: 613b str r3, [r7, #16]
  13755. 8005648: 687b ldr r3, [r7, #4]
  13756. 800564a: 681b ldr r3, [r3, #0]
  13757. 800564c: 691b ldr r3, [r3, #16]
  13758. 800564e: 60fb str r3, [r7, #12]
  13759. 8005650: 2300 movs r3, #0
  13760. 8005652: 617b str r3, [r7, #20]
  13761. 8005654: 697b ldr r3, [r7, #20]
  13762. 8005656: 61bb str r3, [r7, #24]
  13763. for (;;) {
  13764. w = p[si++]; /* Get a character */
  13765. 8005658: 69bb ldr r3, [r7, #24]
  13766. 800565a: 1c5a adds r2, r3, #1
  13767. 800565c: 61ba str r2, [r7, #24]
  13768. 800565e: 693a ldr r2, [r7, #16]
  13769. 8005660: 4413 add r3, r2
  13770. 8005662: 781b ldrb r3, [r3, #0]
  13771. 8005664: 84bb strh r3, [r7, #36] ; 0x24
  13772. if (w < ' ') break; /* Break if end of the path name */
  13773. 8005666: 8cbb ldrh r3, [r7, #36] ; 0x24
  13774. 8005668: 2b1f cmp r3, #31
  13775. 800566a: d940 bls.n 80056ee <create_name+0xb6>
  13776. if (w == '/' || w == '\\') { /* Break if a separator is found */
  13777. 800566c: 8cbb ldrh r3, [r7, #36] ; 0x24
  13778. 800566e: 2b2f cmp r3, #47 ; 0x2f
  13779. 8005670: d006 beq.n 8005680 <create_name+0x48>
  13780. 8005672: 8cbb ldrh r3, [r7, #36] ; 0x24
  13781. 8005674: 2b5c cmp r3, #92 ; 0x5c
  13782. 8005676: d110 bne.n 800569a <create_name+0x62>
  13783. while (p[si] == '/' || p[si] == '\\') si++; /* Skip duplicated separator if exist */
  13784. 8005678: e002 b.n 8005680 <create_name+0x48>
  13785. 800567a: 69bb ldr r3, [r7, #24]
  13786. 800567c: 3301 adds r3, #1
  13787. 800567e: 61bb str r3, [r7, #24]
  13788. 8005680: 693a ldr r2, [r7, #16]
  13789. 8005682: 69bb ldr r3, [r7, #24]
  13790. 8005684: 4413 add r3, r2
  13791. 8005686: 781b ldrb r3, [r3, #0]
  13792. 8005688: 2b2f cmp r3, #47 ; 0x2f
  13793. 800568a: d0f6 beq.n 800567a <create_name+0x42>
  13794. 800568c: 693a ldr r2, [r7, #16]
  13795. 800568e: 69bb ldr r3, [r7, #24]
  13796. 8005690: 4413 add r3, r2
  13797. 8005692: 781b ldrb r3, [r3, #0]
  13798. 8005694: 2b5c cmp r3, #92 ; 0x5c
  13799. 8005696: d0f0 beq.n 800567a <create_name+0x42>
  13800. break;
  13801. 8005698: e02a b.n 80056f0 <create_name+0xb8>
  13802. }
  13803. if (di >= _MAX_LFN) return FR_INVALID_NAME; /* Reject too long name */
  13804. 800569a: 697b ldr r3, [r7, #20]
  13805. 800569c: 2bfe cmp r3, #254 ; 0xfe
  13806. 800569e: d901 bls.n 80056a4 <create_name+0x6c>
  13807. 80056a0: 2306 movs r3, #6
  13808. 80056a2: e177 b.n 8005994 <create_name+0x35c>
  13809. #if !_LFN_UNICODE
  13810. w &= 0xFF;
  13811. 80056a4: 8cbb ldrh r3, [r7, #36] ; 0x24
  13812. 80056a6: b2db uxtb r3, r3
  13813. 80056a8: 84bb strh r3, [r7, #36] ; 0x24
  13814. if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
  13815. b = (BYTE)p[si++]; /* Get 2nd byte */
  13816. w = (w << 8) + b; /* Create a DBC */
  13817. if (!IsDBCS2(b)) return FR_INVALID_NAME; /* Reject invalid sequence */
  13818. }
  13819. w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */
  13820. 80056aa: 8cbb ldrh r3, [r7, #36] ; 0x24
  13821. 80056ac: 2101 movs r1, #1
  13822. 80056ae: 4618 mov r0, r3
  13823. 80056b0: f001 fcac bl 800700c <ff_convert>
  13824. 80056b4: 4603 mov r3, r0
  13825. 80056b6: 84bb strh r3, [r7, #36] ; 0x24
  13826. if (!w) return FR_INVALID_NAME; /* Reject invalid code */
  13827. 80056b8: 8cbb ldrh r3, [r7, #36] ; 0x24
  13828. 80056ba: 2b00 cmp r3, #0
  13829. 80056bc: d101 bne.n 80056c2 <create_name+0x8a>
  13830. 80056be: 2306 movs r3, #6
  13831. 80056c0: e168 b.n 8005994 <create_name+0x35c>
  13832. #endif
  13833. if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) return FR_INVALID_NAME; /* Reject illegal characters for LFN */
  13834. 80056c2: 8cbb ldrh r3, [r7, #36] ; 0x24
  13835. 80056c4: 2b7f cmp r3, #127 ; 0x7f
  13836. 80056c6: d809 bhi.n 80056dc <create_name+0xa4>
  13837. 80056c8: 8cbb ldrh r3, [r7, #36] ; 0x24
  13838. 80056ca: 4619 mov r1, r3
  13839. 80056cc: 48b3 ldr r0, [pc, #716] ; (800599c <create_name+0x364>)
  13840. 80056ce: f7fe fcf4 bl 80040ba <chk_chr>
  13841. 80056d2: 4603 mov r3, r0
  13842. 80056d4: 2b00 cmp r3, #0
  13843. 80056d6: d001 beq.n 80056dc <create_name+0xa4>
  13844. 80056d8: 2306 movs r3, #6
  13845. 80056da: e15b b.n 8005994 <create_name+0x35c>
  13846. lfn[di++] = w; /* Store the Unicode character */
  13847. 80056dc: 697b ldr r3, [r7, #20]
  13848. 80056de: 1c5a adds r2, r3, #1
  13849. 80056e0: 617a str r2, [r7, #20]
  13850. 80056e2: 005b lsls r3, r3, #1
  13851. 80056e4: 68fa ldr r2, [r7, #12]
  13852. 80056e6: 4413 add r3, r2
  13853. 80056e8: 8cba ldrh r2, [r7, #36] ; 0x24
  13854. 80056ea: 801a strh r2, [r3, #0]
  13855. w = p[si++]; /* Get a character */
  13856. 80056ec: e7b4 b.n 8005658 <create_name+0x20>
  13857. if (w < ' ') break; /* Break if end of the path name */
  13858. 80056ee: bf00 nop
  13859. }
  13860. *path = &p[si]; /* Return pointer to the next segment */
  13861. 80056f0: 693a ldr r2, [r7, #16]
  13862. 80056f2: 69bb ldr r3, [r7, #24]
  13863. 80056f4: 441a add r2, r3
  13864. 80056f6: 683b ldr r3, [r7, #0]
  13865. 80056f8: 601a str r2, [r3, #0]
  13866. cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */
  13867. 80056fa: 8cbb ldrh r3, [r7, #36] ; 0x24
  13868. 80056fc: 2b1f cmp r3, #31
  13869. 80056fe: d801 bhi.n 8005704 <create_name+0xcc>
  13870. 8005700: 2304 movs r3, #4
  13871. 8005702: e000 b.n 8005706 <create_name+0xce>
  13872. 8005704: 2300 movs r3, #0
  13873. 8005706: f887 3027 strb.w r3, [r7, #39] ; 0x27
  13874. dp->fn[i] = (i < di) ? '.' : ' ';
  13875. dp->fn[i] = cf | NS_DOT; /* This is a dot entry */
  13876. return FR_OK;
  13877. }
  13878. #endif
  13879. while (di) { /* Snip off trailing spaces and dots if exist */
  13880. 800570a: e011 b.n 8005730 <create_name+0xf8>
  13881. w = lfn[di - 1];
  13882. 800570c: 697b ldr r3, [r7, #20]
  13883. 800570e: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000
  13884. 8005712: 3b01 subs r3, #1
  13885. 8005714: 005b lsls r3, r3, #1
  13886. 8005716: 68fa ldr r2, [r7, #12]
  13887. 8005718: 4413 add r3, r2
  13888. 800571a: 881b ldrh r3, [r3, #0]
  13889. 800571c: 84bb strh r3, [r7, #36] ; 0x24
  13890. if (w != ' ' && w != '.') break;
  13891. 800571e: 8cbb ldrh r3, [r7, #36] ; 0x24
  13892. 8005720: 2b20 cmp r3, #32
  13893. 8005722: d002 beq.n 800572a <create_name+0xf2>
  13894. 8005724: 8cbb ldrh r3, [r7, #36] ; 0x24
  13895. 8005726: 2b2e cmp r3, #46 ; 0x2e
  13896. 8005728: d106 bne.n 8005738 <create_name+0x100>
  13897. di--;
  13898. 800572a: 697b ldr r3, [r7, #20]
  13899. 800572c: 3b01 subs r3, #1
  13900. 800572e: 617b str r3, [r7, #20]
  13901. while (di) { /* Snip off trailing spaces and dots if exist */
  13902. 8005730: 697b ldr r3, [r7, #20]
  13903. 8005732: 2b00 cmp r3, #0
  13904. 8005734: d1ea bne.n 800570c <create_name+0xd4>
  13905. 8005736: e000 b.n 800573a <create_name+0x102>
  13906. if (w != ' ' && w != '.') break;
  13907. 8005738: bf00 nop
  13908. }
  13909. lfn[di] = 0; /* LFN is created */
  13910. 800573a: 697b ldr r3, [r7, #20]
  13911. 800573c: 005b lsls r3, r3, #1
  13912. 800573e: 68fa ldr r2, [r7, #12]
  13913. 8005740: 4413 add r3, r2
  13914. 8005742: 2200 movs r2, #0
  13915. 8005744: 801a strh r2, [r3, #0]
  13916. if (di == 0) return FR_INVALID_NAME; /* Reject nul name */
  13917. 8005746: 697b ldr r3, [r7, #20]
  13918. 8005748: 2b00 cmp r3, #0
  13919. 800574a: d101 bne.n 8005750 <create_name+0x118>
  13920. 800574c: 2306 movs r3, #6
  13921. 800574e: e121 b.n 8005994 <create_name+0x35c>
  13922. /* Create SFN in directory form */
  13923. mem_set(dp->fn, ' ', 11);
  13924. 8005750: 687b ldr r3, [r7, #4]
  13925. 8005752: 3324 adds r3, #36 ; 0x24
  13926. 8005754: 220b movs r2, #11
  13927. 8005756: 2120 movs r1, #32
  13928. 8005758: 4618 mov r0, r3
  13929. 800575a: f7fe fc6f bl 800403c <mem_set>
  13930. for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */
  13931. 800575e: 2300 movs r3, #0
  13932. 8005760: 61bb str r3, [r7, #24]
  13933. 8005762: e002 b.n 800576a <create_name+0x132>
  13934. 8005764: 69bb ldr r3, [r7, #24]
  13935. 8005766: 3301 adds r3, #1
  13936. 8005768: 61bb str r3, [r7, #24]
  13937. 800576a: 69bb ldr r3, [r7, #24]
  13938. 800576c: 005b lsls r3, r3, #1
  13939. 800576e: 68fa ldr r2, [r7, #12]
  13940. 8005770: 4413 add r3, r2
  13941. 8005772: 881b ldrh r3, [r3, #0]
  13942. 8005774: 2b20 cmp r3, #32
  13943. 8005776: d0f5 beq.n 8005764 <create_name+0x12c>
  13944. 8005778: 69bb ldr r3, [r7, #24]
  13945. 800577a: 005b lsls r3, r3, #1
  13946. 800577c: 68fa ldr r2, [r7, #12]
  13947. 800577e: 4413 add r3, r2
  13948. 8005780: 881b ldrh r3, [r3, #0]
  13949. 8005782: 2b2e cmp r3, #46 ; 0x2e
  13950. 8005784: d0ee beq.n 8005764 <create_name+0x12c>
  13951. if (si) cf |= NS_LOSS | NS_LFN;
  13952. 8005786: 69bb ldr r3, [r7, #24]
  13953. 8005788: 2b00 cmp r3, #0
  13954. 800578a: d009 beq.n 80057a0 <create_name+0x168>
  13955. 800578c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  13956. 8005790: f043 0303 orr.w r3, r3, #3
  13957. 8005794: f887 3027 strb.w r3, [r7, #39] ; 0x27
  13958. while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */
  13959. 8005798: e002 b.n 80057a0 <create_name+0x168>
  13960. 800579a: 697b ldr r3, [r7, #20]
  13961. 800579c: 3b01 subs r3, #1
  13962. 800579e: 617b str r3, [r7, #20]
  13963. 80057a0: 697b ldr r3, [r7, #20]
  13964. 80057a2: 2b00 cmp r3, #0
  13965. 80057a4: d009 beq.n 80057ba <create_name+0x182>
  13966. 80057a6: 697b ldr r3, [r7, #20]
  13967. 80057a8: f103 4300 add.w r3, r3, #2147483648 ; 0x80000000
  13968. 80057ac: 3b01 subs r3, #1
  13969. 80057ae: 005b lsls r3, r3, #1
  13970. 80057b0: 68fa ldr r2, [r7, #12]
  13971. 80057b2: 4413 add r3, r2
  13972. 80057b4: 881b ldrh r3, [r3, #0]
  13973. 80057b6: 2b2e cmp r3, #46 ; 0x2e
  13974. 80057b8: d1ef bne.n 800579a <create_name+0x162>
  13975. i = b = 0; ni = 8;
  13976. 80057ba: 2300 movs r3, #0
  13977. 80057bc: f887 3026 strb.w r3, [r7, #38] ; 0x26
  13978. 80057c0: 2300 movs r3, #0
  13979. 80057c2: 623b str r3, [r7, #32]
  13980. 80057c4: 2308 movs r3, #8
  13981. 80057c6: 61fb str r3, [r7, #28]
  13982. for (;;) {
  13983. w = lfn[si++]; /* Get an LFN character */
  13984. 80057c8: 69bb ldr r3, [r7, #24]
  13985. 80057ca: 1c5a adds r2, r3, #1
  13986. 80057cc: 61ba str r2, [r7, #24]
  13987. 80057ce: 005b lsls r3, r3, #1
  13988. 80057d0: 68fa ldr r2, [r7, #12]
  13989. 80057d2: 4413 add r3, r2
  13990. 80057d4: 881b ldrh r3, [r3, #0]
  13991. 80057d6: 84bb strh r3, [r7, #36] ; 0x24
  13992. if (!w) break; /* Break on end of the LFN */
  13993. 80057d8: 8cbb ldrh r3, [r7, #36] ; 0x24
  13994. 80057da: 2b00 cmp r3, #0
  13995. 80057dc: f000 8090 beq.w 8005900 <create_name+0x2c8>
  13996. if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */
  13997. 80057e0: 8cbb ldrh r3, [r7, #36] ; 0x24
  13998. 80057e2: 2b20 cmp r3, #32
  13999. 80057e4: d006 beq.n 80057f4 <create_name+0x1bc>
  14000. 80057e6: 8cbb ldrh r3, [r7, #36] ; 0x24
  14001. 80057e8: 2b2e cmp r3, #46 ; 0x2e
  14002. 80057ea: d10a bne.n 8005802 <create_name+0x1ca>
  14003. 80057ec: 69ba ldr r2, [r7, #24]
  14004. 80057ee: 697b ldr r3, [r7, #20]
  14005. 80057f0: 429a cmp r2, r3
  14006. 80057f2: d006 beq.n 8005802 <create_name+0x1ca>
  14007. cf |= NS_LOSS | NS_LFN; continue;
  14008. 80057f4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14009. 80057f8: f043 0303 orr.w r3, r3, #3
  14010. 80057fc: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14011. 8005800: e07d b.n 80058fe <create_name+0x2c6>
  14012. }
  14013. if (i >= ni || si == di) { /* Extension or end of SFN */
  14014. 8005802: 6a3a ldr r2, [r7, #32]
  14015. 8005804: 69fb ldr r3, [r7, #28]
  14016. 8005806: 429a cmp r2, r3
  14017. 8005808: d203 bcs.n 8005812 <create_name+0x1da>
  14018. 800580a: 69ba ldr r2, [r7, #24]
  14019. 800580c: 697b ldr r3, [r7, #20]
  14020. 800580e: 429a cmp r2, r3
  14021. 8005810: d123 bne.n 800585a <create_name+0x222>
  14022. if (ni == 11) { /* Long extension */
  14023. 8005812: 69fb ldr r3, [r7, #28]
  14024. 8005814: 2b0b cmp r3, #11
  14025. 8005816: d106 bne.n 8005826 <create_name+0x1ee>
  14026. cf |= NS_LOSS | NS_LFN; break;
  14027. 8005818: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14028. 800581c: f043 0303 orr.w r3, r3, #3
  14029. 8005820: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14030. 8005824: e06f b.n 8005906 <create_name+0x2ce>
  14031. }
  14032. if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */
  14033. 8005826: 69ba ldr r2, [r7, #24]
  14034. 8005828: 697b ldr r3, [r7, #20]
  14035. 800582a: 429a cmp r2, r3
  14036. 800582c: d005 beq.n 800583a <create_name+0x202>
  14037. 800582e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14038. 8005832: f043 0303 orr.w r3, r3, #3
  14039. 8005836: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14040. if (si > di) break; /* No extension */
  14041. 800583a: 69ba ldr r2, [r7, #24]
  14042. 800583c: 697b ldr r3, [r7, #20]
  14043. 800583e: 429a cmp r2, r3
  14044. 8005840: d860 bhi.n 8005904 <create_name+0x2cc>
  14045. si = di; i = 8; ni = 11; /* Enter extension section */
  14046. 8005842: 697b ldr r3, [r7, #20]
  14047. 8005844: 61bb str r3, [r7, #24]
  14048. 8005846: 2308 movs r3, #8
  14049. 8005848: 623b str r3, [r7, #32]
  14050. 800584a: 230b movs r3, #11
  14051. 800584c: 61fb str r3, [r7, #28]
  14052. b <<= 2; continue;
  14053. 800584e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14054. 8005852: 009b lsls r3, r3, #2
  14055. 8005854: f887 3026 strb.w r3, [r7, #38] ; 0x26
  14056. 8005858: e051 b.n 80058fe <create_name+0x2c6>
  14057. }
  14058. if (w >= 0x80) { /* Non ASCII character */
  14059. 800585a: 8cbb ldrh r3, [r7, #36] ; 0x24
  14060. 800585c: 2b7f cmp r3, #127 ; 0x7f
  14061. 800585e: d914 bls.n 800588a <create_name+0x252>
  14062. #ifdef _EXCVT
  14063. w = ff_convert(w, 0); /* Unicode -> OEM code */
  14064. 8005860: 8cbb ldrh r3, [r7, #36] ; 0x24
  14065. 8005862: 2100 movs r1, #0
  14066. 8005864: 4618 mov r0, r3
  14067. 8005866: f001 fbd1 bl 800700c <ff_convert>
  14068. 800586a: 4603 mov r3, r0
  14069. 800586c: 84bb strh r3, [r7, #36] ; 0x24
  14070. if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */
  14071. 800586e: 8cbb ldrh r3, [r7, #36] ; 0x24
  14072. 8005870: 2b00 cmp r3, #0
  14073. 8005872: d004 beq.n 800587e <create_name+0x246>
  14074. 8005874: 8cbb ldrh r3, [r7, #36] ; 0x24
  14075. 8005876: 3b80 subs r3, #128 ; 0x80
  14076. 8005878: 4a49 ldr r2, [pc, #292] ; (80059a0 <create_name+0x368>)
  14077. 800587a: 5cd3 ldrb r3, [r2, r3]
  14078. 800587c: 84bb strh r3, [r7, #36] ; 0x24
  14079. #else
  14080. w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */
  14081. #endif
  14082. cf |= NS_LFN; /* Force create LFN entry */
  14083. 800587e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14084. 8005882: f043 0302 orr.w r3, r3, #2
  14085. 8005886: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14086. if (i >= ni - 1) {
  14087. cf |= NS_LOSS | NS_LFN; i = ni; continue;
  14088. }
  14089. dp->fn[i++] = (BYTE)(w >> 8);
  14090. } else { /* SBC */
  14091. if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */
  14092. 800588a: 8cbb ldrh r3, [r7, #36] ; 0x24
  14093. 800588c: 2b00 cmp r3, #0
  14094. 800588e: d007 beq.n 80058a0 <create_name+0x268>
  14095. 8005890: 8cbb ldrh r3, [r7, #36] ; 0x24
  14096. 8005892: 4619 mov r1, r3
  14097. 8005894: 4843 ldr r0, [pc, #268] ; (80059a4 <create_name+0x36c>)
  14098. 8005896: f7fe fc10 bl 80040ba <chk_chr>
  14099. 800589a: 4603 mov r3, r0
  14100. 800589c: 2b00 cmp r3, #0
  14101. 800589e: d008 beq.n 80058b2 <create_name+0x27a>
  14102. w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
  14103. 80058a0: 235f movs r3, #95 ; 0x5f
  14104. 80058a2: 84bb strh r3, [r7, #36] ; 0x24
  14105. 80058a4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14106. 80058a8: f043 0303 orr.w r3, r3, #3
  14107. 80058ac: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14108. 80058b0: e01b b.n 80058ea <create_name+0x2b2>
  14109. } else {
  14110. if (IsUpper(w)) { /* ASCII large capital */
  14111. 80058b2: 8cbb ldrh r3, [r7, #36] ; 0x24
  14112. 80058b4: 2b40 cmp r3, #64 ; 0x40
  14113. 80058b6: d909 bls.n 80058cc <create_name+0x294>
  14114. 80058b8: 8cbb ldrh r3, [r7, #36] ; 0x24
  14115. 80058ba: 2b5a cmp r3, #90 ; 0x5a
  14116. 80058bc: d806 bhi.n 80058cc <create_name+0x294>
  14117. b |= 2;
  14118. 80058be: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14119. 80058c2: f043 0302 orr.w r3, r3, #2
  14120. 80058c6: f887 3026 strb.w r3, [r7, #38] ; 0x26
  14121. 80058ca: e00e b.n 80058ea <create_name+0x2b2>
  14122. } else {
  14123. if (IsLower(w)) { /* ASCII small capital */
  14124. 80058cc: 8cbb ldrh r3, [r7, #36] ; 0x24
  14125. 80058ce: 2b60 cmp r3, #96 ; 0x60
  14126. 80058d0: d90b bls.n 80058ea <create_name+0x2b2>
  14127. 80058d2: 8cbb ldrh r3, [r7, #36] ; 0x24
  14128. 80058d4: 2b7a cmp r3, #122 ; 0x7a
  14129. 80058d6: d808 bhi.n 80058ea <create_name+0x2b2>
  14130. b |= 1; w -= 0x20;
  14131. 80058d8: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14132. 80058dc: f043 0301 orr.w r3, r3, #1
  14133. 80058e0: f887 3026 strb.w r3, [r7, #38] ; 0x26
  14134. 80058e4: 8cbb ldrh r3, [r7, #36] ; 0x24
  14135. 80058e6: 3b20 subs r3, #32
  14136. 80058e8: 84bb strh r3, [r7, #36] ; 0x24
  14137. }
  14138. }
  14139. }
  14140. }
  14141. dp->fn[i++] = (BYTE)w;
  14142. 80058ea: 6a3b ldr r3, [r7, #32]
  14143. 80058ec: 1c5a adds r2, r3, #1
  14144. 80058ee: 623a str r2, [r7, #32]
  14145. 80058f0: 8cba ldrh r2, [r7, #36] ; 0x24
  14146. 80058f2: b2d1 uxtb r1, r2
  14147. 80058f4: 687a ldr r2, [r7, #4]
  14148. 80058f6: 4413 add r3, r2
  14149. 80058f8: 460a mov r2, r1
  14150. 80058fa: f883 2024 strb.w r2, [r3, #36] ; 0x24
  14151. w = lfn[si++]; /* Get an LFN character */
  14152. 80058fe: e763 b.n 80057c8 <create_name+0x190>
  14153. if (!w) break; /* Break on end of the LFN */
  14154. 8005900: bf00 nop
  14155. 8005902: e000 b.n 8005906 <create_name+0x2ce>
  14156. if (si > di) break; /* No extension */
  14157. 8005904: bf00 nop
  14158. }
  14159. if (dp->fn[0] == DDEM) dp->fn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */
  14160. 8005906: 687b ldr r3, [r7, #4]
  14161. 8005908: f893 3024 ldrb.w r3, [r3, #36] ; 0x24
  14162. 800590c: 2be5 cmp r3, #229 ; 0xe5
  14163. 800590e: d103 bne.n 8005918 <create_name+0x2e0>
  14164. 8005910: 687b ldr r3, [r7, #4]
  14165. 8005912: 2205 movs r2, #5
  14166. 8005914: f883 2024 strb.w r2, [r3, #36] ; 0x24
  14167. if (ni == 8) b <<= 2;
  14168. 8005918: 69fb ldr r3, [r7, #28]
  14169. 800591a: 2b08 cmp r3, #8
  14170. 800591c: d104 bne.n 8005928 <create_name+0x2f0>
  14171. 800591e: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14172. 8005922: 009b lsls r3, r3, #2
  14173. 8005924: f887 3026 strb.w r3, [r7, #38] ; 0x26
  14174. if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) cf |= NS_LFN; /* Create LFN entry when there are composite capitals */
  14175. 8005928: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14176. 800592c: f003 030c and.w r3, r3, #12
  14177. 8005930: 2b0c cmp r3, #12
  14178. 8005932: d005 beq.n 8005940 <create_name+0x308>
  14179. 8005934: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14180. 8005938: f003 0303 and.w r3, r3, #3
  14181. 800593c: 2b03 cmp r3, #3
  14182. 800593e: d105 bne.n 800594c <create_name+0x314>
  14183. 8005940: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14184. 8005944: f043 0302 orr.w r3, r3, #2
  14185. 8005948: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14186. if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */
  14187. 800594c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14188. 8005950: f003 0302 and.w r3, r3, #2
  14189. 8005954: 2b00 cmp r3, #0
  14190. 8005956: d117 bne.n 8005988 <create_name+0x350>
  14191. if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */
  14192. 8005958: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14193. 800595c: f003 0303 and.w r3, r3, #3
  14194. 8005960: 2b01 cmp r3, #1
  14195. 8005962: d105 bne.n 8005970 <create_name+0x338>
  14196. 8005964: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14197. 8005968: f043 0310 orr.w r3, r3, #16
  14198. 800596c: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14199. if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
  14200. 8005970: f897 3026 ldrb.w r3, [r7, #38] ; 0x26
  14201. 8005974: f003 030c and.w r3, r3, #12
  14202. 8005978: 2b04 cmp r3, #4
  14203. 800597a: d105 bne.n 8005988 <create_name+0x350>
  14204. 800597c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27
  14205. 8005980: f043 0308 orr.w r3, r3, #8
  14206. 8005984: f887 3027 strb.w r3, [r7, #39] ; 0x27
  14207. }
  14208. dp->fn[NSFLAG] = cf; /* SFN is created */
  14209. 8005988: 687b ldr r3, [r7, #4]
  14210. 800598a: f897 2027 ldrb.w r2, [r7, #39] ; 0x27
  14211. 800598e: f883 202f strb.w r2, [r3, #47] ; 0x2f
  14212. return FR_OK;
  14213. 8005992: 2300 movs r3, #0
  14214. if (sfn[0] == DDEM) sfn[0] = RDDEM; /* If the first character collides with DDEM, replace it with RDDEM */
  14215. sfn[NSFLAG] = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of the path */
  14216. return FR_OK;
  14217. #endif /* _USE_LFN != 0 */
  14218. }
  14219. 8005994: 4618 mov r0, r3
  14220. 8005996: 3728 adds r7, #40 ; 0x28
  14221. 8005998: 46bd mov sp, r7
  14222. 800599a: bd80 pop {r7, pc}
  14223. 800599c: 08007b18 .word 0x08007b18
  14224. 80059a0: 08007b84 .word 0x08007b84
  14225. 80059a4: 08007b24 .word 0x08007b24
  14226. 080059a8 <follow_path>:
  14227. static
  14228. FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
  14229. DIR* dp, /* Directory object to return last directory and found object */
  14230. const TCHAR* path /* Full-path string to find a file or directory */
  14231. )
  14232. {
  14233. 80059a8: b580 push {r7, lr}
  14234. 80059aa: b086 sub sp, #24
  14235. 80059ac: af00 add r7, sp, #0
  14236. 80059ae: 6078 str r0, [r7, #4]
  14237. 80059b0: 6039 str r1, [r7, #0]
  14238. FRESULT res;
  14239. BYTE ns;
  14240. _FDID *obj = &dp->obj;
  14241. 80059b2: 687b ldr r3, [r7, #4]
  14242. 80059b4: 613b str r3, [r7, #16]
  14243. FATFS *fs = obj->fs;
  14244. 80059b6: 693b ldr r3, [r7, #16]
  14245. 80059b8: 681b ldr r3, [r3, #0]
  14246. 80059ba: 60fb str r3, [r7, #12]
  14247. if (*path != '/' && *path != '\\') { /* Without heading separator */
  14248. obj->sclust = fs->cdir; /* Start from current directory */
  14249. } else
  14250. #endif
  14251. { /* With heading separator */
  14252. while (*path == '/' || *path == '\\') path++; /* Strip heading separator */
  14253. 80059bc: e002 b.n 80059c4 <follow_path+0x1c>
  14254. 80059be: 683b ldr r3, [r7, #0]
  14255. 80059c0: 3301 adds r3, #1
  14256. 80059c2: 603b str r3, [r7, #0]
  14257. 80059c4: 683b ldr r3, [r7, #0]
  14258. 80059c6: 781b ldrb r3, [r3, #0]
  14259. 80059c8: 2b2f cmp r3, #47 ; 0x2f
  14260. 80059ca: d0f8 beq.n 80059be <follow_path+0x16>
  14261. 80059cc: 683b ldr r3, [r7, #0]
  14262. 80059ce: 781b ldrb r3, [r3, #0]
  14263. 80059d0: 2b5c cmp r3, #92 ; 0x5c
  14264. 80059d2: d0f4 beq.n 80059be <follow_path+0x16>
  14265. obj->sclust = 0; /* Start from root directory */
  14266. 80059d4: 693b ldr r3, [r7, #16]
  14267. 80059d6: 2200 movs r2, #0
  14268. 80059d8: 609a str r2, [r3, #8]
  14269. obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
  14270. }
  14271. #endif
  14272. #endif
  14273. if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */
  14274. 80059da: 683b ldr r3, [r7, #0]
  14275. 80059dc: 781b ldrb r3, [r3, #0]
  14276. 80059de: 2b1f cmp r3, #31
  14277. 80059e0: d80a bhi.n 80059f8 <follow_path+0x50>
  14278. dp->fn[NSFLAG] = NS_NONAME;
  14279. 80059e2: 687b ldr r3, [r7, #4]
  14280. 80059e4: 2280 movs r2, #128 ; 0x80
  14281. 80059e6: f883 202f strb.w r2, [r3, #47] ; 0x2f
  14282. res = dir_sdi(dp, 0);
  14283. 80059ea: 2100 movs r1, #0
  14284. 80059ec: 6878 ldr r0, [r7, #4]
  14285. 80059ee: f7ff f8fe bl 8004bee <dir_sdi>
  14286. 80059f2: 4603 mov r3, r0
  14287. 80059f4: 75fb strb r3, [r7, #23]
  14288. 80059f6: e048 b.n 8005a8a <follow_path+0xe2>
  14289. } else { /* Follow path */
  14290. for (;;) {
  14291. res = create_name(dp, &path); /* Get a segment name of the path */
  14292. 80059f8: 463b mov r3, r7
  14293. 80059fa: 4619 mov r1, r3
  14294. 80059fc: 6878 ldr r0, [r7, #4]
  14295. 80059fe: f7ff fe1b bl 8005638 <create_name>
  14296. 8005a02: 4603 mov r3, r0
  14297. 8005a04: 75fb strb r3, [r7, #23]
  14298. if (res != FR_OK) break;
  14299. 8005a06: 7dfb ldrb r3, [r7, #23]
  14300. 8005a08: 2b00 cmp r3, #0
  14301. 8005a0a: d139 bne.n 8005a80 <follow_path+0xd8>
  14302. res = dir_find(dp); /* Find an object with the segment name */
  14303. 8005a0c: 6878 ldr r0, [r7, #4]
  14304. 8005a0e: f7ff fc5a bl 80052c6 <dir_find>
  14305. 8005a12: 4603 mov r3, r0
  14306. 8005a14: 75fb strb r3, [r7, #23]
  14307. ns = dp->fn[NSFLAG];
  14308. 8005a16: 687b ldr r3, [r7, #4]
  14309. 8005a18: f893 302f ldrb.w r3, [r3, #47] ; 0x2f
  14310. 8005a1c: 72fb strb r3, [r7, #11]
  14311. if (res != FR_OK) { /* Failed to find the object */
  14312. 8005a1e: 7dfb ldrb r3, [r7, #23]
  14313. 8005a20: 2b00 cmp r3, #0
  14314. 8005a22: d00a beq.n 8005a3a <follow_path+0x92>
  14315. if (res == FR_NO_FILE) { /* Object is not found */
  14316. 8005a24: 7dfb ldrb r3, [r7, #23]
  14317. 8005a26: 2b04 cmp r3, #4
  14318. 8005a28: d12c bne.n 8005a84 <follow_path+0xdc>
  14319. if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, stay there */
  14320. if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */
  14321. dp->fn[NSFLAG] = NS_NONAME;
  14322. res = FR_OK;
  14323. } else { /* Could not find the object */
  14324. if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */
  14325. 8005a2a: 7afb ldrb r3, [r7, #11]
  14326. 8005a2c: f003 0304 and.w r3, r3, #4
  14327. 8005a30: 2b00 cmp r3, #0
  14328. 8005a32: d127 bne.n 8005a84 <follow_path+0xdc>
  14329. 8005a34: 2305 movs r3, #5
  14330. 8005a36: 75fb strb r3, [r7, #23]
  14331. }
  14332. }
  14333. break;
  14334. 8005a38: e024 b.n 8005a84 <follow_path+0xdc>
  14335. }
  14336. if (ns & NS_LAST) break; /* Last segment matched. Function completed. */
  14337. 8005a3a: 7afb ldrb r3, [r7, #11]
  14338. 8005a3c: f003 0304 and.w r3, r3, #4
  14339. 8005a40: 2b00 cmp r3, #0
  14340. 8005a42: d121 bne.n 8005a88 <follow_path+0xe0>
  14341. /* Get into the sub-directory */
  14342. if (!(obj->attr & AM_DIR)) { /* It is not a sub-directory and cannot follow */
  14343. 8005a44: 693b ldr r3, [r7, #16]
  14344. 8005a46: 799b ldrb r3, [r3, #6]
  14345. 8005a48: f003 0310 and.w r3, r3, #16
  14346. 8005a4c: 2b00 cmp r3, #0
  14347. 8005a4e: d102 bne.n 8005a56 <follow_path+0xae>
  14348. res = FR_NO_PATH; break;
  14349. 8005a50: 2305 movs r3, #5
  14350. 8005a52: 75fb strb r3, [r7, #23]
  14351. 8005a54: e019 b.n 8005a8a <follow_path+0xe2>
  14352. obj->stat = fs->dirbuf[XDIR_GenFlags] & 2;
  14353. obj->objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
  14354. } else
  14355. #endif
  14356. {
  14357. obj->sclust = ld_clust(fs, fs->win + dp->dptr % SS(fs)); /* Open next directory */
  14358. 8005a56: 68fb ldr r3, [r7, #12]
  14359. 8005a58: f103 0138 add.w r1, r3, #56 ; 0x38
  14360. 8005a5c: 687b ldr r3, [r7, #4]
  14361. 8005a5e: 695b ldr r3, [r3, #20]
  14362. 8005a60: 68fa ldr r2, [r7, #12]
  14363. 8005a62: 8992 ldrh r2, [r2, #12]
  14364. 8005a64: fbb3 f0f2 udiv r0, r3, r2
  14365. 8005a68: fb02 f200 mul.w r2, r2, r0
  14366. 8005a6c: 1a9b subs r3, r3, r2
  14367. 8005a6e: 440b add r3, r1
  14368. 8005a70: 4619 mov r1, r3
  14369. 8005a72: 68f8 ldr r0, [r7, #12]
  14370. 8005a74: f7ff fa61 bl 8004f3a <ld_clust>
  14371. 8005a78: 4602 mov r2, r0
  14372. 8005a7a: 693b ldr r3, [r7, #16]
  14373. 8005a7c: 609a str r2, [r3, #8]
  14374. res = create_name(dp, &path); /* Get a segment name of the path */
  14375. 8005a7e: e7bb b.n 80059f8 <follow_path+0x50>
  14376. if (res != FR_OK) break;
  14377. 8005a80: bf00 nop
  14378. 8005a82: e002 b.n 8005a8a <follow_path+0xe2>
  14379. break;
  14380. 8005a84: bf00 nop
  14381. 8005a86: e000 b.n 8005a8a <follow_path+0xe2>
  14382. if (ns & NS_LAST) break; /* Last segment matched. Function completed. */
  14383. 8005a88: bf00 nop
  14384. }
  14385. }
  14386. }
  14387. return res;
  14388. 8005a8a: 7dfb ldrb r3, [r7, #23]
  14389. }
  14390. 8005a8c: 4618 mov r0, r3
  14391. 8005a8e: 3718 adds r7, #24
  14392. 8005a90: 46bd mov sp, r7
  14393. 8005a92: bd80 pop {r7, pc}
  14394. 08005a94 <get_ldnumber>:
  14395. static
  14396. int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */
  14397. const TCHAR** path /* Pointer to pointer to the path name */
  14398. )
  14399. {
  14400. 8005a94: b480 push {r7}
  14401. 8005a96: b087 sub sp, #28
  14402. 8005a98: af00 add r7, sp, #0
  14403. 8005a9a: 6078 str r0, [r7, #4]
  14404. const TCHAR *tp, *tt;
  14405. UINT i;
  14406. int vol = -1;
  14407. 8005a9c: f04f 33ff mov.w r3, #4294967295
  14408. 8005aa0: 613b str r3, [r7, #16]
  14409. char c;
  14410. TCHAR tc;
  14411. #endif
  14412. if (*path) { /* If the pointer is not a null */
  14413. 8005aa2: 687b ldr r3, [r7, #4]
  14414. 8005aa4: 681b ldr r3, [r3, #0]
  14415. 8005aa6: 2b00 cmp r3, #0
  14416. 8005aa8: d031 beq.n 8005b0e <get_ldnumber+0x7a>
  14417. for (tt = *path; (UINT)*tt >= (_USE_LFN ? ' ' : '!') && *tt != ':'; tt++) ; /* Find ':' in the path */
  14418. 8005aaa: 687b ldr r3, [r7, #4]
  14419. 8005aac: 681b ldr r3, [r3, #0]
  14420. 8005aae: 617b str r3, [r7, #20]
  14421. 8005ab0: e002 b.n 8005ab8 <get_ldnumber+0x24>
  14422. 8005ab2: 697b ldr r3, [r7, #20]
  14423. 8005ab4: 3301 adds r3, #1
  14424. 8005ab6: 617b str r3, [r7, #20]
  14425. 8005ab8: 697b ldr r3, [r7, #20]
  14426. 8005aba: 781b ldrb r3, [r3, #0]
  14427. 8005abc: 2b1f cmp r3, #31
  14428. 8005abe: d903 bls.n 8005ac8 <get_ldnumber+0x34>
  14429. 8005ac0: 697b ldr r3, [r7, #20]
  14430. 8005ac2: 781b ldrb r3, [r3, #0]
  14431. 8005ac4: 2b3a cmp r3, #58 ; 0x3a
  14432. 8005ac6: d1f4 bne.n 8005ab2 <get_ldnumber+0x1e>
  14433. if (*tt == ':') { /* If a ':' is exist in the path name */
  14434. 8005ac8: 697b ldr r3, [r7, #20]
  14435. 8005aca: 781b ldrb r3, [r3, #0]
  14436. 8005acc: 2b3a cmp r3, #58 ; 0x3a
  14437. 8005ace: d11c bne.n 8005b0a <get_ldnumber+0x76>
  14438. tp = *path;
  14439. 8005ad0: 687b ldr r3, [r7, #4]
  14440. 8005ad2: 681b ldr r3, [r3, #0]
  14441. 8005ad4: 60fb str r3, [r7, #12]
  14442. i = *tp++ - '0';
  14443. 8005ad6: 68fb ldr r3, [r7, #12]
  14444. 8005ad8: 1c5a adds r2, r3, #1
  14445. 8005ada: 60fa str r2, [r7, #12]
  14446. 8005adc: 781b ldrb r3, [r3, #0]
  14447. 8005ade: 3b30 subs r3, #48 ; 0x30
  14448. 8005ae0: 60bb str r3, [r7, #8]
  14449. if (i < 10 && tp == tt) { /* Is there a numeric drive id? */
  14450. 8005ae2: 68bb ldr r3, [r7, #8]
  14451. 8005ae4: 2b09 cmp r3, #9
  14452. 8005ae6: d80e bhi.n 8005b06 <get_ldnumber+0x72>
  14453. 8005ae8: 68fa ldr r2, [r7, #12]
  14454. 8005aea: 697b ldr r3, [r7, #20]
  14455. 8005aec: 429a cmp r2, r3
  14456. 8005aee: d10a bne.n 8005b06 <get_ldnumber+0x72>
  14457. if (i < _VOLUMES) { /* If a drive id is found, get the value and strip it */
  14458. 8005af0: 68bb ldr r3, [r7, #8]
  14459. 8005af2: 2b00 cmp r3, #0
  14460. 8005af4: d107 bne.n 8005b06 <get_ldnumber+0x72>
  14461. vol = (int)i;
  14462. 8005af6: 68bb ldr r3, [r7, #8]
  14463. 8005af8: 613b str r3, [r7, #16]
  14464. *path = ++tt;
  14465. 8005afa: 697b ldr r3, [r7, #20]
  14466. 8005afc: 3301 adds r3, #1
  14467. 8005afe: 617b str r3, [r7, #20]
  14468. 8005b00: 687b ldr r3, [r7, #4]
  14469. 8005b02: 697a ldr r2, [r7, #20]
  14470. 8005b04: 601a str r2, [r3, #0]
  14471. vol = (int)i;
  14472. *path = tt;
  14473. }
  14474. }
  14475. #endif
  14476. return vol;
  14477. 8005b06: 693b ldr r3, [r7, #16]
  14478. 8005b08: e002 b.n 8005b10 <get_ldnumber+0x7c>
  14479. }
  14480. #if _FS_RPATH != 0 && _VOLUMES >= 2
  14481. vol = CurrVol; /* Current drive */
  14482. #else
  14483. vol = 0; /* Drive 0 */
  14484. 8005b0a: 2300 movs r3, #0
  14485. 8005b0c: 613b str r3, [r7, #16]
  14486. #endif
  14487. }
  14488. return vol;
  14489. 8005b0e: 693b ldr r3, [r7, #16]
  14490. }
  14491. 8005b10: 4618 mov r0, r3
  14492. 8005b12: 371c adds r7, #28
  14493. 8005b14: 46bd mov sp, r7
  14494. 8005b16: bc80 pop {r7}
  14495. 8005b18: 4770 bx lr
  14496. ...
  14497. 08005b1c <check_fs>:
  14498. static
  14499. BYTE check_fs ( /* 0:FAT, 1:exFAT, 2:Valid BS but not FAT, 3:Not a BS, 4:Disk error */
  14500. FATFS* fs, /* File system object */
  14501. DWORD sect /* Sector# (lba) to load and check if it is an FAT-VBR or not */
  14502. )
  14503. {
  14504. 8005b1c: b580 push {r7, lr}
  14505. 8005b1e: b082 sub sp, #8
  14506. 8005b20: af00 add r7, sp, #0
  14507. 8005b22: 6078 str r0, [r7, #4]
  14508. 8005b24: 6039 str r1, [r7, #0]
  14509. fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */
  14510. 8005b26: 687b ldr r3, [r7, #4]
  14511. 8005b28: 2200 movs r2, #0
  14512. 8005b2a: 70da strb r2, [r3, #3]
  14513. 8005b2c: 687b ldr r3, [r7, #4]
  14514. 8005b2e: f04f 32ff mov.w r2, #4294967295
  14515. 8005b32: 635a str r2, [r3, #52] ; 0x34
  14516. if (move_window(fs, sect) != FR_OK) return 4; /* Load boot record */
  14517. 8005b34: 6839 ldr r1, [r7, #0]
  14518. 8005b36: 6878 ldr r0, [r7, #4]
  14519. 8005b38: f7fe fc82 bl 8004440 <move_window>
  14520. 8005b3c: 4603 mov r3, r0
  14521. 8005b3e: 2b00 cmp r3, #0
  14522. 8005b40: d001 beq.n 8005b46 <check_fs+0x2a>
  14523. 8005b42: 2304 movs r3, #4
  14524. 8005b44: e038 b.n 8005bb8 <check_fs+0x9c>
  14525. if (ld_word(fs->win + BS_55AA) != 0xAA55) return 3; /* Check boot record signature (always placed here even if the sector size is >512) */
  14526. 8005b46: 687b ldr r3, [r7, #4]
  14527. 8005b48: 3338 adds r3, #56 ; 0x38
  14528. 8005b4a: f503 73ff add.w r3, r3, #510 ; 0x1fe
  14529. 8005b4e: 4618 mov r0, r3
  14530. 8005b50: f7fe f9d6 bl 8003f00 <ld_word>
  14531. 8005b54: 4603 mov r3, r0
  14532. 8005b56: 461a mov r2, r3
  14533. 8005b58: f64a 2355 movw r3, #43605 ; 0xaa55
  14534. 8005b5c: 429a cmp r2, r3
  14535. 8005b5e: d001 beq.n 8005b64 <check_fs+0x48>
  14536. 8005b60: 2303 movs r3, #3
  14537. 8005b62: e029 b.n 8005bb8 <check_fs+0x9c>
  14538. if (fs->win[BS_JmpBoot] == 0xE9 || (fs->win[BS_JmpBoot] == 0xEB && fs->win[BS_JmpBoot + 2] == 0x90)) {
  14539. 8005b64: 687b ldr r3, [r7, #4]
  14540. 8005b66: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
  14541. 8005b6a: 2be9 cmp r3, #233 ; 0xe9
  14542. 8005b6c: d009 beq.n 8005b82 <check_fs+0x66>
  14543. 8005b6e: 687b ldr r3, [r7, #4]
  14544. 8005b70: f893 3038 ldrb.w r3, [r3, #56] ; 0x38
  14545. 8005b74: 2beb cmp r3, #235 ; 0xeb
  14546. 8005b76: d11e bne.n 8005bb6 <check_fs+0x9a>
  14547. 8005b78: 687b ldr r3, [r7, #4]
  14548. 8005b7a: f893 303a ldrb.w r3, [r3, #58] ; 0x3a
  14549. 8005b7e: 2b90 cmp r3, #144 ; 0x90
  14550. 8005b80: d119 bne.n 8005bb6 <check_fs+0x9a>
  14551. if ((ld_dword(fs->win + BS_FilSysType) & 0xFFFFFF) == 0x544146) return 0; /* Check "FAT" string */
  14552. 8005b82: 687b ldr r3, [r7, #4]
  14553. 8005b84: 3338 adds r3, #56 ; 0x38
  14554. 8005b86: 3336 adds r3, #54 ; 0x36
  14555. 8005b88: 4618 mov r0, r3
  14556. 8005b8a: f7fe f9d0 bl 8003f2e <ld_dword>
  14557. 8005b8e: 4603 mov r3, r0
  14558. 8005b90: f023 437f bic.w r3, r3, #4278190080 ; 0xff000000
  14559. 8005b94: 4a0a ldr r2, [pc, #40] ; (8005bc0 <check_fs+0xa4>)
  14560. 8005b96: 4293 cmp r3, r2
  14561. 8005b98: d101 bne.n 8005b9e <check_fs+0x82>
  14562. 8005b9a: 2300 movs r3, #0
  14563. 8005b9c: e00c b.n 8005bb8 <check_fs+0x9c>
  14564. if (ld_dword(fs->win + BS_FilSysType32) == 0x33544146) return 0; /* Check "FAT3" string */
  14565. 8005b9e: 687b ldr r3, [r7, #4]
  14566. 8005ba0: 3338 adds r3, #56 ; 0x38
  14567. 8005ba2: 3352 adds r3, #82 ; 0x52
  14568. 8005ba4: 4618 mov r0, r3
  14569. 8005ba6: f7fe f9c2 bl 8003f2e <ld_dword>
  14570. 8005baa: 4602 mov r2, r0
  14571. 8005bac: 4b05 ldr r3, [pc, #20] ; (8005bc4 <check_fs+0xa8>)
  14572. 8005bae: 429a cmp r2, r3
  14573. 8005bb0: d101 bne.n 8005bb6 <check_fs+0x9a>
  14574. 8005bb2: 2300 movs r3, #0
  14575. 8005bb4: e000 b.n 8005bb8 <check_fs+0x9c>
  14576. }
  14577. #if _FS_EXFAT
  14578. if (!mem_cmp(fs->win + BS_JmpBoot, "\xEB\x76\x90" "EXFAT ", 11)) return 1;
  14579. #endif
  14580. return 2;
  14581. 8005bb6: 2302 movs r3, #2
  14582. }
  14583. 8005bb8: 4618 mov r0, r3
  14584. 8005bba: 3708 adds r7, #8
  14585. 8005bbc: 46bd mov sp, r7
  14586. 8005bbe: bd80 pop {r7, pc}
  14587. 8005bc0: 00544146 .word 0x00544146
  14588. 8005bc4: 33544146 .word 0x33544146
  14589. 08005bc8 <find_volume>:
  14590. FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */
  14591. const TCHAR** path, /* Pointer to pointer to the path name (drive number) */
  14592. FATFS** rfs, /* Pointer to pointer to the found file system object */
  14593. BYTE mode /* !=0: Check write protection for write access */
  14594. )
  14595. {
  14596. 8005bc8: b580 push {r7, lr}
  14597. 8005bca: b096 sub sp, #88 ; 0x58
  14598. 8005bcc: af00 add r7, sp, #0
  14599. 8005bce: 60f8 str r0, [r7, #12]
  14600. 8005bd0: 60b9 str r1, [r7, #8]
  14601. 8005bd2: 4613 mov r3, r2
  14602. 8005bd4: 71fb strb r3, [r7, #7]
  14603. FATFS *fs;
  14604. UINT i;
  14605. /* Get logical drive number */
  14606. *rfs = 0;
  14607. 8005bd6: 68bb ldr r3, [r7, #8]
  14608. 8005bd8: 2200 movs r2, #0
  14609. 8005bda: 601a str r2, [r3, #0]
  14610. vol = get_ldnumber(path);
  14611. 8005bdc: 68f8 ldr r0, [r7, #12]
  14612. 8005bde: f7ff ff59 bl 8005a94 <get_ldnumber>
  14613. 8005be2: 63f8 str r0, [r7, #60] ; 0x3c
  14614. if (vol < 0) return FR_INVALID_DRIVE;
  14615. 8005be4: 6bfb ldr r3, [r7, #60] ; 0x3c
  14616. 8005be6: 2b00 cmp r3, #0
  14617. 8005be8: da01 bge.n 8005bee <find_volume+0x26>
  14618. 8005bea: 230b movs r3, #11
  14619. 8005bec: e268 b.n 80060c0 <find_volume+0x4f8>
  14620. /* Check if the file system object is valid or not */
  14621. fs = FatFs[vol]; /* Get pointer to the file system object */
  14622. 8005bee: 4ab0 ldr r2, [pc, #704] ; (8005eb0 <find_volume+0x2e8>)
  14623. 8005bf0: 6bfb ldr r3, [r7, #60] ; 0x3c
  14624. 8005bf2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
  14625. 8005bf6: 63bb str r3, [r7, #56] ; 0x38
  14626. if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */
  14627. 8005bf8: 6bbb ldr r3, [r7, #56] ; 0x38
  14628. 8005bfa: 2b00 cmp r3, #0
  14629. 8005bfc: d101 bne.n 8005c02 <find_volume+0x3a>
  14630. 8005bfe: 230c movs r3, #12
  14631. 8005c00: e25e b.n 80060c0 <find_volume+0x4f8>
  14632. ENTER_FF(fs); /* Lock the volume */
  14633. *rfs = fs; /* Return pointer to the file system object */
  14634. 8005c02: 68bb ldr r3, [r7, #8]
  14635. 8005c04: 6bba ldr r2, [r7, #56] ; 0x38
  14636. 8005c06: 601a str r2, [r3, #0]
  14637. mode &= (BYTE)~FA_READ; /* Desired access mode, write access or not */
  14638. 8005c08: 79fb ldrb r3, [r7, #7]
  14639. 8005c0a: f023 0301 bic.w r3, r3, #1
  14640. 8005c0e: 71fb strb r3, [r7, #7]
  14641. if (fs->fs_type) { /* If the volume has been mounted */
  14642. 8005c10: 6bbb ldr r3, [r7, #56] ; 0x38
  14643. 8005c12: 781b ldrb r3, [r3, #0]
  14644. 8005c14: 2b00 cmp r3, #0
  14645. 8005c16: d01a beq.n 8005c4e <find_volume+0x86>
  14646. stat = disk_status(fs->drv);
  14647. 8005c18: 6bbb ldr r3, [r7, #56] ; 0x38
  14648. 8005c1a: 785b ldrb r3, [r3, #1]
  14649. 8005c1c: 4618 mov r0, r3
  14650. 8005c1e: f7fe f8d1 bl 8003dc4 <disk_status>
  14651. 8005c22: 4603 mov r3, r0
  14652. 8005c24: f887 3037 strb.w r3, [r7, #55] ; 0x37
  14653. if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */
  14654. 8005c28: f897 3037 ldrb.w r3, [r7, #55] ; 0x37
  14655. 8005c2c: f003 0301 and.w r3, r3, #1
  14656. 8005c30: 2b00 cmp r3, #0
  14657. 8005c32: d10c bne.n 8005c4e <find_volume+0x86>
  14658. if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */
  14659. 8005c34: 79fb ldrb r3, [r7, #7]
  14660. 8005c36: 2b00 cmp r3, #0
  14661. 8005c38: d007 beq.n 8005c4a <find_volume+0x82>
  14662. 8005c3a: f897 3037 ldrb.w r3, [r7, #55] ; 0x37
  14663. 8005c3e: f003 0304 and.w r3, r3, #4
  14664. 8005c42: 2b00 cmp r3, #0
  14665. 8005c44: d001 beq.n 8005c4a <find_volume+0x82>
  14666. return FR_WRITE_PROTECTED;
  14667. 8005c46: 230a movs r3, #10
  14668. 8005c48: e23a b.n 80060c0 <find_volume+0x4f8>
  14669. }
  14670. return FR_OK; /* The file system object is valid */
  14671. 8005c4a: 2300 movs r3, #0
  14672. 8005c4c: e238 b.n 80060c0 <find_volume+0x4f8>
  14673. }
  14674. /* The file system object is not valid. */
  14675. /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
  14676. fs->fs_type = 0; /* Clear the file system object */
  14677. 8005c4e: 6bbb ldr r3, [r7, #56] ; 0x38
  14678. 8005c50: 2200 movs r2, #0
  14679. 8005c52: 701a strb r2, [r3, #0]
  14680. fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */
  14681. 8005c54: 6bfb ldr r3, [r7, #60] ; 0x3c
  14682. 8005c56: b2da uxtb r2, r3
  14683. 8005c58: 6bbb ldr r3, [r7, #56] ; 0x38
  14684. 8005c5a: 705a strb r2, [r3, #1]
  14685. stat = disk_initialize(fs->drv); /* Initialize the physical drive */
  14686. 8005c5c: 6bbb ldr r3, [r7, #56] ; 0x38
  14687. 8005c5e: 785b ldrb r3, [r3, #1]
  14688. 8005c60: 4618 mov r0, r3
  14689. 8005c62: f7fe f8c9 bl 8003df8 <disk_initialize>
  14690. 8005c66: 4603 mov r3, r0
  14691. 8005c68: f887 3037 strb.w r3, [r7, #55] ; 0x37
  14692. if (stat & STA_NOINIT) { /* Check if the initialization succeeded */
  14693. 8005c6c: f897 3037 ldrb.w r3, [r7, #55] ; 0x37
  14694. 8005c70: f003 0301 and.w r3, r3, #1
  14695. 8005c74: 2b00 cmp r3, #0
  14696. 8005c76: d001 beq.n 8005c7c <find_volume+0xb4>
  14697. return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */
  14698. 8005c78: 2303 movs r3, #3
  14699. 8005c7a: e221 b.n 80060c0 <find_volume+0x4f8>
  14700. }
  14701. if (!_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */
  14702. 8005c7c: 79fb ldrb r3, [r7, #7]
  14703. 8005c7e: 2b00 cmp r3, #0
  14704. 8005c80: d007 beq.n 8005c92 <find_volume+0xca>
  14705. 8005c82: f897 3037 ldrb.w r3, [r7, #55] ; 0x37
  14706. 8005c86: f003 0304 and.w r3, r3, #4
  14707. 8005c8a: 2b00 cmp r3, #0
  14708. 8005c8c: d001 beq.n 8005c92 <find_volume+0xca>
  14709. return FR_WRITE_PROTECTED;
  14710. 8005c8e: 230a movs r3, #10
  14711. 8005c90: e216 b.n 80060c0 <find_volume+0x4f8>
  14712. }
  14713. #if _MAX_SS != _MIN_SS /* Get sector size (multiple sector size cfg only) */
  14714. if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK) return FR_DISK_ERR;
  14715. 8005c92: 6bbb ldr r3, [r7, #56] ; 0x38
  14716. 8005c94: 7858 ldrb r0, [r3, #1]
  14717. 8005c96: 6bbb ldr r3, [r7, #56] ; 0x38
  14718. 8005c98: 330c adds r3, #12
  14719. 8005c9a: 461a mov r2, r3
  14720. 8005c9c: 2102 movs r1, #2
  14721. 8005c9e: f7fe f911 bl 8003ec4 <disk_ioctl>
  14722. 8005ca2: 4603 mov r3, r0
  14723. 8005ca4: 2b00 cmp r3, #0
  14724. 8005ca6: d001 beq.n 8005cac <find_volume+0xe4>
  14725. 8005ca8: 2301 movs r3, #1
  14726. 8005caa: e209 b.n 80060c0 <find_volume+0x4f8>
  14727. if (SS(fs) > _MAX_SS || SS(fs) < _MIN_SS || (SS(fs) & (SS(fs) - 1))) return FR_DISK_ERR;
  14728. 8005cac: 6bbb ldr r3, [r7, #56] ; 0x38
  14729. 8005cae: 899b ldrh r3, [r3, #12]
  14730. 8005cb0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  14731. 8005cb4: d80d bhi.n 8005cd2 <find_volume+0x10a>
  14732. 8005cb6: 6bbb ldr r3, [r7, #56] ; 0x38
  14733. 8005cb8: 899b ldrh r3, [r3, #12]
  14734. 8005cba: f5b3 7f00 cmp.w r3, #512 ; 0x200
  14735. 8005cbe: d308 bcc.n 8005cd2 <find_volume+0x10a>
  14736. 8005cc0: 6bbb ldr r3, [r7, #56] ; 0x38
  14737. 8005cc2: 899b ldrh r3, [r3, #12]
  14738. 8005cc4: 461a mov r2, r3
  14739. 8005cc6: 6bbb ldr r3, [r7, #56] ; 0x38
  14740. 8005cc8: 899b ldrh r3, [r3, #12]
  14741. 8005cca: 3b01 subs r3, #1
  14742. 8005ccc: 4013 ands r3, r2
  14743. 8005cce: 2b00 cmp r3, #0
  14744. 8005cd0: d001 beq.n 8005cd6 <find_volume+0x10e>
  14745. 8005cd2: 2301 movs r3, #1
  14746. 8005cd4: e1f4 b.n 80060c0 <find_volume+0x4f8>
  14747. #endif
  14748. /* Find an FAT partition on the drive. Supports only generic partitioning rules, FDISK and SFD. */
  14749. bsect = 0;
  14750. 8005cd6: 2300 movs r3, #0
  14751. 8005cd8: 653b str r3, [r7, #80] ; 0x50
  14752. fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT-VBR as SFD */
  14753. 8005cda: 6d39 ldr r1, [r7, #80] ; 0x50
  14754. 8005cdc: 6bb8 ldr r0, [r7, #56] ; 0x38
  14755. 8005cde: f7ff ff1d bl 8005b1c <check_fs>
  14756. 8005ce2: 4603 mov r3, r0
  14757. 8005ce4: f887 3057 strb.w r3, [r7, #87] ; 0x57
  14758. if (fmt == 2 || (fmt < 2 && LD2PT(vol) != 0)) { /* Not an FAT-VBR or forced partition number */
  14759. 8005ce8: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  14760. 8005cec: 2b02 cmp r3, #2
  14761. 8005cee: d14b bne.n 8005d88 <find_volume+0x1c0>
  14762. for (i = 0; i < 4; i++) { /* Get partition offset */
  14763. 8005cf0: 2300 movs r3, #0
  14764. 8005cf2: 643b str r3, [r7, #64] ; 0x40
  14765. 8005cf4: e01f b.n 8005d36 <find_volume+0x16e>
  14766. pt = fs->win + (MBR_Table + i * SZ_PTE);
  14767. 8005cf6: 6bbb ldr r3, [r7, #56] ; 0x38
  14768. 8005cf8: f103 0238 add.w r2, r3, #56 ; 0x38
  14769. 8005cfc: 6c3b ldr r3, [r7, #64] ; 0x40
  14770. 8005cfe: 011b lsls r3, r3, #4
  14771. 8005d00: f503 73df add.w r3, r3, #446 ; 0x1be
  14772. 8005d04: 4413 add r3, r2
  14773. 8005d06: 633b str r3, [r7, #48] ; 0x30
  14774. br[i] = pt[PTE_System] ? ld_dword(pt + PTE_StLba) : 0;
  14775. 8005d08: 6b3b ldr r3, [r7, #48] ; 0x30
  14776. 8005d0a: 3304 adds r3, #4
  14777. 8005d0c: 781b ldrb r3, [r3, #0]
  14778. 8005d0e: 2b00 cmp r3, #0
  14779. 8005d10: d006 beq.n 8005d20 <find_volume+0x158>
  14780. 8005d12: 6b3b ldr r3, [r7, #48] ; 0x30
  14781. 8005d14: 3308 adds r3, #8
  14782. 8005d16: 4618 mov r0, r3
  14783. 8005d18: f7fe f909 bl 8003f2e <ld_dword>
  14784. 8005d1c: 4602 mov r2, r0
  14785. 8005d1e: e000 b.n 8005d22 <find_volume+0x15a>
  14786. 8005d20: 2200 movs r2, #0
  14787. 8005d22: 6c3b ldr r3, [r7, #64] ; 0x40
  14788. 8005d24: 009b lsls r3, r3, #2
  14789. 8005d26: f107 0158 add.w r1, r7, #88 ; 0x58
  14790. 8005d2a: 440b add r3, r1
  14791. 8005d2c: f843 2c44 str.w r2, [r3, #-68]
  14792. for (i = 0; i < 4; i++) { /* Get partition offset */
  14793. 8005d30: 6c3b ldr r3, [r7, #64] ; 0x40
  14794. 8005d32: 3301 adds r3, #1
  14795. 8005d34: 643b str r3, [r7, #64] ; 0x40
  14796. 8005d36: 6c3b ldr r3, [r7, #64] ; 0x40
  14797. 8005d38: 2b03 cmp r3, #3
  14798. 8005d3a: d9dc bls.n 8005cf6 <find_volume+0x12e>
  14799. }
  14800. i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */
  14801. 8005d3c: 2300 movs r3, #0
  14802. 8005d3e: 643b str r3, [r7, #64] ; 0x40
  14803. if (i) i--;
  14804. 8005d40: 6c3b ldr r3, [r7, #64] ; 0x40
  14805. 8005d42: 2b00 cmp r3, #0
  14806. 8005d44: d002 beq.n 8005d4c <find_volume+0x184>
  14807. 8005d46: 6c3b ldr r3, [r7, #64] ; 0x40
  14808. 8005d48: 3b01 subs r3, #1
  14809. 8005d4a: 643b str r3, [r7, #64] ; 0x40
  14810. do { /* Find an FAT volume */
  14811. bsect = br[i];
  14812. 8005d4c: 6c3b ldr r3, [r7, #64] ; 0x40
  14813. 8005d4e: 009b lsls r3, r3, #2
  14814. 8005d50: f107 0258 add.w r2, r7, #88 ; 0x58
  14815. 8005d54: 4413 add r3, r2
  14816. 8005d56: f853 3c44 ldr.w r3, [r3, #-68]
  14817. 8005d5a: 653b str r3, [r7, #80] ; 0x50
  14818. fmt = bsect ? check_fs(fs, bsect) : 3; /* Check the partition */
  14819. 8005d5c: 6d3b ldr r3, [r7, #80] ; 0x50
  14820. 8005d5e: 2b00 cmp r3, #0
  14821. 8005d60: d005 beq.n 8005d6e <find_volume+0x1a6>
  14822. 8005d62: 6d39 ldr r1, [r7, #80] ; 0x50
  14823. 8005d64: 6bb8 ldr r0, [r7, #56] ; 0x38
  14824. 8005d66: f7ff fed9 bl 8005b1c <check_fs>
  14825. 8005d6a: 4603 mov r3, r0
  14826. 8005d6c: e000 b.n 8005d70 <find_volume+0x1a8>
  14827. 8005d6e: 2303 movs r3, #3
  14828. 8005d70: f887 3057 strb.w r3, [r7, #87] ; 0x57
  14829. } while (LD2PT(vol) == 0 && fmt >= 2 && ++i < 4);
  14830. 8005d74: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  14831. 8005d78: 2b01 cmp r3, #1
  14832. 8005d7a: d905 bls.n 8005d88 <find_volume+0x1c0>
  14833. 8005d7c: 6c3b ldr r3, [r7, #64] ; 0x40
  14834. 8005d7e: 3301 adds r3, #1
  14835. 8005d80: 643b str r3, [r7, #64] ; 0x40
  14836. 8005d82: 6c3b ldr r3, [r7, #64] ; 0x40
  14837. 8005d84: 2b03 cmp r3, #3
  14838. 8005d86: d9e1 bls.n 8005d4c <find_volume+0x184>
  14839. }
  14840. if (fmt == 4) return FR_DISK_ERR; /* An error occured in the disk I/O layer */
  14841. 8005d88: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  14842. 8005d8c: 2b04 cmp r3, #4
  14843. 8005d8e: d101 bne.n 8005d94 <find_volume+0x1cc>
  14844. 8005d90: 2301 movs r3, #1
  14845. 8005d92: e195 b.n 80060c0 <find_volume+0x4f8>
  14846. if (fmt >= 2) return FR_NO_FILESYSTEM; /* No FAT volume is found */
  14847. 8005d94: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  14848. 8005d98: 2b01 cmp r3, #1
  14849. 8005d9a: d901 bls.n 8005da0 <find_volume+0x1d8>
  14850. 8005d9c: 230d movs r3, #13
  14851. 8005d9e: e18f b.n 80060c0 <find_volume+0x4f8>
  14852. #endif
  14853. fmt = FS_EXFAT; /* FAT sub-type */
  14854. } else
  14855. #endif /* _FS_EXFAT */
  14856. {
  14857. if (ld_word(fs->win + BPB_BytsPerSec) != SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_BytsPerSec must be equal to the physical sector size) */
  14858. 8005da0: 6bbb ldr r3, [r7, #56] ; 0x38
  14859. 8005da2: 3338 adds r3, #56 ; 0x38
  14860. 8005da4: 330b adds r3, #11
  14861. 8005da6: 4618 mov r0, r3
  14862. 8005da8: f7fe f8aa bl 8003f00 <ld_word>
  14863. 8005dac: 4603 mov r3, r0
  14864. 8005dae: 461a mov r2, r3
  14865. 8005db0: 6bbb ldr r3, [r7, #56] ; 0x38
  14866. 8005db2: 899b ldrh r3, [r3, #12]
  14867. 8005db4: 429a cmp r2, r3
  14868. 8005db6: d001 beq.n 8005dbc <find_volume+0x1f4>
  14869. 8005db8: 230d movs r3, #13
  14870. 8005dba: e181 b.n 80060c0 <find_volume+0x4f8>
  14871. fasize = ld_word(fs->win + BPB_FATSz16); /* Number of sectors per FAT */
  14872. 8005dbc: 6bbb ldr r3, [r7, #56] ; 0x38
  14873. 8005dbe: 3338 adds r3, #56 ; 0x38
  14874. 8005dc0: 3316 adds r3, #22
  14875. 8005dc2: 4618 mov r0, r3
  14876. 8005dc4: f7fe f89c bl 8003f00 <ld_word>
  14877. 8005dc8: 4603 mov r3, r0
  14878. 8005dca: 64fb str r3, [r7, #76] ; 0x4c
  14879. if (fasize == 0) fasize = ld_dword(fs->win + BPB_FATSz32);
  14880. 8005dcc: 6cfb ldr r3, [r7, #76] ; 0x4c
  14881. 8005dce: 2b00 cmp r3, #0
  14882. 8005dd0: d106 bne.n 8005de0 <find_volume+0x218>
  14883. 8005dd2: 6bbb ldr r3, [r7, #56] ; 0x38
  14884. 8005dd4: 3338 adds r3, #56 ; 0x38
  14885. 8005dd6: 3324 adds r3, #36 ; 0x24
  14886. 8005dd8: 4618 mov r0, r3
  14887. 8005dda: f7fe f8a8 bl 8003f2e <ld_dword>
  14888. 8005dde: 64f8 str r0, [r7, #76] ; 0x4c
  14889. fs->fsize = fasize;
  14890. 8005de0: 6bbb ldr r3, [r7, #56] ; 0x38
  14891. 8005de2: 6cfa ldr r2, [r7, #76] ; 0x4c
  14892. 8005de4: 621a str r2, [r3, #32]
  14893. fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FATs */
  14894. 8005de6: 6bbb ldr r3, [r7, #56] ; 0x38
  14895. 8005de8: f893 2048 ldrb.w r2, [r3, #72] ; 0x48
  14896. 8005dec: 6bbb ldr r3, [r7, #56] ; 0x38
  14897. 8005dee: 709a strb r2, [r3, #2]
  14898. if (fs->n_fats != 1 && fs->n_fats != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
  14899. 8005df0: 6bbb ldr r3, [r7, #56] ; 0x38
  14900. 8005df2: 789b ldrb r3, [r3, #2]
  14901. 8005df4: 2b01 cmp r3, #1
  14902. 8005df6: d005 beq.n 8005e04 <find_volume+0x23c>
  14903. 8005df8: 6bbb ldr r3, [r7, #56] ; 0x38
  14904. 8005dfa: 789b ldrb r3, [r3, #2]
  14905. 8005dfc: 2b02 cmp r3, #2
  14906. 8005dfe: d001 beq.n 8005e04 <find_volume+0x23c>
  14907. 8005e00: 230d movs r3, #13
  14908. 8005e02: e15d b.n 80060c0 <find_volume+0x4f8>
  14909. fasize *= fs->n_fats; /* Number of sectors for FAT area */
  14910. 8005e04: 6bbb ldr r3, [r7, #56] ; 0x38
  14911. 8005e06: 789b ldrb r3, [r3, #2]
  14912. 8005e08: 461a mov r2, r3
  14913. 8005e0a: 6cfb ldr r3, [r7, #76] ; 0x4c
  14914. 8005e0c: fb02 f303 mul.w r3, r2, r3
  14915. 8005e10: 64fb str r3, [r7, #76] ; 0x4c
  14916. fs->csize = fs->win[BPB_SecPerClus]; /* Cluster size */
  14917. 8005e12: 6bbb ldr r3, [r7, #56] ; 0x38
  14918. 8005e14: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
  14919. 8005e18: b29a uxth r2, r3
  14920. 8005e1a: 6bbb ldr r3, [r7, #56] ; 0x38
  14921. 8005e1c: 815a strh r2, [r3, #10]
  14922. if (fs->csize == 0 || (fs->csize & (fs->csize - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */
  14923. 8005e1e: 6bbb ldr r3, [r7, #56] ; 0x38
  14924. 8005e20: 895b ldrh r3, [r3, #10]
  14925. 8005e22: 2b00 cmp r3, #0
  14926. 8005e24: d008 beq.n 8005e38 <find_volume+0x270>
  14927. 8005e26: 6bbb ldr r3, [r7, #56] ; 0x38
  14928. 8005e28: 895b ldrh r3, [r3, #10]
  14929. 8005e2a: 461a mov r2, r3
  14930. 8005e2c: 6bbb ldr r3, [r7, #56] ; 0x38
  14931. 8005e2e: 895b ldrh r3, [r3, #10]
  14932. 8005e30: 3b01 subs r3, #1
  14933. 8005e32: 4013 ands r3, r2
  14934. 8005e34: 2b00 cmp r3, #0
  14935. 8005e36: d001 beq.n 8005e3c <find_volume+0x274>
  14936. 8005e38: 230d movs r3, #13
  14937. 8005e3a: e141 b.n 80060c0 <find_volume+0x4f8>
  14938. fs->n_rootdir = ld_word(fs->win + BPB_RootEntCnt); /* Number of root directory entries */
  14939. 8005e3c: 6bbb ldr r3, [r7, #56] ; 0x38
  14940. 8005e3e: 3338 adds r3, #56 ; 0x38
  14941. 8005e40: 3311 adds r3, #17
  14942. 8005e42: 4618 mov r0, r3
  14943. 8005e44: f7fe f85c bl 8003f00 <ld_word>
  14944. 8005e48: 4603 mov r3, r0
  14945. 8005e4a: 461a mov r2, r3
  14946. 8005e4c: 6bbb ldr r3, [r7, #56] ; 0x38
  14947. 8005e4e: 811a strh r2, [r3, #8]
  14948. if (fs->n_rootdir % (SS(fs) / SZDIRE)) return FR_NO_FILESYSTEM; /* (Must be sector aligned) */
  14949. 8005e50: 6bbb ldr r3, [r7, #56] ; 0x38
  14950. 8005e52: 891b ldrh r3, [r3, #8]
  14951. 8005e54: 6bba ldr r2, [r7, #56] ; 0x38
  14952. 8005e56: 8992 ldrh r2, [r2, #12]
  14953. 8005e58: 0952 lsrs r2, r2, #5
  14954. 8005e5a: b292 uxth r2, r2
  14955. 8005e5c: fbb3 f1f2 udiv r1, r3, r2
  14956. 8005e60: fb02 f201 mul.w r2, r2, r1
  14957. 8005e64: 1a9b subs r3, r3, r2
  14958. 8005e66: b29b uxth r3, r3
  14959. 8005e68: 2b00 cmp r3, #0
  14960. 8005e6a: d001 beq.n 8005e70 <find_volume+0x2a8>
  14961. 8005e6c: 230d movs r3, #13
  14962. 8005e6e: e127 b.n 80060c0 <find_volume+0x4f8>
  14963. tsect = ld_word(fs->win + BPB_TotSec16); /* Number of sectors on the volume */
  14964. 8005e70: 6bbb ldr r3, [r7, #56] ; 0x38
  14965. 8005e72: 3338 adds r3, #56 ; 0x38
  14966. 8005e74: 3313 adds r3, #19
  14967. 8005e76: 4618 mov r0, r3
  14968. 8005e78: f7fe f842 bl 8003f00 <ld_word>
  14969. 8005e7c: 4603 mov r3, r0
  14970. 8005e7e: 64bb str r3, [r7, #72] ; 0x48
  14971. if (tsect == 0) tsect = ld_dword(fs->win + BPB_TotSec32);
  14972. 8005e80: 6cbb ldr r3, [r7, #72] ; 0x48
  14973. 8005e82: 2b00 cmp r3, #0
  14974. 8005e84: d106 bne.n 8005e94 <find_volume+0x2cc>
  14975. 8005e86: 6bbb ldr r3, [r7, #56] ; 0x38
  14976. 8005e88: 3338 adds r3, #56 ; 0x38
  14977. 8005e8a: 3320 adds r3, #32
  14978. 8005e8c: 4618 mov r0, r3
  14979. 8005e8e: f7fe f84e bl 8003f2e <ld_dword>
  14980. 8005e92: 64b8 str r0, [r7, #72] ; 0x48
  14981. nrsv = ld_word(fs->win + BPB_RsvdSecCnt); /* Number of reserved sectors */
  14982. 8005e94: 6bbb ldr r3, [r7, #56] ; 0x38
  14983. 8005e96: 3338 adds r3, #56 ; 0x38
  14984. 8005e98: 330e adds r3, #14
  14985. 8005e9a: 4618 mov r0, r3
  14986. 8005e9c: f7fe f830 bl 8003f00 <ld_word>
  14987. 8005ea0: 4603 mov r3, r0
  14988. 8005ea2: 85fb strh r3, [r7, #46] ; 0x2e
  14989. if (nrsv == 0) return FR_NO_FILESYSTEM; /* (Must not be 0) */
  14990. 8005ea4: 8dfb ldrh r3, [r7, #46] ; 0x2e
  14991. 8005ea6: 2b00 cmp r3, #0
  14992. 8005ea8: d104 bne.n 8005eb4 <find_volume+0x2ec>
  14993. 8005eaa: 230d movs r3, #13
  14994. 8005eac: e108 b.n 80060c0 <find_volume+0x4f8>
  14995. 8005eae: bf00 nop
  14996. 8005eb0: 200000ac .word 0x200000ac
  14997. /* Determine the FAT sub type */
  14998. sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZDIRE); /* RSV + FAT + DIR */
  14999. 8005eb4: 8dfa ldrh r2, [r7, #46] ; 0x2e
  15000. 8005eb6: 6cfb ldr r3, [r7, #76] ; 0x4c
  15001. 8005eb8: 4413 add r3, r2
  15002. 8005eba: 6bba ldr r2, [r7, #56] ; 0x38
  15003. 8005ebc: 8911 ldrh r1, [r2, #8]
  15004. 8005ebe: 6bba ldr r2, [r7, #56] ; 0x38
  15005. 8005ec0: 8992 ldrh r2, [r2, #12]
  15006. 8005ec2: 0952 lsrs r2, r2, #5
  15007. 8005ec4: b292 uxth r2, r2
  15008. 8005ec6: fbb1 f2f2 udiv r2, r1, r2
  15009. 8005eca: b292 uxth r2, r2
  15010. 8005ecc: 4413 add r3, r2
  15011. 8005ece: 62bb str r3, [r7, #40] ; 0x28
  15012. if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
  15013. 8005ed0: 6cba ldr r2, [r7, #72] ; 0x48
  15014. 8005ed2: 6abb ldr r3, [r7, #40] ; 0x28
  15015. 8005ed4: 429a cmp r2, r3
  15016. 8005ed6: d201 bcs.n 8005edc <find_volume+0x314>
  15017. 8005ed8: 230d movs r3, #13
  15018. 8005eda: e0f1 b.n 80060c0 <find_volume+0x4f8>
  15019. nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
  15020. 8005edc: 6cba ldr r2, [r7, #72] ; 0x48
  15021. 8005ede: 6abb ldr r3, [r7, #40] ; 0x28
  15022. 8005ee0: 1ad3 subs r3, r2, r3
  15023. 8005ee2: 6bba ldr r2, [r7, #56] ; 0x38
  15024. 8005ee4: 8952 ldrh r2, [r2, #10]
  15025. 8005ee6: fbb3 f3f2 udiv r3, r3, r2
  15026. 8005eea: 627b str r3, [r7, #36] ; 0x24
  15027. if (nclst == 0) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
  15028. 8005eec: 6a7b ldr r3, [r7, #36] ; 0x24
  15029. 8005eee: 2b00 cmp r3, #0
  15030. 8005ef0: d101 bne.n 8005ef6 <find_volume+0x32e>
  15031. 8005ef2: 230d movs r3, #13
  15032. 8005ef4: e0e4 b.n 80060c0 <find_volume+0x4f8>
  15033. fmt = FS_FAT32;
  15034. 8005ef6: 2303 movs r3, #3
  15035. 8005ef8: f887 3057 strb.w r3, [r7, #87] ; 0x57
  15036. if (nclst <= MAX_FAT16) fmt = FS_FAT16;
  15037. 8005efc: 6a7b ldr r3, [r7, #36] ; 0x24
  15038. 8005efe: f64f 72f5 movw r2, #65525 ; 0xfff5
  15039. 8005f02: 4293 cmp r3, r2
  15040. 8005f04: d802 bhi.n 8005f0c <find_volume+0x344>
  15041. 8005f06: 2302 movs r3, #2
  15042. 8005f08: f887 3057 strb.w r3, [r7, #87] ; 0x57
  15043. if (nclst <= MAX_FAT12) fmt = FS_FAT12;
  15044. 8005f0c: 6a7b ldr r3, [r7, #36] ; 0x24
  15045. 8005f0e: f640 72f5 movw r2, #4085 ; 0xff5
  15046. 8005f12: 4293 cmp r3, r2
  15047. 8005f14: d802 bhi.n 8005f1c <find_volume+0x354>
  15048. 8005f16: 2301 movs r3, #1
  15049. 8005f18: f887 3057 strb.w r3, [r7, #87] ; 0x57
  15050. /* Boundaries and Limits */
  15051. fs->n_fatent = nclst + 2; /* Number of FAT entries */
  15052. 8005f1c: 6a7b ldr r3, [r7, #36] ; 0x24
  15053. 8005f1e: 1c9a adds r2, r3, #2
  15054. 8005f20: 6bbb ldr r3, [r7, #56] ; 0x38
  15055. 8005f22: 61da str r2, [r3, #28]
  15056. fs->volbase = bsect; /* Volume start sector */
  15057. 8005f24: 6bbb ldr r3, [r7, #56] ; 0x38
  15058. 8005f26: 6d3a ldr r2, [r7, #80] ; 0x50
  15059. 8005f28: 625a str r2, [r3, #36] ; 0x24
  15060. fs->fatbase = bsect + nrsv; /* FAT start sector */
  15061. 8005f2a: 8dfa ldrh r2, [r7, #46] ; 0x2e
  15062. 8005f2c: 6d3b ldr r3, [r7, #80] ; 0x50
  15063. 8005f2e: 441a add r2, r3
  15064. 8005f30: 6bbb ldr r3, [r7, #56] ; 0x38
  15065. 8005f32: 629a str r2, [r3, #40] ; 0x28
  15066. fs->database = bsect + sysect; /* Data start sector */
  15067. 8005f34: 6d3a ldr r2, [r7, #80] ; 0x50
  15068. 8005f36: 6abb ldr r3, [r7, #40] ; 0x28
  15069. 8005f38: 441a add r2, r3
  15070. 8005f3a: 6bbb ldr r3, [r7, #56] ; 0x38
  15071. 8005f3c: 631a str r2, [r3, #48] ; 0x30
  15072. if (fmt == FS_FAT32) {
  15073. 8005f3e: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  15074. 8005f42: 2b03 cmp r3, #3
  15075. 8005f44: d11e bne.n 8005f84 <find_volume+0x3bc>
  15076. if (ld_word(fs->win + BPB_FSVer32) != 0) return FR_NO_FILESYSTEM; /* (Must be FAT32 revision 0.0) */
  15077. 8005f46: 6bbb ldr r3, [r7, #56] ; 0x38
  15078. 8005f48: 3338 adds r3, #56 ; 0x38
  15079. 8005f4a: 332a adds r3, #42 ; 0x2a
  15080. 8005f4c: 4618 mov r0, r3
  15081. 8005f4e: f7fd ffd7 bl 8003f00 <ld_word>
  15082. 8005f52: 4603 mov r3, r0
  15083. 8005f54: 2b00 cmp r3, #0
  15084. 8005f56: d001 beq.n 8005f5c <find_volume+0x394>
  15085. 8005f58: 230d movs r3, #13
  15086. 8005f5a: e0b1 b.n 80060c0 <find_volume+0x4f8>
  15087. if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
  15088. 8005f5c: 6bbb ldr r3, [r7, #56] ; 0x38
  15089. 8005f5e: 891b ldrh r3, [r3, #8]
  15090. 8005f60: 2b00 cmp r3, #0
  15091. 8005f62: d001 beq.n 8005f68 <find_volume+0x3a0>
  15092. 8005f64: 230d movs r3, #13
  15093. 8005f66: e0ab b.n 80060c0 <find_volume+0x4f8>
  15094. fs->dirbase = ld_dword(fs->win + BPB_RootClus32); /* Root directory start cluster */
  15095. 8005f68: 6bbb ldr r3, [r7, #56] ; 0x38
  15096. 8005f6a: 3338 adds r3, #56 ; 0x38
  15097. 8005f6c: 332c adds r3, #44 ; 0x2c
  15098. 8005f6e: 4618 mov r0, r3
  15099. 8005f70: f7fd ffdd bl 8003f2e <ld_dword>
  15100. 8005f74: 4602 mov r2, r0
  15101. 8005f76: 6bbb ldr r3, [r7, #56] ; 0x38
  15102. 8005f78: 62da str r2, [r3, #44] ; 0x2c
  15103. szbfat = fs->n_fatent * 4; /* (Needed FAT size) */
  15104. 8005f7a: 6bbb ldr r3, [r7, #56] ; 0x38
  15105. 8005f7c: 69db ldr r3, [r3, #28]
  15106. 8005f7e: 009b lsls r3, r3, #2
  15107. 8005f80: 647b str r3, [r7, #68] ; 0x44
  15108. 8005f82: e01f b.n 8005fc4 <find_volume+0x3fc>
  15109. } else {
  15110. if (fs->n_rootdir == 0) return FR_NO_FILESYSTEM;/* (BPB_RootEntCnt must not be 0) */
  15111. 8005f84: 6bbb ldr r3, [r7, #56] ; 0x38
  15112. 8005f86: 891b ldrh r3, [r3, #8]
  15113. 8005f88: 2b00 cmp r3, #0
  15114. 8005f8a: d101 bne.n 8005f90 <find_volume+0x3c8>
  15115. 8005f8c: 230d movs r3, #13
  15116. 8005f8e: e097 b.n 80060c0 <find_volume+0x4f8>
  15117. fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
  15118. 8005f90: 6bbb ldr r3, [r7, #56] ; 0x38
  15119. 8005f92: 6a9a ldr r2, [r3, #40] ; 0x28
  15120. 8005f94: 6cfb ldr r3, [r7, #76] ; 0x4c
  15121. 8005f96: 441a add r2, r3
  15122. 8005f98: 6bbb ldr r3, [r7, #56] ; 0x38
  15123. 8005f9a: 62da str r2, [r3, #44] ; 0x2c
  15124. szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */
  15125. fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
  15126. 8005f9c: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  15127. 8005fa0: 2b02 cmp r3, #2
  15128. 8005fa2: d103 bne.n 8005fac <find_volume+0x3e4>
  15129. 8005fa4: 6bbb ldr r3, [r7, #56] ; 0x38
  15130. 8005fa6: 69db ldr r3, [r3, #28]
  15131. 8005fa8: 005b lsls r3, r3, #1
  15132. 8005faa: e00a b.n 8005fc2 <find_volume+0x3fa>
  15133. 8005fac: 6bbb ldr r3, [r7, #56] ; 0x38
  15134. 8005fae: 69da ldr r2, [r3, #28]
  15135. 8005fb0: 4613 mov r3, r2
  15136. 8005fb2: 005b lsls r3, r3, #1
  15137. 8005fb4: 4413 add r3, r2
  15138. 8005fb6: 085a lsrs r2, r3, #1
  15139. 8005fb8: 6bbb ldr r3, [r7, #56] ; 0x38
  15140. 8005fba: 69db ldr r3, [r3, #28]
  15141. 8005fbc: f003 0301 and.w r3, r3, #1
  15142. 8005fc0: 4413 add r3, r2
  15143. szbfat = (fmt == FS_FAT16) ? /* (Needed FAT size) */
  15144. 8005fc2: 647b str r3, [r7, #68] ; 0x44
  15145. }
  15146. if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) return FR_NO_FILESYSTEM; /* (BPB_FATSz must not be less than the size needed) */
  15147. 8005fc4: 6bbb ldr r3, [r7, #56] ; 0x38
  15148. 8005fc6: 6a1a ldr r2, [r3, #32]
  15149. 8005fc8: 6bbb ldr r3, [r7, #56] ; 0x38
  15150. 8005fca: 899b ldrh r3, [r3, #12]
  15151. 8005fcc: 4619 mov r1, r3
  15152. 8005fce: 6c7b ldr r3, [r7, #68] ; 0x44
  15153. 8005fd0: 440b add r3, r1
  15154. 8005fd2: 3b01 subs r3, #1
  15155. 8005fd4: 6bb9 ldr r1, [r7, #56] ; 0x38
  15156. 8005fd6: 8989 ldrh r1, [r1, #12]
  15157. 8005fd8: fbb3 f3f1 udiv r3, r3, r1
  15158. 8005fdc: 429a cmp r2, r3
  15159. 8005fde: d201 bcs.n 8005fe4 <find_volume+0x41c>
  15160. 8005fe0: 230d movs r3, #13
  15161. 8005fe2: e06d b.n 80060c0 <find_volume+0x4f8>
  15162. #if !_FS_READONLY
  15163. /* Get FSINFO if available */
  15164. fs->last_clst = fs->free_clst = 0xFFFFFFFF; /* Initialize cluster allocation information */
  15165. 8005fe4: 6bbb ldr r3, [r7, #56] ; 0x38
  15166. 8005fe6: f04f 32ff mov.w r2, #4294967295
  15167. 8005fea: 619a str r2, [r3, #24]
  15168. 8005fec: 6bbb ldr r3, [r7, #56] ; 0x38
  15169. 8005fee: 699a ldr r2, [r3, #24]
  15170. 8005ff0: 6bbb ldr r3, [r7, #56] ; 0x38
  15171. 8005ff2: 615a str r2, [r3, #20]
  15172. fs->fsi_flag = 0x80;
  15173. 8005ff4: 6bbb ldr r3, [r7, #56] ; 0x38
  15174. 8005ff6: 2280 movs r2, #128 ; 0x80
  15175. 8005ff8: 711a strb r2, [r3, #4]
  15176. #if (_FS_NOFSINFO & 3) != 3
  15177. if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo32 == 1 */
  15178. 8005ffa: f897 3057 ldrb.w r3, [r7, #87] ; 0x57
  15179. 8005ffe: 2b03 cmp r3, #3
  15180. 8006000: d149 bne.n 8006096 <find_volume+0x4ce>
  15181. && ld_word(fs->win + BPB_FSInfo32) == 1
  15182. 8006002: 6bbb ldr r3, [r7, #56] ; 0x38
  15183. 8006004: 3338 adds r3, #56 ; 0x38
  15184. 8006006: 3330 adds r3, #48 ; 0x30
  15185. 8006008: 4618 mov r0, r3
  15186. 800600a: f7fd ff79 bl 8003f00 <ld_word>
  15187. 800600e: 4603 mov r3, r0
  15188. 8006010: 2b01 cmp r3, #1
  15189. 8006012: d140 bne.n 8006096 <find_volume+0x4ce>
  15190. && move_window(fs, bsect + 1) == FR_OK)
  15191. 8006014: 6d3b ldr r3, [r7, #80] ; 0x50
  15192. 8006016: 3301 adds r3, #1
  15193. 8006018: 4619 mov r1, r3
  15194. 800601a: 6bb8 ldr r0, [r7, #56] ; 0x38
  15195. 800601c: f7fe fa10 bl 8004440 <move_window>
  15196. 8006020: 4603 mov r3, r0
  15197. 8006022: 2b00 cmp r3, #0
  15198. 8006024: d137 bne.n 8006096 <find_volume+0x4ce>
  15199. {
  15200. fs->fsi_flag = 0;
  15201. 8006026: 6bbb ldr r3, [r7, #56] ; 0x38
  15202. 8006028: 2200 movs r2, #0
  15203. 800602a: 711a strb r2, [r3, #4]
  15204. if (ld_word(fs->win + BS_55AA) == 0xAA55 /* Load FSINFO data if available */
  15205. 800602c: 6bbb ldr r3, [r7, #56] ; 0x38
  15206. 800602e: 3338 adds r3, #56 ; 0x38
  15207. 8006030: f503 73ff add.w r3, r3, #510 ; 0x1fe
  15208. 8006034: 4618 mov r0, r3
  15209. 8006036: f7fd ff63 bl 8003f00 <ld_word>
  15210. 800603a: 4603 mov r3, r0
  15211. 800603c: 461a mov r2, r3
  15212. 800603e: f64a 2355 movw r3, #43605 ; 0xaa55
  15213. 8006042: 429a cmp r2, r3
  15214. 8006044: d127 bne.n 8006096 <find_volume+0x4ce>
  15215. && ld_dword(fs->win + FSI_LeadSig) == 0x41615252
  15216. 8006046: 6bbb ldr r3, [r7, #56] ; 0x38
  15217. 8006048: 3338 adds r3, #56 ; 0x38
  15218. 800604a: 4618 mov r0, r3
  15219. 800604c: f7fd ff6f bl 8003f2e <ld_dword>
  15220. 8006050: 4602 mov r2, r0
  15221. 8006052: 4b1d ldr r3, [pc, #116] ; (80060c8 <find_volume+0x500>)
  15222. 8006054: 429a cmp r2, r3
  15223. 8006056: d11e bne.n 8006096 <find_volume+0x4ce>
  15224. && ld_dword(fs->win + FSI_StrucSig) == 0x61417272)
  15225. 8006058: 6bbb ldr r3, [r7, #56] ; 0x38
  15226. 800605a: 3338 adds r3, #56 ; 0x38
  15227. 800605c: f503 73f2 add.w r3, r3, #484 ; 0x1e4
  15228. 8006060: 4618 mov r0, r3
  15229. 8006062: f7fd ff64 bl 8003f2e <ld_dword>
  15230. 8006066: 4602 mov r2, r0
  15231. 8006068: 4b18 ldr r3, [pc, #96] ; (80060cc <find_volume+0x504>)
  15232. 800606a: 429a cmp r2, r3
  15233. 800606c: d113 bne.n 8006096 <find_volume+0x4ce>
  15234. {
  15235. #if (_FS_NOFSINFO & 1) == 0
  15236. fs->free_clst = ld_dword(fs->win + FSI_Free_Count);
  15237. 800606e: 6bbb ldr r3, [r7, #56] ; 0x38
  15238. 8006070: 3338 adds r3, #56 ; 0x38
  15239. 8006072: f503 73f4 add.w r3, r3, #488 ; 0x1e8
  15240. 8006076: 4618 mov r0, r3
  15241. 8006078: f7fd ff59 bl 8003f2e <ld_dword>
  15242. 800607c: 4602 mov r2, r0
  15243. 800607e: 6bbb ldr r3, [r7, #56] ; 0x38
  15244. 8006080: 619a str r2, [r3, #24]
  15245. #endif
  15246. #if (_FS_NOFSINFO & 2) == 0
  15247. fs->last_clst = ld_dword(fs->win + FSI_Nxt_Free);
  15248. 8006082: 6bbb ldr r3, [r7, #56] ; 0x38
  15249. 8006084: 3338 adds r3, #56 ; 0x38
  15250. 8006086: f503 73f6 add.w r3, r3, #492 ; 0x1ec
  15251. 800608a: 4618 mov r0, r3
  15252. 800608c: f7fd ff4f bl 8003f2e <ld_dword>
  15253. 8006090: 4602 mov r2, r0
  15254. 8006092: 6bbb ldr r3, [r7, #56] ; 0x38
  15255. 8006094: 615a str r2, [r3, #20]
  15256. }
  15257. #endif /* (_FS_NOFSINFO & 3) != 3 */
  15258. #endif /* !_FS_READONLY */
  15259. }
  15260. fs->fs_type = fmt; /* FAT sub-type */
  15261. 8006096: 6bbb ldr r3, [r7, #56] ; 0x38
  15262. 8006098: f897 2057 ldrb.w r2, [r7, #87] ; 0x57
  15263. 800609c: 701a strb r2, [r3, #0]
  15264. fs->id = ++Fsid; /* File system mount ID */
  15265. 800609e: 4b0c ldr r3, [pc, #48] ; (80060d0 <find_volume+0x508>)
  15266. 80060a0: 881b ldrh r3, [r3, #0]
  15267. 80060a2: 3301 adds r3, #1
  15268. 80060a4: b29a uxth r2, r3
  15269. 80060a6: 4b0a ldr r3, [pc, #40] ; (80060d0 <find_volume+0x508>)
  15270. 80060a8: 801a strh r2, [r3, #0]
  15271. 80060aa: 4b09 ldr r3, [pc, #36] ; (80060d0 <find_volume+0x508>)
  15272. 80060ac: 881a ldrh r2, [r3, #0]
  15273. 80060ae: 6bbb ldr r3, [r7, #56] ; 0x38
  15274. 80060b0: 80da strh r2, [r3, #6]
  15275. #if _USE_LFN == 1
  15276. fs->lfnbuf = LfnBuf; /* Static LFN working buffer */
  15277. 80060b2: 6bbb ldr r3, [r7, #56] ; 0x38
  15278. 80060b4: 4a07 ldr r2, [pc, #28] ; (80060d4 <find_volume+0x50c>)
  15279. 80060b6: 611a str r2, [r3, #16]
  15280. #endif
  15281. #if _FS_RPATH != 0
  15282. fs->cdir = 0; /* Initialize current directory */
  15283. #endif
  15284. #if _FS_LOCK != 0 /* Clear file lock semaphores */
  15285. clear_lock(fs);
  15286. 80060b8: 6bb8 ldr r0, [r7, #56] ; 0x38
  15287. 80060ba: f7fe f95b bl 8004374 <clear_lock>
  15288. #endif
  15289. return FR_OK;
  15290. 80060be: 2300 movs r3, #0
  15291. }
  15292. 80060c0: 4618 mov r0, r3
  15293. 80060c2: 3758 adds r7, #88 ; 0x58
  15294. 80060c4: 46bd mov sp, r7
  15295. 80060c6: bd80 pop {r7, pc}
  15296. 80060c8: 41615252 .word 0x41615252
  15297. 80060cc: 61417272 .word 0x61417272
  15298. 80060d0: 200000b0 .word 0x200000b0
  15299. 80060d4: 200000d4 .word 0x200000d4
  15300. 080060d8 <validate>:
  15301. static
  15302. FRESULT validate ( /* Returns FR_OK or FR_INVALID_OBJECT */
  15303. _FDID* obj, /* Pointer to the _OBJ, the 1st member in the FIL/DIR object, to check validity */
  15304. FATFS** fs /* Pointer to pointer to the owner file system object to return */
  15305. )
  15306. {
  15307. 80060d8: b580 push {r7, lr}
  15308. 80060da: b084 sub sp, #16
  15309. 80060dc: af00 add r7, sp, #0
  15310. 80060de: 6078 str r0, [r7, #4]
  15311. 80060e0: 6039 str r1, [r7, #0]
  15312. FRESULT res = FR_INVALID_OBJECT;
  15313. 80060e2: 2309 movs r3, #9
  15314. 80060e4: 73fb strb r3, [r7, #15]
  15315. if (obj && obj->fs && obj->fs->fs_type && obj->id == obj->fs->id) { /* Test if the object is valid */
  15316. 80060e6: 687b ldr r3, [r7, #4]
  15317. 80060e8: 2b00 cmp r3, #0
  15318. 80060ea: d01c beq.n 8006126 <validate+0x4e>
  15319. 80060ec: 687b ldr r3, [r7, #4]
  15320. 80060ee: 681b ldr r3, [r3, #0]
  15321. 80060f0: 2b00 cmp r3, #0
  15322. 80060f2: d018 beq.n 8006126 <validate+0x4e>
  15323. 80060f4: 687b ldr r3, [r7, #4]
  15324. 80060f6: 681b ldr r3, [r3, #0]
  15325. 80060f8: 781b ldrb r3, [r3, #0]
  15326. 80060fa: 2b00 cmp r3, #0
  15327. 80060fc: d013 beq.n 8006126 <validate+0x4e>
  15328. 80060fe: 687b ldr r3, [r7, #4]
  15329. 8006100: 889a ldrh r2, [r3, #4]
  15330. 8006102: 687b ldr r3, [r7, #4]
  15331. 8006104: 681b ldr r3, [r3, #0]
  15332. 8006106: 88db ldrh r3, [r3, #6]
  15333. 8006108: 429a cmp r2, r3
  15334. 800610a: d10c bne.n 8006126 <validate+0x4e>
  15335. }
  15336. } else {
  15337. res = FR_TIMEOUT;
  15338. }
  15339. #else
  15340. if (!(disk_status(obj->fs->drv) & STA_NOINIT)) { /* Test if the phsical drive is kept initialized */
  15341. 800610c: 687b ldr r3, [r7, #4]
  15342. 800610e: 681b ldr r3, [r3, #0]
  15343. 8006110: 785b ldrb r3, [r3, #1]
  15344. 8006112: 4618 mov r0, r3
  15345. 8006114: f7fd fe56 bl 8003dc4 <disk_status>
  15346. 8006118: 4603 mov r3, r0
  15347. 800611a: f003 0301 and.w r3, r3, #1
  15348. 800611e: 2b00 cmp r3, #0
  15349. 8006120: d101 bne.n 8006126 <validate+0x4e>
  15350. res = FR_OK;
  15351. 8006122: 2300 movs r3, #0
  15352. 8006124: 73fb strb r3, [r7, #15]
  15353. }
  15354. #endif
  15355. }
  15356. *fs = (res == FR_OK) ? obj->fs : 0; /* Corresponding filesystem object */
  15357. 8006126: 7bfb ldrb r3, [r7, #15]
  15358. 8006128: 2b00 cmp r3, #0
  15359. 800612a: d102 bne.n 8006132 <validate+0x5a>
  15360. 800612c: 687b ldr r3, [r7, #4]
  15361. 800612e: 681b ldr r3, [r3, #0]
  15362. 8006130: e000 b.n 8006134 <validate+0x5c>
  15363. 8006132: 2300 movs r3, #0
  15364. 8006134: 683a ldr r2, [r7, #0]
  15365. 8006136: 6013 str r3, [r2, #0]
  15366. return res;
  15367. 8006138: 7bfb ldrb r3, [r7, #15]
  15368. }
  15369. 800613a: 4618 mov r0, r3
  15370. 800613c: 3710 adds r7, #16
  15371. 800613e: 46bd mov sp, r7
  15372. 8006140: bd80 pop {r7, pc}
  15373. ...
  15374. 08006144 <f_mount>:
  15375. FRESULT f_mount (
  15376. FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/
  15377. const TCHAR* path, /* Logical drive number to be mounted/unmounted */
  15378. BYTE opt /* Mode option 0:Do not mount (delayed mount), 1:Mount immediately */
  15379. )
  15380. {
  15381. 8006144: b580 push {r7, lr}
  15382. 8006146: b088 sub sp, #32
  15383. 8006148: af00 add r7, sp, #0
  15384. 800614a: 60f8 str r0, [r7, #12]
  15385. 800614c: 60b9 str r1, [r7, #8]
  15386. 800614e: 4613 mov r3, r2
  15387. 8006150: 71fb strb r3, [r7, #7]
  15388. FATFS *cfs;
  15389. int vol;
  15390. FRESULT res;
  15391. const TCHAR *rp = path;
  15392. 8006152: 68bb ldr r3, [r7, #8]
  15393. 8006154: 613b str r3, [r7, #16]
  15394. /* Get logical drive number */
  15395. vol = get_ldnumber(&rp);
  15396. 8006156: f107 0310 add.w r3, r7, #16
  15397. 800615a: 4618 mov r0, r3
  15398. 800615c: f7ff fc9a bl 8005a94 <get_ldnumber>
  15399. 8006160: 61f8 str r0, [r7, #28]
  15400. if (vol < 0) return FR_INVALID_DRIVE;
  15401. 8006162: 69fb ldr r3, [r7, #28]
  15402. 8006164: 2b00 cmp r3, #0
  15403. 8006166: da01 bge.n 800616c <f_mount+0x28>
  15404. 8006168: 230b movs r3, #11
  15405. 800616a: e02b b.n 80061c4 <f_mount+0x80>
  15406. cfs = FatFs[vol]; /* Pointer to fs object */
  15407. 800616c: 4a17 ldr r2, [pc, #92] ; (80061cc <f_mount+0x88>)
  15408. 800616e: 69fb ldr r3, [r7, #28]
  15409. 8006170: f852 3023 ldr.w r3, [r2, r3, lsl #2]
  15410. 8006174: 61bb str r3, [r7, #24]
  15411. if (cfs) {
  15412. 8006176: 69bb ldr r3, [r7, #24]
  15413. 8006178: 2b00 cmp r3, #0
  15414. 800617a: d005 beq.n 8006188 <f_mount+0x44>
  15415. #if _FS_LOCK != 0
  15416. clear_lock(cfs);
  15417. 800617c: 69b8 ldr r0, [r7, #24]
  15418. 800617e: f7fe f8f9 bl 8004374 <clear_lock>
  15419. #endif
  15420. #if _FS_REENTRANT /* Discard sync object of the current volume */
  15421. if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR;
  15422. #endif
  15423. cfs->fs_type = 0; /* Clear old fs object */
  15424. 8006182: 69bb ldr r3, [r7, #24]
  15425. 8006184: 2200 movs r2, #0
  15426. 8006186: 701a strb r2, [r3, #0]
  15427. }
  15428. if (fs) {
  15429. 8006188: 68fb ldr r3, [r7, #12]
  15430. 800618a: 2b00 cmp r3, #0
  15431. 800618c: d002 beq.n 8006194 <f_mount+0x50>
  15432. fs->fs_type = 0; /* Clear new fs object */
  15433. 800618e: 68fb ldr r3, [r7, #12]
  15434. 8006190: 2200 movs r2, #0
  15435. 8006192: 701a strb r2, [r3, #0]
  15436. #if _FS_REENTRANT /* Create sync object for the new volume */
  15437. if (!ff_cre_syncobj((BYTE)vol, &fs->sobj)) return FR_INT_ERR;
  15438. #endif
  15439. }
  15440. FatFs[vol] = fs; /* Register new fs object */
  15441. 8006194: 68fa ldr r2, [r7, #12]
  15442. 8006196: 490d ldr r1, [pc, #52] ; (80061cc <f_mount+0x88>)
  15443. 8006198: 69fb ldr r3, [r7, #28]
  15444. 800619a: f841 2023 str.w r2, [r1, r3, lsl #2]
  15445. if (!fs || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */
  15446. 800619e: 68fb ldr r3, [r7, #12]
  15447. 80061a0: 2b00 cmp r3, #0
  15448. 80061a2: d002 beq.n 80061aa <f_mount+0x66>
  15449. 80061a4: 79fb ldrb r3, [r7, #7]
  15450. 80061a6: 2b01 cmp r3, #1
  15451. 80061a8: d001 beq.n 80061ae <f_mount+0x6a>
  15452. 80061aa: 2300 movs r3, #0
  15453. 80061ac: e00a b.n 80061c4 <f_mount+0x80>
  15454. res = find_volume(&path, &fs, 0); /* Force mounted the volume */
  15455. 80061ae: f107 010c add.w r1, r7, #12
  15456. 80061b2: f107 0308 add.w r3, r7, #8
  15457. 80061b6: 2200 movs r2, #0
  15458. 80061b8: 4618 mov r0, r3
  15459. 80061ba: f7ff fd05 bl 8005bc8 <find_volume>
  15460. 80061be: 4603 mov r3, r0
  15461. 80061c0: 75fb strb r3, [r7, #23]
  15462. LEAVE_FF(fs, res);
  15463. 80061c2: 7dfb ldrb r3, [r7, #23]
  15464. }
  15465. 80061c4: 4618 mov r0, r3
  15466. 80061c6: 3720 adds r7, #32
  15467. 80061c8: 46bd mov sp, r7
  15468. 80061ca: bd80 pop {r7, pc}
  15469. 80061cc: 200000ac .word 0x200000ac
  15470. 080061d0 <f_open>:
  15471. FRESULT f_open (
  15472. FIL* fp, /* Pointer to the blank file object */
  15473. const TCHAR* path, /* Pointer to the file name */
  15474. BYTE mode /* Access mode and file open mode flags */
  15475. )
  15476. {
  15477. 80061d0: b580 push {r7, lr}
  15478. 80061d2: b09a sub sp, #104 ; 0x68
  15479. 80061d4: af00 add r7, sp, #0
  15480. 80061d6: 60f8 str r0, [r7, #12]
  15481. 80061d8: 60b9 str r1, [r7, #8]
  15482. 80061da: 4613 mov r3, r2
  15483. 80061dc: 71fb strb r3, [r7, #7]
  15484. FSIZE_t ofs;
  15485. #endif
  15486. DEF_NAMBUF
  15487. if (!fp) return FR_INVALID_OBJECT;
  15488. 80061de: 68fb ldr r3, [r7, #12]
  15489. 80061e0: 2b00 cmp r3, #0
  15490. 80061e2: d101 bne.n 80061e8 <f_open+0x18>
  15491. 80061e4: 2309 movs r3, #9
  15492. 80061e6: e1bb b.n 8006560 <f_open+0x390>
  15493. /* Get logical drive */
  15494. mode &= _FS_READONLY ? FA_READ : FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_CREATE_NEW | FA_OPEN_ALWAYS | FA_OPEN_APPEND | FA_SEEKEND;
  15495. 80061e8: 79fb ldrb r3, [r7, #7]
  15496. 80061ea: f003 033f and.w r3, r3, #63 ; 0x3f
  15497. 80061ee: 71fb strb r3, [r7, #7]
  15498. res = find_volume(&path, &fs, mode);
  15499. 80061f0: 79fa ldrb r2, [r7, #7]
  15500. 80061f2: f107 0114 add.w r1, r7, #20
  15501. 80061f6: f107 0308 add.w r3, r7, #8
  15502. 80061fa: 4618 mov r0, r3
  15503. 80061fc: f7ff fce4 bl 8005bc8 <find_volume>
  15504. 8006200: 4603 mov r3, r0
  15505. 8006202: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15506. if (res == FR_OK) {
  15507. 8006206: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15508. 800620a: 2b00 cmp r3, #0
  15509. 800620c: f040 819f bne.w 800654e <f_open+0x37e>
  15510. dj.obj.fs = fs;
  15511. 8006210: 697b ldr r3, [r7, #20]
  15512. 8006212: 61bb str r3, [r7, #24]
  15513. INIT_NAMBUF(fs);
  15514. res = follow_path(&dj, path); /* Follow the file path */
  15515. 8006214: 68ba ldr r2, [r7, #8]
  15516. 8006216: f107 0318 add.w r3, r7, #24
  15517. 800621a: 4611 mov r1, r2
  15518. 800621c: 4618 mov r0, r3
  15519. 800621e: f7ff fbc3 bl 80059a8 <follow_path>
  15520. 8006222: 4603 mov r3, r0
  15521. 8006224: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15522. #if !_FS_READONLY /* R/W configuration */
  15523. if (res == FR_OK) {
  15524. 8006228: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15525. 800622c: 2b00 cmp r3, #0
  15526. 800622e: d11a bne.n 8006266 <f_open+0x96>
  15527. if (dj.fn[NSFLAG] & NS_NONAME) { /* Origin directory itself? */
  15528. 8006230: f897 3047 ldrb.w r3, [r7, #71] ; 0x47
  15529. 8006234: b25b sxtb r3, r3
  15530. 8006236: 2b00 cmp r3, #0
  15531. 8006238: da03 bge.n 8006242 <f_open+0x72>
  15532. res = FR_INVALID_NAME;
  15533. 800623a: 2306 movs r3, #6
  15534. 800623c: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15535. 8006240: e011 b.n 8006266 <f_open+0x96>
  15536. }
  15537. #if _FS_LOCK != 0
  15538. else {
  15539. res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
  15540. 8006242: 79fb ldrb r3, [r7, #7]
  15541. 8006244: f023 0301 bic.w r3, r3, #1
  15542. 8006248: 2b00 cmp r3, #0
  15543. 800624a: bf14 ite ne
  15544. 800624c: 2301 movne r3, #1
  15545. 800624e: 2300 moveq r3, #0
  15546. 8006250: b2db uxtb r3, r3
  15547. 8006252: 461a mov r2, r3
  15548. 8006254: f107 0318 add.w r3, r7, #24
  15549. 8006258: 4611 mov r1, r2
  15550. 800625a: 4618 mov r0, r3
  15551. 800625c: f7fd ff48 bl 80040f0 <chk_lock>
  15552. 8006260: 4603 mov r3, r0
  15553. 8006262: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15554. }
  15555. #endif
  15556. }
  15557. /* Create or Open a file */
  15558. if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
  15559. 8006266: 79fb ldrb r3, [r7, #7]
  15560. 8006268: f003 031c and.w r3, r3, #28
  15561. 800626c: 2b00 cmp r3, #0
  15562. 800626e: d07f beq.n 8006370 <f_open+0x1a0>
  15563. if (res != FR_OK) { /* No file, create new */
  15564. 8006270: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15565. 8006274: 2b00 cmp r3, #0
  15566. 8006276: d017 beq.n 80062a8 <f_open+0xd8>
  15567. if (res == FR_NO_FILE) { /* There is no file to open, create a new entry */
  15568. 8006278: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15569. 800627c: 2b04 cmp r3, #4
  15570. 800627e: d10e bne.n 800629e <f_open+0xce>
  15571. #if _FS_LOCK != 0
  15572. res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
  15573. 8006280: f7fd ff90 bl 80041a4 <enq_lock>
  15574. 8006284: 4603 mov r3, r0
  15575. 8006286: 2b00 cmp r3, #0
  15576. 8006288: d006 beq.n 8006298 <f_open+0xc8>
  15577. 800628a: f107 0318 add.w r3, r7, #24
  15578. 800628e: 4618 mov r0, r3
  15579. 8006290: f7ff f8da bl 8005448 <dir_register>
  15580. 8006294: 4603 mov r3, r0
  15581. 8006296: e000 b.n 800629a <f_open+0xca>
  15582. 8006298: 2312 movs r3, #18
  15583. 800629a: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15584. #else
  15585. res = dir_register(&dj);
  15586. #endif
  15587. }
  15588. mode |= FA_CREATE_ALWAYS; /* File is created */
  15589. 800629e: 79fb ldrb r3, [r7, #7]
  15590. 80062a0: f043 0308 orr.w r3, r3, #8
  15591. 80062a4: 71fb strb r3, [r7, #7]
  15592. 80062a6: e010 b.n 80062ca <f_open+0xfa>
  15593. }
  15594. else { /* Any object is already existing */
  15595. if (dj.obj.attr & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */
  15596. 80062a8: 7fbb ldrb r3, [r7, #30]
  15597. 80062aa: f003 0311 and.w r3, r3, #17
  15598. 80062ae: 2b00 cmp r3, #0
  15599. 80062b0: d003 beq.n 80062ba <f_open+0xea>
  15600. res = FR_DENIED;
  15601. 80062b2: 2307 movs r3, #7
  15602. 80062b4: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15603. 80062b8: e007 b.n 80062ca <f_open+0xfa>
  15604. } else {
  15605. if (mode & FA_CREATE_NEW) res = FR_EXIST; /* Cannot create as new file */
  15606. 80062ba: 79fb ldrb r3, [r7, #7]
  15607. 80062bc: f003 0304 and.w r3, r3, #4
  15608. 80062c0: 2b00 cmp r3, #0
  15609. 80062c2: d002 beq.n 80062ca <f_open+0xfa>
  15610. 80062c4: 2308 movs r3, #8
  15611. 80062c6: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15612. }
  15613. }
  15614. if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
  15615. 80062ca: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15616. 80062ce: 2b00 cmp r3, #0
  15617. 80062d0: d168 bne.n 80063a4 <f_open+0x1d4>
  15618. 80062d2: 79fb ldrb r3, [r7, #7]
  15619. 80062d4: f003 0308 and.w r3, r3, #8
  15620. 80062d8: 2b00 cmp r3, #0
  15621. 80062da: d063 beq.n 80063a4 <f_open+0x1d4>
  15622. dw = GET_FATTIME();
  15623. 80062dc: f7fd fd16 bl 8003d0c <get_fattime>
  15624. 80062e0: 65b8 str r0, [r7, #88] ; 0x58
  15625. }
  15626. } else
  15627. #endif
  15628. {
  15629. /* Clean directory info */
  15630. st_dword(dj.dir + DIR_CrtTime, dw); /* Set created time */
  15631. 80062e2: 6bbb ldr r3, [r7, #56] ; 0x38
  15632. 80062e4: 330e adds r3, #14
  15633. 80062e6: 6db9 ldr r1, [r7, #88] ; 0x58
  15634. 80062e8: 4618 mov r0, r3
  15635. 80062ea: f7fd fe5c bl 8003fa6 <st_dword>
  15636. st_dword(dj.dir + DIR_ModTime, dw); /* Set modified time */
  15637. 80062ee: 6bbb ldr r3, [r7, #56] ; 0x38
  15638. 80062f0: 3316 adds r3, #22
  15639. 80062f2: 6db9 ldr r1, [r7, #88] ; 0x58
  15640. 80062f4: 4618 mov r0, r3
  15641. 80062f6: f7fd fe56 bl 8003fa6 <st_dword>
  15642. dj.dir[DIR_Attr] = AM_ARC; /* Reset attribute */
  15643. 80062fa: 6bbb ldr r3, [r7, #56] ; 0x38
  15644. 80062fc: 330b adds r3, #11
  15645. 80062fe: 2220 movs r2, #32
  15646. 8006300: 701a strb r2, [r3, #0]
  15647. cl = ld_clust(fs, dj.dir); /* Get cluster chain */
  15648. 8006302: 697b ldr r3, [r7, #20]
  15649. 8006304: 6bba ldr r2, [r7, #56] ; 0x38
  15650. 8006306: 4611 mov r1, r2
  15651. 8006308: 4618 mov r0, r3
  15652. 800630a: f7fe fe16 bl 8004f3a <ld_clust>
  15653. 800630e: 6578 str r0, [r7, #84] ; 0x54
  15654. st_clust(fs, dj.dir, 0); /* Reset file allocation info */
  15655. 8006310: 697b ldr r3, [r7, #20]
  15656. 8006312: 6bb9 ldr r1, [r7, #56] ; 0x38
  15657. 8006314: 2200 movs r2, #0
  15658. 8006316: 4618 mov r0, r3
  15659. 8006318: f7fe fe2e bl 8004f78 <st_clust>
  15660. st_dword(dj.dir + DIR_FileSize, 0);
  15661. 800631c: 6bbb ldr r3, [r7, #56] ; 0x38
  15662. 800631e: 331c adds r3, #28
  15663. 8006320: 2100 movs r1, #0
  15664. 8006322: 4618 mov r0, r3
  15665. 8006324: f7fd fe3f bl 8003fa6 <st_dword>
  15666. fs->wflag = 1;
  15667. 8006328: 697b ldr r3, [r7, #20]
  15668. 800632a: 2201 movs r2, #1
  15669. 800632c: 70da strb r2, [r3, #3]
  15670. if (cl) { /* Remove the cluster chain if exist */
  15671. 800632e: 6d7b ldr r3, [r7, #84] ; 0x54
  15672. 8006330: 2b00 cmp r3, #0
  15673. 8006332: d037 beq.n 80063a4 <f_open+0x1d4>
  15674. dw = fs->winsect;
  15675. 8006334: 697b ldr r3, [r7, #20]
  15676. 8006336: 6b5b ldr r3, [r3, #52] ; 0x34
  15677. 8006338: 65bb str r3, [r7, #88] ; 0x58
  15678. res = remove_chain(&dj.obj, cl, 0);
  15679. 800633a: f107 0318 add.w r3, r7, #24
  15680. 800633e: 2200 movs r2, #0
  15681. 8006340: 6d79 ldr r1, [r7, #84] ; 0x54
  15682. 8006342: 4618 mov r0, r3
  15683. 8006344: f7fe fb1f bl 8004986 <remove_chain>
  15684. 8006348: 4603 mov r3, r0
  15685. 800634a: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15686. if (res == FR_OK) {
  15687. 800634e: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15688. 8006352: 2b00 cmp r3, #0
  15689. 8006354: d126 bne.n 80063a4 <f_open+0x1d4>
  15690. res = move_window(fs, dw);
  15691. 8006356: 697b ldr r3, [r7, #20]
  15692. 8006358: 6db9 ldr r1, [r7, #88] ; 0x58
  15693. 800635a: 4618 mov r0, r3
  15694. 800635c: f7fe f870 bl 8004440 <move_window>
  15695. 8006360: 4603 mov r3, r0
  15696. 8006362: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15697. fs->last_clst = cl - 1; /* Reuse the cluster hole */
  15698. 8006366: 697b ldr r3, [r7, #20]
  15699. 8006368: 6d7a ldr r2, [r7, #84] ; 0x54
  15700. 800636a: 3a01 subs r2, #1
  15701. 800636c: 615a str r2, [r3, #20]
  15702. 800636e: e019 b.n 80063a4 <f_open+0x1d4>
  15703. }
  15704. }
  15705. }
  15706. }
  15707. else { /* Open an existing file */
  15708. if (res == FR_OK) { /* Following succeeded */
  15709. 8006370: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15710. 8006374: 2b00 cmp r3, #0
  15711. 8006376: d115 bne.n 80063a4 <f_open+0x1d4>
  15712. if (dj.obj.attr & AM_DIR) { /* It is a directory */
  15713. 8006378: 7fbb ldrb r3, [r7, #30]
  15714. 800637a: f003 0310 and.w r3, r3, #16
  15715. 800637e: 2b00 cmp r3, #0
  15716. 8006380: d003 beq.n 800638a <f_open+0x1ba>
  15717. res = FR_NO_FILE;
  15718. 8006382: 2304 movs r3, #4
  15719. 8006384: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15720. 8006388: e00c b.n 80063a4 <f_open+0x1d4>
  15721. } else {
  15722. if ((mode & FA_WRITE) && (dj.obj.attr & AM_RDO)) { /* R/O violation */
  15723. 800638a: 79fb ldrb r3, [r7, #7]
  15724. 800638c: f003 0302 and.w r3, r3, #2
  15725. 8006390: 2b00 cmp r3, #0
  15726. 8006392: d007 beq.n 80063a4 <f_open+0x1d4>
  15727. 8006394: 7fbb ldrb r3, [r7, #30]
  15728. 8006396: f003 0301 and.w r3, r3, #1
  15729. 800639a: 2b00 cmp r3, #0
  15730. 800639c: d002 beq.n 80063a4 <f_open+0x1d4>
  15731. res = FR_DENIED;
  15732. 800639e: 2307 movs r3, #7
  15733. 80063a0: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15734. }
  15735. }
  15736. }
  15737. }
  15738. if (res == FR_OK) {
  15739. 80063a4: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15740. 80063a8: 2b00 cmp r3, #0
  15741. 80063aa: d128 bne.n 80063fe <f_open+0x22e>
  15742. if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */
  15743. 80063ac: 79fb ldrb r3, [r7, #7]
  15744. 80063ae: f003 0308 and.w r3, r3, #8
  15745. 80063b2: 2b00 cmp r3, #0
  15746. 80063b4: d003 beq.n 80063be <f_open+0x1ee>
  15747. mode |= FA_MODIFIED;
  15748. 80063b6: 79fb ldrb r3, [r7, #7]
  15749. 80063b8: f043 0340 orr.w r3, r3, #64 ; 0x40
  15750. 80063bc: 71fb strb r3, [r7, #7]
  15751. fp->dir_sect = fs->winsect; /* Pointer to the directory entry */
  15752. 80063be: 697b ldr r3, [r7, #20]
  15753. 80063c0: 6b5a ldr r2, [r3, #52] ; 0x34
  15754. 80063c2: 68fb ldr r3, [r7, #12]
  15755. 80063c4: 625a str r2, [r3, #36] ; 0x24
  15756. fp->dir_ptr = dj.dir;
  15757. 80063c6: 6bba ldr r2, [r7, #56] ; 0x38
  15758. 80063c8: 68fb ldr r3, [r7, #12]
  15759. 80063ca: 629a str r2, [r3, #40] ; 0x28
  15760. #if _FS_LOCK != 0
  15761. fp->obj.lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
  15762. 80063cc: 79fb ldrb r3, [r7, #7]
  15763. 80063ce: f023 0301 bic.w r3, r3, #1
  15764. 80063d2: 2b00 cmp r3, #0
  15765. 80063d4: bf14 ite ne
  15766. 80063d6: 2301 movne r3, #1
  15767. 80063d8: 2300 moveq r3, #0
  15768. 80063da: b2db uxtb r3, r3
  15769. 80063dc: 461a mov r2, r3
  15770. 80063de: f107 0318 add.w r3, r7, #24
  15771. 80063e2: 4611 mov r1, r2
  15772. 80063e4: 4618 mov r0, r3
  15773. 80063e6: f7fd fefd bl 80041e4 <inc_lock>
  15774. 80063ea: 4602 mov r2, r0
  15775. 80063ec: 68fb ldr r3, [r7, #12]
  15776. 80063ee: 611a str r2, [r3, #16]
  15777. if (!fp->obj.lockid) res = FR_INT_ERR;
  15778. 80063f0: 68fb ldr r3, [r7, #12]
  15779. 80063f2: 691b ldr r3, [r3, #16]
  15780. 80063f4: 2b00 cmp r3, #0
  15781. 80063f6: d102 bne.n 80063fe <f_open+0x22e>
  15782. 80063f8: 2302 movs r3, #2
  15783. 80063fa: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15784. }
  15785. }
  15786. }
  15787. #endif
  15788. if (res == FR_OK) {
  15789. 80063fe: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15790. 8006402: 2b00 cmp r3, #0
  15791. 8006404: f040 80a3 bne.w 800654e <f_open+0x37e>
  15792. fp->obj.objsize = ld_qword(fs->dirbuf + XDIR_FileSize);
  15793. fp->obj.stat = fs->dirbuf[XDIR_GenFlags] & 2;
  15794. } else
  15795. #endif
  15796. {
  15797. fp->obj.sclust = ld_clust(fs, dj.dir); /* Get object allocation info */
  15798. 8006408: 697b ldr r3, [r7, #20]
  15799. 800640a: 6bba ldr r2, [r7, #56] ; 0x38
  15800. 800640c: 4611 mov r1, r2
  15801. 800640e: 4618 mov r0, r3
  15802. 8006410: f7fe fd93 bl 8004f3a <ld_clust>
  15803. 8006414: 4602 mov r2, r0
  15804. 8006416: 68fb ldr r3, [r7, #12]
  15805. 8006418: 609a str r2, [r3, #8]
  15806. fp->obj.objsize = ld_dword(dj.dir + DIR_FileSize);
  15807. 800641a: 6bbb ldr r3, [r7, #56] ; 0x38
  15808. 800641c: 331c adds r3, #28
  15809. 800641e: 4618 mov r0, r3
  15810. 8006420: f7fd fd85 bl 8003f2e <ld_dword>
  15811. 8006424: 4602 mov r2, r0
  15812. 8006426: 68fb ldr r3, [r7, #12]
  15813. 8006428: 60da str r2, [r3, #12]
  15814. }
  15815. #if _USE_FASTSEEK
  15816. fp->cltbl = 0; /* Disable fast seek mode */
  15817. 800642a: 68fb ldr r3, [r7, #12]
  15818. 800642c: 2200 movs r2, #0
  15819. 800642e: 62da str r2, [r3, #44] ; 0x2c
  15820. #endif
  15821. fp->obj.fs = fs; /* Validate the file object */
  15822. 8006430: 697a ldr r2, [r7, #20]
  15823. 8006432: 68fb ldr r3, [r7, #12]
  15824. 8006434: 601a str r2, [r3, #0]
  15825. fp->obj.id = fs->id;
  15826. 8006436: 697b ldr r3, [r7, #20]
  15827. 8006438: 88da ldrh r2, [r3, #6]
  15828. 800643a: 68fb ldr r3, [r7, #12]
  15829. 800643c: 809a strh r2, [r3, #4]
  15830. fp->flag = mode; /* Set file access mode */
  15831. 800643e: 68fb ldr r3, [r7, #12]
  15832. 8006440: 79fa ldrb r2, [r7, #7]
  15833. 8006442: 751a strb r2, [r3, #20]
  15834. fp->err = 0; /* Clear error flag */
  15835. 8006444: 68fb ldr r3, [r7, #12]
  15836. 8006446: 2200 movs r2, #0
  15837. 8006448: 755a strb r2, [r3, #21]
  15838. fp->sect = 0; /* Invalidate current data sector */
  15839. 800644a: 68fb ldr r3, [r7, #12]
  15840. 800644c: 2200 movs r2, #0
  15841. 800644e: 621a str r2, [r3, #32]
  15842. fp->fptr = 0; /* Set file pointer top of the file */
  15843. 8006450: 68fb ldr r3, [r7, #12]
  15844. 8006452: 2200 movs r2, #0
  15845. 8006454: 619a str r2, [r3, #24]
  15846. #if !_FS_READONLY
  15847. #if !_FS_TINY
  15848. mem_set(fp->buf, 0, _MAX_SS); /* Clear sector buffer */
  15849. 8006456: 68fb ldr r3, [r7, #12]
  15850. 8006458: 3330 adds r3, #48 ; 0x30
  15851. 800645a: f44f 5280 mov.w r2, #4096 ; 0x1000
  15852. 800645e: 2100 movs r1, #0
  15853. 8006460: 4618 mov r0, r3
  15854. 8006462: f7fd fdeb bl 800403c <mem_set>
  15855. #endif
  15856. if ((mode & FA_SEEKEND) && fp->obj.objsize > 0) { /* Seek to end of file if FA_OPEN_APPEND is specified */
  15857. 8006466: 79fb ldrb r3, [r7, #7]
  15858. 8006468: f003 0320 and.w r3, r3, #32
  15859. 800646c: 2b00 cmp r3, #0
  15860. 800646e: d06e beq.n 800654e <f_open+0x37e>
  15861. 8006470: 68fb ldr r3, [r7, #12]
  15862. 8006472: 68db ldr r3, [r3, #12]
  15863. 8006474: 2b00 cmp r3, #0
  15864. 8006476: d06a beq.n 800654e <f_open+0x37e>
  15865. fp->fptr = fp->obj.objsize; /* Offset to seek */
  15866. 8006478: 68fb ldr r3, [r7, #12]
  15867. 800647a: 68da ldr r2, [r3, #12]
  15868. 800647c: 68fb ldr r3, [r7, #12]
  15869. 800647e: 619a str r2, [r3, #24]
  15870. bcs = (DWORD)fs->csize * SS(fs); /* Cluster size in byte */
  15871. 8006480: 697b ldr r3, [r7, #20]
  15872. 8006482: 895b ldrh r3, [r3, #10]
  15873. 8006484: 461a mov r2, r3
  15874. 8006486: 697b ldr r3, [r7, #20]
  15875. 8006488: 899b ldrh r3, [r3, #12]
  15876. 800648a: fb03 f302 mul.w r3, r3, r2
  15877. 800648e: 653b str r3, [r7, #80] ; 0x50
  15878. clst = fp->obj.sclust; /* Follow the cluster chain */
  15879. 8006490: 68fb ldr r3, [r7, #12]
  15880. 8006492: 689b ldr r3, [r3, #8]
  15881. 8006494: 663b str r3, [r7, #96] ; 0x60
  15882. for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
  15883. 8006496: 68fb ldr r3, [r7, #12]
  15884. 8006498: 68db ldr r3, [r3, #12]
  15885. 800649a: 65fb str r3, [r7, #92] ; 0x5c
  15886. 800649c: e016 b.n 80064cc <f_open+0x2fc>
  15887. clst = get_fat(&fp->obj, clst);
  15888. 800649e: 68fb ldr r3, [r7, #12]
  15889. 80064a0: 6e39 ldr r1, [r7, #96] ; 0x60
  15890. 80064a2: 4618 mov r0, r3
  15891. 80064a4: f7fe f888 bl 80045b8 <get_fat>
  15892. 80064a8: 6638 str r0, [r7, #96] ; 0x60
  15893. if (clst <= 1) res = FR_INT_ERR;
  15894. 80064aa: 6e3b ldr r3, [r7, #96] ; 0x60
  15895. 80064ac: 2b01 cmp r3, #1
  15896. 80064ae: d802 bhi.n 80064b6 <f_open+0x2e6>
  15897. 80064b0: 2302 movs r3, #2
  15898. 80064b2: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15899. if (clst == 0xFFFFFFFF) res = FR_DISK_ERR;
  15900. 80064b6: 6e3b ldr r3, [r7, #96] ; 0x60
  15901. 80064b8: f1b3 3fff cmp.w r3, #4294967295
  15902. 80064bc: d102 bne.n 80064c4 <f_open+0x2f4>
  15903. 80064be: 2301 movs r3, #1
  15904. 80064c0: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15905. for (ofs = fp->obj.objsize; res == FR_OK && ofs > bcs; ofs -= bcs) {
  15906. 80064c4: 6dfa ldr r2, [r7, #92] ; 0x5c
  15907. 80064c6: 6d3b ldr r3, [r7, #80] ; 0x50
  15908. 80064c8: 1ad3 subs r3, r2, r3
  15909. 80064ca: 65fb str r3, [r7, #92] ; 0x5c
  15910. 80064cc: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15911. 80064d0: 2b00 cmp r3, #0
  15912. 80064d2: d103 bne.n 80064dc <f_open+0x30c>
  15913. 80064d4: 6dfa ldr r2, [r7, #92] ; 0x5c
  15914. 80064d6: 6d3b ldr r3, [r7, #80] ; 0x50
  15915. 80064d8: 429a cmp r2, r3
  15916. 80064da: d8e0 bhi.n 800649e <f_open+0x2ce>
  15917. }
  15918. fp->clust = clst;
  15919. 80064dc: 68fb ldr r3, [r7, #12]
  15920. 80064de: 6e3a ldr r2, [r7, #96] ; 0x60
  15921. 80064e0: 61da str r2, [r3, #28]
  15922. if (res == FR_OK && ofs % SS(fs)) { /* Fill sector buffer if not on the sector boundary */
  15923. 80064e2: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15924. 80064e6: 2b00 cmp r3, #0
  15925. 80064e8: d131 bne.n 800654e <f_open+0x37e>
  15926. 80064ea: 697b ldr r3, [r7, #20]
  15927. 80064ec: 899b ldrh r3, [r3, #12]
  15928. 80064ee: 461a mov r2, r3
  15929. 80064f0: 6dfb ldr r3, [r7, #92] ; 0x5c
  15930. 80064f2: fbb3 f1f2 udiv r1, r3, r2
  15931. 80064f6: fb02 f201 mul.w r2, r2, r1
  15932. 80064fa: 1a9b subs r3, r3, r2
  15933. 80064fc: 2b00 cmp r3, #0
  15934. 80064fe: d026 beq.n 800654e <f_open+0x37e>
  15935. if ((sc = clust2sect(fs, clst)) == 0) {
  15936. 8006500: 697b ldr r3, [r7, #20]
  15937. 8006502: 6e39 ldr r1, [r7, #96] ; 0x60
  15938. 8006504: 4618 mov r0, r3
  15939. 8006506: f7fe f839 bl 800457c <clust2sect>
  15940. 800650a: 64f8 str r0, [r7, #76] ; 0x4c
  15941. 800650c: 6cfb ldr r3, [r7, #76] ; 0x4c
  15942. 800650e: 2b00 cmp r3, #0
  15943. 8006510: d103 bne.n 800651a <f_open+0x34a>
  15944. res = FR_INT_ERR;
  15945. 8006512: 2302 movs r3, #2
  15946. 8006514: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15947. 8006518: e019 b.n 800654e <f_open+0x37e>
  15948. } else {
  15949. fp->sect = sc + (DWORD)(ofs / SS(fs));
  15950. 800651a: 697b ldr r3, [r7, #20]
  15951. 800651c: 899b ldrh r3, [r3, #12]
  15952. 800651e: 461a mov r2, r3
  15953. 8006520: 6dfb ldr r3, [r7, #92] ; 0x5c
  15954. 8006522: fbb3 f2f2 udiv r2, r3, r2
  15955. 8006526: 6cfb ldr r3, [r7, #76] ; 0x4c
  15956. 8006528: 441a add r2, r3
  15957. 800652a: 68fb ldr r3, [r7, #12]
  15958. 800652c: 621a str r2, [r3, #32]
  15959. #if !_FS_TINY
  15960. if (disk_read(fs->drv, fp->buf, fp->sect, 1) != RES_OK) res = FR_DISK_ERR;
  15961. 800652e: 697b ldr r3, [r7, #20]
  15962. 8006530: 7858 ldrb r0, [r3, #1]
  15963. 8006532: 68fb ldr r3, [r7, #12]
  15964. 8006534: f103 0130 add.w r1, r3, #48 ; 0x30
  15965. 8006538: 68fb ldr r3, [r7, #12]
  15966. 800653a: 6a1a ldr r2, [r3, #32]
  15967. 800653c: 2301 movs r3, #1
  15968. 800653e: f7fd fc81 bl 8003e44 <disk_read>
  15969. 8006542: 4603 mov r3, r0
  15970. 8006544: 2b00 cmp r3, #0
  15971. 8006546: d002 beq.n 800654e <f_open+0x37e>
  15972. 8006548: 2301 movs r3, #1
  15973. 800654a: f887 3067 strb.w r3, [r7, #103] ; 0x67
  15974. }
  15975. FREE_NAMBUF();
  15976. }
  15977. if (res != FR_OK) fp->obj.fs = 0; /* Invalidate file object on error */
  15978. 800654e: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15979. 8006552: 2b00 cmp r3, #0
  15980. 8006554: d002 beq.n 800655c <f_open+0x38c>
  15981. 8006556: 68fb ldr r3, [r7, #12]
  15982. 8006558: 2200 movs r2, #0
  15983. 800655a: 601a str r2, [r3, #0]
  15984. LEAVE_FF(fs, res);
  15985. 800655c: f897 3067 ldrb.w r3, [r7, #103] ; 0x67
  15986. }
  15987. 8006560: 4618 mov r0, r3
  15988. 8006562: 3768 adds r7, #104 ; 0x68
  15989. 8006564: 46bd mov sp, r7
  15990. 8006566: bd80 pop {r7, pc}
  15991. 08006568 <f_write>:
  15992. FIL* fp, /* Pointer to the file object */
  15993. const void* buff, /* Pointer to the data to be written */
  15994. UINT btw, /* Number of bytes to write */
  15995. UINT* bw /* Pointer to number of bytes written */
  15996. )
  15997. {
  15998. 8006568: b580 push {r7, lr}
  15999. 800656a: b08c sub sp, #48 ; 0x30
  16000. 800656c: af00 add r7, sp, #0
  16001. 800656e: 60f8 str r0, [r7, #12]
  16002. 8006570: 60b9 str r1, [r7, #8]
  16003. 8006572: 607a str r2, [r7, #4]
  16004. 8006574: 603b str r3, [r7, #0]
  16005. FRESULT res;
  16006. FATFS *fs;
  16007. DWORD clst, sect;
  16008. UINT wcnt, cc, csect;
  16009. const BYTE *wbuff = (const BYTE*)buff;
  16010. 8006576: 68bb ldr r3, [r7, #8]
  16011. 8006578: 61fb str r3, [r7, #28]
  16012. *bw = 0; /* Clear write byte counter */
  16013. 800657a: 683b ldr r3, [r7, #0]
  16014. 800657c: 2200 movs r2, #0
  16015. 800657e: 601a str r2, [r3, #0]
  16016. res = validate(&fp->obj, &fs); /* Check validity of the file object */
  16017. 8006580: 68fb ldr r3, [r7, #12]
  16018. 8006582: f107 0210 add.w r2, r7, #16
  16019. 8006586: 4611 mov r1, r2
  16020. 8006588: 4618 mov r0, r3
  16021. 800658a: f7ff fda5 bl 80060d8 <validate>
  16022. 800658e: 4603 mov r3, r0
  16023. 8006590: f887 302f strb.w r3, [r7, #47] ; 0x2f
  16024. if (res != FR_OK || (res = (FRESULT)fp->err) != FR_OK) LEAVE_FF(fs, res); /* Check validity */
  16025. 8006594: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  16026. 8006598: 2b00 cmp r3, #0
  16027. 800659a: d107 bne.n 80065ac <f_write+0x44>
  16028. 800659c: 68fb ldr r3, [r7, #12]
  16029. 800659e: 7d5b ldrb r3, [r3, #21]
  16030. 80065a0: f887 302f strb.w r3, [r7, #47] ; 0x2f
  16031. 80065a4: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  16032. 80065a8: 2b00 cmp r3, #0
  16033. 80065aa: d002 beq.n 80065b2 <f_write+0x4a>
  16034. 80065ac: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
  16035. 80065b0: e16a b.n 8006888 <f_write+0x320>
  16036. if (!(fp->flag & FA_WRITE)) LEAVE_FF(fs, FR_DENIED); /* Check access mode */
  16037. 80065b2: 68fb ldr r3, [r7, #12]
  16038. 80065b4: 7d1b ldrb r3, [r3, #20]
  16039. 80065b6: f003 0302 and.w r3, r3, #2
  16040. 80065ba: 2b00 cmp r3, #0
  16041. 80065bc: d101 bne.n 80065c2 <f_write+0x5a>
  16042. 80065be: 2307 movs r3, #7
  16043. 80065c0: e162 b.n 8006888 <f_write+0x320>
  16044. /* Check fptr wrap-around (file size cannot reach 4GiB on FATxx) */
  16045. if ((!_FS_EXFAT || fs->fs_type != FS_EXFAT) && (DWORD)(fp->fptr + btw) < (DWORD)fp->fptr) {
  16046. 80065c2: 68fb ldr r3, [r7, #12]
  16047. 80065c4: 699a ldr r2, [r3, #24]
  16048. 80065c6: 687b ldr r3, [r7, #4]
  16049. 80065c8: 441a add r2, r3
  16050. 80065ca: 68fb ldr r3, [r7, #12]
  16051. 80065cc: 699b ldr r3, [r3, #24]
  16052. 80065ce: 429a cmp r2, r3
  16053. 80065d0: f080 814c bcs.w 800686c <f_write+0x304>
  16054. btw = (UINT)(0xFFFFFFFF - (DWORD)fp->fptr);
  16055. 80065d4: 68fb ldr r3, [r7, #12]
  16056. 80065d6: 699b ldr r3, [r3, #24]
  16057. 80065d8: 43db mvns r3, r3
  16058. 80065da: 607b str r3, [r7, #4]
  16059. }
  16060. for ( ; btw; /* Repeat until all data written */
  16061. 80065dc: e146 b.n 800686c <f_write+0x304>
  16062. wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) {
  16063. if (fp->fptr % SS(fs) == 0) { /* On the sector boundary? */
  16064. 80065de: 68fb ldr r3, [r7, #12]
  16065. 80065e0: 699b ldr r3, [r3, #24]
  16066. 80065e2: 693a ldr r2, [r7, #16]
  16067. 80065e4: 8992 ldrh r2, [r2, #12]
  16068. 80065e6: fbb3 f1f2 udiv r1, r3, r2
  16069. 80065ea: fb02 f201 mul.w r2, r2, r1
  16070. 80065ee: 1a9b subs r3, r3, r2
  16071. 80065f0: 2b00 cmp r3, #0
  16072. 80065f2: f040 80f1 bne.w 80067d8 <f_write+0x270>
  16073. csect = (UINT)(fp->fptr / SS(fs)) & (fs->csize - 1); /* Sector offset in the cluster */
  16074. 80065f6: 68fb ldr r3, [r7, #12]
  16075. 80065f8: 699b ldr r3, [r3, #24]
  16076. 80065fa: 693a ldr r2, [r7, #16]
  16077. 80065fc: 8992 ldrh r2, [r2, #12]
  16078. 80065fe: fbb3 f3f2 udiv r3, r3, r2
  16079. 8006602: 693a ldr r2, [r7, #16]
  16080. 8006604: 8952 ldrh r2, [r2, #10]
  16081. 8006606: 3a01 subs r2, #1
  16082. 8006608: 4013 ands r3, r2
  16083. 800660a: 61bb str r3, [r7, #24]
  16084. if (csect == 0) { /* On the cluster boundary? */
  16085. 800660c: 69bb ldr r3, [r7, #24]
  16086. 800660e: 2b00 cmp r3, #0
  16087. 8006610: d143 bne.n 800669a <f_write+0x132>
  16088. if (fp->fptr == 0) { /* On the top of the file? */
  16089. 8006612: 68fb ldr r3, [r7, #12]
  16090. 8006614: 699b ldr r3, [r3, #24]
  16091. 8006616: 2b00 cmp r3, #0
  16092. 8006618: d10c bne.n 8006634 <f_write+0xcc>
  16093. clst = fp->obj.sclust; /* Follow from the origin */
  16094. 800661a: 68fb ldr r3, [r7, #12]
  16095. 800661c: 689b ldr r3, [r3, #8]
  16096. 800661e: 62bb str r3, [r7, #40] ; 0x28
  16097. if (clst == 0) { /* If no cluster is allocated, */
  16098. 8006620: 6abb ldr r3, [r7, #40] ; 0x28
  16099. 8006622: 2b00 cmp r3, #0
  16100. 8006624: d11a bne.n 800665c <f_write+0xf4>
  16101. clst = create_chain(&fp->obj, 0); /* create a new cluster chain */
  16102. 8006626: 68fb ldr r3, [r7, #12]
  16103. 8006628: 2100 movs r1, #0
  16104. 800662a: 4618 mov r0, r3
  16105. 800662c: f7fe fa10 bl 8004a50 <create_chain>
  16106. 8006630: 62b8 str r0, [r7, #40] ; 0x28
  16107. 8006632: e013 b.n 800665c <f_write+0xf4>
  16108. }
  16109. } else { /* On the middle or end of the file */
  16110. #if _USE_FASTSEEK
  16111. if (fp->cltbl) {
  16112. 8006634: 68fb ldr r3, [r7, #12]
  16113. 8006636: 6adb ldr r3, [r3, #44] ; 0x2c
  16114. 8006638: 2b00 cmp r3, #0
  16115. 800663a: d007 beq.n 800664c <f_write+0xe4>
  16116. clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
  16117. 800663c: 68fb ldr r3, [r7, #12]
  16118. 800663e: 699b ldr r3, [r3, #24]
  16119. 8006640: 4619 mov r1, r3
  16120. 8006642: 68f8 ldr r0, [r7, #12]
  16121. 8006644: f7fe fa9c bl 8004b80 <clmt_clust>
  16122. 8006648: 62b8 str r0, [r7, #40] ; 0x28
  16123. 800664a: e007 b.n 800665c <f_write+0xf4>
  16124. } else
  16125. #endif
  16126. {
  16127. clst = create_chain(&fp->obj, fp->clust); /* Follow or stretch cluster chain on the FAT */
  16128. 800664c: 68fa ldr r2, [r7, #12]
  16129. 800664e: 68fb ldr r3, [r7, #12]
  16130. 8006650: 69db ldr r3, [r3, #28]
  16131. 8006652: 4619 mov r1, r3
  16132. 8006654: 4610 mov r0, r2
  16133. 8006656: f7fe f9fb bl 8004a50 <create_chain>
  16134. 800665a: 62b8 str r0, [r7, #40] ; 0x28
  16135. }
  16136. }
  16137. if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
  16138. 800665c: 6abb ldr r3, [r7, #40] ; 0x28
  16139. 800665e: 2b00 cmp r3, #0
  16140. 8006660: f000 8109 beq.w 8006876 <f_write+0x30e>
  16141. if (clst == 1) ABORT(fs, FR_INT_ERR);
  16142. 8006664: 6abb ldr r3, [r7, #40] ; 0x28
  16143. 8006666: 2b01 cmp r3, #1
  16144. 8006668: d104 bne.n 8006674 <f_write+0x10c>
  16145. 800666a: 68fb ldr r3, [r7, #12]
  16146. 800666c: 2202 movs r2, #2
  16147. 800666e: 755a strb r2, [r3, #21]
  16148. 8006670: 2302 movs r3, #2
  16149. 8006672: e109 b.n 8006888 <f_write+0x320>
  16150. if (clst == 0xFFFFFFFF) ABORT(fs, FR_DISK_ERR);
  16151. 8006674: 6abb ldr r3, [r7, #40] ; 0x28
  16152. 8006676: f1b3 3fff cmp.w r3, #4294967295
  16153. 800667a: d104 bne.n 8006686 <f_write+0x11e>
  16154. 800667c: 68fb ldr r3, [r7, #12]
  16155. 800667e: 2201 movs r2, #1
  16156. 8006680: 755a strb r2, [r3, #21]
  16157. 8006682: 2301 movs r3, #1
  16158. 8006684: e100 b.n 8006888 <f_write+0x320>
  16159. fp->clust = clst; /* Update current cluster */
  16160. 8006686: 68fb ldr r3, [r7, #12]
  16161. 8006688: 6aba ldr r2, [r7, #40] ; 0x28
  16162. 800668a: 61da str r2, [r3, #28]
  16163. if (fp->obj.sclust == 0) fp->obj.sclust = clst; /* Set start cluster if the first write */
  16164. 800668c: 68fb ldr r3, [r7, #12]
  16165. 800668e: 689b ldr r3, [r3, #8]
  16166. 8006690: 2b00 cmp r3, #0
  16167. 8006692: d102 bne.n 800669a <f_write+0x132>
  16168. 8006694: 68fb ldr r3, [r7, #12]
  16169. 8006696: 6aba ldr r2, [r7, #40] ; 0x28
  16170. 8006698: 609a str r2, [r3, #8]
  16171. }
  16172. #if _FS_TINY
  16173. if (fs->winsect == fp->sect && sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Write-back sector cache */
  16174. #else
  16175. if (fp->flag & FA_DIRTY) { /* Write-back sector cache */
  16176. 800669a: 68fb ldr r3, [r7, #12]
  16177. 800669c: 7d1b ldrb r3, [r3, #20]
  16178. 800669e: b25b sxtb r3, r3
  16179. 80066a0: 2b00 cmp r3, #0
  16180. 80066a2: da18 bge.n 80066d6 <f_write+0x16e>
  16181. if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) ABORT(fs, FR_DISK_ERR);
  16182. 80066a4: 693b ldr r3, [r7, #16]
  16183. 80066a6: 7858 ldrb r0, [r3, #1]
  16184. 80066a8: 68fb ldr r3, [r7, #12]
  16185. 80066aa: f103 0130 add.w r1, r3, #48 ; 0x30
  16186. 80066ae: 68fb ldr r3, [r7, #12]
  16187. 80066b0: 6a1a ldr r2, [r3, #32]
  16188. 80066b2: 2301 movs r3, #1
  16189. 80066b4: f7fd fbe6 bl 8003e84 <disk_write>
  16190. 80066b8: 4603 mov r3, r0
  16191. 80066ba: 2b00 cmp r3, #0
  16192. 80066bc: d004 beq.n 80066c8 <f_write+0x160>
  16193. 80066be: 68fb ldr r3, [r7, #12]
  16194. 80066c0: 2201 movs r2, #1
  16195. 80066c2: 755a strb r2, [r3, #21]
  16196. 80066c4: 2301 movs r3, #1
  16197. 80066c6: e0df b.n 8006888 <f_write+0x320>
  16198. fp->flag &= (BYTE)~FA_DIRTY;
  16199. 80066c8: 68fb ldr r3, [r7, #12]
  16200. 80066ca: 7d1b ldrb r3, [r3, #20]
  16201. 80066cc: f003 037f and.w r3, r3, #127 ; 0x7f
  16202. 80066d0: b2da uxtb r2, r3
  16203. 80066d2: 68fb ldr r3, [r7, #12]
  16204. 80066d4: 751a strb r2, [r3, #20]
  16205. }
  16206. #endif
  16207. sect = clust2sect(fs, fp->clust); /* Get current sector */
  16208. 80066d6: 693a ldr r2, [r7, #16]
  16209. 80066d8: 68fb ldr r3, [r7, #12]
  16210. 80066da: 69db ldr r3, [r3, #28]
  16211. 80066dc: 4619 mov r1, r3
  16212. 80066de: 4610 mov r0, r2
  16213. 80066e0: f7fd ff4c bl 800457c <clust2sect>
  16214. 80066e4: 6178 str r0, [r7, #20]
  16215. if (!sect) ABORT(fs, FR_INT_ERR);
  16216. 80066e6: 697b ldr r3, [r7, #20]
  16217. 80066e8: 2b00 cmp r3, #0
  16218. 80066ea: d104 bne.n 80066f6 <f_write+0x18e>
  16219. 80066ec: 68fb ldr r3, [r7, #12]
  16220. 80066ee: 2202 movs r2, #2
  16221. 80066f0: 755a strb r2, [r3, #21]
  16222. 80066f2: 2302 movs r3, #2
  16223. 80066f4: e0c8 b.n 8006888 <f_write+0x320>
  16224. sect += csect;
  16225. 80066f6: 697a ldr r2, [r7, #20]
  16226. 80066f8: 69bb ldr r3, [r7, #24]
  16227. 80066fa: 4413 add r3, r2
  16228. 80066fc: 617b str r3, [r7, #20]
  16229. cc = btw / SS(fs); /* When remaining bytes >= sector size, */
  16230. 80066fe: 693b ldr r3, [r7, #16]
  16231. 8006700: 899b ldrh r3, [r3, #12]
  16232. 8006702: 461a mov r2, r3
  16233. 8006704: 687b ldr r3, [r7, #4]
  16234. 8006706: fbb3 f3f2 udiv r3, r3, r2
  16235. 800670a: 623b str r3, [r7, #32]
  16236. if (cc) { /* Write maximum contiguous sectors directly */
  16237. 800670c: 6a3b ldr r3, [r7, #32]
  16238. 800670e: 2b00 cmp r3, #0
  16239. 8006710: d043 beq.n 800679a <f_write+0x232>
  16240. if (csect + cc > fs->csize) { /* Clip at cluster boundary */
  16241. 8006712: 69ba ldr r2, [r7, #24]
  16242. 8006714: 6a3b ldr r3, [r7, #32]
  16243. 8006716: 4413 add r3, r2
  16244. 8006718: 693a ldr r2, [r7, #16]
  16245. 800671a: 8952 ldrh r2, [r2, #10]
  16246. 800671c: 4293 cmp r3, r2
  16247. 800671e: d905 bls.n 800672c <f_write+0x1c4>
  16248. cc = fs->csize - csect;
  16249. 8006720: 693b ldr r3, [r7, #16]
  16250. 8006722: 895b ldrh r3, [r3, #10]
  16251. 8006724: 461a mov r2, r3
  16252. 8006726: 69bb ldr r3, [r7, #24]
  16253. 8006728: 1ad3 subs r3, r2, r3
  16254. 800672a: 623b str r3, [r7, #32]
  16255. }
  16256. if (disk_write(fs->drv, wbuff, sect, cc) != RES_OK) ABORT(fs, FR_DISK_ERR);
  16257. 800672c: 693b ldr r3, [r7, #16]
  16258. 800672e: 7858 ldrb r0, [r3, #1]
  16259. 8006730: 6a3b ldr r3, [r7, #32]
  16260. 8006732: 697a ldr r2, [r7, #20]
  16261. 8006734: 69f9 ldr r1, [r7, #28]
  16262. 8006736: f7fd fba5 bl 8003e84 <disk_write>
  16263. 800673a: 4603 mov r3, r0
  16264. 800673c: 2b00 cmp r3, #0
  16265. 800673e: d004 beq.n 800674a <f_write+0x1e2>
  16266. 8006740: 68fb ldr r3, [r7, #12]
  16267. 8006742: 2201 movs r2, #1
  16268. 8006744: 755a strb r2, [r3, #21]
  16269. 8006746: 2301 movs r3, #1
  16270. 8006748: e09e b.n 8006888 <f_write+0x320>
  16271. if (fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
  16272. mem_cpy(fs->win, wbuff + ((fs->winsect - sect) * SS(fs)), SS(fs));
  16273. fs->wflag = 0;
  16274. }
  16275. #else
  16276. if (fp->sect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
  16277. 800674a: 68fb ldr r3, [r7, #12]
  16278. 800674c: 6a1a ldr r2, [r3, #32]
  16279. 800674e: 697b ldr r3, [r7, #20]
  16280. 8006750: 1ad3 subs r3, r2, r3
  16281. 8006752: 6a3a ldr r2, [r7, #32]
  16282. 8006754: 429a cmp r2, r3
  16283. 8006756: d918 bls.n 800678a <f_write+0x222>
  16284. mem_cpy(fp->buf, wbuff + ((fp->sect - sect) * SS(fs)), SS(fs));
  16285. 8006758: 68fb ldr r3, [r7, #12]
  16286. 800675a: f103 0030 add.w r0, r3, #48 ; 0x30
  16287. 800675e: 68fb ldr r3, [r7, #12]
  16288. 8006760: 6a1a ldr r2, [r3, #32]
  16289. 8006762: 697b ldr r3, [r7, #20]
  16290. 8006764: 1ad3 subs r3, r2, r3
  16291. 8006766: 693a ldr r2, [r7, #16]
  16292. 8006768: 8992 ldrh r2, [r2, #12]
  16293. 800676a: fb02 f303 mul.w r3, r2, r3
  16294. 800676e: 69fa ldr r2, [r7, #28]
  16295. 8006770: 18d1 adds r1, r2, r3
  16296. 8006772: 693b ldr r3, [r7, #16]
  16297. 8006774: 899b ldrh r3, [r3, #12]
  16298. 8006776: 461a mov r2, r3
  16299. 8006778: f7fd fc40 bl 8003ffc <mem_cpy>
  16300. fp->flag &= (BYTE)~FA_DIRTY;
  16301. 800677c: 68fb ldr r3, [r7, #12]
  16302. 800677e: 7d1b ldrb r3, [r3, #20]
  16303. 8006780: f003 037f and.w r3, r3, #127 ; 0x7f
  16304. 8006784: b2da uxtb r2, r3
  16305. 8006786: 68fb ldr r3, [r7, #12]
  16306. 8006788: 751a strb r2, [r3, #20]
  16307. }
  16308. #endif
  16309. #endif
  16310. wcnt = SS(fs) * cc; /* Number of bytes transferred */
  16311. 800678a: 693b ldr r3, [r7, #16]
  16312. 800678c: 899b ldrh r3, [r3, #12]
  16313. 800678e: 461a mov r2, r3
  16314. 8006790: 6a3b ldr r3, [r7, #32]
  16315. 8006792: fb02 f303 mul.w r3, r2, r3
  16316. 8006796: 627b str r3, [r7, #36] ; 0x24
  16317. continue;
  16318. 8006798: e04b b.n 8006832 <f_write+0x2ca>
  16319. if (fp->fptr >= fp->obj.objsize) { /* Avoid silly cache filling on the growing edge */
  16320. if (sync_window(fs) != FR_OK) ABORT(fs, FR_DISK_ERR);
  16321. fs->winsect = sect;
  16322. }
  16323. #else
  16324. if (fp->sect != sect && /* Fill sector cache with file data */
  16325. 800679a: 68fb ldr r3, [r7, #12]
  16326. 800679c: 6a1b ldr r3, [r3, #32]
  16327. 800679e: 697a ldr r2, [r7, #20]
  16328. 80067a0: 429a cmp r2, r3
  16329. 80067a2: d016 beq.n 80067d2 <f_write+0x26a>
  16330. fp->fptr < fp->obj.objsize &&
  16331. 80067a4: 68fb ldr r3, [r7, #12]
  16332. 80067a6: 699a ldr r2, [r3, #24]
  16333. 80067a8: 68fb ldr r3, [r7, #12]
  16334. 80067aa: 68db ldr r3, [r3, #12]
  16335. if (fp->sect != sect && /* Fill sector cache with file data */
  16336. 80067ac: 429a cmp r2, r3
  16337. 80067ae: d210 bcs.n 80067d2 <f_write+0x26a>
  16338. disk_read(fs->drv, fp->buf, sect, 1) != RES_OK) {
  16339. 80067b0: 693b ldr r3, [r7, #16]
  16340. 80067b2: 7858 ldrb r0, [r3, #1]
  16341. 80067b4: 68fb ldr r3, [r7, #12]
  16342. 80067b6: f103 0130 add.w r1, r3, #48 ; 0x30
  16343. 80067ba: 2301 movs r3, #1
  16344. 80067bc: 697a ldr r2, [r7, #20]
  16345. 80067be: f7fd fb41 bl 8003e44 <disk_read>
  16346. 80067c2: 4603 mov r3, r0
  16347. fp->fptr < fp->obj.objsize &&
  16348. 80067c4: 2b00 cmp r3, #0
  16349. 80067c6: d004 beq.n 80067d2 <f_write+0x26a>
  16350. ABORT(fs, FR_DISK_ERR);
  16351. 80067c8: 68fb ldr r3, [r7, #12]
  16352. 80067ca: 2201 movs r2, #1
  16353. 80067cc: 755a strb r2, [r3, #21]
  16354. 80067ce: 2301 movs r3, #1
  16355. 80067d0: e05a b.n 8006888 <f_write+0x320>
  16356. }
  16357. #endif
  16358. fp->sect = sect;
  16359. 80067d2: 68fb ldr r3, [r7, #12]
  16360. 80067d4: 697a ldr r2, [r7, #20]
  16361. 80067d6: 621a str r2, [r3, #32]
  16362. }
  16363. wcnt = SS(fs) - (UINT)fp->fptr % SS(fs); /* Number of bytes left in the sector */
  16364. 80067d8: 693b ldr r3, [r7, #16]
  16365. 80067da: 899b ldrh r3, [r3, #12]
  16366. 80067dc: 4618 mov r0, r3
  16367. 80067de: 68fb ldr r3, [r7, #12]
  16368. 80067e0: 699b ldr r3, [r3, #24]
  16369. 80067e2: 693a ldr r2, [r7, #16]
  16370. 80067e4: 8992 ldrh r2, [r2, #12]
  16371. 80067e6: fbb3 f1f2 udiv r1, r3, r2
  16372. 80067ea: fb02 f201 mul.w r2, r2, r1
  16373. 80067ee: 1a9b subs r3, r3, r2
  16374. 80067f0: 1ac3 subs r3, r0, r3
  16375. 80067f2: 627b str r3, [r7, #36] ; 0x24
  16376. if (wcnt > btw) wcnt = btw; /* Clip it by btw if needed */
  16377. 80067f4: 6a7a ldr r2, [r7, #36] ; 0x24
  16378. 80067f6: 687b ldr r3, [r7, #4]
  16379. 80067f8: 429a cmp r2, r3
  16380. 80067fa: d901 bls.n 8006800 <f_write+0x298>
  16381. 80067fc: 687b ldr r3, [r7, #4]
  16382. 80067fe: 627b str r3, [r7, #36] ; 0x24
  16383. #if _FS_TINY
  16384. if (move_window(fs, fp->sect) != FR_OK) ABORT(fs, FR_DISK_ERR); /* Move sector window */
  16385. mem_cpy(fs->win + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */
  16386. fs->wflag = 1;
  16387. #else
  16388. mem_cpy(fp->buf + fp->fptr % SS(fs), wbuff, wcnt); /* Fit data to the sector */
  16389. 8006800: 68fb ldr r3, [r7, #12]
  16390. 8006802: f103 0130 add.w r1, r3, #48 ; 0x30
  16391. 8006806: 68fb ldr r3, [r7, #12]
  16392. 8006808: 699b ldr r3, [r3, #24]
  16393. 800680a: 693a ldr r2, [r7, #16]
  16394. 800680c: 8992 ldrh r2, [r2, #12]
  16395. 800680e: fbb3 f0f2 udiv r0, r3, r2
  16396. 8006812: fb02 f200 mul.w r2, r2, r0
  16397. 8006816: 1a9b subs r3, r3, r2
  16398. 8006818: 440b add r3, r1
  16399. 800681a: 6a7a ldr r2, [r7, #36] ; 0x24
  16400. 800681c: 69f9 ldr r1, [r7, #28]
  16401. 800681e: 4618 mov r0, r3
  16402. 8006820: f7fd fbec bl 8003ffc <mem_cpy>
  16403. fp->flag |= FA_DIRTY;
  16404. 8006824: 68fb ldr r3, [r7, #12]
  16405. 8006826: 7d1b ldrb r3, [r3, #20]
  16406. 8006828: f063 037f orn r3, r3, #127 ; 0x7f
  16407. 800682c: b2da uxtb r2, r3
  16408. 800682e: 68fb ldr r3, [r7, #12]
  16409. 8006830: 751a strb r2, [r3, #20]
  16410. wbuff += wcnt, fp->fptr += wcnt, fp->obj.objsize = (fp->fptr > fp->obj.objsize) ? fp->fptr : fp->obj.objsize, *bw += wcnt, btw -= wcnt) {
  16411. 8006832: 69fa ldr r2, [r7, #28]
  16412. 8006834: 6a7b ldr r3, [r7, #36] ; 0x24
  16413. 8006836: 4413 add r3, r2
  16414. 8006838: 61fb str r3, [r7, #28]
  16415. 800683a: 68fb ldr r3, [r7, #12]
  16416. 800683c: 699a ldr r2, [r3, #24]
  16417. 800683e: 6a7b ldr r3, [r7, #36] ; 0x24
  16418. 8006840: 441a add r2, r3
  16419. 8006842: 68fb ldr r3, [r7, #12]
  16420. 8006844: 619a str r2, [r3, #24]
  16421. 8006846: 68fb ldr r3, [r7, #12]
  16422. 8006848: 68da ldr r2, [r3, #12]
  16423. 800684a: 68fb ldr r3, [r7, #12]
  16424. 800684c: 699b ldr r3, [r3, #24]
  16425. 800684e: 429a cmp r2, r3
  16426. 8006850: bf38 it cc
  16427. 8006852: 461a movcc r2, r3
  16428. 8006854: 68fb ldr r3, [r7, #12]
  16429. 8006856: 60da str r2, [r3, #12]
  16430. 8006858: 683b ldr r3, [r7, #0]
  16431. 800685a: 681a ldr r2, [r3, #0]
  16432. 800685c: 6a7b ldr r3, [r7, #36] ; 0x24
  16433. 800685e: 441a add r2, r3
  16434. 8006860: 683b ldr r3, [r7, #0]
  16435. 8006862: 601a str r2, [r3, #0]
  16436. 8006864: 687a ldr r2, [r7, #4]
  16437. 8006866: 6a7b ldr r3, [r7, #36] ; 0x24
  16438. 8006868: 1ad3 subs r3, r2, r3
  16439. 800686a: 607b str r3, [r7, #4]
  16440. for ( ; btw; /* Repeat until all data written */
  16441. 800686c: 687b ldr r3, [r7, #4]
  16442. 800686e: 2b00 cmp r3, #0
  16443. 8006870: f47f aeb5 bne.w 80065de <f_write+0x76>
  16444. 8006874: e000 b.n 8006878 <f_write+0x310>
  16445. if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
  16446. 8006876: bf00 nop
  16447. #endif
  16448. }
  16449. fp->flag |= FA_MODIFIED; /* Set file change flag */
  16450. 8006878: 68fb ldr r3, [r7, #12]
  16451. 800687a: 7d1b ldrb r3, [r3, #20]
  16452. 800687c: f043 0340 orr.w r3, r3, #64 ; 0x40
  16453. 8006880: b2da uxtb r2, r3
  16454. 8006882: 68fb ldr r3, [r7, #12]
  16455. 8006884: 751a strb r2, [r3, #20]
  16456. LEAVE_FF(fs, FR_OK);
  16457. 8006886: 2300 movs r3, #0
  16458. }
  16459. 8006888: 4618 mov r0, r3
  16460. 800688a: 3730 adds r7, #48 ; 0x30
  16461. 800688c: 46bd mov sp, r7
  16462. 800688e: bd80 pop {r7, pc}
  16463. 08006890 <f_sync>:
  16464. /*-----------------------------------------------------------------------*/
  16465. FRESULT f_sync (
  16466. FIL* fp /* Pointer to the file object */
  16467. )
  16468. {
  16469. 8006890: b580 push {r7, lr}
  16470. 8006892: b086 sub sp, #24
  16471. 8006894: af00 add r7, sp, #0
  16472. 8006896: 6078 str r0, [r7, #4]
  16473. #if _FS_EXFAT
  16474. DIR dj;
  16475. DEF_NAMBUF
  16476. #endif
  16477. res = validate(&fp->obj, &fs); /* Check validity of the file object */
  16478. 8006898: 687b ldr r3, [r7, #4]
  16479. 800689a: f107 0208 add.w r2, r7, #8
  16480. 800689e: 4611 mov r1, r2
  16481. 80068a0: 4618 mov r0, r3
  16482. 80068a2: f7ff fc19 bl 80060d8 <validate>
  16483. 80068a6: 4603 mov r3, r0
  16484. 80068a8: 75fb strb r3, [r7, #23]
  16485. if (res == FR_OK) {
  16486. 80068aa: 7dfb ldrb r3, [r7, #23]
  16487. 80068ac: 2b00 cmp r3, #0
  16488. 80068ae: d168 bne.n 8006982 <f_sync+0xf2>
  16489. if (fp->flag & FA_MODIFIED) { /* Is there any change to the file? */
  16490. 80068b0: 687b ldr r3, [r7, #4]
  16491. 80068b2: 7d1b ldrb r3, [r3, #20]
  16492. 80068b4: f003 0340 and.w r3, r3, #64 ; 0x40
  16493. 80068b8: 2b00 cmp r3, #0
  16494. 80068ba: d062 beq.n 8006982 <f_sync+0xf2>
  16495. #if !_FS_TINY
  16496. if (fp->flag & FA_DIRTY) { /* Write-back cached data if needed */
  16497. 80068bc: 687b ldr r3, [r7, #4]
  16498. 80068be: 7d1b ldrb r3, [r3, #20]
  16499. 80068c0: b25b sxtb r3, r3
  16500. 80068c2: 2b00 cmp r3, #0
  16501. 80068c4: da15 bge.n 80068f2 <f_sync+0x62>
  16502. if (disk_write(fs->drv, fp->buf, fp->sect, 1) != RES_OK) LEAVE_FF(fs, FR_DISK_ERR);
  16503. 80068c6: 68bb ldr r3, [r7, #8]
  16504. 80068c8: 7858 ldrb r0, [r3, #1]
  16505. 80068ca: 687b ldr r3, [r7, #4]
  16506. 80068cc: f103 0130 add.w r1, r3, #48 ; 0x30
  16507. 80068d0: 687b ldr r3, [r7, #4]
  16508. 80068d2: 6a1a ldr r2, [r3, #32]
  16509. 80068d4: 2301 movs r3, #1
  16510. 80068d6: f7fd fad5 bl 8003e84 <disk_write>
  16511. 80068da: 4603 mov r3, r0
  16512. 80068dc: 2b00 cmp r3, #0
  16513. 80068de: d001 beq.n 80068e4 <f_sync+0x54>
  16514. 80068e0: 2301 movs r3, #1
  16515. 80068e2: e04f b.n 8006984 <f_sync+0xf4>
  16516. fp->flag &= (BYTE)~FA_DIRTY;
  16517. 80068e4: 687b ldr r3, [r7, #4]
  16518. 80068e6: 7d1b ldrb r3, [r3, #20]
  16519. 80068e8: f003 037f and.w r3, r3, #127 ; 0x7f
  16520. 80068ec: b2da uxtb r2, r3
  16521. 80068ee: 687b ldr r3, [r7, #4]
  16522. 80068f0: 751a strb r2, [r3, #20]
  16523. }
  16524. #endif
  16525. /* Update the directory entry */
  16526. tm = GET_FATTIME(); /* Modified time */
  16527. 80068f2: f7fd fa0b bl 8003d0c <get_fattime>
  16528. 80068f6: 6138 str r0, [r7, #16]
  16529. FREE_NAMBUF();
  16530. }
  16531. } else
  16532. #endif
  16533. {
  16534. res = move_window(fs, fp->dir_sect);
  16535. 80068f8: 68ba ldr r2, [r7, #8]
  16536. 80068fa: 687b ldr r3, [r7, #4]
  16537. 80068fc: 6a5b ldr r3, [r3, #36] ; 0x24
  16538. 80068fe: 4619 mov r1, r3
  16539. 8006900: 4610 mov r0, r2
  16540. 8006902: f7fd fd9d bl 8004440 <move_window>
  16541. 8006906: 4603 mov r3, r0
  16542. 8006908: 75fb strb r3, [r7, #23]
  16543. if (res == FR_OK) {
  16544. 800690a: 7dfb ldrb r3, [r7, #23]
  16545. 800690c: 2b00 cmp r3, #0
  16546. 800690e: d138 bne.n 8006982 <f_sync+0xf2>
  16547. dir = fp->dir_ptr;
  16548. 8006910: 687b ldr r3, [r7, #4]
  16549. 8006912: 6a9b ldr r3, [r3, #40] ; 0x28
  16550. 8006914: 60fb str r3, [r7, #12]
  16551. dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
  16552. 8006916: 68fb ldr r3, [r7, #12]
  16553. 8006918: 330b adds r3, #11
  16554. 800691a: 781a ldrb r2, [r3, #0]
  16555. 800691c: 68fb ldr r3, [r7, #12]
  16556. 800691e: 330b adds r3, #11
  16557. 8006920: f042 0220 orr.w r2, r2, #32
  16558. 8006924: b2d2 uxtb r2, r2
  16559. 8006926: 701a strb r2, [r3, #0]
  16560. st_clust(fp->obj.fs, dir, fp->obj.sclust); /* Update file allocation info */
  16561. 8006928: 687b ldr r3, [r7, #4]
  16562. 800692a: 6818 ldr r0, [r3, #0]
  16563. 800692c: 687b ldr r3, [r7, #4]
  16564. 800692e: 689b ldr r3, [r3, #8]
  16565. 8006930: 461a mov r2, r3
  16566. 8006932: 68f9 ldr r1, [r7, #12]
  16567. 8006934: f7fe fb20 bl 8004f78 <st_clust>
  16568. st_dword(dir + DIR_FileSize, (DWORD)fp->obj.objsize); /* Update file size */
  16569. 8006938: 68fb ldr r3, [r7, #12]
  16570. 800693a: f103 021c add.w r2, r3, #28
  16571. 800693e: 687b ldr r3, [r7, #4]
  16572. 8006940: 68db ldr r3, [r3, #12]
  16573. 8006942: 4619 mov r1, r3
  16574. 8006944: 4610 mov r0, r2
  16575. 8006946: f7fd fb2e bl 8003fa6 <st_dword>
  16576. st_dword(dir + DIR_ModTime, tm); /* Update modified time */
  16577. 800694a: 68fb ldr r3, [r7, #12]
  16578. 800694c: 3316 adds r3, #22
  16579. 800694e: 6939 ldr r1, [r7, #16]
  16580. 8006950: 4618 mov r0, r3
  16581. 8006952: f7fd fb28 bl 8003fa6 <st_dword>
  16582. st_word(dir + DIR_LstAccDate, 0);
  16583. 8006956: 68fb ldr r3, [r7, #12]
  16584. 8006958: 3312 adds r3, #18
  16585. 800695a: 2100 movs r1, #0
  16586. 800695c: 4618 mov r0, r3
  16587. 800695e: f7fd fb08 bl 8003f72 <st_word>
  16588. fs->wflag = 1;
  16589. 8006962: 68bb ldr r3, [r7, #8]
  16590. 8006964: 2201 movs r2, #1
  16591. 8006966: 70da strb r2, [r3, #3]
  16592. res = sync_fs(fs); /* Restore it to the directory */
  16593. 8006968: 68bb ldr r3, [r7, #8]
  16594. 800696a: 4618 mov r0, r3
  16595. 800696c: f7fd fd96 bl 800449c <sync_fs>
  16596. 8006970: 4603 mov r3, r0
  16597. 8006972: 75fb strb r3, [r7, #23]
  16598. fp->flag &= (BYTE)~FA_MODIFIED;
  16599. 8006974: 687b ldr r3, [r7, #4]
  16600. 8006976: 7d1b ldrb r3, [r3, #20]
  16601. 8006978: f023 0340 bic.w r3, r3, #64 ; 0x40
  16602. 800697c: b2da uxtb r2, r3
  16603. 800697e: 687b ldr r3, [r7, #4]
  16604. 8006980: 751a strb r2, [r3, #20]
  16605. }
  16606. }
  16607. }
  16608. }
  16609. LEAVE_FF(fs, res);
  16610. 8006982: 7dfb ldrb r3, [r7, #23]
  16611. }
  16612. 8006984: 4618 mov r0, r3
  16613. 8006986: 3718 adds r7, #24
  16614. 8006988: 46bd mov sp, r7
  16615. 800698a: bd80 pop {r7, pc}
  16616. 0800698c <f_close>:
  16617. /*-----------------------------------------------------------------------*/
  16618. FRESULT f_close (
  16619. FIL* fp /* Pointer to the file object to be closed */
  16620. )
  16621. {
  16622. 800698c: b580 push {r7, lr}
  16623. 800698e: b084 sub sp, #16
  16624. 8006990: af00 add r7, sp, #0
  16625. 8006992: 6078 str r0, [r7, #4]
  16626. FRESULT res;
  16627. FATFS *fs;
  16628. #if !_FS_READONLY
  16629. res = f_sync(fp); /* Flush cached data */
  16630. 8006994: 6878 ldr r0, [r7, #4]
  16631. 8006996: f7ff ff7b bl 8006890 <f_sync>
  16632. 800699a: 4603 mov r3, r0
  16633. 800699c: 73fb strb r3, [r7, #15]
  16634. if (res == FR_OK)
  16635. 800699e: 7bfb ldrb r3, [r7, #15]
  16636. 80069a0: 2b00 cmp r3, #0
  16637. 80069a2: d118 bne.n 80069d6 <f_close+0x4a>
  16638. #endif
  16639. {
  16640. res = validate(&fp->obj, &fs); /* Lock volume */
  16641. 80069a4: 687b ldr r3, [r7, #4]
  16642. 80069a6: f107 0208 add.w r2, r7, #8
  16643. 80069aa: 4611 mov r1, r2
  16644. 80069ac: 4618 mov r0, r3
  16645. 80069ae: f7ff fb93 bl 80060d8 <validate>
  16646. 80069b2: 4603 mov r3, r0
  16647. 80069b4: 73fb strb r3, [r7, #15]
  16648. if (res == FR_OK) {
  16649. 80069b6: 7bfb ldrb r3, [r7, #15]
  16650. 80069b8: 2b00 cmp r3, #0
  16651. 80069ba: d10c bne.n 80069d6 <f_close+0x4a>
  16652. #if _FS_LOCK != 0
  16653. res = dec_lock(fp->obj.lockid); /* Decrement file open counter */
  16654. 80069bc: 687b ldr r3, [r7, #4]
  16655. 80069be: 691b ldr r3, [r3, #16]
  16656. 80069c0: 4618 mov r0, r3
  16657. 80069c2: f7fd fc9d bl 8004300 <dec_lock>
  16658. 80069c6: 4603 mov r3, r0
  16659. 80069c8: 73fb strb r3, [r7, #15]
  16660. if (res == FR_OK)
  16661. 80069ca: 7bfb ldrb r3, [r7, #15]
  16662. 80069cc: 2b00 cmp r3, #0
  16663. 80069ce: d102 bne.n 80069d6 <f_close+0x4a>
  16664. #endif
  16665. {
  16666. fp->obj.fs = 0; /* Invalidate file object */
  16667. 80069d0: 687b ldr r3, [r7, #4]
  16668. 80069d2: 2200 movs r2, #0
  16669. 80069d4: 601a str r2, [r3, #0]
  16670. #if _FS_REENTRANT
  16671. unlock_fs(fs, FR_OK); /* Unlock volume */
  16672. #endif
  16673. }
  16674. }
  16675. return res;
  16676. 80069d6: 7bfb ldrb r3, [r7, #15]
  16677. }
  16678. 80069d8: 4618 mov r0, r3
  16679. 80069da: 3710 adds r7, #16
  16680. 80069dc: 46bd mov sp, r7
  16681. 80069de: bd80 pop {r7, pc}
  16682. 080069e0 <putc_bfd>:
  16683. static
  16684. void putc_bfd ( /* Buffered write with code conversion */
  16685. putbuff* pb,
  16686. TCHAR c
  16687. )
  16688. {
  16689. 80069e0: b580 push {r7, lr}
  16690. 80069e2: b084 sub sp, #16
  16691. 80069e4: af00 add r7, sp, #0
  16692. 80069e6: 6078 str r0, [r7, #4]
  16693. 80069e8: 460b mov r3, r1
  16694. 80069ea: 70fb strb r3, [r7, #3]
  16695. UINT bw;
  16696. int i;
  16697. if (_USE_STRFUNC == 2 && c == '\n') { /* LF -> CRLF conversion */
  16698. 80069ec: 78fb ldrb r3, [r7, #3]
  16699. 80069ee: 2b0a cmp r3, #10
  16700. 80069f0: d103 bne.n 80069fa <putc_bfd+0x1a>
  16701. putc_bfd(pb, '\r');
  16702. 80069f2: 210d movs r1, #13
  16703. 80069f4: 6878 ldr r0, [r7, #4]
  16704. 80069f6: f7ff fff3 bl 80069e0 <putc_bfd>
  16705. }
  16706. i = pb->idx; /* Write index of pb->buf[] */
  16707. 80069fa: 687b ldr r3, [r7, #4]
  16708. 80069fc: 685b ldr r3, [r3, #4]
  16709. 80069fe: 60fb str r3, [r7, #12]
  16710. if (i < 0) return;
  16711. 8006a00: 68fb ldr r3, [r7, #12]
  16712. 8006a02: 2b00 cmp r3, #0
  16713. 8006a04: db25 blt.n 8006a52 <putc_bfd+0x72>
  16714. if (c >= 0x100)
  16715. pb->buf[i++] = (BYTE)(c >> 8);
  16716. pb->buf[i++] = (BYTE)c;
  16717. #endif
  16718. #else /* Write a character without conversion */
  16719. pb->buf[i++] = (BYTE)c;
  16720. 8006a06: 68fb ldr r3, [r7, #12]
  16721. 8006a08: 1c5a adds r2, r3, #1
  16722. 8006a0a: 60fa str r2, [r7, #12]
  16723. 8006a0c: 687a ldr r2, [r7, #4]
  16724. 8006a0e: 4413 add r3, r2
  16725. 8006a10: 78fa ldrb r2, [r7, #3]
  16726. 8006a12: 731a strb r2, [r3, #12]
  16727. #endif
  16728. if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */
  16729. 8006a14: 68fb ldr r3, [r7, #12]
  16730. 8006a16: 2b3c cmp r3, #60 ; 0x3c
  16731. 8006a18: dd12 ble.n 8006a40 <putc_bfd+0x60>
  16732. f_write(pb->fp, pb->buf, (UINT)i, &bw);
  16733. 8006a1a: 687b ldr r3, [r7, #4]
  16734. 8006a1c: 6818 ldr r0, [r3, #0]
  16735. 8006a1e: 687b ldr r3, [r7, #4]
  16736. 8006a20: f103 010c add.w r1, r3, #12
  16737. 8006a24: 68fa ldr r2, [r7, #12]
  16738. 8006a26: f107 0308 add.w r3, r7, #8
  16739. 8006a2a: f7ff fd9d bl 8006568 <f_write>
  16740. i = (bw == (UINT)i) ? 0 : -1;
  16741. 8006a2e: 68ba ldr r2, [r7, #8]
  16742. 8006a30: 68fb ldr r3, [r7, #12]
  16743. 8006a32: 429a cmp r2, r3
  16744. 8006a34: d101 bne.n 8006a3a <putc_bfd+0x5a>
  16745. 8006a36: 2300 movs r3, #0
  16746. 8006a38: e001 b.n 8006a3e <putc_bfd+0x5e>
  16747. 8006a3a: f04f 33ff mov.w r3, #4294967295
  16748. 8006a3e: 60fb str r3, [r7, #12]
  16749. }
  16750. pb->idx = i;
  16751. 8006a40: 687b ldr r3, [r7, #4]
  16752. 8006a42: 68fa ldr r2, [r7, #12]
  16753. 8006a44: 605a str r2, [r3, #4]
  16754. pb->nchr++;
  16755. 8006a46: 687b ldr r3, [r7, #4]
  16756. 8006a48: 689b ldr r3, [r3, #8]
  16757. 8006a4a: 1c5a adds r2, r3, #1
  16758. 8006a4c: 687b ldr r3, [r7, #4]
  16759. 8006a4e: 609a str r2, [r3, #8]
  16760. 8006a50: e000 b.n 8006a54 <putc_bfd+0x74>
  16761. if (i < 0) return;
  16762. 8006a52: bf00 nop
  16763. }
  16764. 8006a54: 3710 adds r7, #16
  16765. 8006a56: 46bd mov sp, r7
  16766. 8006a58: bd80 pop {r7, pc}
  16767. 08006a5a <putc_flush>:
  16768. static
  16769. int putc_flush ( /* Flush left characters in the buffer */
  16770. putbuff* pb
  16771. )
  16772. {
  16773. 8006a5a: b580 push {r7, lr}
  16774. 8006a5c: b084 sub sp, #16
  16775. 8006a5e: af00 add r7, sp, #0
  16776. 8006a60: 6078 str r0, [r7, #4]
  16777. UINT nw;
  16778. if ( pb->idx >= 0 /* Flush buffered characters to the file */
  16779. 8006a62: 687b ldr r3, [r7, #4]
  16780. 8006a64: 685b ldr r3, [r3, #4]
  16781. 8006a66: 2b00 cmp r3, #0
  16782. 8006a68: db17 blt.n 8006a9a <putc_flush+0x40>
  16783. && f_write(pb->fp, pb->buf, (UINT)pb->idx, &nw) == FR_OK
  16784. 8006a6a: 687b ldr r3, [r7, #4]
  16785. 8006a6c: 6818 ldr r0, [r3, #0]
  16786. 8006a6e: 687b ldr r3, [r7, #4]
  16787. 8006a70: f103 010c add.w r1, r3, #12
  16788. 8006a74: 687b ldr r3, [r7, #4]
  16789. 8006a76: 685b ldr r3, [r3, #4]
  16790. 8006a78: 461a mov r2, r3
  16791. 8006a7a: f107 030c add.w r3, r7, #12
  16792. 8006a7e: f7ff fd73 bl 8006568 <f_write>
  16793. 8006a82: 4603 mov r3, r0
  16794. 8006a84: 2b00 cmp r3, #0
  16795. 8006a86: d108 bne.n 8006a9a <putc_flush+0x40>
  16796. && (UINT)pb->idx == nw) return pb->nchr;
  16797. 8006a88: 687b ldr r3, [r7, #4]
  16798. 8006a8a: 685b ldr r3, [r3, #4]
  16799. 8006a8c: 461a mov r2, r3
  16800. 8006a8e: 68fb ldr r3, [r7, #12]
  16801. 8006a90: 429a cmp r2, r3
  16802. 8006a92: d102 bne.n 8006a9a <putc_flush+0x40>
  16803. 8006a94: 687b ldr r3, [r7, #4]
  16804. 8006a96: 689b ldr r3, [r3, #8]
  16805. 8006a98: e001 b.n 8006a9e <putc_flush+0x44>
  16806. return EOF;
  16807. 8006a9a: f04f 33ff mov.w r3, #4294967295
  16808. }
  16809. 8006a9e: 4618 mov r0, r3
  16810. 8006aa0: 3710 adds r7, #16
  16811. 8006aa2: 46bd mov sp, r7
  16812. 8006aa4: bd80 pop {r7, pc}
  16813. 08006aa6 <putc_init>:
  16814. static
  16815. void putc_init ( /* Initialize write buffer */
  16816. putbuff* pb,
  16817. FIL* fp
  16818. )
  16819. {
  16820. 8006aa6: b480 push {r7}
  16821. 8006aa8: b083 sub sp, #12
  16822. 8006aaa: af00 add r7, sp, #0
  16823. 8006aac: 6078 str r0, [r7, #4]
  16824. 8006aae: 6039 str r1, [r7, #0]
  16825. pb->fp = fp;
  16826. 8006ab0: 687b ldr r3, [r7, #4]
  16827. 8006ab2: 683a ldr r2, [r7, #0]
  16828. 8006ab4: 601a str r2, [r3, #0]
  16829. pb->nchr = pb->idx = 0;
  16830. 8006ab6: 687b ldr r3, [r7, #4]
  16831. 8006ab8: 2200 movs r2, #0
  16832. 8006aba: 605a str r2, [r3, #4]
  16833. 8006abc: 687b ldr r3, [r7, #4]
  16834. 8006abe: 685a ldr r2, [r3, #4]
  16835. 8006ac0: 687b ldr r3, [r7, #4]
  16836. 8006ac2: 609a str r2, [r3, #8]
  16837. }
  16838. 8006ac4: bf00 nop
  16839. 8006ac6: 370c adds r7, #12
  16840. 8006ac8: 46bd mov sp, r7
  16841. 8006aca: bc80 pop {r7}
  16842. 8006acc: 4770 bx lr
  16843. 08006ace <f_puts>:
  16844. int f_puts (
  16845. const TCHAR* str, /* Pointer to the string to be output */
  16846. FIL* fp /* Pointer to the file object */
  16847. )
  16848. {
  16849. 8006ace: b580 push {r7, lr}
  16850. 8006ad0: b096 sub sp, #88 ; 0x58
  16851. 8006ad2: af00 add r7, sp, #0
  16852. 8006ad4: 6078 str r0, [r7, #4]
  16853. 8006ad6: 6039 str r1, [r7, #0]
  16854. putbuff pb;
  16855. putc_init(&pb, fp);
  16856. 8006ad8: f107 030c add.w r3, r7, #12
  16857. 8006adc: 6839 ldr r1, [r7, #0]
  16858. 8006ade: 4618 mov r0, r3
  16859. 8006ae0: f7ff ffe1 bl 8006aa6 <putc_init>
  16860. while (*str) putc_bfd(&pb, *str++); /* Put the string */
  16861. 8006ae4: e009 b.n 8006afa <f_puts+0x2c>
  16862. 8006ae6: 687b ldr r3, [r7, #4]
  16863. 8006ae8: 1c5a adds r2, r3, #1
  16864. 8006aea: 607a str r2, [r7, #4]
  16865. 8006aec: 781a ldrb r2, [r3, #0]
  16866. 8006aee: f107 030c add.w r3, r7, #12
  16867. 8006af2: 4611 mov r1, r2
  16868. 8006af4: 4618 mov r0, r3
  16869. 8006af6: f7ff ff73 bl 80069e0 <putc_bfd>
  16870. 8006afa: 687b ldr r3, [r7, #4]
  16871. 8006afc: 781b ldrb r3, [r3, #0]
  16872. 8006afe: 2b00 cmp r3, #0
  16873. 8006b00: d1f1 bne.n 8006ae6 <f_puts+0x18>
  16874. return putc_flush(&pb);
  16875. 8006b02: f107 030c add.w r3, r7, #12
  16876. 8006b06: 4618 mov r0, r3
  16877. 8006b08: f7ff ffa7 bl 8006a5a <putc_flush>
  16878. 8006b0c: 4603 mov r3, r0
  16879. }
  16880. 8006b0e: 4618 mov r0, r3
  16881. 8006b10: 3758 adds r7, #88 ; 0x58
  16882. 8006b12: 46bd mov sp, r7
  16883. 8006b14: bd80 pop {r7, pc}
  16884. ...
  16885. 08006b18 <f_printf>:
  16886. int f_printf (
  16887. FIL* fp, /* Pointer to the file object */
  16888. const TCHAR* fmt, /* Pointer to the format string */
  16889. ... /* Optional arguments... */
  16890. )
  16891. {
  16892. 8006b18: b40e push {r1, r2, r3}
  16893. 8006b1a: b580 push {r7, lr}
  16894. 8006b1c: b0a7 sub sp, #156 ; 0x9c
  16895. 8006b1e: af00 add r7, sp, #0
  16896. 8006b20: 6078 str r0, [r7, #4]
  16897. UINT i, j, w;
  16898. DWORD v;
  16899. TCHAR c, d, str[32], *p;
  16900. putc_init(&pb, fp);
  16901. 8006b22: f107 032c add.w r3, r7, #44 ; 0x2c
  16902. 8006b26: 6879 ldr r1, [r7, #4]
  16903. 8006b28: 4618 mov r0, r3
  16904. 8006b2a: f7ff ffbc bl 8006aa6 <putc_init>
  16905. va_start(arp, fmt);
  16906. 8006b2e: f107 03a8 add.w r3, r7, #168 ; 0xa8
  16907. 8006b32: 67bb str r3, [r7, #120] ; 0x78
  16908. for (;;) {
  16909. c = *fmt++;
  16910. 8006b34: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
  16911. 8006b38: 1c5a adds r2, r3, #1
  16912. 8006b3a: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
  16913. 8006b3e: 781b ldrb r3, [r3, #0]
  16914. 8006b40: f887 3083 strb.w r3, [r7, #131] ; 0x83
  16915. if (c == 0) break; /* End of string */
  16916. 8006b44: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16917. 8006b48: 2b00 cmp r3, #0
  16918. 8006b4a: f000 81f4 beq.w 8006f36 <f_printf+0x41e>
  16919. if (c != '%') { /* Non escape character */
  16920. 8006b4e: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16921. 8006b52: 2b25 cmp r3, #37 ; 0x25
  16922. 8006b54: d008 beq.n 8006b68 <f_printf+0x50>
  16923. putc_bfd(&pb, c);
  16924. 8006b56: f897 2083 ldrb.w r2, [r7, #131] ; 0x83
  16925. 8006b5a: f107 032c add.w r3, r7, #44 ; 0x2c
  16926. 8006b5e: 4611 mov r1, r2
  16927. 8006b60: 4618 mov r0, r3
  16928. 8006b62: f7ff ff3d bl 80069e0 <putc_bfd>
  16929. continue;
  16930. 8006b66: e1e5 b.n 8006f34 <f_printf+0x41c>
  16931. }
  16932. w = f = 0;
  16933. 8006b68: 2300 movs r3, #0
  16934. 8006b6a: f887 3097 strb.w r3, [r7, #151] ; 0x97
  16935. 8006b6e: 2300 movs r3, #0
  16936. 8006b70: f8c7 3088 str.w r3, [r7, #136] ; 0x88
  16937. c = *fmt++;
  16938. 8006b74: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
  16939. 8006b78: 1c5a adds r2, r3, #1
  16940. 8006b7a: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
  16941. 8006b7e: 781b ldrb r3, [r3, #0]
  16942. 8006b80: f887 3083 strb.w r3, [r7, #131] ; 0x83
  16943. if (c == '0') { /* Flag: '0' padding */
  16944. 8006b84: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16945. 8006b88: 2b30 cmp r3, #48 ; 0x30
  16946. 8006b8a: d10b bne.n 8006ba4 <f_printf+0x8c>
  16947. f = 1; c = *fmt++;
  16948. 8006b8c: 2301 movs r3, #1
  16949. 8006b8e: f887 3097 strb.w r3, [r7, #151] ; 0x97
  16950. 8006b92: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
  16951. 8006b96: 1c5a adds r2, r3, #1
  16952. 8006b98: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
  16953. 8006b9c: 781b ldrb r3, [r3, #0]
  16954. 8006b9e: f887 3083 strb.w r3, [r7, #131] ; 0x83
  16955. 8006ba2: e024 b.n 8006bee <f_printf+0xd6>
  16956. } else {
  16957. if (c == '-') { /* Flag: left justified */
  16958. 8006ba4: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16959. 8006ba8: 2b2d cmp r3, #45 ; 0x2d
  16960. 8006baa: d120 bne.n 8006bee <f_printf+0xd6>
  16961. f = 2; c = *fmt++;
  16962. 8006bac: 2302 movs r3, #2
  16963. 8006bae: f887 3097 strb.w r3, [r7, #151] ; 0x97
  16964. 8006bb2: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
  16965. 8006bb6: 1c5a adds r2, r3, #1
  16966. 8006bb8: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
  16967. 8006bbc: 781b ldrb r3, [r3, #0]
  16968. 8006bbe: f887 3083 strb.w r3, [r7, #131] ; 0x83
  16969. }
  16970. }
  16971. while (IsDigit(c)) { /* Precision */
  16972. 8006bc2: e014 b.n 8006bee <f_printf+0xd6>
  16973. w = w * 10 + c - '0';
  16974. 8006bc4: f8d7 2088 ldr.w r2, [r7, #136] ; 0x88
  16975. 8006bc8: 4613 mov r3, r2
  16976. 8006bca: 009b lsls r3, r3, #2
  16977. 8006bcc: 4413 add r3, r2
  16978. 8006bce: 005b lsls r3, r3, #1
  16979. 8006bd0: 461a mov r2, r3
  16980. 8006bd2: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16981. 8006bd6: 4413 add r3, r2
  16982. 8006bd8: 3b30 subs r3, #48 ; 0x30
  16983. 8006bda: f8c7 3088 str.w r3, [r7, #136] ; 0x88
  16984. c = *fmt++;
  16985. 8006bde: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
  16986. 8006be2: 1c5a adds r2, r3, #1
  16987. 8006be4: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
  16988. 8006be8: 781b ldrb r3, [r3, #0]
  16989. 8006bea: f887 3083 strb.w r3, [r7, #131] ; 0x83
  16990. while (IsDigit(c)) { /* Precision */
  16991. 8006bee: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16992. 8006bf2: 2b2f cmp r3, #47 ; 0x2f
  16993. 8006bf4: d903 bls.n 8006bfe <f_printf+0xe6>
  16994. 8006bf6: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  16995. 8006bfa: 2b39 cmp r3, #57 ; 0x39
  16996. 8006bfc: d9e2 bls.n 8006bc4 <f_printf+0xac>
  16997. }
  16998. if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
  16999. 8006bfe: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  17000. 8006c02: 2b6c cmp r3, #108 ; 0x6c
  17001. 8006c04: d003 beq.n 8006c0e <f_printf+0xf6>
  17002. 8006c06: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  17003. 8006c0a: 2b4c cmp r3, #76 ; 0x4c
  17004. 8006c0c: d10d bne.n 8006c2a <f_printf+0x112>
  17005. f |= 4; c = *fmt++;
  17006. 8006c0e: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17007. 8006c12: f043 0304 orr.w r3, r3, #4
  17008. 8006c16: f887 3097 strb.w r3, [r7, #151] ; 0x97
  17009. 8006c1a: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4
  17010. 8006c1e: 1c5a adds r2, r3, #1
  17011. 8006c20: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
  17012. 8006c24: 781b ldrb r3, [r3, #0]
  17013. 8006c26: f887 3083 strb.w r3, [r7, #131] ; 0x83
  17014. }
  17015. if (!c) break;
  17016. 8006c2a: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  17017. 8006c2e: 2b00 cmp r3, #0
  17018. 8006c30: f000 8183 beq.w 8006f3a <f_printf+0x422>
  17019. d = c;
  17020. 8006c34: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  17021. 8006c38: f887 3082 strb.w r3, [r7, #130] ; 0x82
  17022. if (IsLower(d)) d -= 0x20;
  17023. 8006c3c: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17024. 8006c40: 2b60 cmp r3, #96 ; 0x60
  17025. 8006c42: d908 bls.n 8006c56 <f_printf+0x13e>
  17026. 8006c44: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17027. 8006c48: 2b7a cmp r3, #122 ; 0x7a
  17028. 8006c4a: d804 bhi.n 8006c56 <f_printf+0x13e>
  17029. 8006c4c: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17030. 8006c50: 3b20 subs r3, #32
  17031. 8006c52: f887 3082 strb.w r3, [r7, #130] ; 0x82
  17032. switch (d) { /* Type is... */
  17033. 8006c56: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17034. 8006c5a: 3b42 subs r3, #66 ; 0x42
  17035. 8006c5c: 2b16 cmp r3, #22
  17036. 8006c5e: f200 8098 bhi.w 8006d92 <f_printf+0x27a>
  17037. 8006c62: a201 add r2, pc, #4 ; (adr r2, 8006c68 <f_printf+0x150>)
  17038. 8006c64: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  17039. 8006c68: 08006d73 .word 0x08006d73
  17040. 8006c6c: 08006d5b .word 0x08006d5b
  17041. 8006c70: 08006d83 .word 0x08006d83
  17042. 8006c74: 08006d93 .word 0x08006d93
  17043. 8006c78: 08006d93 .word 0x08006d93
  17044. 8006c7c: 08006d93 .word 0x08006d93
  17045. 8006c80: 08006d93 .word 0x08006d93
  17046. 8006c84: 08006d93 .word 0x08006d93
  17047. 8006c88: 08006d93 .word 0x08006d93
  17048. 8006c8c: 08006d93 .word 0x08006d93
  17049. 8006c90: 08006d93 .word 0x08006d93
  17050. 8006c94: 08006d93 .word 0x08006d93
  17051. 8006c98: 08006d93 .word 0x08006d93
  17052. 8006c9c: 08006d7b .word 0x08006d7b
  17053. 8006ca0: 08006d93 .word 0x08006d93
  17054. 8006ca4: 08006d93 .word 0x08006d93
  17055. 8006ca8: 08006d93 .word 0x08006d93
  17056. 8006cac: 08006cc5 .word 0x08006cc5
  17057. 8006cb0: 08006d93 .word 0x08006d93
  17058. 8006cb4: 08006d83 .word 0x08006d83
  17059. 8006cb8: 08006d93 .word 0x08006d93
  17060. 8006cbc: 08006d93 .word 0x08006d93
  17061. 8006cc0: 08006d8b .word 0x08006d8b
  17062. case 'S' : /* String */
  17063. p = va_arg(arp, TCHAR*);
  17064. 8006cc4: 6fbb ldr r3, [r7, #120] ; 0x78
  17065. 8006cc6: 1d1a adds r2, r3, #4
  17066. 8006cc8: 67ba str r2, [r7, #120] ; 0x78
  17067. 8006cca: 681b ldr r3, [r3, #0]
  17068. 8006ccc: 67fb str r3, [r7, #124] ; 0x7c
  17069. for (j = 0; p[j]; j++) ;
  17070. 8006cce: 2300 movs r3, #0
  17071. 8006cd0: f8c7 308c str.w r3, [r7, #140] ; 0x8c
  17072. 8006cd4: e004 b.n 8006ce0 <f_printf+0x1c8>
  17073. 8006cd6: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
  17074. 8006cda: 3301 adds r3, #1
  17075. 8006cdc: f8c7 308c str.w r3, [r7, #140] ; 0x8c
  17076. 8006ce0: 6ffa ldr r2, [r7, #124] ; 0x7c
  17077. 8006ce2: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
  17078. 8006ce6: 4413 add r3, r2
  17079. 8006ce8: 781b ldrb r3, [r3, #0]
  17080. 8006cea: 2b00 cmp r3, #0
  17081. 8006cec: d1f3 bne.n 8006cd6 <f_printf+0x1be>
  17082. if (!(f & 2)) {
  17083. 8006cee: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17084. 8006cf2: f003 0302 and.w r3, r3, #2
  17085. 8006cf6: 2b00 cmp r3, #0
  17086. 8006cf8: d11a bne.n 8006d30 <f_printf+0x218>
  17087. while (j++ < w) putc_bfd(&pb, ' ');
  17088. 8006cfa: e005 b.n 8006d08 <f_printf+0x1f0>
  17089. 8006cfc: f107 032c add.w r3, r7, #44 ; 0x2c
  17090. 8006d00: 2120 movs r1, #32
  17091. 8006d02: 4618 mov r0, r3
  17092. 8006d04: f7ff fe6c bl 80069e0 <putc_bfd>
  17093. 8006d08: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
  17094. 8006d0c: 1c5a adds r2, r3, #1
  17095. 8006d0e: f8c7 208c str.w r2, [r7, #140] ; 0x8c
  17096. 8006d12: f8d7 2088 ldr.w r2, [r7, #136] ; 0x88
  17097. 8006d16: 429a cmp r2, r3
  17098. 8006d18: d8f0 bhi.n 8006cfc <f_printf+0x1e4>
  17099. }
  17100. while (*p) putc_bfd(&pb, *p++);
  17101. 8006d1a: e009 b.n 8006d30 <f_printf+0x218>
  17102. 8006d1c: 6ffb ldr r3, [r7, #124] ; 0x7c
  17103. 8006d1e: 1c5a adds r2, r3, #1
  17104. 8006d20: 67fa str r2, [r7, #124] ; 0x7c
  17105. 8006d22: 781a ldrb r2, [r3, #0]
  17106. 8006d24: f107 032c add.w r3, r7, #44 ; 0x2c
  17107. 8006d28: 4611 mov r1, r2
  17108. 8006d2a: 4618 mov r0, r3
  17109. 8006d2c: f7ff fe58 bl 80069e0 <putc_bfd>
  17110. 8006d30: 6ffb ldr r3, [r7, #124] ; 0x7c
  17111. 8006d32: 781b ldrb r3, [r3, #0]
  17112. 8006d34: 2b00 cmp r3, #0
  17113. 8006d36: d1f1 bne.n 8006d1c <f_printf+0x204>
  17114. while (j++ < w) putc_bfd(&pb, ' ');
  17115. 8006d38: e005 b.n 8006d46 <f_printf+0x22e>
  17116. 8006d3a: f107 032c add.w r3, r7, #44 ; 0x2c
  17117. 8006d3e: 2120 movs r1, #32
  17118. 8006d40: 4618 mov r0, r3
  17119. 8006d42: f7ff fe4d bl 80069e0 <putc_bfd>
  17120. 8006d46: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
  17121. 8006d4a: 1c5a adds r2, r3, #1
  17122. 8006d4c: f8c7 208c str.w r2, [r7, #140] ; 0x8c
  17123. 8006d50: f8d7 2088 ldr.w r2, [r7, #136] ; 0x88
  17124. 8006d54: 429a cmp r2, r3
  17125. 8006d56: d8f0 bhi.n 8006d3a <f_printf+0x222>
  17126. continue;
  17127. 8006d58: e0ec b.n 8006f34 <f_printf+0x41c>
  17128. case 'C' : /* Character */
  17129. putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue;
  17130. 8006d5a: 6fbb ldr r3, [r7, #120] ; 0x78
  17131. 8006d5c: 1d1a adds r2, r3, #4
  17132. 8006d5e: 67ba str r2, [r7, #120] ; 0x78
  17133. 8006d60: 681b ldr r3, [r3, #0]
  17134. 8006d62: b2da uxtb r2, r3
  17135. 8006d64: f107 032c add.w r3, r7, #44 ; 0x2c
  17136. 8006d68: 4611 mov r1, r2
  17137. 8006d6a: 4618 mov r0, r3
  17138. 8006d6c: f7ff fe38 bl 80069e0 <putc_bfd>
  17139. 8006d70: e0e0 b.n 8006f34 <f_printf+0x41c>
  17140. case 'B' : /* Binary */
  17141. r = 2; break;
  17142. 8006d72: 2302 movs r3, #2
  17143. 8006d74: f887 3096 strb.w r3, [r7, #150] ; 0x96
  17144. 8006d78: e014 b.n 8006da4 <f_printf+0x28c>
  17145. case 'O' : /* Octal */
  17146. r = 8; break;
  17147. 8006d7a: 2308 movs r3, #8
  17148. 8006d7c: f887 3096 strb.w r3, [r7, #150] ; 0x96
  17149. 8006d80: e010 b.n 8006da4 <f_printf+0x28c>
  17150. case 'D' : /* Signed decimal */
  17151. case 'U' : /* Unsigned decimal */
  17152. r = 10; break;
  17153. 8006d82: 230a movs r3, #10
  17154. 8006d84: f887 3096 strb.w r3, [r7, #150] ; 0x96
  17155. 8006d88: e00c b.n 8006da4 <f_printf+0x28c>
  17156. case 'X' : /* Hexdecimal */
  17157. r = 16; break;
  17158. 8006d8a: 2310 movs r3, #16
  17159. 8006d8c: f887 3096 strb.w r3, [r7, #150] ; 0x96
  17160. 8006d90: e008 b.n 8006da4 <f_printf+0x28c>
  17161. default: /* Unknown type (pass-through) */
  17162. putc_bfd(&pb, c); continue;
  17163. 8006d92: f897 2083 ldrb.w r2, [r7, #131] ; 0x83
  17164. 8006d96: f107 032c add.w r3, r7, #44 ; 0x2c
  17165. 8006d9a: 4611 mov r1, r2
  17166. 8006d9c: 4618 mov r0, r3
  17167. 8006d9e: f7ff fe1f bl 80069e0 <putc_bfd>
  17168. 8006da2: e0c7 b.n 8006f34 <f_printf+0x41c>
  17169. }
  17170. /* Get an argument and put it in numeral */
  17171. v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int));
  17172. 8006da4: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17173. 8006da8: f003 0304 and.w r3, r3, #4
  17174. 8006dac: 2b00 cmp r3, #0
  17175. 8006dae: d004 beq.n 8006dba <f_printf+0x2a2>
  17176. 8006db0: 6fbb ldr r3, [r7, #120] ; 0x78
  17177. 8006db2: 1d1a adds r2, r3, #4
  17178. 8006db4: 67ba str r2, [r7, #120] ; 0x78
  17179. 8006db6: 681b ldr r3, [r3, #0]
  17180. 8006db8: e00c b.n 8006dd4 <f_printf+0x2bc>
  17181. 8006dba: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17182. 8006dbe: 2b44 cmp r3, #68 ; 0x44
  17183. 8006dc0: d104 bne.n 8006dcc <f_printf+0x2b4>
  17184. 8006dc2: 6fbb ldr r3, [r7, #120] ; 0x78
  17185. 8006dc4: 1d1a adds r2, r3, #4
  17186. 8006dc6: 67ba str r2, [r7, #120] ; 0x78
  17187. 8006dc8: 681b ldr r3, [r3, #0]
  17188. 8006dca: e003 b.n 8006dd4 <f_printf+0x2bc>
  17189. 8006dcc: 6fbb ldr r3, [r7, #120] ; 0x78
  17190. 8006dce: 1d1a adds r2, r3, #4
  17191. 8006dd0: 67ba str r2, [r7, #120] ; 0x78
  17192. 8006dd2: 681b ldr r3, [r3, #0]
  17193. 8006dd4: f8c7 3084 str.w r3, [r7, #132] ; 0x84
  17194. if (d == 'D' && (v & 0x80000000)) {
  17195. 8006dd8: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17196. 8006ddc: 2b44 cmp r3, #68 ; 0x44
  17197. 8006dde: d10e bne.n 8006dfe <f_printf+0x2e6>
  17198. 8006de0: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
  17199. 8006de4: 2b00 cmp r3, #0
  17200. 8006de6: da0a bge.n 8006dfe <f_printf+0x2e6>
  17201. v = 0 - v;
  17202. 8006de8: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
  17203. 8006dec: 425b negs r3, r3
  17204. 8006dee: f8c7 3084 str.w r3, [r7, #132] ; 0x84
  17205. f |= 8;
  17206. 8006df2: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17207. 8006df6: f043 0308 orr.w r3, r3, #8
  17208. 8006dfa: f887 3097 strb.w r3, [r7, #151] ; 0x97
  17209. }
  17210. i = 0;
  17211. 8006dfe: 2300 movs r3, #0
  17212. 8006e00: f8c7 3090 str.w r3, [r7, #144] ; 0x90
  17213. do {
  17214. d = (TCHAR)(v % r); v /= r;
  17215. 8006e04: f897 2096 ldrb.w r2, [r7, #150] ; 0x96
  17216. 8006e08: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
  17217. 8006e0c: fbb3 f1f2 udiv r1, r3, r2
  17218. 8006e10: fb02 f201 mul.w r2, r2, r1
  17219. 8006e14: 1a9b subs r3, r3, r2
  17220. 8006e16: f887 3082 strb.w r3, [r7, #130] ; 0x82
  17221. 8006e1a: f897 3096 ldrb.w r3, [r7, #150] ; 0x96
  17222. 8006e1e: f8d7 2084 ldr.w r2, [r7, #132] ; 0x84
  17223. 8006e22: fbb2 f3f3 udiv r3, r2, r3
  17224. 8006e26: f8c7 3084 str.w r3, [r7, #132] ; 0x84
  17225. if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
  17226. 8006e2a: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17227. 8006e2e: 2b09 cmp r3, #9
  17228. 8006e30: d90b bls.n 8006e4a <f_printf+0x332>
  17229. 8006e32: f897 3083 ldrb.w r3, [r7, #131] ; 0x83
  17230. 8006e36: 2b78 cmp r3, #120 ; 0x78
  17231. 8006e38: d101 bne.n 8006e3e <f_printf+0x326>
  17232. 8006e3a: 2227 movs r2, #39 ; 0x27
  17233. 8006e3c: e000 b.n 8006e40 <f_printf+0x328>
  17234. 8006e3e: 2207 movs r2, #7
  17235. 8006e40: f897 3082 ldrb.w r3, [r7, #130] ; 0x82
  17236. 8006e44: 4413 add r3, r2
  17237. 8006e46: f887 3082 strb.w r3, [r7, #130] ; 0x82
  17238. str[i++] = d + '0';
  17239. 8006e4a: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17240. 8006e4e: 1c5a adds r2, r3, #1
  17241. 8006e50: f8c7 2090 str.w r2, [r7, #144] ; 0x90
  17242. 8006e54: f897 2082 ldrb.w r2, [r7, #130] ; 0x82
  17243. 8006e58: 3230 adds r2, #48 ; 0x30
  17244. 8006e5a: b2d2 uxtb r2, r2
  17245. 8006e5c: f107 0198 add.w r1, r7, #152 ; 0x98
  17246. 8006e60: 440b add r3, r1
  17247. 8006e62: f803 2c8c strb.w r2, [r3, #-140]
  17248. } while (v && i < sizeof str / sizeof str[0]);
  17249. 8006e66: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84
  17250. 8006e6a: 2b00 cmp r3, #0
  17251. 8006e6c: d003 beq.n 8006e76 <f_printf+0x35e>
  17252. 8006e6e: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17253. 8006e72: 2b1f cmp r3, #31
  17254. 8006e74: d9c6 bls.n 8006e04 <f_printf+0x2ec>
  17255. if (f & 8) str[i++] = '-';
  17256. 8006e76: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17257. 8006e7a: f003 0308 and.w r3, r3, #8
  17258. 8006e7e: 2b00 cmp r3, #0
  17259. 8006e80: d00a beq.n 8006e98 <f_printf+0x380>
  17260. 8006e82: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17261. 8006e86: 1c5a adds r2, r3, #1
  17262. 8006e88: f8c7 2090 str.w r2, [r7, #144] ; 0x90
  17263. 8006e8c: f107 0298 add.w r2, r7, #152 ; 0x98
  17264. 8006e90: 4413 add r3, r2
  17265. 8006e92: 222d movs r2, #45 ; 0x2d
  17266. 8006e94: f803 2c8c strb.w r2, [r3, #-140]
  17267. j = i; d = (f & 1) ? '0' : ' ';
  17268. 8006e98: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17269. 8006e9c: f8c7 308c str.w r3, [r7, #140] ; 0x8c
  17270. 8006ea0: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17271. 8006ea4: f003 0301 and.w r3, r3, #1
  17272. 8006ea8: 2b00 cmp r3, #0
  17273. 8006eaa: d001 beq.n 8006eb0 <f_printf+0x398>
  17274. 8006eac: 2330 movs r3, #48 ; 0x30
  17275. 8006eae: e000 b.n 8006eb2 <f_printf+0x39a>
  17276. 8006eb0: 2320 movs r3, #32
  17277. 8006eb2: f887 3082 strb.w r3, [r7, #130] ; 0x82
  17278. while (!(f & 2) && j++ < w) putc_bfd(&pb, d);
  17279. 8006eb6: e007 b.n 8006ec8 <f_printf+0x3b0>
  17280. 8006eb8: f897 2082 ldrb.w r2, [r7, #130] ; 0x82
  17281. 8006ebc: f107 032c add.w r3, r7, #44 ; 0x2c
  17282. 8006ec0: 4611 mov r1, r2
  17283. 8006ec2: 4618 mov r0, r3
  17284. 8006ec4: f7ff fd8c bl 80069e0 <putc_bfd>
  17285. 8006ec8: f897 3097 ldrb.w r3, [r7, #151] ; 0x97
  17286. 8006ecc: f003 0302 and.w r3, r3, #2
  17287. 8006ed0: 2b00 cmp r3, #0
  17288. 8006ed2: d108 bne.n 8006ee6 <f_printf+0x3ce>
  17289. 8006ed4: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
  17290. 8006ed8: 1c5a adds r2, r3, #1
  17291. 8006eda: f8c7 208c str.w r2, [r7, #140] ; 0x8c
  17292. 8006ede: f8d7 2088 ldr.w r2, [r7, #136] ; 0x88
  17293. 8006ee2: 429a cmp r2, r3
  17294. 8006ee4: d8e8 bhi.n 8006eb8 <f_printf+0x3a0>
  17295. do {
  17296. putc_bfd(&pb, str[--i]);
  17297. 8006ee6: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17298. 8006eea: 3b01 subs r3, #1
  17299. 8006eec: f8c7 3090 str.w r3, [r7, #144] ; 0x90
  17300. 8006ef0: f107 020c add.w r2, r7, #12
  17301. 8006ef4: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17302. 8006ef8: 4413 add r3, r2
  17303. 8006efa: 781a ldrb r2, [r3, #0]
  17304. 8006efc: f107 032c add.w r3, r7, #44 ; 0x2c
  17305. 8006f00: 4611 mov r1, r2
  17306. 8006f02: 4618 mov r0, r3
  17307. 8006f04: f7ff fd6c bl 80069e0 <putc_bfd>
  17308. } while (i);
  17309. 8006f08: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90
  17310. 8006f0c: 2b00 cmp r3, #0
  17311. 8006f0e: d1ea bne.n 8006ee6 <f_printf+0x3ce>
  17312. while (j++ < w) putc_bfd(&pb, d);
  17313. 8006f10: e007 b.n 8006f22 <f_printf+0x40a>
  17314. 8006f12: f897 2082 ldrb.w r2, [r7, #130] ; 0x82
  17315. 8006f16: f107 032c add.w r3, r7, #44 ; 0x2c
  17316. 8006f1a: 4611 mov r1, r2
  17317. 8006f1c: 4618 mov r0, r3
  17318. 8006f1e: f7ff fd5f bl 80069e0 <putc_bfd>
  17319. 8006f22: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c
  17320. 8006f26: 1c5a adds r2, r3, #1
  17321. 8006f28: f8c7 208c str.w r2, [r7, #140] ; 0x8c
  17322. 8006f2c: f8d7 2088 ldr.w r2, [r7, #136] ; 0x88
  17323. 8006f30: 429a cmp r2, r3
  17324. 8006f32: d8ee bhi.n 8006f12 <f_printf+0x3fa>
  17325. c = *fmt++;
  17326. 8006f34: e5fe b.n 8006b34 <f_printf+0x1c>
  17327. if (c == 0) break; /* End of string */
  17328. 8006f36: bf00 nop
  17329. 8006f38: e000 b.n 8006f3c <f_printf+0x424>
  17330. if (!c) break;
  17331. 8006f3a: bf00 nop
  17332. }
  17333. va_end(arp);
  17334. return putc_flush(&pb);
  17335. 8006f3c: f107 032c add.w r3, r7, #44 ; 0x2c
  17336. 8006f40: 4618 mov r0, r3
  17337. 8006f42: f7ff fd8a bl 8006a5a <putc_flush>
  17338. 8006f46: 4603 mov r3, r0
  17339. }
  17340. 8006f48: 4618 mov r0, r3
  17341. 8006f4a: 379c adds r7, #156 ; 0x9c
  17342. 8006f4c: 46bd mov sp, r7
  17343. 8006f4e: e8bd 4080 ldmia.w sp!, {r7, lr}
  17344. 8006f52: b003 add sp, #12
  17345. 8006f54: 4770 bx lr
  17346. 8006f56: bf00 nop
  17347. 08006f58 <FATFS_LinkDriverEx>:
  17348. * @param lun : only used for USB Key Disk to add multi-lun management
  17349. else the parameter must be equal to 0
  17350. * @retval Returns 0 in case of success, otherwise 1.
  17351. */
  17352. uint8_t FATFS_LinkDriverEx(const Diskio_drvTypeDef *drv, char *path, uint8_t lun)
  17353. {
  17354. 8006f58: b480 push {r7}
  17355. 8006f5a: b087 sub sp, #28
  17356. 8006f5c: af00 add r7, sp, #0
  17357. 8006f5e: 60f8 str r0, [r7, #12]
  17358. 8006f60: 60b9 str r1, [r7, #8]
  17359. 8006f62: 4613 mov r3, r2
  17360. 8006f64: 71fb strb r3, [r7, #7]
  17361. uint8_t ret = 1;
  17362. 8006f66: 2301 movs r3, #1
  17363. 8006f68: 75fb strb r3, [r7, #23]
  17364. uint8_t DiskNum = 0;
  17365. 8006f6a: 2300 movs r3, #0
  17366. 8006f6c: 75bb strb r3, [r7, #22]
  17367. if(disk.nbr < _VOLUMES)
  17368. 8006f6e: 4b1e ldr r3, [pc, #120] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17369. 8006f70: 7a5b ldrb r3, [r3, #9]
  17370. 8006f72: b2db uxtb r3, r3
  17371. 8006f74: 2b00 cmp r3, #0
  17372. 8006f76: d131 bne.n 8006fdc <FATFS_LinkDriverEx+0x84>
  17373. {
  17374. disk.is_initialized[disk.nbr] = 0;
  17375. 8006f78: 4b1b ldr r3, [pc, #108] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17376. 8006f7a: 7a5b ldrb r3, [r3, #9]
  17377. 8006f7c: b2db uxtb r3, r3
  17378. 8006f7e: 461a mov r2, r3
  17379. 8006f80: 4b19 ldr r3, [pc, #100] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17380. 8006f82: 2100 movs r1, #0
  17381. 8006f84: 5499 strb r1, [r3, r2]
  17382. disk.drv[disk.nbr] = drv;
  17383. 8006f86: 4b18 ldr r3, [pc, #96] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17384. 8006f88: 7a5b ldrb r3, [r3, #9]
  17385. 8006f8a: b2db uxtb r3, r3
  17386. 8006f8c: 4a16 ldr r2, [pc, #88] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17387. 8006f8e: 009b lsls r3, r3, #2
  17388. 8006f90: 4413 add r3, r2
  17389. 8006f92: 68fa ldr r2, [r7, #12]
  17390. 8006f94: 605a str r2, [r3, #4]
  17391. disk.lun[disk.nbr] = lun;
  17392. 8006f96: 4b14 ldr r3, [pc, #80] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17393. 8006f98: 7a5b ldrb r3, [r3, #9]
  17394. 8006f9a: b2db uxtb r3, r3
  17395. 8006f9c: 461a mov r2, r3
  17396. 8006f9e: 4b12 ldr r3, [pc, #72] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17397. 8006fa0: 4413 add r3, r2
  17398. 8006fa2: 79fa ldrb r2, [r7, #7]
  17399. 8006fa4: 721a strb r2, [r3, #8]
  17400. DiskNum = disk.nbr++;
  17401. 8006fa6: 4b10 ldr r3, [pc, #64] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17402. 8006fa8: 7a5b ldrb r3, [r3, #9]
  17403. 8006faa: b2db uxtb r3, r3
  17404. 8006fac: 1c5a adds r2, r3, #1
  17405. 8006fae: b2d1 uxtb r1, r2
  17406. 8006fb0: 4a0d ldr r2, [pc, #52] ; (8006fe8 <FATFS_LinkDriverEx+0x90>)
  17407. 8006fb2: 7251 strb r1, [r2, #9]
  17408. 8006fb4: 75bb strb r3, [r7, #22]
  17409. path[0] = DiskNum + '0';
  17410. 8006fb6: 7dbb ldrb r3, [r7, #22]
  17411. 8006fb8: 3330 adds r3, #48 ; 0x30
  17412. 8006fba: b2da uxtb r2, r3
  17413. 8006fbc: 68bb ldr r3, [r7, #8]
  17414. 8006fbe: 701a strb r2, [r3, #0]
  17415. path[1] = ':';
  17416. 8006fc0: 68bb ldr r3, [r7, #8]
  17417. 8006fc2: 3301 adds r3, #1
  17418. 8006fc4: 223a movs r2, #58 ; 0x3a
  17419. 8006fc6: 701a strb r2, [r3, #0]
  17420. path[2] = '/';
  17421. 8006fc8: 68bb ldr r3, [r7, #8]
  17422. 8006fca: 3302 adds r3, #2
  17423. 8006fcc: 222f movs r2, #47 ; 0x2f
  17424. 8006fce: 701a strb r2, [r3, #0]
  17425. path[3] = 0;
  17426. 8006fd0: 68bb ldr r3, [r7, #8]
  17427. 8006fd2: 3303 adds r3, #3
  17428. 8006fd4: 2200 movs r2, #0
  17429. 8006fd6: 701a strb r2, [r3, #0]
  17430. ret = 0;
  17431. 8006fd8: 2300 movs r3, #0
  17432. 8006fda: 75fb strb r3, [r7, #23]
  17433. }
  17434. return ret;
  17435. 8006fdc: 7dfb ldrb r3, [r7, #23]
  17436. }
  17437. 8006fde: 4618 mov r0, r3
  17438. 8006fe0: 371c adds r7, #28
  17439. 8006fe2: 46bd mov sp, r7
  17440. 8006fe4: bc80 pop {r7}
  17441. 8006fe6: 4770 bx lr
  17442. 8006fe8: 200002d4 .word 0x200002d4
  17443. 08006fec <FATFS_LinkDriver>:
  17444. * @param drv: pointer to the disk IO Driver structure
  17445. * @param path: pointer to the logical drive path
  17446. * @retval Returns 0 in case of success, otherwise 1.
  17447. */
  17448. uint8_t FATFS_LinkDriver(const Diskio_drvTypeDef *drv, char *path)
  17449. {
  17450. 8006fec: b580 push {r7, lr}
  17451. 8006fee: b082 sub sp, #8
  17452. 8006ff0: af00 add r7, sp, #0
  17453. 8006ff2: 6078 str r0, [r7, #4]
  17454. 8006ff4: 6039 str r1, [r7, #0]
  17455. return FATFS_LinkDriverEx(drv, path, 0);
  17456. 8006ff6: 2200 movs r2, #0
  17457. 8006ff8: 6839 ldr r1, [r7, #0]
  17458. 8006ffa: 6878 ldr r0, [r7, #4]
  17459. 8006ffc: f7ff ffac bl 8006f58 <FATFS_LinkDriverEx>
  17460. 8007000: 4603 mov r3, r0
  17461. }
  17462. 8007002: 4618 mov r0, r3
  17463. 8007004: 3708 adds r7, #8
  17464. 8007006: 46bd mov sp, r7
  17465. 8007008: bd80 pop {r7, pc}
  17466. ...
  17467. 0800700c <ff_convert>:
  17468. WCHAR ff_convert ( /* Converted character, Returns zero on error */
  17469. WCHAR chr, /* Character code to be converted */
  17470. UINT dir /* 0: Unicode to OEM code, 1: OEM code to Unicode */
  17471. )
  17472. {
  17473. 800700c: b480 push {r7}
  17474. 800700e: b085 sub sp, #20
  17475. 8007010: af00 add r7, sp, #0
  17476. 8007012: 4603 mov r3, r0
  17477. 8007014: 6039 str r1, [r7, #0]
  17478. 8007016: 80fb strh r3, [r7, #6]
  17479. WCHAR c;
  17480. if (chr < 0x80) { /* ASCII */
  17481. 8007018: 88fb ldrh r3, [r7, #6]
  17482. 800701a: 2b7f cmp r3, #127 ; 0x7f
  17483. 800701c: d802 bhi.n 8007024 <ff_convert+0x18>
  17484. c = chr;
  17485. 800701e: 88fb ldrh r3, [r7, #6]
  17486. 8007020: 81fb strh r3, [r7, #14]
  17487. 8007022: e025 b.n 8007070 <ff_convert+0x64>
  17488. } else {
  17489. if (dir) { /* OEM code to Unicode */
  17490. 8007024: 683b ldr r3, [r7, #0]
  17491. 8007026: 2b00 cmp r3, #0
  17492. 8007028: d00b beq.n 8007042 <ff_convert+0x36>
  17493. c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80];
  17494. 800702a: 88fb ldrh r3, [r7, #6]
  17495. 800702c: 2bff cmp r3, #255 ; 0xff
  17496. 800702e: d805 bhi.n 800703c <ff_convert+0x30>
  17497. 8007030: 88fb ldrh r3, [r7, #6]
  17498. 8007032: 3b80 subs r3, #128 ; 0x80
  17499. 8007034: 4a11 ldr r2, [pc, #68] ; (800707c <ff_convert+0x70>)
  17500. 8007036: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
  17501. 800703a: e000 b.n 800703e <ff_convert+0x32>
  17502. 800703c: 2300 movs r3, #0
  17503. 800703e: 81fb strh r3, [r7, #14]
  17504. 8007040: e016 b.n 8007070 <ff_convert+0x64>
  17505. } else { /* Unicode to OEM code */
  17506. for (c = 0; c < 0x80; c++) {
  17507. 8007042: 2300 movs r3, #0
  17508. 8007044: 81fb strh r3, [r7, #14]
  17509. 8007046: e009 b.n 800705c <ff_convert+0x50>
  17510. if (chr == Tbl[c]) break;
  17511. 8007048: 89fb ldrh r3, [r7, #14]
  17512. 800704a: 4a0c ldr r2, [pc, #48] ; (800707c <ff_convert+0x70>)
  17513. 800704c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
  17514. 8007050: 88fa ldrh r2, [r7, #6]
  17515. 8007052: 429a cmp r2, r3
  17516. 8007054: d006 beq.n 8007064 <ff_convert+0x58>
  17517. for (c = 0; c < 0x80; c++) {
  17518. 8007056: 89fb ldrh r3, [r7, #14]
  17519. 8007058: 3301 adds r3, #1
  17520. 800705a: 81fb strh r3, [r7, #14]
  17521. 800705c: 89fb ldrh r3, [r7, #14]
  17522. 800705e: 2b7f cmp r3, #127 ; 0x7f
  17523. 8007060: d9f2 bls.n 8007048 <ff_convert+0x3c>
  17524. 8007062: e000 b.n 8007066 <ff_convert+0x5a>
  17525. if (chr == Tbl[c]) break;
  17526. 8007064: bf00 nop
  17527. }
  17528. c = (c + 0x80) & 0xFF;
  17529. 8007066: 89fb ldrh r3, [r7, #14]
  17530. 8007068: 3380 adds r3, #128 ; 0x80
  17531. 800706a: b29b uxth r3, r3
  17532. 800706c: b2db uxtb r3, r3
  17533. 800706e: 81fb strh r3, [r7, #14]
  17534. }
  17535. }
  17536. return c;
  17537. 8007070: 89fb ldrh r3, [r7, #14]
  17538. }
  17539. 8007072: 4618 mov r0, r3
  17540. 8007074: 3714 adds r7, #20
  17541. 8007076: 46bd mov sp, r7
  17542. 8007078: bc80 pop {r7}
  17543. 800707a: 4770 bx lr
  17544. 800707c: 08007c14 .word 0x08007c14
  17545. 08007080 <ff_wtoupper>:
  17546. WCHAR ff_wtoupper ( /* Returns upper converted character */
  17547. WCHAR chr /* Unicode character to be upper converted (BMP only) */
  17548. )
  17549. {
  17550. 8007080: b480 push {r7}
  17551. 8007082: b087 sub sp, #28
  17552. 8007084: af00 add r7, sp, #0
  17553. 8007086: 4603 mov r3, r0
  17554. 8007088: 80fb strh r3, [r7, #6]
  17555. };
  17556. const WCHAR *p;
  17557. WCHAR bc, nc, cmd;
  17558. p = chr < 0x1000 ? cvt1 : cvt2;
  17559. 800708a: 88fb ldrh r3, [r7, #6]
  17560. 800708c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
  17561. 8007090: d201 bcs.n 8007096 <ff_wtoupper+0x16>
  17562. 8007092: 4b3d ldr r3, [pc, #244] ; (8007188 <ff_wtoupper+0x108>)
  17563. 8007094: e000 b.n 8007098 <ff_wtoupper+0x18>
  17564. 8007096: 4b3d ldr r3, [pc, #244] ; (800718c <ff_wtoupper+0x10c>)
  17565. 8007098: 617b str r3, [r7, #20]
  17566. for (;;) {
  17567. bc = *p++; /* Get block base */
  17568. 800709a: 697b ldr r3, [r7, #20]
  17569. 800709c: 1c9a adds r2, r3, #2
  17570. 800709e: 617a str r2, [r7, #20]
  17571. 80070a0: 881b ldrh r3, [r3, #0]
  17572. 80070a2: 827b strh r3, [r7, #18]
  17573. if (!bc || chr < bc) break;
  17574. 80070a4: 8a7b ldrh r3, [r7, #18]
  17575. 80070a6: 2b00 cmp r3, #0
  17576. 80070a8: d068 beq.n 800717c <ff_wtoupper+0xfc>
  17577. 80070aa: 88fa ldrh r2, [r7, #6]
  17578. 80070ac: 8a7b ldrh r3, [r7, #18]
  17579. 80070ae: 429a cmp r2, r3
  17580. 80070b0: d364 bcc.n 800717c <ff_wtoupper+0xfc>
  17581. nc = *p++; cmd = nc >> 8; nc &= 0xFF; /* Get processing command and block size */
  17582. 80070b2: 697b ldr r3, [r7, #20]
  17583. 80070b4: 1c9a adds r2, r3, #2
  17584. 80070b6: 617a str r2, [r7, #20]
  17585. 80070b8: 881b ldrh r3, [r3, #0]
  17586. 80070ba: 823b strh r3, [r7, #16]
  17587. 80070bc: 8a3b ldrh r3, [r7, #16]
  17588. 80070be: 0a1b lsrs r3, r3, #8
  17589. 80070c0: 81fb strh r3, [r7, #14]
  17590. 80070c2: 8a3b ldrh r3, [r7, #16]
  17591. 80070c4: b2db uxtb r3, r3
  17592. 80070c6: 823b strh r3, [r7, #16]
  17593. if (chr < bc + nc) { /* In the block? */
  17594. 80070c8: 88fa ldrh r2, [r7, #6]
  17595. 80070ca: 8a79 ldrh r1, [r7, #18]
  17596. 80070cc: 8a3b ldrh r3, [r7, #16]
  17597. 80070ce: 440b add r3, r1
  17598. 80070d0: 429a cmp r2, r3
  17599. 80070d2: da49 bge.n 8007168 <ff_wtoupper+0xe8>
  17600. switch (cmd) {
  17601. 80070d4: 89fb ldrh r3, [r7, #14]
  17602. 80070d6: 2b08 cmp r3, #8
  17603. 80070d8: d84f bhi.n 800717a <ff_wtoupper+0xfa>
  17604. 80070da: a201 add r2, pc, #4 ; (adr r2, 80070e0 <ff_wtoupper+0x60>)
  17605. 80070dc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
  17606. 80070e0: 08007105 .word 0x08007105
  17607. 80070e4: 08007117 .word 0x08007117
  17608. 80070e8: 0800712d .word 0x0800712d
  17609. 80070ec: 08007135 .word 0x08007135
  17610. 80070f0: 0800713d .word 0x0800713d
  17611. 80070f4: 08007145 .word 0x08007145
  17612. 80070f8: 0800714d .word 0x0800714d
  17613. 80070fc: 08007155 .word 0x08007155
  17614. 8007100: 0800715d .word 0x0800715d
  17615. case 0: chr = p[chr - bc]; break; /* Table conversion */
  17616. 8007104: 88fa ldrh r2, [r7, #6]
  17617. 8007106: 8a7b ldrh r3, [r7, #18]
  17618. 8007108: 1ad3 subs r3, r2, r3
  17619. 800710a: 005b lsls r3, r3, #1
  17620. 800710c: 697a ldr r2, [r7, #20]
  17621. 800710e: 4413 add r3, r2
  17622. 8007110: 881b ldrh r3, [r3, #0]
  17623. 8007112: 80fb strh r3, [r7, #6]
  17624. 8007114: e027 b.n 8007166 <ff_wtoupper+0xe6>
  17625. case 1: chr -= (chr - bc) & 1; break; /* Case pairs */
  17626. 8007116: 88fa ldrh r2, [r7, #6]
  17627. 8007118: 8a7b ldrh r3, [r7, #18]
  17628. 800711a: 1ad3 subs r3, r2, r3
  17629. 800711c: b29b uxth r3, r3
  17630. 800711e: f003 0301 and.w r3, r3, #1
  17631. 8007122: b29b uxth r3, r3
  17632. 8007124: 88fa ldrh r2, [r7, #6]
  17633. 8007126: 1ad3 subs r3, r2, r3
  17634. 8007128: 80fb strh r3, [r7, #6]
  17635. 800712a: e01c b.n 8007166 <ff_wtoupper+0xe6>
  17636. case 2: chr -= 16; break; /* Shift -16 */
  17637. 800712c: 88fb ldrh r3, [r7, #6]
  17638. 800712e: 3b10 subs r3, #16
  17639. 8007130: 80fb strh r3, [r7, #6]
  17640. 8007132: e018 b.n 8007166 <ff_wtoupper+0xe6>
  17641. case 3: chr -= 32; break; /* Shift -32 */
  17642. 8007134: 88fb ldrh r3, [r7, #6]
  17643. 8007136: 3b20 subs r3, #32
  17644. 8007138: 80fb strh r3, [r7, #6]
  17645. 800713a: e014 b.n 8007166 <ff_wtoupper+0xe6>
  17646. case 4: chr -= 48; break; /* Shift -48 */
  17647. 800713c: 88fb ldrh r3, [r7, #6]
  17648. 800713e: 3b30 subs r3, #48 ; 0x30
  17649. 8007140: 80fb strh r3, [r7, #6]
  17650. 8007142: e010 b.n 8007166 <ff_wtoupper+0xe6>
  17651. case 5: chr -= 26; break; /* Shift -26 */
  17652. 8007144: 88fb ldrh r3, [r7, #6]
  17653. 8007146: 3b1a subs r3, #26
  17654. 8007148: 80fb strh r3, [r7, #6]
  17655. 800714a: e00c b.n 8007166 <ff_wtoupper+0xe6>
  17656. case 6: chr += 8; break; /* Shift +8 */
  17657. 800714c: 88fb ldrh r3, [r7, #6]
  17658. 800714e: 3308 adds r3, #8
  17659. 8007150: 80fb strh r3, [r7, #6]
  17660. 8007152: e008 b.n 8007166 <ff_wtoupper+0xe6>
  17661. case 7: chr -= 80; break; /* Shift -80 */
  17662. 8007154: 88fb ldrh r3, [r7, #6]
  17663. 8007156: 3b50 subs r3, #80 ; 0x50
  17664. 8007158: 80fb strh r3, [r7, #6]
  17665. 800715a: e004 b.n 8007166 <ff_wtoupper+0xe6>
  17666. case 8: chr -= 0x1C60; break; /* Shift -0x1C60 */
  17667. 800715c: 88fb ldrh r3, [r7, #6]
  17668. 800715e: f5a3 53e3 sub.w r3, r3, #7264 ; 0x1c60
  17669. 8007162: 80fb strh r3, [r7, #6]
  17670. 8007164: bf00 nop
  17671. }
  17672. break;
  17673. 8007166: e008 b.n 800717a <ff_wtoupper+0xfa>
  17674. }
  17675. if (!cmd) p += nc;
  17676. 8007168: 89fb ldrh r3, [r7, #14]
  17677. 800716a: 2b00 cmp r3, #0
  17678. 800716c: d195 bne.n 800709a <ff_wtoupper+0x1a>
  17679. 800716e: 8a3b ldrh r3, [r7, #16]
  17680. 8007170: 005b lsls r3, r3, #1
  17681. 8007172: 697a ldr r2, [r7, #20]
  17682. 8007174: 4413 add r3, r2
  17683. 8007176: 617b str r3, [r7, #20]
  17684. bc = *p++; /* Get block base */
  17685. 8007178: e78f b.n 800709a <ff_wtoupper+0x1a>
  17686. break;
  17687. 800717a: bf00 nop
  17688. }
  17689. return chr;
  17690. 800717c: 88fb ldrh r3, [r7, #6]
  17691. }
  17692. 800717e: 4618 mov r0, r3
  17693. 8007180: 371c adds r7, #28
  17694. 8007182: 46bd mov sp, r7
  17695. 8007184: bc80 pop {r7}
  17696. 8007186: 4770 bx lr
  17697. 8007188: 08007d14 .word 0x08007d14
  17698. 800718c: 08007f08 .word 0x08007f08
  17699. 08007190 <__errno>:
  17700. 8007190: 4b01 ldr r3, [pc, #4] ; (8007198 <__errno+0x8>)
  17701. 8007192: 6818 ldr r0, [r3, #0]
  17702. 8007194: 4770 bx lr
  17703. 8007196: bf00 nop
  17704. 8007198: 20000024 .word 0x20000024
  17705. 0800719c <__libc_init_array>:
  17706. 800719c: b570 push {r4, r5, r6, lr}
  17707. 800719e: 2500 movs r5, #0
  17708. 80071a0: 4e0c ldr r6, [pc, #48] ; (80071d4 <__libc_init_array+0x38>)
  17709. 80071a2: 4c0d ldr r4, [pc, #52] ; (80071d8 <__libc_init_array+0x3c>)
  17710. 80071a4: 1ba4 subs r4, r4, r6
  17711. 80071a6: 10a4 asrs r4, r4, #2
  17712. 80071a8: 42a5 cmp r5, r4
  17713. 80071aa: d109 bne.n 80071c0 <__libc_init_array+0x24>
  17714. 80071ac: f000 fc44 bl 8007a38 <_init>
  17715. 80071b0: 2500 movs r5, #0
  17716. 80071b2: 4e0a ldr r6, [pc, #40] ; (80071dc <__libc_init_array+0x40>)
  17717. 80071b4: 4c0a ldr r4, [pc, #40] ; (80071e0 <__libc_init_array+0x44>)
  17718. 80071b6: 1ba4 subs r4, r4, r6
  17719. 80071b8: 10a4 asrs r4, r4, #2
  17720. 80071ba: 42a5 cmp r5, r4
  17721. 80071bc: d105 bne.n 80071ca <__libc_init_array+0x2e>
  17722. 80071be: bd70 pop {r4, r5, r6, pc}
  17723. 80071c0: f856 3025 ldr.w r3, [r6, r5, lsl #2]
  17724. 80071c4: 4798 blx r3
  17725. 80071c6: 3501 adds r5, #1
  17726. 80071c8: e7ee b.n 80071a8 <__libc_init_array+0xc>
  17727. 80071ca: f856 3025 ldr.w r3, [r6, r5, lsl #2]
  17728. 80071ce: 4798 blx r3
  17729. 80071d0: 3501 adds r5, #1
  17730. 80071d2: e7f2 b.n 80071ba <__libc_init_array+0x1e>
  17731. 80071d4: 08008000 .word 0x08008000
  17732. 80071d8: 08008000 .word 0x08008000
  17733. 80071dc: 08008000 .word 0x08008000
  17734. 80071e0: 08008004 .word 0x08008004
  17735. 080071e4 <memset>:
  17736. 80071e4: 4603 mov r3, r0
  17737. 80071e6: 4402 add r2, r0
  17738. 80071e8: 4293 cmp r3, r2
  17739. 80071ea: d100 bne.n 80071ee <memset+0xa>
  17740. 80071ec: 4770 bx lr
  17741. 80071ee: f803 1b01 strb.w r1, [r3], #1
  17742. 80071f2: e7f9 b.n 80071e8 <memset+0x4>
  17743. 080071f4 <siprintf>:
  17744. 80071f4: b40e push {r1, r2, r3}
  17745. 80071f6: f06f 4100 mvn.w r1, #2147483648 ; 0x80000000
  17746. 80071fa: b500 push {lr}
  17747. 80071fc: b09c sub sp, #112 ; 0x70
  17748. 80071fe: ab1d add r3, sp, #116 ; 0x74
  17749. 8007200: 9002 str r0, [sp, #8]
  17750. 8007202: 9006 str r0, [sp, #24]
  17751. 8007204: 9107 str r1, [sp, #28]
  17752. 8007206: 9104 str r1, [sp, #16]
  17753. 8007208: 4808 ldr r0, [pc, #32] ; (800722c <siprintf+0x38>)
  17754. 800720a: 4909 ldr r1, [pc, #36] ; (8007230 <siprintf+0x3c>)
  17755. 800720c: f853 2b04 ldr.w r2, [r3], #4
  17756. 8007210: 9105 str r1, [sp, #20]
  17757. 8007212: 6800 ldr r0, [r0, #0]
  17758. 8007214: a902 add r1, sp, #8
  17759. 8007216: 9301 str r3, [sp, #4]
  17760. 8007218: f000 f876 bl 8007308 <_svfiprintf_r>
  17761. 800721c: 2200 movs r2, #0
  17762. 800721e: 9b02 ldr r3, [sp, #8]
  17763. 8007220: 701a strb r2, [r3, #0]
  17764. 8007222: b01c add sp, #112 ; 0x70
  17765. 8007224: f85d eb04 ldr.w lr, [sp], #4
  17766. 8007228: b003 add sp, #12
  17767. 800722a: 4770 bx lr
  17768. 800722c: 20000024 .word 0x20000024
  17769. 8007230: ffff0208 .word 0xffff0208
  17770. 08007234 <strcat>:
  17771. 8007234: 4603 mov r3, r0
  17772. 8007236: b510 push {r4, lr}
  17773. 8007238: 781a ldrb r2, [r3, #0]
  17774. 800723a: 1c5c adds r4, r3, #1
  17775. 800723c: b93a cbnz r2, 800724e <strcat+0x1a>
  17776. 800723e: 3b01 subs r3, #1
  17777. 8007240: f811 2b01 ldrb.w r2, [r1], #1
  17778. 8007244: f803 2f01 strb.w r2, [r3, #1]!
  17779. 8007248: 2a00 cmp r2, #0
  17780. 800724a: d1f9 bne.n 8007240 <strcat+0xc>
  17781. 800724c: bd10 pop {r4, pc}
  17782. 800724e: 4623 mov r3, r4
  17783. 8007250: e7f2 b.n 8007238 <strcat+0x4>
  17784. 08007252 <__ssputs_r>:
  17785. 8007252: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  17786. 8007256: 688e ldr r6, [r1, #8]
  17787. 8007258: 4682 mov sl, r0
  17788. 800725a: 429e cmp r6, r3
  17789. 800725c: 460c mov r4, r1
  17790. 800725e: 4690 mov r8, r2
  17791. 8007260: 4699 mov r9, r3
  17792. 8007262: d837 bhi.n 80072d4 <__ssputs_r+0x82>
  17793. 8007264: 898a ldrh r2, [r1, #12]
  17794. 8007266: f412 6f90 tst.w r2, #1152 ; 0x480
  17795. 800726a: d031 beq.n 80072d0 <__ssputs_r+0x7e>
  17796. 800726c: 2302 movs r3, #2
  17797. 800726e: 6825 ldr r5, [r4, #0]
  17798. 8007270: 6909 ldr r1, [r1, #16]
  17799. 8007272: 1a6f subs r7, r5, r1
  17800. 8007274: 6965 ldr r5, [r4, #20]
  17801. 8007276: eb05 0545 add.w r5, r5, r5, lsl #1
  17802. 800727a: fb95 f5f3 sdiv r5, r5, r3
  17803. 800727e: f109 0301 add.w r3, r9, #1
  17804. 8007282: 443b add r3, r7
  17805. 8007284: 429d cmp r5, r3
  17806. 8007286: bf38 it cc
  17807. 8007288: 461d movcc r5, r3
  17808. 800728a: 0553 lsls r3, r2, #21
  17809. 800728c: d530 bpl.n 80072f0 <__ssputs_r+0x9e>
  17810. 800728e: 4629 mov r1, r5
  17811. 8007290: f000 fb38 bl 8007904 <_malloc_r>
  17812. 8007294: 4606 mov r6, r0
  17813. 8007296: b950 cbnz r0, 80072ae <__ssputs_r+0x5c>
  17814. 8007298: 230c movs r3, #12
  17815. 800729a: f04f 30ff mov.w r0, #4294967295
  17816. 800729e: f8ca 3000 str.w r3, [sl]
  17817. 80072a2: 89a3 ldrh r3, [r4, #12]
  17818. 80072a4: f043 0340 orr.w r3, r3, #64 ; 0x40
  17819. 80072a8: 81a3 strh r3, [r4, #12]
  17820. 80072aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  17821. 80072ae: 463a mov r2, r7
  17822. 80072b0: 6921 ldr r1, [r4, #16]
  17823. 80072b2: f000 fab7 bl 8007824 <memcpy>
  17824. 80072b6: 89a3 ldrh r3, [r4, #12]
  17825. 80072b8: f423 6390 bic.w r3, r3, #1152 ; 0x480
  17826. 80072bc: f043 0380 orr.w r3, r3, #128 ; 0x80
  17827. 80072c0: 81a3 strh r3, [r4, #12]
  17828. 80072c2: 6126 str r6, [r4, #16]
  17829. 80072c4: 443e add r6, r7
  17830. 80072c6: 6026 str r6, [r4, #0]
  17831. 80072c8: 464e mov r6, r9
  17832. 80072ca: 6165 str r5, [r4, #20]
  17833. 80072cc: 1bed subs r5, r5, r7
  17834. 80072ce: 60a5 str r5, [r4, #8]
  17835. 80072d0: 454e cmp r6, r9
  17836. 80072d2: d900 bls.n 80072d6 <__ssputs_r+0x84>
  17837. 80072d4: 464e mov r6, r9
  17838. 80072d6: 4632 mov r2, r6
  17839. 80072d8: 4641 mov r1, r8
  17840. 80072da: 6820 ldr r0, [r4, #0]
  17841. 80072dc: f000 faad bl 800783a <memmove>
  17842. 80072e0: 68a3 ldr r3, [r4, #8]
  17843. 80072e2: 2000 movs r0, #0
  17844. 80072e4: 1b9b subs r3, r3, r6
  17845. 80072e6: 60a3 str r3, [r4, #8]
  17846. 80072e8: 6823 ldr r3, [r4, #0]
  17847. 80072ea: 441e add r6, r3
  17848. 80072ec: 6026 str r6, [r4, #0]
  17849. 80072ee: e7dc b.n 80072aa <__ssputs_r+0x58>
  17850. 80072f0: 462a mov r2, r5
  17851. 80072f2: f000 fb61 bl 80079b8 <_realloc_r>
  17852. 80072f6: 4606 mov r6, r0
  17853. 80072f8: 2800 cmp r0, #0
  17854. 80072fa: d1e2 bne.n 80072c2 <__ssputs_r+0x70>
  17855. 80072fc: 6921 ldr r1, [r4, #16]
  17856. 80072fe: 4650 mov r0, sl
  17857. 8007300: f000 fab4 bl 800786c <_free_r>
  17858. 8007304: e7c8 b.n 8007298 <__ssputs_r+0x46>
  17859. ...
  17860. 08007308 <_svfiprintf_r>:
  17861. 8007308: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
  17862. 800730c: 461d mov r5, r3
  17863. 800730e: 898b ldrh r3, [r1, #12]
  17864. 8007310: b09d sub sp, #116 ; 0x74
  17865. 8007312: 061f lsls r7, r3, #24
  17866. 8007314: 4680 mov r8, r0
  17867. 8007316: 460c mov r4, r1
  17868. 8007318: 4616 mov r6, r2
  17869. 800731a: d50f bpl.n 800733c <_svfiprintf_r+0x34>
  17870. 800731c: 690b ldr r3, [r1, #16]
  17871. 800731e: b96b cbnz r3, 800733c <_svfiprintf_r+0x34>
  17872. 8007320: 2140 movs r1, #64 ; 0x40
  17873. 8007322: f000 faef bl 8007904 <_malloc_r>
  17874. 8007326: 6020 str r0, [r4, #0]
  17875. 8007328: 6120 str r0, [r4, #16]
  17876. 800732a: b928 cbnz r0, 8007338 <_svfiprintf_r+0x30>
  17877. 800732c: 230c movs r3, #12
  17878. 800732e: f8c8 3000 str.w r3, [r8]
  17879. 8007332: f04f 30ff mov.w r0, #4294967295
  17880. 8007336: e0c8 b.n 80074ca <_svfiprintf_r+0x1c2>
  17881. 8007338: 2340 movs r3, #64 ; 0x40
  17882. 800733a: 6163 str r3, [r4, #20]
  17883. 800733c: 2300 movs r3, #0
  17884. 800733e: 9309 str r3, [sp, #36] ; 0x24
  17885. 8007340: 2320 movs r3, #32
  17886. 8007342: f88d 3029 strb.w r3, [sp, #41] ; 0x29
  17887. 8007346: 2330 movs r3, #48 ; 0x30
  17888. 8007348: f04f 0b01 mov.w fp, #1
  17889. 800734c: f88d 302a strb.w r3, [sp, #42] ; 0x2a
  17890. 8007350: 9503 str r5, [sp, #12]
  17891. 8007352: 4637 mov r7, r6
  17892. 8007354: 463d mov r5, r7
  17893. 8007356: f815 3b01 ldrb.w r3, [r5], #1
  17894. 800735a: b10b cbz r3, 8007360 <_svfiprintf_r+0x58>
  17895. 800735c: 2b25 cmp r3, #37 ; 0x25
  17896. 800735e: d13e bne.n 80073de <_svfiprintf_r+0xd6>
  17897. 8007360: ebb7 0a06 subs.w sl, r7, r6
  17898. 8007364: d00b beq.n 800737e <_svfiprintf_r+0x76>
  17899. 8007366: 4653 mov r3, sl
  17900. 8007368: 4632 mov r2, r6
  17901. 800736a: 4621 mov r1, r4
  17902. 800736c: 4640 mov r0, r8
  17903. 800736e: f7ff ff70 bl 8007252 <__ssputs_r>
  17904. 8007372: 3001 adds r0, #1
  17905. 8007374: f000 80a4 beq.w 80074c0 <_svfiprintf_r+0x1b8>
  17906. 8007378: 9b09 ldr r3, [sp, #36] ; 0x24
  17907. 800737a: 4453 add r3, sl
  17908. 800737c: 9309 str r3, [sp, #36] ; 0x24
  17909. 800737e: 783b ldrb r3, [r7, #0]
  17910. 8007380: 2b00 cmp r3, #0
  17911. 8007382: f000 809d beq.w 80074c0 <_svfiprintf_r+0x1b8>
  17912. 8007386: 2300 movs r3, #0
  17913. 8007388: f04f 32ff mov.w r2, #4294967295
  17914. 800738c: e9cd 2305 strd r2, r3, [sp, #20]
  17915. 8007390: 9304 str r3, [sp, #16]
  17916. 8007392: 9307 str r3, [sp, #28]
  17917. 8007394: f88d 3053 strb.w r3, [sp, #83] ; 0x53
  17918. 8007398: 931a str r3, [sp, #104] ; 0x68
  17919. 800739a: 462f mov r7, r5
  17920. 800739c: 2205 movs r2, #5
  17921. 800739e: f817 1b01 ldrb.w r1, [r7], #1
  17922. 80073a2: 4850 ldr r0, [pc, #320] ; (80074e4 <_svfiprintf_r+0x1dc>)
  17923. 80073a4: f000 fa30 bl 8007808 <memchr>
  17924. 80073a8: 9b04 ldr r3, [sp, #16]
  17925. 80073aa: b9d0 cbnz r0, 80073e2 <_svfiprintf_r+0xda>
  17926. 80073ac: 06d9 lsls r1, r3, #27
  17927. 80073ae: bf44 itt mi
  17928. 80073b0: 2220 movmi r2, #32
  17929. 80073b2: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
  17930. 80073b6: 071a lsls r2, r3, #28
  17931. 80073b8: bf44 itt mi
  17932. 80073ba: 222b movmi r2, #43 ; 0x2b
  17933. 80073bc: f88d 2053 strbmi.w r2, [sp, #83] ; 0x53
  17934. 80073c0: 782a ldrb r2, [r5, #0]
  17935. 80073c2: 2a2a cmp r2, #42 ; 0x2a
  17936. 80073c4: d015 beq.n 80073f2 <_svfiprintf_r+0xea>
  17937. 80073c6: 462f mov r7, r5
  17938. 80073c8: 2000 movs r0, #0
  17939. 80073ca: 250a movs r5, #10
  17940. 80073cc: 9a07 ldr r2, [sp, #28]
  17941. 80073ce: 4639 mov r1, r7
  17942. 80073d0: f811 3b01 ldrb.w r3, [r1], #1
  17943. 80073d4: 3b30 subs r3, #48 ; 0x30
  17944. 80073d6: 2b09 cmp r3, #9
  17945. 80073d8: d94d bls.n 8007476 <_svfiprintf_r+0x16e>
  17946. 80073da: b1b8 cbz r0, 800740c <_svfiprintf_r+0x104>
  17947. 80073dc: e00f b.n 80073fe <_svfiprintf_r+0xf6>
  17948. 80073de: 462f mov r7, r5
  17949. 80073e0: e7b8 b.n 8007354 <_svfiprintf_r+0x4c>
  17950. 80073e2: 4a40 ldr r2, [pc, #256] ; (80074e4 <_svfiprintf_r+0x1dc>)
  17951. 80073e4: 463d mov r5, r7
  17952. 80073e6: 1a80 subs r0, r0, r2
  17953. 80073e8: fa0b f000 lsl.w r0, fp, r0
  17954. 80073ec: 4318 orrs r0, r3
  17955. 80073ee: 9004 str r0, [sp, #16]
  17956. 80073f0: e7d3 b.n 800739a <_svfiprintf_r+0x92>
  17957. 80073f2: 9a03 ldr r2, [sp, #12]
  17958. 80073f4: 1d11 adds r1, r2, #4
  17959. 80073f6: 6812 ldr r2, [r2, #0]
  17960. 80073f8: 9103 str r1, [sp, #12]
  17961. 80073fa: 2a00 cmp r2, #0
  17962. 80073fc: db01 blt.n 8007402 <_svfiprintf_r+0xfa>
  17963. 80073fe: 9207 str r2, [sp, #28]
  17964. 8007400: e004 b.n 800740c <_svfiprintf_r+0x104>
  17965. 8007402: 4252 negs r2, r2
  17966. 8007404: f043 0302 orr.w r3, r3, #2
  17967. 8007408: 9207 str r2, [sp, #28]
  17968. 800740a: 9304 str r3, [sp, #16]
  17969. 800740c: 783b ldrb r3, [r7, #0]
  17970. 800740e: 2b2e cmp r3, #46 ; 0x2e
  17971. 8007410: d10c bne.n 800742c <_svfiprintf_r+0x124>
  17972. 8007412: 787b ldrb r3, [r7, #1]
  17973. 8007414: 2b2a cmp r3, #42 ; 0x2a
  17974. 8007416: d133 bne.n 8007480 <_svfiprintf_r+0x178>
  17975. 8007418: 9b03 ldr r3, [sp, #12]
  17976. 800741a: 3702 adds r7, #2
  17977. 800741c: 1d1a adds r2, r3, #4
  17978. 800741e: 681b ldr r3, [r3, #0]
  17979. 8007420: 9203 str r2, [sp, #12]
  17980. 8007422: 2b00 cmp r3, #0
  17981. 8007424: bfb8 it lt
  17982. 8007426: f04f 33ff movlt.w r3, #4294967295
  17983. 800742a: 9305 str r3, [sp, #20]
  17984. 800742c: 4d2e ldr r5, [pc, #184] ; (80074e8 <_svfiprintf_r+0x1e0>)
  17985. 800742e: 2203 movs r2, #3
  17986. 8007430: 7839 ldrb r1, [r7, #0]
  17987. 8007432: 4628 mov r0, r5
  17988. 8007434: f000 f9e8 bl 8007808 <memchr>
  17989. 8007438: b138 cbz r0, 800744a <_svfiprintf_r+0x142>
  17990. 800743a: 2340 movs r3, #64 ; 0x40
  17991. 800743c: 1b40 subs r0, r0, r5
  17992. 800743e: fa03 f000 lsl.w r0, r3, r0
  17993. 8007442: 9b04 ldr r3, [sp, #16]
  17994. 8007444: 3701 adds r7, #1
  17995. 8007446: 4303 orrs r3, r0
  17996. 8007448: 9304 str r3, [sp, #16]
  17997. 800744a: 7839 ldrb r1, [r7, #0]
  17998. 800744c: 2206 movs r2, #6
  17999. 800744e: 4827 ldr r0, [pc, #156] ; (80074ec <_svfiprintf_r+0x1e4>)
  18000. 8007450: 1c7e adds r6, r7, #1
  18001. 8007452: f88d 1028 strb.w r1, [sp, #40] ; 0x28
  18002. 8007456: f000 f9d7 bl 8007808 <memchr>
  18003. 800745a: 2800 cmp r0, #0
  18004. 800745c: d038 beq.n 80074d0 <_svfiprintf_r+0x1c8>
  18005. 800745e: 4b24 ldr r3, [pc, #144] ; (80074f0 <_svfiprintf_r+0x1e8>)
  18006. 8007460: bb13 cbnz r3, 80074a8 <_svfiprintf_r+0x1a0>
  18007. 8007462: 9b03 ldr r3, [sp, #12]
  18008. 8007464: 3307 adds r3, #7
  18009. 8007466: f023 0307 bic.w r3, r3, #7
  18010. 800746a: 3308 adds r3, #8
  18011. 800746c: 9303 str r3, [sp, #12]
  18012. 800746e: 9b09 ldr r3, [sp, #36] ; 0x24
  18013. 8007470: 444b add r3, r9
  18014. 8007472: 9309 str r3, [sp, #36] ; 0x24
  18015. 8007474: e76d b.n 8007352 <_svfiprintf_r+0x4a>
  18016. 8007476: fb05 3202 mla r2, r5, r2, r3
  18017. 800747a: 2001 movs r0, #1
  18018. 800747c: 460f mov r7, r1
  18019. 800747e: e7a6 b.n 80073ce <_svfiprintf_r+0xc6>
  18020. 8007480: 2300 movs r3, #0
  18021. 8007482: 250a movs r5, #10
  18022. 8007484: 4619 mov r1, r3
  18023. 8007486: 3701 adds r7, #1
  18024. 8007488: 9305 str r3, [sp, #20]
  18025. 800748a: 4638 mov r0, r7
  18026. 800748c: f810 2b01 ldrb.w r2, [r0], #1
  18027. 8007490: 3a30 subs r2, #48 ; 0x30
  18028. 8007492: 2a09 cmp r2, #9
  18029. 8007494: d903 bls.n 800749e <_svfiprintf_r+0x196>
  18030. 8007496: 2b00 cmp r3, #0
  18031. 8007498: d0c8 beq.n 800742c <_svfiprintf_r+0x124>
  18032. 800749a: 9105 str r1, [sp, #20]
  18033. 800749c: e7c6 b.n 800742c <_svfiprintf_r+0x124>
  18034. 800749e: fb05 2101 mla r1, r5, r1, r2
  18035. 80074a2: 2301 movs r3, #1
  18036. 80074a4: 4607 mov r7, r0
  18037. 80074a6: e7f0 b.n 800748a <_svfiprintf_r+0x182>
  18038. 80074a8: ab03 add r3, sp, #12
  18039. 80074aa: 9300 str r3, [sp, #0]
  18040. 80074ac: 4622 mov r2, r4
  18041. 80074ae: 4b11 ldr r3, [pc, #68] ; (80074f4 <_svfiprintf_r+0x1ec>)
  18042. 80074b0: a904 add r1, sp, #16
  18043. 80074b2: 4640 mov r0, r8
  18044. 80074b4: f3af 8000 nop.w
  18045. 80074b8: f1b0 3fff cmp.w r0, #4294967295
  18046. 80074bc: 4681 mov r9, r0
  18047. 80074be: d1d6 bne.n 800746e <_svfiprintf_r+0x166>
  18048. 80074c0: 89a3 ldrh r3, [r4, #12]
  18049. 80074c2: 065b lsls r3, r3, #25
  18050. 80074c4: f53f af35 bmi.w 8007332 <_svfiprintf_r+0x2a>
  18051. 80074c8: 9809 ldr r0, [sp, #36] ; 0x24
  18052. 80074ca: b01d add sp, #116 ; 0x74
  18053. 80074cc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
  18054. 80074d0: ab03 add r3, sp, #12
  18055. 80074d2: 9300 str r3, [sp, #0]
  18056. 80074d4: 4622 mov r2, r4
  18057. 80074d6: 4b07 ldr r3, [pc, #28] ; (80074f4 <_svfiprintf_r+0x1ec>)
  18058. 80074d8: a904 add r1, sp, #16
  18059. 80074da: 4640 mov r0, r8
  18060. 80074dc: f000 f882 bl 80075e4 <_printf_i>
  18061. 80074e0: e7ea b.n 80074b8 <_svfiprintf_r+0x1b0>
  18062. 80074e2: bf00 nop
  18063. 80074e4: 08007fc4 .word 0x08007fc4
  18064. 80074e8: 08007fca .word 0x08007fca
  18065. 80074ec: 08007fce .word 0x08007fce
  18066. 80074f0: 00000000 .word 0x00000000
  18067. 80074f4: 08007253 .word 0x08007253
  18068. 080074f8 <_printf_common>:
  18069. 80074f8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
  18070. 80074fc: 4691 mov r9, r2
  18071. 80074fe: 461f mov r7, r3
  18072. 8007500: 688a ldr r2, [r1, #8]
  18073. 8007502: 690b ldr r3, [r1, #16]
  18074. 8007504: 4606 mov r6, r0
  18075. 8007506: 4293 cmp r3, r2
  18076. 8007508: bfb8 it lt
  18077. 800750a: 4613 movlt r3, r2
  18078. 800750c: f8c9 3000 str.w r3, [r9]
  18079. 8007510: f891 2043 ldrb.w r2, [r1, #67] ; 0x43
  18080. 8007514: 460c mov r4, r1
  18081. 8007516: f8dd 8020 ldr.w r8, [sp, #32]
  18082. 800751a: b112 cbz r2, 8007522 <_printf_common+0x2a>
  18083. 800751c: 3301 adds r3, #1
  18084. 800751e: f8c9 3000 str.w r3, [r9]
  18085. 8007522: 6823 ldr r3, [r4, #0]
  18086. 8007524: 0699 lsls r1, r3, #26
  18087. 8007526: bf42 ittt mi
  18088. 8007528: f8d9 3000 ldrmi.w r3, [r9]
  18089. 800752c: 3302 addmi r3, #2
  18090. 800752e: f8c9 3000 strmi.w r3, [r9]
  18091. 8007532: 6825 ldr r5, [r4, #0]
  18092. 8007534: f015 0506 ands.w r5, r5, #6
  18093. 8007538: d107 bne.n 800754a <_printf_common+0x52>
  18094. 800753a: f104 0a19 add.w sl, r4, #25
  18095. 800753e: 68e3 ldr r3, [r4, #12]
  18096. 8007540: f8d9 2000 ldr.w r2, [r9]
  18097. 8007544: 1a9b subs r3, r3, r2
  18098. 8007546: 42ab cmp r3, r5
  18099. 8007548: dc29 bgt.n 800759e <_printf_common+0xa6>
  18100. 800754a: f894 3043 ldrb.w r3, [r4, #67] ; 0x43
  18101. 800754e: 6822 ldr r2, [r4, #0]
  18102. 8007550: 3300 adds r3, #0
  18103. 8007552: bf18 it ne
  18104. 8007554: 2301 movne r3, #1
  18105. 8007556: 0692 lsls r2, r2, #26
  18106. 8007558: d42e bmi.n 80075b8 <_printf_common+0xc0>
  18107. 800755a: f104 0243 add.w r2, r4, #67 ; 0x43
  18108. 800755e: 4639 mov r1, r7
  18109. 8007560: 4630 mov r0, r6
  18110. 8007562: 47c0 blx r8
  18111. 8007564: 3001 adds r0, #1
  18112. 8007566: d021 beq.n 80075ac <_printf_common+0xb4>
  18113. 8007568: 6823 ldr r3, [r4, #0]
  18114. 800756a: 68e5 ldr r5, [r4, #12]
  18115. 800756c: f003 0306 and.w r3, r3, #6
  18116. 8007570: 2b04 cmp r3, #4
  18117. 8007572: bf18 it ne
  18118. 8007574: 2500 movne r5, #0
  18119. 8007576: f8d9 2000 ldr.w r2, [r9]
  18120. 800757a: f04f 0900 mov.w r9, #0
  18121. 800757e: bf08 it eq
  18122. 8007580: 1aad subeq r5, r5, r2
  18123. 8007582: 68a3 ldr r3, [r4, #8]
  18124. 8007584: 6922 ldr r2, [r4, #16]
  18125. 8007586: bf08 it eq
  18126. 8007588: ea25 75e5 biceq.w r5, r5, r5, asr #31
  18127. 800758c: 4293 cmp r3, r2
  18128. 800758e: bfc4 itt gt
  18129. 8007590: 1a9b subgt r3, r3, r2
  18130. 8007592: 18ed addgt r5, r5, r3
  18131. 8007594: 341a adds r4, #26
  18132. 8007596: 454d cmp r5, r9
  18133. 8007598: d11a bne.n 80075d0 <_printf_common+0xd8>
  18134. 800759a: 2000 movs r0, #0
  18135. 800759c: e008 b.n 80075b0 <_printf_common+0xb8>
  18136. 800759e: 2301 movs r3, #1
  18137. 80075a0: 4652 mov r2, sl
  18138. 80075a2: 4639 mov r1, r7
  18139. 80075a4: 4630 mov r0, r6
  18140. 80075a6: 47c0 blx r8
  18141. 80075a8: 3001 adds r0, #1
  18142. 80075aa: d103 bne.n 80075b4 <_printf_common+0xbc>
  18143. 80075ac: f04f 30ff mov.w r0, #4294967295
  18144. 80075b0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
  18145. 80075b4: 3501 adds r5, #1
  18146. 80075b6: e7c2 b.n 800753e <_printf_common+0x46>
  18147. 80075b8: 2030 movs r0, #48 ; 0x30
  18148. 80075ba: 18e1 adds r1, r4, r3
  18149. 80075bc: f881 0043 strb.w r0, [r1, #67] ; 0x43
  18150. 80075c0: 1c5a adds r2, r3, #1
  18151. 80075c2: f894 1045 ldrb.w r1, [r4, #69] ; 0x45
  18152. 80075c6: 4422 add r2, r4
  18153. 80075c8: 3302 adds r3, #2
  18154. 80075ca: f882 1043 strb.w r1, [r2, #67] ; 0x43
  18155. 80075ce: e7c4 b.n 800755a <_printf_common+0x62>
  18156. 80075d0: 2301 movs r3, #1
  18157. 80075d2: 4622 mov r2, r4
  18158. 80075d4: 4639 mov r1, r7
  18159. 80075d6: 4630 mov r0, r6
  18160. 80075d8: 47c0 blx r8
  18161. 80075da: 3001 adds r0, #1
  18162. 80075dc: d0e6 beq.n 80075ac <_printf_common+0xb4>
  18163. 80075de: f109 0901 add.w r9, r9, #1
  18164. 80075e2: e7d8 b.n 8007596 <_printf_common+0x9e>
  18165. 080075e4 <_printf_i>:
  18166. 80075e4: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr}
  18167. 80075e8: f101 0c43 add.w ip, r1, #67 ; 0x43
  18168. 80075ec: 460c mov r4, r1
  18169. 80075ee: 7e09 ldrb r1, [r1, #24]
  18170. 80075f0: b085 sub sp, #20
  18171. 80075f2: 296e cmp r1, #110 ; 0x6e
  18172. 80075f4: 4617 mov r7, r2
  18173. 80075f6: 4606 mov r6, r0
  18174. 80075f8: 4698 mov r8, r3
  18175. 80075fa: 9a0c ldr r2, [sp, #48] ; 0x30
  18176. 80075fc: f000 80b3 beq.w 8007766 <_printf_i+0x182>
  18177. 8007600: d822 bhi.n 8007648 <_printf_i+0x64>
  18178. 8007602: 2963 cmp r1, #99 ; 0x63
  18179. 8007604: d036 beq.n 8007674 <_printf_i+0x90>
  18180. 8007606: d80a bhi.n 800761e <_printf_i+0x3a>
  18181. 8007608: 2900 cmp r1, #0
  18182. 800760a: f000 80b9 beq.w 8007780 <_printf_i+0x19c>
  18183. 800760e: 2958 cmp r1, #88 ; 0x58
  18184. 8007610: f000 8083 beq.w 800771a <_printf_i+0x136>
  18185. 8007614: f104 0542 add.w r5, r4, #66 ; 0x42
  18186. 8007618: f884 1042 strb.w r1, [r4, #66] ; 0x42
  18187. 800761c: e032 b.n 8007684 <_printf_i+0xa0>
  18188. 800761e: 2964 cmp r1, #100 ; 0x64
  18189. 8007620: d001 beq.n 8007626 <_printf_i+0x42>
  18190. 8007622: 2969 cmp r1, #105 ; 0x69
  18191. 8007624: d1f6 bne.n 8007614 <_printf_i+0x30>
  18192. 8007626: 6820 ldr r0, [r4, #0]
  18193. 8007628: 6813 ldr r3, [r2, #0]
  18194. 800762a: 0605 lsls r5, r0, #24
  18195. 800762c: f103 0104 add.w r1, r3, #4
  18196. 8007630: d52a bpl.n 8007688 <_printf_i+0xa4>
  18197. 8007632: 681b ldr r3, [r3, #0]
  18198. 8007634: 6011 str r1, [r2, #0]
  18199. 8007636: 2b00 cmp r3, #0
  18200. 8007638: da03 bge.n 8007642 <_printf_i+0x5e>
  18201. 800763a: 222d movs r2, #45 ; 0x2d
  18202. 800763c: 425b negs r3, r3
  18203. 800763e: f884 2043 strb.w r2, [r4, #67] ; 0x43
  18204. 8007642: 486f ldr r0, [pc, #444] ; (8007800 <_printf_i+0x21c>)
  18205. 8007644: 220a movs r2, #10
  18206. 8007646: e039 b.n 80076bc <_printf_i+0xd8>
  18207. 8007648: 2973 cmp r1, #115 ; 0x73
  18208. 800764a: f000 809d beq.w 8007788 <_printf_i+0x1a4>
  18209. 800764e: d808 bhi.n 8007662 <_printf_i+0x7e>
  18210. 8007650: 296f cmp r1, #111 ; 0x6f
  18211. 8007652: d020 beq.n 8007696 <_printf_i+0xb2>
  18212. 8007654: 2970 cmp r1, #112 ; 0x70
  18213. 8007656: d1dd bne.n 8007614 <_printf_i+0x30>
  18214. 8007658: 6823 ldr r3, [r4, #0]
  18215. 800765a: f043 0320 orr.w r3, r3, #32
  18216. 800765e: 6023 str r3, [r4, #0]
  18217. 8007660: e003 b.n 800766a <_printf_i+0x86>
  18218. 8007662: 2975 cmp r1, #117 ; 0x75
  18219. 8007664: d017 beq.n 8007696 <_printf_i+0xb2>
  18220. 8007666: 2978 cmp r1, #120 ; 0x78
  18221. 8007668: d1d4 bne.n 8007614 <_printf_i+0x30>
  18222. 800766a: 2378 movs r3, #120 ; 0x78
  18223. 800766c: 4865 ldr r0, [pc, #404] ; (8007804 <_printf_i+0x220>)
  18224. 800766e: f884 3045 strb.w r3, [r4, #69] ; 0x45
  18225. 8007672: e055 b.n 8007720 <_printf_i+0x13c>
  18226. 8007674: 6813 ldr r3, [r2, #0]
  18227. 8007676: f104 0542 add.w r5, r4, #66 ; 0x42
  18228. 800767a: 1d19 adds r1, r3, #4
  18229. 800767c: 681b ldr r3, [r3, #0]
  18230. 800767e: 6011 str r1, [r2, #0]
  18231. 8007680: f884 3042 strb.w r3, [r4, #66] ; 0x42
  18232. 8007684: 2301 movs r3, #1
  18233. 8007686: e08c b.n 80077a2 <_printf_i+0x1be>
  18234. 8007688: 681b ldr r3, [r3, #0]
  18235. 800768a: f010 0f40 tst.w r0, #64 ; 0x40
  18236. 800768e: 6011 str r1, [r2, #0]
  18237. 8007690: bf18 it ne
  18238. 8007692: b21b sxthne r3, r3
  18239. 8007694: e7cf b.n 8007636 <_printf_i+0x52>
  18240. 8007696: 6813 ldr r3, [r2, #0]
  18241. 8007698: 6825 ldr r5, [r4, #0]
  18242. 800769a: 1d18 adds r0, r3, #4
  18243. 800769c: 6010 str r0, [r2, #0]
  18244. 800769e: 0628 lsls r0, r5, #24
  18245. 80076a0: d501 bpl.n 80076a6 <_printf_i+0xc2>
  18246. 80076a2: 681b ldr r3, [r3, #0]
  18247. 80076a4: e002 b.n 80076ac <_printf_i+0xc8>
  18248. 80076a6: 0668 lsls r0, r5, #25
  18249. 80076a8: d5fb bpl.n 80076a2 <_printf_i+0xbe>
  18250. 80076aa: 881b ldrh r3, [r3, #0]
  18251. 80076ac: 296f cmp r1, #111 ; 0x6f
  18252. 80076ae: bf14 ite ne
  18253. 80076b0: 220a movne r2, #10
  18254. 80076b2: 2208 moveq r2, #8
  18255. 80076b4: 4852 ldr r0, [pc, #328] ; (8007800 <_printf_i+0x21c>)
  18256. 80076b6: 2100 movs r1, #0
  18257. 80076b8: f884 1043 strb.w r1, [r4, #67] ; 0x43
  18258. 80076bc: 6865 ldr r5, [r4, #4]
  18259. 80076be: 2d00 cmp r5, #0
  18260. 80076c0: 60a5 str r5, [r4, #8]
  18261. 80076c2: f2c0 8095 blt.w 80077f0 <_printf_i+0x20c>
  18262. 80076c6: 6821 ldr r1, [r4, #0]
  18263. 80076c8: f021 0104 bic.w r1, r1, #4
  18264. 80076cc: 6021 str r1, [r4, #0]
  18265. 80076ce: 2b00 cmp r3, #0
  18266. 80076d0: d13d bne.n 800774e <_printf_i+0x16a>
  18267. 80076d2: 2d00 cmp r5, #0
  18268. 80076d4: f040 808e bne.w 80077f4 <_printf_i+0x210>
  18269. 80076d8: 4665 mov r5, ip
  18270. 80076da: 2a08 cmp r2, #8
  18271. 80076dc: d10b bne.n 80076f6 <_printf_i+0x112>
  18272. 80076de: 6823 ldr r3, [r4, #0]
  18273. 80076e0: 07db lsls r3, r3, #31
  18274. 80076e2: d508 bpl.n 80076f6 <_printf_i+0x112>
  18275. 80076e4: 6923 ldr r3, [r4, #16]
  18276. 80076e6: 6862 ldr r2, [r4, #4]
  18277. 80076e8: 429a cmp r2, r3
  18278. 80076ea: bfde ittt le
  18279. 80076ec: 2330 movle r3, #48 ; 0x30
  18280. 80076ee: f805 3c01 strble.w r3, [r5, #-1]
  18281. 80076f2: f105 35ff addle.w r5, r5, #4294967295
  18282. 80076f6: ebac 0305 sub.w r3, ip, r5
  18283. 80076fa: 6123 str r3, [r4, #16]
  18284. 80076fc: f8cd 8000 str.w r8, [sp]
  18285. 8007700: 463b mov r3, r7
  18286. 8007702: aa03 add r2, sp, #12
  18287. 8007704: 4621 mov r1, r4
  18288. 8007706: 4630 mov r0, r6
  18289. 8007708: f7ff fef6 bl 80074f8 <_printf_common>
  18290. 800770c: 3001 adds r0, #1
  18291. 800770e: d14d bne.n 80077ac <_printf_i+0x1c8>
  18292. 8007710: f04f 30ff mov.w r0, #4294967295
  18293. 8007714: b005 add sp, #20
  18294. 8007716: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
  18295. 800771a: 4839 ldr r0, [pc, #228] ; (8007800 <_printf_i+0x21c>)
  18296. 800771c: f884 1045 strb.w r1, [r4, #69] ; 0x45
  18297. 8007720: 6813 ldr r3, [r2, #0]
  18298. 8007722: 6821 ldr r1, [r4, #0]
  18299. 8007724: 1d1d adds r5, r3, #4
  18300. 8007726: 681b ldr r3, [r3, #0]
  18301. 8007728: 6015 str r5, [r2, #0]
  18302. 800772a: 060a lsls r2, r1, #24
  18303. 800772c: d50b bpl.n 8007746 <_printf_i+0x162>
  18304. 800772e: 07ca lsls r2, r1, #31
  18305. 8007730: bf44 itt mi
  18306. 8007732: f041 0120 orrmi.w r1, r1, #32
  18307. 8007736: 6021 strmi r1, [r4, #0]
  18308. 8007738: b91b cbnz r3, 8007742 <_printf_i+0x15e>
  18309. 800773a: 6822 ldr r2, [r4, #0]
  18310. 800773c: f022 0220 bic.w r2, r2, #32
  18311. 8007740: 6022 str r2, [r4, #0]
  18312. 8007742: 2210 movs r2, #16
  18313. 8007744: e7b7 b.n 80076b6 <_printf_i+0xd2>
  18314. 8007746: 064d lsls r5, r1, #25
  18315. 8007748: bf48 it mi
  18316. 800774a: b29b uxthmi r3, r3
  18317. 800774c: e7ef b.n 800772e <_printf_i+0x14a>
  18318. 800774e: 4665 mov r5, ip
  18319. 8007750: fbb3 f1f2 udiv r1, r3, r2
  18320. 8007754: fb02 3311 mls r3, r2, r1, r3
  18321. 8007758: 5cc3 ldrb r3, [r0, r3]
  18322. 800775a: f805 3d01 strb.w r3, [r5, #-1]!
  18323. 800775e: 460b mov r3, r1
  18324. 8007760: 2900 cmp r1, #0
  18325. 8007762: d1f5 bne.n 8007750 <_printf_i+0x16c>
  18326. 8007764: e7b9 b.n 80076da <_printf_i+0xf6>
  18327. 8007766: 6813 ldr r3, [r2, #0]
  18328. 8007768: 6825 ldr r5, [r4, #0]
  18329. 800776a: 1d18 adds r0, r3, #4
  18330. 800776c: 6961 ldr r1, [r4, #20]
  18331. 800776e: 6010 str r0, [r2, #0]
  18332. 8007770: 0628 lsls r0, r5, #24
  18333. 8007772: 681b ldr r3, [r3, #0]
  18334. 8007774: d501 bpl.n 800777a <_printf_i+0x196>
  18335. 8007776: 6019 str r1, [r3, #0]
  18336. 8007778: e002 b.n 8007780 <_printf_i+0x19c>
  18337. 800777a: 066a lsls r2, r5, #25
  18338. 800777c: d5fb bpl.n 8007776 <_printf_i+0x192>
  18339. 800777e: 8019 strh r1, [r3, #0]
  18340. 8007780: 2300 movs r3, #0
  18341. 8007782: 4665 mov r5, ip
  18342. 8007784: 6123 str r3, [r4, #16]
  18343. 8007786: e7b9 b.n 80076fc <_printf_i+0x118>
  18344. 8007788: 6813 ldr r3, [r2, #0]
  18345. 800778a: 1d19 adds r1, r3, #4
  18346. 800778c: 6011 str r1, [r2, #0]
  18347. 800778e: 681d ldr r5, [r3, #0]
  18348. 8007790: 6862 ldr r2, [r4, #4]
  18349. 8007792: 2100 movs r1, #0
  18350. 8007794: 4628 mov r0, r5
  18351. 8007796: f000 f837 bl 8007808 <memchr>
  18352. 800779a: b108 cbz r0, 80077a0 <_printf_i+0x1bc>
  18353. 800779c: 1b40 subs r0, r0, r5
  18354. 800779e: 6060 str r0, [r4, #4]
  18355. 80077a0: 6863 ldr r3, [r4, #4]
  18356. 80077a2: 6123 str r3, [r4, #16]
  18357. 80077a4: 2300 movs r3, #0
  18358. 80077a6: f884 3043 strb.w r3, [r4, #67] ; 0x43
  18359. 80077aa: e7a7 b.n 80076fc <_printf_i+0x118>
  18360. 80077ac: 6923 ldr r3, [r4, #16]
  18361. 80077ae: 462a mov r2, r5
  18362. 80077b0: 4639 mov r1, r7
  18363. 80077b2: 4630 mov r0, r6
  18364. 80077b4: 47c0 blx r8
  18365. 80077b6: 3001 adds r0, #1
  18366. 80077b8: d0aa beq.n 8007710 <_printf_i+0x12c>
  18367. 80077ba: 6823 ldr r3, [r4, #0]
  18368. 80077bc: 079b lsls r3, r3, #30
  18369. 80077be: d413 bmi.n 80077e8 <_printf_i+0x204>
  18370. 80077c0: 68e0 ldr r0, [r4, #12]
  18371. 80077c2: 9b03 ldr r3, [sp, #12]
  18372. 80077c4: 4298 cmp r0, r3
  18373. 80077c6: bfb8 it lt
  18374. 80077c8: 4618 movlt r0, r3
  18375. 80077ca: e7a3 b.n 8007714 <_printf_i+0x130>
  18376. 80077cc: 2301 movs r3, #1
  18377. 80077ce: 464a mov r2, r9
  18378. 80077d0: 4639 mov r1, r7
  18379. 80077d2: 4630 mov r0, r6
  18380. 80077d4: 47c0 blx r8
  18381. 80077d6: 3001 adds r0, #1
  18382. 80077d8: d09a beq.n 8007710 <_printf_i+0x12c>
  18383. 80077da: 3501 adds r5, #1
  18384. 80077dc: 68e3 ldr r3, [r4, #12]
  18385. 80077de: 9a03 ldr r2, [sp, #12]
  18386. 80077e0: 1a9b subs r3, r3, r2
  18387. 80077e2: 42ab cmp r3, r5
  18388. 80077e4: dcf2 bgt.n 80077cc <_printf_i+0x1e8>
  18389. 80077e6: e7eb b.n 80077c0 <_printf_i+0x1dc>
  18390. 80077e8: 2500 movs r5, #0
  18391. 80077ea: f104 0919 add.w r9, r4, #25
  18392. 80077ee: e7f5 b.n 80077dc <_printf_i+0x1f8>
  18393. 80077f0: 2b00 cmp r3, #0
  18394. 80077f2: d1ac bne.n 800774e <_printf_i+0x16a>
  18395. 80077f4: 7803 ldrb r3, [r0, #0]
  18396. 80077f6: f104 0542 add.w r5, r4, #66 ; 0x42
  18397. 80077fa: f884 3042 strb.w r3, [r4, #66] ; 0x42
  18398. 80077fe: e76c b.n 80076da <_printf_i+0xf6>
  18399. 8007800: 08007fd5 .word 0x08007fd5
  18400. 8007804: 08007fe6 .word 0x08007fe6
  18401. 08007808 <memchr>:
  18402. 8007808: b510 push {r4, lr}
  18403. 800780a: b2c9 uxtb r1, r1
  18404. 800780c: 4402 add r2, r0
  18405. 800780e: 4290 cmp r0, r2
  18406. 8007810: 4603 mov r3, r0
  18407. 8007812: d101 bne.n 8007818 <memchr+0x10>
  18408. 8007814: 2300 movs r3, #0
  18409. 8007816: e003 b.n 8007820 <memchr+0x18>
  18410. 8007818: 781c ldrb r4, [r3, #0]
  18411. 800781a: 3001 adds r0, #1
  18412. 800781c: 428c cmp r4, r1
  18413. 800781e: d1f6 bne.n 800780e <memchr+0x6>
  18414. 8007820: 4618 mov r0, r3
  18415. 8007822: bd10 pop {r4, pc}
  18416. 08007824 <memcpy>:
  18417. 8007824: b510 push {r4, lr}
  18418. 8007826: 1e43 subs r3, r0, #1
  18419. 8007828: 440a add r2, r1
  18420. 800782a: 4291 cmp r1, r2
  18421. 800782c: d100 bne.n 8007830 <memcpy+0xc>
  18422. 800782e: bd10 pop {r4, pc}
  18423. 8007830: f811 4b01 ldrb.w r4, [r1], #1
  18424. 8007834: f803 4f01 strb.w r4, [r3, #1]!
  18425. 8007838: e7f7 b.n 800782a <memcpy+0x6>
  18426. 0800783a <memmove>:
  18427. 800783a: 4288 cmp r0, r1
  18428. 800783c: b510 push {r4, lr}
  18429. 800783e: eb01 0302 add.w r3, r1, r2
  18430. 8007842: d807 bhi.n 8007854 <memmove+0x1a>
  18431. 8007844: 1e42 subs r2, r0, #1
  18432. 8007846: 4299 cmp r1, r3
  18433. 8007848: d00a beq.n 8007860 <memmove+0x26>
  18434. 800784a: f811 4b01 ldrb.w r4, [r1], #1
  18435. 800784e: f802 4f01 strb.w r4, [r2, #1]!
  18436. 8007852: e7f8 b.n 8007846 <memmove+0xc>
  18437. 8007854: 4283 cmp r3, r0
  18438. 8007856: d9f5 bls.n 8007844 <memmove+0xa>
  18439. 8007858: 1881 adds r1, r0, r2
  18440. 800785a: 1ad2 subs r2, r2, r3
  18441. 800785c: 42d3 cmn r3, r2
  18442. 800785e: d100 bne.n 8007862 <memmove+0x28>
  18443. 8007860: bd10 pop {r4, pc}
  18444. 8007862: f813 4d01 ldrb.w r4, [r3, #-1]!
  18445. 8007866: f801 4d01 strb.w r4, [r1, #-1]!
  18446. 800786a: e7f7 b.n 800785c <memmove+0x22>
  18447. 0800786c <_free_r>:
  18448. 800786c: b538 push {r3, r4, r5, lr}
  18449. 800786e: 4605 mov r5, r0
  18450. 8007870: 2900 cmp r1, #0
  18451. 8007872: d043 beq.n 80078fc <_free_r+0x90>
  18452. 8007874: f851 3c04 ldr.w r3, [r1, #-4]
  18453. 8007878: 1f0c subs r4, r1, #4
  18454. 800787a: 2b00 cmp r3, #0
  18455. 800787c: bfb8 it lt
  18456. 800787e: 18e4 addlt r4, r4, r3
  18457. 8007880: f000 f8d0 bl 8007a24 <__malloc_lock>
  18458. 8007884: 4a1e ldr r2, [pc, #120] ; (8007900 <_free_r+0x94>)
  18459. 8007886: 6813 ldr r3, [r2, #0]
  18460. 8007888: 4610 mov r0, r2
  18461. 800788a: b933 cbnz r3, 800789a <_free_r+0x2e>
  18462. 800788c: 6063 str r3, [r4, #4]
  18463. 800788e: 6014 str r4, [r2, #0]
  18464. 8007890: 4628 mov r0, r5
  18465. 8007892: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
  18466. 8007896: f000 b8c6 b.w 8007a26 <__malloc_unlock>
  18467. 800789a: 42a3 cmp r3, r4
  18468. 800789c: d90b bls.n 80078b6 <_free_r+0x4a>
  18469. 800789e: 6821 ldr r1, [r4, #0]
  18470. 80078a0: 1862 adds r2, r4, r1
  18471. 80078a2: 4293 cmp r3, r2
  18472. 80078a4: bf01 itttt eq
  18473. 80078a6: 681a ldreq r2, [r3, #0]
  18474. 80078a8: 685b ldreq r3, [r3, #4]
  18475. 80078aa: 1852 addeq r2, r2, r1
  18476. 80078ac: 6022 streq r2, [r4, #0]
  18477. 80078ae: 6063 str r3, [r4, #4]
  18478. 80078b0: 6004 str r4, [r0, #0]
  18479. 80078b2: e7ed b.n 8007890 <_free_r+0x24>
  18480. 80078b4: 4613 mov r3, r2
  18481. 80078b6: 685a ldr r2, [r3, #4]
  18482. 80078b8: b10a cbz r2, 80078be <_free_r+0x52>
  18483. 80078ba: 42a2 cmp r2, r4
  18484. 80078bc: d9fa bls.n 80078b4 <_free_r+0x48>
  18485. 80078be: 6819 ldr r1, [r3, #0]
  18486. 80078c0: 1858 adds r0, r3, r1
  18487. 80078c2: 42a0 cmp r0, r4
  18488. 80078c4: d10b bne.n 80078de <_free_r+0x72>
  18489. 80078c6: 6820 ldr r0, [r4, #0]
  18490. 80078c8: 4401 add r1, r0
  18491. 80078ca: 1858 adds r0, r3, r1
  18492. 80078cc: 4282 cmp r2, r0
  18493. 80078ce: 6019 str r1, [r3, #0]
  18494. 80078d0: d1de bne.n 8007890 <_free_r+0x24>
  18495. 80078d2: 6810 ldr r0, [r2, #0]
  18496. 80078d4: 6852 ldr r2, [r2, #4]
  18497. 80078d6: 4401 add r1, r0
  18498. 80078d8: 6019 str r1, [r3, #0]
  18499. 80078da: 605a str r2, [r3, #4]
  18500. 80078dc: e7d8 b.n 8007890 <_free_r+0x24>
  18501. 80078de: d902 bls.n 80078e6 <_free_r+0x7a>
  18502. 80078e0: 230c movs r3, #12
  18503. 80078e2: 602b str r3, [r5, #0]
  18504. 80078e4: e7d4 b.n 8007890 <_free_r+0x24>
  18505. 80078e6: 6820 ldr r0, [r4, #0]
  18506. 80078e8: 1821 adds r1, r4, r0
  18507. 80078ea: 428a cmp r2, r1
  18508. 80078ec: bf01 itttt eq
  18509. 80078ee: 6811 ldreq r1, [r2, #0]
  18510. 80078f0: 6852 ldreq r2, [r2, #4]
  18511. 80078f2: 1809 addeq r1, r1, r0
  18512. 80078f4: 6021 streq r1, [r4, #0]
  18513. 80078f6: 6062 str r2, [r4, #4]
  18514. 80078f8: 605c str r4, [r3, #4]
  18515. 80078fa: e7c9 b.n 8007890 <_free_r+0x24>
  18516. 80078fc: bd38 pop {r3, r4, r5, pc}
  18517. 80078fe: bf00 nop
  18518. 8007900: 200002e0 .word 0x200002e0
  18519. 08007904 <_malloc_r>:
  18520. 8007904: b570 push {r4, r5, r6, lr}
  18521. 8007906: 1ccd adds r5, r1, #3
  18522. 8007908: f025 0503 bic.w r5, r5, #3
  18523. 800790c: 3508 adds r5, #8
  18524. 800790e: 2d0c cmp r5, #12
  18525. 8007910: bf38 it cc
  18526. 8007912: 250c movcc r5, #12
  18527. 8007914: 2d00 cmp r5, #0
  18528. 8007916: 4606 mov r6, r0
  18529. 8007918: db01 blt.n 800791e <_malloc_r+0x1a>
  18530. 800791a: 42a9 cmp r1, r5
  18531. 800791c: d903 bls.n 8007926 <_malloc_r+0x22>
  18532. 800791e: 230c movs r3, #12
  18533. 8007920: 6033 str r3, [r6, #0]
  18534. 8007922: 2000 movs r0, #0
  18535. 8007924: bd70 pop {r4, r5, r6, pc}
  18536. 8007926: f000 f87d bl 8007a24 <__malloc_lock>
  18537. 800792a: 4a21 ldr r2, [pc, #132] ; (80079b0 <_malloc_r+0xac>)
  18538. 800792c: 6814 ldr r4, [r2, #0]
  18539. 800792e: 4621 mov r1, r4
  18540. 8007930: b991 cbnz r1, 8007958 <_malloc_r+0x54>
  18541. 8007932: 4c20 ldr r4, [pc, #128] ; (80079b4 <_malloc_r+0xb0>)
  18542. 8007934: 6823 ldr r3, [r4, #0]
  18543. 8007936: b91b cbnz r3, 8007940 <_malloc_r+0x3c>
  18544. 8007938: 4630 mov r0, r6
  18545. 800793a: f000 f863 bl 8007a04 <_sbrk_r>
  18546. 800793e: 6020 str r0, [r4, #0]
  18547. 8007940: 4629 mov r1, r5
  18548. 8007942: 4630 mov r0, r6
  18549. 8007944: f000 f85e bl 8007a04 <_sbrk_r>
  18550. 8007948: 1c43 adds r3, r0, #1
  18551. 800794a: d124 bne.n 8007996 <_malloc_r+0x92>
  18552. 800794c: 230c movs r3, #12
  18553. 800794e: 4630 mov r0, r6
  18554. 8007950: 6033 str r3, [r6, #0]
  18555. 8007952: f000 f868 bl 8007a26 <__malloc_unlock>
  18556. 8007956: e7e4 b.n 8007922 <_malloc_r+0x1e>
  18557. 8007958: 680b ldr r3, [r1, #0]
  18558. 800795a: 1b5b subs r3, r3, r5
  18559. 800795c: d418 bmi.n 8007990 <_malloc_r+0x8c>
  18560. 800795e: 2b0b cmp r3, #11
  18561. 8007960: d90f bls.n 8007982 <_malloc_r+0x7e>
  18562. 8007962: 600b str r3, [r1, #0]
  18563. 8007964: 18cc adds r4, r1, r3
  18564. 8007966: 50cd str r5, [r1, r3]
  18565. 8007968: 4630 mov r0, r6
  18566. 800796a: f000 f85c bl 8007a26 <__malloc_unlock>
  18567. 800796e: f104 000b add.w r0, r4, #11
  18568. 8007972: 1d23 adds r3, r4, #4
  18569. 8007974: f020 0007 bic.w r0, r0, #7
  18570. 8007978: 1ac3 subs r3, r0, r3
  18571. 800797a: d0d3 beq.n 8007924 <_malloc_r+0x20>
  18572. 800797c: 425a negs r2, r3
  18573. 800797e: 50e2 str r2, [r4, r3]
  18574. 8007980: e7d0 b.n 8007924 <_malloc_r+0x20>
  18575. 8007982: 684b ldr r3, [r1, #4]
  18576. 8007984: 428c cmp r4, r1
  18577. 8007986: bf16 itet ne
  18578. 8007988: 6063 strne r3, [r4, #4]
  18579. 800798a: 6013 streq r3, [r2, #0]
  18580. 800798c: 460c movne r4, r1
  18581. 800798e: e7eb b.n 8007968 <_malloc_r+0x64>
  18582. 8007990: 460c mov r4, r1
  18583. 8007992: 6849 ldr r1, [r1, #4]
  18584. 8007994: e7cc b.n 8007930 <_malloc_r+0x2c>
  18585. 8007996: 1cc4 adds r4, r0, #3
  18586. 8007998: f024 0403 bic.w r4, r4, #3
  18587. 800799c: 42a0 cmp r0, r4
  18588. 800799e: d005 beq.n 80079ac <_malloc_r+0xa8>
  18589. 80079a0: 1a21 subs r1, r4, r0
  18590. 80079a2: 4630 mov r0, r6
  18591. 80079a4: f000 f82e bl 8007a04 <_sbrk_r>
  18592. 80079a8: 3001 adds r0, #1
  18593. 80079aa: d0cf beq.n 800794c <_malloc_r+0x48>
  18594. 80079ac: 6025 str r5, [r4, #0]
  18595. 80079ae: e7db b.n 8007968 <_malloc_r+0x64>
  18596. 80079b0: 200002e0 .word 0x200002e0
  18597. 80079b4: 200002e4 .word 0x200002e4
  18598. 080079b8 <_realloc_r>:
  18599. 80079b8: b5f8 push {r3, r4, r5, r6, r7, lr}
  18600. 80079ba: 4607 mov r7, r0
  18601. 80079bc: 4614 mov r4, r2
  18602. 80079be: 460e mov r6, r1
  18603. 80079c0: b921 cbnz r1, 80079cc <_realloc_r+0x14>
  18604. 80079c2: e8bd 40f8 ldmia.w sp!, {r3, r4, r5, r6, r7, lr}
  18605. 80079c6: 4611 mov r1, r2
  18606. 80079c8: f7ff bf9c b.w 8007904 <_malloc_r>
  18607. 80079cc: b922 cbnz r2, 80079d8 <_realloc_r+0x20>
  18608. 80079ce: f7ff ff4d bl 800786c <_free_r>
  18609. 80079d2: 4625 mov r5, r4
  18610. 80079d4: 4628 mov r0, r5
  18611. 80079d6: bdf8 pop {r3, r4, r5, r6, r7, pc}
  18612. 80079d8: f000 f826 bl 8007a28 <_malloc_usable_size_r>
  18613. 80079dc: 42a0 cmp r0, r4
  18614. 80079de: d20f bcs.n 8007a00 <_realloc_r+0x48>
  18615. 80079e0: 4621 mov r1, r4
  18616. 80079e2: 4638 mov r0, r7
  18617. 80079e4: f7ff ff8e bl 8007904 <_malloc_r>
  18618. 80079e8: 4605 mov r5, r0
  18619. 80079ea: 2800 cmp r0, #0
  18620. 80079ec: d0f2 beq.n 80079d4 <_realloc_r+0x1c>
  18621. 80079ee: 4631 mov r1, r6
  18622. 80079f0: 4622 mov r2, r4
  18623. 80079f2: f7ff ff17 bl 8007824 <memcpy>
  18624. 80079f6: 4631 mov r1, r6
  18625. 80079f8: 4638 mov r0, r7
  18626. 80079fa: f7ff ff37 bl 800786c <_free_r>
  18627. 80079fe: e7e9 b.n 80079d4 <_realloc_r+0x1c>
  18628. 8007a00: 4635 mov r5, r6
  18629. 8007a02: e7e7 b.n 80079d4 <_realloc_r+0x1c>
  18630. 08007a04 <_sbrk_r>:
  18631. 8007a04: b538 push {r3, r4, r5, lr}
  18632. 8007a06: 2300 movs r3, #0
  18633. 8007a08: 4c05 ldr r4, [pc, #20] ; (8007a20 <_sbrk_r+0x1c>)
  18634. 8007a0a: 4605 mov r5, r0
  18635. 8007a0c: 4608 mov r0, r1
  18636. 8007a0e: 6023 str r3, [r4, #0]
  18637. 8007a10: f7f9 fdd8 bl 80015c4 <_sbrk>
  18638. 8007a14: 1c43 adds r3, r0, #1
  18639. 8007a16: d102 bne.n 8007a1e <_sbrk_r+0x1a>
  18640. 8007a18: 6823 ldr r3, [r4, #0]
  18641. 8007a1a: b103 cbz r3, 8007a1e <_sbrk_r+0x1a>
  18642. 8007a1c: 602b str r3, [r5, #0]
  18643. 8007a1e: bd38 pop {r3, r4, r5, pc}
  18644. 8007a20: 20004550 .word 0x20004550
  18645. 08007a24 <__malloc_lock>:
  18646. 8007a24: 4770 bx lr
  18647. 08007a26 <__malloc_unlock>:
  18648. 8007a26: 4770 bx lr
  18649. 08007a28 <_malloc_usable_size_r>:
  18650. 8007a28: f851 3c04 ldr.w r3, [r1, #-4]
  18651. 8007a2c: 1f18 subs r0, r3, #4
  18652. 8007a2e: 2b00 cmp r3, #0
  18653. 8007a30: bfbc itt lt
  18654. 8007a32: 580b ldrlt r3, [r1, r0]
  18655. 8007a34: 18c0 addlt r0, r0, r3
  18656. 8007a36: 4770 bx lr
  18657. 08007a38 <_init>:
  18658. 8007a38: b5f8 push {r3, r4, r5, r6, r7, lr}
  18659. 8007a3a: bf00 nop
  18660. 8007a3c: bcf8 pop {r3, r4, r5, r6, r7}
  18661. 8007a3e: bc08 pop {r3}
  18662. 8007a40: 469e mov lr, r3
  18663. 8007a42: 4770 bx lr
  18664. 08007a44 <_fini>:
  18665. 8007a44: b5f8 push {r3, r4, r5, r6, r7, lr}
  18666. 8007a46: bf00 nop
  18667. 8007a48: bcf8 pop {r3, r4, r5, r6, r7}
  18668. 8007a4a: bc08 pop {r3}
  18669. 8007a4c: 469e mov lr, r3
  18670. 8007a4e: 4770 bx lr