signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

-- Anlegen der Variablen des Programms
entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

-- Signale anlegen
architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
	signal index_run :integer range 0 to 2;
	signal start_value : std_logic;
	signal done_value : std_logic;
	signal write_value : std_logic_vector( 31 downto 0 );

begin
	-- Instanziierung der float_add.vhd
	u_float_add : entity work.float_add
		port map(
			clk => clk,
			reset => reset,
			start => start_value,
			done => done_value,
			a => signal_a_readdata,
			b => signal_b_readdata,
			sum => write_value
		);

	-- Zustandsautomat fuer die Zustandsswechsel
    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

	-- Zustandautomat fuer die Berechnung
    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
			-- alle Signale in der Reset Bedingung initialisieren
			start_value <= '0';
			signal_a_read <= '0';
			signal_b_read <= '0';
			signal_write <= '0';
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
				-- idle
		        when work.task.TASK_IDLE =>
		            index <= 0;
		            signal_write <= '0';
				-- running
		        when work.task.TASK_RUNNING =>
					case index_run is					

						when 0 =>
							signal_writedata <= ( others => '0' );
							start_value <= '1';
							index_run <= index_run + 1;

						when 1 =>
							if(done_value = '1') then
								start_value <= '0';
															
								signal_write <= '1';
								signal_writedata <= write_value;
								
								signal_a_read <= '1';
								signal_b_read <= '1';

								index_run <= index_run + 1;
							end if;
						when 2 =>
							signal_write <= '0';
							signal_a_read <= '0';
							signal_b_read <= '0';
							index_run <= 0;	
							index <= index + 1;						
					end case;			
				-- done
		        when work.task.TASK_DONE =>
		            index <= 0;
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;