signal_processing_vorlage/hardware/signal_processing/sine.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.float.all;
    use work.task.all;

entity sine is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        step_size : in work.reg32.word;
        phase : in work.reg32.word;
        amplitude : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity sine;

architecture rtl of sine is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;
	signal index_run :integer range 0 to 2;
	signal data_valid : std_logic;
	signal busy : std_logic;
	signal result_valid : std_logic;
	signal angle : signed(31 downto 0);
	signal write_value : signed(31 downto 0);

begin
	-- Instanziierung der float_sine.vhd
	u_float_sine : entity work.float_sine 
		generic map(
			ITERATIONS => 8
		)
		port map(
        	clk => clk,
        	reset => reset,

        	data_valid => data_valid,
        	busy => busy,
        	result_valid => result_valid,
        	angle => angle,
        	sine => write_value
    	);

	-- Zustandsautomat fuer die Zustandsswechsel
    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN ) then -- - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

	-- Zustandautomat fuer die Berechnung
    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            index <= 0;
			-- alle Signale in der Reset Bedingung initialisieren
			data_valid <= '0';
			signal_write <= '0';
			angle <= x"00000000";
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
				-- idle
		        when work.task.TASK_IDLE =>
		            index <= 0;
		            signal_write <= '0';
				-- running
		        when work.task.TASK_RUNNING =>
					case index_run is					
						when 0 =>
							signal_write <= '0';
							angle <= angle + signed(step_size);--signed(phase)
							data_valid <= '1';
						
							index_run <= index_run + 1;
						when 1 =>
							data_valid <= '0';
							if(result_valid = '1') then
								signal_write <= '1';
								signal_writedata <= std_logic_vector(write_value);

								index_run <= index_run + 1;
							end if;
						when 2 =>
							signal_write <= '0';
							index_run <= 0;
							index <= index + 1;											
					end case;
				-- done
		        when work.task.TASK_DONE =>
		            index <= 0;
		            signal_write <= '0';
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;