126 lines
3.4 KiB
VHDL
126 lines
3.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.float.all;
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use work.task.all;
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entity sine is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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step_size : in work.reg32.word;
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phase : in work.reg32.word;
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amplitude : in work.reg32.word;
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity sine;
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architecture rtl of sine is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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signal index_run :integer range 0 to 2;
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signal data_valid : std_logic;
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signal busy : std_logic;
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signal result_valid : std_logic;
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signal angle : signed(31 downto 0);
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signal write_value : signed(31 downto 0);
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begin
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-- Instanziierung der float_sine.vhd
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u_float_sine : entity work.float_sine
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generic map(
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ITERATIONS => 8
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)
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port map(
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clk => clk,
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reset => reset,
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data_valid => data_valid,
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busy => busy,
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result_valid => result_valid,
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angle => angle,
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sine => write_value
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);
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-- Zustandsautomat fuer die Zustandsswechsel
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN ) then -- - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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-- Zustandautomat fuer die Berechnung
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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-- alle Signale in der Reset Bedingung initialisieren
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data_valid <= '0';
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signal_write <= '0';
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angle <= x"00000000";
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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-- idle
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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-- running
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when work.task.TASK_RUNNING =>
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case index_run is
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when 0 =>
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signal_write <= '0';
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angle <= angle + signed(step_size);--signed(phase)
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data_valid <= '1';
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index_run <= index_run + 1;
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when 1 =>
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data_valid <= '0';
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if(result_valid = '1') then
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signal_write <= '1';
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signal_writedata <= std_logic_vector(write_value);
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index_run <= index_run + 1;
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end if;
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when 2 =>
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signal_write <= '0';
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index_run <= 0;
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index <= index + 1;
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end case;
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-- done
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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