KutningJo/signal_processing_vorlage
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Started implementing Task Sine in vhdl

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schoeffelbe82781 2024-11-13 11:08:56 +01:00
parent 45e909c886
commit 151772a809
1 changed files with 33 additions and 0 deletions
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33
hardware/signal_processing/sine.vhd
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@ -30,7 +30,39 @@ architecture rtl of sine is
signal next_task_state : work.task.State; signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN; signal index : integer range 0 to work.task.STREAM_LEN;
type CalcState is (
CALC_IDLE,
CALC_READ,
CALC_PROCESS,
CALC_WRITE
);
signal Calc_State : CalcState;
signal data_valid_ipcore : std_logic;
signal busy_ipcore : std_logic;
signal result_valid_ipcore : std_logic;
signal phase_ipcore : signed(31 downto 0);
signal sine_ipcore : signed(31 downto 0);
begin begin
u_float_sine: entity work.float_sine
generic map(
ITERATIONS => 8
)
port map(
clk => clk,
reset => reset,
data_valid => data_valid_ipcore,
busy => busy_ipcore,
result_valid => result_valid_ipcore,
-- " TODO Check if this is allowed (direkt access to maped signal)"
angle => phase_ipcore,
sine => sine_ipcore
);
task_state_transitions : process ( current_task_state, task_start, index ) is task_state_transitions : process ( current_task_state, task_start, index ) is
begin begin
next_task_state <= current_task_state; next_task_state <= current_task_state;
@ -73,5 +105,6 @@ begin
end process sync; end process sync;
task_state <= current_task_state; task_state <= current_task_state;
phase_ipcore <= (SIGNED(phase));
end architecture rtl; end architecture rtl;