Sollte theoretisch funktionieren

hardware/signal_processing/add.vhd

@@ -13,8 +13,8 @@ entity add is
 
         task_start : in std_logic;
         task_state : out work.task.State;
-
-        signal_a_read : out std_logic;
+					
+        signal_a_read : out std_logic;				--signal_read wird als Bestätigung gesetzt, dass die Daten gelesen wurden, d.h. bei der nächsten rising edge werden die nächsten Daten angelegt.
         signal_a_readdata : in std_logic_vector( 31 downto 0 );
 
         signal_b_read : out std_logic;
@@ -30,7 +30,39 @@ architecture rtl of add is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	--hier noch einige Signale anlegen
+	signal done_flag  : std_logic;
+	signal start_flag : std_logic;
+
+	--Zustände für die Zustandsmaschine für die Berechnung
+	type CalcState is (
+		CALC_IDLE,
+		CALC_ADD,
+		CALC_STORE_RESULT
+	);
+
+	--Signale für die Zustandsmaschine für die Berechnung
+	signal current_calc_state : CalcState;
+	signal next_calc_state : CalcState;
+
+	signal ergebnis : signed( 31 downto 0);	--das hier vielleicht zu std_logic_vector oder float
+	signal ergebnis_valid : std_logic;
+
 begin
+
+	u_float_add : entity work.float_add --Das hier ist der IP Core !!!
+	port map(
+		clk =>		clk,
+		reset =>	reset,
+		start =>	start_flag,
+		done =>		done_flag,
+		A =>		signal_a_readdata,
+		B =>		signal_b_readdata,
+		sum =>		signal_writedata
+	);
+
+    --task_state_transitions wird nicht geaendert
+    --Übergangsschaltnetz der Zustandsmaschine zu Steuerung der Tasks
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -50,28 +82,71 @@ begin
         end case;
     end process task_state_transitions;
 
-    sync : process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            current_task_state <= work.task.TASK_IDLE;
-            index <= 0;
-        elsif ( rising_edge( clk ) ) then
-            current_task_state <= next_task_state;
-            case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
-            when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
-            end case;
-        end if;
-    end process sync;
+	
+	--Übergangsschaltnetz der Zustandsmaschine für die Berechnung ###Fertig
+	calc_state_transitions: process (all) is
+	begin
+		next_calc_state <= current_calc_state; 
+		case current_calc_state is
+			when CALC_IDLE=>
+				if (current_task_state= work.task.TASK_RUNNING) then 
+					next_calc_state <= CALC_ADD;
+				end if;
+			when CALC_ADD =>
+				if (done_flag = '1') then
+					next_calc_state <= CALC_STORE_RESULT;
+				end if;
+			when CALC STORE RESULT =>
+				next_calc_state <= CALC_IDLE;
+		end case;
+	end process calc state transitions;
 
-    task_state <= current_task_state;
+
+	--Zustandsspeicher und Ausgangsschaltnetz zu der Steuerung der Tasks 
+	task_sync : process (clk, reset) is
+	begin
+		if (reset = '1') then
+			current_task_state <= work.task.TASK_IDLE;
+			
+		elsif (rising_edge( clk)) then
+			current_task_state <= next_task_state; 
+			case next_task_state is
+				when work.task. TASK IDLE => null;
+				when work.task. TASK_RUNNING => null; 
+				when work.task. TASK_DONE => null;
+			end case;
+		end if;
+	end process task_sync;
+
+	--Zustandsspeicher und Ausgangsschaltnetz zu Berechnung 
+	sync : process (clk, reset) is
+	begin
+		if (reset = '1') then
+			index <= 0;
+			current_calc_state <= CALC_IDLE;
+			ergebnis <= (others => '0'); 
+			ergebnis_valid <= '0';
+			signal_write <= '0';
+			signal_writedata <= (others => '0'); 
+		elsif (rising_edge( clk)) then
+			current_calc_state <= next_calc_state; 
+			ergebnis_valid <= '0';
+			case next_calc_state is 
+				when CALC_IDLE =>
+					start_flag <= '0';
+					signal_read <= '0';	--Daten wurden noch nicht verwendet.
+					signal_write <= '0';
+				when CALC_ADD => 				--hier Berechnung mit IP Core?
+					start_flag <= '1';
+				when CALC_STORE_RESULT =>
+					start_flag <= '0';
+					index <= index + 1;
+					signal_write <= '1';
+					--signal_writedata <= std_logic_vector( ergebnis ); --Ergebnis schreiben, ergebnis direkt aus IP Core anschliessen
+					signal_read <= '1'	--mitteilen, dass die Daten gelesen wurden und jetzt neue Daten angelegt werden sollen
+			end case;
+		end if;
+	end process sync;
+	task_state <= current_task_state;
 
 end architecture rtl;

software/signal_processing/add.c

@@ -5,6 +5,18 @@
 int task_add_run( void * task ) {
 
     // TODO
+	add_config * config = ( add_config * ) task;
+
+// Nachfolgende Antworten lesen..
+	for ( uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++) {
+		float a;
+		data_channel_read( config->sources[ 0 ], ( uint32_t * ) & a );
+		float b;
+		data_channel_read( config->sources[ 1 ], ( uint32_t * ) & b );
+		float_word c;
+		c.value = a + b;
+		data_channel_write( config->sink, c.word );
+	}
 
     return 0;
 }