Finished Task Rand in vhdl

hardware/signal_processing/add.vhd

@@ -30,7 +30,34 @@ architecture rtl of add is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	signal start_ipcore : std_logic;
+	signal done_ipcore : std_logic;
+
+	signal a_readdata : std_logic_vector(31 downto 0);
+	signal b_readdata : std_logic_vector(31 downto 0);
+	signal result : std_logic_vector(31 downto 0);
+
+	type CalcState is (
+		CALC_IDLE,
+		CALC_READ,
+		CALC_PROCESS,	
+		CALC_WRITE
+	);
+	signal Calc_State : CalcState;
+
+
 begin
+	u_float_add: entity work.float_add
+		port map (
+			clk => clk,
+			reset => reset,
+			start => start_ipcore,
+			done => done_ipcore,
+			A => a_readdata,
+			B => b_readdata,
+			sum => result
+		);
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -39,14 +66,17 @@ begin
                 if ( task_start = '1' ) then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
+
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
+
             when work.task.TASK_DONE =>
                 if ( task_start = '1' ) then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
+
         end case;
     end process task_state_transitions;
 
@@ -54,24 +84,52 @@ begin
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
+			Calc_State <= CALC_IDLE;
             index <= 0;
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
-            when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
+				when work.task.TASK_IDLE =>
+					index <= 0;
+					Calc_State <= CALC_IDLE;
+					signal_write <= '0';
+
+				when work.task.TASK_RUNNING =>
+					case Calc_State is
+						when CALC_IDLE =>
+							Calc_State <= CALC_READ;
+						when CALC_READ =>
+							signal_write <= '0';
+							signal_a_read <= '1';
+							signal_b_read <= '1';
+							Calc_State <= CALC_PROCESS;
+						when CALC_PROCESS =>
+							signal_a_read <= '0';
+							signal_b_read <= '0';
+							start_ipcore <= '1';
+							if(done_ipcore = '1') then
+								start_ipcore <= '0';
+								Calc_State <= CALC_WRITE;
+							end if;
+						when CALC_WRITE =>
+							Calc_State <= CALC_READ;
+							index <= index + 1;
+							signal_write <= '1';
+					end case;
+
+				when work.task.TASK_DONE =>
+					index <= 0;
+					Calc_State <= CALC_IDLE;
+					signal_write <= '0';
+
             end case;
         end if;
     end process sync;
 
+	signal_writedata <= result;
+	a_readdata <= signal_a_readdata;
+	b_readdata <= signal_b_readdata;
+
     task_state <= current_task_state;
 
 end architecture rtl;

hardware/signal_processing/rand.vhd

@@ -26,6 +26,19 @@ architecture rtl of rand is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	type CalcState is (
+		CALC_IDLE,
+		CALC_WRITE
+	);
+	signal Calc_State : CalcState;
+
+	signal lsfr : SIGNED( 31 downto 0 );
+	signal lsfr_std_logic : std_logic_vector( 31 downto 0 );
+	signal POLYNOM : std_logic_vector (31 downto 0);
+
+	signal lsfr_dump : SIGNED( 31 downto 0 );
+
+
 begin
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
@@ -47,20 +60,59 @@ begin
     end process task_state_transitions;
 
     sync : process ( clk, reset ) is
+	variable var_lsfr_logic : std_logic_vector( 31 downto 0);
+	variable var_lsfr_signed : SIGNED( 31 downto 0);
+
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
+			Calc_State <= CALC_IDLE; 
+			lsfr <= SIGNED(seed);
+			lsfr_std_logic <= seed;
+			POLYNOM <= (others => '0');
+			POLYNOM(31) <= '1';
+			POLYNOM(21) <= '1';
+			POLYNOM(1) <= '1';
+			POLYNOM(0) <= '1';
             index <= 0;
+
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
             when work.task.TASK_IDLE =>
                 index <= 0;
+				lsfr <= SIGNED(seed);
                 signal_write <= '0';
+
             when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
+				case Calc_State is
+					when CALC_IDLE =>
+						signal_write <= '0';
+						var_lsfr_logic := STD_LOGIC_VECTOR(lsfr);
+						if(var_lsfr_logic(0) = '1') then
+							var_lsfr_logic := '0' & (var_lsfr_logic(31 downto 1));
+							--var_lsfr_logic := (var_lsfr_logic(31:1);
+							var_lsfr_logic := (var_lsfr_logic XOR POLYNOM);
+						else
+							--var_lsfr_logic := (var_lsfr_logic srl 1);
+							var_lsfr_logic := '0' & var_lsfr_logic(31 downto 1);
+						end if;	
+						var_lsfr_signed := SIGNED(var_lsfr_logic);
+						lsfr_dump <= SIGNED(var_lsfr_logic);
+
+						if(var_lsfr_signed(30) = '1') then
+							var_lsfr_signed := var_lsfr_signed(31 downto 31) & "1000000" & var_lsfr_signed(23 downto 0);
+						else
+							var_lsfr_signed := var_lsfr_signed(31 downto 31) & "011111" & var_lsfr_signed(24 downto 0);
+						end if;
+						lsfr <= var_lsfr_signed;
+						Calc_State <= CALC_WRITE;
+					when CALC_WRITE =>
+						signal_write <= '1';
+						index <= index + 1;
+						Calc_State <= CALC_IDLE;
+				end case;
+
             when work.task.TASK_DONE =>
                 index <= 0;
                 signal_write <= '0';
@@ -69,5 +121,6 @@ begin
     end process sync;
 
     task_state <= current_task_state;
+	signal_writedata <= STD_LOGIC_VECTOR(lsfr);
 
 end architecture rtl;

hardware/signal_processing/sine.vhd

@@ -30,7 +30,43 @@ architecture rtl of sine is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	type CalcState is (
+		CALC_IDLE,
+		CALC_ANGLE,
+		CALC_START,
+		CALC_BUSY,	
+		CALC_WRITE,
+		CALC_DONE
+	);
+	signal Calc_State : CalcState;
+
+	signal data_valid_ipcore : std_logic;
+	signal busy_ipcore : std_logic;
+	signal result_valid_ipcore : std_logic;
+
+	signal angle_ipcore : signed(31 downto 0); 
+	signal step_size_adapted : std_logic_vector( 31 downto 0 );
+	signal sine_amplitude : signed(31 downto 0);
+	signal sine_ipcore : signed(31 downto 0);
+
+	
 begin
+	u_float_sine: entity work.float_sine
+		generic map(
+			ITERATIONS => 8
+		)
+		port map(
+			clk => clk,
+			reset => reset,
+
+			data_valid => data_valid_ipcore,
+			busy => busy_ipcore,
+			result_valid => result_valid_ipcore,
+			-- " TODO Check if this is allowed (direkt access to maped signal)"
+			angle => angle_ipcore,
+			sine => sine_ipcore
+		);
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -40,7 +76,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -54,24 +90,66 @@ begin
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
+			Calc_State <= CALC_IDLE;
             index <= 0;
+			signal_write <= '0';
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
-            when work.task.TASK_DONE =>
-                index <= 0;
-                signal_write <= '0';
+				when work.task.TASK_IDLE =>
+					index <= 0;
+					signal_write <= '0';
+					Calc_State <= CALC_IDLE;
+
+				when work.task.TASK_RUNNING =>
+					case Calc_State is
+						when CALC_IDLE =>
+							angle_ipcore <= SIGNED(phase);
+							Calc_State <= CALC_START;
+
+						when CALC_ANGLE =>
+							angle_ipcore <= (angle_ipcore + (SIGNED(step_size_adapted))); 
+							Calc_State <= CALC_START;
+
+						when CALC_START =>
+							data_valid_ipcore <= '1';
+							if(busy_ipcore = '1') then
+								Calc_State <= CALC_BUSY;
+							end if;
+
+						when CALC_BUSY =>
+							data_valid_ipcore <= '0';
+							if(result_valid_ipcore = '1') then
+								Calc_State <= CALC_WRITE;
+							end if;
+
+						when CALC_WRITE =>
+							-- sine_amplitude <= sine_ipcore(30 downto 23) + (signed(amplitude))(30 downto 23) - "127";
+							sine_amplitude <= sine_ipcore(31 downto 31) & (sine_ipcore(30 downto 23) + (signed(amplitude(30 downto 23)) - 127)) & sine_ipcore(22 downto 0);  
+							-- sine_amplitude <= STD_LOGIC_VECTOR(sine_ipcore(30 downto 23)) + STD_LOGIC_VECTOR(amplitude(30 downto 23)) - "127";
+							
+							signal_write <= '1';
+							Calc_State <= CALC_DONE;
+
+						when CALC_DONE =>
+							signal_write <= '0';
+							index <= index + 1;
+							Calc_State <= CALC_ANGLE;
+					end case;
+
+				when work.task.TASK_DONE =>
+					index <= 0;
+					signal_write <= '0';
             end case;
         end if;
     end process sync;
 
+	signal_writedata <= STD_LOGIC_VECTOR(sine_amplitude);
+	--step_size_adapted <= (step_size(31-5 downto 0) & "00000");
+	step_size_adapted <= (step_size );
+
+
     task_state <= current_task_state;
+	-- #TODO phase_ipcore <= (SIGNED(phase));
 
 end architecture rtl;

software/signal_processing/add.c

@@ -3,8 +3,18 @@
 #include "system/float_word.h"
 
 int task_add_run( void * task ) {
+	add_config* taskConfig = (add_config*) task;
 
-    // TODO
+	for(uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
+		float chnl1, chnl2;
+		data_channel_read(taskConfig->sources[0], (uint32_t*) &chnl1);
+		data_channel_read(taskConfig->sources[1], (uint32_t*) &chnl2);
+
+		float_word result;
+		result.value = chnl1 + chnl2;
+
+		data_channel_write(taskConfig->sink, result.word);
+	}
 
     return 0;
 }

software/signal_processing/rand.c

@@ -3,9 +3,72 @@
 #include "system/data_channel.h"
 #include "system/float_word.h"
 
-int task_rand_run( void * task ) {
+#include "stdio.h"
 
-    // TODO
+#define POLYNOM ((1 << 31)|(1 << 21)|(1 << 1)|(1 << 0))
+
+int32_t shift_lsfr(int32_t *lsfr) {
+	int feedback;
+
+	feedback = *lsfr & 1;
+
+	*lsfr >>= 1;
+
+	if(feedback == 1)
+		*lsfr ^= POLYNOM;
+	return *lsfr;
+
+}
+
+int32_t pot(int32_t base, int exp) {
+	int32_t res = 1;
+	while(exp-- >= 0)
+		res *= base;
+
+	return res;
+}
+
+uint8_t clamp_value(uint8_t value) {
+		
+	if(value & 128) {
+		value &= 0b10000001;
+		//value &= ((1 << 7) | (1 << 0));
+	} else {
+		//value |= ~((1 << 1) | (1 << 0));
+		value |= 0b01111100;
+	}
+	return value;
+
+}
+
+int task_rand_run( void * task ) {
+	
+	rand_config* config = ( rand_config* ) task;
+	float_word seed = { .value = config->seed };
+
+	uint32_t lfsr = seed.word;
+
+	uint32_t data_channel_base = config->base.sink;
+	data_channel_clear(data_channel_base);
+
+	for(uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
+		float_word res, value;
+
+		//res.value = lfsr;
+		//
+
+
+		uint32_t E = (value.word >> 23) & 0xff;
+		E = clamp_value(E);
+		
+		res.word = value.word;
+		res.word &= ~(0xFF << 23);
+		res.word |= (E << 23);
+
+		value.word = shift_lsfr(&lfsr) ;
+
+		data_channel_write( data_channel_base, res.word);
+	}
 
     return 0;
 }

software/signal_processing/sine.c

@@ -2,9 +2,21 @@
 #include "system/data_channel.h"
 #include "system/float_word.h"
 
-int task_sine_run( void * data ) {
+#include <math.h>
 
-    // TODO
+int task_sine_run( void * data ) {
+	sine_config* task = (sine_config*) data;
+
+	uint32_t data_chnl_base = task->base.sink;
+	data_channel_clear(data_chnl_base);
+
+	for(uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
+		float_word result;
+		result.value = task->amplitude * sin(task->phase + ((2 * M_PI)/(double)task->samples_per_periode) * i);
+
+		data_channel_write(data_chnl_base, result.word);
+	}
+	
 
     return 0;
 }

software/signal_processing/system/task_rand.c

@@ -21,7 +21,7 @@ rand_config RAND_CONFIG = {
         .cycle_count = 0 },
     .seed = 1.3,
     .abs_min = 0.125,
-    .abs_max = 9.0 };
+    .abs_max = 8.0 };
 
 int task_rand_configure( void * data ) {
     rand_config * task = ( rand_config * ) data;