FPGA Software bearbeitet

hardware/signal_processing/add.vhd

@@ -30,7 +30,40 @@ architecture rtl of add is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+--Initialisierung der weiteren Ablaufstruktur
+type AddState is (
+	AddIdle,
+	AddWait1,
+	AddStart,	
+	AddAddition,
+	AddStore 
+);
+
+--Signale fuer die Zustandsmaschine
+signal current_add_state : AddState;
+signal next_add_state : AddState;
+signal A      : std_logic_vector(31 downto 0);
+signal B      : std_logic_vector(31 downto 0);
+signal start  : std_logic;
+signal done   : std_logic;
+signal sum    : std_logic_vector ( 31 downto 0 );
+
+
 begin
+
+
+    c_float_add : entity work.float_add
+	PORT MAP (
+	  	A      => A,
+	       	B      => B,
+	       	clk    => clk,
+	       	reset  => reset,
+	       	start  => start,
+	       	done   => done,
+	       	sum    => sum
+	       	);
+
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -40,7 +73,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if ( index = work.task.STREAM_LEN) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -50,11 +83,43 @@ begin
         end case;
     end process task_state_transitions;
 
+----------------------------------------------------------------------
+	add_state_transitions : process ( all ) is
+	begin
+		next_add_state <= current_add_state;
+		case current_add_state is
+			when AddIdle =>
+				if ( current_task_state = work.task.TASK_RUNNING ) then -- Weiterschaltbedingung					
+					next_add_state <= AddStart;	
+				end if;
+
+			when AddStart =>
+				next_add_state <= AddAddition;
+
+			when AddAddition =>
+				next_add_state <= AddWait1;	-- Weiterschaltbedingung
+
+			when AddWait1 =>
+				if ( done = '1' ) then	-- Weiterschaltbedingung
+					next_add_state <= AddStore;
+				end if;
+
+			when AddStore =>
+				next_add_state <= AddIdle; 	-- Weiterschaltbedingung
+
+		end case;
+	end process add_state_transitions;
+----------------------------------------------------------------------
     sync : process ( clk, reset ) is
-    begin
+    begin							--INDEX WIRD NOCH JEDEN TAKT HOCHGEZÄHLT UND NICHT NUR WENN DAS ERGEBNIS GESPEICHERT WIRD
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
+	    current_add_state <= AddIdle;
             index <= 0;
+	    start <= '0';
+	    A <= ( others => '0' );
+	    B <= ( others => '0' );
+	    
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
@@ -62,13 +127,45 @@ begin
                 index <= 0;
                 signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                index <= index + 1;
+                --index <= index + 1;
                 signal_write <= '1';
                 signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
                 index <= 0;
                 signal_write <= '0';
             end case;
+
+		-------------------------------------------
+	    current_add_state <= next_add_state;
+	    signal_write <= '0';
+	    signal_a_read <= '0';
+	    signal_b_read <= '0';
+	    case next_add_state is
+		when AddIdle =>
+			signal_write <= '0';
+			start <= '0';
+		when AddStart =>
+			--start <= '1';
+			
+		when AddAddition =>
+			start <= '1';
+			signal_a_read <= '1';
+			signal_b_read <= '1';
+			A <= signal_a_readdata;
+			B <= signal_b_readdata;			
+
+		when AddWait1 =>
+			signal_a_read <= '0';
+			signal_b_read <= '0';
+
+		when AddStore =>
+			signal_write <= '1';
+			signal_writedata <= sum;
+			index <= index + 1;
+
+
+	   end case;
+		-------------------------------------------
         end if;
     end process sync;
 

hardware/signal_processing/fft.vhd

@@ -1,26 +1,13 @@
 ------------------------------------------------------------------------
 -- fft
 --
--- calculation of FFT magnitudes
+-- calculation of FFT magnitude
 --
 -- Inputs:
 -- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
 --
 -- Outputs
 -- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
--- 
---
--- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor 
--- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist) 
--- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln 
--- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0) 
--- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich) 
--- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float) 
--- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32). 
--- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist) 
--- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html) 
--- (z.B: ein Array verwenden, um die Werte zu sortieren)
--- Dann das Ergebnis in den Ausgangsfifo speichern 
 --
 -----------------------------------------------------------------------
 library ieee;
@@ -35,10 +22,10 @@ library work;
 entity fft is
   generic (
 
-    -- input data width of real/img part 
+    -- input data width of real/img part
       input_data_width : integer := 32;
 
-    -- output data width of real/img part 
+    -- output data width of real/img part
       output_data_width : integer := 32
 
     );
@@ -48,10 +35,10 @@ entity fft is
 
         task_start : in std_logic;
         task_state : out work.task.State;
-	  
+
         signal_read : out std_logic;
         signal_readdata : in std_logic_vector( 31 downto 0 );
-		  
+
         signal_write : out std_logic;
         signal_writedata : out std_logic_vector( 31 downto 0 )
     );
@@ -59,112 +46,100 @@ end entity fft;
 
 architecture rtl of fft is
 
-
--- Signale für Task State Machine
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
-    --signal index : integer range 0 to 2000;
 
--- component des Verilog IP-Cores fuer die FFT
 component fftmain is
-	port(
-		clock: in std_logic; -- Master Clock
-		reset: in std_logic; -- Active High Asynchronous Reset
-		di_en: in std_logic; --  Input Data Enable
-		di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
-                di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
-		do_en: out std_logic; -- Output Data Enable
-		do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
-                do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
+    port(
+	clock: in std_logic;  --  Master Clock
+    	reset: in std_logic;  --  Active High Asynchronous Reset
+    	di_en: in std_logic; --  Input Data Enable
+    	di_re: in std_logic_vector(input_data_width-1 downto 0); --   Input Data (Real)
+   	di_im: in std_logic_vector(input_data_width-1 downto 0); --  Input Data (Imag)
+   	do_en: out std_logic; --  Output Data Enable
+	do_re: out std_logic_vector(output_data_width-1 downto 0); --  Output Data (Real)
+        do_im: out std_logic_vector(output_data_width-1 downto 0) --    Output Data (Imag)
 	);
 end component;
+--Initialisierung der weiteren Ablaufstruktur
+type FFTState is (
+	FFTIdle,
+	FFTRead,
+	FFTWait,	
+	MAGRead,
+	MAGStore 
+);
 
---  Signale Input skaliert
-    signal fft_float_input : signed( 31 downto 0 ); 
-    signal fft_float_scaled_input : signed( 31 downto 0 ); 
+--Signale fuer die Zustandsmaschine
+signal current_fft_state : FFTState;
+signal next_fft_state : FFTState;
+--signal fifo_in     	: unsigned(31 downto 0);
+constant B		: signed(7 downto 0) := "00000100";
+--signal C     	 	: unsigned(31 downto 0);
+--signal D     	 	: unsigned(31 downto 0);
+--signal E     	 	: unsigned(31 downto 0);
+--signal F     	 	: unsigned(31 downto 0);
+signal read_index 	: integer range 0 to work.task.STREAM_LEN +100;
+signal fft_index 	: integer range 0 to work.task.STREAM_LEN;
+signal result 		: std_logic_vector ( 31 downto 0 );
+signal input_valid	: std_logic;
+signal input_re 	: std_logic_vector( 31 downto 0 ); -- in Fixpoint
+signal input_im 	: std_logic_vector( 31 downto 0 ); -- in Fixpoint
+signal output_valid 	: std_logic;
+signal output_magnitude : std_logic_vector( 31 downto 0 );
+signal cnt		: integer range 0 to work.task.STREAM_LEN;
+signal di_en		: std_logic; --  Input Data Enable
+signal di_re		: std_logic_vector(31 downto 0); --   Input Data (Real)
+signal di_im		: std_logic_vector(31 downto 0); --  Input Data (Imag)
+signal do_en		: std_logic; --  Output Data Enable
+signal do_re		: std_logic_vector(31 downto 0); --  Output Data (Real)
+signal do_im		: std_logic_vector(31 downto 0); --    Output Data (Imag)
 
--- Signale fuer FFT-IP Core
-    -- fft data input signal
-    signal fft_input_data_enable: std_logic;
-    signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
-    signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
-    -- fft output data
-    signal fft_output_valid : std_logic;
-    signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
-    signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
 
--- Signale fuer Magnitude IP-Core
-    signal fft_mag_calc_valid : std_logic;	
-    signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
-
--- Signale fuer Ergebnis skaliert
-    signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);	
-    signal fft_float_scaled : signed( 31 downto 0 ); 
-	 
--- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
-	
-    signal data_memory : work.reg32.RegArray( 0 to 1023 );
-    signal index_reversed : std_logic_vector(9 downto 0);
-    signal index_output_sv : std_logic_vector(9 downto 0);
-    signal index_output : integer range 0 to 1023;
-
--- Signal um in den Write FIFO zu schreiben
-    signal wr_fifo : std_logic;	 
-	  
 begin
-    
-    -----------------------------------------------------------------------------------------------
-    -- Hier muss der Verilog FFT IP-Core instanziert werden
-    -----------------------------------------------------------------------------------------------
 
-    --u_fft : fftmain
-    --    port map (		      
-    --        clock => , -- system clock				
-    --        reset => , -- Active High Asynchronous Reset				    
-    --	    di_en => , -- Input Data Enable
-    --	    di_re => , -- Input Data (Real)
-    --      di_im => , -- Input Data (Imag)				
-    --      do_en => , -- Output Data Enable				
-    --	    do_re => , -- Output Data (Real)
-    --      do_im =>  -- Output Data (Imag)
-    --    ); 
-    
-    fft_output_valid <= '0';
-    data_out_re <= (others => '0');
-    data_out_im <= (others => '0');
+	--Port Zuweisung
+	c_float_fft: entity work.fft_magnitude_calc 
+	    PORT MAP (
+		clk    => clk,
+		reset  => reset,
+			  
+		input_valid => input_valid,		  
+		input_re => input_re, -- in Fixpoint
+		input_im => input_im, -- in Fixpoint
+		  
+		output_valid => output_valid,
+		output_magnitude => output_magnitude
+	    );
+	u_fft : fftmain
+		port map (
+		clock => clk,
+		reset => reset,
 
-    -----------------------------------------------------------------------------------------------
-    -- Hier muss der VHDL Magnitue IP-COre instanziert werden
-    -----------------------------------------------------------------------------------------------
-			 
-    -- u_fft_mag_calc : entity work.fft_magnitude_calc
-    -- port map (
-    --  clk => , -- system clock
-    --  reset => , -- Active High Asynchronous Reset	
-    --	input_valid => , -- Input Data Valid
-    --	input_re => ,  -- Input Realteil in Fixpoint format
-    --	input_im =>  , -- Input Imaginaerteil in Fixpoint format
-    --	output_valid => , -- Output Data Valid
-    --	output_magnitude =>  -- Magnitude Output in Fixpoint format
-    --  );
+		di_en => di_en,
+		di_re => di_re,
+		di_im => di_im,
 
-    fft_mag_calc_valid <= '1' when index = 0 else '0';
-    fft_mag_calc_result <= (others => '0');
+		do_en => do_en,
+		do_re => do_re,
+		do_im => do_im
+		);
+	
 
-    -----------------------------------------------------------------------------------------------
-    -- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
-    -----------------------------------------------------------------------------------------------
-    task_state_transitions : process (all) is
+
+
+
+    task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
         case current_task_state is
             when work.task.TASK_IDLE =>
                 if ( task_start = '1' ) then
-                    next_task_state <= work.task.TASK_RUNNING;
+                    next_task_state <= work.task.TASK_RUNNING;	
                 end if;
             when work.task.TASK_RUNNING =>
-                if (  index = 2 ) then
+                if ( index = (work.task.STREAM_LEN - 1) ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -174,157 +149,148 @@ begin
         end case;
     end process task_state_transitions;
 
-    -----------------------------------------------------------------------------------------------
-    -- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
-    -----------------------------------------------------------------------------------------------
+----------------------------------------------------------------------
+	--FFT Statemachine
+	fft_state_transitions : process ( all ) is
+	begin
+		next_fft_state <= current_fft_state;
+		case current_fft_state is
+			when FFTIdle =>
+				if ( current_task_state = work.task.TASK_RUNNING ) then -- Weiterschaltbedingung					
+					next_fft_state <= FFTRead;	
+				end if;
 
-    -- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
+			when FFTRead =>
+				if ( fft_index = work.task.STREAM_LEN ) then
+                 			next_fft_state <= FFTWait;
+                		end if;	
+ 				
+			when FFTWait =>
+				if ( do_en = '1') then
+					next_fft_state <= MAGRead;
+				end if;
+				
+			when MAGRead =>
+				if ( output_valid = '1' ) then	-- Weiterschaltbedingung
+					next_fft_state <= MAGStore;
+				end if;
+				
+			when MAGStore =>
+				if ( cnt = (work.task.STREAM_LEN - 1)) then
+					next_fft_state <= FFTIdle;
+				end if;
+			
+			
+		end case;
+	end process fft_state_transitions;
+----------------------------------------------------------------------
 
-
-    -----------------------------------------------------------------------------------------------
-    -- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
-    -----------------------------------------------------------------------------------------------
-   sync : process ( clk, reset ) is
+		
+    sync : process ( clk, reset ) is
+    variable fifo_in : signed(31 downto 0);
+    variable fifo_in2 : signed(31 downto 0);
+    variable mag_out : signed(31 downto 0);
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
             index <= 0;
-            wr_fifo <= '0';
+	    read_index <= 0;
+	    fft_index <= 0;
+	    cnt <= 0;
+	    signal_write <= '0';
+	    signal_read <= '0';
+	    input_valid <= '0';
+	    fifo_in := (others => '0');
+	    fifo_in2 := (others => '0');
+	    mag_out := (others => '0');
+	--    C <= (others => '0');
+	--    D <= (others => '0');
+	  --  E <= (others => '0');
+	    --F <= (others => '0');
+	    input_re <= (others => '0');
+	    input_im <= (others => '0');
+	    signal_writedata <= (others => '0');
+	    di_en <= '0';
+	    di_re <= (others => '0');
+            di_im <= (others => '0');
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
-            wr_fifo <= '0';
             case next_task_state is
-		    when work.task.TASK_IDLE => 
-                      index <= 0;
-		    when work.task.TASK_RUNNING =>
-                      -- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
-                      -- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
-		      if (  index_output = work.task.STREAM_LEN - 1 ) then
-		      	  index <= index + 1;	
-                      end if;
-                      if index = 1 then				 
-			  wr_fifo <= '1';
-		      end if; 
-		    when work.task.TASK_DONE => null;
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+               -- index <= index + 1;			--Index wird hier hochgezählt, muss in FFT State gemacht werden
+               -- signal_write <= '1';
+               -- signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
             end case;
+
+----------------------------------------------------------------------
+	--Output Statemachine
+
+	    current_fft_state <= next_fft_state;
+	    signal_write <= '0';
+	    signal_read <= '0';
+	    input_valid <= '0';
+	    di_en <= '0';
+	    case next_fft_state is
+		when FFTIdle =>
+		
+		when FFTRead =>
+			di_en <= '1';
+			signal_read <= '1';
+			--fifo_in <= signal_readdata(31 downto 0);
+			if(signal_readdata(30 downto 23) /= "00000000") then
+				fifo_in(31) := signal_readdata(31);
+				fifo_in(30 downto 23) := signed(signal_readdata(30 downto 23)) - 4;
+				fifo_in(22 downto 0) := signed(signal_readdata(22 downto 0));
+				--fifo_in2 := (fifo_in(31) & (signed(fifo_in(30 downto 23)) - 4) & (signed(fifo_in(22 downto 0))));
+			
+			end if;
+		
+			di_re <= to_fixed(std_logic_vector(fifo_in));
+			di_im <= (others => '0');
+			fft_index <= fft_index +1;
+		when FFTWait =>
+			fft_index <= 0;
+		when MAGRead =>
+			--D <= do_im(31) & ( unsigned(do_im(30 downto 23)) - B ) & unsigned(do_im(22 downto 0));
+			input_valid <= '1';
+			input_re <= do_re;
+			input_im <= do_im;
+			read_index <= read_index + 1;
+		when MAGStore =>
+			--read
+			if(read_index <= work.task.STREAM_LEN) then
+				--A <= do_re(31) & ( unsigned(do_re(30 downto 23)) - B ) & unsigned(do_re(22 downto 0));
+
+				--D <= do_im(31) & ( unsigned(do_im(30 downto 23)) - B ) & unsigned(do_im(22 downto 0));
+			
+				signal_read <= '1';
+				input_valid <= '1';
+				input_re <= do_re;
+				input_im <= do_im;
+				read_index <= read_index + 1;
+
+			end if;
+			--store
+			signal_write <= '1';
+			mag_out(31) := output_magnitude(31) ;
+			mag_out(30 downto 23) := signed(output_magnitude(30 downto 23)) + 4; 
+			mag_out(22 downto 0) := signed(output_magnitude(22 downto 0));
+			signal_writedata <= to_float(std_logic_vector(mag_out));
+			index <= index + 1;
+			cnt <= cnt + 1;
+	    end case;
+			
+
+----------------------------------------------------------------------
         end if;
-    end process sync; 
-	 
+    end process sync;
 
-    -----------------------------------------------------------------------------------------------
-    --
-    -- Skalierung der Eingangswerte welche vom FIFO gelesen werden
-    -- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
-    -- und im naechsten Takt schon weiter verarbeitet werden können
-    --
-    -- Erforderliches Scaling:
-    --
-    -- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
-    -- multiplication is a simple addition of the exponents.
-    -- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
-    -- This means an divsion through 16 -> exponent needs an addition of - 4
-    --
-    -- fft_float_input = gelesener Wert vom FIFO (floating point)
-    -- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
-    -- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
-    -----------------------------------------------------------------------------------------------
-
-    fft_float_input <= signed(signal_readdata);
-
-    fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden 
-				
-
-    -----------------------------------------------------------------------------------------------
-    --
-    -- Skalierung der Eingangswerte welche vom FIFO gelesen werden
-    -- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
-    -- und im naechsten Takt schon weiter verarbeitet werden können
-    --
-    -- Erforderliches Scaling:
-    --
-    -- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
-    -- multiplication is a simple addition of the exponents.
-    -- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16 
-    -- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
-    -- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
-    -- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
-    --
-    -- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
-    -- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
-    -----------------------------------------------------------------------------------------------
-
-    data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
-
-    fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
-
-
-    -----------------------------------------------------------------------------------------------
-    -- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
-	-- Umordnung der Ausgangswerte erfolgen
-	-- 
-	-- index_output_sv = std_logic_vector des Integer Ausgangsindex
-	-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
-	--
-    c_index_output_sv:
-            index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
-    c_reversed_index:
-            index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
-	
-	   
-    -----------------------------------------------------------------------------------------------
-    -- Prozess steuert das hochzaehlen des Ausgang Index
-    -----------------------------------------------------------------------------------------------
-	p_number_output_sample: process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            index_output <= 0; 
-        elsif ( rising_edge( clk ) ) then
-            -- Ruecksetz Bedingung für index_output
-            if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
-		index_output <= 0;
-            -- index_output hochzaehlen um in natural order im array zu speichern
-	    elsif fft_mag_calc_valid = '1' then
-		index_output <= index_output + 1;
-            -- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
-	    elsif wr_fifo = '1' then
-		index_output <= index_output + 1;
-	    end if;
-        end if;
-    end process p_number_output_sample;
-	
-    -----------------------------------------------------------------------------------------------
-    -- Prozess speichert das skalierte Endergbenis iun der natural order
-    -----------------------------------------------------------------------------------------------
-    p_output2float_memory: process ( clk, reset) is
-    begin
-        if ( reset = '1' ) then
-	    null;
-        elsif ( rising_edge( clk ) ) then
-            if fft_mag_calc_valid = '1' then
-	                data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
-            end if;
-        end if;
-    end process p_output2float_memory;	
-	
-    -----------------------------------------------------------------------------------------------
-    -- Schreiben der berechneten Werte in den FIFO
-    -----------------------------------------------------------------------------------------------
-   p_output_fifo: process ( clk, reset ) is
-    begin
-        if ( reset = '1' ) then
-            signal_writedata <= (others => '0');
-		  signal_write <= '0';
-        elsif ( rising_edge( clk ) ) then
-		  signal_write <= '0';		  
-            if wr_fifo = '1' then
-		  signal_writedata <= data_memory(index_output);
-	          signal_write <= '1';
-            end if;
-        end if;
-    end process p_output_fifo;	
-	
-	
-	-- Hier sollen die sonstigen benoetigten Anweisungen stehen
-    task_state <= current_task_state;	
+    task_state <= current_task_state;
 
 end architecture rtl;

software/signal_processing/fft.c

@@ -2,10 +2,19 @@
 #include "system/data_channel.h"
 #include "system/Complex.h"
 #include "system/float_word.h"
+#include <math.h>
+
+
+
 
 int task_fft_run( void * task ) {
-
-    // TODO
+	Complex Array[DATA_CHANNEL_DEPTH];
+	fft_config * fft = (fft_config *) task;
+	for(int a = 0; a<DATA_CHANNEL_DEPTH; a++)
+	{
+		data_channel_read(task->sources, Array.re[a]);
+		Array.im[a]=0; 
+	}
 
     return 0;
 }

tests/hardware/task_add_rand/transcript

@@ -0,0 +1,66 @@
+# vsim -voptargs="+acc" -c work.test_task_add_rand -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 08:42:56 on Dec 05,2023
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 1 FSM in architecture body "float_add(mixed)".
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.sine_cosine_data
+# Loading work.rand_data
+# Loading work.add_rand_data
+# Loading work.test_task_add_rand(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.float_add(mixed)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_rand
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 08:42:56 on Dec 05,2023, Elapsed time: 0:00:00
+# Errors: 0, Warnings: 1

tests/hardware/task_add_rand/work/@_opt/VH_HASH_DATA

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+2
+24 avalon_slave_transitions
+1
+84 /users/ads1/schmelzma80036/linux/signal_processing/tests/hardware/task_add_rand/work
+9
+6 struct
+6
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tests/hardware/task_add_rand/work/@_opt1/VH_HASH_DATA

@@ -0,0 +1,156 @@
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+8
+12 data_channel
+13
+8 GUI_MODE
+3
+3 rtl
+7
+5 DEPTH
+10
+18 test_task_add_rand
+2
+24 avalon_slave_transitions
+1
+84 /users/ads1/schmelzma80036/linux/signal_processing/tests/hardware/task_add_rand/work
+9
+6 struct
+6
+4 fifo
+4
+9 REG_COUNT
+5
+16 REG_ACCESS_TYPES
+11
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+]
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tests/hardware/task_add_rand/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

tests/hardware/task_add_sine_cosine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 08:40:25 on Dec 05,2023
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.sine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.cosine_data
+# Loading work.sine_cosine_data
+# Loading work.test_task_add_sine_cosine(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.float_add(mixed)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_sine_cosine
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 08:40:26 on Dec 05,2023, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 1