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2 Commits
Author | SHA1 | Date | |
---|---|---|---|
![]() |
c90753aa23 | ||
![]() |
5efb80253b |
@ -30,40 +30,7 @@ architecture rtl of add is
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--Initialisierung der weiteren Ablaufstruktur
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type AddState is (
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AddIdle,
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AddWait1,
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AddStart,
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AddAddition,
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AddStore
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);
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--Signale fuer die Zustandsmaschine
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signal current_add_state : AddState;
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signal next_add_state : AddState;
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signal A : std_logic_vector(31 downto 0);
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signal B : std_logic_vector(31 downto 0);
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signal start : std_logic;
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signal done : std_logic;
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signal sum : std_logic_vector ( 31 downto 0 );
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begin
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c_float_add : entity work.float_add
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PORT MAP (
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A => A,
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B => B,
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clk => clk,
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reset => reset,
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start => start,
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done => done,
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sum => sum
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);
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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@ -73,7 +40,7 @@ begin
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN) then
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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@ -83,43 +50,11 @@ begin
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end case;
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end process task_state_transitions;
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----------------------------------------------------------------------
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add_state_transitions : process ( all ) is
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begin
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next_add_state <= current_add_state;
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case current_add_state is
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when AddIdle =>
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if ( current_task_state = work.task.TASK_RUNNING ) then -- Weiterschaltbedingung
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next_add_state <= AddStart;
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end if;
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when AddStart =>
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next_add_state <= AddAddition;
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when AddAddition =>
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next_add_state <= AddWait1; -- Weiterschaltbedingung
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when AddWait1 =>
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if ( done = '1' ) then -- Weiterschaltbedingung
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next_add_state <= AddStore;
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end if;
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when AddStore =>
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next_add_state <= AddIdle; -- Weiterschaltbedingung
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end case;
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end process add_state_transitions;
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----------------------------------------------------------------------
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sync : process ( clk, reset ) is
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begin --INDEX WIRD NOCH JEDEN TAKT HOCHGEZÄHLT UND NICHT NUR WENN DAS ERGEBNIS GESPEICHERT WIRD
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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current_add_state <= AddIdle;
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index <= 0;
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start <= '0';
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A <= ( others => '0' );
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B <= ( others => '0' );
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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@ -127,45 +62,13 @@ begin
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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--index <= index + 1;
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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-------------------------------------------
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current_add_state <= next_add_state;
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signal_write <= '0';
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signal_a_read <= '0';
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signal_b_read <= '0';
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case next_add_state is
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when AddIdle =>
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signal_write <= '0';
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start <= '0';
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when AddStart =>
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--start <= '1';
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when AddAddition =>
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start <= '1';
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signal_a_read <= '1';
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signal_b_read <= '1';
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A <= signal_a_readdata;
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B <= signal_b_readdata;
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when AddWait1 =>
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signal_a_read <= '0';
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signal_b_read <= '0';
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when AddStore =>
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signal_write <= '1';
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signal_writedata <= sum;
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index <= index + 1;
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end case;
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-------------------------------------------
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end if;
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end process sync;
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@ -1,13 +1,26 @@
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------------------------------------------------------------------------
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-- fft
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--
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-- calculation of FFT magnitude
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-- calculation of FFT magnitudes
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--
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-- Inputs:
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-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
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--
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-- Outputs
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-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
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--
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--
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-- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor
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-- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist)
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-- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln
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-- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0)
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-- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich)
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-- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float)
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-- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32).
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-- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist)
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-- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html)
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-- (z.B: ein Array verwenden, um die Werte zu sortieren)
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-- Dann das Ergebnis in den Ausgangsfifo speichern
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--
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-----------------------------------------------------------------------
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library ieee;
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@ -22,10 +35,10 @@ library work;
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entity fft is
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generic (
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-- input data width of real/img part
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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@ -35,10 +48,10 @@ entity fft is
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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@ -46,100 +59,112 @@ end entity fft;
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architecture rtl of fft is
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-- Signale für Task State Machine
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--signal index : integer range 0 to 2000;
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-- component des Verilog IP-Cores fuer die FFT
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component fftmain is
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port(
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clock: in std_logic; -- Master Clock
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reset: in std_logic; -- Active High Asynchronous Reset
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di_en: in std_logic; -- Input Data Enable
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di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
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di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
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do_en: out std_logic; -- Output Data Enable
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do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
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do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
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port(
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clock: in std_logic; -- Master Clock
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reset: in std_logic; -- Active High Asynchronous Reset
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di_en: in std_logic; -- Input Data Enable
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di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
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di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
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do_en: out std_logic; -- Output Data Enable
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do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
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do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
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);
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end component;
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--Initialisierung der weiteren Ablaufstruktur
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type FFTState is (
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FFTIdle,
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FFTRead,
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FFTWait,
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MAGRead,
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MAGStore
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);
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--Signale fuer die Zustandsmaschine
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signal current_fft_state : FFTState;
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signal next_fft_state : FFTState;
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--signal fifo_in : unsigned(31 downto 0);
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constant B : signed(7 downto 0) := "00000100";
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--signal C : unsigned(31 downto 0);
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--signal D : unsigned(31 downto 0);
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--signal E : unsigned(31 downto 0);
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--signal F : unsigned(31 downto 0);
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signal read_index : integer range 0 to work.task.STREAM_LEN +100;
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signal fft_index : integer range 0 to work.task.STREAM_LEN;
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signal result : std_logic_vector ( 31 downto 0 );
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signal input_valid : std_logic;
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signal input_re : std_logic_vector( 31 downto 0 ); -- in Fixpoint
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signal input_im : std_logic_vector( 31 downto 0 ); -- in Fixpoint
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signal output_valid : std_logic;
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signal output_magnitude : std_logic_vector( 31 downto 0 );
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signal cnt : integer range 0 to work.task.STREAM_LEN;
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signal di_en : std_logic; -- Input Data Enable
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signal di_re : std_logic_vector(31 downto 0); -- Input Data (Real)
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signal di_im : std_logic_vector(31 downto 0); -- Input Data (Imag)
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signal do_en : std_logic; -- Output Data Enable
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signal do_re : std_logic_vector(31 downto 0); -- Output Data (Real)
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signal do_im : std_logic_vector(31 downto 0); -- Output Data (Imag)
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-- Signale Input skaliert
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signal fft_float_input : signed( 31 downto 0 );
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signal fft_float_scaled_input : signed( 31 downto 0 );
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-- Signale fuer FFT-IP Core
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-- fft data input signal
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signal fft_input_data_enable: std_logic;
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signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
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signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
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-- fft output data
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signal fft_output_valid : std_logic;
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signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
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signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
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begin
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-- Signale fuer Magnitude IP-Core
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signal fft_mag_calc_valid : std_logic;
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signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
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--Port Zuweisung
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c_float_fft: entity work.fft_magnitude_calc
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PORT MAP (
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clk => clk,
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reset => reset,
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input_valid => input_valid,
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input_re => input_re, -- in Fixpoint
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input_im => input_im, -- in Fixpoint
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output_valid => output_valid,
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output_magnitude => output_magnitude
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);
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u_fft : fftmain
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port map (
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clock => clk,
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reset => reset,
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di_en => di_en,
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di_re => di_re,
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di_im => di_im,
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do_en => do_en,
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do_re => do_re,
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do_im => do_im
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);
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-- Signale fuer Ergebnis skaliert
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signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);
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signal fft_float_scaled : signed( 31 downto 0 );
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-- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
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signal data_memory : work.reg32.RegArray( 0 to 1023 );
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signal index_reversed : std_logic_vector(9 downto 0);
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signal index_output_sv : std_logic_vector(9 downto 0);
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signal index_output : integer range 0 to 1023;
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-- Signal um in den Write FIFO zu schreiben
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signal wr_fifo : std_logic;
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begin
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-----------------------------------------------------------------------------------------------
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-- Hier muss der Verilog FFT IP-Core instanziert werden
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-----------------------------------------------------------------------------------------------
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--u_fft : fftmain
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-- port map (
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-- clock => , -- system clock
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-- reset => , -- Active High Asynchronous Reset
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-- di_en => , -- Input Data Enable
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-- di_re => , -- Input Data (Real)
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-- di_im => , -- Input Data (Imag)
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-- do_en => , -- Output Data Enable
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-- do_re => , -- Output Data (Real)
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-- do_im => -- Output Data (Imag)
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-- );
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fft_output_valid <= '0';
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data_out_re <= (others => '0');
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data_out_im <= (others => '0');
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-----------------------------------------------------------------------------------------------
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-- Hier muss der VHDL Magnitue IP-COre instanziert werden
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-----------------------------------------------------------------------------------------------
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-- u_fft_mag_calc : entity work.fft_magnitude_calc
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-- port map (
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-- clk => , -- system clock
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-- reset => , -- Active High Asynchronous Reset
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-- input_valid => , -- Input Data Valid
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-- input_re => , -- Input Realteil in Fixpoint format
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-- input_im => , -- Input Imaginaerteil in Fixpoint format
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-- output_valid => , -- Output Data Valid
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-- output_magnitude => -- Magnitude Output in Fixpoint format
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-- );
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task_state_transitions : process ( current_task_state, task_start, index ) is
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fft_mag_calc_valid <= '1' when index = 0 else '0';
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fft_mag_calc_result <= (others => '0');
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-----------------------------------------------------------------------------------------------
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-- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
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-----------------------------------------------------------------------------------------------
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task_state_transitions : process (all) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = (work.task.STREAM_LEN - 1) ) then
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if ( index = 2 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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@ -149,148 +174,157 @@ begin
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end case;
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end process task_state_transitions;
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----------------------------------------------------------------------
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--FFT Statemachine
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fft_state_transitions : process ( all ) is
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begin
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next_fft_state <= current_fft_state;
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case current_fft_state is
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when FFTIdle =>
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if ( current_task_state = work.task.TASK_RUNNING ) then -- Weiterschaltbedingung
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next_fft_state <= FFTRead;
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end if;
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-----------------------------------------------------------------------------------------------
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-- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
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-----------------------------------------------------------------------------------------------
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when FFTRead =>
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if ( fft_index = work.task.STREAM_LEN ) then
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next_fft_state <= FFTWait;
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end if;
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when FFTWait =>
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if ( do_en = '1') then
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next_fft_state <= MAGRead;
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end if;
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when MAGRead =>
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if ( output_valid = '1' ) then -- Weiterschaltbedingung
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next_fft_state <= MAGStore;
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end if;
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when MAGStore =>
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if ( cnt = (work.task.STREAM_LEN - 1)) then
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next_fft_state <= FFTIdle;
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end if;
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end case;
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end process fft_state_transitions;
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----------------------------------------------------------------------
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-- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
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sync : process ( clk, reset ) is
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variable fifo_in : signed(31 downto 0);
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variable fifo_in2 : signed(31 downto 0);
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variable mag_out : signed(31 downto 0);
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-----------------------------------------------------------------------------------------------
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-- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
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-----------------------------------------------------------------------------------------------
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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read_index <= 0;
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fft_index <= 0;
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cnt <= 0;
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signal_write <= '0';
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signal_read <= '0';
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input_valid <= '0';
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fifo_in := (others => '0');
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fifo_in2 := (others => '0');
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mag_out := (others => '0');
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-- C <= (others => '0');
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-- D <= (others => '0');
|
||||
-- E <= (others => '0');
|
||||
--F <= (others => '0');
|
||||
input_re <= (others => '0');
|
||||
input_im <= (others => '0');
|
||||
signal_writedata <= (others => '0');
|
||||
di_en <= '0';
|
||||
di_re <= (others => '0');
|
||||
di_im <= (others => '0');
|
||||
wr_fifo <= '0';
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
current_task_state <= next_task_state;
|
||||
wr_fifo <= '0';
|
||||
case next_task_state is
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
when work.task.TASK_RUNNING =>
|
||||
-- index <= index + 1; --Index wird hier hochgezählt, muss in FFT State gemacht werden
|
||||
-- signal_write <= '1';
|
||||
-- signal_writedata <= ( others => '0' );
|
||||
when work.task.TASK_DONE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
when work.task.TASK_RUNNING =>
|
||||
-- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
|
||||
-- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
|
||||
if ( index_output = work.task.STREAM_LEN - 1 ) then
|
||||
index <= index + 1;
|
||||
end if;
|
||||
if index = 1 then
|
||||
wr_fifo <= '1';
|
||||
end if;
|
||||
when work.task.TASK_DONE => null;
|
||||
end case;
|
||||
|
||||
----------------------------------------------------------------------
|
||||
--Output Statemachine
|
||||
|
||||
current_fft_state <= next_fft_state;
|
||||
signal_write <= '0';
|
||||
signal_read <= '0';
|
||||
input_valid <= '0';
|
||||
di_en <= '0';
|
||||
case next_fft_state is
|
||||
when FFTIdle =>
|
||||
|
||||
when FFTRead =>
|
||||
di_en <= '1';
|
||||
signal_read <= '1';
|
||||
--fifo_in <= signal_readdata(31 downto 0);
|
||||
if(signal_readdata(30 downto 23) /= "00000000") then
|
||||
fifo_in(31) := signal_readdata(31);
|
||||
fifo_in(30 downto 23) := signed(signal_readdata(30 downto 23)) - 4;
|
||||
fifo_in(22 downto 0) := signed(signal_readdata(22 downto 0));
|
||||
--fifo_in2 := (fifo_in(31) & (signed(fifo_in(30 downto 23)) - 4) & (signed(fifo_in(22 downto 0))));
|
||||
|
||||
end if;
|
||||
|
||||
di_re <= to_fixed(std_logic_vector(fifo_in));
|
||||
di_im <= (others => '0');
|
||||
fft_index <= fft_index +1;
|
||||
when FFTWait =>
|
||||
fft_index <= 0;
|
||||
when MAGRead =>
|
||||
--D <= do_im(31) & ( unsigned(do_im(30 downto 23)) - B ) & unsigned(do_im(22 downto 0));
|
||||
input_valid <= '1';
|
||||
input_re <= do_re;
|
||||
input_im <= do_im;
|
||||
read_index <= read_index + 1;
|
||||
when MAGStore =>
|
||||
--read
|
||||
if(read_index <= work.task.STREAM_LEN) then
|
||||
--A <= do_re(31) & ( unsigned(do_re(30 downto 23)) - B ) & unsigned(do_re(22 downto 0));
|
||||
|
||||
--D <= do_im(31) & ( unsigned(do_im(30 downto 23)) - B ) & unsigned(do_im(22 downto 0));
|
||||
|
||||
signal_read <= '1';
|
||||
input_valid <= '1';
|
||||
input_re <= do_re;
|
||||
input_im <= do_im;
|
||||
read_index <= read_index + 1;
|
||||
|
||||
end if;
|
||||
--store
|
||||
signal_write <= '1';
|
||||
mag_out(31) := output_magnitude(31) ;
|
||||
mag_out(30 downto 23) := signed(output_magnitude(30 downto 23)) + 4;
|
||||
mag_out(22 downto 0) := signed(output_magnitude(22 downto 0));
|
||||
signal_writedata <= to_float(std_logic_vector(mag_out));
|
||||
index <= index + 1;
|
||||
cnt <= cnt + 1;
|
||||
end case;
|
||||
|
||||
|
||||
----------------------------------------------------------------------
|
||||
end if;
|
||||
end process sync;
|
||||
end process sync;
|
||||
|
||||
|
||||
task_state <= current_task_state;
|
||||
-----------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
|
||||
-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
|
||||
-- und im naechsten Takt schon weiter verarbeitet werden können
|
||||
--
|
||||
-- Erforderliches Scaling:
|
||||
--
|
||||
-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
|
||||
-- multiplication is a simple addition of the exponents.
|
||||
-- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
|
||||
-- This means an divsion through 16 -> exponent needs an addition of - 4
|
||||
--
|
||||
-- fft_float_input = gelesener Wert vom FIFO (floating point)
|
||||
-- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
|
||||
-- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
fft_float_input <= signed(signal_readdata);
|
||||
|
||||
fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
--
|
||||
-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
|
||||
-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
|
||||
-- und im naechsten Takt schon weiter verarbeitet werden können
|
||||
--
|
||||
-- Erforderliches Scaling:
|
||||
--
|
||||
-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
|
||||
-- multiplication is a simple addition of the exponents.
|
||||
-- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16
|
||||
-- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
|
||||
-- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
|
||||
-- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
|
||||
--
|
||||
-- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
|
||||
-- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
|
||||
-----------------------------------------------------------------------------------------------
|
||||
|
||||
data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
|
||||
|
||||
fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
|
||||
-- Umordnung der Ausgangswerte erfolgen
|
||||
--
|
||||
-- index_output_sv = std_logic_vector des Integer Ausgangsindex
|
||||
-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
|
||||
--
|
||||
c_index_output_sv:
|
||||
index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
|
||||
c_reversed_index:
|
||||
index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Prozess steuert das hochzaehlen des Ausgang Index
|
||||
-----------------------------------------------------------------------------------------------
|
||||
p_number_output_sample: process ( clk, reset ) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
index_output <= 0;
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
-- Ruecksetz Bedingung für index_output
|
||||
if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
|
||||
index_output <= 0;
|
||||
-- index_output hochzaehlen um in natural order im array zu speichern
|
||||
elsif fft_mag_calc_valid = '1' then
|
||||
index_output <= index_output + 1;
|
||||
-- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
|
||||
elsif wr_fifo = '1' then
|
||||
index_output <= index_output + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process p_number_output_sample;
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Prozess speichert das skalierte Endergbenis iun der natural order
|
||||
-----------------------------------------------------------------------------------------------
|
||||
p_output2float_memory: process ( clk, reset) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
null;
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
if fft_mag_calc_valid = '1' then
|
||||
data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
|
||||
end if;
|
||||
end if;
|
||||
end process p_output2float_memory;
|
||||
|
||||
-----------------------------------------------------------------------------------------------
|
||||
-- Schreiben der berechneten Werte in den FIFO
|
||||
-----------------------------------------------------------------------------------------------
|
||||
p_output_fifo: process ( clk, reset ) is
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
signal_writedata <= (others => '0');
|
||||
signal_write <= '0';
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
signal_write <= '0';
|
||||
if wr_fifo = '1' then
|
||||
signal_writedata <= data_memory(index_output);
|
||||
signal_write <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process p_output_fifo;
|
||||
|
||||
|
||||
-- Hier sollen die sonstigen benoetigten Anweisungen stehen
|
||||
task_state <= current_task_state;
|
||||
|
||||
end architecture rtl;
|
||||
|
@ -2,19 +2,10 @@
|
||||
#include "system/data_channel.h"
|
||||
#include "system/Complex.h"
|
||||
#include "system/float_word.h"
|
||||
#include <math.h>
|
||||
|
||||
|
||||
|
||||
|
||||
int task_fft_run( void * task ) {
|
||||
Complex Array[DATA_CHANNEL_DEPTH];
|
||||
fft_config * fft = (fft_config *) task;
|
||||
for(int a = 0; a<DATA_CHANNEL_DEPTH; a++)
|
||||
{
|
||||
data_channel_read(task->sources, Array.re[a]);
|
||||
Array.im[a]=0;
|
||||
}
|
||||
|
||||
// TODO
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
@ -1,66 +0,0 @@
|
||||
# vsim -voptargs="+acc" -c work.test_task_add_rand -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false
|
||||
# Start time: 08:42:56 on Dec 05,2023
|
||||
# ** Note: (vsim-3812) Design is being optimized...
|
||||
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
|
||||
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "float_add(mixed)".
|
||||
# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
|
||||
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
|
||||
# // Questa Sim-64
|
||||
# // Version 2023.2 linux_x86_64 Apr 11 2023
|
||||
# //
|
||||
# // Copyright 1991-2023 Mentor Graphics Corporation
|
||||
# // All Rights Reserved.
|
||||
# //
|
||||
# // QuestaSim and its associated documentation contain trade
|
||||
# // secrets and commercial or financial information that are the property of
|
||||
# // Mentor Graphics Corporation and are privileged, confidential,
|
||||
# // and exempt from disclosure under the Freedom of Information Act,
|
||||
# // 5 U.S.C. Section 552. Furthermore, this information
|
||||
# // is prohibited from disclosure under the Trade Secrets Act,
|
||||
# // 18 U.S.C. Section 1905.
|
||||
# //
|
||||
# Loading std.standard
|
||||
# Loading std.textio(body)
|
||||
# Loading ieee.std_logic_1164(body)
|
||||
# Loading ieee.numeric_std(body)
|
||||
# Loading ieee.fixed_float_types
|
||||
# Loading ieee.math_real(body)
|
||||
# Loading ieee.fixed_generic_pkg(body)
|
||||
# Loading ieee.float_generic_pkg(body)
|
||||
# Loading ieee.fixed_pkg
|
||||
# Loading ieee.float_pkg
|
||||
# Loading work.reg32(body)
|
||||
# Loading work.avalon_slave
|
||||
# Loading work.test_utility(body)
|
||||
# Loading work.test_avalon_slave(body)
|
||||
# Loading work.task(body)
|
||||
# Loading work.test_hardware_task(body)
|
||||
# Loading work.test_data_channel_pkg(body)
|
||||
# Loading std.env(body)
|
||||
# Loading work.sine_cosine_data
|
||||
# Loading work.rand_data
|
||||
# Loading work.add_rand_data
|
||||
# Loading work.test_task_add_rand(test)#1
|
||||
# Loading work.task_add(struct)#1
|
||||
# Loading work.hardware_task_control(rtl)#1
|
||||
# Loading work.avalon_slave_transitions(rtl)#1
|
||||
# Loading work.add(rtl)#1
|
||||
# Loading work.float_add(mixed)#1
|
||||
# Loading work.data_channel(struct)#1
|
||||
# Loading work.data_channel_control(rtl)#1
|
||||
# Loading work.avalon_slave_transitions(rtl)#2
|
||||
# Loading work.data_sink_mux(rtl)#1
|
||||
# Loading work.fifo(rtl)#1
|
||||
# Loading work.data_source_mux(rtl)#1
|
||||
# set StdArithNoWarnings 1
|
||||
# 1
|
||||
# set NumericStdNoWarnings 1
|
||||
# 1
|
||||
# run -all
|
||||
# --------------------------------------------------------------------------------
|
||||
# Starting test_task_add_rand
|
||||
# test_configure ... [ OK ]
|
||||
# test_execute ... [ OK ]
|
||||
# write_content ... [ OK ]
|
||||
# End time: 08:42:56 on Dec 05,2023, Elapsed time: 0:00:00
|
||||
# Errors: 0, Warnings: 1
|
@ -1,156 +0,0 @@
|
||||
[N
|
||||
13
|
||||
12
|
||||
13 CHECK_RESULTS
|
||||
8
|
||||
12 data_channel
|
||||
13
|
||||
8 GUI_MODE
|
||||
3
|
||||
3 rtl
|
||||
7
|
||||
5 DEPTH
|
||||
10
|
||||
18 test_task_add_rand
|
||||
2
|
||||
24 avalon_slave_transitions
|
||||
1
|
||||
84 /users/ads1/schmelzma80036/linux/signal_processing/tests/hardware/task_add_rand/work
|
||||
9
|
||||
6 struct
|
||||
6
|
||||
4 fifo
|
||||
4
|
||||
9 REG_COUNT
|
||||
5
|
||||
16 REG_ACCESS_TYPES
|
||||
11
|
||||
4 test
|
||||
]
|
||||
[G
|
||||
1
|
||||
8
|
||||
9
|
||||
1
|
||||
7
|
||||
1
|
||||
0
|
||||
1024
|
||||
0
|
||||
0 0
|
||||
0
|
||||
0
|
||||
]
|
||||
[G
|
||||
1
|
||||
6
|
||||
3
|
||||
1
|
||||
7
|
||||
1
|
||||
0
|
||||
1024
|
||||
0
|
||||
0 0
|
||||
0
|
||||
0
|
||||
]
|
||||
[G
|
||||
1
|
||||
2
|
||||
3
|
||||
1
|
||||
4
|
||||
1
|
||||
0
|
||||
6
|
||||
0
|
||||
0 0
|
||||
0
|
||||
0
|
||||
]
|
||||
[G
|
||||
1
|
||||
2
|
||||
3
|
||||
2
|
||||
4
|
||||
1
|
||||
0
|
||||
7
|
||||
0
|
||||
0 0
|
||||
0
|
||||
0
|
||||
]
|
||||
[G
|
||||
1
|
||||
10
|
||||
11
|
||||
1
|
||||
13
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
0 0
|
||||
0
|
||||
0
|
||||
]
|
||||
[G
|
||||
1
|
||||
2
|
||||
3
|
||||
1
|
||||
5
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
6 0
|
||||
2
|
||||
1
|
||||
1
|
||||
3
|
||||
3
|
||||
3
|
||||
1
|
||||
1
|
||||
0 5 1 1
|
||||
]
|
||||
[G
|
||||
1
|
||||
2
|
||||
3
|
||||
2
|
||||
5
|
||||
0
|
||||
0
|
||||
0
|
||||
0
|
||||
7 0
|
||||
3
|
||||
1
|
||||
1
|
||||
1
|
||||
2
|
||||
1
|
||||
2
|
||||
1
|
||||
1
|
||||
0 6 1 1
|
||||
]
|
||||
[G
|
||||
1
|
||||
10
|
||||
11
|
||||
1
|
||||
12
|
||||
0
|
||||
0
|
||||
1
|
||||
0
|
||||
0 0
|
||||
0
|
||||
0
|
||||
]
|
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@ -1,156 +0,0 @@
|
||||
[N
|
||||
13
|
||||
12
|
||||
13 CHECK_RESULTS
|
||||
8
|
||||
12 data_channel
|
||||
13
|
||||
8 GUI_MODE
|
||||
3
|
||||
3 rtl
|
||||
7
|
||||
5 DEPTH
|
||||
10
|
||||
18 test_task_add_rand
|
||||
2
|
||||
24 avalon_slave_transitions
|
||||
1
|
||||
84 /users/ads1/schmelzma80036/linux/signal_processing/tests/hardware/task_add_rand/work
|
||||
9
|
||||
6 struct
|
||||
6
|
||||
4 fifo
|
||||
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|
||||
9 REG_COUNT
|
||||
5
|
||||
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|
||||
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|
||||
4 test
|
||||
]
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@ -1,4 +0,0 @@
|
||||
m255
|
||||
K4
|
||||
z0
|
||||
cModel Technology
|
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@ -1,65 +0,0 @@
|
||||
# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false
|
||||
# Start time: 08:40:25 on Dec 05,2023
|
||||
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
|
||||
# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
|
||||
# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
|
||||
# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
|
||||
# // Questa Sim-64
|
||||
# // Version 2023.2 linux_x86_64 Apr 11 2023
|
||||
# //
|
||||
# // Copyright 1991-2023 Mentor Graphics Corporation
|
||||
# // All Rights Reserved.
|
||||
# //
|
||||
# // QuestaSim and its associated documentation contain trade
|
||||
# // secrets and commercial or financial information that are the property of
|
||||
# // Mentor Graphics Corporation and are privileged, confidential,
|
||||
# // and exempt from disclosure under the Freedom of Information Act,
|
||||
# // 5 U.S.C. Section 552. Furthermore, this information
|
||||
# // is prohibited from disclosure under the Trade Secrets Act,
|
||||
# // 18 U.S.C. Section 1905.
|
||||
# //
|
||||
# Loading std.standard
|
||||
# Loading std.textio(body)
|
||||
# Loading ieee.std_logic_1164(body)
|
||||
# Loading ieee.numeric_std(body)
|
||||
# Loading ieee.fixed_float_types
|
||||
# Loading ieee.math_real(body)
|
||||
# Loading ieee.fixed_generic_pkg(body)
|
||||
# Loading ieee.float_generic_pkg(body)
|
||||
# Loading ieee.fixed_pkg
|
||||
# Loading ieee.float_pkg
|
||||
# Loading work.reg32(body)
|
||||
# Loading work.avalon_slave
|
||||
# Loading work.test_utility(body)
|
||||
# Loading work.test_avalon_slave(body)
|
||||
# Loading work.task(body)
|
||||
# Loading work.sine_data
|
||||
# Loading work.test_hardware_task(body)
|
||||
# Loading work.test_data_channel_pkg(body)
|
||||
# Loading std.env(body)
|
||||
# Loading work.cosine_data
|
||||
# Loading work.sine_cosine_data
|
||||
# Loading work.test_task_add_sine_cosine(test)#1
|
||||
# Loading work.task_add(struct)#1
|
||||
# Loading work.hardware_task_control(rtl)#1
|
||||
# Loading work.avalon_slave_transitions(rtl)#1
|
||||
# Loading work.add(rtl)#1
|
||||
# Loading work.float_add(mixed)#1
|
||||
# Loading work.data_channel(struct)#1
|
||||
# Loading work.data_channel_control(rtl)#1
|
||||
# Loading work.avalon_slave_transitions(rtl)#2
|
||||
# Loading work.data_sink_mux(rtl)#1
|
||||
# Loading work.fifo(rtl)#1
|
||||
# Loading work.data_source_mux(rtl)#1
|
||||
# set StdArithNoWarnings 1
|
||||
# 1
|
||||
# set NumericStdNoWarnings 1
|
||||
# 1
|
||||
# run -all
|
||||
# --------------------------------------------------------------------------------
|
||||
# Starting test_task_add_sine_cosine
|
||||
# test_configure ... [ OK ]
|
||||
# test_execute ... [ OK ]
|
||||
# write_content ... [ OK ]
|
||||
# End time: 08:40:26 on Dec 05,2023, Elapsed time: 0:00:01
|
||||
# Errors: 0, Warnings: 1
|
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Reference in New Issue
Block a user