116 lines
3.9 KiB
VHDL
116 lines
3.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity rand is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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seed : in work.reg32.word;
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity rand;
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architecture rtl of rand is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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-- Register für den LFSR Zustand
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signal lfsr_reg : std_logic_vector(31 downto 0);
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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variable v_feedback : std_logic;
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variable v_lfsr_next : std_logic_vector(31 downto 0);
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variable v_send_cycle : boolean := true; -- toggle um signal_write nur einen Takt auszugeben
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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lfsr_reg <= (others => '0');
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signal_write <= '0';
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signal_writedata <= (others => '0');
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v_send_cycle := true;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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lfsr_reg <= seed;
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v_send_cycle := true; -- Reset toggle für nächsten Start
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when work.task.TASK_RUNNING =>
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if v_send_cycle = true then
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index <= index + 1;
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-- 1. LFSR Feedback berechnen (Polynom x^31 + x^21 + x^1 + 1)
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v_feedback := lfsr_reg(31) xor lfsr_reg(21) xor lfsr_reg(1) xor lfsr_reg(0);
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-- 2. Schieben und neues Bit einfügen
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v_lfsr_next := lfsr_reg(30 downto 0) & v_feedback;
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-- Register aktualisieren für den nächsten Takt
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lfsr_reg <= v_lfsr_next;
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-- 3. Daten schreiben und Bit-Manipulation
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signal_write <= '1';
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-- Wir nutzen hier v_lfsr_next, damit der geschriebene Wert
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-- dem aktuellen Berechnungsschritt entspricht.
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if v_lfsr_next(30) = '1' then
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-- Fall A: Bit 30 ist 1. Bits 29-24 löschen
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-- Maske: AND mit 1100 0000 ... (0xC0...)
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signal_writedata <= v_lfsr_next and x"C0FFFFFF";
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else
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-- Fall B: Bit 30 ist 0. Bits 29-25 setzen
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-- Maske: OR mit 0011 1110 ... (0x3E...)
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signal_writedata <= v_lfsr_next or x"3E000000";
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end if;
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v_send_cycle := false;
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else
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signal_write <= '0';
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v_send_cycle := true;
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end if;
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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