130 lines
4.4 KiB
VHDL
130 lines
4.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity rand is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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seed : in work.reg32.word;
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end entity rand;
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architecture rtl of rand is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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signal f_start : std_logic := '0';
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signal f_done : std_logic := '0';
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signal f_A : std_logic_vector(31 downto 0) := (others => '0');
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signal f_B : std_logic_vector(31 downto 0) := (others => '0');
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signal f_sum : std_logic_vector(31 downto 0) := (others => '0');
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begin
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----------------------------------------------------------------------------------------------------------------------------------------------------------
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u_float_rand : entity work.float_rand --Zugriff auf die Float_ datei
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port map (
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clk => clk,
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reset => reset,
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start => f_start,
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done => f_done,
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A => f_A,
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B => f_B,
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sum => f_sum
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);
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--------------------------------------------------------------------------------------------------------------------------
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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-----------------------------------------------------------------------------------------------------------------------------------------------------
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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f_start <= '0';
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signal_a_read <= '0';
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signal_b_read <= '0';
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signal_write <= '0';
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f_A <= (others => '0');
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f_B <= (others => '0');
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_a_read <= '0';
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signal_b_read <= '0';
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f_start <= '0';
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signal_write <= '0';
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signal_writedata <= (others => '0');
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when work.task.TASK_RUNNING =>
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if f_start = '0' and f_done = '0' then
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--FIFO lesen
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signal_a_read <= '1';
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signal_b_read <= '1';
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f_A <= signal_a_readdata;
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f_B <= signal_b_readdata;
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f_start <= '1';
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signal_write <= '0';
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elsif f_start = '1' and f_done = '0' then
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--Startet nur einen tAKT
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signal_a_read <= '0';
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signal_b_read <= '0';
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elsif f_start ='1' and f_done = '1' then
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--Ergebnisse speiecern
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f_start <= '0';
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signal_write <= '1';
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signal_writedata <= f_sum;
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--signal_write <= '0';
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--signal_writedata <= ( others => '0' );
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--Index erhöhen
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--if index < work.task.STREAM_LEN -1 then
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index <= index + 1;
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--end if;
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else signal_write <= '0';
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end if;
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--index <= index + 1;
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-- signal_write <= '1';
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-- signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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