dippoldha78415 357ceef29b add.vhd and crc.vhd working and finished, results true

2023-12-19 20:26:22 +01:00

hardware

add.vhd and crc.vhd working and finished, results true

2023-12-19 20:26:22 +01:00

software/signal_processing

Initial commit

2023-10-31 07:47:27 +01:00

tests

Initial commit

2023-10-31 07:47:27 +01:00

.gitignore

Initial commit

2023-10-31 07:47:27 +01:00

data_channel_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_task_hw.tcl

Initial commit

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hardware_timestamp_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hdl_sources.qsf

Initial commit

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init.sh

Initial commit

2023-10-31 07:47:27 +01:00

Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

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signal_processing.qpf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

S

Description

Studentenversion des ESY6/A Praktikums "signal_processing".

19 MiB

Languages

VHDL 37.3%

C 17.2%

Verilog 15%

Python 10.7%

Makefile 8.2%

Other 11.6%