121 lines
4.4 KiB
VHDL
121 lines
4.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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entity crc is
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port (
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clk : in std_logic;
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reset : in std_logic;
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector(31 downto 0);
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signal_write : out std_logic;
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signal_writedata: out std_logic_vector(31 downto 0)
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);
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end entity crc;
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architecture rtl of crc is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN := 0;
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constant CRC_INIT : std_logic_vector(31 downto 0) := X"FFFFFFFF";
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constant CRC_POLY : std_logic_vector(31 downto 0) := X"EDB88320";
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signal crc : std_logic_vector(31 downto 0) := CRC_INIT;
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signal data_reg : std_logic_vector(31 downto 0);
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signal data_valid : std_logic := '0';
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begin
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task_state <= current_task_state;
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-- TASK STATE MACHINE (VORLAGE - nicht ändern!)
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task_state_transitions: process(current_task_state, task_start, index)
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if task_start = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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-- WICHTIG: Schreiben nach 1024 Werten (index 0-1023)
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if index = 1023 then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if task_start = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process;
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-- Data Channel Control
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signal_read <= '1' when current_task_state = work.task.TASK_RUNNING
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and data_valid = '0'
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and index < 1024
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else '0';
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signal_write <= '1' when current_task_state = work.task.TASK_DONE else '0';
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signal_writedata <= crc xor X"FFFFFFFF"; -- Final XOR
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-- Haupt-Sync Process (identisch zur SW-Version)
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sync: process(clk, reset)
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variable temp_crc : std_logic_vector(31 downto 0);
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begin
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if reset = '1' then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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crc <= CRC_INIT;
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data_reg <= (others => '0');
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data_valid <= '0';
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elsif rising_edge(clk) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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crc <= CRC_INIT;
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data_valid <= '0';
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when work.task.TASK_RUNNING =>
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-- 1. DATA LESEN (Timing: signal_read='1' -> NEXT CLK data_valid)
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if signal_read = '1' then
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data_reg <= signal_readdata;
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data_valid <= '1';
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end if;
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-- 2. CRC UPDATE (zlib: XOR dann 32x bitweise LSB-first)
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if data_valid = '1' then
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temp_crc := crc xor data_reg;
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crc <= temp_crc;
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-- 32 Bit LSB-first Verarbeitung in EINEM Takt (wie SW)
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for i in 0 to 31 loop
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if temp_crc(0) = '1' then
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temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1)) xor CRC_POLY;
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else
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temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1));
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end if;
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end loop;
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crc <= temp_crc;
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data_valid <= '0';
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index <= index + 1;
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end if;
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when work.task.TASK_DONE =>
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index <= 0;
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data_valid <= '0';
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end case;
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end if;
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end process;
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end architecture rtl;
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