badenbergra78621 69302fa649 crc.c Korrekturen

2023-12-02 23:50:26 +01:00

hardware

Initial commit

2023-10-31 07:47:27 +01:00

software/signal_processing

crc.c Korrekturen

2023-12-02 23:50:26 +01:00

tests

Initial commit

2023-10-31 07:47:27 +01:00

.gitignore

Initial commit

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data_channel_hw.tcl

Initial commit

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hardware_task_hw.tcl

Initial commit

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hardware_timestamp_hw.tcl

Initial commit

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hdl_sources.qsf

Initial commit

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init.sh

Initial commit

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Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

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signal_processing.qpf

Initial commit

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signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

S

Description

Studentenversion des ESY6/A Praktikums "signal_processing".

19 MiB

Languages

VHDL 37.3%

C 17.2%

Verilog 15%

Python 10.7%

Makefile 8.2%

Other 11.6%