165 lines
4.0 KiB
VHDL
165 lines
4.0 KiB
VHDL
------------------------------------------------------------------------
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-- fft
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--
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-- calculation of FFT magnitude
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--
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-- Inputs:
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-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
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--
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-- Outputs
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-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
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--
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-----------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.reg32.all;
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use work.task.all;
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use work.float.all;
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architecture rtl of fft is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--own signals:
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--signal input_re : float(31 downto 0);
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--use xxx.lib?; --componenteninstanziierung FFT IP-Core r22sdf
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--component foo is
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--generic (...)
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--port(...);
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--end component;
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component fftmain is
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generic (
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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di_en : in std_logic;
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di_re : in std_logic_vector(input_data_width-1 downto 0);
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di_im : in std_logic_vector(input_data_width-1 downto 0);
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do_en : in std_logic;
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do_re : in std_logic_vector(input_data_width-1 downto 0);
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do_im : in std_logic_vector(input_data_width-1 downto 0)
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--task_start : in std_logic;
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--task_state : out work.task.State;
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--signal_read : out std_logic;
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--signal_readdata : in std_logic_vector( 31 downto 0 );
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--signal_write : out std_logic;
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--signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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end component fftmain;
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---State machine ----------------------------------
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TYPE State_type IS (A, B, C, D); -- Define the states
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SIGNAL State : State_Type; -- Create a signal that uses
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-- the different states
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begin
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u_fft : fftmain
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port map (
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clock => clk,
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reset => fft_reset,
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di_en => fft_input_data_enable,
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di_re => diata_in_re,
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di_im => data_in_im,
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do_en => fft_output_valid,
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do_re => data_out_re,
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do_im => data_out_im
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);
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u_fft_mag_calc : entity work.fft_magnitude_calc
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port map (
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clk => clk,
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reset => reset,
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input_valid => fft_output_valid,
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input_re => data_out_re,
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input_im => data_out_im,
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output_valid => fft_mag_calc_valid,
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output_magnitude => fft_mag_calc_result
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);
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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