signal_processing_vorlage/hardware/signal_processing/sine.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.float.all;
    use work.task.all;

entity sine is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        step_size : in work.reg32.word;
        phase : in work.reg32.word;
        amplitude : in work.reg32.word;

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity sine;

architecture rtl of sine is

    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

	signal valid_gen : std_logic;
    signal angle_gen : signed(31 downto 0);
	signal busy_gen : std_logic;
	signal result_valid_gen : std_logic;
	signal sine_gen : signed(31 downto 0);

	signal sine_sign      : std_logic;       					-- Vorzeichen
	signal sine_exponent  : signed(7 downto 0);  				-- Exponent
	signal sine_mantissa  : std_logic_vector(22 downto 0); 		-- Mantisse
	signal scaled_exponent    : signed(7 downto 0); 			-- Skalierter Exponent
	signal scaled_sine        : std_logic_vector(31 downto 0); 	-- Ergebnis
	

	type CalcState is (
		CALC_IDLE,
		CALC_GEN,
		CALC_WAIT,
		CALC_STORE,
		CALC_STORE_RESULT
	);
	
	signal current_calc_state : CalcState;
	signal next_calc_state : CalcState;

begin


	u_float_sine : entity work.float_sine
		generic map (
			ITERATIONS => 8
		)
		port map (
			clk => clk,
			reset => reset,
			data_valid => valid_gen,
			angle => angle_gen,
			busy => busy_gen,
			result_valid => result_valid_gen,
			sine => sine_gen
		);


    task_state_transitions : process ( all ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;


	calc_state_transistions : process ( all ) is
	begin
		next_calc_state <= current_calc_state;
		case current_calc_state is
			when CALC_IDLE =>
				if current_task_state = work.task.TASK_RUNNING then
					next_calc_state <= CALC_GEN;
				end if;
			when CALC_GEN =>
				next_calc_state <= CALC_WAIT;
			when CALC_WAIT => 
				next_calc_state <= CALC_STORE;
			when CALC_STORE =>
				if result_valid_gen = '1' and busy_gen = '0' then
					next_calc_state <= CALC_STORE_RESULT;
				else
					next_calc_state <= CALC_STORE;
				end if;
			when CALC_STORE_RESULT => 
				next_calc_state <= CALC_IDLE;
		end case;
	end process calc_state_transistions;



    sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
			index <= 0;

        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
			if current_task_state = work.task.TASK_RUNNING then
			end if;

			if current_calc_state = CALC_STORE_RESULT then
				index <= index + 1;

			end if;
        end if;
    end process sync;

	
	sine_sign     <= sine_gen(31);
	sine_exponent <= signed(sine_gen(30 downto 23));
	sine_mantissa <= std_logic_vector(sine_gen(22 downto 0));

	scaled_exponent <= sine_exponent + (signed(amplitude(30 downto 23)) - 127);			    
	scaled_sine <= sine_sign & std_logic_vector(scaled_exponent) & sine_mantissa;


	calc_sync : process ( clk, reset ) is
    begin
        if (reset = '1') then
            current_calc_state <= CALC_IDLE;
			valid_gen <= '0';
			angle_gen <= (others => '0');

			signal_write <= '0';
			signal_writedata <= (others => '0');

        elsif (rising_edge(clk)) then
            current_calc_state <= next_calc_state;
            signal_write <= '0';
			case current_calc_state is
                when CALC_IDLE =>
					valid_gen <= '0';
                    if current_task_state = work.task.TASK_IDLE then
						angle_gen <= signed(phase);
					end if;
				when CALC_GEN =>
					if next_calc_state = CALC_WAIT then
                    	valid_gen <= '1';	

						angle_gen <= angle_gen + signed(step_size);
					end if;
				when CALC_WAIT => 
					valid_gen <= '0';
				when CALC_STORE =>
                     null;            
				when CALC_STORE_RESULT =>
					signal_write <= '1';
					signal_writedata <= scaled_sine;			

            end case;
        end if;
    end process calc_sync;

    task_state <= current_task_state;

end architecture rtl;