Adds checks to tests
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11
.gitignore
vendored
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11
.gitignore
vendored
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@ -0,0 +1,11 @@
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U1_Datentypen/.libwork
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U1_Datentypen/modelsim.ini
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U1_Datentypen/transcript
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U1_Datentypen/vish_stacktrace.vstf
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U1_Datentypen/vsim.wlf
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U1_Datentypen/work/
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U2_Entity_Component/.libwork
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U2_Entity_Component/modelsim.ini
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U2_Entity_Component/transcript
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U2_Entity_Component/vsim.wlf
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U2_Entity_Component/work/
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@ -1,6 +1,7 @@
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vhdl_srcs = DataTypesExample.vhd \
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vhdl_srcs = DataTypesExample.vhd \
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test_DataTypesExample.vhd \
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../scripts/test_utility.vhd \
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test_DataTypesExample.vhd \
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main = test_DataTypesExample
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main = test_DataTypesExample
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@ -4,8 +4,11 @@ library ieee;
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library std;
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library std;
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use std.env.all;
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use std.env.all;
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library work;
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use work.test_utility.all;
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entity test_DataTypesExample is
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entity test_DataTypesExample is
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generic( CHECK_RESULTS : boolean );
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generic( GUI_MODE : boolean; CHECK_RESULTS : boolean );
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end entity test_DataTypesExample;
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end entity test_DataTypesExample;
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architecture test of test_DataTypesExample is
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architecture test of test_DataTypesExample is
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@ -27,7 +30,15 @@ begin
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delay : process
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delay : process
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begin
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begin
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wait for 100 ns;
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wait for 100 ns;
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stop;
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assert_eq( output_slv_calc, x"52" );
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assert_eq( output_slv_mask, x"5a" );
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assert_eq( output_slv_set, x"7a" );
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if ( GUI_MODE ) then
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std.env.stop;
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else
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std.env.finish;
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end if;
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end process delay;
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end process delay;
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end architecture test;
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end architecture test;
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@ -1,5 +1,6 @@
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vhdl_srcs = down_counter_int.vhd \
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vhdl_srcs = down_counter_int.vhd \
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../scripts/test_utility.vhd \
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top_entity.vhd \
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top_entity.vhd \
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test_top_entity.vhd \
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test_top_entity.vhd \
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@ -4,8 +4,11 @@ library ieee;
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library std;
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library std;
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use std.env.all;
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use std.env.all;
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library work;
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use work.test_utility.all;
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entity test_top_entity is
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entity test_top_entity is
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generic( CHECK_RESULTS : boolean );
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generic( GUI_MODE : boolean; CHECK_RESULTS : boolean );
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end entity test_top_entity;
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end entity test_top_entity;
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architecture test of test_top_entity is
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architecture test of test_top_entity is
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@ -31,12 +34,19 @@ begin
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p_run : process
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p_run : process
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begin
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begin
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wait until falling_edge( RESET );
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wait until falling_edge( RESET );
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for i in 0 to 128 loop
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for i in 0 to 128 loop
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wait until rising_edge( CLK );
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wait until rising_edge( CLK );
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end loop;
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end loop;
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wait until rising_edge( CLK );
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wait until rising_edge( CLK );
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stop;
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assert_eq( CNT, "0111000" );
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if ( GUI_MODE ) then
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std.env.stop;
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else
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std.env.finish;
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end if;
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end process p_run;
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end process p_run;
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end architecture test;
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end architecture test;
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11
U3_Anweisungen/Makefile
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11
U3_Anweisungen/Makefile
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vhdl_srcs = down_counter_int.vhd \
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top_entity.vhd \
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test_top_entity.vhd \
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main = test_top_entity
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CHECK_RESULTS = true
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include ../scripts/vhdl.mk
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125
U3_Anweisungen/alu.vhd
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125
U3_Anweisungen/alu.vhd
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-- Importiere die notwendigen Bibliotheken
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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-- Definiere eine ALU-Entity mit zwei Operanden, einem Opcode und einem Ergebnisausgang
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entity SimpleALU is
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Port (
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clk : in STD_LOGIC; -- Takt
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reset : in STD_LOGIC; -- Reset
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operand_a : in STD_LOGIC_VECTOR(3 downto 0); -- Erster Operand
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operand_b : in STD_LOGIC_VECTOR(3 downto 0); -- Zweiter Operand
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opcode : in STD_LOGIC_VECTOR(1 downto 0); -- Opcode, der die Operation bestimmt
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result_out : out STD_LOGIC_VECTOR(3 downto 0); -- Ergebnis der Operation
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flag_zero_out : out STD_LOGIC; -- Flag, das anzeigt, ob das Ergebnis null ist
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flag_or_out : out STD_LOGIC -- Flag, das anzeigt, ob eine Oder Operation bei den Operanden stattgefunden hat
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);
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end SimpleALU;
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-- Architekturdefinition der ALU
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architecture Behavioral of SimpleALU is
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-- Legen Sie das Signal STD_LOGIC_VECTOR reg_a an, in diesem soll spaeter der Eingang operand_a gespeichert werden
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signal reg_a : STD_LOGIC_VECTOR(3 downto 0);
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-- Legen Sie das Signal STD_LOGIC_VECTOR reg_b an, in diesem soll spaeter der Eingang operand_b gespeichert werden
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signal reg_b : STD_LOGIC_VECTOR(3 downto 0);
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-- Legen Sie das Signal STD_LOGIC_VECTOR reg_opcode an, in diesem soll spaeter der Eingang opcode gespeichert werden
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signal reg_opcode : STD_LOGIC_VECTOR(1 downto 0);
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-- Legen Sie ein Signal flag_zero als STD_LOGIC an
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signal flag_zero : STD_LOGIC;
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-- Legen Sie ein Signal result als STD_LOGIC_VECTOR der Laenge 4 an
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signal result : STD_LOGIC_VECTOR(3 downto 0);
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-- Legen Sie ein Signal reg_flag_zero als STD_LOGIC
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signal reg_flag_zero : STD_LOGIC;
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-- Legen Sie ein Signal reg_result als STD_LOGIC_VECTOR der Laenge von result an
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signal reg_result : STD_LOGIC_VECTOR(3 downto 0);
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begin
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-- Prozess fuer die Eingangsregister reg_a, reg_b, reg_c
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-- Bei einem Reset sollen die Register den Wert 0 haben
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-- Ansonsten soll bei einer steigenden Flanke von clk der entsprechnde Eingang (entity) gespeichert werden
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input_register : process(reset,clk)
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begin
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if reset = '1' then
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reg_a <= (others => '0');
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reg_b <= (others => '0');
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reg_opcode <= (others => '0');
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elsif rising_edge(clk) then
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reg_a <= operand_a;
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reg_b <= operand_b;
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reg_opcode <= opcode;
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end if;
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end process input_register;
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-- Prozess, der die ALU-Operationen durchfuehrt
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alu_process: process(all)
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begin
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-- Anweisung fuer die Initialisierung fuer flag_zero mit dem Wert 0
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flag_zero <= '0';
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-- Entscheide basierend auf dem Opcode, welche Operation durchgefuehrt wird
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-- Wenn reg_opcode:
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-- 00 -> result = reg_a + reg_b
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-- 01 -> result = reg_a - reg_b
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-- 10 -> result = reg_a and reg_b
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-- 11 -> result = reg_a or reg_b
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-- Fuer diese Realisierung soll die case-Anweisung verwendet werden
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-- Anm. Bei Berechnungen Datentypen beachten (std_logic_vector kann nicht direkt verwendet werden sondern es muss erst gecastet werden - signed verwenden)
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case reg_opcode is
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when "00" => -- Im Fall von "00" fuehre eine Addition durch
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result <= std_logic_vector(signed(reg_a) + signed(reg_b));
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when "01" => -- Im Fall von "01" fuehre eine Subtraktion durch
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result <= std_logic_vector(signed(reg_a) - signed(reg_b));
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when "10" => -- Im Fall von "10" fuehre eine bitweise AND-Operation durch
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result <= reg_a and reg_b;
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when "11" => -- Im Fall von "11" fuehre eine bitweise OR-Operation durch
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result <= reg_a or reg_b;
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when others => -- In allen anderen Faellen setze ein undefiniertes Verhalten
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result <= (others => 'X');
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end case;
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-- ueberpruefe, ob das Ergebnis result null ist, und setze das flag_zero entsprechend (result = 0 dann 1 ansonsten 0)
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-- Fuer diese Realisierung soll die if-Anweisung verwendet werden
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if result = "0000" then
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flag_zero <= '1';
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end if;
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end process alu_process;
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-- Prozess fuer die Ausgangssregister reg_result, reg_flag_zero
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-- Bei einem Reset sollen die Register den Wert 0 haben
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-- Ansonsten soll bei einer steigenden Flanke von clk das entsprechnde Signal aus dem alu_process zugewiesen werden
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output_register : process(reset,clk)
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begin
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if reset = '1' then
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reg_result <= (others => '0');
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reg_flag_zero <= '0';
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elsif rising_edge(clk) then
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reg_result <= result;
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reg_flag_zero <= flag_zero;
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end if;
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end process output_register;
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-- Anweisung um das Signal reg_result dem Ausgang result_out zu zuweisen
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result_out <= reg_result;
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-- Anweisung um das Signal reg_flag_zero dem Ausgang flag_zero_out zu zuweisen
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flag_zero_out <= reg_flag_zero;
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-- Bedingte Signalzuweisung fuer 'flag_or_out' außerhalb des Prozesses
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-- Es soll anhand des Entity Eingang opcode mit einer With .. Select Anweisung der Ausgang flag_or_out gesetzt werden
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-- opcode von or Operation dann 1 ansonsten 0
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with opcode select
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flag_or_out <= '1' when "11", -- Setze 'flag_or_out' auf '1', wenn 'opcode' "11" ist
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'0' when others; -- Ansonsten 0
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end Behavioral;
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42
U3_Anweisungen/test_alu.vhd
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42
U3_Anweisungen/test_alu.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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library std;
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use std.env.all;
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entity test_top_entity is
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generic( CHECK_RESULTS : boolean );
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end entity test_top_entity;
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architecture test of test_top_entity is
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '1';
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signal CNT : std_logic_vector(6 downto 0);
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begin
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u_top_entity : entity work.top_entity
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port map (
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CLK => CLK,
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RESET => RESET,
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CNT => CNT
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);
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CLK <= not CLK after 10 ns;
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p_reset : process( CLK )
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begin
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if falling_edge( CLK ) then
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RESET <= '0';
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end if;
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end process p_reset;
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p_run : process
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begin
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wait until falling_edge( RESET );
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for i in 0 to 128 loop
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wait until rising_edge( CLK );
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end loop;
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wait until rising_edge( CLK );
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stop;
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end process p_run;
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end architecture test;
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2
U3_Anweisungen/test_top_entity.wave
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2
U3_Anweisungen/test_top_entity.wave
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$ version 1.1
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/test_DataTypesExample/u_DataTypesExample/*
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3
U3_Anweisungen/vsim.wave
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3
U3_Anweisungen/vsim.wave
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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /test_top_entity/u_top_entity/*
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@ -23,11 +23,13 @@ assert_level := error
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gui: ${verilog_objs} ${vhdl_objs}
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gui: ${verilog_objs} ${vhdl_objs}
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@vsim \
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@vsim \
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-gGUI_MODE=true \
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-gCHECK_RESULTS=$(CHECK_RESULTS) \
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-gCHECK_RESULTS=$(CHECK_RESULTS) \
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-voptargs=+acc work.${main} -do "do vsim.wave; run -all"
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-voptargs=+acc work.${main} -do "do vsim.wave; run -all"
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sim: ${verilog_objs} ${vhdl_objs}
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sim: ${verilog_objs} ${vhdl_objs}
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@vsim \
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@vsim \
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-gGUI_MODE=false \
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-gCHECK_RESULTS=$(CHECK_RESULTS) \
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-gCHECK_RESULTS=$(CHECK_RESULTS) \
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-voptargs=+acc -c work.${main} -do "run -all" \
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-voptargs=+acc -c work.${main} -do "run -all" \
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| ../scripts/highlight_test_results.sh
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| ../scripts/highlight_test_results.sh
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71
scripts/test_utility.vhd
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71
scripts/test_utility.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.float_pkg.all;
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library std;
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use std.textio.all;
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package test_utility is
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constant TEST_FAIL : string := "[ FAIL ]";
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constant TEST_OK : string := "[ OK ]" & LF;
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type real_array is array ( natural range <> ) of real;
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procedure assert_eq( a : in std_logic_vector; b : in std_logic_vector );
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procedure assert_near( variable a : in real;
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variable b : in real;
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variable abs_err : in real );
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procedure assert_element_near( variable a : in real;
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variable b : in real;
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variable abs_err : in real;
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variable index : in integer );
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end package test_utility;
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package body test_utility is
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procedure assert_eq( a : in std_logic_vector; b : in std_logic_vector ) is
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begin
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assert( a = b )
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report TEST_FAIL & "assert_eq" & LF &
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" a: " & to_string( a ) & LF &
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" b: " & to_string( b ) & LF
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severity error;
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end procedure assert_eq;
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procedure assert_near( variable a : in real;
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variable b : in real;
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variable abs_err : in real ) is
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variable abs_diff : real;
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begin
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abs_diff := abs( a - b );
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assert( abs_diff <= abs_err )
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report TEST_FAIL & "assert_near" & LF &
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" a: " & to_string( a ) & LF &
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" b: " & to_string( b ) & LF &
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" " & to_string( abs_diff ) & " > " & to_string( abs_err ) & LF
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severity error;
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end procedure assert_near;
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procedure assert_element_near( variable a : in real;
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variable b : in real;
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variable abs_err : in real;
|
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|
variable index : in integer ) is
|
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|
variable abs_diff : real;
|
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|
begin
|
||||||
|
abs_diff := abs( a - b );
|
||||||
|
assert( abs_diff <= abs_err )
|
||||||
|
report TEST_FAIL & "assert_element_near" & LF &
|
||||||
|
" element: " & integer'image( index ) & LF &
|
||||||
|
" a: " & to_string( a ) & LF &
|
||||||
|
" b: " & to_string( b ) & LF &
|
||||||
|
" " & to_string( abs_diff ) & " > " & to_string( abs_err ) & LF
|
||||||
|
severity error;
|
||||||
|
end procedure assert_element_near;
|
||||||
|
|
||||||
|
end package body test_utility;
|
||||||
|
|
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Reference in New Issue
Block a user