Initial commit

.gitignore

+.qsys_edit/
+c5_pin_model_dump.txt
+db/
+incremental_db/
+*.bak
+niosII.sopcinfo
+niosII/
+output_files/
+__pycache__/
+*.pyc
+.assembler
+.fitter
+.map
+.sta
+*.log
+*.o
+*.oo
+*.swp
+*.elf
+

Makefile

+# Check for the required nios2-download command
+# The command is only available in nios2_command_shell
+ifeq (, $(shell which nios2-download))
+$(error "This makefile must be executed within the nios2_command_shell")
+endif
+
+uname = $(shell uname -r)
+ifneq (,$(findstring Microsoft,${uname}))
+exe_suffix=.exe
+endif
+
+# Programm pathes
+quartus_root ?= ${QUARTUS_ROOTDIR}
+intel_root ?= $(quartus_root)/..
+sopc_root = $(quartus_root)/sopc_builder
+
+# Tools
+qsys_generate = $(sopc_root)/bin/qsys-generate$(exe_suffix)
+niosii_bsp = $(intel_root)/nios2eds/sdk2/bin/nios2-bsp
+quartus_map = quartus_map$(exe_suffix)
+quartus_fit = quartus_fit$(exe_suffix)
+quartus_asm = quartus_asm$(exe_suffix)
+quartus_sta = quartus_sta$(exe_suffix)
+nios2_bsp_generate_files = nios2-bsp-generate-files$(exe_suffix)
+quartus_pgm = quartus_pgm$(exe_suffix)
+nios2_download = nios2-download$(exe_suffix)
+nios2_terminal = nios2-terminal$(exe_suffix)
+
+# Directories
+niosii_dir = niosII
+bsp_dir = software/signal_processing_bsp
+app_dir = software/signal_processing
+hw_test_dir = tests/hardware
+sw_test_dir = tests/software
+
+# Settings
+quartus_project = signal_processing
+signal_processing_qsf = signal_processing.qsf
+
+# Sources
+niosii_qsys = niosII.qsys
+
+# Targets
+niosii_qip = $(niosii_dir)/synthesis/niosII.qip
+niosii_info = niosII.sopcinfo
+
+bsp_settings = $(bsp_dir)/settings.bsp
+bsp_makefile = $(bsp_dir)/Makefile
+
+# VHDL source files
+hdl_src += \
+    hardware/system/sync_ff.vhd \
+    hardware/system/sync_rst.vhd \
+    hardware/system/pll/pll_main.vhd \
+    hardware/system/reg32.vhd \
+    hardware/system/avalon_slave_transitions.vhd \
+    hardware/system/avalon_slave.vhd \
+    hardware/system/data_sink_mux.vhd \
+    hardware/system/fifo.vhd \
+    hardware/system/data_source_mux.vhd \
+    hardware/system/data_channel_control.vhd \
+    hardware/system/data_channel.vhd \
+    hardware/system/hardware_timestamp.vhd \
+    hardware/system/task.vhd \
+    hardware/system/float.vhd \
+    hardware/system/hardware_task_control.vhd \
+    hardware/system/hardware_task.vhd \
+    hardware/system/float_add.vhd \
+    hardware/signal_processing/add.vhd \
+    hardware/system/task_add.vhd \
+    hardware/signal_processing/rand.vhd \
+    hardware/system/task_rand.vhd \
+    hardware/system/cordic_pkg.vhd \
+    hardware/system/cordic.vhd \
+    hardware/system/fixed_sine.vhd \
+    hardware/system/float_sine.vhd \
+    hardware/signal_processing/sine.vhd \
+    hardware/system/task_sine.vhd \
+    hardware/system/Butterfly.v \
+    hardware/system/DelayBuffer.v \
+    hardware/system/FFT1024_32B.v \
+    hardware/system/Multiply.v \
+    hardware/system/SdfUnit2.v \
+    hardware/system/SdfUnit.v \
+    hardware/system/Twiddle1024_32B.v \
+    hardware/system/squareRoot_pipe.vhd \
+    hardware/system/fft_magnitude_calc.vhd \
+    hardware/signal_processing/fft.vhd \
+    hardware/system/task_fft.vhd \
+    hardware/signal_processing/crc.vhd \
+    hardware/system/task_crc.vhd \
+    hardware/signal_processing/signal_processing.vhd \
+
+#
+clean_items += \
+    $(niosii_dir) \
+    $(niosii_info) \
+    .map \
+    .fitter \
+    .assembler \
+    .sta \
+    .qsys_edit/ \
+    db/ \
+    incremental_db/ \
+    output_files/ \
+
+.PHONY: all \
+        niosII \
+        fpga \
+        program \
+        clean \
+        app \
+        download \
+        run \
+		tests \
+
+all: run
+
+#------------------------------------------------------------------------------
+# Create the NiosII system from the description file
+niosII: $(niosii_info)
+
+# Create the NiosII sources from the description file
+$(niosii_qip): $(niosii_qsys)
+	@echo Generating the NiosII system from $< ...
+	@$(qsys_generate) -syn=VHDL $<
+
+# The NiosII system information file is created in parallel to the .qip file.
+$(niosii_info): $(niosii_qip)
+
+#------------------------------------------------------------------------------
+# Quartus FPGA toolchain contains the mapper, fitter, assembler and static
+# timing analysis (sta).
+#
+fpga: .sta
+
+# Anaylze and synthesis of the QuartusII project
+.map: $(hdl_src) $(niosii_info) $(signal_processing_qsf)
+	@rm -f $@
+	@$(quartus_map) --read_settings_files=on --write_settings_files=off $(quartus_project) -c $(quartus_project) && date > $@
+
+# Run the quartus fitter on the project
+.fitter: .map $(sdc_src) $(signal_processing_qsf)
+	@rm -f $@
+	@$(quartus_fit) --read_settings_files=on --write_settings_files=off $(quartus_project) -c $(quartus_project) && date > $@
+
+.assembler: .fitter
+	@rm -f $@
+	@$(quartus_asm) --read_settings_files=off --write_settings_files=off $(quartus_project) -c $(quartus_project)&& date > $@
+
+.sta: .assembler
+	@rm -f $@
+	@$(quartus_sta) $(quartus_project) -c $(quartus_project) && date > $@
+
+output_files/signal_processing_time_limited.sof: .sta
+
+# Create the BSP from the sopc description
+bsp: ${bsp_makefile}
+
+$(bsp_settings): $(niosii_info)
+	@echo Generating the NiosII BSP from $< ...
+	@$(niosii_bsp) hal $(bsp_dir) $<
+
+$(bsp_makefile): $(bsp_settings)
+	@$(nios2_bsp_generate_files) --settings software/signal_processing_bsp/settings.bsp --bsp-dir software/signal_processing_bsp/
+
+app: $(bsp_makefile)
+	${MAKE} -C $(app_dir)
+
+# Programme the FPGA design
+program: output_files/signal_processing_time_limited.sof
+	@$(quartus_pgm) signal_processing.cdf
+
+# Programme the NiosII software design
+download: app
+	@$(nios2-download) $(app_dir)/signal_processing.elf -g
+
+# Programme the NiosII software design
+run: fpga download
+	@$(nios2-terminal)
+
+sw_tests:
+	@${MAKE} -C tests/software
+
+hw_tests:
+	@${MAKE} -C tests/hardware
+
+device_tests:
+	@${MAKE} -C tests/device
+
+tests: sw_tests hw_tests device_tests
+
+clean:
+	@rm -rf $(clean_items)
+	@${MAKE} -C ${hw_test_dir} clean
+	@${MAKE} -C ${sw_test_dir} clean
+	@${MAKE} -C ${app_dir} clean
+	@${MAKE} -C ${bsp_dir} clean
+

data_channel_hw.tcl

+# TCL File Generated by Component Editor 21.1
+# Fri Sep 09 13:42:23 CEST 2022
+# DO NOT MODIFY
+
+
+# 
+# data_channel "data_channel" v1.0
+# Johannes Kutning 2022.09.09.13:42:23
+# A data channel for signal data transport
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module data_channel
+# 
+set_module_property DESCRIPTION "A data channel for signal data transport"
+set_module_property NAME data_channel
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP signal_processing
+set_module_property AUTHOR "Johannes Kutning"
+set_module_property DISPLAY_NAME data_channel
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL data_channel
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file data_channel.vhd VHDL PATH hardware/system/data_channel.vhd TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+add_parameter DEPTH POSITIVE 1024
+set_parameter_property DEPTH DEFAULT_VALUE 1024
+set_parameter_property DEPTH DISPLAY_NAME DEPTH
+set_parameter_property DEPTH TYPE POSITIVE
+set_parameter_property DEPTH UNITS None
+set_parameter_property DEPTH ALLOWED_RANGES 1:2147483647
+set_parameter_property DEPTH HDL_PARAMETER true
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point ctrl
+# 
+add_interface ctrl avalon end
+set_interface_property ctrl addressUnits WORDS
+set_interface_property ctrl associatedClock clock
+set_interface_property ctrl associatedReset reset
+set_interface_property ctrl bitsPerSymbol 8
+set_interface_property ctrl burstOnBurstBoundariesOnly false
+set_interface_property ctrl burstcountUnits WORDS
+set_interface_property ctrl explicitAddressSpan 0
+set_interface_property ctrl holdTime 0
+set_interface_property ctrl linewrapBursts false
+set_interface_property ctrl maximumPendingReadTransactions 0
+set_interface_property ctrl maximumPendingWriteTransactions 0
+set_interface_property ctrl readLatency 0
+set_interface_property ctrl readWaitTime 1
+set_interface_property ctrl setupTime 0
+set_interface_property ctrl timingUnits Cycles
+set_interface_property ctrl writeWaitTime 0
+set_interface_property ctrl ENABLED true
+set_interface_property ctrl EXPORT_OF ""
+set_interface_property ctrl PORT_NAME_MAP ""
+set_interface_property ctrl CMSIS_SVD_VARIABLES ""
+set_interface_property ctrl SVD_ADDRESS_GROUP ""
+
+add_interface_port ctrl ctrl_address address Input 4
+add_interface_port ctrl ctrl_read read Input 1
+add_interface_port ctrl ctrl_readdata readdata Output 32
+add_interface_port ctrl ctrl_write write Input 1
+add_interface_port ctrl ctrl_writedata writedata Input 32
+set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
+set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point hw_sink
+# 
+add_interface hw_sink avalon end
+set_interface_property hw_sink addressUnits WORDS
+set_interface_property hw_sink associatedClock clock
+set_interface_property hw_sink associatedReset reset
+set_interface_property hw_sink bitsPerSymbol 8
+set_interface_property hw_sink burstOnBurstBoundariesOnly false
+set_interface_property hw_sink burstcountUnits WORDS
+set_interface_property hw_sink explicitAddressSpan 0
+set_interface_property hw_sink holdTime 0
+set_interface_property hw_sink linewrapBursts false
+set_interface_property hw_sink maximumPendingReadTransactions 0
+set_interface_property hw_sink maximumPendingWriteTransactions 0
+set_interface_property hw_sink readLatency 0
+set_interface_property hw_sink readWaitTime 1
+set_interface_property hw_sink setupTime 0
+set_interface_property hw_sink timingUnits Cycles
+set_interface_property hw_sink writeWaitTime 0
+set_interface_property hw_sink ENABLED true
+set_interface_property hw_sink EXPORT_OF ""
+set_interface_property hw_sink PORT_NAME_MAP ""
+set_interface_property hw_sink CMSIS_SVD_VARIABLES ""
+set_interface_property hw_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port hw_sink hw_sink_write write Input 1
+add_interface_port hw_sink hw_sink_writedata writedata Input 32
+set_interface_assignment hw_sink embeddedsw.configuration.isFlash 0
+set_interface_assignment hw_sink embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment hw_sink embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment hw_sink embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point hw_source
+# 
+add_interface hw_source avalon end
+set_interface_property hw_source addressUnits WORDS
+set_interface_property hw_source associatedClock clock
+set_interface_property hw_source associatedReset reset
+set_interface_property hw_source bitsPerSymbol 8
+set_interface_property hw_source burstOnBurstBoundariesOnly false
+set_interface_property hw_source burstcountUnits WORDS
+set_interface_property hw_source explicitAddressSpan 0
+set_interface_property hw_source holdTime 0
+set_interface_property hw_source linewrapBursts false
+set_interface_property hw_source maximumPendingReadTransactions 0
+set_interface_property hw_source maximumPendingWriteTransactions 0
+set_interface_property hw_source readLatency 0
+set_interface_property hw_source readWaitTime 1
+set_interface_property hw_source setupTime 0
+set_interface_property hw_source timingUnits Cycles
+set_interface_property hw_source writeWaitTime 0
+set_interface_property hw_source ENABLED true
+set_interface_property hw_source EXPORT_OF ""
+set_interface_property hw_source PORT_NAME_MAP ""
+set_interface_property hw_source CMSIS_SVD_VARIABLES ""
+set_interface_property hw_source SVD_ADDRESS_GROUP ""
+
+add_interface_port hw_source hw_source_read read Input 1
+add_interface_port hw_source hw_source_readdata readdata Output 32
+set_interface_assignment hw_source embeddedsw.configuration.isFlash 0
+set_interface_assignment hw_source embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment hw_source embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment hw_source embeddedsw.configuration.isPrintableDevice 0
+

hardware/signal_processing.sdc

+# External clock clk_50 has a frequency of 50 MHz
+create_clock -period 20   [get_ports clk_input]
+
+derive_pll_clocks
+
+set clk_main u_pll_200|pll_200|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk
+
+# Input delays for singals in 50 MHz domain
+set_input_delay \
+    -clock { clk_input }  \
+    2 \
+    [get_ports {reset_n}]
+
+# Input delays for singals in 200 MHz domain
+set_false_path \
+    -from \
+    [get_ports {key_start}]
+
+# Output delays for singals in 200 MHz domain
+set_false_path \
+    -to \
+    [get_ports { \
+        leds[0] \
+        leds[1] \
+        leds[2] \
+        leds[3] \
+        leds[4] \
+        leds[5] \
+        leds[6] \
+        leds[7] \
+    }]
+

hardware/signal_processing/add.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity add is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        task_start : in std_logic;
+        task_state : out work.task.State;
+
+        signal_a_read : out std_logic;
+        signal_a_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_b_read : out std_logic;
+        signal_b_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity add;
+
+architecture rtl of add is
+    signal current_task_state : work.task.State;
+    signal next_task_state : work.task.State;
+    signal index : integer range 0 to work.task.STREAM_LEN;
+
+begin
+    task_state_transitions : process ( current_task_state, task_start, index ) is
+    begin
+        next_task_state <= current_task_state;
+        case current_task_state is
+            when work.task.TASK_IDLE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+            when work.task.TASK_RUNNING =>
+                if ( index = work.task.STREAM_LEN - 1 ) then
+                    next_task_state <= work.task.TASK_DONE;
+                end if;
+            when work.task.TASK_DONE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+        end case;
+    end process task_state_transitions;
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_task_state <= work.task.TASK_IDLE;
+            index <= 0;
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            case next_task_state is
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
+            end case;
+        end if;
+    end process sync;
+
+    task_state <= current_task_state;
+
+end architecture rtl;

hardware/signal_processing/crc.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity crc is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        task_start : in std_logic;
+        task_state : out work.task.State;
+
+        signal_read : out std_logic;
+        signal_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity crc;
+
+architecture rtl of crc is
+
+    signal current_task_state : work.task.State;
+    signal next_task_state : work.task.State;
+    signal index : integer range 0 to work.task.STREAM_LEN;
+
+begin
+    task_state_transitions : process ( current_task_state, task_start, index ) is
+    begin
+        next_task_state <= current_task_state;
+        case current_task_state is
+            when work.task.TASK_IDLE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+            when work.task.TASK_RUNNING =>
+                if ( index = work.task.STREAM_LEN - 1 ) then
+                    next_task_state <= work.task.TASK_DONE;
+                end if;
+            when work.task.TASK_DONE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+        end case;
+    end process task_state_transitions;
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_task_state <= work.task.TASK_IDLE;
+            index <= 0;
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            case next_task_state is
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
+            end case;
+        end if;
+    end process sync;
+
+    task_state <= current_task_state;
+
+end architecture rtl;
+

hardware/signal_processing/fft.vhd

+------------------------------------------------------------------------
+-- fft
+--
+-- calculation of FFT magnitude
+--
+-- Inputs:
+-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
+--
+-- Outputs
+-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
+--
+-----------------------------------------------------------------------
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+	 use work.float.all;
+
+entity fft is
+  generic (
+
+    -- input data width of real/img part
+      input_data_width : integer := 32;
+
+    -- output data width of real/img part
+      output_data_width : integer := 32
+
+    );
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        task_start : in std_logic;
+        task_state : out work.task.State;
+
+        signal_read : out std_logic;
+        signal_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity fft;
+
+architecture rtl of fft is
+
+    signal current_task_state : work.task.State;
+    signal next_task_state : work.task.State;
+    signal index : integer range 0 to work.task.STREAM_LEN;
+
+begin
+    task_state_transitions : process ( current_task_state, task_start, index ) is
+    begin
+        next_task_state <= current_task_state;
+        case current_task_state is
+            when work.task.TASK_IDLE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+            when work.task.TASK_RUNNING =>
+                if ( index = work.task.STREAM_LEN - 1 ) then
+                    next_task_state <= work.task.TASK_DONE;
+                end if;
+            when work.task.TASK_DONE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+        end case;
+    end process task_state_transitions;
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_task_state <= work.task.TASK_IDLE;
+            index <= 0;
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            case next_task_state is
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
+            end case;
+        end if;
+    end process sync;
+
+    task_state <= current_task_state;
+
+end architecture rtl;

hardware/signal_processing/rand.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity rand is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        task_start : in std_logic;
+        task_state : out work.task.State;
+        seed : in work.reg32.word;
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity rand;
+
+architecture rtl of rand is
+
+    signal current_task_state : work.task.State;
+    signal next_task_state : work.task.State;
+    signal index : integer range 0 to work.task.STREAM_LEN;
+
+begin
+    task_state_transitions : process ( current_task_state, task_start, index ) is
+    begin
+        next_task_state <= current_task_state;
+        case current_task_state is
+            when work.task.TASK_IDLE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+            when work.task.TASK_RUNNING =>
+                if ( index = work.task.STREAM_LEN - 1 ) then
+                    next_task_state <= work.task.TASK_DONE;
+                end if;
+            when work.task.TASK_DONE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+        end case;
+    end process task_state_transitions;
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_task_state <= work.task.TASK_IDLE;
+            index <= 0;
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            case next_task_state is
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
+            end case;
+        end if;
+    end process sync;
+
+    task_state <= current_task_state;
+
+end architecture rtl;

hardware/signal_processing/signal_processing.vhd

+--! Use ieee library for std_logic types.
+library ieee;
+    use ieee.std_logic_1164.all;
+
+--! Use the niosII library for all processor system components
+library niosII;
+
+--! Use the pll_200 library for the PLL 200 MHz clock generation
+library pll_main;
+
+entity signal_processing is
+    port
+    (
+        clk_input : in  std_logic;
+        reset_n : in  std_logic;
+
+        --! Push button key_0 used to start a single execution of the signal
+        --! processing.
+        key_start : in  std_logic;
+
+        leds     : out std_logic_vector( 7 downto 0 )
+    );
+end entity signal_processing;
+
+architecture struct of signal_processing is
+
+    --! input clock synchronous reset
+    signal sync_reset : std_logic;
+
+    --! main clock for the NiosII system
+    signal clk_main : std_logic;
+    --! main clock from PLL is locked and the system reset can be released.
+    signal locked_main : std_logic;
+    --! main clock synchronous reset
+    signal sync_reset_main : std_logic;
+    signal sync_reset_main_n : std_logic;
+
+    signal sw_leds : std_logic_vector( 7 downto 0 );
+    signal hw_leds : std_logic_vector( 7 downto 0 );
+
+    signal hardware_task_0_address : std_logic_vector(3 downto 0);
+    signal hardware_task_0_read : std_logic;
+    signal hardware_task_0_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_0_write : std_logic;
+    signal hardware_task_0_writedata : std_logic_vector(31 downto 0);
+
+    signal hardware_task_1_address : std_logic_vector(3 downto 0);
+    signal hardware_task_1_read : std_logic;
+    signal hardware_task_1_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_1_write : std_logic;
+    signal hardware_task_1_writedata : std_logic_vector(31 downto 0);
+
+    signal hardware_task_2_address : std_logic_vector(3 downto 0);
+    signal hardware_task_2_read : std_logic;
+    signal hardware_task_2_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_2_write : std_logic;
+    signal hardware_task_2_writedata : std_logic_vector(31 downto 0);
+
+    signal hardware_task_3_address : std_logic_vector(3 downto 0);
+    signal hardware_task_3_read : std_logic;
+    signal hardware_task_3_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_3_write : std_logic;
+    signal hardware_task_3_writedata : std_logic_vector(31 downto 0);
+
+    signal hardware_task_4_address : std_logic_vector(3 downto 0);
+    signal hardware_task_4_read : std_logic;
+    signal hardware_task_4_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_4_write : std_logic;
+    signal hardware_task_4_writedata : std_logic_vector(31 downto 0);
+
+    signal hardware_task_5_address : std_logic_vector(3 downto 0);
+    signal hardware_task_5_read : std_logic;
+    signal hardware_task_5_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_5_write : std_logic;
+    signal hardware_task_5_writedata : std_logic_vector(31 downto 0);
+
+    signal hardware_task_6_address : std_logic_vector(3 downto 0);
+    signal hardware_task_6_read : std_logic;
+    signal hardware_task_6_readdata : std_logic_vector(31 downto 0);
+    signal hardware_task_6_write : std_logic;
+    signal hardware_task_6_writedata : std_logic_vector(31 downto 0);
+
+    signal data_channel_0_hw_sink_write : std_logic;
+    signal data_channel_0_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_0_hw_source_read : std_logic;
+    signal data_channel_0_hw_source_readdata : std_logic_vector(31 downto 0);
+
+    signal data_channel_1_hw_sink_write : std_logic;
+    signal data_channel_1_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_1_hw_source_read : std_logic;
+    signal data_channel_1_hw_source_readdata : std_logic_vector(31 downto 0);
+
+    signal data_channel_2_hw_sink_write : std_logic;
+    signal data_channel_2_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_2_hw_source_read : std_logic;
+    signal data_channel_2_hw_source_readdata : std_logic_vector(31 downto 0);
+
+    signal data_channel_3_hw_sink_write : std_logic;
+    signal data_channel_3_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_3_hw_source_read : std_logic;
+    signal data_channel_3_hw_source_readdata : std_logic_vector(31 downto 0);
+
+    signal data_channel_4_hw_sink_write : std_logic;
+    signal data_channel_4_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_4_hw_source_read : std_logic;
+    signal data_channel_4_hw_source_readdata : std_logic_vector(31 downto 0);
+
+    signal data_channel_5_hw_sink_write : std_logic;
+    signal data_channel_5_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_5_hw_source_read : std_logic;
+    signal data_channel_5_hw_source_readdata : std_logic_vector(31 downto 0);
+
+    signal data_channel_6_hw_sink_write : std_logic;
+    signal data_channel_6_hw_sink_writedata : std_logic_vector(31 downto 0);
+    signal data_channel_6_hw_source_read : std_logic;
+    signal data_channel_6_hw_source_readdata : std_logic_vector(31 downto 0);
+begin
+
+    -- Synchronize the external reset to the external clock domain
+    u_sync_rst_50: entity work.sync_rst
+        port map
+        (
+            clk => clk_input,
+            reset => not reset_n,
+            rst_sync => sync_reset
+        );
+
+    -- PLL for the main system clock
+    u_pll_main: entity pll_main.pll_main
+        port map
+        (
+            refclk   => clk_input,     -- in  std_logic
+            rst      => sync_reset,   -- in  std_logic
+            outclk_0 => clk_main,    -- out std_logic
+            locked   => locked_main  -- out std_logic
+        );
+
+    -- Synchronize the main reset to the main clock domain
+    u_sync_rst_main: entity work.sync_rst
+        port map
+        (
+            clk => clk_main,
+            reset => not locked_main and sync_reset,
+            rst_sync => sync_reset_main
+        );
+    sync_reset_main_n <= not sync_reset_main;
+
+    -- NiosII system
+    u_niosII : entity niosii.niosII
+        port map
+        (
+            clk_clk => clk_main,
+            reset_reset_n => sync_reset_main_n,
+
+            key_start_export => key_start,
+            leds_export => sw_leds,
+
+			data_channel_0_hw_sink_write => data_channel_0_hw_sink_write,
+			data_channel_0_hw_sink_writedata => data_channel_0_hw_sink_writedata,
+			data_channel_0_hw_source_read => data_channel_0_hw_source_read,
+			data_channel_0_hw_source_readdata => data_channel_0_hw_source_readdata,
+
+			data_channel_1_hw_sink_write => data_channel_1_hw_sink_write,
+			data_channel_1_hw_sink_writedata => data_channel_1_hw_sink_writedata,
+			data_channel_1_hw_source_read => data_channel_1_hw_source_read,
+			data_channel_1_hw_source_readdata => data_channel_1_hw_source_readdata,
+
+			data_channel_2_hw_sink_write => data_channel_2_hw_sink_write,
+			data_channel_2_hw_sink_writedata => data_channel_2_hw_sink_writedata,
+			data_channel_2_hw_source_read => data_channel_2_hw_source_read,
+			data_channel_2_hw_source_readdata => data_channel_2_hw_source_readdata,
+
+			data_channel_3_hw_sink_write => data_channel_3_hw_sink_write,
+			data_channel_3_hw_sink_writedata => data_channel_3_hw_sink_writedata,
+			data_channel_3_hw_source_read => data_channel_3_hw_source_read,
+			data_channel_3_hw_source_readdata => data_channel_3_hw_source_readdata,
+
+			data_channel_4_hw_sink_write => data_channel_4_hw_sink_write,
+			data_channel_4_hw_sink_writedata => data_channel_4_hw_sink_writedata,
+			data_channel_4_hw_source_read => data_channel_4_hw_source_read,
+			data_channel_4_hw_source_readdata => data_channel_4_hw_source_readdata,
+
+			data_channel_5_hw_sink_write => data_channel_5_hw_sink_write,
+			data_channel_5_hw_sink_writedata => data_channel_5_hw_sink_writedata,
+			data_channel_5_hw_source_read => data_channel_5_hw_source_read,
+			data_channel_5_hw_source_readdata => data_channel_5_hw_source_readdata,
+
+			data_channel_6_hw_sink_write => data_channel_6_hw_sink_write,
+			data_channel_6_hw_sink_writedata => data_channel_6_hw_sink_writedata,
+			data_channel_6_hw_source_read => data_channel_6_hw_source_read,
+			data_channel_6_hw_source_readdata => data_channel_6_hw_source_readdata,
+
+			hardware_task_0_task_address => hardware_task_0_address,
+			hardware_task_0_task_read => hardware_task_0_read,
+			hardware_task_0_task_readdata => hardware_task_0_readdata,
+			hardware_task_0_task_write     => hardware_task_0_write,
+			hardware_task_0_task_writedata => hardware_task_0_writedata,
+
+			hardware_task_1_task_address => hardware_task_1_address,
+			hardware_task_1_task_read => hardware_task_1_read,
+			hardware_task_1_task_readdata => hardware_task_1_readdata,
+			hardware_task_1_task_write     => hardware_task_1_write,
+			hardware_task_1_task_writedata => hardware_task_1_writedata,
+
+			hardware_task_2_task_address => hardware_task_2_address,
+			hardware_task_2_task_read => hardware_task_2_read,
+			hardware_task_2_task_readdata => hardware_task_2_readdata,
+			hardware_task_2_task_write     => hardware_task_2_write,
+			hardware_task_2_task_writedata => hardware_task_2_writedata,
+
+			hardware_task_3_task_address => hardware_task_3_address,
+			hardware_task_3_task_read => hardware_task_3_read,
+			hardware_task_3_task_readdata => hardware_task_3_readdata,
+			hardware_task_3_task_write     => hardware_task_3_write,
+			hardware_task_3_task_writedata => hardware_task_3_writedata,
+
+			hardware_task_4_task_address => hardware_task_4_address,
+			hardware_task_4_task_read => hardware_task_4_read,
+			hardware_task_4_task_readdata => hardware_task_4_readdata,
+			hardware_task_4_task_write     => hardware_task_4_write,
+			hardware_task_4_task_writedata => hardware_task_4_writedata,
+
+			hardware_task_5_task_address => hardware_task_5_address,
+			hardware_task_5_task_read => hardware_task_5_read,
+			hardware_task_5_task_readdata => hardware_task_5_readdata,
+			hardware_task_5_task_write     => hardware_task_5_write,
+			hardware_task_5_task_writedata => hardware_task_5_writedata,
+
+			hardware_task_6_task_address => hardware_task_6_address,
+			hardware_task_6_task_read => hardware_task_6_read,
+			hardware_task_6_task_readdata => hardware_task_6_readdata,
+			hardware_task_6_task_write     => hardware_task_6_write,
+			hardware_task_6_task_writedata => hardware_task_6_writedata
+        );
+
+    u_task_sine: entity work.task_sine
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_0_address,
+            read => hardware_task_0_read,
+            readdata => hardware_task_0_readdata,
+            write => hardware_task_0_write,
+            writedata => hardware_task_0_writedata,
+
+            signal_write => data_channel_0_hw_sink_write ,
+            signal_writedata => data_channel_0_hw_sink_writedata
+        );
+
+    u_task_cosine: entity work.task_sine
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_1_address,
+            read => hardware_task_1_read,
+            readdata => hardware_task_1_readdata,
+            write => hardware_task_1_write,
+            writedata => hardware_task_1_writedata,
+
+            signal_write => data_channel_1_hw_sink_write ,
+            signal_writedata => data_channel_1_hw_sink_writedata
+        );
+
+    u_task_rand: entity work.task_rand
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_2_address,
+            read => hardware_task_2_read,
+            readdata => hardware_task_2_readdata,
+            write => hardware_task_2_write,
+            writedata => hardware_task_2_writedata,
+
+            signal_write => data_channel_2_hw_sink_write ,
+            signal_writedata => data_channel_2_hw_sink_writedata
+        );
+
+    u_task_add_sine_cosine: entity work.task_add
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_3_address,
+            read => hardware_task_3_read,
+            readdata => hardware_task_3_readdata,
+            write => hardware_task_3_write,
+            writedata => hardware_task_3_writedata,
+
+            signal_a_read => data_channel_0_hw_source_read,
+            signal_a_readdata => data_channel_0_hw_source_readdata,
+
+            signal_b_read => data_channel_1_hw_source_read,
+            signal_b_readdata => data_channel_1_hw_source_readdata,
+
+            signal_write => data_channel_3_hw_sink_write ,
+            signal_writedata => data_channel_3_hw_sink_writedata
+        );
+
+    u_task_add_rand: entity work.task_add
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_4_address,
+            read => hardware_task_4_read,
+            readdata => hardware_task_4_readdata,
+            write => hardware_task_4_write,
+            writedata => hardware_task_4_writedata,
+
+            signal_a_read => data_channel_2_hw_source_read,
+            signal_a_readdata => data_channel_2_hw_source_readdata,
+
+            signal_b_read => data_channel_3_hw_source_read,
+            signal_b_readdata => data_channel_3_hw_source_readdata,
+
+            signal_write => data_channel_4_hw_sink_write ,
+            signal_writedata => data_channel_4_hw_sink_writedata
+        );
+
+    u_task_fft: entity work.task_fft
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_5_address,
+            read => hardware_task_5_read,
+            readdata => hardware_task_5_readdata,
+            write => hardware_task_5_write,
+            writedata => hardware_task_5_writedata,
+
+            signal_read => data_channel_4_hw_source_read,
+            signal_readdata => data_channel_4_hw_source_readdata,
+
+            signal_write => data_channel_5_hw_sink_write ,
+            signal_writedata => data_channel_5_hw_sink_writedata
+        );
+
+    u_task_crc: entity work.task_crc
+        port map (
+            clk => clk_main,
+            reset => sync_reset_main,
+
+            address => hardware_task_6_address,
+            read => hardware_task_6_read,
+            readdata => hardware_task_6_readdata,
+            write => hardware_task_6_write,
+            writedata => hardware_task_6_writedata,
+
+            signal_read => data_channel_5_hw_source_read,
+            signal_readdata => data_channel_5_hw_source_readdata,
+
+            signal_write => data_channel_6_hw_sink_write ,
+            signal_writedata => data_channel_6_hw_sink_writedata
+        );
+
+    hw_leds <= ( 0 => reset_n, 1 => sync_reset, 2 => locked_main, 3 => sync_reset_main, others => '0' );
+    leds <= sw_leds or hw_leds;
+
+end architecture struct;
+

hardware/signal_processing/sine.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.float.all;
+    use work.task.all;
+
+entity sine is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        task_start : in std_logic;
+        task_state : out work.task.State;
+
+        step_size : in work.reg32.word;
+        phase : in work.reg32.word;
+        amplitude : in work.reg32.word;
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity sine;
+
+architecture rtl of sine is
+
+    signal current_task_state : work.task.State;
+    signal next_task_state : work.task.State;
+    signal index : integer range 0 to work.task.STREAM_LEN;
+
+begin
+    task_state_transitions : process ( current_task_state, task_start, index ) is
+    begin
+        next_task_state <= current_task_state;
+        case current_task_state is
+            when work.task.TASK_IDLE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+            when work.task.TASK_RUNNING =>
+                if ( index = work.task.STREAM_LEN - 1 ) then
+                    next_task_state <= work.task.TASK_DONE;
+                end if;
+            when work.task.TASK_DONE =>
+                if ( task_start = '1' ) then
+                    next_task_state <= work.task.TASK_RUNNING;
+                end if;
+        end case;
+    end process task_state_transitions;
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_task_state <= work.task.TASK_IDLE;
+            index <= 0;
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            case next_task_state is
+            when work.task.TASK_IDLE =>
+                index <= 0;
+                signal_write <= '0';
+            when work.task.TASK_RUNNING =>
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
+            when work.task.TASK_DONE =>
+                index <= 0;
+                signal_write <= '0';
+            end case;
+        end if;
+    end process sync;
+
+    task_state <= current_task_state;
+
+end architecture rtl;

hardware/system/Butterfly.v

+//----------------------------------------------------------------------
+//  Butterfly: Add/Sub and Scaling
+//----------------------------------------------------------------------
+module Butterfly #(
+    parameter   WIDTH = 16,
+    parameter   RH = 0  //  Round Half Up
+)(
+    input   signed  [WIDTH-1:0] x0_re,  //  Input Data #0 (Real)
+    input   signed  [WIDTH-1:0] x0_im,  //  Input Data #0 (Imag)
+    input   signed  [WIDTH-1:0] x1_re,  //  Input Data #1 (Real)
+    input   signed  [WIDTH-1:0] x1_im,  //  Input Data #1 (Imag)
+    output  signed  [WIDTH-1:0] y0_re,  //  Output Data #0 (Real)
+    output  signed  [WIDTH-1:0] y0_im,  //  Output Data #0 (Imag)
+    output  signed  [WIDTH-1:0] y1_re,  //  Output Data #1 (Real)
+    output  signed  [WIDTH-1:0] y1_im   //  Output Data #1 (Imag)
+);
+
+wire signed [WIDTH:0]   add_re, add_im, sub_re, sub_im;
+
+//  Add/Sub
+assign  add_re = x0_re + x1_re;
+assign  add_im = x0_im + x1_im;
+assign  sub_re = x0_re - x1_re;
+assign  sub_im = x0_im - x1_im;
+
+//  Scaling
+assign  y0_re = (add_re + RH) >>> 1;
+assign  y0_im = (add_im + RH) >>> 1;
+assign  y1_re = (sub_re + RH) >>> 1;
+assign  y1_im = (sub_im + RH) >>> 1;
+
+endmodule

hardware/system/DelayBuffer.v

+//----------------------------------------------------------------------
+//  DelayBuffer: Generate Constant Delay
+//----------------------------------------------------------------------
+module DelayBuffer #(
+    parameter   DEPTH = 32,
+    parameter   WIDTH = 16
+)(
+    input               clock,  //  Master Clock
+    input   [WIDTH-1:0] di_re,  //  Data Input (Real)
+    input   [WIDTH-1:0] di_im,  //  Data Input (Imag)
+    output  [WIDTH-1:0] do_re,  //  Data Output (Real)
+    output  [WIDTH-1:0] do_im   //  Data Output (Imag)
+);
+
+reg [WIDTH-1:0] buf_re[0:DEPTH-1];
+reg [WIDTH-1:0] buf_im[0:DEPTH-1];
+integer n;
+
+//  Shift Buffer
+always @(posedge clock) begin
+    for (n = DEPTH-1; n > 0; n = n - 1) begin
+        buf_re[n] <= buf_re[n-1];
+        buf_im[n] <= buf_im[n-1];
+    end
+    buf_re[0] <= di_re;
+    buf_im[0] <= di_im;
+end
+
+assign  do_re = buf_re[DEPTH-1];
+assign  do_im = buf_im[DEPTH-1];
+
+endmodule

hardware/system/FFT1024_32B.v

+//----------------------------------------------------------------------
+//  FFT: 1024-Point FFT Using Radix-2^2 Single-Path Delay Feedback
+//----------------------------------------------------------------------
+module FFTMAIN #(
+    parameter   WIDTH = 32
+)(
+    input               clock,  //  Master Clock
+    input               reset,  //  Active High Asynchronous Reset
+    input               di_en,  //  Input Data Enable
+    input   [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input   [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output              do_en,  //  Output Data Enable
+    output  [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+//----------------------------------------------------------------------
+//  Data must be input consecutively in natural order.
+//  The result is scaled to 1/N and output in bit-reversed order.
+//----------------------------------------------------------------------
+
+wire            su1_do_en;
+wire[WIDTH-1:0] su1_do_re;
+wire[WIDTH-1:0] su1_do_im;
+wire            su2_do_en;
+wire[WIDTH-1:0] su2_do_re;
+wire[WIDTH-1:0] su2_do_im;
+wire            su3_do_en;
+wire[WIDTH-1:0] su3_do_re;
+wire[WIDTH-1:0] su3_do_im;
+wire            su4_do_en;
+wire[WIDTH-1:0] su4_do_re;
+wire[WIDTH-1:0] su4_do_im;
+
+SdfUnit #(.N(1024),.M(1024),.WIDTH(WIDTH)) SU1 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (di_en      ),  //  i
+    .di_re  (di_re      ),  //  i
+    .di_im  (di_im      ),  //  i
+    .do_en  (su1_do_en  ),  //  o
+    .do_re  (su1_do_re  ),  //  o
+    .do_im  (su1_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(256),.WIDTH(WIDTH)) SU2 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su1_do_en  ),  //  i
+    .di_re  (su1_do_re  ),  //  i
+    .di_im  (su1_do_im  ),  //  i
+    .do_en  (su2_do_en  ),  //  o
+    .do_re  (su2_do_re  ),  //  o
+    .do_im  (su2_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(64),.WIDTH(WIDTH)) SU3 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su2_do_en  ),  //  i
+    .di_re  (su2_do_re  ),  //  i
+    .di_im  (su2_do_im  ),  //  i
+    .do_en  (su3_do_en  ),  //  o
+    .do_re  (su3_do_re  ),  //  o
+    .do_im  (su3_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(16),.WIDTH(WIDTH)) SU4 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su3_do_en  ),  //  i
+    .di_re  (su3_do_re  ),  //  i
+    .di_im  (su3_do_im  ),  //  i
+    .do_en  (su4_do_en  ),  //  o
+    .do_re  (su4_do_re  ),  //  o
+    .do_im  (su4_do_im  )   //  o
+);
+
+SdfUnit #(.N(1024),.M(4),.WIDTH(WIDTH)) SU5 (
+    .clock  (clock      ),  //  i
+    .reset  (reset      ),  //  i
+    .di_en  (su4_do_en  ),  //  i
+    .di_re  (su4_do_re  ),  //  i
+    .di_im  (su4_do_im  ),  //  i
+    .do_en  (do_en      ),  //  o
+    .do_re  (do_re      ),  //  o
+    .do_im  (do_im      )   //  o
+);
+
+endmodule

hardware/system/Multiply.v

+//----------------------------------------------------------------------
+//  Multiply: Complex Multiplier
+//----------------------------------------------------------------------
+module Multiply #(
+    parameter   WIDTH = 16
+)(
+    input   signed  [WIDTH-1:0] a_re,
+    input   signed  [WIDTH-1:0] a_im,
+    input   signed  [WIDTH-1:0] b_re,
+    input   signed  [WIDTH-1:0] b_im,
+    output  signed  [WIDTH-1:0] m_re,
+    output  signed  [WIDTH-1:0] m_im
+);
+
+wire signed [WIDTH*2-1:0]   arbr, arbi, aibr, aibi;
+wire signed [WIDTH-1:0]     sc_arbr, sc_arbi, sc_aibr, sc_aibi;
+
+//  Signed Multiplication
+assign  arbr = a_re * b_re;
+assign  arbi = a_re * b_im;
+assign  aibr = a_im * b_re;
+assign  aibi = a_im * b_im;
+
+//  Scaling
+assign  sc_arbr = arbr >>> (WIDTH-1);
+assign  sc_arbi = arbi >>> (WIDTH-1);
+assign  sc_aibr = aibr >>> (WIDTH-1);
+assign  sc_aibi = aibi >>> (WIDTH-1);
+
+//  Sub/Add
+//  These sub/add may overflow if unnormalized data is input.
+assign  m_re = sc_arbr - sc_aibi;
+assign  m_im = sc_arbi + sc_aibr;
+
+endmodule

hardware/system/SdfUnit.v

+//----------------------------------------------------------------------
+//  SdfUnit: Radix-2^2 Single-Path Delay Feedback Unit for N-Point FFT
+//----------------------------------------------------------------------
+module SdfUnit #(
+    parameter   N = 64,     //  Number of FFT Point
+    parameter   M = 64,     //  Twiddle Resolution
+    parameter   WIDTH = 16  //  Data Bit Length
+)(
+    input               clock,  //  Master Clock
+    input               reset,  //  Active High Asynchronous Reset
+    input               di_en,  //  Input Data Enable
+    input   [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input   [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output              do_en,  //  Output Data Enable
+    output  [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+
+//  log2 constant function
+function integer log2;
+    input integer x;
+    integer value;
+    begin
+        value = x-1;
+        for (log2=0; value>0; log2=log2+1)
+            value = value>>1;
+    end
+endfunction
+
+localparam  LOG_N = log2(N);    //  Bit Length of N
+localparam  LOG_M = log2(M);    //  Bit Length of M
+
+//----------------------------------------------------------------------
+//  Internal Regs and Nets
+//----------------------------------------------------------------------
+//  1st Butterfly
+reg [LOG_N-1:0] di_count;   //  Input Data Count
+wire            bf1_bf;     //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] bf1_x0_re;  //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] bf1_x0_im;  //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] bf1_x1_re;  //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] bf1_x1_im;  //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] bf1_y0_re;  //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] bf1_y0_im;  //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] bf1_y1_re;  //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] bf1_y1_im;  //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db1_di_re;  //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db1_di_im;  //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db1_do_re;  //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db1_do_im;  //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf1_sp_re;  //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf1_sp_im;  //  Single-Path Data Output (Imag)
+reg             bf1_sp_en;  //  Single-Path Data Enable
+reg [LOG_N-1:0] bf1_count;  //  Single-Path Data Count
+wire            bf1_start;  //  Single-Path Output Trigger
+wire            bf1_end;    //  End of Single-Path Data
+wire            bf1_mj;     //  Twiddle (-j) Enable
+reg [WIDTH-1:0] bf1_do_re;  //  1st Butterfly Output Data (Real)
+reg [WIDTH-1:0] bf1_do_im;  //  1st Butterfly Output Data (Imag)
+
+//  2nd Butterfly
+reg             bf2_bf;     //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] bf2_x0_re;  //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] bf2_x0_im;  //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] bf2_x1_re;  //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] bf2_x1_im;  //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] bf2_y0_re;  //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] bf2_y0_im;  //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] bf2_y1_re;  //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] bf2_y1_im;  //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db2_di_re;  //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db2_di_im;  //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db2_do_re;  //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db2_do_im;  //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf2_sp_re;  //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf2_sp_im;  //  Single-Path Data Output (Imag)
+reg             bf2_sp_en;  //  Single-Path Data Enable
+reg [LOG_N-1:0] bf2_count;  //  Single-Path Data Count
+reg             bf2_start;  //  Single-Path Output Trigger
+wire            bf2_end;    //  End of Single-Path Data
+reg [WIDTH-1:0] bf2_do_re;  //  2nd Butterfly Output Data (Real)
+reg [WIDTH-1:0] bf2_do_im;  //  2nd Butterfly Output Data (Imag)
+reg             bf2_do_en;  //  2nd Butterfly Output Data Enable
+
+//  Multiplication
+wire[1:0]       tw_sel;     //  Twiddle Select (2n/n/3n)
+wire[LOG_N-3:0] tw_num;     //  Twiddle Number (n)
+wire[LOG_N-1:0] tw_addr;    //  Twiddle Table Address
+wire[WIDTH-1:0] tw_re;      //  Twiddle Factor (Real)
+wire[WIDTH-1:0] tw_im;      //  Twiddle Factor (Imag)
+reg             mu_en;      //  Multiplication Enable
+wire[WIDTH-1:0] mu_a_re;    //  Multiplier Input (Real)
+wire[WIDTH-1:0] mu_a_im;    //  Multiplier Input (Imag)
+wire[WIDTH-1:0] mu_m_re;    //  Multiplier Output (Real)
+wire[WIDTH-1:0] mu_m_im;    //  Multiplier Output (Imag)
+reg [WIDTH-1:0] mu_do_re;   //  Multiplication Output Data (Real)
+reg [WIDTH-1:0] mu_do_im;   //  Multiplication Output Data (Imag)
+reg             mu_do_en;   //  Multiplication Output Data Enable
+
+//----------------------------------------------------------------------
+//  1st Butterfly
+//----------------------------------------------------------------------
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        di_count <= {LOG_N{1'b0}};
+    end else begin
+        di_count <= di_en ? (di_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+assign  bf1_bf = di_count[LOG_M-1];
+
+//  Set unknown value x for verification
+assign  bf1_x0_re = bf1_bf ? db1_do_re : {WIDTH{1'bx}};
+assign  bf1_x0_im = bf1_bf ? db1_do_im : {WIDTH{1'bx}};
+assign  bf1_x1_re = bf1_bf ? di_re : {WIDTH{1'bx}};
+assign  bf1_x1_im = bf1_bf ? di_im : {WIDTH{1'bx}};
+
+Butterfly #(.WIDTH(WIDTH),.RH(0)) BF1 (
+    .x0_re  (bf1_x0_re  ),  //  i
+    .x0_im  (bf1_x0_im  ),  //  i
+    .x1_re  (bf1_x1_re  ),  //  i
+    .x1_im  (bf1_x1_im  ),  //  i
+    .y0_re  (bf1_y0_re  ),  //  o
+    .y0_im  (bf1_y0_im  ),  //  o
+    .y1_re  (bf1_y1_re  ),  //  o
+    .y1_im  (bf1_y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(2**(LOG_M-1)),.WIDTH(WIDTH)) DB1 (
+    .clock  (clock      ),  //  i
+    .di_re  (db1_di_re  ),  //  i
+    .di_im  (db1_di_im  ),  //  i
+    .do_re  (db1_do_re  ),  //  o
+    .do_im  (db1_do_im  )   //  o
+);
+
+assign  db1_di_re = bf1_bf ? bf1_y1_re : di_re;
+assign  db1_di_im = bf1_bf ? bf1_y1_im : di_im;
+assign  bf1_sp_re = bf1_bf ? bf1_y0_re : bf1_mj ?  db1_do_im : db1_do_re;
+assign  bf1_sp_im = bf1_bf ? bf1_y0_im : bf1_mj ? -db1_do_re : db1_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf1_sp_en <= 1'b0;
+        bf1_count <= {LOG_N{1'b0}};
+    end else begin
+        bf1_sp_en <= bf1_start ? 1'b1 : bf1_end ? 1'b0 : bf1_sp_en;
+        bf1_count <= bf1_sp_en ? (bf1_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+assign  bf1_start = (di_count == (2**(LOG_M-1)-1));
+assign  bf1_end = (bf1_count == (2**LOG_N-1));
+assign  bf1_mj = (bf1_count[LOG_M-1:LOG_M-2] == 2'd3);
+
+always @(posedge clock) begin
+    bf1_do_re <= bf1_sp_re;
+    bf1_do_im <= bf1_sp_im;
+end
+
+//----------------------------------------------------------------------
+//  2nd Butterfly
+//----------------------------------------------------------------------
+always @(posedge clock) begin
+    bf2_bf <= bf1_count[LOG_M-2];
+end
+
+//  Set unknown value x for verification
+assign  bf2_x0_re = bf2_bf ? db2_do_re : {WIDTH{1'bx}};
+assign  bf2_x0_im = bf2_bf ? db2_do_im : {WIDTH{1'bx}};
+assign  bf2_x1_re = bf2_bf ? bf1_do_re : {WIDTH{1'bx}};
+assign  bf2_x1_im = bf2_bf ? bf1_do_im : {WIDTH{1'bx}};
+
+//  Negative bias occurs when RH=0 and positive bias occurs when RH=1.
+//  Using both alternately reduces the overall rounding error.
+Butterfly #(.WIDTH(WIDTH),.RH(1)) BF2 (
+    .x0_re  (bf2_x0_re  ),  //  i
+    .x0_im  (bf2_x0_im  ),  //  i
+    .x1_re  (bf2_x1_re  ),  //  i
+    .x1_im  (bf2_x1_im  ),  //  i
+    .y0_re  (bf2_y0_re  ),  //  o
+    .y0_im  (bf2_y0_im  ),  //  o
+    .y1_re  (bf2_y1_re  ),  //  o
+    .y1_im  (bf2_y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(2**(LOG_M-2)),.WIDTH(WIDTH)) DB2 (
+    .clock  (clock      ),  //  i
+    .di_re  (db2_di_re  ),  //  i
+    .di_im  (db2_di_im  ),  //  i
+    .do_re  (db2_do_re  ),  //  o
+    .do_im  (db2_do_im  )   //  o
+);
+
+assign  db2_di_re = bf2_bf ? bf2_y1_re : bf1_do_re;
+assign  db2_di_im = bf2_bf ? bf2_y1_im : bf1_do_im;
+assign  bf2_sp_re = bf2_bf ? bf2_y0_re : db2_do_re;
+assign  bf2_sp_im = bf2_bf ? bf2_y0_im : db2_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf2_sp_en <= 1'b0;
+        bf2_count <= {LOG_N{1'b0}};
+    end else begin
+        bf2_sp_en <= bf2_start ? 1'b1 : bf2_end ? 1'b0 : bf2_sp_en;
+        bf2_count <= bf2_sp_en ? (bf2_count + 1'b1) : {LOG_N{1'b0}};
+    end
+end
+
+always @(posedge clock) begin
+    bf2_start <= (bf1_count == (2**(LOG_M-2)-1)) & bf1_sp_en;
+end
+assign  bf2_end = (bf2_count == (2**LOG_N-1));
+
+always @(posedge clock) begin
+    bf2_do_re <= bf2_sp_re;
+    bf2_do_im <= bf2_sp_im;
+end
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf2_do_en <= 1'b0;
+    end else begin
+        bf2_do_en <= bf2_sp_en;
+    end
+end
+
+//----------------------------------------------------------------------
+//  Multiplication
+//----------------------------------------------------------------------
+assign  tw_sel[1] = bf2_count[LOG_M-2];
+assign  tw_sel[0] = bf2_count[LOG_M-1];
+assign  tw_num = bf2_count << (LOG_N-LOG_M);
+assign  tw_addr = tw_num * tw_sel;
+
+Twiddle TW (
+    .clock  (clock  ),  //  i
+    .addr   (tw_addr),  //  i
+    .tw_re  (tw_re  ),  //  o
+    .tw_im  (tw_im  )   //  o
+);
+
+//  Multiplication is bypassed when twiddle address is 0.
+always @(posedge clock) begin
+    mu_en <= (tw_addr != {LOG_N{1'b0}});
+end
+//  Set unknown value x for verification
+assign  mu_a_re = mu_en ? bf2_do_re : {WIDTH{1'bx}};
+assign  mu_a_im = mu_en ? bf2_do_im : {WIDTH{1'bx}};
+
+Multiply #(.WIDTH(WIDTH)) MU (
+    .a_re   (mu_a_re),  //  i
+    .a_im   (mu_a_im),  //  i
+    .b_re   (tw_re  ),  //  i
+    .b_im   (tw_im  ),  //  i
+    .m_re   (mu_m_re),  //  o
+    .m_im   (mu_m_im)   //  o
+);
+
+always @(posedge clock) begin
+    mu_do_re <= mu_en ? mu_m_re : bf2_do_re;
+    mu_do_im <= mu_en ? mu_m_im : bf2_do_im;
+end
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        mu_do_en <= 1'b0;
+    end else begin
+        mu_do_en <= bf2_do_en;
+    end
+end
+
+//  No multiplication required at final stage
+assign  do_en = (LOG_M == 2) ? bf2_do_en : mu_do_en;
+assign  do_re = (LOG_M == 2) ? bf2_do_re : mu_do_re;
+assign  do_im = (LOG_M == 2) ? bf2_do_im : mu_do_im;
+
+endmodule

hardware/system/SdfUnit2.v

+//----------------------------------------------------------------------
+//  SdfUnit2: Radix-2 SDF Dedicated for Twiddle Resolution M = 2
+//----------------------------------------------------------------------
+module SdfUnit2 #(
+    parameter   WIDTH = 16, //  Data Bit Length
+    parameter   BF_RH = 0   //  Butterfly Round Half Up
+)(
+    input                   clock,  //  Master Clock
+    input                   reset,  //  Active High Asynchronous Reset
+    input                   di_en,  //  Input Data Enable
+    input       [WIDTH-1:0] di_re,  //  Input Data (Real)
+    input       [WIDTH-1:0] di_im,  //  Input Data (Imag)
+    output  reg             do_en,  //  Output Data Enable
+    output  reg [WIDTH-1:0] do_re,  //  Output Data (Real)
+    output  reg [WIDTH-1:0] do_im   //  Output Data (Imag)
+);
+
+//----------------------------------------------------------------------
+//  Internal Regs and Nets
+//----------------------------------------------------------------------
+reg             bf_en;      //  Butterfly Add/Sub Enable
+wire[WIDTH-1:0] x0_re;      //  Data #0 to Butterfly (Real)
+wire[WIDTH-1:0] x0_im;      //  Data #0 to Butterfly (Imag)
+wire[WIDTH-1:0] x1_re;      //  Data #1 to Butterfly (Real)
+wire[WIDTH-1:0] x1_im;      //  Data #1 to Butterfly (Imag)
+wire[WIDTH-1:0] y0_re;      //  Data #0 from Butterfly (Real)
+wire[WIDTH-1:0] y0_im;      //  Data #0 from Butterfly (Imag)
+wire[WIDTH-1:0] y1_re;      //  Data #1 from Butterfly (Real)
+wire[WIDTH-1:0] y1_im;      //  Data #1 from Butterfly (Imag)
+wire[WIDTH-1:0] db_di_re;   //  Data to DelayBuffer (Real)
+wire[WIDTH-1:0] db_di_im;   //  Data to DelayBuffer (Imag)
+wire[WIDTH-1:0] db_do_re;   //  Data from DelayBuffer (Real)
+wire[WIDTH-1:0] db_do_im;   //  Data from DelayBuffer (Imag)
+wire[WIDTH-1:0] bf_sp_re;   //  Single-Path Data Output (Real)
+wire[WIDTH-1:0] bf_sp_im;   //  Single-Path Data Output (Imag)
+reg             bf_sp_en;   //  Single-Path Data Enable
+
+//----------------------------------------------------------------------
+//  Butterfly Add/Sub
+//----------------------------------------------------------------------
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf_en <= 1'b0;
+    end else begin
+        bf_en <= di_en ? ~bf_en : 1'b0;
+    end
+end
+
+//  Set unknown value x for verification
+assign  x0_re = bf_en ? db_do_re : {WIDTH{1'bx}};
+assign  x0_im = bf_en ? db_do_im : {WIDTH{1'bx}};
+assign  x1_re = bf_en ? di_re : {WIDTH{1'bx}};
+assign  x1_im = bf_en ? di_im : {WIDTH{1'bx}};
+
+Butterfly #(.WIDTH(WIDTH),.RH(BF_RH)) BF (
+    .x0_re  (x0_re  ),  //  i
+    .x0_im  (x0_im  ),  //  i
+    .x1_re  (x1_re  ),  //  i
+    .x1_im  (x1_im  ),  //  i
+    .y0_re  (y0_re  ),  //  o
+    .y0_im  (y0_im  ),  //  o
+    .y1_re  (y1_re  ),  //  o
+    .y1_im  (y1_im  )   //  o
+);
+
+DelayBuffer #(.DEPTH(1),.WIDTH(WIDTH)) DB (
+    .clock  (clock      ),  //  i
+    .di_re  (db_di_re   ),  //  i
+    .di_im  (db_di_im   ),  //  i
+    .do_re  (db_do_re   ),  //  o
+    .do_im  (db_do_im   )   //  o
+);
+
+assign  db_di_re = bf_en ? y1_re : di_re;
+assign  db_di_im = bf_en ? y1_im : di_im;
+assign  bf_sp_re = bf_en ? y0_re : db_do_re;
+assign  bf_sp_im = bf_en ? y0_im : db_do_im;
+
+always @(posedge clock or posedge reset) begin
+    if (reset) begin
+        bf_sp_en <= 1'b0;
+        do_en <= 1'b0;
+    end else begin
+        bf_sp_en <= di_en;
+        do_en <= bf_sp_en;
+    end
+end
+
+always @(posedge clock) begin
+    do_re <= bf_sp_re;
+    do_im <= bf_sp_im;
+end
+
+endmodule

hardware/system/avalon_slave.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+package avalon_slave is
+
+    type State is (
+        SLAVE_IDLE,
+        SLAVE_READ,
+        SLAVE_READ_DATA,
+        SLAVE_WRITE
+    );
+
+    type Request is record
+        address : std_logic_vector( 3 downto 0 );
+        read : std_logic;
+        write : std_logic;
+        writedata : std_logic_vector( 31 downto 0 );
+    end record Request;
+
+    type Response is record
+        readdata : std_logic_vector( 31 downto 0 );
+    end record Response;
+
+end package avalon_slave;

hardware/system/avalon_slave_transitions.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.avalon_slave.all;
+
+entity avalon_slave_transitions is
+    generic (
+        REG_COUNT : natural;
+        REG_ACCESS_TYPES : work.reg32.AccessArray
+    );
+    port (
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        write : in std_logic;
+
+        current_state : in work.avalon_slave.State;
+        next_state : out work.avalon_slave.State;
+        reg_index : out integer range  0 to REG_COUNT - 1
+    );
+end entity avalon_slave_transitions;
+
+architecture rtl of avalon_slave_transitions is
+
+    signal is_access : boolean;
+    signal is_read : boolean;
+    signal is_write : boolean;
+    signal address_index : integer range 0 to 2 ** address'high - 1;
+    signal is_valid_reg_index : boolean;
+    signal access_type : work.reg32.AccessType;
+    signal is_valid_access : boolean;
+    signal is_valid_access_type : boolean;
+    signal index : integer range  0 to REG_COUNT - 1;
+
+begin
+
+    c_is_access: is_access <= ( read or write ) = '1';
+    c_is_read: is_read <= read = '1';
+    c_is_write: is_write <= write = '1' and not is_read;
+
+    c_address_index: address_index <= to_integer( unsigned( address ) );
+
+    c_is_valid_reg_index: is_valid_reg_index <= address_index <= ( REG_COUNT - 1 );
+
+    c_index: index <= address_index when is_valid_reg_index else 0;
+    c_reg_index: reg_index <= index;
+
+    c_access_type: access_type <= REG_ACCESS_TYPES( index );
+
+    c_is_valid_access_type: is_valid_access_type <= true when
+        ( is_read and work.reg32.allows_read( access_type ) ) or
+        ( is_write and work.reg32.allows_write( access_type ) )
+        else false;
+
+    c_is_valid_access: is_valid_access <= is_access and is_valid_reg_index and
+        is_valid_access_type;
+
+    transition : process( all ) is
+    begin
+        case current_state is
+        when SLAVE_IDLE =>
+            if ( is_valid_access and is_read ) then
+                next_state <= SLAVE_READ;
+            elsif ( is_valid_access and is_write ) then
+                next_state <= SLAVE_WRITE;
+            else
+                next_state <= SLAVE_IDLE;
+            end if;
+
+        when SLAVE_READ =>
+            next_state <= SLAVE_READ_DATA;
+
+        when SLAVE_READ_DATA =>
+            if ( is_valid_access and is_read ) then
+                next_state <= SLAVE_READ;
+            elsif ( is_valid_access and is_write ) then
+                next_state <= SLAVE_WRITE;
+            else
+                next_state <= SLAVE_IDLE;
+            end if;
+
+        when SLAVE_WRITE =>
+            next_state <= SLAVE_IDLE;
+        end case;
+    end process transition;
+
+end architecture rtl;

hardware/system/cordic.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+    use ieee.math_real.all;
+
+library work;
+    use work.cordic_pkg.all;
+
+entity cordic is
+  generic (
+    SIZE       : positive;
+    ITERATIONS : positive;
+    RESET_ACTIVE_LEVEL : std_ulogic := '1'
+  );
+  port (
+    Clock : in std_ulogic;
+    Reset : in std_ulogic;
+
+    Data_valid   : in std_ulogic;  --# Load new input data
+    Busy         : out std_ulogic; --# Generating new result
+    Result_valid : out std_ulogic; --# Flag when result is valid
+    Mode         : in cordic_mode; --# Rotation or vector mode selection
+
+    X : in signed(SIZE-1 downto 0);
+    Y : in signed(SIZE-1 downto 0);
+    Z : in signed(SIZE-1 downto 0);
+
+    X_result : out signed(SIZE-1 downto 0);
+    Y_result : out signed(SIZE-1 downto 0);
+    Z_result : out signed(SIZE-1 downto 0)
+  );
+end entity;
+
+architecture rtl of cordic is
+  type signed_array is array (natural range <>) of signed(SIZE-1 downto 0);
+
+  function gen_atan_table(s : positive) return signed_array is
+    variable table : signed_array(0 to ITERATIONS-1);
+  begin
+    for i in table'range loop
+      table(i) := to_signed(integer(arctan(2.0**(-i)) * 2.0**s / MATH_2_PI), s);
+    end loop;
+
+    return table;
+  end function;
+
+  constant ATAN_TABLE : signed_array(0 to ITERATIONS-1) := gen_atan_table(SIZE);
+
+  signal xr : signed(X'range);
+  signal yr : signed(Y'range);
+  signal zr : signed(Z'range);
+
+  signal x_shift : signed(X'range);
+  signal y_shift : signed(Y'range);
+
+  subtype iter_count is integer range 0 to ITERATIONS;
+
+  signal cur_iter : iter_count;
+begin
+
+  p_cordic: process(Clock, Reset) is
+    variable negative : boolean;
+  begin
+    if Reset = RESET_ACTIVE_LEVEL then
+      xr <= (others => '0');
+      yr <= (others => '0');
+      zr <= (others => '0');
+      cur_iter <= 0;
+      Result_valid <= '0';
+      Busy <= '0';
+    elsif rising_edge(Clock) then
+      if Data_valid = '1' then
+        xr <= X;
+        yr <= Y;
+        zr <= Z;
+        cur_iter <= 0;
+        Result_valid <= '0';
+        Busy <= '1';
+      else
+        if cur_iter /= ITERATIONS then
+        --if cur_iter(ITERATIONS) /= '1' then
+          if Mode = cordic_rotate then
+            negative := zr(z'high) = '1';
+          else
+            negative := yr(y'high) = '0';
+          end if;
+
+          --if zr(z'high) = '1' then -- z or y is negative
+          if negative then
+            xr <= xr + y_shift; --(yr / 2**(cur_iter));
+            yr <= yr - x_shift; --(xr / 2**(cur_iter));
+            zr <= zr + ATAN_TABLE(cur_iter);
+          else -- z or y is positive
+            xr <= xr - y_shift; --(yr / 2**(cur_iter));
+            yr <= yr + x_shift; --(xr / 2**(cur_iter));
+            zr <= zr - ATAN_TABLE(cur_iter);
+          end if;
+
+          cur_iter <= cur_iter + 1;
+          --cur_iter <= '0' & cur_iter(0 to ITERATIONS-1);
+        end if;
+
+        if cur_iter = ITERATIONS-1 then
+          Result_valid <= '1';
+          Busy <= '0';
+        end if;
+      end if;
+
+    end if;
+  end process;
+
+  x_shift <= shift_right(xr, cur_iter);
+  y_shift <= shift_right(yr, cur_iter);
+
+
+  X_result <= xr;
+  Y_result <= yr;
+  Z_result <= zr;
+
+end architecture;

hardware/system/cordic_pkg.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+    use ieee.math_real.all;
+
+package cordic_pkg is
+  type cordic_mode is (cordic_rotate, cordic_vector);
+
+  function cordic_gain(Iterations : positive) return real;
+
+  procedure adjust_angle(x, y, z : in signed; signal xa, ya, za : out signed);
+end package cordic_pkg;
+
+package body cordic_pkg is
+  function cordic_gain(iterations : positive) return real is
+    variable g : real := 1.0;
+  begin
+    for i in 0 to iterations-1 loop
+      g := g * sqrt(1.0 + 2.0**(-2*i));
+    end loop;
+    return g;
+  end function;
+
+  procedure adjust_angle(x, y, z : in signed; signal xa, ya, za : out signed) is
+    variable quad : unsigned(1 downto 0);
+    variable zp : signed(z'length-1 downto 0) := z;
+    variable yp : signed(y'length-1 downto 0) := y;
+    variable xp : signed(x'length-1 downto 0) := x;
+  begin
+
+    -- 0-based quadrant number of angle
+    quad := unsigned(zp(zp'high downto zp'high-1));
+
+    if quad = 1 or quad = 2 then -- Rotate into quadrant 0 and 3 (right half of plane)
+      xp := -xp;
+      yp := -yp;
+      -- Add 180 degrees (flip the sign bit)
+      zp := (not zp(zp'left)) & zp(zp'left-1 downto 0);
+    end if;
+
+    xa <= xp;
+    ya <= yp;
+    za <= zp;
+  end procedure;
+end package body cordic_pkg;

hardware/system/data_channel.cmp.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity data_channel is
+    generic (
+        DEPTH : positive := 1024
+    );
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        ctrl_address : in std_logic_vector( 3 downto 0 );
+        ctrl_read : in std_logic;
+        ctrl_readdata : out std_logic_vector( 31 downto 0 );
+        ctrl_write : in std_logic;
+        ctrl_writedata : in std_logic_vector( 31 downto 0 );
+
+        hw_sink_write : in std_logic;
+        hw_sink_writedata : in std_logic_vector( 31 downto 0 );
+
+        hw_source_read : in std_logic;
+        hw_source_readdata : out std_logic_vector( 31 downto 0 )
+    );
+end entity data_channel;
+

hardware/system/data_channel.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity data_channel is
+    generic (
+        DEPTH : positive := 1024
+    );
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        ctrl_address : in std_logic_vector( 3 downto 0 );
+        ctrl_read : in std_logic;
+        ctrl_readdata : out std_logic_vector( 31 downto 0 );
+        ctrl_write : in std_logic;
+        ctrl_writedata : in std_logic_vector( 31 downto 0 );
+
+        hw_sink_write : in std_logic;
+        hw_sink_writedata : in std_logic_vector( 31 downto 0 );
+
+        hw_source_read : in std_logic;
+        hw_source_readdata : out std_logic_vector( 31 downto 0 )
+    );
+end entity data_channel;
+
+architecture struct of data_channel is
+
+    signal sink_config : std_logic;
+    signal source_config : std_logic;
+
+    signal clear : std_logic;
+    signal empty : std_logic;
+    signal full : std_logic;
+    signal level : std_logic_vector( 9 downto 0 );
+
+    signal ctrl_sink_write : std_logic;
+    signal ctrl_sink_writedata : std_logic_vector( 31 downto 0 );
+
+    signal ctrl_source_read : std_logic;
+    signal ctrl_source_readdata : std_logic_vector( 31 downto 0 );
+
+    signal sink_write : std_logic;
+    signal sink_writedata : std_logic_vector( 31 downto 0 );
+
+    signal source_read : std_logic;
+    signal source_readdata : std_logic_vector( 31 downto 0 );
+
+begin
+
+    u_control : entity work.data_channel_control
+        port map (
+            clk => clk,
+            reset => reset,
+
+            address => ctrl_address,
+            read => ctrl_read,
+            readdata => ctrl_readdata,
+            write => ctrl_write,
+            writedata => ctrl_writedata,
+
+            sink_config => sink_config,
+            source_config => source_config,
+
+            clear => clear,
+            empty => empty,
+            full => full,
+            level => level,
+
+            sink_write => ctrl_sink_write,
+            sink_writedata => ctrl_sink_writedata,
+
+            source_read => ctrl_source_read,
+            source_readdata => ctrl_source_readdata
+        );
+
+    u_data_sink_mux : entity work.data_sink_mux
+        port map (
+            sel => sink_config,
+
+            sw_write => ctrl_sink_write,
+            sw_writedata => ctrl_sink_writedata,
+
+            hw_write => hw_sink_write,
+            hw_writedata => hw_sink_writedata,
+
+            write => sink_write,
+            writedata => sink_writedata
+        );
+
+    u_fifo : entity work.fifo
+        generic map (
+            DEPTH => DEPTH
+        )
+        port map (
+            aclr => reset,
+            clock => clk,
+            sclr => clear,
+            data => sink_writedata,
+            rdreq => source_read,
+            wrreq => sink_write,
+            empty => empty,
+            full => full,
+            q => source_readdata,
+            usedw => level
+        );
+
+    u_data_source_mux : entity work.data_source_mux
+        port map (
+            sel => source_config,
+
+            sw_read => ctrl_source_read,
+            sw_readdata => ctrl_source_readdata,
+
+            hw_read => hw_source_read,
+            hw_readdata => hw_source_readdata,
+
+            read => source_read,
+            readdata => source_readdata
+        );
+
+end architecture;

hardware/system/data_channel_control.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.avalon_slave.all;
+
+entity data_channel_control is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        sink_config : out std_logic;
+        source_config : out std_logic;
+
+        clear : out std_logic;
+        empty : in std_logic;
+        full : in std_logic;
+        level : in std_logic_vector( 9 downto 0 );
+
+        sink_write : out std_logic;
+        sink_writedata : out std_logic_vector( 31 downto 0 );
+
+        source_read : out std_logic;
+        source_readdata : in std_logic_vector( 31 downto 0 )
+    );
+end entity data_channel_control;
+
+architecture rtl of data_channel_control is
+
+    type Registers is (
+        REG_CONFIG,
+        REG_EMPTY,
+        REG_FULL,
+        REG_LEVEL,
+        REG_SINK,
+        REG_SOURCE,
+        REG_CLEAR
+    );
+
+    constant REG_CONFIG_POS : natural := Registers'pos( REG_CONFIG );
+    constant REG_EMPTY_POS : natural := Registers'pos( REG_EMPTY );
+    constant REG_FULL_POS : natural := Registers'pos( REG_FULL );
+    constant REG_LEVEL_POS : natural := Registers'pos( REG_LEVEL );
+    constant REG_SINK_POS : natural := Registers'pos( REG_SINK );
+    constant REG_SOURCE_POS : natural := Registers'pos( REG_SOURCE );
+    constant REG_CLEAR_POS : natural := Registers'pos( REG_CLEAR );
+
+    constant REG_COUNT : natural := registers'pos( registers'right ) + 1;
+
+    constant REG_ACCESS_TYPES : work.reg32.AccessArray( 0 to REG_COUNT - 1 ) := (
+        READ_WRITE,
+        READ_ONLY,
+        READ_ONLY,
+        READ_ONLY,
+        WRITE_ONLY,
+        READ_ONLY,
+        WRITE_ONLY
+    );
+
+    signal reg_index : integer range  0 to REG_COUNT - 1;
+
+    -- Internal registers
+    signal current_state : work.avalon_slave.State;
+    signal next_state : work.avalon_slave.State;
+    signal reg_data : RegArray( 0 to REG_COUNT - 1 );
+    signal fifo_read_req : std_logic;
+
+begin
+
+    u_avalon_slave_transitions: entity work.avalon_slave_transitions
+        generic map (
+            REG_COUNT => REG_COUNT,
+            REG_ACCESS_TYPES => REG_ACCESS_TYPES
+        )
+        port map (
+            address => address,
+            read => read,
+            write => write,
+
+            current_state => current_state,
+            next_state => next_state,
+            reg_index => reg_index
+        );
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_state <= SLAVE_IDLE;
+            reg_data( REG_CONFIG_POS ) <= ( others => '0' );
+            fifo_read_req <= '0';
+            clear <= '0';
+
+        elsif ( rising_edge( clk ) ) then
+            current_state <= next_state;
+            sink_write <= '0';
+            source_read <= '0';
+            clear <= '0';
+
+            case next_state is
+            when SLAVE_IDLE =>
+                null;
+
+            when SLAVE_READ =>
+                readdata <= ( others => '0' );
+                if ( reg_index = REG_CONFIG_POS ) then
+                    readdata( 1 downto 0 ) <= reg_data( reg_index )( 1 downto 0 );
+                elsif ( reg_index = REG_EMPTY_POS ) then
+                    readdata( 0 ) <= reg_data( reg_index )( 0 );
+                elsif ( reg_index = REG_FULL_POS ) then
+                    readdata( 0 ) <= reg_data( reg_index )( 0 );
+                elsif ( reg_index = REG_LEVEL_POS ) then
+                    readdata( 9 downto 0 ) <= reg_data( reg_index )( 9 downto 0 );
+                elsif ( reg_index = REG_SINK_POS ) then
+                    readdata <= reg_data( reg_index );
+                elsif ( reg_index = REG_SOURCE_POS ) then
+                    readdata <= source_readdata;
+                    source_read <= '1';
+                end if;
+            when SLAVE_READ_DATA =>
+                null;
+
+            when SLAVE_WRITE =>
+                if ( reg_index = REG_SINK_POS ) then
+                    sink_write <= '1';
+                    sink_writedata <= writedata;
+                elsif ( reg_index = REG_CLEAR_POS ) then
+                    clear <= '1';
+                else
+                    reg_data( reg_index ) <= writedata;
+                end if;
+            end case;
+
+            reg_data( REG_EMPTY_POS )( 0 ) <= empty;
+            reg_data( REG_FULL_POS )( 0 ) <= full;
+            reg_data( REG_LEVEL_POS )( level'left downto level'right ) <= level;
+        end if;
+    end process sync;
+
+    sink_config <= reg_data( REG_CONFIG_POS )( 0 );
+    source_config <= reg_data( REG_CONFIG_POS )( 1 );
+
+end architecture rtl;
+

hardware/system/data_channel_hw.tcl

+# TCL File Generated by Component Editor 20.1
+# Tue Jun 14 23:19:06 CEST 2022
+# DO NOT MODIFY
+
+
+# 
+# data_channel "data_channel" v1.0
+# Johannes Kutning 2022.06.14.23:19:06
+# A data channel between two tasks
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module data_channel
+# 
+set_module_property DESCRIPTION "A data channel between two tasks"
+set_module_property NAME data_channel
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP signal_processing
+set_module_property AUTHOR "Johannes Kutning"
+set_module_property DISPLAY_NAME data_channel
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL data_channel
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file data_channel.vhd VHDL PATH data_channel.vhd TOP_LEVEL_FILE
+
+add_fileset SIM_VHDL SIM_VHDL "" ""
+set_fileset_property SIM_VHDL TOP_LEVEL data_channel
+set_fileset_property SIM_VHDL ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property SIM_VHDL ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file data_channel.vhd VHDL PATH data_channel.vhd
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point ctrl
+# 
+add_interface ctrl avalon end
+set_interface_property ctrl addressUnits WORDS
+set_interface_property ctrl associatedClock clock
+set_interface_property ctrl associatedReset reset
+set_interface_property ctrl bitsPerSymbol 8
+set_interface_property ctrl burstOnBurstBoundariesOnly false
+set_interface_property ctrl burstcountUnits WORDS
+set_interface_property ctrl explicitAddressSpan 0
+set_interface_property ctrl holdTime 0
+set_interface_property ctrl linewrapBursts false
+set_interface_property ctrl maximumPendingReadTransactions 0
+set_interface_property ctrl maximumPendingWriteTransactions 0
+set_interface_property ctrl readLatency 0
+set_interface_property ctrl readWaitTime 1
+set_interface_property ctrl setupTime 0
+set_interface_property ctrl timingUnits Cycles
+set_interface_property ctrl writeWaitTime 0
+set_interface_property ctrl ENABLED true
+set_interface_property ctrl EXPORT_OF ""
+set_interface_property ctrl PORT_NAME_MAP ""
+set_interface_property ctrl CMSIS_SVD_VARIABLES ""
+set_interface_property ctrl SVD_ADDRESS_GROUP ""
+
+add_interface_port ctrl ctrl_address address Input 4
+add_interface_port ctrl ctrl_read read Input 1
+add_interface_port ctrl ctrl_readdata readdata Output 32
+add_interface_port ctrl ctrl_write write Input 1
+add_interface_port ctrl ctrl_writedata writedata Input 32
+set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
+set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point hw_sink
+# 
+add_interface hw_sink avalon end
+set_interface_property hw_sink addressUnits WORDS
+set_interface_property hw_sink associatedClock clock
+set_interface_property hw_sink associatedReset reset
+set_interface_property hw_sink bitsPerSymbol 8
+set_interface_property hw_sink burstOnBurstBoundariesOnly false
+set_interface_property hw_sink burstcountUnits WORDS
+set_interface_property hw_sink explicitAddressSpan 0
+set_interface_property hw_sink holdTime 0
+set_interface_property hw_sink linewrapBursts false
+set_interface_property hw_sink maximumPendingReadTransactions 0
+set_interface_property hw_sink maximumPendingWriteTransactions 0
+set_interface_property hw_sink readLatency 0
+set_interface_property hw_sink readWaitTime 1
+set_interface_property hw_sink setupTime 0
+set_interface_property hw_sink timingUnits Cycles
+set_interface_property hw_sink writeWaitTime 0
+set_interface_property hw_sink ENABLED true
+set_interface_property hw_sink EXPORT_OF ""
+set_interface_property hw_sink PORT_NAME_MAP ""
+set_interface_property hw_sink CMSIS_SVD_VARIABLES ""
+set_interface_property hw_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port hw_sink hw_sink_write write Input 1
+add_interface_port hw_sink hw_sink_writedata writedata Input 32
+set_interface_assignment hw_sink embeddedsw.configuration.isFlash 0
+set_interface_assignment hw_sink embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment hw_sink embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment hw_sink embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point hw_source
+# 
+add_interface hw_source avalon end
+set_interface_property hw_source addressUnits WORDS
+set_interface_property hw_source associatedClock clock
+set_interface_property hw_source associatedReset reset
+set_interface_property hw_source bitsPerSymbol 8
+set_interface_property hw_source burstOnBurstBoundariesOnly false
+set_interface_property hw_source burstcountUnits WORDS
+set_interface_property hw_source explicitAddressSpan 0
+set_interface_property hw_source holdTime 0
+set_interface_property hw_source linewrapBursts false
+set_interface_property hw_source maximumPendingReadTransactions 0
+set_interface_property hw_source maximumPendingWriteTransactions 0
+set_interface_property hw_source readLatency 0
+set_interface_property hw_source readWaitTime 1
+set_interface_property hw_source setupTime 0
+set_interface_property hw_source timingUnits Cycles
+set_interface_property hw_source writeWaitTime 0
+set_interface_property hw_source ENABLED true
+set_interface_property hw_source EXPORT_OF ""
+set_interface_property hw_source PORT_NAME_MAP ""
+set_interface_property hw_source CMSIS_SVD_VARIABLES ""
+set_interface_property hw_source SVD_ADDRESS_GROUP ""
+
+add_interface_port hw_source hw_source_read read Input 1
+add_interface_port hw_source hw_source_readdata readdata Output 32
+set_interface_assignment hw_source embeddedsw.configuration.isFlash 0
+set_interface_assignment hw_source embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment hw_source embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment hw_source embeddedsw.configuration.isPrintableDevice 0
+

hardware/system/data_sink_mux.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity data_sink_mux is
+    port (
+        sel : in std_logic;
+
+        sw_write : in std_logic;
+        sw_writedata : in std_logic_vector( 31 downto 0 );
+
+        hw_write : in std_logic;
+        hw_writedata : in std_logic_vector( 31 downto 0 );
+
+        write : out std_logic;
+        writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity data_sink_mux;
+
+architecture rtl of data_sink_mux is
+begin
+    write <= sw_write when sel = '0' else hw_write;
+
+    writedata <= sw_writedata when sel = '0' else
+        hw_writedata;
+
+end architecture rtl;

hardware/system/data_source_mux.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity data_source_mux is
+    port (
+        sel : in std_logic;
+
+        sw_read : in std_logic;
+        sw_readdata : out std_logic_vector( 31 downto 0 );
+
+        hw_read : in std_logic;
+        hw_readdata : out std_logic_vector( 31 downto 0 );
+
+        read : out std_logic;
+        readdata : in std_logic_vector( 31 downto 0 )
+    );
+end entity data_source_mux;
+
+architecture rtl of data_source_mux is
+begin
+    read <= sw_read when sel = '0' else hw_read;
+
+    sw_readdata <= readdata;
+    hw_readdata <= readdata;
+
+end architecture rtl;

hardware/system/fft_magnitude_calc.vhd

+------------------------------------------------------------------------
+-- fft_magnitude_calc
+--
+-- calculation of FFT magnitude sqrt(real_part²+im_part²)
+-- Inputs:
+-- input_re in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
+-- input_im in: +-1 signed Fixpoint (0.5=0x40000000, -0.5=0xC0000000 (negative numbers in 2K)
+-- input_valid: high = inputs are valid for data processing 
+-- Outputs
+-- output_magnitude: Fixpoint 0.5=0x40000000 (always positive)
+-- output_valid:     high = magnitude data is valid
+-----------------------------------------------------------------------
+
+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.task.all;
+	 use work.float.all;
+
+entity fft_magnitude_calc is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+		  
+        input_valid: in std_logic;		  
+        input_re : in std_logic_vector( 31 downto 0 ); -- in Fixpoint
+		  input_im : in std_logic_vector( 31 downto 0 ); -- in Fixpoint
+		  
+        output_valid : out std_logic;
+        output_magnitude : out std_logic_vector( 31 downto 0 )
+    );
+end entity fft_magnitude_calc;
+
+architecture rtl of fft_magnitude_calc is
+
+    subtype Word_64 is std_logic_vector( 63 downto 0 );
+    type Array_64 is array ( natural range <> ) of Word_64;
+
+    subtype Word_32 is std_logic_vector( 31 downto 0 );
+    type Array_32 is array ( natural range <> ) of Word_32;
+
+    subtype Word_16 is std_logic_vector( 15 downto 0 );
+    type Array_16 is array ( natural range <> ) of Word_16;
+ 
+    signal input_valid_stage1 : std_logic;
+    signal re_multiply_re_stage1 : signed(63 downto 0);
+	 signal im_multiply_re_stage1 : signed(63 downto 0);
+	  
+	 signal input_valid_stage2 : std_logic;
+    signal re2_add_im2 : signed(63 downto 0);
+	 
+	 signal input_valid_stage3 : std_logic;
+    signal input_sqrt : Array_32( 0 to 16 );
+	 signal output_sqrt:  Array_16( 0 to 16 );
+	 
+	 signal output_delay_sqrt: std_logic_vector(15 downto 0);	
+	 
+	 signal data_memory : work.reg32.RegArray( 0 to 1023 );
+	 signal index_sqrt : integer range 0 to 16;	 
+	  
+begin
+
+
+    -- calculation of real_part² and im_part²
+	 p_pow2_stage1: process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            input_valid_stage1 <= '0'; 
+				re_multiply_re_stage1 <= (others => '0');
+				im_multiply_re_stage1 <= (others => '0');
+        elsif ( rising_edge( clk ) ) then
+		      input_valid_stage1 <= input_valid;		
+		      if input_valid = '1' then		
+				    re_multiply_re_stage1 <= signed(input_re) * signed(input_re);
+				    im_multiply_re_stage1 <= signed(input_im) * signed(input_im);
+				end if;
+        end if;
+    end process p_pow2_stage1;
+
+	 -- calculation of real_part²*+im_part²
+    p_add_stage2: process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            input_valid_stage2 <= '0'; 
+				re2_add_im2 <= (others => '0');
+        elsif ( rising_edge( clk ) ) then
+		      input_valid_stage2 <= input_valid_stage1;
+            re2_add_im2 <= re_multiply_re_stage1 + im_multiply_re_stage1;
+        end if;
+    end process p_add_stage2;
+	 
+	 -- calculation of sqrt (one sqrt caluation needs 16 clks with G_DATA_W => 32 
+    -- for continous stream 17 sqrt instances are needed	 
+	 p_sqrt_stage3: process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            input_valid_stage3 <= '0'; 
+				index_sqrt <= 0;
+				input_sqrt(0) <= (others => '0');
+				input_sqrt(1) <= (others => '0');
+				input_sqrt(2) <= (others => '0');
+				input_sqrt(3) <= (others => '0');
+				input_sqrt(4) <= (others => '0');
+				input_sqrt(5) <= (others => '0');
+				input_sqrt(6) <= (others => '0');
+				input_sqrt(7) <= (others => '0');
+				input_sqrt(8) <= (others => '0');
+				input_sqrt(9) <= (others => '0');
+				input_sqrt(10) <= (others => '0');
+				input_sqrt(11) <= (others => '0');
+				input_sqrt(12) <= (others => '0');
+				input_sqrt(13) <= (others => '0');
+				input_sqrt(14) <= (others => '0');
+				input_sqrt(15) <= (others => '0');
+            input_sqrt(16) <= (others => '0');
+        elsif ( rising_edge( clk ) ) then
+		      input_valid_stage3 <= input_valid_stage2;	
+			   if input_valid_stage2 = '1' then	
+					if index_sqrt = 16 then
+						 index_sqrt	<= 0;
+					else
+						 index_sqrt <= index_sqrt +1;
+					end if;				
+				end if;
+				 case index_sqrt is
+              when 16 => input_sqrt(16) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 15 => input_sqrt(15) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 14 => input_sqrt(14) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 13 => input_sqrt(13) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 12 => input_sqrt(12) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 11 => input_sqrt(11) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 10 => input_sqrt(10) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 9 => input_sqrt(9) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 8 => input_sqrt(8) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 7 => input_sqrt(7) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 6 => input_sqrt(6) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 5 => input_sqrt(5) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 4 => input_sqrt(4) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 3 => input_sqrt(3) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 2 => input_sqrt(2) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 1 => input_sqrt(1) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when 0 => input_sqrt(0) <= std_logic_vector(re2_add_im2(63 downto 32));
+				  when others => null;
+				  end case;
+        end if;
+    end process p_sqrt_stage3;
+	
+	 -- generate sqrt instances for continous data stream	 
+	gen_sqrt_array: for i in 0 to 16 generate		
+	sqrt_module : entity work.squareRoot_pipe
+		  generic map (
+            G_DATA_W => 32
+        )
+        port map (
+            clk => clk,
+            rst => reset,
+            iv_data => input_sqrt(i),
+            ov_res => output_sqrt(i)
+        );
+	end generate gen_sqrt_array;  
+		  
+    -- output assignment
+    p_output_stage4: process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            output_valid <= '0'; 
+				output_magnitude <= (others => '0');
+				output_delay_sqrt <= (others => '0');
+        elsif ( rising_edge( clk ) ) then
+		      output_delay_sqrt <= output_delay_sqrt(14 downto 0) & input_valid_stage3;
+				output_valid <= output_delay_sqrt(15);
+				output_magnitude <= std_logic_vector(output_sqrt(index_sqrt)) & x"0000";
+        end if;
+    end process p_output_stage4;
+
+	 
+end architecture rtl;
+

hardware/system/fifo.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+entity fifo is
+    generic (
+        DEPTH : positive := 1024
+    );
+    port
+    (
+        aclr : in std_logic;
+        clock : in std_logic;
+        sclr : in std_logic;
+        data : in std_logic_vector( 31 downto 0 );
+        rdreq : in std_logic;
+        wrreq : in std_logic;
+        empty : out std_logic;
+        full : out std_logic;
+        q : out std_logic_vector( 31 downto 0 );
+        usedw : out std_logic_vector( 9 downto 0 )
+    );
+end entity fifo;
+
+architecture rtl of fifo is
+
+    type Operation is (
+        OPERATION_IDLE,
+        OPERATION_CLEAR,
+        OPERATION_READ,
+        OPERATION_WRITE,
+        OPERATION_READ_WRITE
+    );
+
+    signal is_empty : boolean;
+    signal is_full : boolean;
+
+    signal is_read : boolean;
+    signal is_write : boolean;
+    signal is_read_write : boolean;
+
+    signal next_operation : Operation;
+
+    signal fifo_data : work.reg32.RegArray( 0 to DEPTH - 1 );
+
+    signal write_index : integer range 0 to DEPTH - 1;
+    signal read_index : integer range 0 to DEPTH - 1;
+    signal item_count : integer range 0 to DEPTH;
+
+    function increment_with_overflow( value : integer; max : integer ) return integer
+    is
+    begin
+        if ( value < max - 1 ) then
+            return value + 1;
+        end if;
+        return 0;
+    end function increment_with_overflow;
+
+begin
+
+    c_is_empty: is_empty <= item_count = 0;
+    c_is_full: is_full <= item_count = DEPTH;
+
+    c_is_read: is_read <= rdreq = '1' and not is_empty;
+    c_is_write: is_write <= wrreq = '1' and not is_full;
+    c_is_read_write: is_read_write <= is_read and is_write;
+
+    c_next_operation: next_operation <= OPERATION_CLEAR when sclr
+        else OPERATION_READ_WRITE when is_read_write
+        else OPERATION_READ when is_read
+        else OPERATION_WRITE when is_write
+        else OPERATION_IDLE;
+
+    sync: process( clock, aclr ) is
+    begin
+        if ( aclr = '1' ) then
+            write_index <= 0;
+            read_index <= 0;
+            item_count <= 0;
+        elsif ( rising_edge( clock ) ) then
+
+            case next_operation is
+            when OPERATION_IDLE =>
+                null;
+
+            when OPERATION_CLEAR =>
+                write_index <= 0;
+                read_index <= 0;
+                item_count <= 0;
+
+            when OPERATION_READ =>
+                item_count <= item_count - 1;
+                read_index <= increment_with_overflow( read_index, DEPTH );
+
+            when OPERATION_WRITE =>
+                fifo_data( write_index ) <= data;
+                item_count <= item_count + 1;
+                write_index <= increment_with_overflow( write_index, DEPTH );
+
+            when OPERATION_READ_WRITE =>
+                read_index <= increment_with_overflow( read_index, DEPTH );
+
+                fifo_data( write_index ) <= data;
+                write_index <= increment_with_overflow( write_index, DEPTH );
+            end case;
+
+        end if;
+    end process;
+
+    c_assign_q: q <= data when ( is_empty and is_write ) else
+        fifo_data( read_index );
+
+    c_assign_usedw:
+        usedw <= std_logic_vector( to_unsigned( item_count, usedw'length ) );
+
+    full <= '1' when is_full else '0';
+    empty <= '1' when is_empty else '0';
+end architecture rtl;
+

hardware/system/fixed_sine.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+    use ieee.math_real.all;
+
+library work;
+    use work.cordic_pkg.all;
+
+entity fixed_sine is
+    generic (
+        SIZE       : positive;   -- Width of parameters
+        ITERATIONS : positive;   -- Number of CORDIC iterations
+        FRAC_BITS  : positive;   -- Total fractional bits
+        MAGNITUDE  : real := 1.0;
+        RESET_ACTIVE_LEVEL : std_ulogic := '1'
+    );
+    port (
+        clock : in std_ulogic;
+        reset : in std_ulogic;
+        data_valid   : in std_ulogic;  --# load new input data
+        busy         : out std_ulogic; --# generating new result
+        result_valid : out std_ulogic; --# flag when result is valid
+        angle : in signed(size-1 downto 0); -- angle in brads (2**size brads = 2*pi radians)
+        sine   : out signed(size-1 downto 0)
+    );
+end entity fixed_sine;
+
+architecture rtl of fixed_sine is
+    signal xa, ya, za, x_result, y_result : signed(Angle'range);
+    signal rv_loc : std_ulogic;
+begin
+
+    adj: process(clock, reset) is
+        constant Y : signed(Angle'range) := (others => '0');
+        constant X : signed(Angle'range) := --to_signed(1, Angle'length);
+        to_signed(integer(MAGNITUDE/cordic_gain(ITERATIONS) * 2.0 ** FRAC_BITS), Angle'length);
+    begin
+        if reset = RESET_ACTIVE_LEVEL then
+            xa <= (others => '0');
+            ya <= (others => '0');
+            za <= (others => '0');
+        elsif rising_edge(clock) then
+            adjust_angle(X, Y, Angle, xa, ya, za);
+        end if;
+    end process;
+
+    c: entity work.cordic
+        generic map (
+            SIZE => SIZE,
+            ITERATIONS => ITERATIONS,
+            RESET_ACTIVE_LEVEL => RESET_ACTIVE_LEVEL
+        )
+        port map (
+            clock => clock,
+            reset => reset,
+            data_valid => data_valid,
+            result_valid => rv_loc,
+            busy => busy,
+            Mode => cordic_rotate,
+
+            X => xa,
+            Y => ya,
+            Z => za,
+
+            X_result => x_result,
+            Y_result => y_result,
+            Z_result => open
+        );
+
+    reg: process(clock, reset) is
+    begin
+        if reset = RESET_ACTIVE_LEVEL then
+            sine <= (others => '0');
+            result_valid <= '0';
+        elsif rising_edge(clock) then
+            result_valid <= rv_loc;
+
+            if rv_loc = '1' then -- Capture result
+                sine <= y_result;
+            end if;
+        end if;
+    end process;
+end architecture;

hardware/system/float.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package float is
+    constant SIGN : std_logic_vector( 31 downto 31 ) := ( others => '0' );
+    constant EXP : std_logic_vector( 30 downto 23 ) := ( others => '0' );
+    constant MANTISSA : std_logic_vector( 22 downto 0 ) := ( others => '0' );
+
+    function find_leftmost( arg : unsigned; value : std_ulogic ) return integer;
+
+    function count_leading_digits( arg : unsigned; value : std_ulogic ) return integer;
+
+    function to_float( arg : std_logic_vector ) return std_logic_vector;
+
+    function to_fixed( arg : std_logic_vector ) return std_logic_vector;
+
+end package float;
+
+package body float is
+    function find_leftmost( arg : unsigned; value : std_ulogic ) return integer is
+    begin
+        for i in arg'left downto arg'right loop
+            if ( arg( i ) = value ) then
+                return i;
+            end if;
+        end loop;
+
+        return -1;
+    end function find_leftmost;
+
+    function count_leading_digits( arg : unsigned; value : std_ulogic ) return integer is
+        variable left_most_value : integer range -1 to arg'high;
+        variable leading_values : integer range 0 to arg'high;
+    begin
+        left_most_value := find_leftmost( arg, not value );
+        leading_values := 0;
+
+        if ( left_most_value /= -1 ) then
+            leading_values := arg'high - left_most_value;
+        end if;
+
+        return leading_values;
+    end function count_leading_digits;
+
+    function to_float( arg : std_logic_vector ) return std_logic_vector is
+        variable y : std_logic_vector( 31 downto 0 );
+        variable s : std_logic;
+        variable e : unsigned( 7 downto 0 );
+        variable m : unsigned( 22 downto 0 );
+        variable value : unsigned( 30 downto 0 );
+
+        variable leading_sign_digits : integer range 0 to value'high;
+        variable reminding : integer range 0 to value'high;
+    begin
+        s := arg( 31 );
+
+        if ( s = '0' ) then
+            value := unsigned( arg( 30 downto 0 ) );
+        else
+            value := not unsigned( arg( 30 downto 0 ) );
+            value := value +1;
+        end if;
+        leading_sign_digits := count_leading_digits( value, '0' );
+        reminding := value'high - leading_sign_digits;
+        e := to_unsigned( 126 - leading_sign_digits, e'length );
+
+        if ( reminding > m'length ) then
+            m := value( reminding - 1 downto reminding - m'length );
+        elsif ( reminding > 1 ) then
+            m := ( others => '0' );
+            m( m'high downto m'high - reminding + 1 ) := value( reminding - 1 downto 0 );
+        else
+            m := ( others => '0' );
+        end if;
+
+        if (arg = x"00000000") then
+            y := (others => '0');
+        else
+            y := s & std_logic_vector( e ) & std_logic_vector( m );
+        end if;
+
+        return y;
+    end function to_float;
+
+    function to_fixed( arg : std_logic_vector ) return std_logic_vector is
+        variable y : unsigned( 31 downto 0 );
+        variable s : std_logic;
+        variable e : unsigned( 7 downto 0 );
+        variable m_index_max : integer range -127 to 128;
+
+    begin
+        s := arg( 31 );
+        e := unsigned(arg(30 downto 23));
+        m_index_max := to_integer(signed(30-(126-e)));
+
+        if (arg = x"00000000") then
+            y := (others => '0');
+        else
+            y := (others => '0');
+            case m_index_max is
+                when 30 => y(30 downto 7):= '1' & unsigned( arg(22 downto 0) );
+                when 29 => y(29 downto 6):= '1' & unsigned( arg(22 downto 0) );
+                when 28 => y(28 downto 5):= '1' & unsigned( arg(22 downto 0) );
+                when 27 => y(27 downto 4):= '1' & unsigned( arg(22 downto 0) );
+                when 26 => y(26 downto 3):= '1' & unsigned( arg(22 downto 0) );
+                when 25 => y(25 downto 2):= '1' & unsigned( arg(22 downto 0) );
+                when 24 => y(24 downto 1):= '1' & unsigned( arg(22 downto 0) );
+                when 23 => y(23 downto 0):= '1' & unsigned( arg(22 downto 0) );
+                when 22 => y(22 downto 0):= '1' & unsigned( arg(22 downto 1) );
+                when 21 => y(21 downto 0):= '1' & unsigned( arg(22 downto 2) );
+                when 20 => y(20 downto 0):= '1' & unsigned( arg(22 downto 3) );
+                when 19 => y(19 downto 0):= '1' & unsigned( arg(22 downto 4) );
+                when 18 => y(18 downto 0):= '1' & unsigned( arg(22 downto 5) );
+                when 17 => y(17 downto 0):= '1' & unsigned( arg(22 downto 6) );
+                when 16 => y(16 downto 0):= '1' & unsigned( arg(22 downto 7) );
+                when 15 => y(15 downto 0):= '1' & unsigned( arg(22 downto 8) );
+                when 14 => y(14 downto 0):= '1' & unsigned( arg(22 downto 9) );
+                when 13 => y(13 downto 0):= '1' & unsigned( arg(22 downto 10) );
+                when 12 => y(12 downto 0):= '1' & unsigned( arg(22 downto 11) );
+                when 11 => y(11 downto 0):= '1' & unsigned( arg(22 downto 12) );
+                when 10 => y(10 downto 0):= '1' & unsigned( arg(22 downto 13) );
+                when 9 => y(9 downto 0):= '1' & unsigned( arg(22 downto 14) );
+                when 8 => y(8 downto 0):= '1' & unsigned( arg(22 downto 15) );
+                when 7 => y(7 downto 0):= '1' & unsigned( arg(22 downto 16) );
+                when 6 => y(6 downto 0):= '1' & unsigned( arg(22 downto 17) );
+                when 5 => y(5 downto 0):= '1' & unsigned( arg(22 downto 18) );
+                when 4 => y(4 downto 0):= '1' & unsigned( arg(22 downto 19) );
+                when 3 => y(3 downto 0):= '1' & unsigned( arg(22 downto 20) );
+                when 2 => y(2 downto 0):= '1' & unsigned( arg(22 downto 21) );
+                when 1 => y(1 downto 0):= '1' & unsigned( arg(22 downto 22) );
+                when 0 => y(0):= '1';
+                when others => null;
+            end case;
+            if ( s = '1' ) then
+                y := not(y);
+                y:=  y + x"00000001";
+            end if;
+        end if;
+
+        return std_logic_vector( y );
+    end function to_fixed;
+
+end package body float;

hardware/system/float_add.vhd

+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+entity float_add is
+  port(A      : in  std_logic_vector(31 downto 0);
+       B      : in  std_logic_vector(31 downto 0);
+       clk    : in  std_logic;
+       reset  : in  std_logic;
+       start  : in  std_logic;
+       done   : out std_logic;
+       sum : out std_logic_vector(31 downto 0)
+       );
+end float_add;
+
+architecture mixed of float_add is
+  type ST is (WAIT_STATE, ALIGN_STATE, ADDITION_STATE, NORMALIZE_STATE, OUTPUT_STATE);
+  signal state : ST := WAIT_STATE;
+
+  ---Internal Signals latched from the inputs
+  signal A_mantissa, B_mantissa : std_logic_vector (24 downto 0);
+  signal A_exp, B_exp           : std_logic_vector (8 downto 0);
+  signal A_sgn, B_sgn           : std_logic;
+
+  --Internal signals for Output
+  signal sum_exp: std_logic_vector (8 downto 0);
+  signal sum_mantissa           : std_logic_vector (24 downto 0);
+  signal sum_sgn           : std_logic;
+
+begin
+
+  Control_Unit : process (clk, reset) is
+    variable diff : signed(8 downto 0);
+  begin
+    if(reset = '1') then
+      state <= WAIT_STATE;                 --start in wait state
+      done    <= '0';
+    elsif rising_edge(clk) then
+      case state is
+        when WAIT_STATE =>
+          if (start = '1') then            --wait till start request startes high
+            A_sgn      <= A(31);
+            A_exp      <= '0' & A(30 downto 23);	--One bit is added for signed subtraction
+            A_mantissa <= "01" & A(22 downto 0);	--Two bits are added extra, one for leading 1 and other one for storing carry
+            B_sgn      <= B(31);
+            B_exp      <= '0' & B(30 downto 23);
+            B_mantissa <= "01" & B(22 downto 0);
+            state    <= ALIGN_STATE;
+          else
+            state <= WAIT_STATE;
+          end if;
+        when ALIGN_STATE =>  --Compare exponent and align it
+          --If any num is greater by 2**24, we skip the addition.
+          if unsigned(A_exp) > unsigned(B_exp) then
+			--B needs downshifting
+            diff := signed(A_exp) - signed(B_exp);  --Small Alu
+            if diff > 23 then
+              sum_mantissa <= A_mantissa;  --B insignificant relative to A
+			  sum_exp <= A_exp;
+              sum_sgn      <= A_sgn;
+              state      <= OUTPUT_STATE;   --start latch A as output
+            else
+			  --downshift B to equilabrate B_exp to A_exp
+			  sum_exp <= A_exp;
+              B_mantissa(24-to_integer(diff) downto 0)  <= B_mantissa(24 downto to_integer(diff));
+              B_mantissa(24 downto 25-to_integer(diff)) <= (others => '0');
+              state                                   <= ADDITION_STATE;
+            end if;
+          elsif unsigned(A_exp) < unsigned(B_exp)  then   --A_exp < B_exp. A needs downshifting
+            diff := signed(B_exp) - signed(A_exp);  -- Small Alu
+            if diff > 23 then
+              sum_mantissa <= B_mantissa;  --A insignificant relative to B
+              sum_sgn      <= B_sgn;
+              sum_exp      <= B_exp;
+              state      <= OUTPUT_STATE;   --start latch B as output
+            else
+			  --downshift A to equilabrate A_exp to B_exp
+              sum_exp <= B_exp;
+              A_mantissa(24-to_integer(diff) downto 0)  <= A_mantissa(24 downto to_integer(diff));
+              A_mantissa(24 downto 25-to_integer(diff)) <= (others => '0');
+              state                                   <= ADDITION_STATE;
+            end if;
+		  else				-- Both exponent is equal. No need to mantissa shift
+		    sum_exp <= A_exp;
+            state <= ADDITION_STATE;
+          end if;
+        when ADDITION_STATE =>                    --Mantissa addition
+          state <= NORMALIZE_STATE;
+          if (A_sgn xor B_sgn) = '0' then  --signs are the same. Just add them
+            sum_mantissa <= std_logic_vector((unsigned(A_mantissa) + unsigned(B_mantissa)));	--Big Alu
+            sum_sgn      <= A_sgn;      --both nums have same sign
+          --Else subtract smaller from larger and use sign of larger
+          elsif unsigned(A_mantissa) >= unsigned(B_mantissa) then
+            sum_mantissa <= std_logic_vector((unsigned(A_mantissa) - unsigned(B_mantissa)));	--Big Alu
+            sum_sgn      <= A_sgn;
+          else
+            sum_mantissa <= std_logic_vector((unsigned(B_mantissa) - unsigned(A_mantissa)));	--Big Alu
+            sum_sgn      <= B_sgn;
+          end if;
+
+        when NORMALIZE_STATE =>  --Normalization.
+          if unsigned(sum_mantissa) = TO_UNSIGNED(0, 25) then
+			--The sum is 0
+            sum_mantissa <= (others => '0');
+            sum_exp        <= (others => '0');
+            state      <= OUTPUT_STATE;
+          elsif(sum_mantissa(24) = '1') then  --If sum overflowed we downshift and are done.
+            sum_mantissa <= '0' & sum_mantissa(24 downto 1);  --shift the 1 down
+            sum_exp        <= std_logic_vector((unsigned(sum_exp)+ 1));
+            state      <= OUTPUT_STATE;
+          elsif(sum_mantissa(23) = '0') then  --in this case we need to upshift
+			  --This iterates the normalization shifts, thus can take many clocks.
+			  sum_mantissa <= sum_mantissa(23 downto 0) & '0';
+			  sum_exp <= std_logic_vector((unsigned(sum_exp)-1));
+			  state<= NORMALIZE_STATE; --keep shifting till  leading 1 appears
+          else
+            state <= OUTPUT_STATE;  --leading 1 already there. Latch output
+          end if;
+        when OUTPUT_STATE =>
+          sum(22 downto 0)  <= sum_mantissa(22 downto 0);
+          sum(30 downto 23) <= sum_exp(7 downto 0);
+          sum(31) <= sum_sgn;
+          done              <= '1';     -- signal done
+          if (start = '0') then         -- stay in the state till request ends i.e start is low
+            done    <= '0';
+            state <= WAIT_STATE;
+          end if;
+        when others =>
+			state <= WAIT_STATE;      --Just in case.
+      end case;
+    end if;
+  end process;
+
+end mixed;

hardware/system/float_sine.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+    use ieee.math_real.all;
+
+library work;
+    use work.cordic_pkg.all;
+    use work.float.all;
+
+entity float_sine is
+    generic (
+        ITERATIONS : positive    -- Number of CORDIC iterations
+    );
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        data_valid : in std_logic;  --# load new input data
+        busy : out std_logic; --# generating new result
+        result_valid : out std_logic; --# flag when result is valid
+        angle : in signed(31 downto 0); -- angle in brads (2**size brads = 2*pi radians)
+        sine : out signed(31 downto 0)
+    );
+end entity float_sine;
+
+architecture rtl of float_sine is
+    signal fixed : signed( 31 downto 0 );
+begin
+
+    u_fixed_sine : entity work.fixed_sine
+        generic map (
+          SIZE => 32,
+          ITERATIONS => 8,
+          FRAC_BITS => 31
+        )
+        port map (
+            clock => clk,
+            reset => reset,
+
+            data_valid => data_valid,
+            busy => busy,
+            result_valid => result_valid,
+            angle => angle,
+            sine => fixed
+          );
+
+    sine <= signed( to_float( std_logic_vector( fixed ) ) );
+
+end architecture;

hardware/system/hardware_task.cmp.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity hardware_task is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        ctrl_address : in std_logic_vector( 3 downto 0 );
+        ctrl_read : in std_logic;
+        ctrl_readdata : out std_logic_vector( 31 downto 0 );
+        ctrl_write : in std_logic;
+        ctrl_writedata : in std_logic_vector( 31 downto 0 );
+
+        task_address : out std_logic_vector( 3 downto 0 );
+        task_read : out std_logic;
+        task_readdata : in std_logic_vector( 31 downto 0 );
+        task_write : out std_logic;
+        task_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity hardware_task;
+

hardware/system/hardware_task.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity hardware_task is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        ctrl_address : in std_logic_vector( 3 downto 0 );
+        ctrl_read : in std_logic;
+        ctrl_readdata : out std_logic_vector( 31 downto 0 );
+        ctrl_write : in std_logic;
+        ctrl_writedata : in std_logic_vector( 31 downto 0 );
+
+        task_address : out std_logic_vector( 3 downto 0 );
+        task_read : out std_logic;
+        task_readdata : in std_logic_vector( 31 downto 0 );
+        task_write : out std_logic;
+        task_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity hardware_task;
+
+architecture rtl of hardware_task is
+begin
+    task_address <= ctrl_address;
+    task_read <= ctrl_read;
+    ctrl_readdata <= task_readdata;
+    task_write <= ctrl_write;
+    task_writedata <= ctrl_writedata;
+end architecture rtl;
+

hardware/system/hardware_task_control.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+    use work.avalon_slave.all;
+
+entity hardware_task_control is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        task_start : out std_logic;
+        task_state : in work.task.State;
+        task_config : out work.reg32.RegArray( 0 to 2 )
+    );
+end entity hardware_task_control;
+
+architecture rtl of hardware_task_control is
+
+    type Registers is (
+        REG_START,
+        REG_STATE,
+        REG_CYCLE_COUNT,
+        REG_CONFIG_0,
+        REG_CONFIG_1,
+        REG_CONFIG_2
+    );
+
+    constant REG_START_POS : natural := Registers'pos( REG_START );
+    constant REG_STATE_POS : natural := Registers'pos( REG_STATE );
+    constant REG_CYCLE_COUNT_POS : natural := Registers'pos( REG_CYCLE_COUNT );
+    constant REG_CONFIG_0_POS : natural := Registers'pos( REG_CONFIG_0 );
+    constant REG_CONFIG_1_POS : natural := Registers'pos( REG_CONFIG_1 );
+    constant REG_CONFIG_2_POS : natural := Registers'pos( REG_CONFIG_2 );
+
+    constant REG_COUNT : natural := registers'pos( registers'right ) + 1;
+
+    constant REG_ACCESS_TYPES : work.reg32.AccessArray( 0 to REG_COUNT - 1 ) := (
+        WRITE_ONLY,
+        READ_ONLY,
+        READ_ONLY,
+        READ_WRITE,
+        READ_WRITE,
+        READ_WRITE
+    );
+
+    -- Internal control and data signals
+    signal reg_index : integer range  0 to REG_COUNT - 1;
+
+    -- Internal registers
+    signal current_state : work.avalon_slave.State;
+    signal next_state : work.avalon_slave.State;
+    signal reg_data : RegArray( 0 to REG_COUNT - 1 );
+    signal task_running : std_logic;
+
+begin
+
+    u_avalon_slave_transitions: entity work.avalon_slave_transitions
+        generic map (
+            REG_COUNT => REG_COUNT,
+            REG_ACCESS_TYPES => REG_ACCESS_TYPES
+        )
+        port map (
+            address => address,
+            read => read,
+            write => write,
+
+            current_state => current_state,
+            next_state => next_state,
+            reg_index => reg_index
+        );
+
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_state <= SLAVE_IDLE;
+            reg_data( Registers'pos( REG_CYCLE_COUNT ) ) <= ( others => '0' );
+            reg_data( Registers'pos( REG_CONFIG_0 ) ) <= ( others => '0' );
+
+        elsif ( rising_edge( clk ) ) then
+            current_state <= next_state;
+            task_start <= '0';
+
+            if ( task_state = work.task.TASK_DONE ) then
+                task_running <= '0';
+            end if;
+
+            case next_state is
+            when SLAVE_IDLE =>
+                null;
+
+            when SLAVE_READ =>
+                readdata <= ( others => '0' );
+                if ( reg_index = REG_STATE_POS ) then
+                    readdata <= to_std_logic_vector( task_state, work.reg32.word'length );
+                elsif ( reg_index = REG_CYCLE_COUNT_POS ) then
+                    readdata <= reg_data( REG_CYCLE_COUNT_POS );
+                else
+                    readdata <= reg_data( reg_index );
+                end if;
+
+            when SLAVE_READ_DATA =>
+                null;
+
+            when SLAVE_WRITE =>
+
+                if ( reg_index = REG_START_POS ) then
+                    task_start <= '1';
+                    reg_data( REG_CYCLE_COUNT_POS ) <= ( others => '0' );
+                    task_running <= '1';
+                else
+                    reg_data( reg_index ) <= writedata;
+                end if;
+
+            end case;
+
+            if ( task_running = '1' ) then
+                reg_data( REG_CYCLE_COUNT_POS ) <=
+                    std_logic_vector(
+                        unsigned(
+                            reg_data( REG_CYCLE_COUNT_POS ) ) + 1 );
+            end if;
+        end if;
+    end process sync;
+    task_config <= reg_data( REG_CONFIG_0_POS to REG_CONFIG_2_POS );
+end architecture rtl;
+

hardware/system/hardware_timestamp.cmp.vhd

+entity timer is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 )
+    );
+end entity timer;
+

hardware/system/hardware_timestamp.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.avalon_slave.all;
+
+entity timer is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 )
+    );
+end entity timer;
+
+architecture rtl of timer is
+
+    type Registers is (
+        REG_STATE,
+        REG_CYCLE_COUNT
+    );
+
+    constant REG_STATE_POS : natural := Registers'pos( REG_STATE );
+    constant REG_CYCLE_COUNT_POS : natural := Registers'pos( REG_CYCLE_COUNT );
+    constant REG_COUNT : natural := Registers'pos( Registers'right ) + 1;
+
+    constant REG_ACCESS_TYPES : work.reg32.AccessArray( 0 to REG_COUNT - 1 ) := (
+        READ_WRITE,
+        READ_ONLY
+    );
+
+    signal reg_index : integer range  0 to REG_COUNT - 1;
+
+    signal current_avalon_state : work.avalon_slave.State;
+    signal next_avalon_state : work.avalon_slave.State;
+
+    signal running : std_logic;
+    signal cycle_count : unsigned( 31 downto 0 );
+
+begin
+
+    u_avalon_slave_transitions: entity work.avalon_slave_transitions
+        generic map (
+            REG_COUNT => REG_COUNT,
+            REG_ACCESS_TYPES => REG_ACCESS_TYPES
+        )
+        port map (
+            address => address,
+            read => read,
+            write => write,
+
+            current_state => current_avalon_state,
+            next_state => next_avalon_state,
+            reg_index => reg_index
+        );
+
+    sync : process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            current_avalon_state <= SLAVE_IDLE;
+            running <= '0';
+
+        elsif ( rising_edge( clk ) ) then
+            current_avalon_state <= next_avalon_state;
+
+            if ( running = '1' ) then
+                cycle_count <= cycle_count + 1;
+            end if;
+
+            case next_avalon_state is
+            when SLAVE_IDLE =>
+                null;
+
+            when SLAVE_READ =>
+                readdata <= ( others => '0' );
+                if ( reg_index = REG_STATE_POS ) then
+                    readdata( 0 ) <= running;
+                elsif ( reg_index = REG_CYCLE_COUNT_POS ) then
+                    readdata <= std_logic_vector( cycle_count );
+                end if;
+
+            when SLAVE_READ_DATA =>
+                null;
+
+            when SLAVE_WRITE =>
+                if ( reg_index = REG_STATE_POS ) then
+                    running <= writedata( 0 );
+                    if ( writedata( 0 ) = '1' ) then
+                        cycle_count <= ( others => '0' );
+                    end if;
+                end if;
+
+            end case;
+        end if;
+    end process sync;
+end architecture rtl;

hardware/system/pll/pll_main.bsf

+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2022  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and any partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details, at
+https://fpgasoftware.intel.com/eula.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 144)
+	(text "pll_main" (rect 56 -1 87 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
+		(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 48 112)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 112 72)(line_width 1))
+	)
+	(port
+		(pt 160 112)
+		(output)
+		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
+		(text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
+		(line (pt 160 112)(pt 112 112)(line_width 1))
+	)
+	(drawing
+		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
+		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
+		(text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
+		(text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
+		(line (pt 48 32)(pt 112 32)(line_width 1))
+		(line (pt 112 32)(pt 112 128)(line_width 1))
+		(line (pt 48 128)(pt 112 128)(line_width 1))
+		(line (pt 48 32)(pt 48 128)(line_width 1))
+		(line (pt 49 52)(pt 49 76)(line_width 1))
+		(line (pt 50 52)(pt 50 76)(line_width 1))
+		(line (pt 49 92)(pt 49 116)(line_width 1))
+		(line (pt 50 92)(pt 50 116)(line_width 1))
+		(line (pt 111 52)(pt 111 76)(line_width 1))
+		(line (pt 110 52)(pt 110 76)(line_width 1))
+		(line (pt 111 92)(pt 111 116)(line_width 1))
+		(line (pt 110 92)(pt 110 116)(line_width 1))
+		(line (pt 0 0)(pt 160 0)(line_width 1))
+		(line (pt 160 0)(pt 160 144)(line_width 1))
+		(line (pt 0 144)(pt 160 144)(line_width 1))
+		(line (pt 0 0)(pt 0 144)(line_width 1))
+	)
+)

hardware/system/pll/pll_main.cmp

+	component pll_main is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_main;
+

hardware/system/pll/pll_main.ppf

+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="pll_main"
+ megafunction_name="ALTERA_PLL"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+  <pin name="refclk" direction="input" scope="external" />
+  <pin name="rst" direction="input" scope="external" />
+  <pin name="outclk_0" direction="output" scope="external" />
+  <pin name="locked" direction="output" scope="external" />
+ </global>
+</pinplan>

hardware/system/pll/pll_main.qip

+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_main" -name MISC_FILE [file join $::quartus(qip_path) "pll_main.cmp"]
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_NAME "cGxsX21haW4="
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "pll_main" -library "pll_main" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_NAME "cGxsX21haW5fMDAwMg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_VERSION "MjEuMQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::Ng==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::Mw==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTAwLjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MywzLDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwyLDEsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSwyLDMwLDIwMDAsMzAwLjAgTUh6LDEsbm9uZSxnbGIsbV9jbnQscGhfbXV4X2NsayxmYWxzZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll_main" -name VHDL_FILE [file join $::quartus(qip_path) "pll_main.vhd"]
+set_global_assignment -library "pll_main" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_main/pll_main_0002.v"]
+set_global_assignment -library "pll_main" -name QIP_FILE [file join $::quartus(qip_path) "pll_main/pll_main_0002.qip"]
+
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "pll_main_0002" -library "pll_main" -name IP_TOOL_ENV "mwpim"

hardware/system/pll/pll_main.sip

+set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_VERSION "21.1"
+set_global_assignment -entity "pll_main" -library "lib_pll_main" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_pll_main" -name SPD_FILE [file join $::quartus(sip_path) "pll_main.spd"]
+
+set_global_assignment -library "lib_pll_main" -name MISC_FILE [file join $::quartus(sip_path) "pll_main_sim/pll_main.vho"]

hardware/system/pll/pll_main.spd

+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="pll_main_sim/pll_main.vho" type="VHDL" />
+ <topLevel name="pll_main" />
+ <deviceFamily name="cyclonev" />
+</simPackage>

hardware/system/pll/pll_main.vhd

+-- megafunction wizard: %PLL Intel FPGA IP v21.1%
+-- GENERATION: XML
+-- pll_main.vhd
+
+-- Generated using ACDS version 21.1 850
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity pll_main is
+	port (
+		refclk   : in  std_logic := '0'; --  refclk.clk
+		rst      : in  std_logic := '0'; --   reset.reset
+		outclk_0 : out std_logic;        -- outclk0.clk
+		locked   : out std_logic         --  locked.export
+	);
+end entity pll_main;
+
+architecture rtl of pll_main is
+	component pll_main_0002 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_main_0002;
+
+begin
+
+	pll_main_inst : component pll_main_0002
+		port map (
+			refclk   => refclk,   --  refclk.clk
+			rst      => rst,      --   reset.reset
+			outclk_0 => outclk_0, -- outclk0.clk
+			locked   => locked    --  locked.export
+		);
+
+end architecture rtl; -- of pll_main
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+--	Generated by Altera MegaWizard Launcher Utility version 1.0
+--	************************************************************
+--	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--	************************************************************
+--	Copyright (C) 1991-2022 Altera Corporation
+--	Any megafunction design, and related net list (encrypted or decrypted),
+--	support information, device programming or simulation file, and any other
+--	associated documentation or information provided by Altera or a partner
+--	under Altera's Megafunction Partnership Program may be used only to
+--	program PLD devices (but not masked PLD devices) from Altera.  Any other
+--	use of such megafunction design, net list, support information, device
+--	programming or simulation file, or any other related documentation or
+--	information is prohibited for any other purpose, including, but not
+--	limited to modification, reverse engineering, de-compiling, or use with
+--	any other silicon devices, unless such use is explicitly licensed under
+--	a separate agreement with Altera or a megafunction partner.  Title to
+--	the intellectual property, including patents, copyrights, trademarks,
+--	trade secrets, or maskworks, embodied in any such megafunction design,
+--	net list, support information, device programming or simulation file, or
+--	any other related documentation or information provided by Altera or a
+--	megafunction partner, remains with Altera, the megafunction partner, or
+--	their respective licensors.  No other licenses, including any licenses
+--	needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_pll" version="21.1" >
+-- Retrieval info: 	<generic name="debug_print_output" value="false" />
+-- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+-- Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+-- Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+-- Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />
+-- Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+-- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+-- Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+-- Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+-- Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+-- Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+-- Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+-- Retrieval info: 	<generic name="gui_use_locked" value="true" />
+-- Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+-- Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />
+-- Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+-- Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency0" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency1" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+-- Retrieval info: 	<generic name="gui_pll_auto_reset" value="Off" />
+-- Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+-- Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+-- Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_phout_division" value="1" />
+-- Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+-- Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+-- Retrieval info: 	<generic name="gui_dps_num" value="1" />
+-- Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+-- Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+-- Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+-- Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+-- Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+-- Retrieval info: 	<generic name="gui_active_clk" value="false" />
+-- Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+-- Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+-- Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : pll_main.vho
+-- RELATED_FILES: pll_main.vhd, pll_main_0002.v

hardware/system/pll/pll_main/pll_main_0002.qip

+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_main_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_main_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_main_0002*|altera_pll:altera_pll_i*|*"

hardware/system/pll/pll_main/pll_main_0002.v

+`timescale 1ns/10ps
+module  pll_main_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("direct"),
+		.number_of_clocks(1),
+		.output_clock_frequency0("100.000000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("0 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+

hardware/system/pll/pll_main_sim.f

+pll_main_sim/pll_main.vho

hardware/system/pll/pll_main_sim/aldec/rivierapro_setup.tcl

+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2022.08.29.18:38:18
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_main
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_main is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll_main"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/datadisk/opt/quartus-lite-21.1.1/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib               ./libraries/altera       
+vmap       altera        ./libraries/altera       
+ensure_lib               ./libraries/lpm          
+vmap       lpm           ./libraries/lpm          
+ensure_lib               ./libraries/sgate        
+vmap       sgate         ./libraries/sgate        
+ensure_lib               ./libraries/altera_mf    
+vmap       altera_mf     ./libraries/altera_mf    
+ensure_lib               ./libraries/altera_lnsim 
+vmap       altera_lnsim  ./libraries/altera_lnsim 
+ensure_lib               ./libraries/cyclonev     
+vmap       cyclonev      ./libraries/cyclonev     
+ensure_lib               ./libraries/cyclonev_hssi
+vmap       cyclonev_hssi ./libraries/cyclonev_hssi
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"          -work altera       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"      -work altera       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"         -work altera       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"      -work altera       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"   -work altera       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"              -work altera       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                        -work lpm          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                       -work lpm          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                     -work sgate        
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                          -work sgate        
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"           -work altera_mf    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                      -work altera_mf    
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                    -work altera_lnsim 
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"        -work altera_lnsim 
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"      -work cyclonev     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"                 -work cyclonev     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"            -work cyclonev     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd"       -work cyclonev_hssi
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd"            -work cyclonev_hssi
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h

hardware/system/pll/pll_main_sim/cadence/cds.lib

+
+DEFINE std            $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys       $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee           $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit          $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory   $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils        $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal     $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels       $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work           ./libraries/work/                         
+DEFINE altera         ./libraries/altera/                       
+DEFINE lpm            ./libraries/lpm/                          
+DEFINE sgate          ./libraries/sgate/                        
+DEFINE altera_mf      ./libraries/altera_mf/                    
+DEFINE altera_lnsim   ./libraries/altera_lnsim/                 
+DEFINE cyclonev       ./libraries/cyclonev/                     
+DEFINE cyclonev_hssi  ./libraries/cyclonev_hssi/                

hardware/system/pll/pll_main_sim/cadence/hdl.var

+
+DEFINE WORK work

hardware/system/pll/pll_main_sim/cadence/ncsim_setup.sh

+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2022.08.29.18:38:18
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_main
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_main is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2022.08.29.18:38:18
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll_main"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/datadisk/opt/quartus-lite-21.1.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+mkdir -p ./libraries/cyclonev_hssi/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"            -work altera       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"        -work altera       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"           -work altera       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"        -work altera       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"     -work altera       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"                -work altera       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                          -work lpm          
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                         -work lpm          
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                       -work sgate        
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                            -work sgate        
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"             -work altera_mf    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                        -work altera_mf    
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                      -work altera_lnsim 
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"          -work altera_lnsim 
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"      -work cyclonev     
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"                   -work cyclonev     
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"              -work cyclonev     
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd"         -work cyclonev_hssi
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd"              -work cyclonev_hssi
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  export GENERIC_PARAM_COMPAT_CHECK=1
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

hardware/system/pll/pll_main_sim/mentor/msim_setup.tcl

+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_main
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_main is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2022.08.29.18:38:18
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll_main"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/datadisk/opt/quartus-lite-21.1.1/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
+  ensure_lib               ./libraries/altera/       
+  vmap       altera        ./libraries/altera/       
+  ensure_lib               ./libraries/lpm/          
+  vmap       lpm           ./libraries/lpm/          
+  ensure_lib               ./libraries/sgate/        
+  vmap       sgate         ./libraries/sgate/        
+  ensure_lib               ./libraries/altera_mf/    
+  vmap       altera_mf     ./libraries/altera_mf/    
+  ensure_lib               ./libraries/altera_lnsim/ 
+  vmap       altera_lnsim  ./libraries/altera_lnsim/ 
+  ensure_lib               ./libraries/cyclonev/     
+  vmap       cyclonev      ./libraries/cyclonev/     
+  ensure_lib               ./libraries/cyclonev_hssi/
+  vmap       cyclonev_hssi ./libraries/cyclonev_hssi/
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"           -work altera       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"       -work altera       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"          -work altera       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"       -work altera       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"    -work altera       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"               -work altera       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                         -work lpm          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                        -work lpm          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                      -work sgate        
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                           -work sgate        
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"            -work altera_mf    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                       -work altera_mf    
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"     -work altera_lnsim 
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"         -work altera_lnsim 
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"      -work cyclonev     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"                  -work cyclonev     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"             -work cyclonev     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd"        -work cyclonev_hssi
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd"             -work cyclonev_hssi
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -voptargs=+acc option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev -L cyclonev_hssi $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -voptargs=+acc
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h

hardware/system/pll/pll_main_sim/pll_main.vho

+--IP Functional Simulation Model
+--VERSION_BEGIN 21.1 cbx_mgl 2022:06:23:22:26:17:SJ cbx_simgen 2022:06:23:22:02:32:SJ  VERSION_END
+
+
+-- Copyright (C) 2022  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and any partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details, at
+-- https://fpgasoftware.intel.com/eula.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Intel disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_lnsim;
+ USE altera_lnsim.altera_lnsim_components.all;
+
+--synthesis_resources = altera_pll 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  pll_main IS 
+	 PORT 
+	 ( 
+		 locked	:	OUT  STD_LOGIC;
+		 outclk_0	:	OUT  STD_LOGIC;
+		 refclk	:	IN  STD_LOGIC;
+		 rst	:	IN  STD_LOGIC
+	 ); 
+ END pll_main;
+
+ ARCHITECTURE RTL OF pll_main IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+	 SIGNAL  wire_gnd	:	STD_LOGIC;
+	 SIGNAL  wire_pll_main_altera_pll_altera_pll_i_639_locked	:	STD_LOGIC;
+	 SIGNAL  wire_pll_main_altera_pll_altera_pll_i_639_outclk	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+	wire_gnd <= '0';
+	locked <= wire_pll_main_altera_pll_altera_pll_i_639_locked;
+	outclk_0 <= wire_pll_main_altera_pll_altera_pll_i_639_outclk(0);
+	pll_main_altera_pll_altera_pll_i_639 :  altera_pll
+	  GENERIC MAP (
+		c_cnt_bypass_en0 => "false",
+		c_cnt_bypass_en1 => "false",
+		c_cnt_bypass_en10 => "false",
+		c_cnt_bypass_en11 => "false",
+		c_cnt_bypass_en12 => "false",
+		c_cnt_bypass_en13 => "false",
+		c_cnt_bypass_en14 => "false",
+		c_cnt_bypass_en15 => "false",
+		c_cnt_bypass_en16 => "false",
+		c_cnt_bypass_en17 => "false",
+		c_cnt_bypass_en2 => "false",
+		c_cnt_bypass_en3 => "false",
+		c_cnt_bypass_en4 => "false",
+		c_cnt_bypass_en5 => "false",
+		c_cnt_bypass_en6 => "false",
+		c_cnt_bypass_en7 => "false",
+		c_cnt_bypass_en8 => "false",
+		c_cnt_bypass_en9 => "false",
+		c_cnt_hi_div0 => 1,
+		c_cnt_hi_div1 => 1,
+		c_cnt_hi_div10 => 1,
+		c_cnt_hi_div11 => 1,
+		c_cnt_hi_div12 => 1,
+		c_cnt_hi_div13 => 1,
+		c_cnt_hi_div14 => 1,
+		c_cnt_hi_div15 => 1,
+		c_cnt_hi_div16 => 1,
+		c_cnt_hi_div17 => 1,
+		c_cnt_hi_div2 => 1,
+		c_cnt_hi_div3 => 1,
+		c_cnt_hi_div4 => 1,
+		c_cnt_hi_div5 => 1,
+		c_cnt_hi_div6 => 1,
+		c_cnt_hi_div7 => 1,
+		c_cnt_hi_div8 => 1,
+		c_cnt_hi_div9 => 1,
+		c_cnt_in_src0 => "ph_mux_clk",
+		c_cnt_in_src1 => "ph_mux_clk",
+		c_cnt_in_src10 => "ph_mux_clk",
+		c_cnt_in_src11 => "ph_mux_clk",
+		c_cnt_in_src12 => "ph_mux_clk",
+		c_cnt_in_src13 => "ph_mux_clk",
+		c_cnt_in_src14 => "ph_mux_clk",
+		c_cnt_in_src15 => "ph_mux_clk",
+		c_cnt_in_src16 => "ph_mux_clk",
+		c_cnt_in_src17 => "ph_mux_clk",
+		c_cnt_in_src2 => "ph_mux_clk",
+		c_cnt_in_src3 => "ph_mux_clk",
+		c_cnt_in_src4 => "ph_mux_clk",
+		c_cnt_in_src5 => "ph_mux_clk",
+		c_cnt_in_src6 => "ph_mux_clk",
+		c_cnt_in_src7 => "ph_mux_clk",
+		c_cnt_in_src8 => "ph_mux_clk",
+		c_cnt_in_src9 => "ph_mux_clk",
+		c_cnt_lo_div0 => 1,
+		c_cnt_lo_div1 => 1,
+		c_cnt_lo_div10 => 1,
+		c_cnt_lo_div11 => 1,
+		c_cnt_lo_div12 => 1,
+		c_cnt_lo_div13 => 1,
+		c_cnt_lo_div14 => 1,
+		c_cnt_lo_div15 => 1,
+		c_cnt_lo_div16 => 1,
+		c_cnt_lo_div17 => 1,
+		c_cnt_lo_div2 => 1,
+		c_cnt_lo_div3 => 1,
+		c_cnt_lo_div4 => 1,
+		c_cnt_lo_div5 => 1,
+		c_cnt_lo_div6 => 1,
+		c_cnt_lo_div7 => 1,
+		c_cnt_lo_div8 => 1,
+		c_cnt_lo_div9 => 1,
+		c_cnt_odd_div_duty_en0 => "false",
+		c_cnt_odd_div_duty_en1 => "false",
+		c_cnt_odd_div_duty_en10 => "false",
+		c_cnt_odd_div_duty_en11 => "false",
+		c_cnt_odd_div_duty_en12 => "false",
+		c_cnt_odd_div_duty_en13 => "false",
+		c_cnt_odd_div_duty_en14 => "false",
+		c_cnt_odd_div_duty_en15 => "false",
+		c_cnt_odd_div_duty_en16 => "false",
+		c_cnt_odd_div_duty_en17 => "false",
+		c_cnt_odd_div_duty_en2 => "false",
+		c_cnt_odd_div_duty_en3 => "false",
+		c_cnt_odd_div_duty_en4 => "false",
+		c_cnt_odd_div_duty_en5 => "false",
+		c_cnt_odd_div_duty_en6 => "false",
+		c_cnt_odd_div_duty_en7 => "false",
+		c_cnt_odd_div_duty_en8 => "false",
+		c_cnt_odd_div_duty_en9 => "false",
+		c_cnt_ph_mux_prst0 => 0,
+		c_cnt_ph_mux_prst1 => 0,
+		c_cnt_ph_mux_prst10 => 0,
+		c_cnt_ph_mux_prst11 => 0,
+		c_cnt_ph_mux_prst12 => 0,
+		c_cnt_ph_mux_prst13 => 0,
+		c_cnt_ph_mux_prst14 => 0,
+		c_cnt_ph_mux_prst15 => 0,
+		c_cnt_ph_mux_prst16 => 0,
+		c_cnt_ph_mux_prst17 => 0,
+		c_cnt_ph_mux_prst2 => 0,
+		c_cnt_ph_mux_prst3 => 0,
+		c_cnt_ph_mux_prst4 => 0,
+		c_cnt_ph_mux_prst5 => 0,
+		c_cnt_ph_mux_prst6 => 0,
+		c_cnt_ph_mux_prst7 => 0,
+		c_cnt_ph_mux_prst8 => 0,
+		c_cnt_ph_mux_prst9 => 0,
+		c_cnt_prst0 => 1,
+		c_cnt_prst1 => 1,
+		c_cnt_prst10 => 1,
+		c_cnt_prst11 => 1,
+		c_cnt_prst12 => 1,
+		c_cnt_prst13 => 1,
+		c_cnt_prst14 => 1,
+		c_cnt_prst15 => 1,
+		c_cnt_prst16 => 1,
+		c_cnt_prst17 => 1,
+		c_cnt_prst2 => 1,
+		c_cnt_prst3 => 1,
+		c_cnt_prst4 => 1,
+		c_cnt_prst5 => 1,
+		c_cnt_prst6 => 1,
+		c_cnt_prst7 => 1,
+		c_cnt_prst8 => 1,
+		c_cnt_prst9 => 1,
+		clock_name_0 => "UNUSED",
+		clock_name_1 => "UNUSED",
+		clock_name_2 => "UNUSED",
+		clock_name_3 => "UNUSED",
+		clock_name_4 => "UNUSED",
+		clock_name_5 => "UNUSED",
+		clock_name_6 => "UNUSED",
+		clock_name_7 => "UNUSED",
+		clock_name_8 => "UNUSED",
+		clock_name_global_0 => "false",
+		clock_name_global_1 => "false",
+		clock_name_global_2 => "false",
+		clock_name_global_3 => "false",
+		clock_name_global_4 => "false",
+		clock_name_global_5 => "false",
+		clock_name_global_6 => "false",
+		clock_name_global_7 => "false",
+		clock_name_global_8 => "false",
+		data_rate => 0,
+		deserialization_factor => 4,
+		duty_cycle0 => 50,
+		duty_cycle1 => 50,
+		duty_cycle10 => 50,
+		duty_cycle11 => 50,
+		duty_cycle12 => 50,
+		duty_cycle13 => 50,
+		duty_cycle14 => 50,
+		duty_cycle15 => 50,
+		duty_cycle16 => 50,
+		duty_cycle17 => 50,
+		duty_cycle2 => 50,
+		duty_cycle3 => 50,
+		duty_cycle4 => 50,
+		duty_cycle5 => 50,
+		duty_cycle6 => 50,
+		duty_cycle7 => 50,
+		duty_cycle8 => 50,
+		duty_cycle9 => 50,
+		fractional_vco_multiplier => "false",
+		m_cnt_bypass_en => "false",
+		m_cnt_hi_div => 1,
+		m_cnt_lo_div => 1,
+		m_cnt_odd_div_duty_en => "false",
+		mimic_fbclk_type => "gclk",
+		n_cnt_bypass_en => "false",
+		n_cnt_hi_div => 1,
+		n_cnt_lo_div => 1,
+		n_cnt_odd_div_duty_en => "false",
+		number_of_clocks => 1,
+		operation_mode => "direct",
+		output_clock_frequency0 => "100.000000 MHz",
+		output_clock_frequency1 => "0 MHz",
+		output_clock_frequency10 => "0 MHz",
+		output_clock_frequency11 => "0 MHz",
+		output_clock_frequency12 => "0 MHz",
+		output_clock_frequency13 => "0 MHz",
+		output_clock_frequency14 => "0 MHz",
+		output_clock_frequency15 => "0 MHz",
+		output_clock_frequency16 => "0 MHz",
+		output_clock_frequency17 => "0 MHz",
+		output_clock_frequency2 => "0 MHz",
+		output_clock_frequency3 => "0 MHz",
+		output_clock_frequency4 => "0 MHz",
+		output_clock_frequency5 => "0 MHz",
+		output_clock_frequency6 => "0 MHz",
+		output_clock_frequency7 => "0 MHz",
+		output_clock_frequency8 => "0 MHz",
+		output_clock_frequency9 => "0 MHz",
+		phase_shift0 => "0 ps",
+		phase_shift1 => "0 ps",
+		phase_shift10 => "0 ps",
+		phase_shift11 => "0 ps",
+		phase_shift12 => "0 ps",
+		phase_shift13 => "0 ps",
+		phase_shift14 => "0 ps",
+		phase_shift15 => "0 ps",
+		phase_shift16 => "0 ps",
+		phase_shift17 => "0 ps",
+		phase_shift2 => "0 ps",
+		phase_shift3 => "0 ps",
+		phase_shift4 => "0 ps",
+		phase_shift5 => "0 ps",
+		phase_shift6 => "0 ps",
+		phase_shift7 => "0 ps",
+		phase_shift8 => "0 ps",
+		phase_shift9 => "0 ps",
+		pll_auto_clk_sw_en => "false",
+		pll_bw_sel => "low",
+		pll_bwctrl => 0,
+		pll_clk_loss_sw_en => "false",
+		pll_clk_sw_dly => 0,
+		pll_clkin_0_src => "clk_0",
+		pll_clkin_1_src => "clk_0",
+		pll_cp_current => 0,
+		pll_dsm_out_sel => "1st_order",
+		pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_fbclk_mux_1 => "glb",
+		pll_fbclk_mux_2 => "fb_1",
+		pll_fractional_cout => 24,
+		pll_fractional_division => 1,
+		pll_m_cnt_in_src => "ph_mux_clk",
+		pll_manu_clk_sw_en => "false",
+		pll_output_clk_frequency => "0 MHz",
+		pll_slf_rst => "false",
+		pll_subtype => "General",
+		pll_type => "General",
+		pll_vco_div => 1,
+		pll_vcoph_div => 1,
+		refclk1_frequency => "0 MHz",
+		reference_clock_frequency => "50.0 MHz",
+		sim_additional_refclk_cycles_to_lock => 0
+	  )
+	  PORT MAP ( 
+		fbclk => wire_gnd,
+		locked => wire_pll_main_altera_pll_altera_pll_i_639_locked,
+		outclk => wire_pll_main_altera_pll_altera_pll_i_639_outclk,
+		refclk => refclk,
+		rst => rst
+	  );
+
+ END RTL; --pll_main
+--synopsys translate_on
+--VALID FILE

hardware/system/pll/pll_main_sim/synopsys/vcsmx/synopsys_sim.setup

+
+WORK > DEFAULT
+DEFAULT:       ./libraries/work/         
+work:          ./libraries/work/         
+altera:        ./libraries/altera/       
+lpm:           ./libraries/lpm/          
+sgate:         ./libraries/sgate/        
+altera_mf:     ./libraries/altera_mf/    
+altera_lnsim:  ./libraries/altera_lnsim/ 
+cyclonev:      ./libraries/cyclonev/     
+cyclonev_hssi: ./libraries/cyclonev_hssi/
+LIBRARY_SCAN = TRUE

hardware/system/pll/pll_main_sim/synopsys/vcsmx/vcsmx_setup.sh

+
+# (C) 2001-2022 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 21.1 850 linux 2022.08.29.18:38:18
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_main
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries 
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_main is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 21.1 850 linux 2022.08.29.18:38:18
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll_main"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/datadisk/opt/quartus-lite-21.1.1/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+mkdir -p ./libraries/cyclonev_hssi/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"             -work altera       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"         -work altera       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"            -work altera       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"         -work altera       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"      -work altera       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"                 -work altera       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                           -work lpm          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                          -work lpm          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                        -work sgate        
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                             -work sgate        
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"              -work altera_mf    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                         -work altera_mf    
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                       -work altera_lnsim 
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"           -work altera_lnsim 
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v"      -work cyclonev     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"                    -work cyclonev     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"               -work cyclonev     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_components.vhd"          -work cyclonev_hssi
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.vhd"               -work cyclonev_hssi
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_main.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

hardware/system/reg32.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+package reg32 is
+
+    subtype Word is std_logic_vector( 31 downto 0 );
+
+    type RegArray is array ( natural range <> ) of Word;
+
+    type AccessType is (
+        NONE,
+        READ_ONLY,
+        WRITE_ONLY,
+        READ_WRITE
+    );
+
+    type AccessArray is array ( natural range <> ) of AccessType;
+
+    function allows_read( access_type : AccessType )
+        return boolean;
+
+    function allows_write( access_type : AccessType )
+        return boolean;
+
+end package reg32;
+
+package body reg32 is
+
+    function allows_read( access_type : AccessType )
+        return boolean is
+    begin
+        return access_type = READ_ONLY or access_type = READ_WRITE;
+    end function allows_read;
+
+    function allows_write( access_type : AccessType )
+        return boolean is
+    begin
+        return access_type = WRITE_ONLY or access_type = READ_WRITE;
+    end function allows_write;
+
+end package body reg32;
+

hardware/system/squareRoot_pipe.vhd

+----------------------------------------------------------------------------------------------------
+-- Component   : squareRoot_pipe
+-- Author      : pwkolas
+----------------------------------------------------------------------------------------------------
+-- File        : squareRoot_pipe.vhd
+-- Mod. Date   : XX.XX.XXXX
+-- Version     : 1.00
+----------------------------------------------------------------------------------------------------
+-- Description : Square root calculator.
+--               Based on
+--               "A New Non-Restoring Square Root Algorithm and Its VLSI Implementations"
+--
+----------------------------------------------------------------------------------------------------
+-- Modification History :
+--
+----------------------------------------------------------------------------------------------------
+-- Comments :
+--
+----------------------------------------------------------------------------------------------------
+
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity squareRoot_pipe is
+   generic (
+      G_DATA_W : integer := 32
+      );
+   port (
+      clk     : in  std_logic;
+      rst     : in  std_logic;
+      iv_data : in  std_logic_vector(G_DATA_W-1 downto 0);
+      ov_res  : out std_logic_vector((G_DATA_W/2)-1 downto 0)
+      );
+end entity squareRoot_pipe;
+
+architecture squareRoot_pipe_rtl of squareRoot_pipe is
+
+   constant C_ALU_W  : integer := ((G_DATA_W/2) + 2);
+   constant C_PIPE_L : integer := G_DATA_W/2;
+   constant C_OFFSET : integer := 3;    -- width of start vectors going  to ALU
+
+   type t_arr_pipe_x_data is array (C_PIPE_L-1 downto 0) of unsigned(G_DATA_W-1 downto 0);
+   signal a_data : t_arr_pipe_x_data;   -- (D)
+   signal a_R    : t_arr_pipe_x_data;   -- (R)
+
+   type t_arr_pipe_x_alu is array (C_PIPE_L-1 downto 0) of unsigned(C_ALU_W-1 downto 0);
+
+   type t_arr_pipe_x_res is array (C_PIPE_L-1 downto 0) of unsigned(G_DATA_W/2-1 downto 0);
+   signal a_Q : t_arr_pipe_x_res;       -- (ALU Q out)
+
+   signal nextOp : std_logic_vector(C_PIPE_L-1 downto 0);
+
+begin
+   sqrt_p : process (clk, rst)
+      variable va_AluInR : t_arr_pipe_x_alu;  -- (ALU R in)
+      variable va_AluInQ : t_arr_pipe_x_alu;  -- (ALU Q in)
+      variable va_AluOut : t_arr_pipe_x_alu;  -- (ALU Q out)
+   begin
+      if (rst = '1') then
+         a_data    <= (others => (others => '0'));
+         a_R       <= (others => (others => '0'));
+         a_Q       <= (others => (others => '0'));
+         va_AluInR := (others => (others => '0'));
+         va_AluInQ := (others => (others => '0'));
+         va_AluOut := (others => (others => '0'));
+         nextOp    <= (others => '0');
+      elsif rising_edge(clk) then
+         -- stage 0 start conditions, ALU inputs
+         va_AluInR(0)             := (others => '0');
+         va_AluInR(0)(1 downto 0) := unsigned(iv_data(G_DATA_W-1 downto G_DATA_W-1-1));
+         va_AluInQ(0)             := (others => '0');
+         va_AluInQ(0)(0)          := '1';
+
+         -- stage 0 calculations
+         va_AluOut(0) := va_AluInR(0) - va_AluInQ(0);
+
+         -- stage 0 result registers, ALU output
+         a_data(0)                              <= shift_left(unsigned(iv_data), 2);
+         a_R(0)                                 <= (others => '0');
+         a_R(0)(G_DATA_W-1 downto G_DATA_W-1-1) <= va_AluOut(0)(1 downto 0);
+         a_Q(0)                                 <= (others => '0');
+         a_Q(0)(0)                              <= not va_AluOut(0)(2);
+         nextOp(0)                              <= not va_AluOut(0)(2);
+
+         -- next stages
+         for i in 1 to C_PIPE_L-1 loop
+            -- prepare inputs for next stage
+            va_AluInR(i)                            := (others => '0');
+            va_AluInR(i)(C_OFFSET+i-1 downto 2)     := a_R(i-1)(G_DATA_W-(i-1)-1 downto G_DATA_W-(2*i));
+            va_AluInR(i)(2-1 downto 0)              := a_data(i-1)(G_DATA_W-1 downto G_DATA_W-1-1);
+            va_AluInQ(i)                            := (others => '0');
+            va_AluInQ(i)(C_OFFSET+(i-1)-1 downto 2) := a_Q(i-1)(i-1 downto 0);
+            va_AluInQ(i)(1)                         := not a_Q(i-1)(0);
+            va_AluInQ(i)(0)                         := '1';
+
+            -- ALU ADD/SUB
+            if (nextOp(i-1) = '1') then
+               va_AluOut(i) := va_AluInR(i) - va_AluInQ(i);
+            else
+               va_AluOut(i) := va_AluInR(i) + va_AluInQ(i);
+            end if;
+
+            -- result registers
+            a_data(i)                                    <= shift_left(unsigned(a_data(i-1)), 2);
+            a_R(i)                                       <= (others => '0');
+            a_R(i)(G_DATA_W-i-1 downto G_DATA_W-2*(i+1)) <= va_AluOut(i)(i+1 downto 0);
+            a_Q(i)                                       <= shift_left(unsigned(a_Q(i-1)), 1);
+            a_Q(i)(0)                                    <= not va_AluOut(i)(i+2);
+            nextOp(i)                                    <= not va_AluOut(i)(i+2);
+
+         end loop;
+      end if;
+   end process;
+
+   ov_res <= std_logic_vector(a_Q(C_PIPE_L-1));
+
+end architecture squareRoot_pipe_rtl;

hardware/system/sync_ff.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity sync_ff is
+    generic
+    (
+        DEPTH     : positive range 2 to 5 := 2;
+        RST_VALUE : std_logic             := '0'
+    );
+
+    port
+    (
+        --! Destination domain clock
+        clk    : in  std_logic;
+        --! Low active destination domain reset
+        reset  : in  std_logic;
+
+        --! Single bit data input
+        din    : in  std_logic;
+        --! Single bit data output
+        dout   : out std_logic
+    );
+
+end entity sync_ff;
+
+architecture rtl of sync_ff is
+
+    signal sync : std_logic_vector( DEPTH - 1 downto 0 );
+
+begin
+
+    p_sync: process ( clk, reset ) is
+    begin
+
+        if ( reset = '1' ) then
+
+	    sync <= ( others => RST_VALUE );
+
+	elsif ( rising_edge( clk ) ) then
+
+            sync( DEPTH - 1 downto 1 ) <= sync( DEPTH - 2 downto 0 );
+            sync( 0 )                  <= din;
+
+        end if;
+    end process p_sync;
+
+    c_dout:   dout                       <= sync( DEPTH - 1 );
+
+end architecture rtl;
+

hardware/system/sync_rst.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+
+entity sync_rst is
+    generic
+    (
+        WIDTH : positive range 2 to 5 := 3
+    );
+
+    port
+    (
+        clk : in  std_logic;
+        reset : in  std_logic;
+        rst_sync : out std_logic
+    );
+end entity sync_rst;
+
+architecture rtl of sync_rst is
+
+   --! Synchronization FFs
+   signal sync : std_logic_vector( WIDTH - 1 downto 0 );
+
+begin
+
+    p_sync: process ( clk, reset ) is
+    begin
+
+        if ( reset = '1' ) then
+
+            sync <= ( others => '1' );
+
+        elsif ( rising_edge( clk ) ) then
+
+            sync( 0 ) <= '0';
+
+            sync( WIDTH - 1 downto 1 ) <= sync( WIDTH - 2 downto 0 );
+        end if;
+
+    end process p_sync;
+
+    rst_sync <= sync( WIDTH - 1 );
+
+end architecture rtl;

hardware/system/task.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+    use ieee.math_real.all;
+
+
+package task is
+
+    type State is (
+        TASK_IDLE,
+        TASK_RUNNING,
+        TASK_DONE
+    );
+
+    function to_std_logic_vector( s : State; len : positive ) return std_logic_vector;
+
+    constant STREAM_LEN : integer := 1024;
+
+end package task;
+
+package body task is
+
+    function to_std_logic_vector( s : State; len : positive ) return std_logic_vector is
+        constant MIN_LEN : positive := positive( ceil( log2( real( State'pos( State'right ) + 1 ) ) ) );
+        variable vector : std_logic_vector( MIN_LEN - 1 downto 0 );
+        variable output : std_logic_vector( len - 1 downto 0 );
+    begin
+        vector := std_logic_vector( to_unsigned( State'pos( s ), MIN_LEN ) );
+        if ( len < MIN_LEN ) then
+            output := ( others => 'U' );
+        elsif ( len = MIN_LEN ) then
+            output := vector;
+        else
+            output := ( others => '0' );
+            output( vector'range ) := vector;
+        end if;
+        return output;
+    end function to_std_logic_vector;
+
+end package body task;
+

hardware/system/task_add.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity task_add is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        signal_a_read : out std_logic;
+        signal_a_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_b_read : out std_logic;
+        signal_b_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity task_add;
+
+architecture struct of task_add is
+
+    signal task_start : std_logic;
+    signal task_state : work.task.State := work.task.TASK_IDLE;
+    signal task_config : work.reg32.RegArray( 0 to 2 );
+
+begin
+    u_control: entity work.hardware_task_control
+        port map (
+            clk => clk,
+            reset => reset,
+
+            address => address,
+            read => read,
+            readdata => readdata,
+            write => write,
+            writedata => writedata,
+
+            task_start => task_start,
+            task_state => task_state,
+            task_config => task_config
+        );
+
+    u_add: entity work.add
+        port map (
+            clk => clk,
+            reset => reset,
+
+            task_start => task_start,
+            task_state => task_state,
+
+            signal_a_read => signal_a_read,
+            signal_a_readdata => signal_a_readdata,
+
+            signal_b_read => signal_b_read,
+            signal_b_readdata => signal_b_readdata,
+
+            signal_write => signal_write,
+            signal_writedata => signal_writedata
+        );
+
+end architecture struct;
+

hardware/system/task_crc.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity task_crc is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        signal_read : out std_logic;
+        signal_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity task_crc;
+
+architecture struct of task_crc is
+
+    signal task_start : std_logic;
+    signal task_state : work.task.State := work.task.TASK_IDLE;
+    signal task_config : work.reg32.RegArray( 0 to 2 );
+
+begin
+    u_control: entity work.hardware_task_control
+        port map (
+            clk => clk,
+            reset => reset,
+
+            address => address,
+            read => read,
+            readdata => readdata,
+            write => write,
+            writedata => writedata,
+
+            task_start => task_start,
+            task_state => task_state,
+            task_config => task_config
+        );
+
+    u_crc: entity work.crc
+        port map (
+            clk => clk,
+            reset => reset,
+
+            task_start => task_start,
+            task_state => task_state,
+
+            signal_read => signal_read,
+            signal_readdata => signal_readdata,
+
+            signal_write => signal_write,
+            signal_writedata => signal_writedata
+        );
+
+end architecture struct;
+

hardware/system/task_fft.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity task_fft is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        signal_read : out std_logic;
+        signal_readdata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity task_fft;
+
+architecture struct of task_fft is
+
+    signal task_start : std_logic;
+    signal task_state : work.task.State := work.task.TASK_IDLE;
+    signal task_config : work.reg32.RegArray( 0 to 2 );
+
+begin
+    u_control: entity work.hardware_task_control
+        port map (
+            clk => clk,
+            reset => reset,
+
+            address => address,
+            read => read,
+            readdata => readdata,
+            write => write,
+            writedata => writedata,
+
+            task_start => task_start,
+            task_state => task_state,
+            task_config => task_config
+        );
+
+		
+    u_fft: entity work.fft
+	     generic map (
+		      -- input data width of real/img part 
+            input_data_width => 32,
+				-- output data width of real/img part 
+            output_data_width => 32
+        )
+        port map (
+            clk => clk,
+            reset => reset,
+
+            task_start => task_start,
+            task_state => task_state,
+
+            signal_read => signal_read,
+            signal_readdata => signal_readdata,
+
+            signal_write => signal_write,
+            signal_writedata => signal_writedata
+        );
+
+end architecture struct;

hardware/system/task_rand.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity task_rand is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity task_rand;
+
+architecture struct of task_rand is
+
+    signal task_start : std_logic;
+    signal task_state : work.task.State := work.task.TASK_IDLE;
+    signal task_config : work.reg32.RegArray( 0 to 2 );
+
+begin
+    u_control: entity work.hardware_task_control
+        port map (
+            clk => clk,
+            reset => reset,
+
+            address => address,
+            read => read,
+            readdata => readdata,
+            write => write,
+            writedata => writedata,
+
+            task_start => task_start,
+            task_state => task_state,
+            task_config => task_config
+        );
+
+    u_rand: entity work.rand
+        port map (
+            clk => clk,
+            reset => reset,
+
+            task_start => task_start,
+            task_state => task_state,
+            seed => task_config( 0 ),
+
+            signal_write => signal_write,
+            signal_writedata => signal_writedata
+        );
+
+end architecture struct;
+

hardware/system/task_sine.vhd

+library ieee;
+    use ieee.std_logic_1164.all;
+    use ieee.numeric_std.all;
+
+library work;
+    use work.reg32.all;
+    use work.task.all;
+
+entity task_sine is
+    port (
+        clk : in std_logic;
+        reset : in std_logic;
+
+        address : in std_logic_vector( 3 downto 0 );
+        read : in std_logic;
+        readdata : out std_logic_vector( 31 downto 0 );
+        write : in std_logic;
+        writedata : in std_logic_vector( 31 downto 0 );
+
+        signal_write : out std_logic;
+        signal_writedata : out std_logic_vector( 31 downto 0 )
+    );
+end entity task_sine;
+
+architecture struct of task_sine is
+
+    signal task_start : std_logic;
+    signal task_state : work.task.State := work.task.TASK_IDLE;
+    signal task_config : work.reg32.RegArray( 0 to 2 );
+
+begin
+    u_control: entity work.hardware_task_control
+        port map (
+            clk => clk,
+            reset => reset,
+
+            address => address,
+            read => read,
+            readdata => readdata,
+            write => write,
+            writedata => writedata,
+
+            task_start => task_start,
+            task_state => task_state,
+            task_config => task_config
+        );
+
+    u_sine: entity work.sine
+        port map (
+            clk => clk,
+            reset => reset,
+
+            task_start => task_start,
+            task_state => task_state,
+
+            step_size => task_config( 0 ),
+            phase => task_config( 1 ),
+            amplitude => task_config( 2 ),
+
+            signal_write => signal_write,
+            signal_writedata => signal_writedata
+        );
+
+end architecture struct;
+

hardware_task_hw.tcl

+# TCL File Generated by Component Editor 21.1
+# Thu Sep 08 23:38:44 CEST 2022
+# DO NOT MODIFY
+
+
+# 
+# hardware_task "hardware_task" v1.0
+#  2022.09.08.23:38:44
+# A hardware task status and control interface
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module hardware_task
+# 
+set_module_property DESCRIPTION "A hardware task status and control interface"
+set_module_property NAME hardware_task
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP signal_processing
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME hardware_task
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL hardware_task
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
+add_fileset_file hardware_task.vhd VHDL PATH hardware/system/hardware_task.vhd TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point ctrl
+# 
+add_interface ctrl avalon end
+set_interface_property ctrl addressUnits WORDS
+set_interface_property ctrl associatedClock clock
+set_interface_property ctrl associatedReset reset
+set_interface_property ctrl bitsPerSymbol 8
+set_interface_property ctrl burstOnBurstBoundariesOnly false
+set_interface_property ctrl burstcountUnits WORDS
+set_interface_property ctrl explicitAddressSpan 0
+set_interface_property ctrl holdTime 0
+set_interface_property ctrl linewrapBursts false
+set_interface_property ctrl maximumPendingReadTransactions 0
+set_interface_property ctrl maximumPendingWriteTransactions 0
+set_interface_property ctrl readLatency 0
+set_interface_property ctrl readWaitTime 1
+set_interface_property ctrl setupTime 0
+set_interface_property ctrl timingUnits Cycles
+set_interface_property ctrl writeWaitTime 0
+set_interface_property ctrl ENABLED true
+set_interface_property ctrl EXPORT_OF ""
+set_interface_property ctrl PORT_NAME_MAP ""
+set_interface_property ctrl CMSIS_SVD_VARIABLES ""
+set_interface_property ctrl SVD_ADDRESS_GROUP ""
+
+add_interface_port ctrl ctrl_address address Input 4
+add_interface_port ctrl ctrl_read read Input 1
+add_interface_port ctrl ctrl_readdata readdata Output 32
+add_interface_port ctrl ctrl_write write Input 1
+add_interface_port ctrl ctrl_writedata writedata Input 32
+set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
+set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
+
+
+# 
+# connection point task
+# 
+add_interface task avalon start
+set_interface_property task addressUnits SYMBOLS
+set_interface_property task associatedClock clock
+set_interface_property task associatedReset reset
+set_interface_property task bitsPerSymbol 8
+set_interface_property task burstOnBurstBoundariesOnly false
+set_interface_property task burstcountUnits WORDS
+set_interface_property task doStreamReads false
+set_interface_property task doStreamWrites false
+set_interface_property task holdTime 0
+set_interface_property task linewrapBursts false
+set_interface_property task maximumPendingReadTransactions 0
+set_interface_property task maximumPendingWriteTransactions 0
+set_interface_property task readLatency 0
+set_interface_property task readWaitTime 1
+set_interface_property task setupTime 0
+set_interface_property task timingUnits Cycles
+set_interface_property task writeWaitTime 0
+set_interface_property task ENABLED true
+set_interface_property task EXPORT_OF ""
+set_interface_property task PORT_NAME_MAP ""
+set_interface_property task CMSIS_SVD_VARIABLES ""
+set_interface_property task SVD_ADDRESS_GROUP ""
+
+add_interface_port task task_address address Output 4
+add_interface_port task task_read read Output 1
+add_interface_port task task_readdata readdata Input 32
+add_interface_port task task_write write Output 1
+add_interface_port task task_writedata writedata Output 32
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+

hardware_timestamp_hw.tcl

+# TCL File Generated by Component Editor 21.1
+# Thu Sep 08 23:25:06 CEST 2022
+# DO NOT MODIFY
+
+
+# 
+# hardware_timestamp "hardware_timestamp" v1.0
+# Johannes Kutning 2022.09.08.23:25:06
+# Timestamp device used to measure software execution time
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module hardware_timestamp
+# 
+set_module_property DESCRIPTION "Timestamp device used to measure software execution time"
+set_module_property NAME hardware_timestamp
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property GROUP signal_processing
+set_module_property AUTHOR "Johannes Kutning"
+set_module_property DISPLAY_NAME hardware_timestamp
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL timer
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file hardware_timestamp.vhd VHDL PATH hardware/system/hardware_timestamp.vhd TOP_LEVEL_FILE
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock
+# 
+add_interface clock clock end
+set_interface_property clock clockRate 0
+set_interface_property clock ENABLED true
+set_interface_property clock EXPORT_OF ""
+set_interface_property clock PORT_NAME_MAP ""
+set_interface_property clock CMSIS_SVD_VARIABLES ""
+set_interface_property clock SVD_ADDRESS_GROUP ""
+
+add_interface_port clock clk clk Input 1
+
+
+# 
+# connection point reset
+# 
+add_interface reset reset end
+set_interface_property reset associatedClock clock
+set_interface_property reset synchronousEdges DEASSERT
+set_interface_property reset ENABLED true
+set_interface_property reset EXPORT_OF ""
+set_interface_property reset PORT_NAME_MAP ""
+set_interface_property reset CMSIS_SVD_VARIABLES ""
+set_interface_property reset SVD_ADDRESS_GROUP ""
+
+add_interface_port reset reset reset Input 1
+
+
+# 
+# connection point ctrl
+# 
+add_interface ctrl avalon end
+set_interface_property ctrl addressUnits WORDS
+set_interface_property ctrl associatedClock clock
+set_interface_property ctrl associatedReset reset
+set_interface_property ctrl bitsPerSymbol 8
+set_interface_property ctrl burstOnBurstBoundariesOnly false
+set_interface_property ctrl burstcountUnits WORDS
+set_interface_property ctrl explicitAddressSpan 0
+set_interface_property ctrl holdTime 0
+set_interface_property ctrl linewrapBursts false
+set_interface_property ctrl maximumPendingReadTransactions 0
+set_interface_property ctrl maximumPendingWriteTransactions 0
+set_interface_property ctrl readLatency 0
+set_interface_property ctrl readWaitTime 1
+set_interface_property ctrl setupTime 0
+set_interface_property ctrl timingUnits Cycles
+set_interface_property ctrl writeWaitTime 0
+set_interface_property ctrl ENABLED true
+set_interface_property ctrl EXPORT_OF ""
+set_interface_property ctrl PORT_NAME_MAP ""
+set_interface_property ctrl CMSIS_SVD_VARIABLES ""
+set_interface_property ctrl SVD_ADDRESS_GROUP ""
+
+add_interface_port ctrl address address Input 4
+add_interface_port ctrl read read Input 1
+add_interface_port ctrl readdata readdata Output 32
+add_interface_port ctrl write write Input 1
+add_interface_port ctrl writedata writedata Input 32
+set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
+set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
+set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
+set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
+

hdl_sources.qsf

+set_global_assignment -name VHDL_FILE hardware/system/sync_ff.vhd
+set_global_assignment -name VHDL_FILE hardware/system/sync_rst.vhd
+set_global_assignment -name VHDL_FILE hardware/system/pll_main.vhd
+
+set_global_assignment -name VHDL_FILE hardware/system/reg32.vhd
+set_global_assignment -name VHDL_FILE hardware/system/avalon_slave_transitions.vhd
+set_global_assignment -name VHDL_FILE hardware/system/avalon_slave.vhd
+
+set_global_assignment -name VHDL_FILE hardware/system/data_sink_mux.vhd
+set_global_assignment -name VHDL_FILE hardware/system/fifo.vhd
+set_global_assignment -name VHDL_FILE hardware/system/data_source_mux.vhd
+set_global_assignment -name VHDL_FILE hardware/system/data_channel_control.vhd
+set_global_assignment -name VHDL_FILE hardware/system/data_channel.vhd
+
+set_global_assignment -name VHDL_FILE hardware/system/hardware_timestamp.vhd
+
+set_global_assignment -name VHDL_FILE hardware/system/task.vhd
+set_global_assignment -name VHDL_FILE hardware/system/float.vhd
+set_global_assignment -name VHDL_FILE hardware/system/hardware_task_control.vhd
+set_global_assignment -name VHDL_FILE hardware/system/hardware_task.vhd
+
+set_global_assignment -name VHDL_FILE hardware/system/float_add.vhd
+set_global_assignment -name VHDL_FILE hardware/signal_processing/add.vhd
+set_global_assignment -name VHDL_FILE hardware/system/task_add.vhd
+
+set_global_assignment -name VHDL_FILE hardware/signal_processing/rand.vhd
+set_global_assignment -name VHDL_FILE hardware/system/task_rand.vhd
+
+set_global_assignment -name VHDL_FILE hardware/system/cordic_pkg.vhd
+set_global_assignment -name VHDL_FILE hardware/system/cordic.vhd
+set_global_assignment -name VHDL_FILE hardware/system/fixed_sine.vhd
+set_global_assignment -name VHDL_FILE hardware/system/float_sine.vhd
+set_global_assignment -name VHDL_FILE hardware/signal_processing/sine.vhd
+set_global_assignment -name VHDL_FILE hardware/system/task_sine.vhd
+
+set_global_assignment -name VERILOG_FILE hardware/system/Butterfly.v
+set_global_assignment -name VERILOG_FILE hardware/system/DelayBuffer.v
+set_global_assignment -name VERILOG_FILE hardware/system/FFT1024_32B.v
+set_global_assignment -name VERILOG_FILE hardware/system/Multiply.v
+set_global_assignment -name VERILOG_FILE hardware/system/SdfUnit2.v
+set_global_assignment -name VERILOG_FILE hardware/system/SdfUnit.v
+set_global_assignment -name VERILOG_FILE hardware/system/Twiddle1024_32B.v
+set_global_assignment -name VHDL_FILE hardware/system/squareRoot_pipe.vhd
+set_global_assignment -name VHDL_FILE hardware/system/fft_magnitude_calc.vhd
+set_global_assignment -name VHDL_FILE hardware/signal_processing/fft.vhd
+set_global_assignment -name VHDL_FILE hardware/system/task_fft.vhd
+
+set_global_assignment -name VHDL_FILE hardware/signal_processing/crc.vhd
+set_global_assignment -name VHDL_FILE hardware/system/task_crc.vhd
+
+set_global_assignment -name VHDL_FILE hardware/signal_processing/signal_processing.vhd

init.sh

+#!/bin/bash
+
+transfer=${HOME}/.info/Fak_EFI/Labore/System_Design/Systementwurf/Transfer/signal_processing_${USER}
+
+git init .
+git checkout -b master
+
+git config --global user.name "${USER}"
+git config --global user.email "${USER}@th-nuernberg.de"
+
+git add * 
+git commit -m "Initial commit"
+
+git remote remove origin
+git init --bare ${transfer}
+git remote add origin ${transfer}
+git push --set-upstream origin master
+
+

signal_processing.cdf

+/* Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Ign)
+		Device PartName(SOCVHPS) MfrSpec(OpMask(0));
+	P ActionCode(Cfg)
+		Device PartName(5CSEBA6U23) Path("output_files/") File("signal_processing.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;

signal_processing.qpf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 23:07:58  June 12, 2022
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "20.1"
+DATE = "23:07:58  June 12, 2022"
+
+# Revisions
+
+PROJECT_REVISION = "signal_processing"

signal_processing.qsf

+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2020  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions
+# and other software and tools, and any partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Intel Program License
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
+# Date created = 23:07:58  June 12, 2022
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		signal_processing_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSEBA6U23I7
+set_global_assignment -name TOP_LEVEL_ENTITY signal_processing
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:07:58  JUNE 12, 2022"
+set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_location_assignment PIN_V11 -to clk_input
+set_location_assignment PIN_AH17 -to reset_n
+
+set_location_assignment PIN_AA23 -to leds[7]
+set_location_assignment PIN_Y16 -to leds[6]
+set_location_assignment PIN_AE26 -to leds[5]
+set_location_assignment PIN_AF26 -to leds[4]
+set_location_assignment PIN_V15 -to leds[3]
+set_location_assignment PIN_V16 -to leds[2]
+set_location_assignment PIN_AA24 -to leds[1]
+set_location_assignment PIN_W15 -to leds[0]
+
+
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/data_channel_control.stp
+#set_global_assignment -name QSYS_FILE niosII.qsys
+
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
+
+set_global_assignment -name QIP_FILE niosII/synthesis/niosII.qip
+set_global_assignment -name QIP_FILE hardware/system/pll/pll_main.qip
+set_global_assignment -name SIP_FILE hardware/system/pll/pll_main.sip
+source hdl_sources.qsf
+
+set_global_assignment -name SDC_FILE hardware/signal_processing.sdc
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

software/signal_processing/.cproject

+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<buildSystem id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625">
+			<storageModule id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625" moduleId="org.eclipse.cdt.core.settings"/>
+		</buildSystem>
+		<cconfiguration id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625">
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration buildProperties="" description="" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625" name="Nios II" parent="org.eclipse.cdt.build.core.prefbase.cfg">
+					<folderInfo id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625." name="/" resourcePath="">
+						<toolChain id="altera.nios2.linux.gcc4.1436420066" name="Linux Nios II GCC4" superClass="altera.nios2.linux.gcc4">
+							<targetPlatform id="altera.nios2.linux.gcc4.1506303804" name="Nios II" osList="linux" superClass="altera.nios2.linux.gcc4"/>
+							<builder buildPath="${workspace_loc://signal_processing}" id="altera.tool.gnu.builder.1107813232" keepEnvironmentInBuildfile="false" managedBuildOn="false" name="Gnu Make Builder" superClass="altera.tool.gnu.builder"/>
+							<tool id="altera.tool.gnu.c.compiler.1149346695" name="Nios II GCC C Compiler" superClass="altera.tool.gnu.c.compiler">
+								<inputType id="cdt.managedbuild.tool.gnu.c.compiler.input.1301990062" superClass="cdt.managedbuild.tool.gnu.c.compiler.input"/>
+							</tool>
+							<tool id="altera.tool.gnu.cpp.compiler.423409496" name="Nios II GCC C++ Compiler" superClass="altera.tool.gnu.cpp.compiler">
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.compiler.input.1863230573" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.input"/>
+							</tool>
+							<tool id="altera.tool.gnu.archiver.1974628331" name="Nios II GCC Archiver" superClass="altera.tool.gnu.archiver"/>
+							<tool id="altera.tool.gnu.c.linker.164791439" name="Nios II GCC C Linker" superClass="altera.tool.gnu.c.linker"/>
+							<tool id="altera.tool.gnu.cpp.linker.425602587" name="Nios II GCC C++ Linker" superClass="altera.tool.gnu.cpp.linker">
+								<inputType id="cdt.managedbuild.tool.gnu.cpp.linker.input.947771420" superClass="cdt.managedbuild.tool.gnu.cpp.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="altera.tool.gnu.assembler.1629937142" name="Nios II GCC Assembler" superClass="altera.tool.gnu.assembler">
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.1175573843" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625" moduleId="org.eclipse.cdt.core.settings" name="Nios II">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="signal_processing.null.700250918" name="signal_processing"/>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625.;altera.tool.gnu.c.compiler.1149346695;cdt.managedbuild.tool.gnu.c.compiler.input.1301990062">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625;preference.org.eclipse.cdt.managedbuilder.core.configurationDataProvider.1578931625.;altera.tool.gnu.cpp.compiler.423409496;cdt.managedbuild.tool.gnu.cpp.compiler.input.1863230573">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets">
+		<buildTargets>
+			<target name="mem_init_install" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+				<buildCommand>make</buildCommand>
+				<buildArguments/>
+				<buildTarget>mem_init_install</buildTarget>
+				<stopOnError>true</stopOnError>
+				<useDefaultCommand>false</useDefaultCommand>
+				<runAllBuilders>false</runAllBuilders>
+			</target>
+			<target name="mem_init_generate" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+				<buildCommand>make</buildCommand>
+				<buildArguments/>
+				<buildTarget>mem_init_generate</buildTarget>
+				<stopOnError>true</stopOnError>
+				<useDefaultCommand>false</useDefaultCommand>
+				<runAllBuilders>false</runAllBuilders>
+			</target>
+			<target name="help" path="" targetID="org.eclipse.cdt.build.MakeTargetBuilder">
+				<buildCommand>make</buildCommand>
+				<buildArguments/>
+				<buildTarget>help</buildTarget>
+				<stopOnError>true</stopOnError>
+				<useDefaultCommand>false</useDefaultCommand>
+				<runAllBuilders>false</runAllBuilders>
+			</target>
+		</buildTargets>
+	</storageModule>
+</cproject>

software/signal_processing/.gitignore

+.settings/
+obj/
+readme.txt
+signal_processing.elf
+signal_processing.map
+signal_processing.objdump
+

software/signal_processing/.project

+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>signal_processing</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>com.altera.sbtgui.project.makefileBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.cdt.core.ccnature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUINature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIAppNature</nature>
+		<nature>com.altera.sbtgui.project.SBTGUIManagedNature</nature>
+	</natures>
+</projectDescription>

software/signal_processing/add.c

+#include "system/task_add.h"
+#include "system/data_channel.h"
+#include "system/float_word.h"
+
+int task_add_run( void * task ) {
+
+    // TODO
+
+    return 0;
+}
+

software/signal_processing/crc.c

+#include "system/task_crc.h"
+#include "system/data_channel.h"
+#include "system/float_word.h"
+
+int task_crc_run( void * task ) {
+
+    // TODO
+
+    return 0;
+}
+

software/signal_processing/fft.c

+#include "system/task_fft.h"
+#include "system/data_channel.h"
+#include "system/Complex.h"
+#include "system/float_word.h"
+
+int task_fft_run( void * task ) {
+
+    // TODO
+
+    return 0;
+}
+

software/signal_processing/main.c

+#include <stdio.h>
+#include <system.h>
+#include <inttypes.h>
+
+#include "system/binding.h"
+#include "system/signal_processing.h"
+
+int main()
+{
+    uint32_t bindings[ TASK_COUNT ] = {
+        BINDING_SW,
+        BINDING_SW,
+        BINDING_SW,
+        BINDING_SW,
+        BINDING_HW,
+        BINDING_SW,
+        BINDING_SW
+    };
+
+    SignalProcessing system;
+    signal_processing_init( & system, bindings );
+    signal_processing_run( & system );
+    signal_processing_print_results( & system );
+
+    return 0;
+}
+

software/signal_processing/rand.c

+#include "system/task_rand.h"
+#include "system/hardware_task.h"
+#include "system/data_channel.h"
+#include "system/float_word.h"
+
+int task_rand_run( void * task ) {
+
+    // TODO
+
+    return 0;
+}
+

software/signal_processing/sine.c

+#include "system/task_sine.h"
+#include "system/data_channel.h"
+#include "system/float_word.h"
+
+int task_sine_run( void * data ) {
+
+    // TODO
+
+    return 0;
+}

software/signal_processing/system/Complex.c

+#include "Complex.h"
+#include <math.h>
+
+float complex_abs( const Complex * c ) {
+    return sqrt( pow( c->re, 2 ) + pow( c->im, 2 ) );
+}
+
+float complex_arg( const Complex * a )
+{
+    return atan2( a->im, a->re );
+}
+
+Complex complex_comjunction( const Complex * a ) {
+    Complex c = { a->re, - a->im };
+    return c;
+}
+
+float complex_phi( const Complex * c ) {
+    float phi = 0.0;
+
+    // quadrant I
+    if ( c->re >= 0 && c->im >= 0 ) phi = atan( c->im / c->re );
+    // quadrant II, III
+    if ( c->re  < 0 ) phi = atan( c->im / c->re ) + M_PI;
+    // quadrant IV
+    if ( c->re  > 0 && c->im  < 0 ) phi = atan( c->im / c->re ) + 2 * M_PI;
+
+    return phi * 180.0 / M_PI;
+}
+
+Complex complex_scalar_mul( const Complex * a, const float b ) {
+    Complex c = { 0.0, 0.0 };
+    float o_re = b;
+    float o_im = 0.0;
+
+    c.re = a->re * o_re - a->im * o_im;
+    c.im = a->re * o_im + o_re * a->im;
+
+    return c;
+}
+
+Complex complex_mul( const Complex * a, const Complex * b ) {
+    Complex c = { 0.0, 0.0 };
+    float o_re = b->re;
+    float o_im = b->im;
+
+    c.re = a->re * o_re - a->im * o_im;
+    c.im = a->re * o_im + o_re * a->im;
+
+    return c;
+}
+
+Complex complex_add( const Complex * a, const Complex * b ) {
+    Complex c = { 0.0, 0.0 };
+    c.re = a->re + b->re;
+    c.im = a->im + b->im;
+
+    return c;
+}
+
+Complex complex_sub( const Complex * a, const Complex * b ) {
+    Complex c = { 0.0, 0.0 };
+    c.re = a->re - b->re;
+    c.im = a->im - b->im;
+
+    return c;
+}
+
+Complex complex_polar( float roh, float theta )
+{
+    Complex c = { roh * cos( theta ), roh * sin( theta ) };
+
+    return c;
+}
+
+Complex complex_pow( const Complex * a, int n )
+{
+    float roh   = pow( complex_abs( a ), n );
+    float theta = complex_arg( a );
+
+    return complex_polar( roh, ( float )( n ) * theta );
+}
+

software/signal_processing/system/Complex.h

+#pragma once
+
+typedef struct {
+    float re;
+    float im;
+} Complex;
+
+float complex_abs( const Complex * c );
+
+float complex_arg( const Complex * a );
+
+Complex complex_comjunction( const Complex * a );
+
+float complex_phi( const Complex * c );
+
+Complex complex_scalar_mul( const Complex * a, const float b );
+
+Complex complex_mul( const Complex * a, const Complex * b );
+
+Complex complex_add( const Complex * a, const Complex * b );
+
+Complex complex_sub( const Complex * a, const Complex * b );
+
+Complex complex_polar( float roh, float theta );
+
+Complex complex_pow( const Complex * a, int n );
+

software/signal_processing/system/add_config.h

+#pragma once
+
+#include "task_base_config.h"
+
+typedef task_base_config add_config;
+

software/signal_processing/system/binding.c

+#include "binding.h"
+#include "signal_processing.h"
+
+#include <stdio.h>
+
+static const char * BINDING_HW_STRING = "HW";
+static const char * BINDING_SW_STRING = "SW";
+static const char * UNKOWN_STRING = "UNKOWN_STRING";
+
+void binding_from_value( uint32_t value, uint32_t * binding ) {
+    for ( uint32_t i = 0; i < TASK_COUNT; ++i ) {
+        binding[ i ] = value & 1;
+        value >>= 1;
+    }
+}
+
+int binding_get_channel_binding( const uint32_t * connections,
+    const uint32_t * binding,
+    uint32_t n,
+    DataChannelBinding * channel_binding ) {
+
+    if ( n >= CHANNEL_COUNT ) {
+        printf( "ERROR in %s: %" PRIu32 " not a valid channel number\n",
+            __func__, n );
+        return 1;
+    }
+
+    channel_binding->sink = binding[ n ];
+    channel_binding->source = binding[ connections[ n ] ];
+
+    return 0;
+}
+
+const char * binding_to_string( uint32_t binding ) {
+    switch ( binding ) {
+    case BINDING_SW: return BINDING_SW_STRING;
+    case BINDING_HW: return BINDING_HW_STRING;
+    }
+
+    return UNKOWN_STRING;
+}
+

software/signal_processing/system/binding.h

+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <inttypes.h>
+
+enum {
+    BINDING_SW = 0,
+    BINDING_HW = 1
+};
+
+typedef struct {
+    uint32_t sink;
+    uint32_t source;
+} DataChannelBinding;
+
+void binding_from_value( uint32_t value, uint32_t * config );
+
+int binding_get_channel_binding( const uint32_t * connections,
+    const uint32_t * binding,
+    uint32_t n,
+    DataChannelBinding * channel_binding );
+
+const char * binding_to_string( uint32_t binding );
+
+
+#ifdef __cplusplus
+}
+#endif
+

software/signal_processing/system/crc_config.h

+#pragma once
+
+#include "task_base_config.h"
+
+typedef struct {
+    task_base_config base;
+    uint32_t start;
+} crc_config;

software/signal_processing/system/data_channel.c

+#include "data_channel.h"
+
+#include <system.h>
+#include <stdio.h>
+#include <io.h>
+
+const uint32_t DATA_CHANNEL_DEPTH = 1024;
+const uint32_t DATA_CHANNEL_COUNT = 7;
+
+const uint32_t DATA_CHANNEL_BASE_LIST[] = {
+    DATA_CHANNEL_0_BASE,
+    DATA_CHANNEL_1_BASE,
+    DATA_CHANNEL_2_BASE,
+    DATA_CHANNEL_3_BASE,
+    DATA_CHANNEL_4_BASE,
+    DATA_CHANNEL_5_BASE,
+    DATA_CHANNEL_6_BASE
+};
+
+#define REG_BINDING_OFFSET 0
+#define BINDING_SINK_POS 0
+#define BINDING_SOURCE_POS 1
+
+#define REG_EMPTY_OFFSET 1
+#define REG_FULL_OFFSET 2
+#define REG_LEVEL_OFFSET 3
+#define REG_SINK_OFFSET 4
+#define REG_SOURCE_OFFSET 5
+#define REG_CLEAR_OFFSET 6
+
+void data_channel_bind( uint32_t base, const DataChannelBinding * binding ) {
+
+    uint32_t value = binding->sink << BINDING_SINK_POS |
+        binding->source << BINDING_SOURCE_POS;
+
+    IOWR( base, REG_BINDING_OFFSET, value );
+}
+
+uint32_t data_channel_get_binding( uint32_t base ) {
+    return IORD( base, REG_BINDING_OFFSET );
+}
+
+uint32_t data_channel_is_empty( uint32_t base ) {
+    return IORD( base, REG_EMPTY_OFFSET );
+}
+
+uint32_t data_channel_is_full( uint32_t base ) {
+    return IORD( base, REG_FULL_OFFSET );
+}
+
+uint32_t data_channel_level( uint32_t base ) {
+    return IORD( base, REG_LEVEL_OFFSET );
+}
+
+void data_channel_clear( uint32_t base ) {
+    IOWR( base, REG_CLEAR_OFFSET, 1 );
+}
+
+int data_channel_write( uint32_t base, uint32_t value ) {
+    if ( data_channel_is_full( base ) ) {
+        return 1;
+    }
+    IOWR( base, REG_SINK_OFFSET, value );
+    return 0;
+}
+
+int data_channel_write_all( uint32_t base, const uint32_t * data, uint32_t len ) {
+    for ( uint32_t i = 0; i < len; ++i ) {
+        int ret = data_channel_write( base, data[ i ] );
+        if ( ret ) return ret;
+    }
+
+    return 0;
+}
+
+int data_channel_read( uint32_t base, uint32_t * value ) {
+    if ( data_channel_is_empty( base ) ) {
+        return 1;
+    }
+    * value = IORD( base, REG_SOURCE_OFFSET );
+    return 0;
+}
+
+int data_channel_read_all( uint32_t base, void * buffer ) {
+    int i;
+    for ( i = 0; i < DATA_CHANNEL_DEPTH; ++i ) {
+        int ret = data_channel_read( base, buffer + i );
+        if ( ret ) {
+            break;
+        }
+    }
+
+    return i;
+}
+
+uint32_t data_channel_base_from_number( uint32_t channel ) {
+    return DATA_CHANNEL_BASE_LIST[ channel ];
+}
+

software/signal_processing/system/data_channel.h

+#pragma once
+
+#include "binding.h"
+
+#include <inttypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint32_t DATA_CHANNEL_DEPTH;
+extern const uint32_t DATA_CHANNEL_COUNT;
+extern const uint32_t DATA_CHANNEL_BASE_LIST[];
+
+void data_channel_bind( uint32_t base, const DataChannelBinding * binding );
+
+uint32_t data_channel_get_binding( uint32_t base );
+
+uint32_t data_channel_is_empty( uint32_t base );
+uint32_t data_channel_is_full( uint32_t base );
+uint32_t data_channel_level( uint32_t base );
+
+void data_channel_clear( uint32_t base );
+
+int data_channel_write( uint32_t base, uint32_t value );
+int data_channel_write_all( uint32_t base, const uint32_t * data, uint32_t len );
+int data_channel_read( uint32_t base, uint32_t * value );
+int data_channel_read_all( uint32_t base, void * buffer );
+
+uint32_t data_channel_base_from_number( uint32_t channel );
+
+#ifdef __cplusplus
+}
+#endif
+

software/signal_processing/system/fft_config.h

+#pragma once
+
+#include "task_base_config.h"
+
+typedef struct {
+    task_base_config base;
+    float interval;
+} fft_config;
+

software/signal_processing/system/float_word.h

+#pragma once
+
+#include <inttypes.h>
+
+typedef union {
+    float value;
+    uint32_t word;
+} float_word;
+

software/signal_processing/system/hardware_task.c

+#include "hardware_task.h"
+
+#include <io.h>
+#include <stdio.h>
+
+
+#define REG_START_OFFSET 0
+#define START 1
+
+#define REG_STATE_OFFSET 1
+#define REG_CYCLE_COUNT_OFFSET 2
+#define REG_CONFIG_OFFSET 3
+
+void hardware_task_start( uint32_t base ) {
+    IOWR( base, REG_START_OFFSET, START );
+}
+
+uint32_t hardware_task_get_state( uint32_t base ) {
+    return IORD( base, REG_STATE_OFFSET );
+}
+
+uint32_t hardware_task_get_cycle_count( uint32_t base ) {
+    return IORD( base, REG_CYCLE_COUNT_OFFSET );
+}
+
+void hardware_task_set_config( uint32_t base, uint32_t offset, uint32_t value ) {
+    IOWR( base, REG_CONFIG_OFFSET + offset, value );
+}
+uint32_t hardware_task_get_config( uint32_t base, uint32_t offset ) {
+    return IORD( base, REG_CONFIG_OFFSET + offset );
+}
+

software/signal_processing/system/hardware_task.h

+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <inttypes.h>
+
+enum {
+    HARDWARE_TASK_IDLE = 0,
+    HARDWARE_TASK_RUNNING = 1,
+    HARDWARE_TASK_DONE = 2
+};
+
+void hardware_task_start( uint32_t base );
+
+uint32_t hardware_task_get_state( uint32_t base );
+
+uint32_t hardware_task_get_cycle_count( uint32_t base );
+
+void hardware_task_set_config( uint32_t base, uint32_t offset, uint32_t value );
+uint32_t hardware_task_get_config( uint32_t base, uint32_t offset );
+
+#ifdef __cplusplus
+}
+#endif
+

software/signal_processing/system/hardware_timestamp.c

+#include "hardware_timestamp.h"
+
+#include <io.h>
+
+#define REG_STATE_OFFSET 0
+#define STOPPED 0
+#define RUNNING 1
+
+#define REG_CYCLE_COUNT_OFFSET 1
+
+uint32_t hardware_timestamp_is_running( uint32_t base ) {
+    return IORD( base, REG_STATE_OFFSET ) == RUNNING;
+}
+
+uint32_t hardware_timestamp_is_stopped( uint32_t base ) {
+    return IORD( base, REG_STATE_OFFSET ) == STOPPED;
+}
+
+uint32_t hardware_timestamp( uint32_t base ) {
+    return IORD( base, REG_CYCLE_COUNT_OFFSET );
+}
+
+void hardware_timestamp_start( uint32_t base ) {
+    IOWR( base, REG_STATE_OFFSET, RUNNING );
+}
+
+void hardware_timestamp_stop( uint32_t base ) {
+    IOWR( base, REG_STATE_OFFSET, STOPPED );
+}
+

software/signal_processing/system/hardware_timestamp.h

+#pragma once
+
+#include <inttypes.h>
+
+uint32_t hardware_timestamp_is_running( uint32_t base );
+uint32_t hardware_timestamp_is_stopped( uint32_t base );
+uint32_t hardware_timestamp( uint32_t base );
+
+void hardware_timestamp_start( uint32_t base );
+void hardware_timestamp_stop( uint32_t base );

software/signal_processing/system/rand_config.h

+#pragma once
+
+#include "task_base_config.h"
+
+#include <inttypes.h>
+
+typedef struct {
+    task_base_config base;
+    float seed;
+    float abs_min;
+    float abs_max;
+} rand_config;
+