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2 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
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c90753aa23 | ||
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5efb80253b |
@ -1,13 +1,26 @@
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------------------------------------------------------------------------
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-- fft
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--
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-- calculation of FFT magnitude
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-- calculation of FFT magnitudes
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--
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-- Inputs:
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-- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
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--
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-- Outputs
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-- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
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--
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--
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-- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor
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-- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist)
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-- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln
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-- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0)
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-- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich)
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-- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float)
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-- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32).
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-- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist)
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-- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html)
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-- (z.B: ein Array verwenden, um die Werte zu sortieren)
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-- Dann das Ergebnis in den Ausgangsfifo speichern
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--
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-----------------------------------------------------------------------
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library ieee;
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@ -22,10 +35,10 @@ library work;
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entity fft is
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generic (
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-- input data width of real/img part
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-- input data width of real/img part
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input_data_width : integer := 32;
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-- output data width of real/img part
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-- output data width of real/img part
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output_data_width : integer := 32
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);
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@ -35,10 +48,10 @@ entity fft is
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task_start : in std_logic;
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task_state : out work.task.State;
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signal_read : out std_logic;
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signal_readdata : in std_logic_vector( 31 downto 0 );
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector( 31 downto 0 )
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);
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@ -46,12 +59,103 @@ end entity fft;
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architecture rtl of fft is
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-- Signale für Task State Machine
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--signal index : integer range 0 to 2000;
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-- component des Verilog IP-Cores fuer die FFT
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component fftmain is
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port(
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clock: in std_logic; -- Master Clock
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reset: in std_logic; -- Active High Asynchronous Reset
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di_en: in std_logic; -- Input Data Enable
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di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
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di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
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do_en: out std_logic; -- Output Data Enable
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do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
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do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
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);
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end component;
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-- Signale Input skaliert
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signal fft_float_input : signed( 31 downto 0 );
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signal fft_float_scaled_input : signed( 31 downto 0 );
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-- Signale fuer FFT-IP Core
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-- fft data input signal
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signal fft_input_data_enable: std_logic;
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signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
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signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
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-- fft output data
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signal fft_output_valid : std_logic;
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signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
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signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
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-- Signale fuer Magnitude IP-Core
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signal fft_mag_calc_valid : std_logic;
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signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
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-- Signale fuer Ergebnis skaliert
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signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);
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signal fft_float_scaled : signed( 31 downto 0 );
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-- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
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signal data_memory : work.reg32.RegArray( 0 to 1023 );
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signal index_reversed : std_logic_vector(9 downto 0);
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signal index_output_sv : std_logic_vector(9 downto 0);
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signal index_output : integer range 0 to 1023;
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-- Signal um in den Write FIFO zu schreiben
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signal wr_fifo : std_logic;
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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-----------------------------------------------------------------------------------------------
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-- Hier muss der Verilog FFT IP-Core instanziert werden
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-----------------------------------------------------------------------------------------------
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--u_fft : fftmain
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-- port map (
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-- clock => , -- system clock
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-- reset => , -- Active High Asynchronous Reset
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-- di_en => , -- Input Data Enable
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-- di_re => , -- Input Data (Real)
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-- di_im => , -- Input Data (Imag)
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-- do_en => , -- Output Data Enable
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-- do_re => , -- Output Data (Real)
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-- do_im => -- Output Data (Imag)
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-- );
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fft_output_valid <= '0';
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data_out_re <= (others => '0');
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data_out_im <= (others => '0');
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-----------------------------------------------------------------------------------------------
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-- Hier muss der VHDL Magnitue IP-COre instanziert werden
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-----------------------------------------------------------------------------------------------
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-- u_fft_mag_calc : entity work.fft_magnitude_calc
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-- port map (
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-- clk => , -- system clock
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-- reset => , -- Active High Asynchronous Reset
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-- input_valid => , -- Input Data Valid
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-- input_re => , -- Input Realteil in Fixpoint format
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-- input_im => , -- Input Imaginaerteil in Fixpoint format
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-- output_valid => , -- Output Data Valid
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-- output_magnitude => -- Magnitude Output in Fixpoint format
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-- );
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fft_mag_calc_valid <= '1' when index = 0 else '0';
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fft_mag_calc_result <= (others => '0');
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-----------------------------------------------------------------------------------------------
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-- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
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-----------------------------------------------------------------------------------------------
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task_state_transitions : process (all) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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@ -60,7 +164,7 @@ begin
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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if ( index = 2 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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@ -70,28 +174,157 @@ begin
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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-----------------------------------------------------------------------------------------------
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-- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
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-----------------------------------------------------------------------------------------------
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-- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
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-----------------------------------------------------------------------------------------------
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-- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
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-----------------------------------------------------------------------------------------------
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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wr_fifo <= '0';
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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wr_fifo <= '0';
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_IDLE =>
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index <= 0;
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when work.task.TASK_RUNNING =>
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-- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
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-- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
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if ( index_output = work.task.STREAM_LEN - 1 ) then
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index <= index + 1;
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end if;
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if index = 1 then
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wr_fifo <= '1';
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end if;
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when work.task.TASK_DONE => null;
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end case;
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end if;
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end process sync;
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end process sync;
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task_state <= current_task_state;
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-----------------------------------------------------------------------------------------------
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--
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-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
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-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
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-- und im naechsten Takt schon weiter verarbeitet werden können
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--
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-- Erforderliches Scaling:
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--
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-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
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-- multiplication is a simple addition of the exponents.
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-- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
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-- This means an divsion through 16 -> exponent needs an addition of - 4
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--
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-- fft_float_input = gelesener Wert vom FIFO (floating point)
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-- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
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-- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
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-----------------------------------------------------------------------------------------------
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fft_float_input <= signed(signal_readdata);
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fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden
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-----------------------------------------------------------------------------------------------
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--
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-- Skalierung der Eingangswerte welche vom FIFO gelesen werden
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-- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
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-- und im naechsten Takt schon weiter verarbeitet werden können
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--
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-- Erforderliches Scaling:
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--
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-- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
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-- multiplication is a simple addition of the exponents.
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-- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16
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-- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
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-- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
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-- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
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--
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-- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
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-- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
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-----------------------------------------------------------------------------------------------
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data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
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fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
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-----------------------------------------------------------------------------------------------
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-- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
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-- Umordnung der Ausgangswerte erfolgen
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--
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-- index_output_sv = std_logic_vector des Integer Ausgangsindex
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-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
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--
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c_index_output_sv:
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index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
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c_reversed_index:
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index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
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-----------------------------------------------------------------------------------------------
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-- Prozess steuert das hochzaehlen des Ausgang Index
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-----------------------------------------------------------------------------------------------
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p_number_output_sample: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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index_output <= 0;
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elsif ( rising_edge( clk ) ) then
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-- Ruecksetz Bedingung für index_output
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if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
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index_output <= 0;
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-- index_output hochzaehlen um in natural order im array zu speichern
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elsif fft_mag_calc_valid = '1' then
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index_output <= index_output + 1;
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-- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
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elsif wr_fifo = '1' then
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index_output <= index_output + 1;
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end if;
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end if;
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end process p_number_output_sample;
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-----------------------------------------------------------------------------------------------
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-- Prozess speichert das skalierte Endergbenis iun der natural order
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-----------------------------------------------------------------------------------------------
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p_output2float_memory: process ( clk, reset) is
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begin
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if ( reset = '1' ) then
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null;
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elsif ( rising_edge( clk ) ) then
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if fft_mag_calc_valid = '1' then
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data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
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end if;
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end if;
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end process p_output2float_memory;
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-----------------------------------------------------------------------------------------------
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-- Schreiben der berechneten Werte in den FIFO
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-----------------------------------------------------------------------------------------------
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p_output_fifo: process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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signal_writedata <= (others => '0');
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signal_write <= '0';
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elsif ( rising_edge( clk ) ) then
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signal_write <= '0';
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if wr_fifo = '1' then
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signal_writedata <= data_memory(index_output);
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signal_write <= '1';
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end if;
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end if;
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end process p_output_fifo;
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-- Hier sollen die sonstigen benoetigten Anweisungen stehen
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task_state <= current_task_state;
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end architecture rtl;
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@ -26,37 +26,7 @@ architecture rtl of rand is
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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--Signale anlegen:
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signal data_valid_intern : std_logic; --um skalieren zu gehen
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--signal angle_intern : signed(31 downto 0);
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--signal busy_intern : std_logic;
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--signal result_valid_intern : std_logic;
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--signal sine_intern : signed(31 downto 0);
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--State Machine anlegen:
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type CalcState is(
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CALC_IDLE,
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CALC_RANDOMISIEREN,--2) neuen Randomwert berechnen
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--(dauert einige Takte)
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CALC_SKALIEREN,--3) den berechneten Wert skalieren
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CALC_IN_FIFO_ABSPEICHERN); --4) im FIFO abspeichern
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signal current_calc_state : CalcState;
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signal next_calc_state : CalcState;
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begin
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--IP-Core instanzieren und entsprechende Signale verbinden:
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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@ -76,69 +46,11 @@ begin
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end case;
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end process task_state_transitions;
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--ZUSTANDSMASCHINE:
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calc_state_transitions : process (all) is
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begin
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next_calc_state <= current_calc_state;
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case current_calc_state is
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when CALC_IDLE =>
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if(current_task_state = work.task.TASK_RUNNING) then
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next_calc_state <= CALC_RANDOMISIEREN;
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end if;
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when CALC_RANDOMISIEREN =>
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--if(result_valid_intern = '1' and busy_intern = '0') then--busy_intern = '0'
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if(data_valid_intern = '1') then
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next_calc_state <= CALC_SKALIEREN;
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end if;
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when CALC_SKALIEREN =>
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next_calc_state <= CALC_IN_FIFO_ABSPEICHERN;
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when CALC_IN_FIFO_ABSPEICHERN =>
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next_calc_state <= CALC_RANDOMISIEREN;
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if(index = 1024) then
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next_calc_state <= CALC_IDLE;
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end if;
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end case;
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end process calc_state_transitions;
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sync : process ( clk, reset ) is
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--VARIABLEN:
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VARIABLE randomisiert : signed ( 31 downto 0 );
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VARIABLE scaled : signed ( 31 downto 0 );
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random_number_word : std_logic_vector(31 downto 0);
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variable mask_bit_0 : std_logic_vector(31 downto 0);
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variable mask_bit_1 : std_logic_vector(31 downto 0);
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variable mask_bit_21 : std_logic_vector(31 downto 0);
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variable mask_bit_31 : std_logic_vector(31 downto 0);
|
||||
variable xor_result : std_logic_vector(0 downto 0);
|
||||
variable shifted : std_logic_vector(31 downto 0);
|
||||
|
||||
variable exponent : std_logic_vector(7 downto 0);
|
||||
variable shifted_modified : std_logic_vector(31 downto 0);
|
||||
variable shifted_exponent : std_logic_vector(31 downto 0);
|
||||
variable shifted_modifiziert : std_logic_vector(31 downto 0);
|
||||
|
||||
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
current_task_state <= work.task.TASK_IDLE;
|
||||
index <= 0;
|
||||
|
||||
--START VALUES:
|
||||
randomisiert := (others => '0');
|
||||
data_valid_intern <= '0';
|
||||
signal_write <= '0';
|
||||
signal_writedata <= ( others => '0' );
|
||||
|
||||
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
current_task_state <= next_task_state;
|
||||
case next_task_state is
|
||||
@ -153,102 +65,9 @@ begin
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
end case;
|
||||
|
||||
|
||||
|
||||
--ZUSTANDSMACHINE LOGIK:
|
||||
--A:
|
||||
current_calc_state <= next_calc_state;
|
||||
data_valid_intern <= '0';
|
||||
signal_write <= '0';
|
||||
case next_calc_state is
|
||||
when CALC_IDLE =>
|
||||
--angle_intern <= (others => '0');
|
||||
index <= 0;
|
||||
when CALC_RANDOMISIEREN =>
|
||||
|
||||
randomisiert := 5;
|
||||
|
||||
if (index == 0) then
|
||||
random_number_word := seed;
|
||||
end if;
|
||||
|
||||
-- Bits extrahieren und XOR durchführen
|
||||
bit_0 := random_number_word(0) and mask_bit_0(0);
|
||||
bit_1 := random_number_word(1) and mask_bit_1(1);
|
||||
bit_21 := random_number_word(21) and mask_bit_21(21);
|
||||
bit_31 := random_number_word(31) and mask_bit_31(31);
|
||||
|
||||
xor_result := bit_0 xor bit_1 xor bit_21 xor bit_31;
|
||||
|
||||
-- Shift um 1 nach rechts
|
||||
shifted := random_number_word(30 downto 0) & '0';
|
||||
shifted(31) := xor_result(0); -- XOR-Ergebnis an das MSB (Bit 31) setzen
|
||||
|
||||
-- Ergebnis ausgeben
|
||||
shifted_result <= shifted;
|
||||
|
||||
|
||||
data_valid_intern <= '1';
|
||||
when CALC_SKALIEREN =>
|
||||
--if(result_valid_intern = '1') then
|
||||
scaled := randomisiert;
|
||||
--scaled := 6;
|
||||
--randomisiert(30 downto 23) := randomisiert(30 downto 23) + ( signed(amplitude(30 downto 23)) - 127);
|
||||
|
||||
--end if;
|
||||
|
||||
|
||||
|
||||
-- Exponent extrahieren
|
||||
exponent := shifted_result(30 downto 23);
|
||||
-- Überprüfen, ob das 7. Bit des Exponenten gesetzt ist
|
||||
if (exponent(7) = '1') then
|
||||
exponent := exponent and "10000001";
|
||||
else
|
||||
exponent := exponent or "01111100";
|
||||
end if;
|
||||
|
||||
-- Verschiebung vorbereiten
|
||||
shifted_modified := shifted_result;
|
||||
shifted_exponent := ('0' & exponent) & (others => '0');
|
||||
|
||||
-- Verschiedene Teile kombinieren
|
||||
shifted_modifiziert := shifted_modified and x"807FFFFF";
|
||||
shifted_modifiziert := shifted_modifiziert or shifted_exponent;
|
||||
|
||||
-- Ergebnis ausgeben
|
||||
scaled_modified_result <= shifted_modifiziert;
|
||||
|
||||
|
||||
|
||||
|
||||
when CALC_IN_FIFO_ABSPEICHERN =>
|
||||
|
||||
if(index > 1) then
|
||||
signal_writedata <= std_logic_vector(scaled);
|
||||
end if;
|
||||
|
||||
signal_write <= '1';
|
||||
|
||||
index <= index + 1;
|
||||
end case;
|
||||
--E
|
||||
|
||||
|
||||
|
||||
|
||||
end if;
|
||||
end process sync;
|
||||
|
||||
task_state <= current_task_state;
|
||||
|
||||
end architecture rtl;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -28,48 +28,9 @@ architecture rtl of sine is
|
||||
|
||||
signal current_task_state : work.task.State;
|
||||
signal next_task_state : work.task.State;
|
||||
signal index : integer range 1 to 1025;
|
||||
|
||||
--Signale anlegen:
|
||||
signal data_valid_intern : std_logic;
|
||||
signal angle_intern : signed(31 downto 0);
|
||||
signal busy_intern : std_logic;
|
||||
signal result_valid_intern : std_logic;
|
||||
signal sine_intern : signed(31 downto 0);
|
||||
signal count : INTEGER RANGE 1 TO 1025;
|
||||
|
||||
|
||||
|
||||
|
||||
type CalcState is(
|
||||
CALC_IDLE,
|
||||
CALC_ZUWEISEN,--1) dem IP-Core einen neuen angle Wert zuführen
|
||||
CALC_WARTEN,--2) warten bis dieser einen neuen Sinuswert berechnet hat
|
||||
--(dauert einige Takte - Hinweis result_valid und busy Signale des IP-Cores)
|
||||
CALC_SKALIEREN,--3) den berechneten Wert skalieren
|
||||
CALC_IN_FIFO_ABSPEICHERN); --4) im FIFO abspeichern
|
||||
|
||||
signal current_calc_state : CalcState;
|
||||
signal next_calc_state : CalcState;
|
||||
|
||||
signal index : integer range 0 to work.task.STREAM_LEN;
|
||||
|
||||
begin
|
||||
|
||||
--IP-Core instanzieren und entsprechende Signale verbinden:
|
||||
u_float_sine: entity work.float_sine
|
||||
generic map (
|
||||
ITERATIONS => 8
|
||||
)
|
||||
port map (
|
||||
clk => clk,
|
||||
reset => reset,
|
||||
data_valid => data_valid_intern,
|
||||
angle => angle_intern,
|
||||
busy => busy_intern,
|
||||
result_valid => result_valid_intern,
|
||||
sine => sine_intern
|
||||
);
|
||||
|
||||
task_state_transitions : process ( current_task_state, task_start, index ) is
|
||||
begin
|
||||
next_task_state <= current_task_state;
|
||||
@ -79,7 +40,7 @@ begin
|
||||
next_task_state <= work.task.TASK_RUNNING;
|
||||
end if;
|
||||
when work.task.TASK_RUNNING =>
|
||||
if ( index = work.task.STREAM_LEN ) then
|
||||
if ( index = work.task.STREAM_LEN - 1 ) then
|
||||
next_task_state <= work.task.TASK_DONE;
|
||||
end if;
|
||||
when work.task.TASK_DONE =>
|
||||
@ -89,88 +50,25 @@ begin
|
||||
end case;
|
||||
end process task_state_transitions;
|
||||
|
||||
|
||||
calc_state_transitions : process (all) is
|
||||
begin
|
||||
next_calc_state <= current_calc_state;
|
||||
case current_calc_state is
|
||||
when CALC_IDLE =>
|
||||
if(current_task_state = work.task.TASK_RUNNING) then
|
||||
next_calc_state <= CALC_ZUWEISEN;
|
||||
end if;
|
||||
when CALC_ZUWEISEN =>
|
||||
next_calc_state <= CALC_WARTEN;
|
||||
when CALC_WARTEN =>
|
||||
if(result_valid_intern = '1' and busy_intern = '0') then--busy_intern = '0'
|
||||
next_calc_state <= CALC_SKALIEREN;
|
||||
end if;
|
||||
when CALC_SKALIEREN =>
|
||||
next_calc_state <= CALC_IN_FIFO_ABSPEICHERN;
|
||||
when CALC_IN_FIFO_ABSPEICHERN =>
|
||||
next_calc_state <= CALC_ZUWEISEN;
|
||||
|
||||
if(index = 1024) then
|
||||
next_calc_state <= CALC_IDLE;
|
||||
end if;
|
||||
end case;
|
||||
end process calc_state_transitions;
|
||||
|
||||
|
||||
sync : process ( clk, reset ) is
|
||||
|
||||
|
||||
VARIABLE sine_scaled : signed ( 31 downto 0 );
|
||||
|
||||
begin
|
||||
if ( reset = '1' ) then
|
||||
current_task_state <= work.task.TASK_IDLE;
|
||||
index <= 1;
|
||||
count <= 1;
|
||||
sine_scaled := (others => '0');
|
||||
data_valid_intern <= '0';
|
||||
signal_write <= '0';
|
||||
signal_writedata <= ( others => '0' );
|
||||
index <= 0;
|
||||
elsif ( rising_edge( clk ) ) then
|
||||
current_task_state <= next_task_state;
|
||||
case next_task_state is
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
when work.task.TASK_RUNNING =>
|
||||
index <= index + 1;
|
||||
signal_write <= '1';
|
||||
signal_writedata <= ( others => '0' );
|
||||
when work.task.TASK_DONE =>
|
||||
index <= 0;
|
||||
signal_write <= '0';
|
||||
end case;
|
||||
|
||||
--A:
|
||||
current_calc_state <= next_calc_state;
|
||||
data_valid_intern <= '0';
|
||||
signal_write <= '0';
|
||||
case next_calc_state is
|
||||
when CALC_IDLE =>
|
||||
angle_intern <= (others => '0');
|
||||
count <= 1;
|
||||
when CALC_ZUWEISEN =>
|
||||
--if(index > 1) then
|
||||
angle_intern <= angle_intern + signed(step_size);
|
||||
--end if;
|
||||
data_valid_intern <= '1';
|
||||
when CALC_WARTEN =>
|
||||
when CALC_SKALIEREN =>
|
||||
--if(result_valid_intern = '1') then
|
||||
sine_scaled := sine_intern;
|
||||
sine_scaled(30 downto 23) := sine_scaled(30 downto 23) + ( signed(amplitude(30 downto 23)) - 127);
|
||||
|
||||
--end if;
|
||||
when CALC_IN_FIFO_ABSPEICHERN =>
|
||||
|
||||
if(index > 1) then
|
||||
signal_writedata <= std_logic_vector(sine_scaled);
|
||||
end if;
|
||||
|
||||
signal_write <= '1';
|
||||
|
||||
index <= index + 1;
|
||||
count <= count + 1;
|
||||
end case;
|
||||
--E
|
||||
|
||||
end if;
|
||||
end process sync;
|
||||
|
||||
|
||||
@ -3,78 +3,10 @@
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
|
||||
#include <stdio.h>
|
||||
int task_rand_run( void * task ) {
|
||||
|
||||
int task_rand_run( void * data )
|
||||
{
|
||||
// TODO
|
||||
|
||||
rand_config * task = ( rand_config * ) data;
|
||||
|
||||
|
||||
uint32_t data_channel_base = task->base.sink;
|
||||
|
||||
float seed = task->seed; //1.3
|
||||
float abs_min = task->abs_min; //0.125
|
||||
float abs_max = task->abs_max; //9.0
|
||||
|
||||
float_word random_number;
|
||||
random_number.value = seed;
|
||||
|
||||
uint32_t mask_bit_0 = 0x1;
|
||||
uint32_t mask_bit_1 = 0x2;
|
||||
uint32_t mask_bit_21 = 0x200000;
|
||||
uint32_t mask_bit_31 = 0x80000000;
|
||||
|
||||
uint32_t exponent = 0;
|
||||
uint32_t shifted_exponent = 0;
|
||||
uint32_t shifted = 0;
|
||||
uint32_t shifted_modifiziert = 0;
|
||||
|
||||
data_channel_clear( data_channel_base );
|
||||
|
||||
for(uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i)
|
||||
{
|
||||
|
||||
//Bits extrahieren:
|
||||
uint32_t bit_0 = (random_number.word & mask_bit_0) >> 0;
|
||||
uint32_t bit_1 = (random_number.word & mask_bit_1) >> 1;
|
||||
uint32_t bit_21 = (random_number.word & mask_bit_21) >> 21;
|
||||
uint32_t bit_31 = (random_number.word & mask_bit_31) >> 31;
|
||||
|
||||
//XOR:
|
||||
uint32_t xor_result = bit_0 ^ bit_1 ^ bit_21 ^ bit_31;
|
||||
|
||||
//Shifted:
|
||||
shifted = random_number.word >> 1;
|
||||
|
||||
//shifted &= ~(0x80000000);
|
||||
shifted |= (xor_result << 31);
|
||||
|
||||
printf("%08x %08x %d \n", random_number.word, shifted, xor_result);
|
||||
|
||||
//Skalierung:
|
||||
#if 1
|
||||
exponent = (shifted >> 23) & 0xFF;
|
||||
if(exponent & (1 << 7)){
|
||||
exponent &= (0b10000001);
|
||||
}else{
|
||||
exponent |= (0b01111100);
|
||||
}
|
||||
|
||||
|
||||
shifted_modifiziert = shifted;
|
||||
shifted_exponent = exponent << 23;
|
||||
shifted_modifiziert &= 0x807FFFFF;
|
||||
shifted_modifiziert |= shifted_exponent;
|
||||
#endif
|
||||
|
||||
random_number.word = shifted_modifiziert;
|
||||
data_channel_write( data_channel_base, random_number.word );
|
||||
random_number.word = shifted;
|
||||
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
@ -2,54 +2,9 @@
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
|
||||
#include <math.h>
|
||||
|
||||
int task_sine_run( void * data ) {
|
||||
|
||||
sine_config * task = ( sine_config * ) data;
|
||||
|
||||
// TODO
|
||||
|
||||
|
||||
uint32_t data_channel_base = task->base.sink;
|
||||
|
||||
uint32_t samples_per_periode = task->samples_per_periode;
|
||||
float phase = task->phase;
|
||||
float amplitude = task->amplitude;
|
||||
|
||||
|
||||
|
||||
data_channel_clear( data_channel_base );
|
||||
#if 0
|
||||
|
||||
for (uint32_t i = 0; i < (DATA_CHANNEL_DEPTH/samples_per_periode); ++i)
|
||||
{
|
||||
|
||||
for(uint32_t j = 0; j < (samples_per_periode); ++j)
|
||||
{
|
||||
|
||||
float_word res;
|
||||
res.value = amplitude * sin((2.0*M_PI/samples_per_periode) * j + phase);
|
||||
|
||||
|
||||
|
||||
data_channel_write( data_channel_base, res.word );
|
||||
}
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i)
|
||||
{
|
||||
|
||||
float_word res;
|
||||
res.value = amplitude * sin((2.0*M_PI/samples_per_periode) * i + phase);
|
||||
|
||||
|
||||
|
||||
data_channel_write( data_channel_base, res.word );
|
||||
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -11,6 +11,8 @@ verilog_srcs = \
|
||||
vhdl_srcs = \
|
||||
../../../hardware/system/reg32.vhd \
|
||||
../../../hardware/system/avalon_slave.vhd \
|
||||
../test_utility.vhd \
|
||||
../test_avalon_slave.vhd \
|
||||
../../hardware/test_data_channel.vhd \
|
||||
../../../hardware/system/avalon_slave_transitions.vhd \
|
||||
../../../hardware/system/task.vhd \
|
||||
|
||||
@ -63,7 +63,7 @@ architecture test of test_task_fft is
|
||||
variable writedata_float : float32;
|
||||
variable writedata_real : real;
|
||||
variable expected_real : real;
|
||||
variable abs_err : real := 0.5e-1;
|
||||
variable abs_err : real := 0.6;
|
||||
variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
|
||||
variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
|
||||
file data_file : text;
|
||||
@ -110,11 +110,13 @@ architecture test of test_task_fft is
|
||||
std.textio.write( data_file_fft, "]" & LF );
|
||||
file_close( data_file_fft );
|
||||
|
||||
index := 0;
|
||||
while index < STREAM_LEN loop
|
||||
writedata_float := to_float( result( index ) );
|
||||
writedata_real := to_real( writedata_float );
|
||||
expected_real := work.fft_data.expected( index );
|
||||
assert_near( writedata_real, expected_real, abs_err );
|
||||
index := index + 1;
|
||||
end loop;
|
||||
|
||||
file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );
|
||||
|
||||
@ -1 +1,2 @@
|
||||
add wave -position end sim:/test_task_fft/dut/*
|
||||
add wave -position end sim:/test_task_fft/dut/u_fft/*
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user