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crc staengert

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allamaaki80515
2025-12-23 10:56:59 +01:00
parent 73c0f540b4
commit 44296a640b
234 changed files with 14685 additions and 147 deletions
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hardware/signal_processing/add.vhd
+128 -96
View File
@@ -8,155 +8,187 @@ library work;
entity add is
port (
clk : in std_logic;
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
signal_a_read : out std_logic;
signal_a_readdata : in std_logic_vector( 31 downto 0 );
signal_a_read : out std_logic;
signal_a_readdata : in std_logic_vector(31 downto 0);
signal_b_read : out std_logic;
signal_b_readdata : in std_logic_vector( 31 downto 0 );
signal_b_read : out std_logic;
signal_b_readdata : in std_logic_vector(31 downto 0);
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
signal_write : out std_logic;
signal_writedata : out std_logic_vector(31 downto 0)
);
end entity add;
u_add: entity word.add
port map (
clk => clk,
reset => reset,
task_start => task_start,
task_state => task_state,
signal_a_read => signal_a_read,
signal_a_readdata => signal_a_readdata,
signal_b_read => signal_b_read,
signal_b_readdata => signal_b_readdata,
signal_write => signal_write,
signal_writedata => signal_writedata
);
architecture rtl of add is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal start_proc : integer range 0 to 7;
signal state : integer range 0 to 255;
signal reset : integer range 0 to 7;
signal start : integer range 0 to 7;
signal done : integer range 0 to 7;
signal A : STD_LOGIC_VECTOR(31 downto 0);
signal B : STD_LOGIC_VECTOR(31 downto 0);
signal sum : STD_LOGIC_VECTOR(31 downto 0);
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
type AddState is (
ADD_IDLE,
ADD_READ_FIFO,
ADD_LATCH_INPUTS,
ADD_START_CALC,
ADD_WAIT_DONE,
ADD_STORE_RESULT
);
signal current_add_state : AddState;
signal next_add_state : AddState;
signal start_proc : std_logic;
signal done : std_logic;
signal A : std_logic_vector(31 downto 0);
signal B : std_logic_vector(31 downto 0);
signal sum : std_logic_vector(31 downto 0);
begin
u_float_add : entity work.float_add
port map (
clk => clk,
clk => clk,
reset => reset,
start => start_proc,
done => done,
A => signal_a_readdata,
B => signal_b_readdata,
sum => sum
done => done,
A => A,
B => B,
sum => sum
);
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
perform_add : process ( clk, reset ) is
add_state_transitions : process ( current_add_state, current_task_state, done ) is
begin
if (start_proc = '1' or reset = '1' ) then
signal_a_read <= '0';
signal_b_read <= '0';
else if (rising_edge(clk)) then
case state is
when 0 =>
start <= '1';
signal_a_read <= '1';
A <= signal_a_readdata;
signal_b_read <= '1';
B <= signal_b_readdata;
if( done = '1' ) then
signal_a_read <= '0';
signal_b_read <= '0';
state <= '2';
next_add_state <= current_add_state;
if (current_task_state /= work.task.TASK_RUNNING) then
next_add_state <= ADD_IDLE;
else
case current_add_state is
when ADD_IDLE =>
next_add_state <= ADD_READ_FIFO;
when ADD_READ_FIFO =>
next_add_state <= ADD_LATCH_INPUTS;
when ADD_LATCH_INPUTS =>
next_add_state <= ADD_START_CALC;
when ADD_START_CALC =>
next_add_state <= ADD_WAIT_DONE;
when ADD_WAIT_DONE =>
if done = '1' then
next_add_state <= ADD_STORE_RESULT;
end if;
when 2 =>
when ADD_STORE_RESULT =>
next_add_state <= ADD_READ_FIFO;
end case;
end if;
end case;
end process perform_add;
end process;
sync : process ( clk, reset ) is
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
signal_a_read <= 'O';
signal_b_read <= 'O';
signal_write <= 'O';
signal_Writedata <= (others => '0');
index <= 0;
state <= 0;
sum <= 0;
done <= 0;
start <= 0;
index <= 0;
current_add_state <= ADD_IDLE;
signal_a_read <= '0';
signal_b_read <= '0';
signal_write <= '0';
signal_writedata <= (others => '0');
start_proc <= '0';
A <= (others => '0');
B <= (others => '0');
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
current_add_state <= next_add_state;
signal_a_read <= '0';
signal_b_read <= '0';
signal_write <= '0';
start_proc <= '0';
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
start_proc <= '1';
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_IDLE =>
index <= 0;
when work.task.TASK_RUNNING =>
if current_add_state = ADD_STORE_RESULT then
index <= index + 1;
end if;
when work.task.TASK_DONE =>
index <= 0;
end case;
case next_add_state is
when ADD_IDLE =>
null;
when ADD_READ_FIFO =>
signal_a_read <= '1';
signal_b_read <= '1';
when ADD_LATCH_INPUTS =>
A <= signal_a_readdata;
B <= signal_b_readdata;
when ADD_START_CALC =>
start_proc <= '1';
when ADD_WAIT_DONE =>
start_proc <= '1';
null;
when ADD_STORE_RESULT =>
signal_write <= '1';
signal_writedata <= sum;
end case;
end if;
end process sync;
task_state <= current_task_state;
end architecture rtl;
hardware/signal_processing/crc.vhd
+79 -35
View File
@@ -8,69 +8,113 @@ library work;
entity crc is
port (
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
signal_read : out std_logic;
signal_readdata : in std_logic_vector( 31 downto 0 );
signal_write : out std_logic;
signal_writedata : out std_logic_vector( 31 downto 0 )
clk : in std_logic;
reset : in std_logic;
task_start : in std_logic;
task_state : out work.task.State;
signal_read : out std_logic;
signal_readdata : in std_logic_vector(31 downto 0);
signal_write : out std_logic;
signal_writedata: out std_logic_vector(31 downto 0)
);
end entity crc;
architecture rtl of crc is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN := 0;
constant CRC_INIT : std_logic_vector(31 downto 0) := X"FFFFFFFF";
constant CRC_POLY : std_logic_vector(31 downto 0) := X"EDB88320";
signal crc : std_logic_vector(31 downto 0) := CRC_INIT;
signal data_reg : std_logic_vector(31 downto 0);
signal data_valid : std_logic := '0';
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
task_state <= current_task_state;
-- TASK STATE MACHINE (VORLAGE - nicht ändern!)
task_state_transitions: process(current_task_state, task_start, index)
begin
next_task_state <= current_task_state;
case current_task_state is
when work.task.TASK_IDLE =>
if ( task_start = '1' ) then
if task_start = '1' then
next_task_state <= work.task.TASK_RUNNING;
end if;
when work.task.TASK_RUNNING =>
if ( index = work.task.STREAM_LEN - 1 ) then
-- WICHTIG: Schreiben nach 1024 Werten (index 0-1023)
if index = 1023 then
next_task_state <= work.task.TASK_DONE;
end if;
when work.task.TASK_DONE =>
if ( task_start = '1' ) then
if task_start = '1' then
next_task_state <= work.task.TASK_RUNNING;
end if;
end case;
end process task_state_transitions;
end process;
sync : process ( clk, reset ) is
-- Data Channel Control
signal_read <= '1' when current_task_state = work.task.TASK_RUNNING
and data_valid = '0'
and index < 1024
else '0';
signal_write <= '1' when current_task_state = work.task.TASK_DONE else '0';
signal_writedata <= crc xor X"FFFFFFFF"; -- Final XOR
-- Haupt-Sync Process (identisch zur SW-Version)
sync: process(clk, reset)
variable temp_crc : std_logic_vector(31 downto 0);
begin
if ( reset = '1' ) then
if reset = '1' then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
elsif ( rising_edge( clk ) ) then
crc <= CRC_INIT;
data_reg <= (others => '0');
data_valid <= '0';
elsif rising_edge(clk) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_IDLE =>
index <= 0;
crc <= CRC_INIT;
data_valid <= '0';
when work.task.TASK_RUNNING =>
-- 1. DATA LESEN (Timing: signal_read='1' -> NEXT CLK data_valid)
if signal_read = '1' then
data_reg <= signal_readdata;
data_valid <= '1';
end if;
-- 2. CRC UPDATE (zlib: XOR dann 32x bitweise LSB-first)
if data_valid = '1' then
temp_crc := crc xor data_reg;
crc <= temp_crc;
-- 32 Bit LSB-first Verarbeitung in EINEM Takt (wie SW)
for i in 0 to 31 loop
if temp_crc(0) = '1' then
temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1)) xor CRC_POLY;
else
temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1));
end if;
end loop;
crc <= temp_crc;
data_valid <= '0';
index <= index + 1;
end if;
when work.task.TASK_DONE =>
index <= 0;
data_valid <= '0';
end case;
end if;
end process sync;
task_state <= current_task_state;
end process;
end architecture rtl;
hardware/signal_processing/sine.vhd
+91 -11
View File
@@ -25,12 +25,38 @@ entity sine is
end entity sine;
architecture rtl of sine is
signal current_task_state : work.task.State;
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
signal angle_reg : signed(31 downto 0);
signal step_size_s : signed(31 downto 0);
signal phase_s : signed(31 downto 0);
signal fs_data_valid : std_logic;
signal fs_busy : std_logic;
signal fs_result_valid: std_logic;
signal fs_sine : signed(31 downto 0);
signal sine_sample : std_logic_vector(31 downto 0);
signal fs_result_valid_d : std_logic;
begin
u_float_sine : entity work.float_sine
generic map (
ITERATIONS => 8
)
port map (
clk => clk,
reset => reset,
data_valid => fs_data_valid,
busy => fs_busy,
result_valid => fs_result_valid,
angle => angle_reg,
sine => fs_sine
);
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
next_task_state <= current_task_state;
@@ -51,23 +77,77 @@ begin
end process task_state_transitions;
sync : process ( clk, reset ) is
variable sine_word : std_logic_vector(31 downto 0);
variable sign_bit : std_logic;
variable exp_bits : unsigned(30 downto 23);
variable man_bits : std_logic_vector(22 downto 0);
variable amp_exp : unsigned(30 downto 23);
variable new_exp : unsigned(30 downto 23);
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
index <= 0;
angle_reg <= (others => '0');
step_size_s <= (others => '0');
phase_s <= (others => '0');
fs_data_valid <= '0';
signal_write <= '0';
signal_writedata <= (others => '0');
sine_sample <= (others => '0');
fs_result_valid_d <= '0';
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
fs_data_valid <= '0';
signal_write <= '0';
fs_result_valid_d <= fs_result_valid;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
when work.task.TASK_IDLE =>
index <= 0;
step_size_s <= signed( step_size );
phase_s <= signed( phase );
angle_reg <= signed( phase );
when work.task.TASK_RUNNING =>
if (index = 0 and fs_busy = '0') then
fs_data_valid <= '1';
end if;
if (fs_result_valid = '1' and fs_result_valid_d = '0') then
sine_word := std_logic_vector(fs_sine);
sign_bit := sine_word(31);
exp_bits := unsigned(sine_word(30 downto 23));
man_bits := sine_word(22 downto 0);
amp_exp := unsigned(amplitude(30 downto 23));
new_exp := exp_bits + (amp_exp - to_unsigned(127, 8));
sine_word(31) := sign_bit;
sine_word(30 downto 23) := std_logic_vector(new_exp);
sine_word(22 downto 0) := man_bits;
signal_write <= '1';
signal_writedata <= sine_word;
angle_reg <= angle_reg + step_size_s;
index <= index + 1;
fs_data_valid <= '1';
end if;
when work.task.TASK_DONE =>
index <= 0;
end case;
end if;
end process sync;