crc staengert

hardware/signal_processing/add.vhd

@@ -8,82 +8,79 @@ library work;
 
 entity add is
     port (
-        clk : in std_logic;
+        clk   : in std_logic;
         reset : in std_logic;
 
         task_start : in std_logic;
         task_state : out work.task.State;
 
-        signal_a_read : out std_logic;
+        signal_a_read     : out std_logic;
-        signal_a_readdata : in std_logic_vector( 31 downto 0 );
+        signal_a_readdata : in  std_logic_vector(31 downto 0);
 
-        signal_b_read : out std_logic;
+        signal_b_read     : out std_logic;
-        signal_b_readdata : in std_logic_vector( 31 downto 0 );
+        signal_b_readdata : in  std_logic_vector(31 downto 0);
 
-        signal_write : out std_logic;
+        signal_write     : out std_logic;
-        signal_writedata : out std_logic_vector( 31 downto 0 )
+        signal_writedata : out std_logic_vector(31 downto 0)
     );
 end entity add;
 
-u_add: entity word.add
-    port map (
-        clk => clk,
-        reset => reset,
-        
-        task_start => task_start,
-        task_state => task_state,
-        
-        signal_a_read => signal_a_read,
-        signal_a_readdata => signal_a_readdata,
-        
-        signal_b_read => signal_b_read,
-        signal_b_readdata => signal_b_readdata,
-        
-        signal_write => signal_write,
-        signal_writedata => signal_writedata
-);
-
-        
-    
-    
 architecture rtl of add is
+
     signal current_task_state : work.task.State;
-    signal next_task_state : work.task.State;
+    signal next_task_state    : work.task.State;
-    signal index : integer range 0 to work.task.STREAM_LEN;
+    signal index              : integer range 0 to work.task.STREAM_LEN;
-    signal start_proc : integer range 0 to 7;
+
-    signal state : integer range 0 to 255;
+
-    signal reset : integer range 0 to 7;
+    type AddState is (
-    signal start : integer range 0 to 7;
+        ADD_IDLE,
-    signal done : integer range 0 to 7;
+        ADD_READ_FIFO,
-    signal A : STD_LOGIC_VECTOR(31 downto 0);
+        ADD_LATCH_INPUTS,
-    signal B : STD_LOGIC_VECTOR(31 downto 0);
+        ADD_START_CALC,
-    signal sum : STD_LOGIC_VECTOR(31 downto 0);
+        ADD_WAIT_DONE,
+        ADD_STORE_RESULT
+    );
+
+    signal current_add_state : AddState;
+    signal next_add_state    : AddState;
+
+    signal start_proc : std_logic;
+    signal done       : std_logic;
+
+    signal A   : std_logic_vector(31 downto 0);
+    signal B   : std_logic_vector(31 downto 0);
+    signal sum : std_logic_vector(31 downto 0);
 
 begin
 
+
     u_float_add : entity work.float_add
         port map (
-            clk => clk,
+            clk   => clk,
             reset => reset,
             start => start_proc,
-            done => done,
+            done  => done,
-            A => signal_a_readdata,
+            A     => A,
-            B => signal_b_readdata,
+            B     => B,
-            sum => sum
+            sum   => sum
         );
 
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
+
         case current_task_state is
             when work.task.TASK_IDLE =>
                 if ( task_start = '1' ) then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
+
             when work.task.TASK_RUNNING =>
                 if ( index = work.task.STREAM_LEN - 1 ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
+
             when work.task.TASK_DONE =>
                 if ( task_start = '1' ) then
                     next_task_state <= work.task.TASK_RUNNING;
@@ -92,71 +89,106 @@ begin
     end process task_state_transitions;
 
 
-    perform_add : process ( clk, reset ) is
+    add_state_transitions : process ( current_add_state, current_task_state, done ) is
     begin
-        if (start_proc = '1' or reset = '1' ) then
+        next_add_state <= current_add_state;
-            signal_a_read <= '0';
-            signal_b_read <= '0';
-        else if (rising_edge(clk)) then
-            case state is
-                when 0 =>
-                    start <= '1';
-                    signal_a_read <= '1';
-                    A <= signal_a_readdata;
-                    signal_b_read <= '1';
-                    B <= signal_b_readdata;
 
-                    if( done = '1' ) then
+        if (current_task_state /= work.task.TASK_RUNNING) then
-                        signal_a_read <= '0';
+            next_add_state <= ADD_IDLE;
-                        signal_b_read <= '0';
+        else
-                        state <= '2';
+            case current_add_state is
+                when ADD_IDLE =>
+                    next_add_state <= ADD_READ_FIFO;
+                when ADD_READ_FIFO =>
+                    next_add_state <= ADD_LATCH_INPUTS;
+                when ADD_LATCH_INPUTS =>
+                    next_add_state <= ADD_START_CALC;
+                when ADD_START_CALC =>
+                    next_add_state <= ADD_WAIT_DONE;
+                when ADD_WAIT_DONE =>
+                    if done = '1' then
+                        next_add_state <= ADD_STORE_RESULT;
                     end if;
-              when 2 =>
+                when ADD_STORE_RESULT =>
-            
+                    next_add_state <= ADD_READ_FIFO;
+            end case;
         end if;
-       
+    end process;
-        
-            
-                    
-                    
-                
-                    
-        end case;
-    end process perform_add;
 
 
     sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
-            signal_a_read <= 'O';
+            index              <= 0;
-            signal_b_read <= 'O';
-            signal_write <= 'O';
-            signal_Writedata <= (others => '0');
-            index <= 0;
-            state <= 0;
-            sum <= 0;
-            done <= 0;
-            start <= 0;
-        elsif ( rising_edge( clk ) ) then
-            current_task_state <= next_task_state;
-            case next_task_state is
-            when work.task.TASK_IDLE =>
-                index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                start_proc <= '1';
 
-                index <= index + 1;
+            current_add_state <= ADD_IDLE;
-                signal_write <= '1';
+
-                signal_writedata <= ( others => '0' );
+            signal_a_read   <= '0';
-            when work.task.TASK_DONE =>
+            signal_b_read   <= '0';
-                index <= 0;
+            signal_write    <= '0';
-                signal_write <= '0';
+            signal_writedata <= (others => '0');
+
+            start_proc <= '0';
+            A          <= (others => '0');
+            B          <= (others => '0');
+
+
+        elsif ( rising_edge( clk ) ) then
+
+            current_task_state <= next_task_state;
+            current_add_state  <= next_add_state;
+
+
+            signal_a_read <= '0';
+            signal_b_read <= '0';
+            signal_write  <= '0';
+            start_proc    <= '0';
+
+
+            case next_task_state is
+                when work.task.TASK_IDLE =>
+                    index <= 0;
+
+                when work.task.TASK_RUNNING =>
+                    if current_add_state = ADD_STORE_RESULT then
+                        index <= index + 1;
+                    end if;
+
+                when work.task.TASK_DONE =>
+                    index <= 0;
             end case;
+
+
+            case next_add_state is
+                when ADD_IDLE =>
+                    null;
+
+                when ADD_READ_FIFO =>
+                    signal_a_read <= '1';
+                    signal_b_read <= '1';
+
+                when ADD_LATCH_INPUTS =>
+                    A <= signal_a_readdata;
+                    B <= signal_b_readdata;
+
+                when ADD_START_CALC =>
+                    start_proc <= '1';
+
+                when ADD_WAIT_DONE =>
+                    start_proc <= '1';
+                    null;
+
+                when ADD_STORE_RESULT =>
+                    signal_write    <= '1';
+                    signal_writedata <= sum;
+            end case;
+
+
         end if;
     end process sync;
 
     task_state <= current_task_state;
 
 end architecture rtl;
+

hardware/signal_processing/crc.vhd

@@ -8,69 +8,113 @@ library work;
 
 entity crc is
     port (
-        clk : in std_logic;
+        clk             : in  std_logic;
-        reset : in std_logic;
+        reset           : in  std_logic;
-
+        task_start      : in  std_logic;
-        task_start : in std_logic;
+        task_state      : out work.task.State;
-        task_state : out work.task.State;
+        signal_read     : out std_logic;
-
+        signal_readdata : in  std_logic_vector(31 downto 0);
-        signal_read : out std_logic;
+        signal_write    : out std_logic;
-        signal_readdata : in std_logic_vector( 31 downto 0 );
+        signal_writedata: out std_logic_vector(31 downto 0)
-
-        signal_write : out std_logic;
-        signal_writedata : out std_logic_vector( 31 downto 0 )
     );
 end entity crc;
 
 architecture rtl of crc is
-
     signal current_task_state : work.task.State;
-    signal next_task_state : work.task.State;
+    signal next_task_state    : work.task.State;
-    signal index : integer range 0 to work.task.STREAM_LEN;
+    signal index              : integer range 0 to work.task.STREAM_LEN := 0;
+    
+    constant CRC_INIT  : std_logic_vector(31 downto 0) := X"FFFFFFFF";
+    constant CRC_POLY  : std_logic_vector(31 downto 0) := X"EDB88320";
+    signal crc         : std_logic_vector(31 downto 0) := CRC_INIT;
+    signal data_reg    : std_logic_vector(31 downto 0);
+    signal data_valid  : std_logic := '0';
 
 begin
-    task_state_transitions : process ( current_task_state, task_start, index ) is
+    task_state <= current_task_state;
+    
+    -- TASK STATE MACHINE (VORLAGE - nicht ändern!)
+    task_state_transitions: process(current_task_state, task_start, index)
     begin
         next_task_state <= current_task_state;
         case current_task_state is
             when work.task.TASK_IDLE =>
-                if ( task_start = '1' ) then
+                if task_start = '1' then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                -- WICHTIG: Schreiben nach 1024 Werten (index 0-1023)
+                if index = 1023 then  
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
-                if ( task_start = '1' ) then
+                if task_start = '1' then
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
         end case;
-    end process task_state_transitions;
+    end process;
 
-    sync : process ( clk, reset ) is
+    -- Data Channel Control
+    signal_read <= '1' when current_task_state = work.task.TASK_RUNNING 
+                             and data_valid = '0' 
+                             and index < 1024 
+                  else '0';
+    
+    signal_write <= '1' when current_task_state = work.task.TASK_DONE else '0';
+    signal_writedata <= crc xor X"FFFFFFFF";  -- Final XOR
+
+    -- Haupt-Sync Process (identisch zur SW-Version)
+    sync: process(clk, reset)
+        variable temp_crc : std_logic_vector(31 downto 0);
     begin
-        if ( reset = '1' ) then
+        if reset = '1' then
             current_task_state <= work.task.TASK_IDLE;
             index <= 0;
-        elsif ( rising_edge( clk ) ) then
+            crc <= CRC_INIT;
+            data_reg <= (others => '0');
+            data_valid <= '0';
+            
+        elsif rising_edge(clk) then
             current_task_state <= next_task_state;
+            
             case next_task_state is
-            when work.task.TASK_IDLE =>
+                when work.task.TASK_IDLE =>
-                index <= 0;
+                    index <= 0;
-                signal_write <= '0';
+                    crc <= CRC_INIT;
-            when work.task.TASK_RUNNING =>
+                    data_valid <= '0';
-                index <= index + 1;
+                    
-                signal_write <= '1';
+                when work.task.TASK_RUNNING =>
-                signal_writedata <= ( others => '0' );
+                    -- 1. DATA LESEN (Timing: signal_read='1' -> NEXT CLK data_valid)
-            when work.task.TASK_DONE =>
+                    if signal_read = '1' then
-                index <= 0;
+                        data_reg <= signal_readdata;
-                signal_write <= '0';
+                        data_valid <= '1';
+                    end if;
+                    
+                    -- 2. CRC UPDATE (zlib: XOR dann 32x bitweise LSB-first)
+                    if data_valid = '1' then
+                        temp_crc := crc xor data_reg;
+                        crc <= temp_crc;
+                        
+                        -- 32 Bit LSB-first Verarbeitung in EINEM Takt (wie SW)
+                        for i in 0 to 31 loop
+                            if temp_crc(0) = '1' then
+                                temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1)) xor CRC_POLY;
+                            else
+                                temp_crc := std_logic_vector(shift_right(unsigned(temp_crc), 1));
+                            end if;
+                        end loop;
+                        crc <= temp_crc;
+                        
+                        data_valid <= '0';
+                        index <= index + 1;
+                    end if;
+                    
+                when work.task.TASK_DONE =>
+                    index <= 0;
+                    data_valid <= '0';
             end case;
         end if;
-    end process sync;
+    end process;
-
-    task_state <= current_task_state;
 
 end architecture rtl;
 

hardware/signal_processing/sine.vhd

@@ -30,7 +30,33 @@ architecture rtl of sine is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
     
+    signal angle_reg      : signed(31 downto 0);
+    signal step_size_s    : signed(31 downto 0);
+    signal phase_s        : signed(31 downto 0);
+
+    signal fs_data_valid  : std_logic;
+    signal fs_busy        : std_logic;
+    signal fs_result_valid: std_logic;
+    signal fs_sine        : signed(31 downto 0);
+
+    signal sine_sample    : std_logic_vector(31 downto 0);
+    signal fs_result_valid_d : std_logic;
+
 begin
+    u_float_sine : entity work.float_sine
+        generic map (
+            ITERATIONS => 8
+        )
+        port map (
+            clk          => clk,
+            reset        => reset,
+            data_valid   => fs_data_valid,
+            busy         => fs_busy,
+            result_valid => fs_result_valid,
+            angle        => angle_reg,
+            sine         => fs_sine
+        );
+            
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -51,23 +77,77 @@ begin
     end process task_state_transitions;
 
     sync : process ( clk, reset ) is
+        
+        variable sine_word      : std_logic_vector(31 downto 0);
+        variable sign_bit       : std_logic;
+        variable exp_bits       : unsigned(30 downto 23);
+        variable man_bits       : std_logic_vector(22 downto 0);
+
+        variable amp_exp        : unsigned(30 downto 23);
+        variable new_exp        : unsigned(30 downto 23);
+    
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
             index <= 0;
+            angle_reg          <= (others => '0');
+            step_size_s        <= (others => '0');
+            phase_s            <= (others => '0');
+            fs_data_valid      <= '0';
+            signal_write       <= '0';
+            signal_writedata   <= (others => '0');
+            sine_sample        <= (others => '0');
+            fs_result_valid_d <= '0';
+            
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
+
+            fs_data_valid <= '0';
+            signal_write  <= '0';
+            
+            fs_result_valid_d <= fs_result_valid;
+
             case next_task_state is
-            when work.task.TASK_IDLE =>
+                
-                index <= 0;
+                when work.task.TASK_IDLE =>
-                signal_write <= '0';
+                    index       <= 0;
-            when work.task.TASK_RUNNING =>
+                    step_size_s <= signed( step_size );
-                index <= index + 1;
+                    phase_s     <= signed( phase );
-                signal_write <= '1';
+                    angle_reg   <= signed( phase );
-                signal_writedata <= ( others => '0' );
+
-            when work.task.TASK_DONE =>
+                
-                index <= 0;
+                when work.task.TASK_RUNNING =>
-                signal_write <= '0';
+
+                    if (index = 0 and fs_busy = '0') then
+                        fs_data_valid <= '1';
+                    end if;
+
+                    if (fs_result_valid = '1' and fs_result_valid_d = '0') then
+                        sine_word := std_logic_vector(fs_sine);
+                        sign_bit  := sine_word(31);
+                        exp_bits  := unsigned(sine_word(30 downto 23));
+                        man_bits  := sine_word(22 downto 0);
+
+                        amp_exp := unsigned(amplitude(30 downto 23));
+                        new_exp := exp_bits + (amp_exp - to_unsigned(127, 8));
+
+                        sine_word(31)           := sign_bit;
+                        sine_word(30 downto 23) := std_logic_vector(new_exp);
+                        sine_word(22 downto 0)  := man_bits;
+
+                        signal_write     <= '1';
+                        signal_writedata <= sine_word;
+
+                        angle_reg <= angle_reg + step_size_s;
+                        index     <= index + 1;
+
+                        fs_data_valid <= '1';
+                    end if;
+
+
+
+                when work.task.TASK_DONE =>
+                    index        <= 0;
             end case;
         end if;
     end process sync;

software/signal_processing/crc.c

@@ -2,9 +2,38 @@
 #include "system/data_channel.h"
 #include "system/float_word.h"
 
-int task_crc_run( void * task ) {
+#define CRC32_POLY 0xEDB88320
+#define CRC32_INIT 0xFFFFFFFF
+#define DATA_CHANNEL_DEPTH 1024
 
-    // TODO
+static uint32_t crc32_update(uint32_t crc, uint32_t data) {
+    int i;
+    crc ^= data;
+    for (i = 0; i < 32; i++) {
+        if (crc & 1) {
+            crc = (crc >> 1) ^ CRC32_POLY;
+        } else {
+            crc >>= 1;
+        }
+    }
+    return crc;
+}
+
+int task_crc_run(void *task) {
+    crc_config *config = (crc_config *)task;
+    uint32_t source_base = config->base.sources[0];
+    uint32_t sink_base = config->base.sink;
+    uint32_t crc = CRC32_INIT;
+    uint32_t value;
+    
+    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++) {
+        data_channel_read(source_base, &value);
+        crc = crc32_update(crc, value);
+    }
+    
+    crc ^= 0xFFFFFFFF;
+    
+    data_channel_write(sink_base, crc);
     
     return 0;
 }

software/signal_processing/sine.c

@@ -2,9 +2,26 @@
 #include "system/data_channel.h"
 #include "system/float_word.h"
 
+#include <math.h>
+#include <limits.h>
+
 int task_sine_run( void * data ) {
 
-    // TODO
+    sine_config *task = (sine_config *)data;
+    uint32_t data_channel_base = task->base.sink;
+
+    uint32_t samples_per_period = task->samples_per_periode;
+    float phase = task->phase;
+    float amplitude = task->amplitude;
+
+    float step = ( 2.0f * (float)M_PI ) / (float)samples_per_period;
+
+    for ( uint32_t i = 0; i < 1024; ++i ) {
+        float_word sample;
+        float angle = phase + (float)i * step;
+        sample.value = amplitude * sinf( angle );
+        data_channel_write( data_channel_base, sample.word );
+    }
 
     return 0;
 }

tests/hardware/task_add_sine_cosine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 11:07:13 on Dec 09,2025
+# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.sine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.cosine_data
+# Loading work.sine_cosine_data
+# Loading work.test_task_add_sine_cosine(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.float_add(mixed)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_sine_cosine
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 11:07:14 on Dec 09,2025, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 1

tests/hardware/task_add_sine_cosine/vish_stacktrace.vstf

@@ -0,0 +1,33 @@
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"

tests/hardware/task_add_sine_cosine/work/_vmake

@@ -0,0 +1,4 @@
+m255
+K4
+z0
+cModel Technology

tests/hardware/task_cosine/transcript

@@ -0,0 +1,65 @@
+# vsim -voptargs="+acc" -c work.test_task_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 10:21:37 on Dec 23,2025
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 1 FSM in architecture body "sine(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.cosine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.test_task_cosine(test)#1
+# Loading work.float(body)
+# Loading work.task_sine(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.cordic_pkg(body)
+# Loading work.sine(rtl)#1
+# Loading work.float_sine(rtl)#1
+# Loading work.fixed_sine(rtl)#1
+# Loading work.cordic(rtl)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 10:21:38 on Dec 23,2025, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 1

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