signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
	signal current_task_state : work.task.State;
	signal next_task_state : work.task.State;
	signal index : integer range 0 to work.task.STREAM_LEN;
	signal fa_start: std_logic;
	signal fa_done: std_logic;
	signal fa_sum: std_logic_vector(31 downto 0);
	signal a_value: std_logic_vector(31 downto 0);
	signal b_value: std_logic_vector(31 downto 0);
	signal sample_done: std_logic;
	signal calc_cnt_int: integer range 0 to 15;
type calc_state_t is (
	C_IDLE,
	C_READ_A_REQ, C_READ_A_LATCH,
	C_READ_B_REQ, C_READ_B_LATCH,
	C_START_ADD, C_WAIT_ADD,
	C_WRITE_RESULT
);
signal calc_state: calc_state_t:=C_IDLE;
begin

	u_float_add : entity work.float_add
	port map(
		clk => clk,
		reset => reset,
		start => fa_start,
		done => fa_done,
		A => a_value,
		B => b_value,
		sum => fa_sum
	);
    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN - 1 ) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;





    sync : process ( clk, reset ) is
    begin
      if ( reset = '1' ) then
            	current_task_state <= work.task.TASK_IDLE;
 		calc_state       <= C_IDLE;
		signal_a_read <= '0';
		signal_b_read <= '0';
		signal_write <= '0';
		signal_writedata <= (others => '0');
		calc_cnt_int <= 0;
		fa_start <= '0';
		a_value          <= (others => '0');
		b_value          <= (others => '0');
		sample_done      <= '0';
 
            index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
		fa_start      <= '0';
		signal_a_read <= '0';
		signal_b_read <= '0';
		signal_write  <= '0';
		sample_done   <= '0';
            case next_task_state is
            when work.task.TASK_IDLE =>
                index <= 0;
                signal_write <= '0';
            when work.task.TASK_RUNNING =>
                index <= index + 1;
                signal_write <= '1';
                signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                index <= 0;
                signal_write <= '0';
            end case;
	case calc_state is
	 when C_IDLE =>
		if current_task_state = work.task.TASK_RUNNING then
		    calc_state <= C_READ_A_REQ;
		end if;
	 when C_READ_A_REQ =>
                signal_a_read <= '1';
                calc_state    <= C_READ_A_LATCH;
 
         when C_READ_A_LATCH =>
                a_value    <= signal_a_readdata;
                calc_state <= C_READ_B_REQ;

	 when C_READ_B_REQ =>
		signal_b_read <= '1';
		calc_state <= C_READ_B_LATCH;

	 when C_READ_B_LATCH =>  
		b_value    <= signal_b_readdata;
		calc_state <= C_START_ADD;

	when C_START_ADD =>  
		fa_start <='1';
		calc_state <= C_WAIT_ADD;

	when C_WAIT_ADD =>  
		if ( fa_done = '1' ) then
			calc_state <= C_WRITE_RESULT;
		end if;

	when C_WRITE_RESULT =>  
		signal_write <= '1' ;
		signal_writedata <= fa_sum;
		calc_cnt_int <= calc_cnt_int + 1;


        end case;
	end if;
    end process sync;

    task_state <= current_task_state;












	
end architecture rtl;