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badenbergra78621 69302fa649 crc.c Korrekturen
2023-12-02 23:50:26 +01:00
hardware
Initial commit
2023-10-31 07:47:27 +01:00
software/signal_processing
crc.c Korrekturen
2023-12-02 23:50:26 +01:00
tests
Initial commit
2023-10-31 07:47:27 +01:00
.gitignore
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data_channel_hw.tcl
Initial commit
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hardware_task_hw.tcl
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hardware_timestamp_hw.tcl
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hdl_sources.qsf
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init.sh
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Makefile
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niosII.qsys
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signal_processing.cdf
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signal_processing.qpf
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signal_processing.qsf
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2023-10-31 07:47:27 +01:00
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Description
Studentenversion des ESY6/A Praktikums "signal_processing".
331 KiB
Languages
VHDL 36.2%
C 17.7%
Verilog 15.2%
Python 10.8%
Makefile 8.3%
Other 11.8%