badenbergra78621 b783fe53a2 crc.c is ready now and works as required

2023-12-05 11:09:00 +01:00

hardware

Initial commit

2023-10-31 07:47:27 +01:00

software/signal_processing

crc.c is ready now and works as required

2023-12-05 11:09:00 +01:00

tests

Initial commit

2023-10-31 07:47:27 +01:00

.gitignore

Initial commit

2023-10-31 07:47:27 +01:00

data_channel_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_task_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_timestamp_hw.tcl

Initial commit

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hdl_sources.qsf

Initial commit

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init.sh

Initial commit

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Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

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signal_processing.qpf

Initial commit

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signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

S

Description

Studentenversion des ESY6/A Praktikums "signal_processing".

331 KiB

Languages

VHDL 36.2%

C 17.7%

Verilog 15.2%

Python 10.8%

Makefile 8.3%

Other 11.8%