Ralph Badenberg badenbergra78621

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• Joined on 2022-04-28

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badenbergra78621 pushed to master at badenbergra78621/signal_processing_vorlage 2023-12-05 10:09:12 +00:00

b783fe53a2 crc.c is ready now and works as required

badenbergra78621 pushed to master at badenbergra78621/signal_processing_vorlage 2023-12-02 22:50:43 +00:00

69302fa649 crc.c Korrekturen

badenbergra78621 pushed to master at badenbergra78621/signal_processing_vorlage 2023-11-28 10:18:19 +00:00

4d3a27edd1 verbessert

badenbergra78621 pushed to master at badenbergra78621/signal_processing_vorlage 2023-11-28 10:13:34 +00:00

903c139097 verschönert

cc653b9c70 verschönert

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badenbergra78621 pushed to master at badenbergra78621/signal_processing_vorlage 2023-11-21 10:19:02 +00:00

fb2d609dbc Added add.c

badenbergra78621 created repository badenbergra78621/signal_processing_vorlage 2023-11-21 10:08:17 +00:00

badenbergra78621 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-17 09:43:00 +00:00

71fd941588 modports angepasst

badenbergra78621 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:59:24 +00:00

9ffb72cf97 Screenshots from RADIANT --> how to create SPI module with radiant

badenbergra78621 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:58:24 +00:00

72c964475f Screenshots from RADIANT --> how to create SPI module with radiant

badenbergra78621 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-06-14 09:42:27 +00:00

c46a1c3b33 add "spi_interface_portsI()" (beginning of document)

badenbergra78621 pushed to main at kuntzschcl/ESY1_Projekt_2022 2022-05-31 10:58:29 +00:00

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