4.Test
This commit is contained in:
beckal87649
parent
c90753aa23
commit
4d0bb79521
@ -26,52 +26,170 @@ entity add is
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end entity add;
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architecture rtl of add is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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-- Task FSM
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signal current_task_state : work.task.State := work.task.TASK_IDLE;
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signal next_task_state : work.task.State := work.task.TASK_IDLE;
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signal index : integer range 0 to work.task.STREAM_LEN-1 := 0;
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-- task_start rising edge detect (combinational pulse)
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signal task_start_d : std_logic := '0';
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signal task_start_re : std_logic;
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-- float_add IP core
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signal fa_start : std_logic := '0';
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signal fa_done : std_logic := '0';
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signal fa_sum : std_logic_vector(31 downto 0);
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signal a_value : std_logic_vector(31 downto 0) := (others => '0');
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signal b_value : std_logic_vector(31 downto 0) := (others => '0');
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-- Calc FSM
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type calc_state_t is (
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C_IDLE,
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C_READ_A,
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C_READ_B,
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C_START_ADD,
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C_WAIT_ADD,
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C_WRITE_RESULT
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);
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signal calc_state : calc_state_t := C_IDLE;
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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-- combinational rising edge detect
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task_start_re <= task_start and not task_start_d;
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task_state <= current_task_state;
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-- float_add instance
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u_float_add : entity work.float_add
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port map (
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A => a_value,
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B => b_value,
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clk => clk,
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reset => reset,
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start => fa_start,
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done => fa_done,
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sum => fa_sum
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);
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-- Task FSM transitions (ONLY driver of next_task_state)
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task_state_transitions : process(current_task_state, task_start_re, index, calc_state)
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if task_start_re = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if (index = work.task.STREAM_LEN - 1) and (calc_state = C_WRITE_RESULT) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if task_start_re = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process;
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-- Synchronous process
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sync : process(clk, reset)
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begin
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if reset = '1' then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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task_start_d <= '0';
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calc_state <= C_IDLE;
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fa_start <= '0';
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signal_a_read <= '0';
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signal_b_read <= '0';
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signal_write <= '0';
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signal_writedata <= (others => '0');
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a_value <= (others => '0');
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b_value <= (others => '0');
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elsif rising_edge(clk) then
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-- register delayed start for edge detect
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task_start_d <= task_start;
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-- defaults
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signal_a_read <= '0';
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signal_b_read <= '0';
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signal_write <= '0';
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fa_start <= '0';
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-- update task state
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current_task_state <= next_task_state;
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-- index update
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case current_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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when work.task.TASK_RUNNING =>
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if calc_state = C_WRITE_RESULT then
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if index < work.task.STREAM_LEN - 1 then
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index <= index + 1;
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end if;
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end if;
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when work.task.TASK_DONE =>
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index <= 0;
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end case;
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-- calc FSM
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case calc_state is
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when C_IDLE =>
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if current_task_state = work.task.TASK_RUNNING then
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calc_state <= C_READ_A;
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end if;
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when C_READ_A =>
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signal_a_read <= '1';
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a_value <= signal_a_readdata;
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calc_state <= C_READ_B;
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when C_READ_B =>
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signal_b_read <= '1';
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b_value <= signal_b_readdata;
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calc_state <= C_START_ADD;
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when C_START_ADD =>
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fa_start <= '1';
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calc_state <= C_WAIT_ADD;
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when C_WAIT_ADD =>
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fa_start <= '1';
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if fa_done = '1' then
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calc_state <= C_WRITE_RESULT;
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end if;
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when C_WRITE_RESULT =>
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signal_write <= '1';
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signal_writedata <= fa_sum;
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if index = work.task.STREAM_LEN - 1 then
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calc_state <= C_IDLE;
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else
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calc_state <= C_READ_A;
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end if;
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end case;
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end if;
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end process;
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end architecture rtl;
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@ -22,11 +22,15 @@ end entity rand;
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architecture rtl of rand is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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signal current_task_state : work.task.State := work.task.TASK_IDLE;
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signal next_task_state : work.task.State := work.task.TASK_IDLE;
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signal index : integer range 0 to work.task.STREAM_LEN-1 := 0;
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signal lfsr : std_logic_vector(31 downto 0) := (others => '0');
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begin
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-- task_state_transitions
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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@ -47,27 +51,92 @@ begin
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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variable fb : std_logic;
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variable lfsr_work : std_logic_vector(31 downto 0);
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variable lfsr_next : std_logic_vector(31 downto 0);
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variable exp_rand : std_logic_vector(7 downto 0);
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variable exp_new : std_logic_vector(7 downto 0);
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variable out_word : std_logic_vector(31 downto 0);
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variable do_run : boolean;
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variable entering : boolean;
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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lfsr <= (others => '0');
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signal_write <= '0';
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signal_writedata <= (others => '0');
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elsif rising_edge( clk ) then
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-- State-Register
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current_task_state <= next_task_state;
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case next_task_state is
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-- Defaults (wichtig für assert_level)
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signal_write <= '0';
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signal_writedata <= (others => '0');
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-- Datapath-Steuerung:
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-- RUNNING-Aktionen ausführen, wenn
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-- a) gerade RUNNING sind (auch wenn next schon DONE ist -> letztes Sample!)
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-- b) in RUNNING eintreten (IDLE/DONE -> RUNNING)
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entering := (current_task_state /= work.task.TASK_RUNNING) and (next_task_state = work.task.TASK_RUNNING);
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do_run := (current_task_state = work.task.TASK_RUNNING) or entering;
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if do_run then
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-- LFSR-Quelle: beim Eintritt seed, sonst aktueller lfsr
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if entering then
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lfsr_work := seed;
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index <= 0; -- erstes Sample hat Index 0
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else
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lfsr_work := lfsr;
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end if;
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-- Output aus aktuellem Zustand bauen
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exp_rand := lfsr_work(30 downto 23);
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if exp_rand(7) = '1' then
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exp_new(7) := '1';
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exp_new(6 downto 1) := (others => '0');
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exp_new(0) := exp_rand(0);
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else
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exp_new(7) := '0';
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exp_new(6 downto 2) := (others => '1');
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exp_new(1 downto 0) := exp_rand(1 downto 0);
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end if;
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out_word(31) := lfsr_work(31);
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out_word(30 downto 23) := exp_new;
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out_word(22 downto 0) := lfsr_work(22 downto 0);
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signal_write <= '1';
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signal_writedata <= out_word;
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-- LFSR Schritt nach Ausgabe
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fb := lfsr_work(31) xor lfsr_work(21) xor lfsr_work(1) xor lfsr_work(0);
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lfsr_next := lfsr_work(30 downto 0) & fb;
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lfsr <= lfsr_next;
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-- Index nach Write erhöhen
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if index < work.task.STREAM_LEN - 1 then
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index <= index + 1;
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end if;
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else
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case current_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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when others =>
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null;
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end case;
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end if;
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end if;
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end process sync;
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task_state <= current_task_state;
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end architecture rtl;
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@ -22,56 +22,235 @@ entity sine is
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signal_write : out std_logic;
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signal_writedata : out std_logic_vector(31 downto 0)
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);
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end entity sine;
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end entity;
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architecture rtl of sine is
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signal current_task_state : work.task.State;
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signal next_task_state : work.task.State;
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signal index : integer range 0 to work.task.STREAM_LEN;
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-- Task FSM states
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signal current_task_state : work.task.State := work.task.TASK_IDLE;
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signal next_task_state : work.task.State := work.task.TASK_IDLE;
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signal index : integer range 0 to work.task.STREAM_LEN-1 := 0;
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-- Rising-edge detector (only task_start_d is registered)
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signal task_start_d : std_logic := '0';
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signal task_start_re : std_logic;
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-- float_sine IP core
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signal fs_data_valid : std_logic := '0';
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signal fs_busy : std_logic;
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signal fs_result_valid : std_logic;
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signal fs_angle : signed(31 downto 0) := (others => '0');
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signal fs_sine : signed(31 downto 0);
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-- Data pipeline
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signal angle_reg : signed(31 downto 0) := (others => '0');
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signal sine_raw_fp : std_logic_vector(31 downto 0) := (others => '0');
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signal sine_scaled_fp : std_logic_vector(31 downto 0) := (others => '0');
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-- Calculation FSM
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type calc_state_t is (
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C_IDLE,
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C_PREPARE,
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C_START,
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C_WAIT,
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C_SCALE,
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C_WRITE
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);
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signal calc_state : calc_state_t := C_IDLE;
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-- Pipeline warm-up fix (CORDIC output invalid on first result_valid)
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signal first_result_seen : std_logic := '0';
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begin
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task_state_transitions : process ( current_task_state, task_start, index ) is
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if ( index = work.task.STREAM_LEN - 1 ) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if ( task_start = '1' ) then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process task_state_transitions;
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sync : process ( clk, reset ) is
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begin
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if ( reset = '1' ) then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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elsif ( rising_edge( clk ) ) then
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current_task_state <= next_task_state;
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case next_task_state is
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when work.task.TASK_IDLE =>
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index <= 0;
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signal_write <= '0';
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when work.task.TASK_RUNNING =>
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index <= index + 1;
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signal_write <= '1';
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signal_writedata <= ( others => '0' );
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when work.task.TASK_DONE =>
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index <= 0;
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signal_write <= '0';
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end case;
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end if;
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end process sync;
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-- combinational rising-edge detect (1-cycle faster than registered pulse)
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task_start_re <= task_start and not task_start_d;
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-- Output current task state
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task_state <= current_task_state;
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end architecture rtl;
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-- Task FSM (combinational)
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task_fsm : process(current_task_state, task_start_re, index, calc_state)
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begin
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next_task_state <= current_task_state;
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case current_task_state is
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when work.task.TASK_IDLE =>
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if task_start_re = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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when work.task.TASK_RUNNING =>
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if (index = work.task.STREAM_LEN - 1) and (calc_state = C_WRITE) then
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next_task_state <= work.task.TASK_DONE;
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end if;
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when work.task.TASK_DONE =>
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if task_start_re = '1' then
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next_task_state <= work.task.TASK_RUNNING;
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end if;
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end case;
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end process;
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-- float_sine instantiation
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fs_angle <= angle_reg;
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u_float_sine : entity work.float_sine
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generic map (
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ITERATIONS => 8
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)
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port map (
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clk => clk,
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reset => reset,
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data_valid => fs_data_valid,
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busy => fs_busy,
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result_valid => fs_result_valid,
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angle => fs_angle,
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sine => fs_sine
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);
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sync : process(clk, reset)
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variable sin_exp : unsigned(7 downto 0);
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variable amp_exp : unsigned(7 downto 0);
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variable new_exp : unsigned(7 downto 0);
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variable sin_e_i : integer;
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variable amp_e_i : integer;
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variable new_e_i : integer;
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begin
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if reset = '1' then
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current_task_state <= work.task.TASK_IDLE;
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index <= 0;
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task_start_d <= '0';
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calc_state <= C_IDLE;
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||||
|
||||
angle_reg <= (others => '0');
|
||||
sine_raw_fp <= (others => '0');
|
||||
sine_scaled_fp <= (others => '0');
|
||||
|
||||
fs_data_valid <= '0';
|
||||
signal_write <= '0';
|
||||
signal_writedata <= (others => '0');
|
||||
|
||||
first_result_seen <= '0';
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
task_start_d <= task_start;
|
||||
|
||||
-- Default outputs
|
||||
|
||||
signal_write <= '0';
|
||||
fs_data_valid <= '0';
|
||||
|
||||
-- Update Task FSM
|
||||
current_task_state <= next_task_state;
|
||||
|
||||
-- Index update
|
||||
|
||||
case current_task_state is
|
||||
|
||||
when work.task.TASK_IDLE =>
|
||||
index <= 0;
|
||||
|
||||
when work.task.TASK_RUNNING =>
|
||||
if calc_state = C_WRITE then
|
||||
if index < work.task.STREAM_LEN - 1 then
|
||||
index <= index + 1;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
when work.task.TASK_DONE =>
|
||||
index <= 0;
|
||||
|
||||
end case;
|
||||
|
||||
-- Calculation FSM
|
||||
|
||||
case calc_state is
|
||||
|
||||
when C_IDLE =>
|
||||
if current_task_state = work.task.TASK_RUNNING then
|
||||
angle_reg <= signed(phase);
|
||||
first_result_seen <= '0';
|
||||
calc_state <= C_PREPARE;
|
||||
end if;
|
||||
|
||||
when C_PREPARE =>
|
||||
calc_state <= C_START;
|
||||
|
||||
when C_START =>
|
||||
if fs_busy = '0' then
|
||||
fs_data_valid <= '1';
|
||||
calc_state <= C_WAIT;
|
||||
end if;
|
||||
|
||||
when C_WAIT =>
|
||||
if fs_result_valid = '1' then
|
||||
|
||||
|
||||
if first_result_seen = '0' then
|
||||
first_result_seen <= '1';
|
||||
angle_reg <= angle_reg + signed(step_size);
|
||||
calc_state <= C_START;
|
||||
else
|
||||
sine_raw_fp <= std_logic_vector(fs_sine);
|
||||
calc_state <= C_SCALE;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
when C_SCALE =>
|
||||
|
||||
sin_exp := unsigned(sine_raw_fp(30 downto 23));
|
||||
amp_exp := unsigned(amplitude(30 downto 23));
|
||||
|
||||
sin_e_i := to_integer(sin_exp);
|
||||
amp_e_i := to_integer(amp_exp);
|
||||
|
||||
new_e_i := sin_e_i + (amp_e_i - 127);
|
||||
|
||||
if new_e_i < 0 then
|
||||
new_exp := (others => '0');
|
||||
else
|
||||
new_exp := to_unsigned(new_e_i, 8);
|
||||
end if;
|
||||
|
||||
sine_scaled_fp(31) <= sine_raw_fp(31);
|
||||
sine_scaled_fp(30 downto 23) <= std_logic_vector(new_exp);
|
||||
sine_scaled_fp(22 downto 0) <= sine_raw_fp(22 downto 0);
|
||||
|
||||
calc_state <= C_WRITE;
|
||||
|
||||
when C_WRITE =>
|
||||
|
||||
signal_write <= '1';
|
||||
signal_writedata <= sine_scaled_fp;
|
||||
|
||||
if index = work.task.STREAM_LEN - 1 then
|
||||
calc_state <= C_IDLE;
|
||||
else
|
||||
angle_reg <= angle_reg + signed(step_size);
|
||||
calc_state <= C_START;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end architecture;
|
||||
|
||||
|
||||
@ -3,10 +3,37 @@
|
||||
#include "system/data_channel.h"
|
||||
#include "system/float_word.h"
|
||||
|
||||
int task_rand_run( void * task ) {
|
||||
int task_rand_run(void *task)
|
||||
{
|
||||
rand_config *config = (rand_config *)task;
|
||||
|
||||
// TODO
|
||||
uint32_t data_channel_base = config->base.sink;
|
||||
data_channel_clear(data_channel_base);
|
||||
|
||||
float_word seed_fw = { .value = config->seed };
|
||||
uint32_t lfsr = seed_fw.word;
|
||||
|
||||
for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
|
||||
|
||||
uint32_t sign = (lfsr >> 31) & 0x1u;
|
||||
uint32_t mant = lfsr & 0x007FFFFFu; // 23 Bit Mantisse
|
||||
uint32_t exp_rand = (lfsr >> 23) & 0xFFu; // 8 Bit Exponent
|
||||
|
||||
uint32_t exp_new;
|
||||
if (exp_rand & 0x80u) {
|
||||
exp_new = 0x80u | (exp_rand & 0x01u);
|
||||
} else {
|
||||
exp_new = 0x7Cu | (exp_rand & 0x03u);
|
||||
}
|
||||
|
||||
float_word out;
|
||||
out.word = (sign << 31) | (exp_new << 23) | mant;
|
||||
|
||||
data_channel_write(data_channel_base, out.word);
|
||||
|
||||
uint32_t fb = ((lfsr >> 31) ^ (lfsr >> 21) ^ (lfsr >> 1) ^ (lfsr >> 0)) & 0x1u;
|
||||
lfsr = (lfsr << 1) | fb;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user