update

software/signal_processing/fft.c

@@ -3,7 +3,7 @@
 #include "system/Complex.h"
 #include "system/float_word.h"
 #include "math.h"
-#include "complex.h"
+#include <complex.h>
 
 void cooley_tukey(float complex *X, const uint32_t N) {
     if (N >= 2) {
@@ -47,7 +47,7 @@ int task_fft_run( void * task ) {
 
 	float_word c;
 	c.value = complex_abs(&input[i]);
-
+	c.value = sqrt( pow( input[i].re, 2 ) + pow( input[i].im, 2 ) );
 
 	if (i > (uint32_t)0)
 	{	

tests/hardware/task_add_rand/transcript

@@ -0,0 +1,64 @@
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# vsim -voptargs="+acc" work.test_task_add_rand -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gGUI_MODE=true -gCHECK_RESULTS=true 
+# Start time: 10:15:08 on Dec 11,2024
+# ** Note: (vsim-8009) Loading existing optimized design _opt1
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.sine_cosine_data
+# Loading work.rand_data
+# Loading work.add_rand_data
+# Loading work.test_task_add_rand(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.float_add(mixed)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# do vsim.wave
+#  set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_rand
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     check_and_write_content ... [ OK ]
+# Break in Process stimulus at test_task_add_rand.vhd line 178
+# End time: 11:04:48 on Dec 11,2024, Elapsed time: 0:49:40
+# Errors: 0, Warnings: 0

tests/hardware/task_add_rand/vish_stacktrace.vstf

@@ -0,0 +1,9 @@
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"
+# transcript error: error writing "stdout": broken pipe
+    while executing
+"puts -nonewline stdout $s"

tests/hardware/task_add_rand/work/_vmake

@@ -0,0 +1,4 @@
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tests/hardware/task_add_sine_cosine/transcript

@@ -0,0 +1,68 @@
+# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false 
+# Start time: 09:12:00 on Nov 16,2024
+# ** Note: (vsim-3812) Design is being optimized...
+# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
+# ** Note: (vopt-143) Recognized 1 FSM in architecture body "add(rtl)".
+# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
+# //  Questa Sim-64
+# //  Version 2023.2 linux_x86_64 Apr 11 2023
+# //
+# //  Copyright 1991-2023 Mentor Graphics Corporation
+# //  All Rights Reserved.
+# //
+# //  QuestaSim and its associated documentation contain trade
+# //  secrets and commercial or financial information that are the property of
+# //  Mentor Graphics Corporation and are privileged, confidential,
+# //  and exempt from disclosure under the Freedom of Information Act,
+# //  5 U.S.C. Section 552. Furthermore, this information
+# //  is prohibited from disclosure under the Trade Secrets Act,
+# //  18 U.S.C. Section 1905.
+# //
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.fixed_float_types
+# Loading ieee.math_real(body)
+# Loading ieee.fixed_generic_pkg(body)
+# Loading ieee.float_generic_pkg(body)
+# Loading ieee.fixed_pkg
+# Loading ieee.float_pkg
+# Loading work.reg32(body)
+# Loading work.avalon_slave
+# Loading work.test_utility(body)
+# Loading work.test_avalon_slave(body)
+# Loading work.task(body)
+# Loading work.sine_data
+# Loading work.test_hardware_task(body)
+# Loading work.test_data_channel_pkg(body)
+# Loading std.env(body)
+# Loading work.cosine_data
+# Loading work.sine_cosine_data
+# Loading work.test_task_add_sine_cosine(test)#1
+# Loading work.task_add(struct)#1
+# Loading work.hardware_task_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#1
+# Loading work.add(rtl)#1
+# Loading work.data_channel(struct)#1
+# Loading work.data_channel_control(rtl)#1
+# Loading work.avalon_slave_transitions(rtl)#2
+# Loading work.data_sink_mux(rtl)#1
+# Loading work.fifo(rtl)#1
+# Loading work.data_source_mux(rtl)#1
+# ** Warning: (vsim-8683) Uninitialized out port /test_task_add_sine_cosine/dut/u_add/signal_a_read has no driver.
+# This port will contribute value (U) to the signal network.
+# ** Warning: (vsim-8683) Uninitialized out port /test_task_add_sine_cosine/dut/u_add/signal_b_read has no driver.
+# This port will contribute value (U) to the signal network.
+# set StdArithNoWarnings 1
+# 1
+#  set NumericStdNoWarnings 1
+# 1
+#  run -all
+# --------------------------------------------------------------------------------
+# Starting test_task_add_sine_cosine
+#     test_configure ... [ OK ]
+#     test_execute ... [ OK ]
+#     write_content ... [ OK ]
+# End time: 09:12:01 on Nov 16,2024, Elapsed time: 0:00:01
+# Errors: 0, Warnings: 3

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