Lösung des ESY6/A Praktikums "signal_processing".
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  1. # // Questa Sim-64
  2. # // Version 2023.2 linux_x86_64 Apr 11 2023
  3. # //
  4. # // Copyright 1991-2023 Mentor Graphics Corporation
  5. # // All Rights Reserved.
  6. # //
  7. # // QuestaSim and its associated documentation contain trade
  8. # // secrets and commercial or financial information that are the property of
  9. # // Mentor Graphics Corporation and are privileged, confidential,
  10. # // and exempt from disclosure under the Freedom of Information Act,
  11. # // 5 U.S.C. Section 552. Furthermore, this information
  12. # // is prohibited from disclosure under the Trade Secrets Act,
  13. # // 18 U.S.C. Section 1905.
  14. # //
  15. # vsim -voptargs="+acc" work.test_task_add_rand -do "do vsim.wave; set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gGUI_MODE=true -gCHECK_RESULTS=true
  16. # Start time: 10:15:08 on Dec 11,2024
  17. # ** Note: (vsim-8009) Loading existing optimized design _opt1
  18. # Loading std.standard
  19. # Loading std.textio(body)
  20. # Loading ieee.std_logic_1164(body)
  21. # Loading ieee.numeric_std(body)
  22. # Loading ieee.fixed_float_types
  23. # Loading ieee.math_real(body)
  24. # Loading ieee.fixed_generic_pkg(body)
  25. # Loading ieee.float_generic_pkg(body)
  26. # Loading ieee.fixed_pkg
  27. # Loading ieee.float_pkg
  28. # Loading work.reg32(body)
  29. # Loading work.avalon_slave
  30. # Loading work.test_utility(body)
  31. # Loading work.test_avalon_slave(body)
  32. # Loading work.task(body)
  33. # Loading work.test_hardware_task(body)
  34. # Loading work.test_data_channel_pkg(body)
  35. # Loading std.env(body)
  36. # Loading work.sine_cosine_data
  37. # Loading work.rand_data
  38. # Loading work.add_rand_data
  39. # Loading work.test_task_add_rand(test)#1
  40. # Loading work.task_add(struct)#1
  41. # Loading work.hardware_task_control(rtl)#1
  42. # Loading work.avalon_slave_transitions(rtl)#1
  43. # Loading work.add(rtl)#1
  44. # Loading work.float_add(mixed)#1
  45. # Loading work.data_channel(struct)#1
  46. # Loading work.data_channel_control(rtl)#1
  47. # Loading work.avalon_slave_transitions(rtl)#2
  48. # Loading work.data_sink_mux(rtl)#1
  49. # Loading work.fifo(rtl)#1
  50. # Loading work.data_source_mux(rtl)#1
  51. # do vsim.wave
  52. # set StdArithNoWarnings 1
  53. # 1
  54. # set NumericStdNoWarnings 1
  55. # 1
  56. # run -all
  57. # --------------------------------------------------------------------------------
  58. # Starting test_task_add_rand
  59. # test_configure ... [ OK ]
  60. # test_execute ... [ OK ]
  61. # check_and_write_content ... [ OK ]
  62. # Break in Process stimulus at test_task_add_rand.vhd line 178
  63. # End time: 11:04:48 on Dec 11,2024, Elapsed time: 0:49:40
  64. # Errors: 0, Warnings: 0