binnerda82916 85a5403150 funktional mit abweichung

2024-12-17 22:33:34 +01:00

hardware

funktional mit abweichung

2024-12-17 22:33:34 +01:00

software

update fft.vhd

2024-12-11 08:20:00 +01:00

tests

fft hardware plottable

2024-12-17 11:44:13 +01:00

.gitignore

Initial commit

2023-10-31 07:47:27 +01:00

data_channel_hw.tcl

Initial commit

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hardware_task_hw.tcl

Initial commit

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hardware_timestamp_hw.tcl

Initial commit

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hdl_sources.qsf

Initial commit

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init.sh

Initial commit

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Makefile

Initial commit

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niosII.qsys

Initial commit

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signal_processing.cdf

Initial commit

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signal_processing.qpf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

Description

Lösung des ESY6/A Praktikums "signal_processing".

6 MiB

Languages

C 42.5%

VHDL 16.9%

Python 12.6%

Makefile 7.1%

Verilog 6.8%

Other 14.1%