signal_processing_vorlage/hardware/system/sync_rst.vhd

library ieee;
    use ieee.std_logic_1164.all;

entity sync_rst is
    generic
    (
        WIDTH : positive range 2 to 5 := 3
    );

    port
    (
        clk : in  std_logic;
        reset : in  std_logic;
        rst_sync : out std_logic
    );
end entity sync_rst;

architecture rtl of sync_rst is

   --! Synchronization FFs
   signal sync : std_logic_vector( WIDTH - 1 downto 0 );

begin

    p_sync: process ( clk, reset ) is
    begin

        if ( reset = '1' ) then

            sync <= ( others => '1' );

        elsif ( rising_edge( clk ) ) then

            sync( 0 ) <= '0';

            sync( WIDTH - 1 downto 1 ) <= sync( WIDTH - 2 downto 0 );
        end if;

    end process p_sync;

    rst_sync <= sync( WIDTH - 1 );

end architecture rtl;