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dippoldha78415 357ceef29b add.vhd and crc.vhd working and finished, results true
2023-12-19 20:26:22 +01:00
hardware
add.vhd and crc.vhd working and finished, results true
2023-12-19 20:26:22 +01:00
software/signal_processing
Initial commit
2023-10-31 07:47:27 +01:00
tests
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.gitignore
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data_channel_hw.tcl
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hardware_task_hw.tcl
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hardware_timestamp_hw.tcl
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hdl_sources.qsf
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init.sh
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Makefile
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niosII.qsys
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signal_processing.cdf
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signal_processing.qpf
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signal_processing.qsf
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Description
Studentenversion des ESY6/A Praktikums "signal_processing".
235 KiB
Languages
VHDL 38.1%
C 17%
Verilog 14.8%
Python 10.5%
Makefile 8.1%
Other 11.5%