add.vhd and crc.vhd working and finished, results true

hardware/signal_processing/add.vhd

@@ -25,12 +25,54 @@ entity add is
     );
 end entity add;
 
+-- tbd
+-- if _read is 1 _readdata is read
+-- if _write is 1 _writedata is written
+-- float_add instanziieren
+
+
+-- state machine that sets taskState and write signals
 architecture rtl of add is
+
+	component float_add
+	port (
+		clk : in std_logic;
+		reset : in std_logic;
+		start : in std_logic;
+		A : in std_logic_vector( 31 downto 0 );
+		B : in std_logic_vector( 31 downto 0 );
+		done : out std_logic;
+		sum : out std_logic_vector( 31 downto 0 )
+		);
+	end component float_add;
+
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
+	
+	signal float_add_start : std_logic;
+	signal float_add_A : std_logic_vector( 31 downto 0 );
+	signal float_add_B : std_logic_vector( 31 downto 0 );
+	signal float_add_done :  std_logic;
+	signal float_add_sum : std_logic_vector( 31 downto 0 );
+
+	signal add_state : integer range 0 to 3;
+	signal flag_index : bit;
+
 
 begin
+
+	float_adder : float_add
+	port map (
+		clk => clk,
+		reset => reset,
+		start => float_add_start,
+		A => float_add_A,		-- feed readdata into float adder
+		B => float_add_B,		-- feed readdata into float adder
+		done => float_add_done,		-- write signal when float addition is finished
+		sum => float_add_sum		-- feed output of float adder into writedata
+		);
+
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -60,18 +102,61 @@ begin
             case next_task_state is
             when work.task.TASK_IDLE =>
                 index <= 0;
-                signal_write <= '0';
-            when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
+--                signal_write <= '0';
+            when work.task.TASK_RUNNING => -- signal_writedata <= result???
+				if ( flag_index = '1' ) then
+					index <= index + 1;
+				end if;
+--                signal_write <= '1';
+--                signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
                 index <= 0;
-                signal_write <= '0';
+--                signal_write <= '0';
             end case;
         end if;
     end process sync;
 
+	add : process (clk, reset) is
+	begin
+		if ( reset = '1' ) then
+            signal_a_read <= '0';
+			signal_b_read <= '0';
+			signal_write <= '0';
+			signal_writedata <= ( others => '0');
+			float_add_start <= '0';
+			float_add_A <= ( others => '0');
+			float_add_B <= ( others => '0');
+        elsif ( rising_edge( clk ) ) then
+			case add_state is
+			when 0 =>
+				if ( current_task_state = work.task.TASK_RUNNING ) then
+					add_state <= 1;
+				end if;
+			when 1 =>
+				signal_a_read <= '1';
+				signal_b_read <= '1';
+				float_add_start <= '1';
+				float_add_A <= signal_a_readdata;
+				float_add_B <= signal_b_readdata;
+				if ( float_add_done = '1' ) then
+					add_state <= 2;
+				end if;
+			when 2 =>
+				signal_write <= '1';
+				signal_writedata <= float_add_sum;
+				float_add_start <= '0';
+				signal_a_read <= '0';
+				signal_b_read <= '0';
+				flag_index <= '1';
+				add_state <= 3;
+			when 3 =>
+				signal_write <= '0';
+				flag_index <= '0';
+				add_state <= 0;
+			end case;
+		end if;
+	end process add;
+
     task_state <= current_task_state;
 
 end architecture rtl;

hardware/signal_processing/crc.vhd

@@ -22,12 +22,21 @@ entity crc is
     );
 end entity crc;
 
+-- tbd
+-- startwert crc32 ist const, vom Algorithmus vorgegeben
+
 architecture rtl of crc is
 
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
+	signal crc_in : std_logic_vector( 31 downto 0 ) := (others => '1');
+	signal crc_out : std_logic_vector( 31 downto 0);
+	signal crc_state : integer range 0 to 2;
+	signal flag_index : bit := '0';
+
+
 begin
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
@@ -58,18 +67,141 @@ begin
             case next_task_state is
             when work.task.TASK_IDLE =>
                 index <= 0;
-                signal_write <= '0';
+                -- signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                index <= index + 1;
-                signal_write <= '1';
-                signal_writedata <= ( others => '0' );
+				if ( flag_index = '1' ) then
+					index <= index + 1;
+				end if;
+                -- signal_write <= '1';
+                -- signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
                 index <= 0;
-                signal_write <= '0';
+                -- signal_write <= '0';
             end case;
         end if;
     end process sync;
 
+	crc_calc :process ( clk, reset ) is
+	begin
+        if ( reset = '1' ) then
+        	signal_read <= '0';
+			signal_write <= '0';
+			signal_writedata <= (others => '0');
+			flag_index <= '0';
+        elsif ( rising_edge( clk ) ) then
+			case crc_state is
+			when 0 =>
+				signal_write <= '0';
+				flag_index <= '0';
+				if ( current_task_state = work.task.TASK_RUNNING ) then
+					signal_read <= '1';
+					crc_state <= 1;
+				end if;
+			when 1 =>
+				signal_read <= '0';
+
+-- calc crc
+-- THIS IS GENERATED VHDL CODE.
+-- https://bues.ch/h/crcgen
+-- 
+-- This code is Public Domain.
+-- Permission to use, copy, modify, and/or distribute this software for any
+-- purpose with or without fee is hereby granted.
+-- 
+-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+-- SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+-- RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
+-- NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+-- USE OR PERFORMANCE OF THIS SOFTWARE.
+
+-- CRC polynomial coefficients: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
+--                              0xEDB88320 (hex)
+-- CRC width:                   32 bits
+-- CRC shift direction:         right (little endian)
+-- Input word width:            32 bits
+
+				crc_out(0) <= crc_in(0) xor crc_in(1) xor crc_in(2) xor crc_in(3) xor crc_in(4) xor crc_in(6) xor crc_in(7) xor crc_in(8) xor crc_in(16) xor crc_in(20) xor crc_in(22) xor crc_in(23) xor crc_in(26) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(26);
+
+    			crc_out(1) <= crc_in(1) xor crc_in(2) xor crc_in(3) xor crc_in(4) xor crc_in(5) xor crc_in(7) xor crc_in(8) xor crc_in(9) xor crc_in(17) xor crc_in(21) xor crc_in(23) xor crc_in(24) xor crc_in(27) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(27);
+
+    			crc_out(2) <= crc_in(0) xor crc_in(2) xor crc_in(3) xor crc_in(4) xor crc_in(5) xor crc_in(6) xor crc_in(8) xor crc_in(9) xor crc_in(10) xor crc_in(18) xor crc_in(22) xor crc_in(24) xor crc_in(25) xor crc_in(28) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(28);
+
+    			crc_out(3) <= crc_in(1) xor crc_in(3) xor crc_in(4) xor crc_in(5) xor crc_in(6) xor crc_in(7) xor crc_in(9) xor crc_in(10) xor crc_in(11) xor crc_in(19) xor crc_in(23) xor crc_in(25) xor crc_in(26) xor crc_in(29) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(29);
+
+    			crc_out(4) <= crc_in(2) xor crc_in(4) xor crc_in(5) xor crc_in(6) xor crc_in(7) xor crc_in(8) xor crc_in(10) xor crc_in(11) xor crc_in(12) xor crc_in(20) xor crc_in(24) xor crc_in(26) xor crc_in(27) xor crc_in(30) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(20) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(30);
+
+    			crc_out(5) <= crc_in(0) xor crc_in(3) xor crc_in(5) xor crc_in(6) xor crc_in(7) xor crc_in(8) xor crc_in(9) xor crc_in(11) xor crc_in(12) xor crc_in(13) xor crc_in(21) xor crc_in(25) xor crc_in(27) xor crc_in(28) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(21) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(31);
+
+    			crc_out(6) <= crc_in(0) xor crc_in(2) xor crc_in(3) xor crc_in(9) xor crc_in(10) xor crc_in(12) xor crc_in(13) xor crc_in(14) xor crc_in(16) xor crc_in(20) xor crc_in(23) xor crc_in(28) xor crc_in(29) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(28) xor signal_readdata(29);
+
+    			crc_out(7) <= crc_in(1) xor crc_in(3) xor crc_in(4) xor crc_in(10) xor crc_in(11) xor crc_in(13) xor crc_in(14) xor crc_in(15) xor crc_in(17) xor crc_in(21) xor crc_in(24) xor crc_in(29) xor crc_in(30) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(29) xor signal_readdata(30);
+
+    			crc_out(8) <= crc_in(0) xor crc_in(2) xor crc_in(4) xor crc_in(5) xor crc_in(11) xor crc_in(12) xor crc_in(14) xor crc_in(15) xor crc_in(16) xor crc_in(18) xor crc_in(22) xor crc_in(25) xor crc_in(30) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(9) <= crc_in(0) xor crc_in(2) xor crc_in(4) xor crc_in(5) xor crc_in(7) xor crc_in(8) xor crc_in(12) xor crc_in(13) xor crc_in(15) xor crc_in(17) xor crc_in(19) xor crc_in(20) xor crc_in(22) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(31);
+
+    			crc_out(10) <= crc_in(0) xor crc_in(2) xor crc_in(4) xor crc_in(5) xor crc_in(7) xor crc_in(9) xor crc_in(13) xor crc_in(14) xor crc_in(18) xor crc_in(21) xor crc_in(22) xor crc_in(26) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(26);
+
+    			crc_out(11) <= crc_in(1) xor crc_in(3) xor crc_in(5) xor crc_in(6) xor crc_in(8) xor crc_in(10) xor crc_in(14) xor crc_in(15) xor crc_in(19) xor crc_in(22) xor crc_in(23) xor crc_in(27) xor signal_readdata(1) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(27);
+
+    			crc_out(12) <= crc_in(2) xor crc_in(4) xor crc_in(6) xor crc_in(7) xor crc_in(9) xor crc_in(11) xor crc_in(15) xor crc_in(16) xor crc_in(20) xor crc_in(23) xor crc_in(24) xor crc_in(28) xor signal_readdata(2) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28);
+
+    			crc_out(13) <= crc_in(0) xor crc_in(3) xor crc_in(5) xor crc_in(7) xor crc_in(8) xor crc_in(10) xor crc_in(12) xor crc_in(16) xor crc_in(17) xor crc_in(21) xor crc_in(24) xor crc_in(25) xor crc_in(29) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29);
+
+    			crc_out(14) <= crc_in(0) xor crc_in(1) xor crc_in(4) xor crc_in(6) xor crc_in(8) xor crc_in(9) xor crc_in(11) xor crc_in(13) xor crc_in(17) xor crc_in(18) xor crc_in(22) xor crc_in(25) xor crc_in(26) xor crc_in(30) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(30);
+
+    			crc_out(15) <= crc_in(1) xor crc_in(2) xor crc_in(5) xor crc_in(7) xor crc_in(9) xor crc_in(10) xor crc_in(12) xor crc_in(14) xor crc_in(18) xor crc_in(19) xor crc_in(23) xor crc_in(26) xor crc_in(27) xor crc_in(31) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(23) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(31);
+
+    			crc_out(16) <= crc_in(1) xor crc_in(4) xor crc_in(7) xor crc_in(10) xor crc_in(11) xor crc_in(13) xor crc_in(15) xor crc_in(16) xor crc_in(19) xor crc_in(22) xor crc_in(23) xor crc_in(24) xor crc_in(26) xor crc_in(27) xor crc_in(28) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28);
+
+    			crc_out(17) <= crc_in(2) xor crc_in(5) xor crc_in(8) xor crc_in(11) xor crc_in(12) xor crc_in(14) xor crc_in(16) xor crc_in(17) xor crc_in(20) xor crc_in(23) xor crc_in(24) xor crc_in(25) xor crc_in(27) xor crc_in(28) xor crc_in(29) xor signal_readdata(2) xor signal_readdata(5) xor signal_readdata(8) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29);
+
+    			crc_out(18) <= crc_in(0) xor crc_in(3) xor crc_in(6) xor crc_in(9) xor crc_in(12) xor crc_in(13) xor crc_in(15) xor crc_in(17) xor crc_in(18) xor crc_in(21) xor crc_in(24) xor crc_in(25) xor crc_in(26) xor crc_in(28) xor crc_in(29) xor crc_in(30) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
+
+    			crc_out(19) <= crc_in(0) xor crc_in(1) xor crc_in(4) xor crc_in(7) xor crc_in(10) xor crc_in(13) xor crc_in(14) xor crc_in(16) xor crc_in(18) xor crc_in(19) xor crc_in(22) xor crc_in(25) xor crc_in(26) xor crc_in(27) xor crc_in(29) xor crc_in(30) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(20) <= crc_in(0) xor crc_in(3) xor crc_in(4) xor crc_in(5) xor crc_in(6) xor crc_in(7) xor crc_in(11) xor crc_in(14) xor crc_in(15) xor crc_in(16) xor crc_in(17) xor crc_in(19) xor crc_in(22) xor crc_in(27) xor crc_in(28) xor crc_in(30) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(19) xor signal_readdata(22) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(21) <= crc_in(0) xor crc_in(2) xor crc_in(3) xor crc_in(5) xor crc_in(12) xor crc_in(15) xor crc_in(17) xor crc_in(18) xor crc_in(22) xor crc_in(26) xor crc_in(28) xor crc_in(29) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(12) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+
+    			crc_out(22) <= crc_in(2) xor crc_in(7) xor crc_in(8) xor crc_in(13) xor crc_in(18) xor crc_in(19) xor crc_in(20) xor crc_in(22) xor crc_in(26) xor crc_in(27) xor crc_in(29) xor crc_in(30) xor signal_readdata(2) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(13) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
+
+    			crc_out(23) <= crc_in(0) xor crc_in(3) xor crc_in(8) xor crc_in(9) xor crc_in(14) xor crc_in(19) xor crc_in(20) xor crc_in(21) xor crc_in(23) xor crc_in(27) xor crc_in(28) xor crc_in(30) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(3) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(14) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(24) <= crc_in(2) xor crc_in(3) xor crc_in(6) xor crc_in(7) xor crc_in(8) xor crc_in(9) xor crc_in(10) xor crc_in(15) xor crc_in(16) xor crc_in(21) xor crc_in(23) xor crc_in(24) xor crc_in(26) xor crc_in(28) xor crc_in(29) xor crc_in(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(8) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(15) xor signal_readdata(16) xor signal_readdata(21) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(26) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+
+    			crc_out(25) <= crc_in(1) xor crc_in(2) xor crc_in(6) xor crc_in(9) xor crc_in(10) xor crc_in(11) xor crc_in(17) xor crc_in(20) xor crc_in(23) xor crc_in(24) xor crc_in(25) xor crc_in(26) xor crc_in(27) xor crc_in(29) xor crc_in(30) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(9) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(17) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(29) xor signal_readdata(30);
+
+    			crc_out(26) <= crc_in(2) xor crc_in(3) xor crc_in(7) xor crc_in(10) xor crc_in(11) xor crc_in(12) xor crc_in(18) xor crc_in(21) xor crc_in(24) xor crc_in(25) xor crc_in(26) xor crc_in(27) xor crc_in(28) xor crc_in(30) xor crc_in(31) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(7) xor signal_readdata(10) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(18) xor signal_readdata(21) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(26) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(27) <= crc_in(0) xor crc_in(1) xor crc_in(2) xor crc_in(6) xor crc_in(7) xor crc_in(11) xor crc_in(12) xor crc_in(13) xor crc_in(16) xor crc_in(19) xor crc_in(20) xor crc_in(23) xor crc_in(25) xor crc_in(27) xor crc_in(28) xor crc_in(29) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(11) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(16) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(23) xor signal_readdata(25) xor signal_readdata(27) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(31);
+
+    			crc_out(28) <= crc_in(0) xor crc_in(4) xor crc_in(6) xor crc_in(12) xor crc_in(13) xor crc_in(14) xor crc_in(16) xor crc_in(17) xor crc_in(21) xor crc_in(22) xor crc_in(23) xor crc_in(24) xor crc_in(28) xor crc_in(29) xor crc_in(30) xor signal_readdata(0) xor signal_readdata(4) xor signal_readdata(6) xor signal_readdata(12) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(16) xor signal_readdata(17) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(28) xor signal_readdata(29) xor signal_readdata(30);
+
+    			crc_out(29) <= crc_in(0) xor crc_in(1) xor crc_in(5) xor crc_in(7) xor crc_in(13) xor crc_in(14) xor crc_in(15) xor crc_in(17) xor crc_in(18) xor crc_in(22) xor crc_in(23) xor crc_in(24) xor crc_in(25) xor crc_in(29) xor crc_in(30) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(5) xor signal_readdata(7) xor signal_readdata(13) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(17) xor signal_readdata(18) xor signal_readdata(22) xor signal_readdata(23) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(29) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(30) <= crc_in(3) xor crc_in(4) xor crc_in(7) xor crc_in(14) xor crc_in(15) xor crc_in(18) xor crc_in(19) xor crc_in(20) xor crc_in(22) xor crc_in(24) xor crc_in(25) xor crc_in(30) xor crc_in(31) xor signal_readdata(3) xor signal_readdata(4) xor signal_readdata(7) xor signal_readdata(14) xor signal_readdata(15) xor signal_readdata(18) xor signal_readdata(19) xor signal_readdata(20) xor signal_readdata(22) xor signal_readdata(24) xor signal_readdata(25) xor signal_readdata(30) xor signal_readdata(31);
+
+    			crc_out(31) <= crc_in(0) xor crc_in(1) xor crc_in(2) xor crc_in(3) xor crc_in(5) xor crc_in(6) xor crc_in(7) xor crc_in(15) xor crc_in(19) xor crc_in(21) xor crc_in(22) xor crc_in(25) xor crc_in(31) xor signal_readdata(0) xor signal_readdata(1) xor signal_readdata(2) xor signal_readdata(3) xor signal_readdata(5) xor signal_readdata(6) xor signal_readdata(7) xor signal_readdata(15) xor signal_readdata(19) xor signal_readdata(21) xor signal_readdata(22) xor signal_readdata(25) xor signal_readdata(31);
+
+			crc_state <= 2;
+			when 2 =>
+				if ( current_task_state = work.task.TASK_DONE ) then
+					signal_writedata <= not(crc_out);
+					signal_write <= '1';
+				end if;		
+				
+				flag_index <= '1';
+				crc_state <= 0;
+				-- assign new crc value
+ 				crc_in <= crc_out;
+
+			end case;
+		end if;
+	end process crc_calc;
+
     task_state <= current_task_state;
 
 end architecture rtl;