Studentenversion des ESY6/A Praktikums "signal_processing".
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hardware_timestamp_hw.tcl 3.7KB

1 year ago
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  1. # TCL File Generated by Component Editor 21.1
  2. # Thu Sep 08 23:25:06 CEST 2022
  3. # DO NOT MODIFY
  4. #
  5. # hardware_timestamp "hardware_timestamp" v1.0
  6. # Johannes Kutning 2022.09.08.23:25:06
  7. # Timestamp device used to measure software execution time
  8. #
  9. #
  10. # request TCL package from ACDS 16.1
  11. #
  12. package require -exact qsys 16.1
  13. #
  14. # module hardware_timestamp
  15. #
  16. set_module_property DESCRIPTION "Timestamp device used to measure software execution time"
  17. set_module_property NAME hardware_timestamp
  18. set_module_property VERSION 1.0
  19. set_module_property INTERNAL false
  20. set_module_property OPAQUE_ADDRESS_MAP true
  21. set_module_property GROUP signal_processing
  22. set_module_property AUTHOR "Johannes Kutning"
  23. set_module_property DISPLAY_NAME hardware_timestamp
  24. set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
  25. set_module_property EDITABLE true
  26. set_module_property REPORT_TO_TALKBACK false
  27. set_module_property ALLOW_GREYBOX_GENERATION false
  28. set_module_property REPORT_HIERARCHY false
  29. #
  30. # file sets
  31. #
  32. add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
  33. set_fileset_property QUARTUS_SYNTH TOP_LEVEL timer
  34. set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
  35. set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
  36. add_fileset_file hardware_timestamp.vhd VHDL PATH hardware/system/hardware_timestamp.vhd TOP_LEVEL_FILE
  37. #
  38. # parameters
  39. #
  40. #
  41. # display items
  42. #
  43. #
  44. # connection point clock
  45. #
  46. add_interface clock clock end
  47. set_interface_property clock clockRate 0
  48. set_interface_property clock ENABLED true
  49. set_interface_property clock EXPORT_OF ""
  50. set_interface_property clock PORT_NAME_MAP ""
  51. set_interface_property clock CMSIS_SVD_VARIABLES ""
  52. set_interface_property clock SVD_ADDRESS_GROUP ""
  53. add_interface_port clock clk clk Input 1
  54. #
  55. # connection point reset
  56. #
  57. add_interface reset reset end
  58. set_interface_property reset associatedClock clock
  59. set_interface_property reset synchronousEdges DEASSERT
  60. set_interface_property reset ENABLED true
  61. set_interface_property reset EXPORT_OF ""
  62. set_interface_property reset PORT_NAME_MAP ""
  63. set_interface_property reset CMSIS_SVD_VARIABLES ""
  64. set_interface_property reset SVD_ADDRESS_GROUP ""
  65. add_interface_port reset reset reset Input 1
  66. #
  67. # connection point ctrl
  68. #
  69. add_interface ctrl avalon end
  70. set_interface_property ctrl addressUnits WORDS
  71. set_interface_property ctrl associatedClock clock
  72. set_interface_property ctrl associatedReset reset
  73. set_interface_property ctrl bitsPerSymbol 8
  74. set_interface_property ctrl burstOnBurstBoundariesOnly false
  75. set_interface_property ctrl burstcountUnits WORDS
  76. set_interface_property ctrl explicitAddressSpan 0
  77. set_interface_property ctrl holdTime 0
  78. set_interface_property ctrl linewrapBursts false
  79. set_interface_property ctrl maximumPendingReadTransactions 0
  80. set_interface_property ctrl maximumPendingWriteTransactions 0
  81. set_interface_property ctrl readLatency 0
  82. set_interface_property ctrl readWaitTime 1
  83. set_interface_property ctrl setupTime 0
  84. set_interface_property ctrl timingUnits Cycles
  85. set_interface_property ctrl writeWaitTime 0
  86. set_interface_property ctrl ENABLED true
  87. set_interface_property ctrl EXPORT_OF ""
  88. set_interface_property ctrl PORT_NAME_MAP ""
  89. set_interface_property ctrl CMSIS_SVD_VARIABLES ""
  90. set_interface_property ctrl SVD_ADDRESS_GROUP ""
  91. add_interface_port ctrl address address Input 4
  92. add_interface_port ctrl read read Input 1
  93. add_interface_port ctrl readdata readdata Output 32
  94. add_interface_port ctrl write write Input 1
  95. add_interface_port ctrl writedata writedata Input 32
  96. set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
  97. set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
  98. set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
  99. set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0