signal_processing_vorlage/tests/hardware/ghdl.mk

#
#
#
#

# Make sure that the top level is assigned to main
$(if $(main),,\
$(error Assign top level entity name to variable "main"))

# Make sure that at least on vhdl source is assigned
$(if $(vhdl_srcs),,\
$(error Assign at least on vhdl source to variable "vhdl_srcs"))

# Append prefix -d to all generics
generics  = $(addprefix -g,$(generics))

# Add VHDL 2008 as default build standard
vhdl_flags += --std=08

vhdl_objs = $(vhdl_srcs:.vhd=.o)

assert_level := error

.PHONY: sim clean

sim: ${main}
	@../../scripts/execute_and_highlight.sh ghdl -r ${vhdl_flags} ${main} -gCHECK_RESULTS=${CHECK_RESULTS} \
		--read-wave-opt=${main}.wave \
		--assert-level=${assert_level}

gui: ${main}.ghw
	@echo "Viewing $<"
	@gtkwave $< --script=gtkwave.view

${main}.ghw: ${main} ${main}.wave
	@ghdl -r ${vhdl_flags} ${main} \
		--read-wave-opt=${main}.wave \
		--wave=$@

${main}: $(vhdl_objs)
	@echo "Elaborating ${main}"
	@ghdl -e ${vhdl_flags} ${main}

%.o: %.vhd
	@echo "Analysing $<"
	@ghdl -a ${vhdl_flags} $<

clean:
	@ghdl --clean
	@rm -rf ${main}.ghw work-obj08.cf ${vhdl_objs} ${main} ${artifacts}

help:
	@echo Use ghdl to simulate and synthesis a vhdl design.
	@echo
	@echo Build configuration variables:
	@echo 	main        main entity
	@echo 	vhdl_flags
	@echo 	generics