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zieglerhe 5efb80253b Fixed FFT Makefile Vorlage
2025-05-29 07:54:55 +02:00
hardware
Initial commit
2023-10-31 07:47:27 +01:00
software/signal_processing
Initial commit
2023-10-31 07:47:27 +01:00
tests
Fixed FFT Makefile Vorlage
2025-05-29 07:54:55 +02:00
.gitignore
Initial commit
2023-10-31 07:47:27 +01:00
data_channel_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hardware_task_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hardware_timestamp_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hdl_sources.qsf
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2023-10-31 07:47:27 +01:00
init.sh
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2023-10-31 07:47:27 +01:00
Makefile
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2023-10-31 07:47:27 +01:00
niosII.qsys
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2023-10-31 07:47:27 +01:00
signal_processing.cdf
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2023-10-31 07:47:27 +01:00
signal_processing.qpf
Initial commit
2023-10-31 07:47:27 +01:00
signal_processing.qsf
Initial commit
2023-10-31 07:47:27 +01:00
Description
Lösung des Praktikums Systementwurf
259 KiB
Languages
VHDL 36.5%
C 17.6%
Verilog 15.1%
Python 10.8%
Makefile 8.3%
Other 11.7%