New FFT.vhd Template and Fix FFT TB (expected values)

hardware/signal_processing/add.vhd

@@ -30,35 +30,7 @@ architecture rtl of add is
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
 
-    -- Zustände für die Zustandsmaschine zur Berechnung
-    type SigState is (
-	SIG_IDLE,
-	SIG_READ,
-	SIG_ADD,
-	SIG_WRITE
-    );
-    
-    signal current_sig_state : SigState;
-    signal next_sig_state : SigState;
-
-    signal signal_add_start : std_logic;
-    signal signal_add_done : std_logic;
-
-
 begin
-
-    u_float_add : entity work.float_add
-	port map(
-		clk => clk,
-		reset => reset,
-		start => signal_add_start,
-		done => signal_add_done,
-		A => signal_a_readdata,
-		B => signal_b_readdata,
-		sum => signal_writedata
-	);
-		    
-
     task_state_transitions : process ( current_task_state, task_start, index ) is
     begin
         next_task_state <= current_task_state;
@@ -68,7 +40,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN) then
+                if ( index = work.task.STREAM_LEN - 1 ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -78,75 +50,24 @@ begin
         end case;
     end process task_state_transitions;
 
-    sig_state_transitions : process (all) is
-    begin
-	next_sig_state <= current_sig_state;
-	case current_sig_state is
-		when SIG_IDLE =>
-		   if ( current_task_state = work.task.TASK_RUNNING ) then
-			next_sig_state <= SIG_READ;
-		   end if;
-		when SIG_READ =>
-			next_sig_state <= SIG_ADD;
-		when SIG_ADD =>
-		    if ( signal_add_done = '1') then
-			next_sig_state <= SIG_WRITE;
-		    end if;
-		when SIG_WRITE =>
-			next_sig_state <= SIG_IDLE;
-	end case;
-    end process sig_state_transitions;
-
-    task_sync : process ( clk, reset ) is
+    sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
-            --index <= 0;
+            index <= 0;
         elsif ( rising_edge( clk ) ) then
             current_task_state <= next_task_state;
             case next_task_state is
             when work.task.TASK_IDLE =>
-                null;
-                -- signal_write <= '0';
+                index <= 0;
+                signal_write <= '0';
             when work.task.TASK_RUNNING =>
-                null;
-                -- signal_write <= '1';
-                -- signal_writedata <= ( others => '0' );
+                index <= index + 1;
+                signal_write <= '1';
+                signal_writedata <= ( others => '0' );
             when work.task.TASK_DONE =>
-                null;
-                -- signal_write <= '0';
-            end case;
-        end if;
-    end process task_sync;
-
-    sync : process (all) is
-    begin
-	if ( reset = '1' ) then
-            current_sig_state <= SIG_IDLE;
-	    index <= 0;
-	    signal_a_read <= '0';
-	    signal_b_read <= '0';
-	    signal_add_start <= '0';
-	    signal_write <= '0';
-        elsif ( rising_edge( clk ) ) then
-            current_sig_state <= next_sig_state;
-            signal_write <= '0';
-	    signal_a_read <= '0';
-	    signal_b_read <= '0';
-            case next_sig_state is
-		    when SIG_IDLE =>
-		        if (index = 0) then
-			   current_sig_state <= SIG_ADD;
-			end if;
-		    when SIG_READ =>
-		        signal_a_read <= '1';
-			signal_b_read <= '1';
-		    when SIG_ADD =>
-		        signal_add_start <= '1';
-		    when SIG_WRITE =>
-			signal_add_start <= '0';
-			signal_write <= '1';
-			index <= index + 1;	
+                index <= 0;
+                signal_write <= '0';
             end case;
         end if;
     end process sync;

hardware/signal_processing/fft.vhd

@@ -1,13 +1,26 @@
 ------------------------------------------------------------------------
 -- fft
 --
--- calculation of FFT magnitude
+-- calculation of FFT magnitudes
 --
 -- Inputs:
 -- 32-Bit Floating Point number in range +-16 expected (loaded from FIFO)
 --
 -- Outputs
 -- 32-Bit Floating Point number in range +-16 calculated (stored in FIFO)
+-- 
+--
+-- Zahlen aus dem Eingangs-FIFO liegen in 32-Bit Floating Point mit Wertebereich +-16 vor 
+-- Diese Zahlen müssen in Floating Point auf den Wertebereich +-1 gebracht werden (In Floating Point können Sie durch :16 teilen, wenn Sie den Exponenten der Floating Point Zahl um -4 verkleinern, falls dieser ungleich Null ist) 
+-- Die auf den Wertebereich +-1 gebrachten Floating Point Zahlen mit to_fixed auf eine Fixpointzahl wandeln 
+-- Diese Fixpointzahl kann dem FFT IP-Core (fftmain) als Eingangswert übergeben werden (Realteil = skalierte auf Fixpoint gewandelte Zahlen; Imaginärteil=0) 
+-- Die vom FFT IP-Core berechneten werden (Realteil und Imaginärteil) können direkt dem IP-Core für die FFT Magnitude Berechnung (fft_magnitude_calc) übergeben werden (dieser arbeitet auch in Fixpoint im gleichen Wertebereich) 
+-- Das Ergebnis des FFT Magnitude Berechnung IP-Cores (fft_magnitude_calc) dann auf Floating Point wandeln (to_float) 
+-- Diese Floating Point Zahlen dann wieder skalieren mit *16 bzw. *32 für den DC-Anteil um auf den ursprünglichen Wertebereich mit +-16 zu kommen (aus dem FFT IP-Core kommt der DC-Anteil / Index 0 um den Faktor 2 zu klein, deswegen dort *32). 
+-- (In Floating Point können Sie *16 machen, wenn Sie den Exponenten der Floating Point Zahl um +4 vergrößern, *32 wenn dieser um +5 vergrößert wird, falls der Exponent ungleich Null ist) 
+-- Die Ergebnisse liegen noch in der bit-reveserd order vor (FFT IP-Core arbeitet nicht in-place) und müssen deswegen noch auf die natural order gebracht werden (https://de.mathworks.com/help/dsp/ug/linear-and-bit-reversed-output-order.html) 
+-- (z.B: ein Array verwenden, um die Werte zu sortieren)
+-- Dann das Ergebnis in den Ausgangsfifo speichern 
 --
 -----------------------------------------------------------------------
 library ieee;
@@ -19,14 +32,13 @@ library work;
     use work.task.all;
 	 use work.float.all;
 
-
 entity fft is
   generic (
 
-    -- input data width of real/img part
+    -- input data width of real/img part 
       input_data_width : integer := 32;
 
-    -- output data width of real/img part
+    -- output data width of real/img part 
       output_data_width : integer := 32
 
     );
@@ -36,112 +48,114 @@ entity fft is
 
         task_start : in std_logic;
         task_state : out work.task.State;
-
+	  
         signal_read : out std_logic;
         signal_readdata : in std_logic_vector( 31 downto 0 );
-
+		  
         signal_write : out std_logic;
         signal_writedata : out std_logic_vector( 31 downto 0 )
     );
 end entity fft;
 
-
 architecture rtl of fft is
 
+
+-- Signale für Task State Machine
     signal current_task_state : work.task.State;
     signal next_task_state : work.task.State;
     signal index : integer range 0 to work.task.STREAM_LEN;
+    --signal index : integer range 0 to 2000;
 
-    component fftmain is
-           -- generic( width : integer := 32
-            --);
-            port(
-                    clock: in std_logic;
-                    reset: in std_logic;
-                    di_en: in std_logic;
-                    di_re: in std_logic_vector(input_data_width-1 downto 0);
-                    di_im: in std_logic_vector(input_data_width-1 downto 0);
-                    do_en: out std_logic;
-                    do_re: out std_logic_vector(output_data_width-1 downto 0);
-                    do_im: out std_logic_vector(output_data_width-1 downto 0)
-                );
-    end component;
+-- component des Verilog IP-Cores fuer die FFT
+component fftmain is
+	port(
+		clock: in std_logic; -- Master Clock
+		reset: in std_logic; -- Active High Asynchronous Reset
+		di_en: in std_logic; --  Input Data Enable
+		di_re: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Real)
+                di_im: in std_logic_vector(input_data_width-1 downto 0); -- Input Data (Imag)
+		do_en: out std_logic; -- Output Data Enable
+		do_re: out std_logic_vector(output_data_width-1 downto 0); -- Output Data (Real)
+                do_im: out std_logic_vector(output_data_width-1 downto 0) -- Output Data (Imag)
+	);
+end component;
 
-    -- Zustände für die Zustandsmaschine zur Berechnung
-    type SigState is (
-	SIG_IDLE,
-	SIG_READ,
-	SIG_FFTMAIN,
-	SIG_FFTMAG,
-	SIG_WRITE
-    );
-    signal current_sig_state : SigState;
-    signal next_sig_state : SigState;
+--  Signale Input skaliert
+    signal fft_float_input : signed( 31 downto 0 ); 
+    signal fft_float_scaled_input : signed( 31 downto 0 ); 
 
-    signal fftmain_start : std_logic;
-    signal fftmain_done : std_logic;
-    signal fftmag_start : std_logic;
-    signal fftmag_done : std_logic;
-    signal fftmain_out_re : std_logic_vector( 31 downto 0 );
-    signal fftmain_out_im : std_logic_vector( 31 downto 0 );
-    
-    signal exp : std_logic_vector( 7 downto 0);
-    signal scaled_exp : std_logic_vector( 7 downto 0);
-    signal scaled_readdata : std_logic_vector( 31 downto 0);
-    signal exp_int : integer;
-    signal scaled_data_fixp : std_logic_vector(31 downto 0);
+-- Signale fuer FFT-IP Core
+    -- fft data input signal
+    signal fft_input_data_enable: std_logic;
+    signal data_in_re : std_logic_vector (input_data_width-1 downto 0);
+    signal data_in_im : std_logic_vector (input_data_width-1 downto 0);
+    -- fft output data
+    signal fft_output_valid : std_logic;
+    signal data_out_re : std_logic_vector (output_data_width-1 downto 0);
+    signal data_out_im : std_logic_vector (output_data_width-1 downto 0);
 
-    signal exp2 : std_logic_vector( 7 downto 0);
-    signal scaled_exp2 : std_logic_vector( 7 downto 0);
-    signal exp_int2 : integer;
-
-    signal magnitude_output : std_logic_vector( 31 downto 0 );
-    signal writedata_float : std_logic_vector( 31 downto 0 );
-
-    type std_logic_vector_array is array (0 to 1023) of std_logic_vector(31 downto 0);
-    signal my_array : std_logic_vector_array;
+-- Signale fuer Magnitude IP-Core
+    signal fft_mag_calc_valid : std_logic;	
+    signal fft_mag_calc_result: std_logic_vector (output_data_width-1 downto 0);
 
+-- Signale fuer Ergebnis skaliert
+    signal data_out_mag_signed_float : signed (output_data_width-1 downto 0);	
+    signal fft_float_scaled : signed( 31 downto 0 ); 
+	 
+-- Signale/Array um Ergebnisse der FFT in der natural order zu speichern
+	
+    signal data_memory : work.reg32.RegArray( 0 to 1023 );
+    signal index_reversed : std_logic_vector(9 downto 0);
+    signal index_output_sv : std_logic_vector(9 downto 0);
+    signal index_output : integer range 0 to 1023;
 
+-- Signal um in den Write FIFO zu schreiben
+    signal wr_fifo : std_logic;	 
+	  
 begin
-
-	exp <= signal_readdata( 30 downto 23 );
-	exp_int <= to_integer(unsigned(exp));
-        scaled_exp <= std_logic_vector(to_unsigned(exp_int - 4, 8));
-	scaled_readdata <= signal_readdata( 31 ) & scaled_exp & signal_readdata( 22 downto 0 ); 
-	scaled_data_fixp <= to_fixed(scaled_readdata);
-
-	writedata_float <= to_float(magnitude_output);
-        exp2 <= writedata_float( 30 downto 23 );
-	exp_int2 <= to_integer(unsigned(exp2));
-        scaled_exp2 <= std_logic_vector(to_unsigned(exp_int2 + 5, 8));
-        my_array(1023 - index) <= writedata_float( 31 ) & scaled_exp2 & writedata_float( 22 downto 0 );
-	signal_writedata <= my_array(index);
     
-    u_fft : fftmain
-    port map (
-	clock => clk,
-	reset => reset,
-	di_en => fftmain_start,
-	di_re => scaled_data_fixp,
-	di_im => x"00000000",
-	do_en => fftmain_done,
-	do_re => fftmain_out_re,
-	do_im => fftmain_out_im
-	);
+    -----------------------------------------------------------------------------------------------
+    -- Hier muss der Verilog FFT IP-Core instanziert werden
+    -----------------------------------------------------------------------------------------------
 
+    --u_fft : fftmain
+    --    port map (		      
+    --        clock => , -- system clock				
+    --        reset => , -- Active High Asynchronous Reset				    
+    --	    di_en => , -- Input Data Enable
+    --	    di_re => , -- Input Data (Real)
+    --      di_im => , -- Input Data (Imag)				
+    --      do_en => , -- Output Data Enable				
+    --	    do_re => , -- Output Data (Real)
+    --      do_im =>  -- Output Data (Imag)
+    --    ); 
     
-    u_fft_mag_calc : entity work.fft_magnitude_calc
-    port map (
-	clk => clk,
-	reset => reset,
-	input_valid => fftmag_start,
-	input_re => fftmain_out_re,
-	input_im => fftmain_out_im,
-	output_valid => fftmag_done,
-	output_magnitude => magnitude_output
-	);
+    fft_output_valid <= '0';
+    data_out_re <= (others => '0');
+    data_out_im <= (others => '0');
 
-    task_state_transitions : process ( current_task_state, task_start, index ) is
+    -----------------------------------------------------------------------------------------------
+    -- Hier muss der VHDL Magnitue IP-COre instanziert werden
+    -----------------------------------------------------------------------------------------------
+			 
+    -- u_fft_mag_calc : entity work.fft_magnitude_calc
+    -- port map (
+    --  clk => , -- system clock
+    --  reset => , -- Active High Asynchronous Reset	
+    --	input_valid => , -- Input Data Valid
+    --	input_re => ,  -- Input Realteil in Fixpoint format
+    --	input_im =>  , -- Input Imaginaerteil in Fixpoint format
+    --	output_valid => , -- Output Data Valid
+    --	output_magnitude =>  -- Magnitude Output in Fixpoint format
+    --  );
+
+    fft_mag_calc_valid <= '1' when index = 0 else '0';
+    fft_mag_calc_result <= (others => '0');
+
+    -----------------------------------------------------------------------------------------------
+    -- Zustandsmaschine fuer die Taskabarbeitung (Uebergangsschaltnetz)
+    -----------------------------------------------------------------------------------------------
+    task_state_transitions : process (all) is
     begin
         next_task_state <= current_task_state;
         case current_task_state is
@@ -150,7 +164,7 @@ begin
                     next_task_state <= work.task.TASK_RUNNING;
                 end if;
             when work.task.TASK_RUNNING =>
-                if ( index = work.task.STREAM_LEN - 1 ) then
+                if (  index = 2 ) then
                     next_task_state <= work.task.TASK_DONE;
                 end if;
             when work.task.TASK_DONE =>
@@ -160,73 +174,157 @@ begin
         end case;
     end process task_state_transitions;
 
-    sig_state_transitions : process (all) is
-    begin
-	next_sig_state <= current_sig_state;
-	case current_sig_state is
-		when SIG_IDLE =>
-		   if ( current_task_state = work.task.TASK_RUNNING ) then
-			next_sig_state <= SIG_READ;
-		   end if;
-		when SIG_READ =>
-			next_sig_state <= SIG_FFTMAIN;
-		when SIG_FFTMAIN =>
-		    if ( fftmain_done = '1') then
-			next_sig_state <= SIG_FFTMAG;
-		    end if;
-		when SIG_FFTMAG =>
-		    if ( fftmain_done = '0') then
-			next_sig_state <= SIG_WRITE;
-		    end if;
-		when SIG_WRITE =>
-			null;
-	end case;
-    end process sig_state_transitions;
+    -----------------------------------------------------------------------------------------------
+    -- Zustandsmaschine fuer die eigentliche Ablaufsteuerung fuer die FFT (Uebergangsschaltnetz)
+    -----------------------------------------------------------------------------------------------
 
-    sync : process ( clk, reset ) is
+    -- Hier soll Ihre Ablaufsteuerung fuer die FFT stehen
+
+
+    -----------------------------------------------------------------------------------------------
+    -- Ausgangsschaltnetz/Zustandsspeicher fuer die Task und FFT Zustandsmaschine
+    -----------------------------------------------------------------------------------------------
+   sync : process ( clk, reset ) is
     begin
         if ( reset = '1' ) then
             current_task_state <= work.task.TASK_IDLE;
-	    current_sig_state <= SIG_IDLE;
-	    index <= 0;
-	    signal_read <= '0';
-	    fftmain_start <= '0';
-	    fftmag_start <= '0';
-	    signal_write <= '0';
-        
-	elsif ( rising_edge( clk ) ) then
-	    current_task_state <= next_task_state;
+            index <= 0;
+            wr_fifo <= '0';
+        elsif ( rising_edge( clk ) ) then
+            current_task_state <= next_task_state;
+            wr_fifo <= '0';
             case next_task_state is
-            when work.task.TASK_IDLE =>
-                null;
-            when work.task.TASK_RUNNING =>
-                null;
-            when work.task.TASK_DONE =>
-                null;
-            end case;
-
-	    current_sig_state <= next_sig_state;
-            case next_sig_state is
-		    when SIG_IDLE =>
-		        signal_write <= '0';
-		    when SIG_READ =>
-		        signal_read <= '1';
-		    when SIG_FFTMAIN =>
-		        fftmain_start <= '1';
-		    when SIG_FFTMAG =>
-			signal_read <= '0';
-			fftmain_start <= '0';
-		        fftmag_start <= '1';
-			signal_write <= '0';
-			index <= index + 1;
-		    when SIG_WRITE =>
-			fftmag_start <= '0';
-			signal_write <= '1';
-			
+		    when work.task.TASK_IDLE => 
+                      index <= 0;
+		    when work.task.TASK_RUNNING =>
+                      -- Nur damit das Template durchlaueft bei index=0 wird das natural order array mit Nullen gefuellt
+                      -- Bei index=1 werden die 1024 Werte in den Ausgangsfifo geschrieben (Task done bei index=2)
+		      if (  index_output = work.task.STREAM_LEN - 1 ) then
+		      	  index <= index + 1;	
+                      end if;
+                      if index = 1 then				 
+			  wr_fifo <= '1';
+		      end if; 
+		    when work.task.TASK_DONE => null;
             end case;
         end if;
-    end process sync;
+    end process sync; 
+	 
 
-    task_state <= current_task_state;
+    -----------------------------------------------------------------------------------------------
+    --
+    -- Skalierung der Eingangswerte welche vom FIFO gelesen werden
+    -- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
+    -- und im naechsten Takt schon weiter verarbeitet werden können
+    --
+    -- Erforderliches Scaling:
+    --
+    -- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
+    -- multiplication is a simple addition of the exponents.
+    -- In the following calculation the inputs are scaled from FP in range +-16 to FP in range +-1
+    -- This means an divsion through 16 -> exponent needs an addition of - 4
+    --
+    -- fft_float_input = gelesener Wert vom FIFO (floating point)
+    -- fft_float_scaled_input = soll skalierter Wert vom FIFO seien (floating point)
+    -- (Anm. Der FFT IP-Core braucht als Format Fix-Point -> noch eine weitere Wandlung erforderlich)
+    -----------------------------------------------------------------------------------------------
+
+    fft_float_input <= signed(signal_readdata);
+
+    fft_float_scaled_input <= fft_float_input; -- Der Eingang muss noch entsprechend skaliert werden 
+				
+
+    -----------------------------------------------------------------------------------------------
+    --
+    -- Skalierung der Eingangswerte welche vom FIFO gelesen werden
+    -- Dies soll außerhalb eines Prozesses geschehen damit die gelesenen Werte direkt skaliert werden
+    -- und im naechsten Takt schon weiter verarbeitet werden können
+    --
+    -- Erforderliches Scaling:
+    --
+    -- By selecting the amplitude as a power of two (e.g. 2 ** 2) the
+    -- multiplication is a simple addition of the exponents.
+    -- In the following calculation the inputs are scaled from FP in range +-1 to FP in range +-16 
+    -- the first frequency bin (DC-bin) needs a multiplication by two compared to the other frequency bins (the used fft ip-core divides the result of the first frequency bin by N instead of the correct N/2)
+    -- This means an divsion through 16 is required for the first frequency bin (DC Part) -> exponent needs an addition of +4
+    -- This means an divsion through 32 is required for the first frequency bin (DC Part) -> exponent needs an addition of +5
+    --
+    -- data_out_mag_signed_float = in float gewandelter Wert der Magnitude Berechnung
+    -- fft_float_scaled = soll der skalierte float Wert der Magnitude seien
+    -----------------------------------------------------------------------------------------------
+
+    data_out_mag_signed_float <= signed(to_float(fft_mag_calc_result));
+
+    fft_float_scaled <= data_out_mag_signed_float; -- Der Ausgang muss noch entsprechend skaliert werden
+
+
+    -----------------------------------------------------------------------------------------------
+    -- Der FFT-IP Core liefert das Ergebnis nicht in der natuerlichen Reihenfolge deswegen muss eine
+	-- Umordnung der Ausgangswerte erfolgen
+	-- 
+	-- index_output_sv = std_logic_vector des Integer Ausgangsindex
+	-- index_reversed = der reversed Ausgangsindex (wird benoetigt fuer damit man die FFT Ergebnisse in die natuerliche Ordnung bringt
+	--
+    c_index_output_sv:
+            index_output_sv <= std_logic_vector(to_unsigned(index_output, index_reversed'length));
+    c_reversed_index:
+            index_reversed <= index_output_sv(0) & index_output_sv(1) & index_output_sv(2) & index_output_sv(3) & index_output_sv(4) & index_output_sv(5) & index_output_sv(6) & index_output_sv(7) & index_output_sv(8) & index_output_sv(9);
+	
+	   
+    -----------------------------------------------------------------------------------------------
+    -- Prozess steuert das hochzaehlen des Ausgang Index
+    -----------------------------------------------------------------------------------------------
+	p_number_output_sample: process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            index_output <= 0; 
+        elsif ( rising_edge( clk ) ) then
+            -- Ruecksetz Bedingung für index_output
+            if index_output = 1023 then -- in diese IF-Bedingung ggf. noch den IDLE Zustand Ihrer FFT FSM einbringen
+		index_output <= 0;
+            -- index_output hochzaehlen um in natural order im array zu speichern
+	    elsif fft_mag_calc_valid = '1' then
+		index_output <= index_output + 1;
+            -- index_output hochzaehlen um Werte im Ausgangsfifo zu speichern
+	    elsif wr_fifo = '1' then
+		index_output <= index_output + 1;
+	    end if;
+        end if;
+    end process p_number_output_sample;
+	
+    -----------------------------------------------------------------------------------------------
+    -- Prozess speichert das skalierte Endergbenis iun der natural order
+    -----------------------------------------------------------------------------------------------
+    p_output2float_memory: process ( clk, reset) is
+    begin
+        if ( reset = '1' ) then
+	    null;
+        elsif ( rising_edge( clk ) ) then
+            if fft_mag_calc_valid = '1' then
+	                data_memory(to_integer(unsigned(index_reversed))) <= std_logic_vector(fft_float_scaled);
+            end if;
+        end if;
+    end process p_output2float_memory;	
+	
+    -----------------------------------------------------------------------------------------------
+    -- Schreiben der berechneten Werte in den FIFO
+    -----------------------------------------------------------------------------------------------
+   p_output_fifo: process ( clk, reset ) is
+    begin
+        if ( reset = '1' ) then
+            signal_writedata <= (others => '0');
+		  signal_write <= '0';
+        elsif ( rising_edge( clk ) ) then
+		  signal_write <= '0';		  
+            if wr_fifo = '1' then
+		  signal_writedata <= data_memory(index_output);
+	          signal_write <= '1';
+            end if;
+        end if;
+    end process p_output_fifo;	
+	
+	
+	-- Hier sollen die sonstigen benoetigten Anweisungen stehen
+    task_state <= current_task_state;	
 
 end architecture rtl;

software/signal_processing/add.c

@@ -4,23 +4,7 @@
 
 int task_add_run( void * task ) {
 
-    add_config * config = (add_config *) task;
-	
-    float_word f;
-
-    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; i++)
-    {
-	float a;
-	data_channel_read(config->sources[0], (uint32_t *) & a);
-	
-	float b;
-	data_channel_read(config->sources[1], (uint32_t *) & b);
-
-	float_word c;
-	c.value = a + b;
-	f.value = c.value;
-	data_channel_write(config->sink, c.word);	
-    }
+    // TODO
 
     return 0;
 }

software/signal_processing/fft.c

@@ -2,96 +2,11 @@
 #include "system/data_channel.h"
 #include "system/Complex.h"
 #include "system/float_word.h"
-#include <math.h>
-#include <complex.h>
-#include <stdio.h>
 
-void fft_radix4(complex float *x) {
-    int n = DATA_CHANNEL_DEPTH;
-    int stages = log(n) / log(4);  // Anzahl der FFT-Stufen
+int task_fft_run( void * task ) {
 
-    // Bit-Reversal-Rearrangement (Umordnung der Daten für FFT)
-    for (int i = 0; i < n; i++) {
-        int rev = 0, num = i;
-        for (int bit = 0; bit < stages; bit++) {
-            rev = rev * 4 + (num % 4);
-	    //printf("i: %d, rev: %d\n", i, rev);
-            num /= 4;
-        }
-        if (i < rev) {
-            complex float temp = x[i];
-            x[i] = x[rev];
-            x[rev] = temp;
-        }
-    }
+    // TODO
 
-    // Radix-4 Butterfly-Berechnung
-    for (int s = 1; s <= stages; s++) {
-        int m = pow(4, s);      // Gruppengröße (4^s)
-        int quarter_m = m / 4;  // Viertel der Gruppengröße
-        float theta = -2.0f * M_PI / m;  // Grundwinkel der Wurzeln der Einheit
-	//printf("Stage: %d, m: %d, theta: %f\n", s, m, theta);
-
-        for (int k = 0; k < n; k += m) {  // Iteration über Gruppen
-            for (int j = 0; j < quarter_m; j++) {  // Innerhalb der Gruppe
-                // Wurzeln der Einheit
-                complex float w0 = 1.0f;  // Wurzel für j = 0
-                complex float w1 = cexpf(I * theta * j);      // Wurzel für j = 1
-                complex float w2 = cexpf(I * theta * 2 * j);  // Wurzel für j = 2
-                complex float w3 = cexpf(I * theta * 3 * j);  // Wurzel für j = 3
-
-                // Lade die Werte aus der Gruppe
-                complex float t0 = x[k + j];
-                complex float t1 = x[k + j + quarter_m] * w1;
-                complex float t2 = x[k + j + 2 * quarter_m] * w2;
-                complex float t3 = x[k + j + 3 * quarter_m] * w3;
-		//printf("w1: %f + %fi, w2: %f + %fi, w3: %f + %fi\n", crealf(w1), cimagf(w1), crealf(w2), cimagf(w2), crealf(w3), cimagf(w3));
-
-		//printf("Before: t0: %f + %fi, t1: %f + %fi, t2: %f + %fi, t3: %f + %fi\n", crealf(t0), cimagf(t0), crealf(t1), cimagf(t1), crealf(t2), cimagf(t2), crealf(t3), cimagf(t3));
-                // Butterfly-Operationen
-                x[k + j] = t0 + t1 + t2 + t3;
-                x[k + j + quarter_m] = t0 - t1 + I * (t3 - t2);
-                x[k + j + 2 * quarter_m] = t0 - t2 + t1 - t3;
-                x[k + j + 3 * quarter_m] = t0 - t1 - I * (t3 - t2);
-		//printf("After: x[%d]: %f + %fi, x[%d]: %f + %fi\n", k + j, crealf(x[k + j]), cimagf(x[k + j]), k + j + quarter_m, crealf(x[k + j + quarter_m]), cimagf(x[k + j + quarter_m]));
-            }
-        }
-    }
-}
-
-
-
-int task_fft_run(void *task) {
-
-    fft_config *config = (fft_config *)task;
-    complex float x[DATA_CHANNEL_DEPTH];
-    float c[DATA_CHANNEL_DEPTH];
-    
-    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
-        float a;
-        data_channel_read(config->base.sources[0], (uint32_t *) &a);
-        x[i] = a;
-	//printf("Input x[%d] = %f + %fi\n", i, crealf(x[i]), cimagf(x[i]));
-    }
-
-    fft_radix4(x);
-
-    for (uint32_t i = 0; i < DATA_CHANNEL_DEPTH; ++i) {
-	//printf("Output complex x[%d] = %f + %fi\n", i, crealf(x[i]), cimagf(x[i]));
-	c[i] = sqrt(pow(crealf(x[i]), 2) + pow(cimagf(x[i]), 2));	// Betrag
-	if (i == 0)
-	    c[i] = c[i] * 1/DATA_CHANNEL_DEPTH;	// Sklaierung
-	else
-	   c[i] = c[i] * 2/DATA_CHANNEL_DEPTH;	// Sklaierung
-	printf("Output Magnitude skaliert c[%d] = %f\n", i, c [i]);
-
-	float_word output;
-	output.value = c[i];	
-
-        data_channel_write(config->base.sink, output.word);
-    }
-   
     return 0;
 }
 
-

tests/hardware/task_fft/Makefile

@@ -11,6 +11,8 @@ verilog_srcs = \
 vhdl_srcs = \
     ../../../hardware/system/reg32.vhd \
     ../../../hardware/system/avalon_slave.vhd \
+    ../test_utility.vhd \
+    ../test_avalon_slave.vhd \
     ../../hardware/test_data_channel.vhd \
     ../../../hardware/system/avalon_slave_transitions.vhd \
     ../../../hardware/system/task.vhd \

tests/hardware/task_fft/test_task_fft.vhd

@@ -63,7 +63,7 @@ architecture test of test_task_fft is
         variable writedata_float : float32;
         variable writedata_real : real;
         variable expected_real : real;
-        variable abs_err : real := 0.5e-1;
+        variable abs_err : real := 0.6;
         variable result : data_array( 0 to work.task.STREAM_LEN - 1 );
         variable result_fft : data_array( 0 to work.task.STREAM_LEN - 1 );
         file data_file : text;
@@ -110,11 +110,13 @@ architecture test of test_task_fft is
         std.textio.write( data_file_fft, "]" & LF );
         file_close( data_file_fft );
 
+        index := 0;
         while index < STREAM_LEN loop
             writedata_float := to_float( result( index ) );
             writedata_real := to_real( writedata_float );
             expected_real := work.fft_data.expected( index );
             assert_near( writedata_real, expected_real, abs_err );
+            index := index + 1;
         end loop;
 
         file_open( data_file_fft_bit_reversed, "fft_out_bit_reversed.py", write_mode );

tests/hardware/task_fft/vsim.wave

@@ -1 +1,2 @@
 add wave -position end  sim:/test_task_fft/dut/*
+add wave -position end  sim:/test_task_fft/dut/u_fft/*