signal_processing_vorlage/hardware/signal_processing/add.vhd

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

library work;
    use work.reg32.all;
    use work.task.all;

entity add is
    port (
        clk : in std_logic;
        reset : in std_logic;

        task_start : in std_logic;
        task_state : out work.task.State;

        signal_a_read : out std_logic;
        signal_a_readdata : in std_logic_vector( 31 downto 0 );

        signal_b_read : out std_logic;
        signal_b_readdata : in std_logic_vector( 31 downto 0 );

        signal_write : out std_logic;
        signal_writedata : out std_logic_vector( 31 downto 0 )
    );
end entity add;

architecture rtl of add is
    signal current_task_state : work.task.State;
    signal next_task_state : work.task.State;
    signal index : integer range 0 to work.task.STREAM_LEN;

    -- Zustände für die Zustandsmaschine zur Berechnung
    type SigState is (
	SIG_IDLE,
	SIG_READ,
	SIG_ADD,
	SIG_WRITE
    );
    
    signal current_sig_state : SigState;
    signal next_sig_state : SigState;

    signal signal_add_start : std_logic;
    signal signal_add_done : std_logic;


begin

    u_float_add : entity work.float_add
	port map(
		clk => clk,
		reset => reset,
		start => signal_add_start,
		done => signal_add_done,
		A => signal_a_readdata,
		B => signal_b_readdata,
		sum => signal_writedata
	);
		    

    task_state_transitions : process ( current_task_state, task_start, index ) is
    begin
        next_task_state <= current_task_state;
        case current_task_state is
            when work.task.TASK_IDLE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
            when work.task.TASK_RUNNING =>
                if ( index = work.task.STREAM_LEN) then
                    next_task_state <= work.task.TASK_DONE;
                end if;
            when work.task.TASK_DONE =>
                if ( task_start = '1' ) then
                    next_task_state <= work.task.TASK_RUNNING;
                end if;
        end case;
    end process task_state_transitions;

    sig_state_transitions : process (all) is
    begin
	next_sig_state <= current_sig_state;
	case current_sig_state is
		when SIG_IDLE =>
		   if ( current_task_state = work.task.TASK_RUNNING ) then
			next_sig_state <= SIG_READ;
		   end if;
		when SIG_READ =>
			next_sig_state <= SIG_ADD;
		when SIG_ADD =>
		    if ( signal_add_done = '1') then
			next_sig_state <= SIG_WRITE;
		    end if;
		when SIG_WRITE =>
			next_sig_state <= SIG_IDLE;
	end case;
    end process sig_state_transitions;

    task_sync : process ( clk, reset ) is
    begin
        if ( reset = '1' ) then
            current_task_state <= work.task.TASK_IDLE;
            --index <= 0;
        elsif ( rising_edge( clk ) ) then
            current_task_state <= next_task_state;
            case next_task_state is
            when work.task.TASK_IDLE =>
                null;
                -- signal_write <= '0';
            when work.task.TASK_RUNNING =>
                null;
                -- signal_write <= '1';
                -- signal_writedata <= ( others => '0' );
            when work.task.TASK_DONE =>
                null;
                -- signal_write <= '0';
            end case;
        end if;
    end process task_sync;

    sync : process (all) is
    begin
	if ( reset = '1' ) then
            current_sig_state <= SIG_IDLE;
	    index <= 0;
	    signal_a_read <= '0';
	    signal_b_read <= '0';
	    signal_add_start <= '0';
	    signal_write <= '0';
        elsif ( rising_edge( clk ) ) then
            current_sig_state <= next_sig_state;
            signal_write <= '0';
	    signal_a_read <= '0';
	    signal_b_read <= '0';
            case next_sig_state is
		    when SIG_IDLE =>
		        if (index = 0) then
			   current_sig_state <= SIG_ADD;
			end if;
		    when SIG_READ =>
		        signal_a_read <= '1';
			signal_b_read <= '1';
		    when SIG_ADD =>
		        signal_add_start <= '1';
		    when SIG_WRITE =>
			signal_add_start <= '0';
			signal_write <= '1';
			index <= index + 1;	
            end case;
        end if;
    end process sync;

    task_state <= current_task_state;

end architecture rtl;