Versuch add abgeschlossen. Funktioniert auch praktisch!
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# vsim -voptargs="+acc" -c work.test_task_add_sine_cosine -do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1; run -all" -gCHECK_RESULTS=false
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# Start time: 09:41:58 on Nov 20,2024
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# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
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# ** Warning: (vopt-10587) Some optimizations are turned off because the +acc switch is in effect. This will cause your simulation to run slowly. Please use -access/-debug to maintain needed visibility.
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# ** Note: (vopt-143) Recognized 2 FSMs in architecture body "add(rtl)".
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# ** Note: (vsim-12126) Error and warning message counts have been restored: Errors=0, Warnings=1.
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# // Questa Sim-64
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# // Version 2023.2 linux_x86_64 Apr 11 2023
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# //
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# // Copyright 1991-2023 Mentor Graphics Corporation
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# // All Rights Reserved.
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# //
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# // QuestaSim and its associated documentation contain trade
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# // secrets and commercial or financial information that are the property of
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# // Mentor Graphics Corporation and are privileged, confidential,
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# // and exempt from disclosure under the Freedom of Information Act,
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# // 5 U.S.C. Section 552. Furthermore, this information
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# // is prohibited from disclosure under the Trade Secrets Act,
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# // 18 U.S.C. Section 1905.
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# //
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# Loading std.standard
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# Loading std.textio(body)
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# Loading ieee.std_logic_1164(body)
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# Loading ieee.numeric_std(body)
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# Loading ieee.fixed_float_types
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# Loading ieee.math_real(body)
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# Loading ieee.fixed_generic_pkg(body)
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# Loading ieee.float_generic_pkg(body)
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# Loading ieee.fixed_pkg
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# Loading ieee.float_pkg
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# Loading work.reg32(body)
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# Loading work.avalon_slave
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# Loading work.test_utility(body)
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# Loading work.test_avalon_slave(body)
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# Loading work.task(body)
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# Loading work.sine_data
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# Loading work.test_hardware_task(body)
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# Loading work.test_data_channel_pkg(body)
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# Loading std.env(body)
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# Loading work.cosine_data
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# Loading work.sine_cosine_data
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# Loading work.test_task_add_sine_cosine(test)#1
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# Loading work.task_add(struct)#1
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# Loading work.hardware_task_control(rtl)#1
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# Loading work.avalon_slave_transitions(rtl)#1
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# Loading work.add(rtl)#1
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# Loading work.float_add(mixed)#1
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# Loading work.data_channel(struct)#1
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# Loading work.data_channel_control(rtl)#1
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# Loading work.avalon_slave_transitions(rtl)#2
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# Loading work.data_sink_mux(rtl)#1
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# Loading work.fifo(rtl)#1
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# Loading work.data_source_mux(rtl)#1
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# set StdArithNoWarnings 1
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# 1
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# set NumericStdNoWarnings 1
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# 1
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# run -all
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# --------------------------------------------------------------------------------
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# Starting test_task_add_sine_cosine
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# test_configure ... [ OK ]
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# test_execute ... [ OK ]
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# write_content ... [ OK ]
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# End time: 09:41:59 on Nov 20,2024, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 1
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[N
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13 CHECK_RESULTS
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8 GUI_MODE
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25 test_task_add_sine_cosine
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105 /users/ads1/brandlfl78731/linux/A_VHDL/signal_processing_vorlage/tests/hardware/task_add_sine_cosine/work
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m255
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K4
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z0
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cModel Technology
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